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-rw-r--r--arch/mips/pmc-sierra/msp71xx/Makefile1
-rw-r--r--arch/mips/pmc-sierra/msp71xx/gpio.c218
-rw-r--r--arch/mips/pmc-sierra/msp71xx/gpio_extended.c148
-rw-r--r--include/asm-mips/pmc-sierra/msp71xx/gpio.h46
4 files changed, 413 insertions, 0 deletions
diff --git a/arch/mips/pmc-sierra/msp71xx/Makefile b/arch/mips/pmc-sierra/msp71xx/Makefile
index 4bba79c1cc79..e107f79b1491 100644
--- a/arch/mips/pmc-sierra/msp71xx/Makefile
+++ b/arch/mips/pmc-sierra/msp71xx/Makefile
@@ -3,6 +3,7 @@
3# 3#
4obj-y += msp_prom.o msp_setup.o msp_irq.o \ 4obj-y += msp_prom.o msp_setup.o msp_irq.o \
5 msp_time.o msp_serial.o msp_elb.o 5 msp_time.o msp_serial.o msp_elb.o
6obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o
6obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o 7obj-$(CONFIG_PMC_MSP7120_GW) += msp_hwbutton.o
7obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o 8obj-$(CONFIG_IRQ_MSP_SLP) += msp_irq_slp.o
8obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o 9obj-$(CONFIG_IRQ_MSP_CIC) += msp_irq_cic.o
diff --git a/arch/mips/pmc-sierra/msp71xx/gpio.c b/arch/mips/pmc-sierra/msp71xx/gpio.c
new file mode 100644
index 000000000000..69848c5813e2
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/gpio.c
@@ -0,0 +1,218 @@
1/*
2 * @file /arch/mips/pmc-sierra/msp71xx/gpio.c
3 *
4 * Generic PMC MSP71xx GPIO handling. These base gpio are controlled by two
5 * types of registers. The data register sets the output level when in output
6 * mode and when in input mode will contain the value at the input. The config
7 * register sets the various modes for each gpio.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * @author Patrick Glass <patrickglass@gmail.com>
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/gpio.h>
20#include <linux/spinlock.h>
21#include <linux/io.h>
22
23#define MSP71XX_CFG_OFFSET(gpio) (4 * (gpio))
24#define CONF_MASK 0x0F
25#define MSP71XX_GPIO_INPUT 0x01
26#define MSP71XX_GPIO_OUTPUT 0x08
27
28#define MSP71XX_GPIO_BASE 0x0B8400000L
29
30#define to_msp71xx_gpio_chip(c) container_of(c, struct msp71xx_gpio_chip, chip)
31
32static spinlock_t gpio_lock;
33
34/*
35 * struct msp71xx_gpio_chip - container for gpio chip and registers
36 * @chip: chip structure for the specified gpio bank
37 * @data_reg: register for reading and writing the gpio pin value
38 * @config_reg: register to set the mode for the gpio pin bank
39 * @out_drive_reg: register to set the output drive mode for the gpio pin bank
40 */
41struct msp71xx_gpio_chip {
42 struct gpio_chip chip;
43 void __iomem *data_reg;
44 void __iomem *config_reg;
45 void __iomem *out_drive_reg;
46};
47
48/*
49 * msp71xx_gpio_get() - return the chip's gpio value
50 * @chip: chip structure which controls the specified gpio
51 * @offset: gpio whose value will be returned
52 *
53 * It will return 0 if gpio value is low and other if high.
54 */
55static int msp71xx_gpio_get(struct gpio_chip *chip, unsigned offset)
56{
57 struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
58
59 return __raw_readl(msp_chip->data_reg) & (1 << offset);
60}
61
62/*
63 * msp71xx_gpio_set() - set the output value for the gpio
64 * @chip: chip structure who controls the specified gpio
65 * @offset: gpio whose value will be assigned
66 * @value: logic level to assign to the gpio initially
67 *
68 * This will set the gpio bit specified to the desired value. It will set the
69 * gpio pin low if value is 0 otherwise it will be high.
70 */
71static void msp71xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
72{
73 struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
74 unsigned long flags;
75 u32 data;
76
77 spin_lock_irqsave(&gpio_lock, flags);
78
79 data = __raw_readl(msp_chip->data_reg);
80 if (value)
81 data |= (1 << offset);
82 else
83 data &= ~(1 << offset);
84 __raw_writel(data, msp_chip->data_reg);
85
86 spin_unlock_irqrestore(&gpio_lock, flags);
87}
88
89/*
90 * msp71xx_set_gpio_mode() - declare the mode for a gpio
91 * @chip: chip structure which controls the specified gpio
92 * @offset: gpio whose value will be assigned
93 * @mode: desired configuration for the gpio (see datasheet)
94 *
95 * It will set the gpio pin config to the @mode value passed in.
96 */
97static int msp71xx_set_gpio_mode(struct gpio_chip *chip,
98 unsigned offset, int mode)
99{
100 struct msp71xx_gpio_chip *msp_chip = to_msp71xx_gpio_chip(chip);
101 const unsigned bit_offset = MSP71XX_CFG_OFFSET(offset);
102 unsigned long flags;
103 u32 cfg;
104
105 spin_lock_irqsave(&gpio_lock, flags);
106
107 cfg = __raw_readl(msp_chip->config_reg);
108 cfg &= ~(CONF_MASK << bit_offset);
109 cfg |= (mode << bit_offset);
110 __raw_writel(cfg, msp_chip->config_reg);
111
112 spin_unlock_irqrestore(&gpio_lock, flags);
113
114 return 0;
115}
116
117/*
118 * msp71xx_direction_output() - declare the direction mode for a gpio
119 * @chip: chip structure which controls the specified gpio
120 * @offset: gpio whose value will be assigned
121 * @value: logic level to assign to the gpio initially
122 *
123 * This call will set the mode for the @gpio to output. It will set the
124 * gpio pin low if value is 0 otherwise it will be high.
125 */
126static int msp71xx_direction_output(struct gpio_chip *chip,
127 unsigned offset, int value)
128{
129 msp71xx_gpio_set(chip, offset, value);
130
131 return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_OUTPUT);
132}
133
134/*
135 * msp71xx_direction_input() - declare the direction mode for a gpio
136 * @chip: chip structure which controls the specified gpio
137 * @offset: gpio whose to which the value will be assigned
138 *
139 * This call will set the mode for the @gpio to input.
140 */
141static int msp71xx_direction_input(struct gpio_chip *chip, unsigned offset)
142{
143 return msp71xx_set_gpio_mode(chip, offset, MSP71XX_GPIO_INPUT);
144}
145
146/*
147 * msp71xx_set_output_drive() - declare the output drive for the gpio line
148 * @gpio: gpio pin whose output drive you wish to modify
149 * @value: zero for active drain 1 for open drain drive
150 *
151 * This call will set the output drive mode for the @gpio to output.
152 */
153int msp71xx_set_output_drive(unsigned gpio, int value)
154{
155 unsigned long flags;
156 u32 data;
157
158 if (gpio > 15 || gpio < 0)
159 return -EINVAL;
160
161 spin_lock_irqsave(&gpio_lock, flags);
162
163 data = __raw_readl((void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
164 if (value)
165 data |= (1 << gpio);
166 else
167 data &= ~(1 << gpio);
168 __raw_writel(data, (void __iomem *)(MSP71XX_GPIO_BASE + 0x190));
169
170 spin_unlock_irqrestore(&gpio_lock, flags);
171
172 return 0;
173}
174EXPORT_SYMBOL(msp71xx_set_output_drive);
175
176#define MSP71XX_GPIO_BANK(name, dr, cr, base_gpio, num_gpio) \
177{ \
178 .chip = { \
179 .label = name, \
180 .direction_input = msp71xx_direction_input, \
181 .direction_output = msp71xx_direction_output, \
182 .get = msp71xx_gpio_get, \
183 .set = msp71xx_gpio_set, \
184 .base = base_gpio, \
185 .ngpio = num_gpio \
186 }, \
187 .data_reg = (void __iomem *)(MSP71XX_GPIO_BASE + dr), \
188 .config_reg = (void __iomem *)(MSP71XX_GPIO_BASE + cr), \
189 .out_drive_reg = (void __iomem *)(MSP71XX_GPIO_BASE + 0x190), \
190}
191
192/*
193 * struct msp71xx_gpio_banks[] - container array of gpio banks
194 * @chip: chip structure for the specified gpio bank
195 * @data_reg: register for reading and writing the gpio pin value
196 * @config_reg: register to set the mode for the gpio pin bank
197 *
198 * This array structure defines the gpio banks for the PMC MIPS Processor.
199 * We specify the bank name, the data register, the config register, base
200 * starting gpio number, and the number of gpios exposed by the bank.
201 */
202static struct msp71xx_gpio_chip msp71xx_gpio_banks[] = {
203
204 MSP71XX_GPIO_BANK("GPIO_1_0", 0x170, 0x180, 0, 2),
205 MSP71XX_GPIO_BANK("GPIO_5_2", 0x174, 0x184, 2, 4),
206 MSP71XX_GPIO_BANK("GPIO_9_6", 0x178, 0x188, 6, 4),
207 MSP71XX_GPIO_BANK("GPIO_15_10", 0x17C, 0x18C, 10, 6),
208};
209
210void __init msp71xx_init_gpio(void)
211{
212 int i;
213
214 spin_lock_init(&gpio_lock);
215
216 for (i = 0; i < ARRAY_SIZE(msp71xx_gpio_banks); i++)
217 gpiochip_add(&msp71xx_gpio_banks[i].chip);
218}
diff --git a/arch/mips/pmc-sierra/msp71xx/gpio_extended.c b/arch/mips/pmc-sierra/msp71xx/gpio_extended.c
new file mode 100644
index 000000000000..fc6dbc6cf1c0
--- /dev/null
+++ b/arch/mips/pmc-sierra/msp71xx/gpio_extended.c
@@ -0,0 +1,148 @@
1/*
2 * @file /arch/mips/pmc-sierra/msp71xx/gpio_extended.c
3 *
4 * Generic PMC MSP71xx EXTENDED (EXD) GPIO handling. The extended gpio is
5 * a set of hardware registers that have no need for explicit locking as
6 * it is handled by unique method of writing individual set/clr bits.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * @author Patrick Glass <patrickglass@gmail.com>
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/gpio.h>
19#include <linux/io.h>
20
21#define MSP71XX_DATA_OFFSET(gpio) (2 * (gpio))
22#define MSP71XX_READ_OFFSET(gpio) (MSP71XX_DATA_OFFSET(gpio) + 1)
23#define MSP71XX_CFG_OUT_OFFSET(gpio) (MSP71XX_DATA_OFFSET(gpio) + 16)
24#define MSP71XX_CFG_IN_OFFSET(gpio) (MSP71XX_CFG_OUT_OFFSET(gpio) + 1)
25
26#define MSP71XX_EXD_GPIO_BASE 0x0BC000000L
27
28#define to_msp71xx_exd_gpio_chip(c) \
29 container_of(c, struct msp71xx_exd_gpio_chip, chip)
30
31/*
32 * struct msp71xx_exd_gpio_chip - container for gpio chip and registers
33 * @chip: chip structure for the specified gpio bank
34 * @reg: register for control and data of gpio pin
35 */
36struct msp71xx_exd_gpio_chip {
37 struct gpio_chip chip;
38 void __iomem *reg;
39};
40
41/*
42 * msp71xx_exd_gpio_get() - return the chip's gpio value
43 * @chip: chip structure which controls the specified gpio
44 * @offset: gpio whose value will be returned
45 *
46 * It will return 0 if gpio value is low and other if high.
47 */
48static int msp71xx_exd_gpio_get(struct gpio_chip *chip, unsigned offset)
49{
50 struct msp71xx_exd_gpio_chip *msp71xx_chip =
51 to_msp71xx_exd_gpio_chip(chip);
52 const unsigned bit = MSP71XX_READ_OFFSET(offset);
53
54 return __raw_readl(msp71xx_chip->reg) & (1 << bit);
55}
56
57/*
58 * msp71xx_exd_gpio_set() - set the output value for the gpio
59 * @chip: chip structure who controls the specified gpio
60 * @offset: gpio whose value will be assigned
61 * @value: logic level to assign to the gpio initially
62 *
63 * This will set the gpio bit specified to the desired value. It will set the
64 * gpio pin low if value is 0 otherwise it will be high.
65 */
66static void msp71xx_exd_gpio_set(struct gpio_chip *chip,
67 unsigned offset, int value)
68{
69 struct msp71xx_exd_gpio_chip *msp71xx_chip =
70 to_msp71xx_exd_gpio_chip(chip);
71 const unsigned bit = MSP71XX_DATA_OFFSET(offset);
72
73 __raw_writel(1 << (bit + (value ? 1 : 0)), msp71xx_chip->reg);
74}
75
76/*
77 * msp71xx_exd_direction_output() - declare the direction mode for a gpio
78 * @chip: chip structure which controls the specified gpio
79 * @offset: gpio whose value will be assigned
80 * @value: logic level to assign to the gpio initially
81 *
82 * This call will set the mode for the @gpio to output. It will set the
83 * gpio pin low if value is 0 otherwise it will be high.
84 */
85static int msp71xx_exd_direction_output(struct gpio_chip *chip,
86 unsigned offset, int value)
87{
88 struct msp71xx_exd_gpio_chip *msp71xx_chip =
89 to_msp71xx_exd_gpio_chip(chip);
90
91 msp71xx_exd_gpio_set(chip, offset, value);
92 __raw_writel(1 << MSP71XX_CFG_OUT_OFFSET(offset), msp71xx_chip->reg);
93 return 0;
94}
95
96/*
97 * msp71xx_exd_direction_input() - declare the direction mode for a gpio
98 * @chip: chip structure which controls the specified gpio
99 * @offset: gpio whose to which the value will be assigned
100 *
101 * This call will set the mode for the @gpio to input.
102 */
103static int msp71xx_exd_direction_input(struct gpio_chip *chip, unsigned offset)
104{
105 struct msp71xx_exd_gpio_chip *msp71xx_chip =
106 to_msp71xx_exd_gpio_chip(chip);
107
108 __raw_writel(1 << MSP71XX_CFG_IN_OFFSET(offset), msp71xx_chip->reg);
109 return 0;
110}
111
112#define MSP71XX_EXD_GPIO_BANK(name, exd_reg, base_gpio, num_gpio) \
113{ \
114 .chip = { \
115 .label = name, \
116 .direction_input = msp71xx_exd_direction_input, \
117 .direction_output = msp71xx_exd_direction_output, \
118 .get = msp71xx_exd_gpio_get, \
119 .set = msp71xx_exd_gpio_set, \
120 .base = base_gpio, \
121 .ngpio = num_gpio, \
122 }, \
123 .reg = (void __iomem *)(MSP71XX_EXD_GPIO_BASE + exd_reg), \
124}
125
126/*
127 * struct msp71xx_exd_gpio_banks[] - container array of gpio banks
128 * @chip: chip structure for the specified gpio bank
129 * @reg: register for reading and writing the gpio pin value
130 *
131 * This array structure defines the extended gpio banks for the
132 * PMC MIPS Processor. We specify the bank name, the data/config
133 * register,the base starting gpio number, and the number of
134 * gpios exposed by the bank of gpios.
135 */
136static struct msp71xx_exd_gpio_chip msp71xx_exd_gpio_banks[] = {
137
138 MSP71XX_EXD_GPIO_BANK("GPIO_23_16", 0x188, 16, 8),
139 MSP71XX_EXD_GPIO_BANK("GPIO_27_24", 0x18C, 24, 4),
140};
141
142void __init msp71xx_init_gpio_extended(void)
143{
144 int i;
145
146 for (i = 0; i < ARRAY_SIZE(msp71xx_exd_gpio_banks); i++)
147 gpiochip_add(&msp71xx_exd_gpio_banks[i].chip);
148}
diff --git a/include/asm-mips/pmc-sierra/msp71xx/gpio.h b/include/asm-mips/pmc-sierra/msp71xx/gpio.h
new file mode 100644
index 000000000000..ebdbab973e41
--- /dev/null
+++ b/include/asm-mips/pmc-sierra/msp71xx/gpio.h
@@ -0,0 +1,46 @@
1/*
2 * include/asm-mips/pmc-sierra/msp71xx/gpio.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * @author Patrick Glass <patrickglass@gmail.com>
9 */
10
11#ifndef __PMC_MSP71XX_GPIO_H
12#define __PMC_MSP71XX_GPIO_H
13
14/* Max number of gpio's is 28 on chip plus 3 banks of I2C IO Expanders */
15#define ARCH_NR_GPIOS (28 + (3 * 8))
16
17/* new generic GPIO API - see Documentation/gpio.txt */
18#include <asm-generic/gpio.h>
19
20#define gpio_get_value __gpio_get_value
21#define gpio_set_value __gpio_set_value
22#define gpio_cansleep __gpio_cansleep
23
24/* Setup calls for the gpio and gpio extended */
25extern void msp71xx_init_gpio(void);
26extern void msp71xx_init_gpio_extended(void);
27extern int msp71xx_set_output_drive(unsigned gpio, int value);
28
29/* Custom output drive functionss */
30static inline int gpio_set_output_drive(unsigned gpio, int value)
31{
32 return msp71xx_set_output_drive(gpio, value);
33}
34
35/* IRQ's are not supported for gpio lines */
36static inline int gpio_to_irq(unsigned gpio)
37{
38 return -EINVAL;
39}
40
41static inline int irq_to_gpio(unsigned irq)
42{
43 return -EINVAL;
44}
45
46#endif /* __PMC_MSP71XX_GPIO_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 02:12:30 -0500