6 files changed, 61 insertions, 50 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f245c588ae95..ce7914c4c044 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -262,6 +262,7 @@ enum intel_pch {
 };
 
 #define QUIRK_PIPEA_FORCE (1<<0)
+#define QUIRK_LVDS_SSC_DISABLE (1<<1)
 
 struct intel_fbdev;
 
@@ -1194,7 +1195,9 @@ void i915_gem_free_all_phys_object(struct drm_device *dev);
 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
 
 uint32_t
-i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);
+i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
+                                    uint32_t size,
+                                    int tiling_mode);
 
 /* i915_gem_gtt.c */
 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5c0d1247f453..a087e1bf0c2f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1374,25 +1374,24 @@ i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
 }
 
 static uint32_t
-i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
+i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
 {
-        struct drm_device *dev = obj->base.dev;
-        uint32_t size;
+        uint32_t gtt_size;
 
         if (INTEL_INFO(dev)->gen >= 4 ||
-            obj->tiling_mode == I915_TILING_NONE)
-                return obj->base.size;
+            tiling_mode == I915_TILING_NONE)
+                return size;
 
         /* Previous chips need a power-of-two fence region when tiling */
         if (INTEL_INFO(dev)->gen == 3)
-                size = 1024*1024;
+                gtt_size = 1024*1024;
         else
-                size = 512*1024;
+                gtt_size = 512*1024;
 
-        while (size < obj->base.size)
-                size <<= 1;
+        while (gtt_size < size)
+                gtt_size <<= 1;
 
-        return size;
+        return gtt_size;
 }
 
 /**
@@ -1403,59 +1402,52 @@ i915_gem_get_gtt_size(struct drm_i915_gem_object *obj)
  * potential fence register mapping.
  */
 static uint32_t
-i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj)
+i915_gem_get_gtt_alignment(struct drm_device *dev,
+                           uint32_t size,
+                           int tiling_mode)
 {
-        struct drm_device *dev = obj->base.dev;
-
         /*
          * Minimum alignment is 4k (GTT page size), but might be greater
          * if a fence register is needed for the object.
          */
         if (INTEL_INFO(dev)->gen >= 4 ||
-            obj->tiling_mode == I915_TILING_NONE)
+            tiling_mode == I915_TILING_NONE)
                 return 4096;
 
         /*
          * Previous chips need to be aligned to the size of the smallest
          * fence register that can contain the object.
          */
-        return i915_gem_get_gtt_size(obj);
+        return i915_gem_get_gtt_size(dev, size, tiling_mode);
 }
 
 /**
  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
  *                                       unfenced object
- * @obj: object to check
+ * @dev: the device
+ * @size: size of the object
+ * @tiling_mode: tiling mode of the object
  *
  * Return the required GTT alignment for an object, only taking into account
  * unfenced tiled surface requirements.
  */
 uint32_t
-i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
+i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
+                                    uint32_t size,
+                                    int tiling_mode)
 {
-        struct drm_device *dev = obj->base.dev;
-        int tile_height;
-
         /*
          * Minimum alignment is 4k (GTT page size) for sane hw.
          */
         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
-            obj->tiling_mode == I915_TILING_NONE)
+            tiling_mode == I915_TILING_NONE)
                 return 4096;
 
-        /*
-         * Older chips need unfenced tiled buffers to be aligned to the left
-         * edge of an even tile row (where tile rows are counted as if the bo is
-         * placed in a fenced gtt region).
+        /* Previous hardware however needs to be aligned to a power-of-two
+         * tile height. The simplest method for determining this is to reuse
+         * the power-of-tile object size.
          */
-        if (IS_GEN2(dev))
-                tile_height = 16;
-        else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
-                tile_height = 32;
-        else
-                tile_height = 8;
-
-        return tile_height * obj->stride * 2;
+        return i915_gem_get_gtt_size(dev, size, tiling_mode);
 }
 
 int
@@ -2744,9 +2736,16 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
                 return -EINVAL;
         }
 
-        fence_size = i915_gem_get_gtt_size(obj);
-        fence_alignment = i915_gem_get_gtt_alignment(obj);
-        unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj);
+        fence_size = i915_gem_get_gtt_size(dev,
+                                           obj->base.size,
+                                           obj->tiling_mode);
+        fence_alignment = i915_gem_get_gtt_alignment(dev,
+                                                     obj->base.size,
+                                                     obj->tiling_mode);
+        unfenced_alignment =
+                i915_gem_get_unfenced_gtt_alignment(dev,
+                                                    obj->base.size,
+                                                    obj->tiling_mode);
 
         if (alignment == 0)
                 alignment = map_and_fenceable ? fence_alignment :
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 82d70fd9e933..99c4faa59d8f 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -348,7 +348,9 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
                 /* Rebind if we need a change of alignment */
                 if (!obj->map_and_fenceable) {
                         u32 unfenced_alignment =
-                                i915_gem_get_unfenced_gtt_alignment(obj);
+                                i915_gem_get_unfenced_gtt_alignment(dev,
+                                                                    obj->base.size,
+                                                                    args->tiling_mode);
                         if (obj->gtt_offset & (unfenced_alignment - 1))
                                 ret = i915_gem_object_unbind(obj);
                 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 21b6f93fe919..0f1c799afea1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4305,7 +4305,8 @@ static void intel_update_watermarks(struct drm_device *dev)
 
 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
 {
-        return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
+        return dev_priv->lvds_use_ssc && i915_panel_use_ssc
+                && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
 }
 
 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
@@ -7810,6 +7811,15 @@ static void quirk_pipea_force (struct drm_device *dev)
         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
 }
 
+/*
+ * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
+ */
+static void quirk_ssc_force_disable(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
+}
+
 struct intel_quirk {
         int device;
         int subsystem_vendor;
@@ -7838,6 +7848,9 @@ struct intel_quirk intel_quirks[] = {
         /* 855 & before need to leave pipe A & dpll A up */
         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
+
+        /* Lenovo U160 cannot use SSC on LVDS */
+        { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
 };
 
 static void intel_init_quirks(struct drm_device *dev)
diff --git a/fs/dcache.c b/fs/dcache.c
index 6e4ea6d87774..fbdcbca40725 100644
--- a/fs/dcache.c
+++ b/fs/dcache.c
@@ -1813,8 +1813,6 @@ seqretry:
                 tname = dentry->d_name.name;
                 i = dentry->d_inode;
                 prefetch(tname);
-                if (i)
-                        prefetch(i);
                 /*
                  * This seqcount check is required to ensure name and
                  * len are loaded atomically, so as not to walk off the
diff --git a/fs/fscache/page.c b/fs/fscache/page.c
index 2f343b4d7a7d..3f7a59bfa7ad 100644
--- a/fs/fscache/page.c
+++ b/fs/fscache/page.c
@@ -976,16 +976,12 @@ void __fscache_uncache_all_inode_pages(struct fscache_cookie *cookie,
 
         pagevec_init(&pvec, 0);
         next = 0;
-        while (next <= (loff_t)-1 &&
-               pagevec_lookup(&pvec, mapping, next, PAGEVEC_SIZE)
-               ) {
+        do {
+                if (!pagevec_lookup(&pvec, mapping, next, PAGEVEC_SIZE))
+                        break;
                 for (i = 0; i < pagevec_count(&pvec); i++) {
                         struct page *page = pvec.pages[i];
-                        pgoff_t page_index = page->index;
-
-                        ASSERTCMP(page_index, >=, next);
-                        next = page_index + 1;
-
+                        next = page->index;
                         if (PageFsCache(page)) {
                                 __fscache_wait_on_page_write(cookie, page);
                                 __fscache_uncache_page(cookie, page);
@@ -993,7 +989,7 @@ void __fscache_uncache_all_inode_pages(struct fscache_cookie *cookie,
                 }
                 pagevec_release(&pvec);
                 cond_resched();
-        }
+        } while (++next);
 
         _leave("");
 }