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-rw-r--r--drivers/net/wireless/iwlwifi/iwl-csr.h6
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom.c8
2 files changed, 12 insertions, 2 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h
index 401e1e01be67..b6ed5a3147a1 100644
--- a/drivers/net/wireless/iwlwifi/iwl-csr.h
+++ b/drivers/net/wireless/iwlwifi/iwl-csr.h
@@ -109,8 +109,9 @@
109 * Bit fields: 109 * Bit fields:
110 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 110 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
111 */ 111 */
112#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 112#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
113#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) 113#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
114#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
114 115
115/* Bits for CSR_HW_IF_CONFIG_REG */ 116/* Bits for CSR_HW_IF_CONFIG_REG */
116#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010) 117#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010)
@@ -195,6 +196,7 @@
195#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 196#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
196#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 197#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
197#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 198#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
199#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
198 200
199/* GP (general purpose) CONTROL */ 201/* GP (general purpose) CONTROL */
200#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 202#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
index 2e8c40576d22..9429cb1c69bd 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
@@ -358,6 +358,14 @@ static int iwl_init_otp_access(struct iwl_priv *priv)
358 udelay(5); 358 udelay(5);
359 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, 359 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
360 APMG_PS_CTRL_VAL_RESET_REQ); 360 APMG_PS_CTRL_VAL_RESET_REQ);
361
362 /*
363 * CSR auto clock gate disable bit -
364 * this is only applicable for HW with OTP shadow RAM
365 */
366 if (priv->cfg->shadow_ram_support)
367 iwl_set_bit(priv, CSR_DBG_LINK_PWR_MGMT_REG,
368 CSR_RESET_LINK_PWR_MGMT_DISABLED);
361 } 369 }
362 return ret; 370 return ret;
363} 371}