diff options
-rw-r--r-- | include/asm-sparc64/spitfire.h | 130 |
1 files changed, 0 insertions, 130 deletions
diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h index 1aa932773af8..962638c9d122 100644 --- a/include/asm-sparc64/spitfire.h +++ b/include/asm-sparc64/spitfire.h | |||
@@ -56,52 +56,6 @@ extern void cheetah_enable_pcache(void); | |||
56 | SPITFIRE_HIGHEST_LOCKED_TLBENT : \ | 56 | SPITFIRE_HIGHEST_LOCKED_TLBENT : \ |
57 | CHEETAH_HIGHEST_LOCKED_TLBENT) | 57 | CHEETAH_HIGHEST_LOCKED_TLBENT) |
58 | 58 | ||
59 | static __inline__ unsigned long spitfire_get_isfsr(void) | ||
60 | { | ||
61 | unsigned long ret; | ||
62 | |||
63 | __asm__ __volatile__("ldxa [%1] %2, %0" | ||
64 | : "=r" (ret) | ||
65 | : "r" (TLB_SFSR), "i" (ASI_IMMU)); | ||
66 | return ret; | ||
67 | } | ||
68 | |||
69 | static __inline__ unsigned long spitfire_get_dsfsr(void) | ||
70 | { | ||
71 | unsigned long ret; | ||
72 | |||
73 | __asm__ __volatile__("ldxa [%1] %2, %0" | ||
74 | : "=r" (ret) | ||
75 | : "r" (TLB_SFSR), "i" (ASI_DMMU)); | ||
76 | return ret; | ||
77 | } | ||
78 | |||
79 | static __inline__ unsigned long spitfire_get_sfar(void) | ||
80 | { | ||
81 | unsigned long ret; | ||
82 | |||
83 | __asm__ __volatile__("ldxa [%1] %2, %0" | ||
84 | : "=r" (ret) | ||
85 | : "r" (DMMU_SFAR), "i" (ASI_DMMU)); | ||
86 | return ret; | ||
87 | } | ||
88 | |||
89 | static __inline__ void spitfire_put_isfsr(unsigned long sfsr) | ||
90 | { | ||
91 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | ||
92 | "membar #Sync" | ||
93 | : /* no outputs */ | ||
94 | : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_IMMU)); | ||
95 | } | ||
96 | |||
97 | static __inline__ void spitfire_put_dsfsr(unsigned long sfsr) | ||
98 | { | ||
99 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | ||
100 | "membar #Sync" | ||
101 | : /* no outputs */ | ||
102 | : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_DMMU)); | ||
103 | } | ||
104 | |||
105 | /* The data cache is write through, so this just invalidates the | 59 | /* The data cache is write through, so this just invalidates the |
106 | * specified line. | 60 | * specified line. |
107 | */ | 61 | */ |
@@ -193,90 +147,6 @@ static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data) | |||
193 | "i" (ASI_ITLB_DATA_ACCESS)); | 147 | "i" (ASI_ITLB_DATA_ACCESS)); |
194 | } | 148 | } |
195 | 149 | ||
196 | /* Spitfire hardware assisted TLB flushes. */ | ||
197 | |||
198 | /* Context level flushes. */ | ||
199 | static __inline__ void spitfire_flush_dtlb_primary_context(void) | ||
200 | { | ||
201 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | ||
202 | "membar #Sync" | ||
203 | : /* No outputs */ | ||
204 | : "r" (0x40), "i" (ASI_DMMU_DEMAP)); | ||
205 | } | ||
206 | |||
207 | static __inline__ void spitfire_flush_itlb_primary_context(void) | ||
208 | { | ||
209 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | ||
210 | "membar #Sync" | ||
211 | : /* No outputs */ | ||
212 | : "r" (0x40), "i" (ASI_IMMU_DEMAP)); | ||
213 | } | ||
214 | |||
215 | static __inline__ void spitfire_flush_dtlb_secondary_context(void) | ||
216 | { | ||
217 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | ||
218 | "membar #Sync" | ||
219 | : /* No outputs */ | ||
220 | : "r" (0x50), "i" (ASI_DMMU_DEMAP)); | ||
221 | } | ||
222 | |||
223 | static __inline__ void spitfire_flush_itlb_secondary_context(void) | ||
224 | { | ||
225 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | ||
226 | "membar #Sync" | ||
227 | : /* No outputs */ | ||
228 | : "r" (0x50), "i" (ASI_IMMU_DEMAP)); | ||
229 | } | ||
230 | |||
231 | static __inline__ void spitfire_flush_dtlb_nucleus_context(void) | ||
232 | { | ||
233 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | ||
234 | "membar #Sync" | ||
235 | : /* No outputs */ | ||
236 | : "r" (0x60), "i" (ASI_DMMU_DEMAP)); | ||
237 | } | ||
238 | |||
239 | static __inline__ void spitfire_flush_itlb_nucleus_context(void) | ||
240 | { | ||
241 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | ||
242 | "membar #Sync" | ||
243 | : /* No outputs */ | ||
244 | : "r" (0x60), "i" (ASI_IMMU_DEMAP)); | ||
245 | } | ||
246 | |||
247 | /* Page level flushes. */ | ||
248 | static __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page) | ||
249 | { | ||
250 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | ||
251 | "membar #Sync" | ||
252 | : /* No outputs */ | ||
253 | : "r" (page), "i" (ASI_DMMU_DEMAP)); | ||
254 | } | ||
255 | |||
256 | static __inline__ void spitfire_flush_itlb_primary_page(unsigned long page) | ||
257 | { | ||
258 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | ||
259 | "membar #Sync" | ||
260 | : /* No outputs */ | ||
261 | : "r" (page), "i" (ASI_IMMU_DEMAP)); | ||
262 | } | ||
263 | |||
264 | static __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page) | ||
265 | { | ||
266 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | ||
267 | "membar #Sync" | ||
268 | : /* No outputs */ | ||
269 | : "r" (page | 0x10), "i" (ASI_DMMU_DEMAP)); | ||
270 | } | ||
271 | |||
272 | static __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page) | ||
273 | { | ||
274 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | ||
275 | "membar #Sync" | ||
276 | : /* No outputs */ | ||
277 | : "r" (page | 0x10), "i" (ASI_IMMU_DEMAP)); | ||
278 | } | ||
279 | |||
280 | static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) | 150 | static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) |
281 | { | 151 | { |
282 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | 152 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" |