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-rw-r--r--drivers/ide/Kconfig8
-rw-r--r--drivers/ide/Makefile1
-rw-r--r--drivers/ide/ppc/scc_pata.c812
3 files changed, 821 insertions, 0 deletions
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index ec03341d2bd8..350764ece7fe 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -797,6 +797,14 @@ config BLK_DEV_IDEDMA_PMAC
797 to transfer data to and from memory. Saying Y is safe and improves 797 to transfer data to and from memory. Saying Y is safe and improves
798 performance. 798 performance.
799 799
800config BLK_DEV_IDE_CELLEB
801 bool "Toshiba's Cell Reference Set IDE support"
802 depends on PPC_CELLEB
803 help
804 This driver provides support for the built-in IDE controller on
805 Toshiba Cell Reference Board.
806 If unsure, say Y.
807
800config BLK_DEV_IDE_SWARM 808config BLK_DEV_IDE_SWARM
801 tristate "IDE for Sibyte evaluation boards" 809 tristate "IDE for Sibyte evaluation boards"
802 depends on SIBYTE_SB1xxx_SOC 810 depends on SIBYTE_SB1xxx_SOC
diff --git a/drivers/ide/Makefile b/drivers/ide/Makefile
index d9f029e8ff74..28feedfbd21d 100644
--- a/drivers/ide/Makefile
+++ b/drivers/ide/Makefile
@@ -37,6 +37,7 @@ ide-core-$(CONFIG_BLK_DEV_Q40IDE) += legacy/q40ide.o
37# built-in only drivers from ppc/ 37# built-in only drivers from ppc/
38ide-core-$(CONFIG_BLK_DEV_MPC8xx_IDE) += ppc/mpc8xx.o 38ide-core-$(CONFIG_BLK_DEV_MPC8xx_IDE) += ppc/mpc8xx.o
39ide-core-$(CONFIG_BLK_DEV_IDE_PMAC) += ppc/pmac.o 39ide-core-$(CONFIG_BLK_DEV_IDE_PMAC) += ppc/pmac.o
40ide-core-$(CONFIG_BLK_DEV_IDE_CELLEB) += ppc/scc_pata.o
40 41
41# built-in only drivers from h8300/ 42# built-in only drivers from h8300/
42ide-core-$(CONFIG_H8300) += h8300/ide-h8300.o 43ide-core-$(CONFIG_H8300) += h8300/ide-h8300.o
diff --git a/drivers/ide/ppc/scc_pata.c b/drivers/ide/ppc/scc_pata.c
new file mode 100644
index 000000000000..3993d08312dc
--- /dev/null
+++ b/drivers/ide/ppc/scc_pata.c
@@ -0,0 +1,812 @@
1/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat <alan@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/delay.h>
29#include <linux/hdreg.h>
30#include <linux/ide.h>
31#include <linux/init.h>
32
33#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
34
35#define SCC_PATA_NAME "scc IDE"
36
37#define TDVHSEL_MASTER 0x00000001
38#define TDVHSEL_SLAVE 0x00000004
39
40#define MODE_JCUSFEN 0x00000080
41
42#define CCKCTRL_ATARESET 0x00040000
43#define CCKCTRL_BUFCNT 0x00020000
44#define CCKCTRL_CRST 0x00010000
45#define CCKCTRL_OCLKEN 0x00000100
46#define CCKCTRL_ATACLKOEN 0x00000002
47#define CCKCTRL_LCLKEN 0x00000001
48
49#define QCHCD_IOS_SS 0x00000001
50
51#define QCHSD_STPDIAG 0x00020000
52
53#define INTMASK_MSK 0xD1000012
54#define INTSTS_SERROR 0x80000000
55#define INTSTS_PRERR 0x40000000
56#define INTSTS_RERR 0x10000000
57#define INTSTS_ICERR 0x01000000
58#define INTSTS_BMSINT 0x00000010
59#define INTSTS_BMHE 0x00000008
60#define INTSTS_IOIRQS 0x00000004
61#define INTSTS_INTRQ 0x00000002
62#define INTSTS_ACTEINT 0x00000001
63
64#define ECMODE_VALUE 0x01
65
66static struct scc_ports {
67 unsigned long ctl, dma;
68 unsigned char hwif_id; /* for removing hwif from system */
69} scc_ports[MAX_HWIFS];
70
71/* PIO transfer mode table */
72/* JCHST */
73static unsigned long JCHSTtbl[2][7] = {
74 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
75 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
76};
77
78/* JCHHT */
79static unsigned long JCHHTtbl[2][7] = {
80 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
81 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
82};
83
84/* JCHCT */
85static unsigned long JCHCTtbl[2][7] = {
86 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
87 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
88};
89
90
91/* DMA transfer mode table */
92/* JCHDCTM/JCHDCTS */
93static unsigned long JCHDCTxtbl[2][7] = {
94 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
95 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
96};
97
98/* JCSTWTM/JCSTWTS */
99static unsigned long JCSTWTxtbl[2][7] = {
100 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
101 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
102};
103
104/* JCTSS */
105static unsigned long JCTSStbl[2][7] = {
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
107 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
108};
109
110/* JCENVT */
111static unsigned long JCENVTtbl[2][7] = {
112 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
113 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
114};
115
116/* JCACTSELS/JCACTSELM */
117static unsigned long JCACTSELtbl[2][7] = {
118 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
119 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
120};
121
122
123static u8 scc_ide_inb(unsigned long port)
124{
125 u32 data = in_be32((void*)port);
126 return (u8)data;
127}
128
129static u16 scc_ide_inw(unsigned long port)
130{
131 u32 data = in_be32((void*)port);
132 return (u16)data;
133}
134
135static u32 scc_ide_inl(unsigned long port)
136{
137 u32 data = in_be32((void*)port);
138 return data;
139}
140
141static void scc_ide_insw(unsigned long port, void *addr, u32 count)
142{
143 u16 *ptr = (u16 *)addr;
144 while (count--) {
145 *ptr++ = le16_to_cpu(in_be32((void*)port));
146 }
147}
148
149static void scc_ide_insl(unsigned long port, void *addr, u32 count)
150{
151 u16 *ptr = (u16 *)addr;
152 while (count--) {
153 *ptr++ = le16_to_cpu(in_be32((void*)port));
154 *ptr++ = le16_to_cpu(in_be32((void*)port));
155 }
156}
157
158static void scc_ide_outb(u8 addr, unsigned long port)
159{
160 out_be32((void*)port, addr);
161}
162
163static void scc_ide_outw(u16 addr, unsigned long port)
164{
165 out_be32((void*)port, addr);
166}
167
168static void scc_ide_outl(u32 addr, unsigned long port)
169{
170 out_be32((void*)port, addr);
171}
172
173static void
174scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
175{
176 ide_hwif_t *hwif = HWIF(drive);
177
178 out_be32((void*)port, addr);
179 __asm__ __volatile__("eieio":::"memory");
180 in_be32((void*)(hwif->dma_base + 0x01c));
181 __asm__ __volatile__("eieio":::"memory");
182}
183
184static void
185scc_ide_outsw(unsigned long port, void *addr, u32 count)
186{
187 u16 *ptr = (u16 *)addr;
188 while (count--) {
189 out_be32((void*)port, cpu_to_le16(*ptr++));
190 }
191}
192
193static void
194scc_ide_outsl(unsigned long port, void *addr, u32 count)
195{
196 u16 *ptr = (u16 *)addr;
197 while (count--) {
198 out_be32((void*)port, cpu_to_le16(*ptr++));
199 out_be32((void*)port, cpu_to_le16(*ptr++));
200 }
201}
202
203/**
204 * scc_ratemask - Compute available modes
205 * @drive: IDE drive
206 *
207 * Compute the available speeds for the devices on the interface.
208 * Enforce UDMA33 as a limit if there is no 80pin cable present.
209 */
210
211static u8 scc_ratemask(ide_drive_t *drive)
212{
213 u8 mode = 4;
214
215 if (!eighty_ninty_three(drive))
216 mode = min(mode, (u8)1);
217 return mode;
218}
219
220/**
221 * scc_tuneproc - tune a drive PIO mode
222 * @drive: drive to tune
223 * @mode_wanted: the target operating mode
224 *
225 * Load the timing settings for this device mode into the
226 * controller.
227 */
228
229static void scc_tuneproc(ide_drive_t *drive, byte mode_wanted)
230{
231 ide_hwif_t *hwif = HWIF(drive);
232 struct scc_ports *ports = ide_get_hwifdata(hwif);
233 unsigned long ctl_base = ports->ctl;
234 unsigned long cckctrl_port = ctl_base + 0xff0;
235 unsigned long piosht_port = ctl_base + 0x000;
236 unsigned long pioct_port = ctl_base + 0x004;
237 unsigned long reg;
238 unsigned char speed = XFER_PIO_0;
239 int offset;
240
241 mode_wanted = ide_get_best_pio_mode(drive, mode_wanted, 4, NULL);
242 switch (mode_wanted) {
243 case 4:
244 speed = XFER_PIO_4;
245 break;
246 case 3:
247 speed = XFER_PIO_3;
248 break;
249 case 2:
250 speed = XFER_PIO_2;
251 break;
252 case 1:
253 speed = XFER_PIO_1;
254 break;
255 case 0:
256 default:
257 speed = XFER_PIO_0;
258 break;
259 }
260
261 reg = hwif->INL(cckctrl_port);
262 if (reg & CCKCTRL_ATACLKOEN) {
263 offset = 1; /* 133MHz */
264 } else {
265 offset = 0; /* 100MHz */
266 }
267 reg = JCHSTtbl[offset][mode_wanted] << 16 | JCHHTtbl[offset][mode_wanted];
268 hwif->OUTL(reg, piosht_port);
269 reg = JCHCTtbl[offset][mode_wanted];
270 hwif->OUTL(reg, pioct_port);
271
272 ide_config_drive_speed(drive, speed);
273}
274
275/**
276 * scc_tune_chipset - tune a drive DMA mode
277 * @drive: Drive to set up
278 * @xferspeed: speed we want to achieve
279 *
280 * Load the timing settings for this device mode into the
281 * controller.
282 */
283
284static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed)
285{
286 ide_hwif_t *hwif = HWIF(drive);
287 u8 speed = ide_rate_filter(scc_ratemask(drive), xferspeed);
288 struct scc_ports *ports = ide_get_hwifdata(hwif);
289 unsigned long ctl_base = ports->ctl;
290 unsigned long cckctrl_port = ctl_base + 0xff0;
291 unsigned long mdmact_port = ctl_base + 0x008;
292 unsigned long mcrcst_port = ctl_base + 0x00c;
293 unsigned long sdmact_port = ctl_base + 0x010;
294 unsigned long scrcst_port = ctl_base + 0x014;
295 unsigned long udenvt_port = ctl_base + 0x018;
296 unsigned long tdvhsel_port = ctl_base + 0x020;
297 int is_slave = (&hwif->drives[1] == drive);
298 int offset, idx;
299 unsigned long reg;
300 unsigned long jcactsel;
301
302 reg = hwif->INL(cckctrl_port);
303 if (reg & CCKCTRL_ATACLKOEN) {
304 offset = 1; /* 133MHz */
305 } else {
306 offset = 0; /* 100MHz */
307 }
308
309 switch (speed) {
310 case XFER_UDMA_6:
311 idx = 6;
312 break;
313 case XFER_UDMA_5:
314 idx = 5;
315 break;
316 case XFER_UDMA_4:
317 idx = 4;
318 break;
319 case XFER_UDMA_3:
320 idx = 3;
321 break;
322 case XFER_UDMA_2:
323 idx = 2;
324 break;
325 case XFER_UDMA_1:
326 idx = 1;
327 break;
328 case XFER_UDMA_0:
329 idx = 0;
330 break;
331 default:
332 return 1;
333 }
334
335 jcactsel = JCACTSELtbl[offset][idx];
336 if (is_slave) {
337 hwif->OUTL(JCHDCTxtbl[offset][idx], sdmact_port);
338 hwif->OUTL(JCSTWTxtbl[offset][idx], scrcst_port);
339 jcactsel = jcactsel << 2 ;
340 hwif->OUTL( (hwif->INL( tdvhsel_port ) & ~TDVHSEL_SLAVE) | jcactsel, tdvhsel_port );
341 } else {
342 hwif->OUTL(JCHDCTxtbl[offset][idx], mdmact_port);
343 hwif->OUTL(JCSTWTxtbl[offset][idx], mcrcst_port);
344 hwif->OUTL( (hwif->INL( tdvhsel_port ) & ~TDVHSEL_MASTER) | jcactsel, tdvhsel_port );
345 }
346 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
347 hwif->OUTL(reg, udenvt_port);
348
349 return ide_config_drive_speed(drive, speed);
350}
351
352/**
353 * scc_config_chipset_for_dma - configure for DMA
354 * @drive: drive to configure
355 *
356 * Called by scc_config_drive_for_dma().
357 */
358
359static int scc_config_chipset_for_dma(ide_drive_t *drive)
360{
361 u8 speed = ide_dma_speed(drive, scc_ratemask(drive));
362
363 if (!speed)
364 return 0;
365
366 if (ide_set_xfer_rate(drive, speed))
367 return 0;
368
369 if (!drive->init_speed)
370 drive->init_speed = speed;
371
372 return ide_dma_enable(drive);
373}
374
375/**
376 * scc_configure_drive_for_dma - set up for DMA transfers
377 * @drive: drive we are going to set up
378 *
379 * Set up the drive for DMA, tune the controller and drive as
380 * required.
381 * If the drive isn't suitable for DMA or we hit other problems
382 * then we will drop down to PIO and set up PIO appropriately.
383 * (return 1)
384 */
385
386static int scc_config_drive_for_dma(ide_drive_t *drive)
387{
388 ide_hwif_t *hwif = HWIF(drive);
389 struct hd_driveid *id = drive->id;
390
391 if ((id->capability & 1) != 0 && drive->autodma) {
392 if (ide_use_dma(drive)) {
393 if (scc_config_chipset_for_dma(drive))
394 return hwif->ide_dma_on(drive);
395 }
396 goto fast_ata_pio;
397 } else if ((id->capability & 8) || (id->field_valid & 2)) {
398 fast_ata_pio:
399 hwif->tuneproc(drive, 4);
400 hwif->ide_dma_off_quietly(drive);
401 }
402 return 1; /* DMA is not supported */
403}
404
405/**
406 * scc_ide_dma_end - Stop DMA
407 * @drive: IDE drive
408 *
409 * Check and clear INT Status register.
410 * Then call __ide_dma_end().
411 */
412
413static int scc_ide_dma_end(ide_drive_t * drive)
414{
415 ide_hwif_t *hwif = HWIF(drive);
416 unsigned long intsts_port = hwif->dma_base + 0x014;
417 u32 reg;
418
419 while (1) {
420 reg = hwif->INL(intsts_port);
421
422 if (reg & INTSTS_SERROR) {
423 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
424 hwif->OUTL(INTSTS_SERROR|INTSTS_BMSINT, intsts_port);
425
426 hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS,
427 hwif->dma_command);
428 continue;
429 }
430
431 if (reg & INTSTS_PRERR) {
432 u32 maea0, maec0;
433 unsigned long ctl_base = hwif->config_data;
434
435 maea0 = hwif->INL(ctl_base + 0xF50);
436 maec0 = hwif->INL(ctl_base + 0xF54);
437
438 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
439
440 hwif->OUTL(INTSTS_PRERR|INTSTS_BMSINT, intsts_port);
441
442 hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS,
443 hwif->dma_command);
444 continue;
445 }
446
447 if (reg & INTSTS_RERR) {
448 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
449 hwif->OUTL(INTSTS_RERR|INTSTS_BMSINT, intsts_port);
450
451 hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS,
452 hwif->dma_command);
453 continue;
454 }
455
456 if (reg & INTSTS_ICERR) {
457 hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS,
458 hwif->dma_command);
459
460 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
461 hwif->OUTL(INTSTS_ICERR|INTSTS_BMSINT, intsts_port);
462 continue;
463 }
464
465 if (reg & INTSTS_BMSINT) {
466 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
467 hwif->OUTL(INTSTS_BMSINT, intsts_port);
468
469 ide_do_reset(drive);
470 continue;
471 }
472
473 if (reg & INTSTS_BMHE) {
474 hwif->OUTL(INTSTS_BMHE, intsts_port);
475 continue;
476 }
477
478 if (reg & INTSTS_ACTEINT) {
479 hwif->OUTL(INTSTS_ACTEINT, intsts_port);
480 continue;
481 }
482
483 if (reg & INTSTS_IOIRQS) {
484 hwif->OUTL(INTSTS_IOIRQS, intsts_port);
485 continue;
486 }
487 break;
488 }
489
490 return __ide_dma_end(drive);
491}
492
493/**
494 * setup_mmio_scc - map CTRL/BMID region
495 * @dev: PCI device we are configuring
496 * @name: device name
497 *
498 */
499
500static int setup_mmio_scc (struct pci_dev *dev, const char *name)
501{
502 unsigned long ctl_base = pci_resource_start(dev, 0);
503 unsigned long dma_base = pci_resource_start(dev, 1);
504 unsigned long ctl_size = pci_resource_len(dev, 0);
505 unsigned long dma_size = pci_resource_len(dev, 1);
506 void *ctl_addr;
507 void *dma_addr;
508 int i;
509
510 for (i = 0; i < MAX_HWIFS; i++) {
511 if (scc_ports[i].ctl == 0)
512 break;
513 }
514 if (i >= MAX_HWIFS)
515 return -ENOMEM;
516
517 if (!request_mem_region(ctl_base, ctl_size, name)) {
518 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
519 goto fail_0;
520 }
521
522 if (!request_mem_region(dma_base, dma_size, name)) {
523 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
524 goto fail_1;
525 }
526
527 if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
528 goto fail_2;
529
530 if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
531 goto fail_3;
532
533 pci_set_master(dev);
534 scc_ports[i].ctl = (unsigned long)ctl_addr;
535 scc_ports[i].dma = (unsigned long)dma_addr;
536 pci_set_drvdata(dev, (void *) &scc_ports[i]);
537
538 return 1;
539
540 fail_3:
541 iounmap(ctl_addr);
542 fail_2:
543 release_mem_region(dma_base, dma_size);
544 fail_1:
545 release_mem_region(ctl_base, ctl_size);
546 fail_0:
547 return -ENOMEM;
548}
549
550/**
551 * init_setup_scc - set up an SCC PATA Controller
552 * @dev: PCI device
553 * @d: IDE PCI device
554 *
555 * Perform the initial set up for this device.
556 */
557
558static int __devinit init_setup_scc(struct pci_dev *dev, ide_pci_device_t *d)
559{
560 unsigned long ctl_base;
561 unsigned long dma_base;
562 unsigned long cckctrl_port;
563 unsigned long intmask_port;
564 unsigned long mode_port;
565 unsigned long ecmode_port;
566 unsigned long dma_status_port;
567 u32 reg = 0;
568 struct scc_ports *ports;
569 int rc;
570
571 rc = setup_mmio_scc(dev, d->name);
572 if (rc < 0) {
573 return rc;
574 }
575
576 ports = pci_get_drvdata(dev);
577 ctl_base = ports->ctl;
578 dma_base = ports->dma;
579 cckctrl_port = ctl_base + 0xff0;
580 intmask_port = dma_base + 0x010;
581 mode_port = ctl_base + 0x024;
582 ecmode_port = ctl_base + 0xf00;
583 dma_status_port = dma_base + 0x004;
584
585 /* controller initialization */
586 reg = 0;
587 out_be32((void*)cckctrl_port, reg);
588 reg |= CCKCTRL_ATACLKOEN;
589 out_be32((void*)cckctrl_port, reg);
590 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
591 out_be32((void*)cckctrl_port, reg);
592 reg |= CCKCTRL_CRST;
593 out_be32((void*)cckctrl_port, reg);
594
595 for (;;) {
596 reg = in_be32((void*)cckctrl_port);
597 if (reg & CCKCTRL_CRST)
598 break;
599 udelay(5000);
600 }
601
602 reg |= CCKCTRL_ATARESET;
603 out_be32((void*)cckctrl_port, reg);
604
605 out_be32((void*)ecmode_port, ECMODE_VALUE);
606 out_be32((void*)mode_port, MODE_JCUSFEN);
607 out_be32((void*)intmask_port, INTMASK_MSK);
608
609 return ide_setup_pci_device(dev, d);
610}
611
612/**
613 * init_mmio_iops_scc - set up the iops for MMIO
614 * @hwif: interface to set up
615 *
616 */
617
618static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
619{
620 struct pci_dev *dev = hwif->pci_dev;
621 struct scc_ports *ports = pci_get_drvdata(dev);
622 unsigned long dma_base = ports->dma;
623
624 ide_set_hwifdata(hwif, ports);
625
626 hwif->INB = scc_ide_inb;
627 hwif->INW = scc_ide_inw;
628 hwif->INL = scc_ide_inl;
629 hwif->INSW = scc_ide_insw;
630 hwif->INSL = scc_ide_insl;
631 hwif->OUTB = scc_ide_outb;
632 hwif->OUTBSYNC = scc_ide_outbsync;
633 hwif->OUTW = scc_ide_outw;
634 hwif->OUTL = scc_ide_outl;
635 hwif->OUTSW = scc_ide_outsw;
636 hwif->OUTSL = scc_ide_outsl;
637
638 hwif->io_ports[IDE_DATA_OFFSET] = dma_base + 0x20;
639 hwif->io_ports[IDE_ERROR_OFFSET] = dma_base + 0x24;
640 hwif->io_ports[IDE_NSECTOR_OFFSET] = dma_base + 0x28;
641 hwif->io_ports[IDE_SECTOR_OFFSET] = dma_base + 0x2c;
642 hwif->io_ports[IDE_LCYL_OFFSET] = dma_base + 0x30;
643 hwif->io_ports[IDE_HCYL_OFFSET] = dma_base + 0x34;
644 hwif->io_ports[IDE_SELECT_OFFSET] = dma_base + 0x38;
645 hwif->io_ports[IDE_STATUS_OFFSET] = dma_base + 0x3c;
646 hwif->io_ports[IDE_CONTROL_OFFSET] = dma_base + 0x40;
647
648 hwif->irq = hwif->pci_dev->irq;
649 hwif->dma_base = dma_base;
650 hwif->config_data = ports->ctl;
651 hwif->mmio = 2;
652}
653
654/**
655 * init_iops_scc - set up iops
656 * @hwif: interface to set up
657 *
658 * Do the basic setup for the SCC hardware interface
659 * and then do the MMIO setup.
660 */
661
662static void __devinit init_iops_scc(ide_hwif_t *hwif)
663{
664 struct pci_dev *dev = hwif->pci_dev;
665 hwif->hwif_data = NULL;
666 if (pci_get_drvdata(dev) == NULL)
667 return;
668 init_mmio_iops_scc(hwif);
669}
670
671/**
672 * init_hwif_scc - set up hwif
673 * @hwif: interface to set up
674 *
675 * We do the basic set up of the interface structure. The SCC
676 * requires several custom handlers so we override the default
677 * ide DMA handlers appropriately.
678 */
679
680static void __devinit init_hwif_scc(ide_hwif_t *hwif)
681{
682 struct scc_ports *ports = ide_get_hwifdata(hwif);
683
684 ports->hwif_id = hwif->index;
685
686 hwif->dma_command = hwif->dma_base;
687 hwif->dma_status = hwif->dma_base + 0x04;
688 hwif->dma_prdtable = hwif->dma_base + 0x08;
689
690 hwif->OUTL(hwif->dmatable_dma, (hwif->dma_base + 0x018)); /* PTERADD */
691
692 hwif->ide_dma_end = scc_ide_dma_end;
693 hwif->speedproc = scc_tune_chipset;
694 hwif->tuneproc = scc_tuneproc;
695 hwif->ide_dma_check = scc_config_drive_for_dma;
696
697 hwif->drives[0].autotune = IDE_TUNE_AUTO;
698 hwif->drives[1].autotune = IDE_TUNE_AUTO;
699
700 if (hwif->INL(hwif->config_data + 0xff0) & CCKCTRL_ATACLKOEN) {
701 hwif->ultra_mask = 0x7f; /* 133MHz */
702 } else {
703 hwif->ultra_mask = 0x3f; /* 100MHz */
704 }
705 hwif->mwdma_mask = 0x00;
706 hwif->swdma_mask = 0x00;
707 hwif->atapi_dma = 1;
708
709 /* we support 80c cable only. */
710 hwif->udma_four = 1;
711
712 hwif->autodma = 0;
713 if (!noautodma)
714 hwif->autodma = 1;
715 hwif->drives[0].autodma = hwif->autodma;
716 hwif->drives[1].autodma = hwif->autodma;
717}
718
719#define DECLARE_SCC_DEV(name_str) \
720 { \
721 .name = name_str, \
722 .init_setup = init_setup_scc, \
723 .init_iops = init_iops_scc, \
724 .init_hwif = init_hwif_scc, \
725 .channels = 1, \
726 .autodma = AUTODMA, \
727 .bootable = ON_BOARD, \
728 }
729
730static ide_pci_device_t scc_chipsets[] __devinitdata = {
731 /* 0 */ DECLARE_SCC_DEV("sccIDE"),
732};
733
734/**
735 * scc_init_one - pci layer discovery entry
736 * @dev: PCI device
737 * @id: ident table entry
738 *
739 * Called by the PCI code when it finds an SCC PATA controller.
740 * We then use the IDE PCI generic helper to do most of the work.
741 */
742
743static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
744{
745 ide_pci_device_t *d = &scc_chipsets[id->driver_data];
746 return d->init_setup(dev, d);
747}
748
749/**
750 * scc_remove - pci layer remove entry
751 * @dev: PCI device
752 *
753 * Called by the PCI code when it removes an SCC PATA controller.
754 */
755
756static void __devexit scc_remove(struct pci_dev *dev)
757{
758 struct scc_ports *ports = pci_get_drvdata(dev);
759 ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id];
760 unsigned long ctl_base = pci_resource_start(dev, 0);
761 unsigned long dma_base = pci_resource_start(dev, 1);
762 unsigned long ctl_size = pci_resource_len(dev, 0);
763 unsigned long dma_size = pci_resource_len(dev, 1);
764
765 if (hwif->dmatable_cpu) {
766 pci_free_consistent(hwif->pci_dev,
767 PRD_ENTRIES * PRD_BYTES,
768 hwif->dmatable_cpu,
769 hwif->dmatable_dma);
770 hwif->dmatable_cpu = NULL;
771 }
772
773 ide_unregister(hwif->index);
774
775 hwif->chipset = ide_unknown;
776 iounmap((void*)ports->dma);
777 iounmap((void*)ports->ctl);
778 release_mem_region(dma_base, dma_size);
779 release_mem_region(ctl_base, ctl_size);
780 memset(ports, 0, sizeof(*ports));
781}
782
783static struct pci_device_id scc_pci_tbl[] = {
784 { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
785 { 0, },
786};
787MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
788
789static struct pci_driver driver = {
790 .name = "SCC IDE",
791 .id_table = scc_pci_tbl,
792 .probe = scc_init_one,
793 .remove = scc_remove,
794};
795
796static int scc_ide_init(void)
797{
798 return ide_pci_register_driver(&driver);
799}
800
801module_init(scc_ide_init);
802/* -- No exit code?
803static void scc_ide_exit(void)
804{
805 ide_pci_unregister_driver(&driver);
806}
807module_exit(scc_ide_exit);
808 */
809
810
811MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
812MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 16:21:20 -0500