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-rw-r--r--drivers/infiniband/hw/ipath/ipath_iba6110.c68
-rw-r--r--drivers/infiniband/hw/ipath/ipath_iba6120.c77
-rw-r--r--drivers/infiniband/hw/ipath/ipath_intr.c76
-rw-r--r--drivers/infiniband/hw/ipath/ipath_kernel.h16
-rw-r--r--drivers/infiniband/hw/ipath/ipath_registers.h18
5 files changed, 158 insertions, 97 deletions
diff --git a/drivers/infiniband/hw/ipath/ipath_iba6110.c b/drivers/infiniband/hw/ipath/ipath_iba6110.c
index 5c9b509e40e4..87eb99af5e19 100644
--- a/drivers/infiniband/hw/ipath/ipath_iba6110.c
+++ b/drivers/infiniband/hw/ipath/ipath_iba6110.c
@@ -389,17 +389,28 @@ static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
389 _IPATH_HTLINK1_CRCBITS))); 389 _IPATH_HTLINK1_CRCBITS)));
390} 390}
391 391
392/* 6110 specific hardware errors... */
393static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
394 INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
395 INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
396 INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
397 INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
398 INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
399 INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
400 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
401 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
402};
403
392/** 404/**
393 * ipath_ht_handle_hwerrors - display hardware errors 405 * ipath_ht_handle_hwerrors - display hardware errors.
394 * @dd: the infinipath device 406 * @dd: the infinipath device
395 * @msg: the output buffer 407 * @msg: the output buffer
396 * @msgl: the size of the output buffer 408 * @msgl: the size of the output buffer
397 * 409 *
398 * Use same msg buffer as regular errors to avoid 410 * Use same msg buffer as regular errors to avoid excessive stack
399 * excessive stack use. Most hardware errors are catastrophic, but for 411 * use. Most hardware errors are catastrophic, but for right now,
400 * right now, we'll print them and continue. 412 * we'll print them and continue. We reuse the same message buffer as
401 * We reuse the same message buffer as ipath_handle_errors() to avoid 413 * ipath_handle_errors() to avoid excessive stack usage.
402 * excessive stack usage.
403 */ 414 */
404static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg, 415static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
405 size_t msgl) 416 size_t msgl)
@@ -499,44 +510,16 @@ static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
499 bits); 510 bits);
500 strlcat(msg, bitsmsg, msgl); 511 strlcat(msg, bitsmsg, msgl);
501 } 512 }
502 if (hwerrs & (INFINIPATH_HWE_RXEMEMPARITYERR_MASK 513
503 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)) { 514 ipath_format_hwerrors(hwerrs,
504 bits = (u32) ((hwerrs >> 515 ipath_6110_hwerror_msgs,
505 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) & 516 sizeof(ipath_6110_hwerror_msgs) /
506 INFINIPATH_HWE_RXEMEMPARITYERR_MASK); 517 sizeof(ipath_6110_hwerror_msgs[0]),
507 snprintf(bitsmsg, sizeof bitsmsg, "[RXE Parity Errs %x] ", 518 msg, msgl);
508 bits);
509 strlcat(msg, bitsmsg, msgl);
510 }
511 if (hwerrs & (INFINIPATH_HWE_TXEMEMPARITYERR_MASK
512 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
513 bits = (u32) ((hwerrs >>
514 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) &
515 INFINIPATH_HWE_TXEMEMPARITYERR_MASK);
516 snprintf(bitsmsg, sizeof bitsmsg, "[TXE Parity Errs %x] ",
517 bits);
518 strlcat(msg, bitsmsg, msgl);
519 }
520 if (hwerrs & INFINIPATH_HWE_IBCBUSTOSPCPARITYERR)
521 strlcat(msg, "[IB2IPATH Parity]", msgl);
522 if (hwerrs & INFINIPATH_HWE_IBCBUSFRSPCPARITYERR)
523 strlcat(msg, "[IPATH2IB Parity]", msgl);
524 if (hwerrs & INFINIPATH_HWE_HTCBUSIREQPARITYERR)
525 strlcat(msg, "[HTC Ireq Parity]", msgl);
526 if (hwerrs & INFINIPATH_HWE_HTCBUSTREQPARITYERR)
527 strlcat(msg, "[HTC Treq Parity]", msgl);
528 if (hwerrs & INFINIPATH_HWE_HTCBUSTRESPPARITYERR)
529 strlcat(msg, "[HTC Tresp Parity]", msgl);
530 519
531 if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS)) 520 if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
532 hwerr_crcbits(dd, hwerrs, msg, msgl); 521 hwerr_crcbits(dd, hwerrs, msg, msgl);
533 522
534 if (hwerrs & INFINIPATH_HWE_HTCMISCERR5)
535 strlcat(msg, "[HT core Misc5]", msgl);
536 if (hwerrs & INFINIPATH_HWE_HTCMISCERR6)
537 strlcat(msg, "[HT core Misc6]", msgl);
538 if (hwerrs & INFINIPATH_HWE_HTCMISCERR7)
539 strlcat(msg, "[HT core Misc7]", msgl);
540 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) { 523 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
541 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]", 524 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
542 msgl); 525 msgl);
@@ -573,11 +556,6 @@ static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
573 dd->ipath_hwerrmask); 556 dd->ipath_hwerrmask);
574 } 557 }
575 558
576 if (hwerrs & INFINIPATH_HWE_RXDSYNCMEMPARITYERR)
577 strlcat(msg, "[Rx Dsync]", msgl);
578 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED)
579 strlcat(msg, "[SerDes PLL]", msgl);
580
581 ipath_dev_err(dd, "%s hardware error\n", msg); 559 ipath_dev_err(dd, "%s hardware error\n", msg);
582 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) 560 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
583 /* 561 /*
diff --git a/drivers/infiniband/hw/ipath/ipath_iba6120.c b/drivers/infiniband/hw/ipath/ipath_iba6120.c
index d64b87bf1f97..a4ec50b0fe87 100644
--- a/drivers/infiniband/hw/ipath/ipath_iba6120.c
+++ b/drivers/infiniband/hw/ipath/ipath_iba6120.c
@@ -301,6 +301,26 @@ static const struct ipath_cregs ipath_pe_cregs = {
301 */ 301 */
302#define INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR (1ULL<<63) 302#define INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR (1ULL<<63)
303 303
304/* 6120 specific hardware errors... */
305static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
306 INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
307 INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
308 /*
309 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
310 * parity or memory parity error failures, because most likely we
311 * won't be able to talk to the core of the chip. Nonetheless, we
312 * might see them, if they are in parts of the PCIe core that aren't
313 * essential.
314 */
315 INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
316 INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
317 INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
318 INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
319 INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
320 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
321 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
322};
323
304/** 324/**
305 * ipath_pe_handle_hwerrors - display hardware errors. 325 * ipath_pe_handle_hwerrors - display hardware errors.
306 * @dd: the infinipath device 326 * @dd: the infinipath device
@@ -403,24 +423,13 @@ static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
403 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 423 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
404 dd->ipath_hwerrmask); 424 dd->ipath_hwerrmask);
405 } 425 }
406 if (hwerrs & (INFINIPATH_HWE_RXEMEMPARITYERR_MASK 426
407 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)) { 427 ipath_format_hwerrors(hwerrs,
408 bits = (u32) ((hwerrs >> 428 ipath_6120_hwerror_msgs,
409 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) & 429 sizeof(ipath_6120_hwerror_msgs)/
410 INFINIPATH_HWE_RXEMEMPARITYERR_MASK); 430 sizeof(ipath_6120_hwerror_msgs[0]),
411 snprintf(bitsmsg, sizeof bitsmsg, "[RXE Parity Errs %x] ", 431 msg, msgl);
412 bits); 432
413 strlcat(msg, bitsmsg, msgl);
414 }
415 if (hwerrs & (INFINIPATH_HWE_TXEMEMPARITYERR_MASK
416 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
417 bits = (u32) ((hwerrs >>
418 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) &
419 INFINIPATH_HWE_TXEMEMPARITYERR_MASK);
420 snprintf(bitsmsg, sizeof bitsmsg, "[TXE Parity Errs %x] ",
421 bits);
422 strlcat(msg, bitsmsg, msgl);
423 }
424 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 433 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
425 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) { 434 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
426 bits = (u32) ((hwerrs >> 435 bits = (u32) ((hwerrs >>
@@ -430,10 +439,6 @@ static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
430 "[PCIe Mem Parity Errs %x] ", bits); 439 "[PCIe Mem Parity Errs %x] ", bits);
431 strlcat(msg, bitsmsg, msgl); 440 strlcat(msg, bitsmsg, msgl);
432 } 441 }
433 if (hwerrs & INFINIPATH_HWE_IBCBUSTOSPCPARITYERR)
434 strlcat(msg, "[IB2IPATH Parity]", msgl);
435 if (hwerrs & INFINIPATH_HWE_IBCBUSFRSPCPARITYERR)
436 strlcat(msg, "[IPATH2IB Parity]", msgl);
437 442
438#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \ 443#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
439 INFINIPATH_HWE_COREPLL_RFSLIP ) 444 INFINIPATH_HWE_COREPLL_RFSLIP )
@@ -459,34 +464,6 @@ static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
459 dd->ipath_hwerrmask); 464 dd->ipath_hwerrmask);
460 } 465 }
461 466
462 if (hwerrs & INFINIPATH_HWE_PCIEPOISONEDTLP)
463 strlcat(msg, "[PCIe Poisoned TLP]", msgl);
464 if (hwerrs & INFINIPATH_HWE_PCIECPLTIMEOUT)
465 strlcat(msg, "[PCIe completion timeout]", msgl);
466
467 /*
468 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
469 * parity or memory parity error failures, because most likely we
470 * won't be able to talk to the core of the chip. Nonetheless, we
471 * might see them, if they are in parts of the PCIe core that aren't
472 * essential.
473 */
474 if (hwerrs & INFINIPATH_HWE_PCIE1PLLFAILED)
475 strlcat(msg, "[PCIePLL1]", msgl);
476 if (hwerrs & INFINIPATH_HWE_PCIE0PLLFAILED)
477 strlcat(msg, "[PCIePLL0]", msgl);
478 if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYXTLH)
479 strlcat(msg, "[PCIe XTLH core parity]", msgl);
480 if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYXADM)
481 strlcat(msg, "[PCIe ADM TX core parity]", msgl);
482 if (hwerrs & INFINIPATH_HWE_PCIEBUSPARITYRADM)
483 strlcat(msg, "[PCIe ADM RX core parity]", msgl);
484
485 if (hwerrs & INFINIPATH_HWE_RXDSYNCMEMPARITYERR)
486 strlcat(msg, "[Rx Dsync]", msgl);
487 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED)
488 strlcat(msg, "[SerDes PLL]", msgl);
489
490 ipath_dev_err(dd, "%s hardware error\n", msg); 467 ipath_dev_err(dd, "%s hardware error\n", msg);
491 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) { 468 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
492 /* 469 /*
diff --git a/drivers/infiniband/hw/ipath/ipath_intr.c b/drivers/infiniband/hw/ipath/ipath_intr.c
index 5762b87d12ec..b58d35e85b53 100644
--- a/drivers/infiniband/hw/ipath/ipath_intr.c
+++ b/drivers/infiniband/hw/ipath/ipath_intr.c
@@ -132,6 +132,82 @@ static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs)
132 return ignore_this_time; 132 return ignore_this_time;
133} 133}
134 134
135/* generic hw error messages... */
136#define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \
137 { \
138 .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \
139 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \
140 .msg = "TXE " #a " Memory Parity" \
141 }
142#define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \
143 { \
144 .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \
145 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \
146 .msg = "RXE " #a " Memory Parity" \
147 }
148
149static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = {
150 INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"),
151 INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"),
152
153 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF),
154 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC),
155 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO),
156
157 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF),
158 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ),
159 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID),
160 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID),
161 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF),
162 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO),
163 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO),
164};
165
166/**
167 * ipath_format_hwmsg - format a single hwerror message
168 * @msg message buffer
169 * @msgl length of message buffer
170 * @hwmsg message to add to message buffer
171 */
172static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg)
173{
174 strlcat(msg, "[", msgl);
175 strlcat(msg, hwmsg, msgl);
176 strlcat(msg, "]", msgl);
177}
178
179/**
180 * ipath_format_hwerrors - format hardware error messages for display
181 * @hwerrs hardware errors bit vector
182 * @hwerrmsgs hardware error descriptions
183 * @nhwerrmsgs number of hwerrmsgs
184 * @msg message buffer
185 * @msgl message buffer length
186 */
187void ipath_format_hwerrors(u64 hwerrs,
188 const struct ipath_hwerror_msgs *hwerrmsgs,
189 size_t nhwerrmsgs,
190 char *msg, size_t msgl)
191{
192 int i;
193 const int glen =
194 sizeof(ipath_generic_hwerror_msgs) /
195 sizeof(ipath_generic_hwerror_msgs[0]);
196
197 for (i=0; i<glen; i++) {
198 if (hwerrs & ipath_generic_hwerror_msgs[i].mask) {
199 ipath_format_hwmsg(msg, msgl,
200 ipath_generic_hwerror_msgs[i].msg);
201 }
202 }
203
204 for (i=0; i<nhwerrmsgs; i++) {
205 if (hwerrs & hwerrmsgs[i].mask) {
206 ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg);
207 }
208 }
209}
210
135/* return the strings for the most common link states */ 211/* return the strings for the most common link states */
136static char *ib_linkstate(u32 linkstate) 212static char *ib_linkstate(u32 linkstate)
137{ 213{
diff --git a/drivers/infiniband/hw/ipath/ipath_kernel.h b/drivers/infiniband/hw/ipath/ipath_kernel.h
index e9cd95f3c2e1..a7342ce334a5 100644
--- a/drivers/infiniband/hw/ipath/ipath_kernel.h
+++ b/drivers/infiniband/hw/ipath/ipath_kernel.h
@@ -897,4 +897,20 @@ extern struct mutex ipath_mutex;
897 897
898#endif /* _IPATH_DEBUGGING */ 898#endif /* _IPATH_DEBUGGING */
899 899
900/*
901 * this is used for formatting hw error messages...
902 */
903struct ipath_hwerror_msgs {
904 u64 mask;
905 const char *msg;
906};
907
908#define INFINIPATH_HWE_MSG(a, b) { .mask = INFINIPATH_HWE_##a, .msg = b }
909
910/* in ipath_intr.c... */
911void ipath_format_hwerrors(u64 hwerrs,
912 const struct ipath_hwerror_msgs *hwerrmsgs,
913 size_t nhwerrmsgs,
914 char *msg, size_t lmsg);
915
900#endif /* _IPATH_KERNEL_H */ 916#endif /* _IPATH_KERNEL_H */
diff --git a/drivers/infiniband/hw/ipath/ipath_registers.h b/drivers/infiniband/hw/ipath/ipath_registers.h
index 6e23b3d632b8..37612a83deeb 100644
--- a/drivers/infiniband/hw/ipath/ipath_registers.h
+++ b/drivers/infiniband/hw/ipath/ipath_registers.h
@@ -134,10 +134,24 @@
134#define INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT 40 134#define INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT 40
135#define INFINIPATH_HWE_RXEMEMPARITYERR_MASK 0x7FULL 135#define INFINIPATH_HWE_RXEMEMPARITYERR_MASK 0x7FULL
136#define INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT 44 136#define INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT 44
137#define INFINIPATH_HWE_RXDSYNCMEMPARITYERR 0x0000000400000000ULL
138#define INFINIPATH_HWE_MEMBISTFAILED 0x0040000000000000ULL
139#define INFINIPATH_HWE_IBCBUSTOSPCPARITYERR 0x4000000000000000ULL 137#define INFINIPATH_HWE_IBCBUSTOSPCPARITYERR 0x4000000000000000ULL
140#define INFINIPATH_HWE_IBCBUSFRSPCPARITYERR 0x8000000000000000ULL 138#define INFINIPATH_HWE_IBCBUSFRSPCPARITYERR 0x8000000000000000ULL
139/* txe mem parity errors (shift by INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) */
140#define INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF 0x1ULL
141#define INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC 0x2ULL
142#define INFINIPATH_HWE_TXEMEMPARITYERR_PIOLAUNCHFIFO 0x4ULL
143/* rxe mem parity errors (shift by INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) */
144#define INFINIPATH_HWE_RXEMEMPARITYERR_RCVBUF 0x01ULL
145#define INFINIPATH_HWE_RXEMEMPARITYERR_LOOKUPQ 0x02ULL
146#define INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID 0x04ULL
147#define INFINIPATH_HWE_RXEMEMPARITYERR_EXPTID 0x08ULL
148#define INFINIPATH_HWE_RXEMEMPARITYERR_FLAGBUF 0x10ULL
149#define INFINIPATH_HWE_RXEMEMPARITYERR_DATAINFO 0x20ULL
150#define INFINIPATH_HWE_RXEMEMPARITYERR_HDRINFO 0x40ULL
151/* waldo specific -- find the rest in ipath_6110.c */
152#define INFINIPATH_HWE_RXDSYNCMEMPARITYERR 0x0000000400000000ULL
153/* monty specific -- find the rest in ipath_6120.c */
154#define INFINIPATH_HWE_MEMBISTFAILED 0x0040000000000000ULL
141 155
142/* kr_hwdiagctrl bits */ 156/* kr_hwdiagctrl bits */
143#define INFINIPATH_DC_FORCETXEMEMPARITYERR_MASK 0xFULL 157#define INFINIPATH_DC_FORCETXEMEMPARITYERR_MASK 0xFULL