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-rw-r--r--arch/powerpc/sysdev/Makefile1
-rw-r--r--arch/powerpc/sysdev/mpc52xx_pic.c538
-rw-r--r--include/asm-powerpc/mpc52xx.h287
3 files changed, 826 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index f15af0e82f1c..5b87f7b42a1f 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
12obj-$(CONFIG_FSL_SOC) += fsl_soc.o 12obj-$(CONFIG_FSL_SOC) += fsl_soc.o
13obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 13obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
14obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ 14obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
15obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_pic.o
15 16
16ifeq ($(CONFIG_PPC_MERGE),y) 17ifeq ($(CONFIG_PPC_MERGE),y)
17obj-$(CONFIG_PPC_I8259) += i8259.o 18obj-$(CONFIG_PPC_I8259) += i8259.o
diff --git a/arch/powerpc/sysdev/mpc52xx_pic.c b/arch/powerpc/sysdev/mpc52xx_pic.c
new file mode 100644
index 000000000000..6df51f04b8f5
--- /dev/null
+++ b/arch/powerpc/sysdev/mpc52xx_pic.c
@@ -0,0 +1,538 @@
1/*
2 *
3 * Programmable Interrupt Controller functions for the Freescale MPC52xx.
4 *
5 * Copyright (C) 2006 bplan GmbH
6 *
7 * Based on the code from the 2.4 kernel by
8 * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
9 *
10 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
11 * Copyright (C) 2003 Montavista Software, Inc
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 *
17 */
18
19#undef DEBUG
20
21#include <linux/stddef.h>
22#include <linux/init.h>
23#include <linux/sched.h>
24#include <linux/signal.h>
25#include <linux/stddef.h>
26#include <linux/delay.h>
27#include <linux/irq.h>
28#include <linux/hardirq.h>
29
30#include <asm/io.h>
31#include <asm/processor.h>
32#include <asm/system.h>
33#include <asm/irq.h>
34#include <asm/prom.h>
35#include <asm/mpc52xx.h>
36
37/*
38 *
39*/
40
41static struct mpc52xx_intr __iomem *intr;
42static struct mpc52xx_sdma __iomem *sdma;
43static struct irq_host *mpc52xx_irqhost = NULL;
44
45static unsigned char mpc52xx_map_senses[4] = {
46 IRQ_TYPE_LEVEL_HIGH,
47 IRQ_TYPE_EDGE_RISING,
48 IRQ_TYPE_EDGE_FALLING,
49 IRQ_TYPE_LEVEL_LOW,
50};
51
52/*
53 *
54*/
55
56static inline void io_be_setbit(u32 __iomem * addr, int bitno)
57{
58 out_be32(addr, in_be32(addr) | (1 << bitno));
59}
60
61static inline void io_be_clrbit(u32 __iomem * addr, int bitno)
62{
63 out_be32(addr, in_be32(addr) & ~(1 << bitno));
64}
65
66/*
67 * IRQ[0-3] interrupt irq_chip
68*/
69
70static void mpc52xx_extirq_mask(unsigned int virq)
71{
72 int irq;
73 int l2irq;
74
75 irq = irq_map[virq].hwirq;
76 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
77
78 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
79
80 io_be_clrbit(&intr->ctrl, 11 - l2irq);
81}
82
83static void mpc52xx_extirq_unmask(unsigned int virq)
84{
85 int irq;
86 int l2irq;
87
88 irq = irq_map[virq].hwirq;
89 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
90
91 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
92
93 io_be_setbit(&intr->ctrl, 11 - l2irq);
94}
95
96static void mpc52xx_extirq_ack(unsigned int virq)
97{
98 int irq;
99 int l2irq;
100
101 irq = irq_map[virq].hwirq;
102 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
103
104 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
105
106 io_be_setbit(&intr->ctrl, 27 - l2irq);
107}
108
109static struct irq_chip mpc52xx_extirq_irqchip = {
110 .typename = " MPC52xx IRQ[0-3] ",
111 .mask = mpc52xx_extirq_mask,
112 .unmask = mpc52xx_extirq_unmask,
113 .ack = mpc52xx_extirq_ack,
114};
115
116/*
117 * Main interrupt irq_chip
118*/
119
120static void mpc52xx_main_mask(unsigned int virq)
121{
122 int irq;
123 int l2irq;
124
125 irq = irq_map[virq].hwirq;
126 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
127
128 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
129
130 io_be_setbit(&intr->main_mask, 15 - l2irq);
131}
132
133static void mpc52xx_main_unmask(unsigned int virq)
134{
135 int irq;
136 int l2irq;
137
138 irq = irq_map[virq].hwirq;
139 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
140
141 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
142
143 io_be_clrbit(&intr->main_mask, 15 - l2irq);
144}
145
146static struct irq_chip mpc52xx_main_irqchip = {
147 .typename = "MPC52xx Main",
148 .mask = mpc52xx_main_mask,
149 .mask_ack = mpc52xx_main_mask,
150 .unmask = mpc52xx_main_unmask,
151};
152
153/*
154 * Peripherals interrupt irq_chip
155*/
156
157static void mpc52xx_periph_mask(unsigned int virq)
158{
159 int irq;
160 int l2irq;
161
162 irq = irq_map[virq].hwirq;
163 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
164
165 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
166
167 io_be_setbit(&intr->per_mask, 31 - l2irq);
168}
169
170static void mpc52xx_periph_unmask(unsigned int virq)
171{
172 int irq;
173 int l2irq;
174
175 irq = irq_map[virq].hwirq;
176 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
177
178 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
179
180 io_be_clrbit(&intr->per_mask, 31 - l2irq);
181}
182
183static struct irq_chip mpc52xx_periph_irqchip = {
184 .typename = "MPC52xx Peripherals",
185 .mask = mpc52xx_periph_mask,
186 .mask_ack = mpc52xx_periph_mask,
187 .unmask = mpc52xx_periph_unmask,
188};
189
190/*
191 * SDMA interrupt irq_chip
192*/
193
194static void mpc52xx_sdma_mask(unsigned int virq)
195{
196 int irq;
197 int l2irq;
198
199 irq = irq_map[virq].hwirq;
200 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
201
202 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
203
204 io_be_setbit(&sdma->IntMask, l2irq);
205}
206
207static void mpc52xx_sdma_unmask(unsigned int virq)
208{
209 int irq;
210 int l2irq;
211
212 irq = irq_map[virq].hwirq;
213 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
214
215 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
216
217 io_be_clrbit(&sdma->IntMask, l2irq);
218}
219
220static void mpc52xx_sdma_ack(unsigned int virq)
221{
222 int irq;
223 int l2irq;
224
225 irq = irq_map[virq].hwirq;
226 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
227
228 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
229
230 out_be32(&sdma->IntPend, 1 << l2irq);
231}
232
233static struct irq_chip mpc52xx_sdma_irqchip = {
234 .typename = "MPC52xx SDMA",
235 .mask = mpc52xx_sdma_mask,
236 .unmask = mpc52xx_sdma_unmask,
237 .ack = mpc52xx_sdma_ack,
238};
239
240/*
241 * irq_host
242*/
243
244static int mpc52xx_irqhost_match(struct irq_host *h, struct device_node *node)
245{
246 pr_debug("%s: node=%p\n", __func__, node);
247 return mpc52xx_irqhost->host_data == node;
248}
249
250static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
251 u32 * intspec, unsigned int intsize,
252 irq_hw_number_t * out_hwirq,
253 unsigned int *out_flags)
254{
255 int intrvect_l1;
256 int intrvect_l2;
257 int intrvect_type;
258 int intrvect_linux;
259
260 if (intsize != 3)
261 return -1;
262
263 intrvect_l1 = (int)intspec[0];
264 intrvect_l2 = (int)intspec[1];
265 intrvect_type = (int)intspec[2];
266
267 intrvect_linux =
268 (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & MPC52xx_IRQ_L1_MASK;
269 intrvect_linux |=
270 (intrvect_l2 << MPC52xx_IRQ_L2_OFFSET) & MPC52xx_IRQ_L2_MASK;
271
272 pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
273 intrvect_l2);
274
275 *out_hwirq = intrvect_linux;
276 *out_flags = mpc52xx_map_senses[intrvect_type];
277
278 return 0;
279}
280
281/*
282 * this function retrieves the correct IRQ type out
283 * of the MPC regs
284 * Only externals IRQs needs this
285*/
286static int mpc52xx_irqx_gettype(int irq)
287{
288 int type;
289 u32 ctrl_reg;
290
291 ctrl_reg = in_be32(&intr->ctrl);
292 type = (ctrl_reg >> (22 - irq * 2)) & 0x3;
293
294 return mpc52xx_map_senses[type];
295}
296
297static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
298 irq_hw_number_t irq)
299{
300 int l1irq;
301 int l2irq;
302 struct irq_chip *good_irqchip;
303 void *good_handle;
304 int type;
305
306 l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
307 l2irq = (irq & MPC52xx_IRQ_L2_MASK) >> MPC52xx_IRQ_L2_OFFSET;
308
309 /*
310 * Most of ours IRQs will be level low
311 * Only external IRQs on some platform may be others
312 */
313 type = IRQ_TYPE_LEVEL_LOW;
314
315 switch (l1irq) {
316 case MPC52xx_IRQ_L1_CRIT:
317 pr_debug("%s: Critical. l2=%x\n", __func__, l2irq);
318
319 BUG_ON(l2irq != 0);
320
321 type = mpc52xx_irqx_gettype(l2irq);
322 good_irqchip = &mpc52xx_extirq_irqchip;
323 break;
324
325 case MPC52xx_IRQ_L1_MAIN:
326 pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq);
327
328 if ((l2irq >= 1) && (l2irq <= 3)) {
329 type = mpc52xx_irqx_gettype(l2irq);
330 good_irqchip = &mpc52xx_extirq_irqchip;
331 } else {
332 good_irqchip = &mpc52xx_main_irqchip;
333 }
334 break;
335
336 case MPC52xx_IRQ_L1_PERP:
337 pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq);
338 good_irqchip = &mpc52xx_periph_irqchip;
339 break;
340
341 case MPC52xx_IRQ_L1_SDMA:
342 pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq);
343 good_irqchip = &mpc52xx_sdma_irqchip;
344 break;
345
346 default:
347 pr_debug("%s: Error, unknown L1 IRQ (0x%x)\n", __func__, l1irq);
348 printk(KERN_ERR "Unknow IRQ!\n");
349 return -EINVAL;
350 }
351
352 switch (type) {
353 case IRQ_TYPE_EDGE_FALLING:
354 case IRQ_TYPE_EDGE_RISING:
355 good_handle = handle_edge_irq;
356 break;
357 default:
358 good_handle = handle_level_irq;
359 }
360
361 set_irq_chip_and_handler(virq, good_irqchip, good_handle);
362
363 pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq,
364 (int)irq, type);
365
366 return 0;
367}
368
369static struct irq_host_ops mpc52xx_irqhost_ops = {
370 .match = mpc52xx_irqhost_match,
371 .xlate = mpc52xx_irqhost_xlate,
372 .map = mpc52xx_irqhost_map,
373};
374
375/*
376 * init (public)
377*/
378
379void __init mpc52xx_init_irq(void)
380{
381 struct device_node *picnode = NULL;
382 int picnode_regsize;
383 u32 picnode_regoffset;
384
385 struct device_node *sdmanode = NULL;
386 int sdmanode_regsize;
387 u32 sdmanode_regoffset;
388
389 u64 size64;
390 int flags;
391
392 u32 intr_ctrl;
393
394 picnode = of_find_compatible_node(NULL, "interrupt-controller",
395 "mpc5200-pic");
396 if (picnode == NULL) {
397 printk(KERN_ERR "MPC52xx PIC: "
398 "Unable to find the interrupt controller "
399 "in the OpenFirmware device tree\n");
400 goto end;
401 }
402
403 sdmanode = of_find_compatible_node(NULL, "dma-controller",
404 "mpc5200-bestcomm");
405 if (sdmanode == NULL) {
406 printk(KERN_ERR "MPC52xx PIC"
407 "Unable to find the Bestcomm DMA controller device "
408 "in the OpenFirmware device tree\n");
409 goto end;
410 }
411
412 /* Retrieve PIC ressources */
413 picnode_regoffset = (u32) of_get_address(picnode, 0, &size64, &flags);
414 if (picnode_regoffset == 0) {
415 printk(KERN_ERR "MPC52xx PIC"
416 "Unable to get the interrupt controller address\n");
417 goto end;
418 }
419
420 picnode_regoffset =
421 of_translate_address(picnode, (u32 *) picnode_regoffset);
422 picnode_regsize = (int)size64;
423
424 /* Retrieve SDMA ressources */
425 sdmanode_regoffset = (u32) of_get_address(sdmanode, 0, &size64, &flags);
426 if (sdmanode_regoffset == 0) {
427 printk(KERN_ERR "MPC52xx PIC: "
428 "Unable to get the Bestcomm DMA controller address\n");
429 goto end;
430 }
431
432 sdmanode_regoffset =
433 of_translate_address(sdmanode, (u32 *) sdmanode_regoffset);
434 sdmanode_regsize = (int)size64;
435
436 /* Remap the necessary zones */
437 intr = ioremap(picnode_regoffset, picnode_regsize);
438 if (intr == NULL) {
439 printk(KERN_ERR "MPC52xx PIC: "
440 "Unable to ioremap interrupt controller registers!\n");
441 goto end;
442 }
443
444 sdma = ioremap(sdmanode_regoffset, sdmanode_regsize);
445 if (sdma == NULL) {
446 iounmap(intr);
447 printk(KERN_ERR "MPC52xx PIC: "
448 "Unable to ioremap Bestcomm DMA registers!\n");
449 goto end;
450 }
451
452 printk(KERN_INFO "MPC52xx PIC: MPC52xx PIC Remapped at 0x%8.8x\n",
453 picnode_regoffset);
454 printk(KERN_INFO "MPC52xx PIC: MPC52xx SDMA Remapped at 0x%8.8x\n",
455 sdmanode_regoffset);
456
457 /* Disable all interrupt sources. */
458 out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
459 out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
460 out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
461 out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
462 intr_ctrl = in_be32(&intr->ctrl);
463 intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
464 intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
465 0x00001000 | /* MEE master external enable */
466 0x00000000 | /* 0 means disable IRQ 0-3 */
467 0x00000001; /* CEb route critical normally */
468 out_be32(&intr->ctrl, intr_ctrl);
469
470 /* Zero a bunch of the priority settings. */
471 out_be32(&intr->per_pri1, 0);
472 out_be32(&intr->per_pri2, 0);
473 out_be32(&intr->per_pri3, 0);
474 out_be32(&intr->main_pri1, 0);
475 out_be32(&intr->main_pri2, 0);
476
477 /*
478 * As last step, add an irq host to translate the real
479 * hw irq information provided by the ofw to linux virq
480 */
481
482 mpc52xx_irqhost =
483 irq_alloc_host(IRQ_HOST_MAP_LINEAR, MPC52xx_IRQ_HIGHTESTHWIRQ,
484 &mpc52xx_irqhost_ops, -1);
485
486 if (mpc52xx_irqhost) {
487 mpc52xx_irqhost->host_data = picnode;
488 printk(KERN_INFO "MPC52xx PIC is up and running!\n");
489 } else {
490 printk(KERN_ERR
491 "MPC52xx PIC: Unable to allocate the IRQ host\n");
492 }
493
494end:
495 of_node_put(picnode);
496 of_node_put(sdmanode);
497}
498
499/*
500 * get_irq (public)
501*/
502unsigned int mpc52xx_get_irq(void)
503{
504 u32 status;
505 int irq = NO_IRQ_IGNORE;
506
507 status = in_be32(&intr->enc_status);
508 if (status & 0x00000400) { /* critical */
509 irq = (status >> 8) & 0x3;
510 if (irq == 2) /* high priority peripheral */
511 goto peripheral;
512 irq |= (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET) &
513 MPC52xx_IRQ_L1_MASK;
514 } else if (status & 0x00200000) { /* main */
515 irq = (status >> 16) & 0x1f;
516 if (irq == 4) /* low priority peripheral */
517 goto peripheral;
518 irq |= (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET) &
519 MPC52xx_IRQ_L1_MASK;
520 } else if (status & 0x20000000) { /* peripheral */
521 peripheral:
522 irq = (status >> 24) & 0x1f;
523 if (irq == 0) { /* bestcomm */
524 status = in_be32(&sdma->IntPend);
525 irq = ffs(status) - 1;
526 irq |= (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET) &
527 MPC52xx_IRQ_L1_MASK;
528 } else
529 irq |= (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET) &
530 MPC52xx_IRQ_L1_MASK;
531 }
532
533 pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
534 irq_linear_revmap(mpc52xx_irqhost, irq));
535
536 return irq_linear_revmap(mpc52xx_irqhost, irq);
537}
538
diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
new file mode 100644
index 000000000000..e9aa622f19f6
--- /dev/null
+++ b/include/asm-powerpc/mpc52xx.h
@@ -0,0 +1,287 @@
1/*
2 * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
3 * May need to be cleaned as the port goes on ...
4 *
5 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2003 MontaVista, Software, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13#ifndef __ASM_POWERPC_MPC52xx_H__
14#define __ASM_POWERPC_MPC52xx_H__
15
16#ifndef __ASSEMBLY__
17#include <asm/types.h>
18#include <asm/prom.h>
19#endif /* __ASSEMBLY__ */
20
21
22/* ======================================================================== */
23/* HW IRQ mapping */
24/* ======================================================================== */
25
26#define MPC52xx_IRQ_L1_CRIT (0)
27#define MPC52xx_IRQ_L1_MAIN (1)
28#define MPC52xx_IRQ_L1_PERP (2)
29#define MPC52xx_IRQ_L1_SDMA (3)
30
31#define MPC52xx_IRQ_L1_OFFSET (6)
32#define MPC52xx_IRQ_L1_MASK (0xc0)
33
34#define MPC52xx_IRQ_L2_OFFSET (0)
35#define MPC52xx_IRQ_L2_MASK (0x3f)
36
37#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
38
39
40/* ======================================================================== */
41/* Structures mapping of some unit register set */
42/* ======================================================================== */
43
44#ifndef __ASSEMBLY__
45
46/* Interrupt controller Register set */
47struct mpc52xx_intr {
48 u32 per_mask; /* INTR + 0x00 */
49 u32 per_pri1; /* INTR + 0x04 */
50 u32 per_pri2; /* INTR + 0x08 */
51 u32 per_pri3; /* INTR + 0x0c */
52 u32 ctrl; /* INTR + 0x10 */
53 u32 main_mask; /* INTR + 0x14 */
54 u32 main_pri1; /* INTR + 0x18 */
55 u32 main_pri2; /* INTR + 0x1c */
56 u32 reserved1; /* INTR + 0x20 */
57 u32 enc_status; /* INTR + 0x24 */
58 u32 crit_status; /* INTR + 0x28 */
59 u32 main_status; /* INTR + 0x2c */
60 u32 per_status; /* INTR + 0x30 */
61 u32 reserved2; /* INTR + 0x34 */
62 u32 per_error; /* INTR + 0x38 */
63};
64
65/* Memory Mapping Control */
66struct mpc52xx_mmap_ctl {
67 u32 mbar; /* MMAP_CTRL + 0x00 */
68
69 u32 cs0_start; /* MMAP_CTRL + 0x04 */
70 u32 cs0_stop; /* MMAP_CTRL + 0x08 */
71 u32 cs1_start; /* MMAP_CTRL + 0x0c */
72 u32 cs1_stop; /* MMAP_CTRL + 0x10 */
73 u32 cs2_start; /* MMAP_CTRL + 0x14 */
74 u32 cs2_stop; /* MMAP_CTRL + 0x18 */
75 u32 cs3_start; /* MMAP_CTRL + 0x1c */
76 u32 cs3_stop; /* MMAP_CTRL + 0x20 */
77 u32 cs4_start; /* MMAP_CTRL + 0x24 */
78 u32 cs4_stop; /* MMAP_CTRL + 0x28 */
79 u32 cs5_start; /* MMAP_CTRL + 0x2c */
80 u32 cs5_stop; /* MMAP_CTRL + 0x30 */
81
82 u32 sdram0; /* MMAP_CTRL + 0x34 */
83 u32 sdram1; /* MMAP_CTRL + 0X38 */
84
85 u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
86
87 u32 boot_start; /* MMAP_CTRL + 0x4c */
88 u32 boot_stop; /* MMAP_CTRL + 0x50 */
89
90 u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
91
92 u32 cs6_start; /* MMAP_CTRL + 0x58 */
93 u32 cs6_stop; /* MMAP_CTRL + 0x5c */
94 u32 cs7_start; /* MMAP_CTRL + 0x60 */
95 u32 cs7_stop; /* MMAP_CTRL + 0x64 */
96};
97
98/* SDRAM control */
99struct mpc52xx_sdram {
100 u32 mode; /* SDRAM + 0x00 */
101 u32 ctrl; /* SDRAM + 0x04 */
102 u32 config1; /* SDRAM + 0x08 */
103 u32 config2; /* SDRAM + 0x0c */
104};
105
106/* SDMA */
107struct mpc52xx_sdma {
108 u32 taskBar; /* SDMA + 0x00 */
109 u32 currentPointer; /* SDMA + 0x04 */
110 u32 endPointer; /* SDMA + 0x08 */
111 u32 variablePointer; /* SDMA + 0x0c */
112
113 u8 IntVect1; /* SDMA + 0x10 */
114 u8 IntVect2; /* SDMA + 0x11 */
115 u16 PtdCntrl; /* SDMA + 0x12 */
116
117 u32 IntPend; /* SDMA + 0x14 */
118 u32 IntMask; /* SDMA + 0x18 */
119
120 u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
121
122 u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
123
124 u32 cReqSelect; /* SDMA + 0x5c */
125 u32 task_size0; /* SDMA + 0x60 */
126 u32 task_size1; /* SDMA + 0x64 */
127 u32 MDEDebug; /* SDMA + 0x68 */
128 u32 ADSDebug; /* SDMA + 0x6c */
129 u32 Value1; /* SDMA + 0x70 */
130 u32 Value2; /* SDMA + 0x74 */
131 u32 Control; /* SDMA + 0x78 */
132 u32 Status; /* SDMA + 0x7c */
133 u32 PTDDebug; /* SDMA + 0x80 */
134};
135
136/* GPT */
137struct mpc52xx_gpt {
138 u32 mode; /* GPTx + 0x00 */
139 u32 count; /* GPTx + 0x04 */
140 u32 pwm; /* GPTx + 0x08 */
141 u32 status; /* GPTx + 0X0c */
142};
143
144/* GPIO */
145struct mpc52xx_gpio {
146 u32 port_config; /* GPIO + 0x00 */
147 u32 simple_gpioe; /* GPIO + 0x04 */
148 u32 simple_ode; /* GPIO + 0x08 */
149 u32 simple_ddr; /* GPIO + 0x0c */
150 u32 simple_dvo; /* GPIO + 0x10 */
151 u32 simple_ival; /* GPIO + 0x14 */
152 u8 outo_gpioe; /* GPIO + 0x18 */
153 u8 reserved1[3]; /* GPIO + 0x19 */
154 u8 outo_dvo; /* GPIO + 0x1c */
155 u8 reserved2[3]; /* GPIO + 0x1d */
156 u8 sint_gpioe; /* GPIO + 0x20 */
157 u8 reserved3[3]; /* GPIO + 0x21 */
158 u8 sint_ode; /* GPIO + 0x24 */
159 u8 reserved4[3]; /* GPIO + 0x25 */
160 u8 sint_ddr; /* GPIO + 0x28 */
161 u8 reserved5[3]; /* GPIO + 0x29 */
162 u8 sint_dvo; /* GPIO + 0x2c */
163 u8 reserved6[3]; /* GPIO + 0x2d */
164 u8 sint_inten; /* GPIO + 0x30 */
165 u8 reserved7[3]; /* GPIO + 0x31 */
166 u16 sint_itype; /* GPIO + 0x34 */
167 u16 reserved8; /* GPIO + 0x36 */
168 u8 gpio_control; /* GPIO + 0x38 */
169 u8 reserved9[3]; /* GPIO + 0x39 */
170 u8 sint_istat; /* GPIO + 0x3c */
171 u8 sint_ival; /* GPIO + 0x3d */
172 u8 bus_errs; /* GPIO + 0x3e */
173 u8 reserved10; /* GPIO + 0x3f */
174};
175
176#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
177#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
178#define MPC52xx_GPIO_PCI_DIS (1<<15)
179
180/* GPIO with WakeUp*/
181struct mpc52xx_gpio_wkup {
182 u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
183 u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
184 u8 wkup_ode; /* GPIO_WKUP + 0x04 */
185 u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
186 u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
187 u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
188 u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
189 u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
190 u8 wkup_inten; /* GPIO_WKUP + 0x10 */
191 u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
192 u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
193 u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
194 u16 wkup_itype; /* GPIO_WKUP + 0x18 */
195 u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
196 u8 wkup_maste; /* GPIO_WKUP + 0x1C */
197 u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
198 u8 wkup_ival; /* GPIO_WKUP + 0x20 */
199 u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
200 u8 wkup_istat; /* GPIO_WKUP + 0x24 */
201 u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
202};
203
204/* XLB Bus control */
205struct mpc52xx_xlb {
206 u8 reserved[0x40];
207 u32 config; /* XLB + 0x40 */
208 u32 version; /* XLB + 0x44 */
209 u32 status; /* XLB + 0x48 */
210 u32 int_enable; /* XLB + 0x4c */
211 u32 addr_capture; /* XLB + 0x50 */
212 u32 bus_sig_capture; /* XLB + 0x54 */
213 u32 addr_timeout; /* XLB + 0x58 */
214 u32 data_timeout; /* XLB + 0x5c */
215 u32 bus_act_timeout; /* XLB + 0x60 */
216 u32 master_pri_enable; /* XLB + 0x64 */
217 u32 master_priority; /* XLB + 0x68 */
218 u32 base_address; /* XLB + 0x6c */
219 u32 snoop_window; /* XLB + 0x70 */
220};
221
222#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
223#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
224
225/* Clock Distribution control */
226struct mpc52xx_cdm {
227 u32 jtag_id; /* CDM + 0x00 reg0 read only */
228 u32 rstcfg; /* CDM + 0x04 reg1 read only */
229 u32 breadcrumb; /* CDM + 0x08 reg2 */
230
231 u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
232 u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
233 u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
234 u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
235
236 u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
237 u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
238 u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
239
240 u32 clk_enables; /* CDM + 0x14 reg5 */
241
242 u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
243 u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
244
245 u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
246 u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
247 u8 reserved1; /* CDM + 0x1e reg7 byte2 */
248 u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
249
250 u8 soft_reset; /* CDM + 0x20 u8 byte0 */
251 u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
252 u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
253
254 u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
255 u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
256 u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
257 u8 reserved3; /* CDM + 0x27 reg9 byte3 */
258
259 u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
260 u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
261
262 u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
263 u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
264
265 u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
266 u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
267
268 u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
269 u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
270};
271
272#endif /* __ASSEMBLY__ */
273
274
275/* ========================================================================= */
276/* Prototypes for MPC52xx sysdev */
277/* ========================================================================= */
278
279#ifndef __ASSEMBLY__
280
281extern void mpc52xx_init_irq(void);
282extern unsigned int mpc52xx_get_irq(void);
283
284#endif /* __ASSEMBLY__ */
285
286#endif /* __ASM_POWERPC_MPC52xx_H__ */
287
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