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-rw-r--r--arch/arm/mach-omap2/devices.c8
-rw-r--r--arch/arm/mach-omap2/timer-mpu.c2
-rw-r--r--arch/arm/mach-omap2/usb-musb.c4
-rw-r--r--arch/arm/plat-omap/devices.c4
-rw-r--r--arch/arm/plat-omap/dma.c2
-rw-r--r--arch/arm/plat-omap/dmtimer.c24
-rw-r--r--arch/arm/plat-omap/gpio.c12
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h92
8 files changed, 31 insertions, 117 deletions
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c104d5ca65b2..23e4d7733610 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -191,7 +191,7 @@ static struct resource omap4_mbox_resources[] = {
191 .flags = IORESOURCE_MEM, 191 .flags = IORESOURCE_MEM,
192 }, 192 },
193 { 193 {
194 .start = INT_44XX_MAIL_U0_MPU, 194 .start = OMAP44XX_IRQ_MAIL_U0,
195 .flags = IORESOURCE_IRQ, 195 .flags = IORESOURCE_IRQ,
196 }, 196 },
197}; 197};
@@ -720,13 +720,13 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
720 if (!cpu_is_omap44xx()) 720 if (!cpu_is_omap44xx())
721 return; 721 return;
722 base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET; 722 base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
723 irq = INT_44XX_MMC4_IRQ; 723 irq = OMAP44XX_IRQ_MMC4;
724 break; 724 break;
725 case 4: 725 case 4:
726 if (!cpu_is_omap44xx()) 726 if (!cpu_is_omap44xx())
727 return; 727 return;
728 base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET; 728 base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
729 irq = INT_44XX_MMC5_IRQ; 729 irq = OMAP44XX_IRQ_MMC4;
730 break; 730 break;
731 default: 731 default:
732 continue; 732 continue;
@@ -738,7 +738,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
738 } else if (cpu_is_omap44xx()) { 738 } else if (cpu_is_omap44xx()) {
739 if (i < 3) { 739 if (i < 3) {
740 base += OMAP4_MMC_REG_OFFSET; 740 base += OMAP4_MMC_REG_OFFSET;
741 irq += IRQ_GIC_START; 741 irq += OMAP44XX_IRQ_GIC_START;
742 } 742 }
743 size = OMAP4_HSMMC_SIZE; 743 size = OMAP4_HSMMC_SIZE;
744 name = "mmci-omap-hs"; 744 name = "mmci-omap-hs";
diff --git a/arch/arm/mach-omap2/timer-mpu.c b/arch/arm/mach-omap2/timer-mpu.c
index c1a650a9910f..954682e64399 100644
--- a/arch/arm/mach-omap2/timer-mpu.c
+++ b/arch/arm/mach-omap2/timer-mpu.c
@@ -28,7 +28,7 @@
28 */ 28 */
29void __cpuinit local_timer_setup(struct clock_event_device *evt) 29void __cpuinit local_timer_setup(struct clock_event_device *evt)
30{ 30{
31 evt->irq = INT_44XX_LOCALTIMER_IRQ; 31 evt->irq = OMAP44XX_IRQ_LOCALTIMER;
32 twd_timer_setup(evt); 32 twd_timer_setup(evt);
33} 33}
34 34
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index d5bea43e9422..6d41fa7b2ce8 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -94,8 +94,8 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
94 musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; 94 musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
95 } else if (cpu_is_omap44xx()) { 95 } else if (cpu_is_omap44xx()) {
96 musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE; 96 musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE;
97 musb_resources[1].start = INT_44XX_HS_USB_MC; 97 musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N;
98 musb_resources[2].start = INT_44XX_HS_USB_DMA; 98 musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N;
99 } 99 }
100 musb_resources[0].end = musb_resources[0].start + SZ_4K - 1; 100 musb_resources[0].end = musb_resources[0].start + SZ_4K - 1;
101 101
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 3a3e357fff3c..4a4cd8774aaa 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -205,8 +205,8 @@ static struct resource mcpdm_resources[] = {
205 }, 205 },
206 { 206 {
207 .name = "mcpdm_irq", 207 .name = "mcpdm_irq",
208 .start = INT_44XX_MCPDM_IRQ, 208 .start = OMAP44XX_IRQ_MCPDM,
209 .end = INT_44XX_MCPDM_IRQ, 209 .end = OMAP44XX_IRQ_MCPDM,
210 .flags = IORESOURCE_IRQ, 210 .flags = IORESOURCE_IRQ,
211 }, 211 },
212}; 212};
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 049165c9aaad..2ab224c8e16c 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2132,7 +2132,7 @@ static int __init omap_init_dma(void)
2132 if (cpu_class_is_omap2()) { 2132 if (cpu_class_is_omap2()) {
2133 int irq; 2133 int irq;
2134 if (cpu_is_omap44xx()) 2134 if (cpu_is_omap44xx())
2135 irq = INT_44XX_SDMA_IRQ0; 2135 irq = OMAP44XX_IRQ_SDMA_0;
2136 else 2136 else
2137 irq = INT_24XX_SDMA_IRQ0; 2137 irq = INT_24XX_SDMA_IRQ0;
2138 setup_irq(irq, &omap24xx_dma_irq); 2138 setup_irq(irq, &omap24xx_dma_irq);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 24bf692fe65e..4d99dfbc8bef 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -250,18 +250,18 @@ static const int omap3_dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
250 250
251#ifdef CONFIG_ARCH_OMAP4 251#ifdef CONFIG_ARCH_OMAP4
252static struct omap_dm_timer omap4_dm_timers[] = { 252static struct omap_dm_timer omap4_dm_timers[] = {
253 { .phys_base = 0x4a318000, .irq = INT_44XX_GPTIMER1 }, 253 { .phys_base = 0x4a318000, .irq = OMAP44XX_IRQ_GPT1 },
254 { .phys_base = 0x48032000, .irq = INT_44XX_GPTIMER2 }, 254 { .phys_base = 0x48032000, .irq = OMAP44XX_IRQ_GPT2 },
255 { .phys_base = 0x48034000, .irq = INT_44XX_GPTIMER3 }, 255 { .phys_base = 0x48034000, .irq = OMAP44XX_IRQ_GPT3 },
256 { .phys_base = 0x48036000, .irq = INT_44XX_GPTIMER4 }, 256 { .phys_base = 0x48036000, .irq = OMAP44XX_IRQ_GPT4 },
257 { .phys_base = 0x40138000, .irq = INT_44XX_GPTIMER5 }, 257 { .phys_base = 0x40138000, .irq = OMAP44XX_IRQ_GPT5 },
258 { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER6 }, 258 { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT6 },
259 { .phys_base = 0x4013a000, .irq = INT_44XX_GPTIMER7 }, 259 { .phys_base = 0x4013a000, .irq = OMAP44XX_IRQ_GPT7 },
260 { .phys_base = 0x4013e000, .irq = INT_44XX_GPTIMER8 }, 260 { .phys_base = 0x4013e000, .irq = OMAP44XX_IRQ_GPT8 },
261 { .phys_base = 0x4803e000, .irq = INT_44XX_GPTIMER9 }, 261 { .phys_base = 0x4803e000, .irq = OMAP44XX_IRQ_GPT9 },
262 { .phys_base = 0x48086000, .irq = INT_44XX_GPTIMER10 }, 262 { .phys_base = 0x48086000, .irq = OMAP44XX_IRQ_GPT10 },
263 { .phys_base = 0x48088000, .irq = INT_44XX_GPTIMER11 }, 263 { .phys_base = 0x48088000, .irq = OMAP44XX_IRQ_GPT11 },
264 { .phys_base = 0x4a320000, .irq = INT_44XX_GPTIMER12 }, 264 { .phys_base = 0x4a320000, .irq = OMAP44XX_IRQ_GPT12 },
265}; 265};
266static const char *omap4_dm_source_names[] __initdata = { 266static const char *omap4_dm_source_names[] __initdata = {
267 "sys_ck", 267 "sys_ck",
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 6055028dff1e..337199ed3479 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -312,17 +312,17 @@ static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
312 312
313#ifdef CONFIG_ARCH_OMAP4 313#ifdef CONFIG_ARCH_OMAP4
314static struct gpio_bank gpio_bank_44xx[6] = { 314static struct gpio_bank gpio_bank_44xx[6] = {
315 { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, 315 { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
316 METHOD_GPIO_44XX }, 316 METHOD_GPIO_44XX },
317 { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, 317 { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
318 METHOD_GPIO_44XX }, 318 METHOD_GPIO_44XX },
319 { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, 319 { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
320 METHOD_GPIO_44XX }, 320 METHOD_GPIO_44XX },
321 { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, 321 { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
322 METHOD_GPIO_44XX }, 322 METHOD_GPIO_44XX },
323 { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, 323 { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
324 METHOD_GPIO_44XX }, 324 METHOD_GPIO_44XX },
325 { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, 325 { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
326 METHOD_GPIO_44XX }, 326 METHOD_GPIO_44XX },
327}; 327};
328 328
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index e8205c13a27a..b65088a869e9 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -28,6 +28,9 @@
28#ifndef __ASM_ARCH_OMAP15XX_IRQS_H 28#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
29#define __ASM_ARCH_OMAP15XX_IRQS_H 29#define __ASM_ARCH_OMAP15XX_IRQS_H
30 30
31/* All OMAP4 specific defines are moved to irqs-44xx.h */
32#include "irqs-44xx.h"
33
31/* 34/*
32 * IRQ numbers for interrupt handler 1 35 * IRQ numbers for interrupt handler 1
33 * 36 *
@@ -355,95 +358,6 @@
355#define INT_35XX_CCDC_VD1_IRQ 92 358#define INT_35XX_CCDC_VD1_IRQ 92
356#define INT_35XX_CCDC_VD2_IRQ 93 359#define INT_35XX_CCDC_VD2_IRQ 93
357 360
358#define IRQ_GIC_START 32
359#define INT_44XX_LOCALTIMER_IRQ 29
360#define INT_44XX_LOCALWDT_IRQ 30
361
362#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
363#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
364#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
365#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
366#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
367#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
368#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
369#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
370#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
371#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
372#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
373#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
374#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
375#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
376#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
377#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
378#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
379#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
380#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
381#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
382#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
383#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
384#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
385#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
386#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
387#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
388#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
389#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
390#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
391#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
392#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
393#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
394#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
395#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
396#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
397#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
398#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
399#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
400#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
401#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
402#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
403#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
404#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
405#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
406#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
407#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
408#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
409#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
410#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
411#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
412#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
413
414#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
415#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
416#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
417#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
418#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
419#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
420#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
421
422#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
423#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
424#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
425#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
426#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
427#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
428#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
429#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
430#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
431#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
432#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
433#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
434#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
435#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START)
436#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
437#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
438#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
439#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
440#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
441#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
442#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
443#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
444#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
445#define INT_44XX_MCPDM_IRQ (112 + IRQ_GIC_START)
446
447/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and 361/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
448 * 16 MPUIO lines */ 362 * 16 MPUIO lines */
449#define OMAP_MAX_GPIO_LINES 192 363#define OMAP_MAX_GPIO_LINES 192
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 00:20:24 -0500