1 files changed, 25 insertions, 25 deletions
diff --git a/include/asm-x86/apicdef.h b/include/asm-x86/apicdef.h
index 674a2280e21e..8b244683431b 100644
--- a/include/asm-x86/apicdef.h
+++ b/include/asm-x86/apicdef.h
@@ -14,10 +14,10 @@
 #define APIC_LVR        0x30
 #define         APIC_LVR_MASK           0xFF00FF
-#define         GET_APIC_VERSION(x)     ((x)&0xFFu)
+#define         GET_APIC_VERSION(x)     ((x) & 0xFFu)
-#define         GET_APIC_MAXLVT(x)      (((x)>>16)&0xFFu)
+#define         GET_APIC_MAXLVT(x)      (((x) >> 16) & 0xFFu)
 #ifdef CONFIG_X86_32
-#  define       APIC_INTEGRATED(x)      ((x)&0xF0u)
+#  define       APIC_INTEGRATED(x)      ((x) & 0xF0u)
 #else
 #  define       APIC_INTEGRATED(x)      (1)
 #endif
@@ -31,16 +31,16 @@
 #define         APIC_EIO_ACK            0x0
 #define APIC_RRR        0xC0
 #define APIC_LDR        0xD0
-#define         APIC_LDR_MASK           (0xFFu<<24)
+#define         APIC_LDR_MASK           (0xFFu << 24)
-#define         GET_APIC_LOGICAL_ID(x)  (((x)>>24)&0xFFu)
+#define         GET_APIC_LOGICAL_ID(x)  (((x) >> 24) & 0xFFu)
-#define         SET_APIC_LOGICAL_ID(x)  (((x)<<24))
+#define         SET_APIC_LOGICAL_ID(x)  (((x) << 24))
 #define         APIC_ALL_CPUS           0xFFu
 #define APIC_DFR        0xE0
 #define         APIC_DFR_CLUSTER                0x0FFFFFFFul
 #define         APIC_DFR_FLAT                   0xFFFFFFFFul
 #define APIC_SPIV       0xF0
-#define         APIC_SPIV_FOCUS_DISABLED        (1<<9)
+#define         APIC_SPIV_FOCUS_DISABLED        (1 << 9)
-#define         APIC_SPIV_APIC_ENABLED          (1<<8)
+#define         APIC_SPIV_APIC_ENABLED          (1 << 8)
 #define APIC_ISR        0x100
 #define APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
 #define APIC_TMR        0x180
@@ -76,27 +76,27 @@
 #define         APIC_DM_EXTINT          0x00700
 #define         APIC_VECTOR_MASK        0x000FF
 #define APIC_ICR2       0x310
-#define         GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
+#define         GET_APIC_DEST_FIELD(x)  (((x) >> 24) & 0xFF)
-#define         SET_APIC_DEST_FIELD(x)  ((x)<<24)
+#define         SET_APIC_DEST_FIELD(x)  ((x) << 24)
 #define APIC_LVTT       0x320
 #define APIC_LVTTHMR    0x330
 #define APIC_LVTPC      0x340
 #define APIC_LVT0       0x350
-#define         APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
+#define         APIC_LVT_TIMER_BASE_MASK        (0x3 << 18)
-#define         GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
+#define         GET_APIC_TIMER_BASE(x)          (((x) >> 18) & 0x3)
-#define         SET_APIC_TIMER_BASE(x)          (((x)<<18))
+#define         SET_APIC_TIMER_BASE(x)          (((x) << 18))
 #define         APIC_TIMER_BASE_CLKIN           0x0
 #define         APIC_TIMER_BASE_TMBASE          0x1
 #define         APIC_TIMER_BASE_DIV             0x2
-#define         APIC_LVT_TIMER_PERIODIC         (1<<17)
+#define         APIC_LVT_TIMER_PERIODIC         (1 << 17)
-#define         APIC_LVT_MASKED                 (1<<16)
+#define         APIC_LVT_MASKED                 (1 << 16)
-#define         APIC_LVT_LEVEL_TRIGGER          (1<<15)
+#define         APIC_LVT_LEVEL_TRIGGER          (1 << 15)
-#define         APIC_LVT_REMOTE_IRR             (1<<14)
+#define         APIC_LVT_REMOTE_IRR             (1 << 14)
-#define         APIC_INPUT_POLARITY             (1<<13)
+#define         APIC_INPUT_POLARITY             (1 << 13)
-#define         APIC_SEND_PENDING               (1<<12)
+#define         APIC_SEND_PENDING               (1 << 12)
 #define         APIC_MODE_MASK                  0x700
-#define         GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
+#define         GET_APIC_DELIVERY_MODE(x)       (((x) >> 8) & 0x7)
-#define         SET_APIC_DELIVERY_MODE(x, y)    (((x)&~0x700)|((y)<<8))
+#define         SET_APIC_DELIVERY_MODE(x, y)    (((x) & ~0x700) | ((y) << 8))
 #define                 APIC_MODE_FIXED         0x0
 #define                 APIC_MODE_NMI           0x4
 #define                 APIC_MODE_EXTINT        0x7
@@ -105,7 +105,7 @@
 #define APIC_TMICT      0x380
 #define APIC_TMCCT      0x390
 #define APIC_TDCR       0x3E0
-#define         APIC_TDR_DIV_TMBASE     (1<<2)
+#define         APIC_TDR_DIV_TMBASE     (1 << 2)
 #define         APIC_TDR_DIV_1          0xB
 #define         APIC_TDR_DIV_2          0x0
 #define         APIC_TDR_DIV_4          0x1
@@ -115,14 +115,14 @@
 #define         APIC_TDR_DIV_64         0x9
 #define         APIC_TDR_DIV_128        0xA
 #define APIC_EILVT0     0x500
-#define         APIC_EILVT_NR_AMD_K8    1       /* Number of extended interrupts */
+#define         APIC_EILVT_NR_AMD_K8    1       /* # of extended interrupts */
 #define         APIC_EILVT_NR_AMD_10H   4
-#define         APIC_EILVT_LVTOFF(x)    (((x)>>4)&0xF)
+#define         APIC_EILVT_LVTOFF(x)    (((x) >> 4) & 0xF)
 #define         APIC_EILVT_MSG_FIX      0x0
 #define         APIC_EILVT_MSG_SMI      0x2
 #define         APIC_EILVT_MSG_NMI      0x4
 #define         APIC_EILVT_MSG_EXT      0x7
-#define         APIC_EILVT_MASKED       (1<<16)
+#define         APIC_EILVT_MASKED       (1 << 16)
 #define APIC_EILVT1     0x510
 #define APIC_EILVT2     0x520
 #define APIC_EILVT3     0x530

diff --git a/include/asm-x86/apicdef.h b/include/asm-x86/apicdef.h index 674a2280e21e..8b244683431b 100644 --- a/include/asm-x86/apicdef.h +++ b/include/asm-x86/apicdef.h
@@ -14,10 +14,10 @@
14		14
15	#define APIC_LVR 0x30	15	#define APIC_LVR 0x30
16	#define APIC_LVR_MASK 0xFF00FF	16	#define APIC_LVR_MASK 0xFF00FF
17	#define GET_APIC_VERSION(x) ((x)&0xFFu)	17	#define GET_APIC_VERSION(x) ((x) & 0xFFu)
18	#define GET_APIC_MAXLVT(x) (((x)>>16)&0xFFu)	18	#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
19	#ifdef CONFIG_X86_32	19	#ifdef CONFIG_X86_32
20	# define APIC_INTEGRATED(x) ((x)&0xF0u)	20	# define APIC_INTEGRATED(x) ((x) & 0xF0u)
21	#else	21	#else
22	# define APIC_INTEGRATED(x) (1)	22	# define APIC_INTEGRATED(x) (1)
23	#endif	23	#endif
@@ -31,16 +31,16 @@
31	#define APIC_EIO_ACK 0x0	31	#define APIC_EIO_ACK 0x0
32	#define APIC_RRR 0xC0	32	#define APIC_RRR 0xC0
33	#define APIC_LDR 0xD0	33	#define APIC_LDR 0xD0
34	#define APIC_LDR_MASK (0xFFu<<24)	34	#define APIC_LDR_MASK (0xFFu << 24)
35	#define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFFu)	35	#define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu)
36	#define SET_APIC_LOGICAL_ID(x) (((x)<<24))	36	#define SET_APIC_LOGICAL_ID(x) (((x) << 24))
37	#define APIC_ALL_CPUS 0xFFu	37	#define APIC_ALL_CPUS 0xFFu
38	#define APIC_DFR 0xE0	38	#define APIC_DFR 0xE0
39	#define APIC_DFR_CLUSTER 0x0FFFFFFFul	39	#define APIC_DFR_CLUSTER 0x0FFFFFFFul
40	#define APIC_DFR_FLAT 0xFFFFFFFFul	40	#define APIC_DFR_FLAT 0xFFFFFFFFul
41	#define APIC_SPIV 0xF0	41	#define APIC_SPIV 0xF0
42	#define APIC_SPIV_FOCUS_DISABLED (1<<9)	42	#define APIC_SPIV_FOCUS_DISABLED (1 << 9)
43	#define APIC_SPIV_APIC_ENABLED (1<<8)	43	#define APIC_SPIV_APIC_ENABLED (1 << 8)
44	#define APIC_ISR 0x100	44	#define APIC_ISR 0x100
45	#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */	45	#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
46	#define APIC_TMR 0x180	46	#define APIC_TMR 0x180
@@ -76,27 +76,27 @@
76	#define APIC_DM_EXTINT 0x00700	76	#define APIC_DM_EXTINT 0x00700
77	#define APIC_VECTOR_MASK 0x000FF	77	#define APIC_VECTOR_MASK 0x000FF
78	#define APIC_ICR2 0x310	78	#define APIC_ICR2 0x310
79	#define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)	79	#define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
80	#define SET_APIC_DEST_FIELD(x) ((x)<<24)	80	#define SET_APIC_DEST_FIELD(x) ((x) << 24)
81	#define APIC_LVTT 0x320	81	#define APIC_LVTT 0x320
82	#define APIC_LVTTHMR 0x330	82	#define APIC_LVTTHMR 0x330
83	#define APIC_LVTPC 0x340	83	#define APIC_LVTPC 0x340
84	#define APIC_LVT0 0x350	84	#define APIC_LVT0 0x350
85	#define APIC_LVT_TIMER_BASE_MASK (0x3<<18)	85	#define APIC_LVT_TIMER_BASE_MASK (0x3 << 18)
86	#define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)	86	#define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
87	#define SET_APIC_TIMER_BASE(x) (((x)<<18))	87	#define SET_APIC_TIMER_BASE(x) (((x) << 18))
88	#define APIC_TIMER_BASE_CLKIN 0x0	88	#define APIC_TIMER_BASE_CLKIN 0x0
89	#define APIC_TIMER_BASE_TMBASE 0x1	89	#define APIC_TIMER_BASE_TMBASE 0x1
90	#define APIC_TIMER_BASE_DIV 0x2	90	#define APIC_TIMER_BASE_DIV 0x2
91	#define APIC_LVT_TIMER_PERIODIC (1<<17)	91	#define APIC_LVT_TIMER_PERIODIC (1 << 17)
92	#define APIC_LVT_MASKED (1<<16)	92	#define APIC_LVT_MASKED (1 << 16)
93	#define APIC_LVT_LEVEL_TRIGGER (1<<15)	93	#define APIC_LVT_LEVEL_TRIGGER (1 << 15)
94	#define APIC_LVT_REMOTE_IRR (1<<14)	94	#define APIC_LVT_REMOTE_IRR (1 << 14)
95	#define APIC_INPUT_POLARITY (1<<13)	95	#define APIC_INPUT_POLARITY (1 << 13)
96	#define APIC_SEND_PENDING (1<<12)	96	#define APIC_SEND_PENDING (1 << 12)
97	#define APIC_MODE_MASK 0x700	97	#define APIC_MODE_MASK 0x700
98	#define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)	98	#define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
99	#define SET_APIC_DELIVERY_MODE(x, y) (((x)&~0x700)\|((y)<<8))	99	#define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) \| ((y) << 8))
100	#define APIC_MODE_FIXED 0x0	100	#define APIC_MODE_FIXED 0x0
101	#define APIC_MODE_NMI 0x4	101	#define APIC_MODE_NMI 0x4
102	#define APIC_MODE_EXTINT 0x7	102	#define APIC_MODE_EXTINT 0x7
@@ -105,7 +105,7 @@
105	#define APIC_TMICT 0x380	105	#define APIC_TMICT 0x380
106	#define APIC_TMCCT 0x390	106	#define APIC_TMCCT 0x390
107	#define APIC_TDCR 0x3E0	107	#define APIC_TDCR 0x3E0
108	#define APIC_TDR_DIV_TMBASE (1<<2)	108	#define APIC_TDR_DIV_TMBASE (1 << 2)
109	#define APIC_TDR_DIV_1 0xB	109	#define APIC_TDR_DIV_1 0xB
110	#define APIC_TDR_DIV_2 0x0	110	#define APIC_TDR_DIV_2 0x0
111	#define APIC_TDR_DIV_4 0x1	111	#define APIC_TDR_DIV_4 0x1
@@ -115,14 +115,14 @@
115	#define APIC_TDR_DIV_64 0x9	115	#define APIC_TDR_DIV_64 0x9
116	#define APIC_TDR_DIV_128 0xA	116	#define APIC_TDR_DIV_128 0xA
117	#define APIC_EILVT0 0x500	117	#define APIC_EILVT0 0x500
118	#define APIC_EILVT_NR_AMD_K8 1 /* Number of extended interrupts */	118	#define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */
119	#define APIC_EILVT_NR_AMD_10H 4	119	#define APIC_EILVT_NR_AMD_10H 4
120	#define APIC_EILVT_LVTOFF(x) (((x)>>4)&0xF)	120	#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF)
121	#define APIC_EILVT_MSG_FIX 0x0	121	#define APIC_EILVT_MSG_FIX 0x0
122	#define APIC_EILVT_MSG_SMI 0x2	122	#define APIC_EILVT_MSG_SMI 0x2
123	#define APIC_EILVT_MSG_NMI 0x4	123	#define APIC_EILVT_MSG_NMI 0x4
124	#define APIC_EILVT_MSG_EXT 0x7	124	#define APIC_EILVT_MSG_EXT 0x7
125	#define APIC_EILVT_MASKED (1<<16)	125	#define APIC_EILVT_MASKED (1 << 16)
126	#define APIC_EILVT1 0x510	126	#define APIC_EILVT1 0x510
127	#define APIC_EILVT2 0x520	127	#define APIC_EILVT2 0x520
128	#define APIC_EILVT3 0x530	128	#define APIC_EILVT3 0x530