aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--sound/soc/codecs/88pm860x-codec.c7
-rw-r--r--sound/soc/codecs/Kconfig4
-rw-r--r--sound/soc/codecs/Makefile2
-rw-r--r--sound/soc/codecs/wm8350.c71
-rw-r--r--sound/soc/codecs/wm8903.c6
-rw-r--r--sound/soc/codecs/wm8962.c5
-rw-r--r--sound/soc/codecs/wm8994.c5
-rw-r--r--sound/soc/codecs/wm8995.c1818
-rw-r--r--sound/soc/codecs/wm8995.h8749
-rw-r--r--sound/soc/samsung/goni_wm8994.c2
10 files changed, 10649 insertions, 20 deletions
diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c
index 08e15dee9182..3e798a12ee3d 100644
--- a/sound/soc/codecs/88pm860x-codec.c
+++ b/sound/soc/codecs/88pm860x-codec.c
@@ -22,6 +22,7 @@
22#include <sound/tlv.h> 22#include <sound/tlv.h>
23#include <sound/initval.h> 23#include <sound/initval.h>
24#include <sound/jack.h> 24#include <sound/jack.h>
25#include <trace/events/asoc.h>
25 26
26#include "88pm860x-codec.h" 27#include "88pm860x-codec.h"
27 28
@@ -1262,6 +1263,12 @@ static irqreturn_t pm860x_codec_handler(int irq, void *data)
1262 mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt 1263 mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt
1263 | pm860x->det.hp_det; 1264 | pm860x->det.hp_det;
1264 1265
1266#ifndef CONFIG_SND_SOC_88PM860X
1267 if (status & (HEADSET_STATUS | MIC_STATUS | SHORT_HS1 | SHORT_HS2 |
1268 SHORT_LO1 | SHORT_LO2))
1269 trace_snd_soc_jack_irq(dev_name(pm860x->codec->dev));
1270#endif
1271
1265 if ((pm860x->det.hp_det & SND_JACK_HEADPHONE) 1272 if ((pm860x->det.hp_det & SND_JACK_HEADPHONE)
1266 && (status & HEADSET_STATUS)) 1273 && (status & HEADSET_STATUS))
1267 report |= SND_JACK_HEADPHONE; 1274 report |= SND_JACK_HEADPHONE;
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 0f33db2be25a..054191ed08ef 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -78,6 +78,7 @@ config SND_SOC_ALL_CODECS
78 select SND_SOC_WM8990 if I2C 78 select SND_SOC_WM8990 if I2C
79 select SND_SOC_WM8993 if I2C 79 select SND_SOC_WM8993 if I2C
80 select SND_SOC_WM8994 if MFD_WM8994 80 select SND_SOC_WM8994 if MFD_WM8994
81 select SND_SOC_WM8995 if SND_SOC_I2C_AND_SPI
81 select SND_SOC_WM9081 if I2C 82 select SND_SOC_WM9081 if I2C
82 select SND_SOC_WM9090 if I2C 83 select SND_SOC_WM9090 if I2C
83 select SND_SOC_WM9705 if SND_SOC_AC97_BUS 84 select SND_SOC_WM9705 if SND_SOC_AC97_BUS
@@ -306,6 +307,9 @@ config SND_SOC_WM8993
306config SND_SOC_WM8994 307config SND_SOC_WM8994
307 tristate 308 tristate
308 309
310config SND_SOC_WM8995
311 tristate
312
309config SND_SOC_WM9081 313config SND_SOC_WM9081
310 tristate 314 tristate
311 315
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 10e5e099334a..6a1e17bbbf83 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -62,6 +62,7 @@ snd-soc-wm8988-objs := wm8988.o
62snd-soc-wm8990-objs := wm8990.o 62snd-soc-wm8990-objs := wm8990.o
63snd-soc-wm8993-objs := wm8993.o 63snd-soc-wm8993-objs := wm8993.o
64snd-soc-wm8994-objs := wm8994.o wm8994-tables.o 64snd-soc-wm8994-objs := wm8994.o wm8994-tables.o
65snd-soc-wm8995-objs := wm8995.o
65snd-soc-wm9081-objs := wm9081.o 66snd-soc-wm9081-objs := wm9081.o
66snd-soc-wm9705-objs := wm9705.o 67snd-soc-wm9705-objs := wm9705.o
67snd-soc-wm9712-objs := wm9712.o 68snd-soc-wm9712-objs := wm9712.o
@@ -140,6 +141,7 @@ obj-$(CONFIG_SND_SOC_WM8988) += snd-soc-wm8988.o
140obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o 141obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o
141obj-$(CONFIG_SND_SOC_WM8993) += snd-soc-wm8993.o 142obj-$(CONFIG_SND_SOC_WM8993) += snd-soc-wm8993.o
142obj-$(CONFIG_SND_SOC_WM8994) += snd-soc-wm8994.o 143obj-$(CONFIG_SND_SOC_WM8994) += snd-soc-wm8994.o
144obj-$(CONFIG_SND_SOC_WM8995) += snd-soc-wm8995.o
143obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o 145obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o
144obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o 146obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o
145obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o 147obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o
diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c
index 07ba7e3f6a8c..db07137bf3b9 100644
--- a/sound/soc/codecs/wm8350.c
+++ b/sound/soc/codecs/wm8350.c
@@ -26,6 +26,7 @@
26#include <sound/soc.h> 26#include <sound/soc.h>
27#include <sound/initval.h> 27#include <sound/initval.h>
28#include <sound/tlv.h> 28#include <sound/tlv.h>
29#include <trace/events/asoc.h>
29 30
30#include "wm8350.h" 31#include "wm8350.h"
31 32
@@ -53,6 +54,7 @@ struct wm8350_output {
53 54
54struct wm8350_jack_data { 55struct wm8350_jack_data {
55 struct snd_soc_jack *jack; 56 struct snd_soc_jack *jack;
57 struct delayed_work work;
56 int report; 58 int report;
57 int short_report; 59 int short_report;
58}; 60};
@@ -1335,45 +1337,69 @@ static int wm8350_resume(struct snd_soc_codec *codec)
1335 return 0; 1337 return 0;
1336} 1338}
1337 1339
1338static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) 1340static void wm8350_hp_work(struct wm8350_data *priv,
1341 struct wm8350_jack_data *jack,
1342 u16 mask)
1339{ 1343{
1340 struct wm8350_data *priv = data;
1341 struct wm8350 *wm8350 = priv->codec.control_data; 1344 struct wm8350 *wm8350 = priv->codec.control_data;
1342 u16 reg; 1345 u16 reg;
1343 int report; 1346 int report;
1344 int mask; 1347
1348 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1349 if (reg & mask)
1350 report = jack->report;
1351 else
1352 report = 0;
1353
1354 snd_soc_jack_report(jack->jack, report, jack->report);
1355
1356}
1357
1358static void wm8350_hpl_work(struct work_struct *work)
1359{
1360 struct wm8350_data *priv =
1361 container_of(work, struct wm8350_data, hpl.work.work);
1362
1363 wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
1364}
1365
1366static void wm8350_hpr_work(struct work_struct *work)
1367{
1368 struct wm8350_data *priv =
1369 container_of(work, struct wm8350_data, hpr.work.work);
1370
1371 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1372}
1373
1374static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
1375{
1376 struct wm8350_data *priv = data;
1377 struct wm8350 *wm8350 = priv->codec.control_data;
1345 struct wm8350_jack_data *jack = NULL; 1378 struct wm8350_jack_data *jack = NULL;
1346 1379
1347 switch (irq - wm8350->irq_base) { 1380 switch (irq - wm8350->irq_base) {
1348 case WM8350_IRQ_CODEC_JCK_DET_L: 1381 case WM8350_IRQ_CODEC_JCK_DET_L:
1382#ifndef CONFIG_SND_SOC_WM8350_MODULE
1383 trace_snd_soc_jack_irq("WM8350 HPL");
1384#endif
1349 jack = &priv->hpl; 1385 jack = &priv->hpl;
1350 mask = WM8350_JACK_L_LVL;
1351 break; 1386 break;
1352 1387
1353 case WM8350_IRQ_CODEC_JCK_DET_R: 1388 case WM8350_IRQ_CODEC_JCK_DET_R:
1389#ifndef CONFIG_SND_SOC_WM8350_MODULE
1390 trace_snd_soc_jack_irq("WM8350 HPR");
1391#endif
1354 jack = &priv->hpr; 1392 jack = &priv->hpr;
1355 mask = WM8350_JACK_R_LVL;
1356 break; 1393 break;
1357 1394
1358 default: 1395 default:
1359 BUG(); 1396 BUG();
1360 } 1397 }
1361 1398
1362 if (!jack->jack) { 1399 if (device_may_wakeup(wm8350->dev))
1363 dev_warn(wm8350->dev, "Jack interrupt called with no jack\n"); 1400 pm_wakeup_event(wm8350->dev, 250);
1364 return IRQ_NONE;
1365 }
1366 1401
1367 /* Debounce */ 1402 schedule_delayed_work(&jack->work, 200);
1368 msleep(200);
1369
1370 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1371 if (reg & mask)
1372 report = jack->report;
1373 else
1374 report = 0;
1375
1376 snd_soc_jack_report(jack->jack, report, jack->report);
1377 1403
1378 return IRQ_HANDLED; 1404 return IRQ_HANDLED;
1379} 1405}
@@ -1437,6 +1463,8 @@ static irqreturn_t wm8350_mic_handler(int irq, void *data)
1437 u16 reg; 1463 u16 reg;
1438 int report = 0; 1464 int report = 0;
1439 1465
1466 trace_snd_soc_jack_irq("WM8350 mic");
1467
1440 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); 1468 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1441 if (reg & WM8350_JACK_MICSCD_LVL) 1469 if (reg & WM8350_JACK_MICSCD_LVL)
1442 report |= priv->mic.short_report; 1470 report |= priv->mic.short_report;
@@ -1552,6 +1580,8 @@ static int wm8350_codec_probe(struct snd_soc_codec *codec)
1552 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1580 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1553 1581
1554 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work); 1582 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work);
1583 INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
1584 INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
1555 1585
1556 /* Enable the codec */ 1586 /* Enable the codec */
1557 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1587 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
@@ -1641,6 +1671,9 @@ static int wm8350_codec_remove(struct snd_soc_codec *codec)
1641 priv->hpr.jack = NULL; 1671 priv->hpr.jack = NULL;
1642 priv->mic.jack = NULL; 1672 priv->mic.jack = NULL;
1643 1673
1674 cancel_delayed_work_sync(&priv->hpl.work);
1675 cancel_delayed_work_sync(&priv->hpr.work);
1676
1644 /* if there was any work waiting then we run it now and 1677 /* if there was any work waiting then we run it now and
1645 * wait for its completion */ 1678 * wait for its completion */
1646 flush_delayed_work_sync(&codec->dapm.delayed_work); 1679 flush_delayed_work_sync(&codec->dapm.delayed_work);
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index d015745a886b..02de5ae42d63 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -31,6 +31,7 @@
31#include <sound/soc.h> 31#include <sound/soc.h>
32#include <sound/initval.h> 32#include <sound/initval.h>
33#include <sound/wm8903.h> 33#include <sound/wm8903.h>
34#include <trace/events/asoc.h>
34 35
35#include "wm8903.h" 36#include "wm8903.h"
36 37
@@ -1533,6 +1534,11 @@ static irqreturn_t wm8903_irq(int irq, void *data)
1533 mic_report = wm8903->mic_last_report; 1534 mic_report = wm8903->mic_last_report;
1534 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1); 1535 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1535 1536
1537#ifndef CONFIG_SND_SOC_WM8903_MODULE
1538 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1539 trace_snd_soc_jack_irq(dev_name(codec->dev));
1540#endif
1541
1536 if (int_val & WM8903_MICSHRT_EINT) { 1542 if (int_val & WM8903_MICSHRT_EINT) {
1537 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol); 1543 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1538 1544
diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
index f0c9d2691842..b311b465c4d8 100644
--- a/sound/soc/codecs/wm8962.c
+++ b/sound/soc/codecs/wm8962.c
@@ -32,6 +32,7 @@
32#include <sound/initval.h> 32#include <sound/initval.h>
33#include <sound/tlv.h> 33#include <sound/tlv.h>
34#include <sound/wm8962.h> 34#include <sound/wm8962.h>
35#include <trace/events/asoc.h>
35 36
36#include "wm8962.h" 37#include "wm8962.h"
37 38
@@ -3353,6 +3354,10 @@ static irqreturn_t wm8962_irq(int irq, void *data)
3353 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { 3354 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3354 dev_dbg(codec->dev, "Microphone event detected\n"); 3355 dev_dbg(codec->dev, "Microphone event detected\n");
3355 3356
3357#ifndef CONFIG_SOUND_SOC_WM862_MODULE
3358 trace_snd_soc_jack_irq(dev_name(codec->dev));
3359#endif
3360
3356 pm_wakeup_event(codec->dev, 300); 3361 pm_wakeup_event(codec->dev, 300);
3357 3362
3358 schedule_delayed_work(&wm8962->mic_work, 3363 schedule_delayed_work(&wm8962->mic_work,
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index e1a775bd83fa..067a532bed15 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -28,6 +28,7 @@
28#include <sound/soc.h> 28#include <sound/soc.h>
29#include <sound/initval.h> 29#include <sound/initval.h>
30#include <sound/tlv.h> 30#include <sound/tlv.h>
31#include <trace/events/asoc.h>
31 32
32#include <linux/mfd/wm8994/core.h> 33#include <linux/mfd/wm8994/core.h>
33#include <linux/mfd/wm8994/registers.h> 34#include <linux/mfd/wm8994/registers.h>
@@ -2755,6 +2756,8 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data)
2755 int reg; 2756 int reg;
2756 int report; 2757 int report;
2757 2758
2759 trace_snd_soc_jack_irq(dev_name(codec->dev));
2760
2758 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); 2761 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2759 if (reg < 0) { 2762 if (reg < 0) {
2760 dev_err(codec->dev, "Failed to read microphone status: %d\n", 2763 dev_err(codec->dev, "Failed to read microphone status: %d\n",
@@ -2901,6 +2904,8 @@ static irqreturn_t wm8958_mic_irq(int irq, void *data)
2901 goto out; 2904 goto out;
2902 } 2905 }
2903 2906
2907 trace_snd_soc_jack_irq(dev_name(codec->dev));
2908
2904 if (wm8994->jack_cb) 2909 if (wm8994->jack_cb)
2905 wm8994->jack_cb(reg, wm8994->jack_cb_data); 2910 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2906 else 2911 else
diff --git a/sound/soc/codecs/wm8995.c b/sound/soc/codecs/wm8995.c
new file mode 100644
index 000000000000..3d2110c1d81f
--- /dev/null
+++ b/sound/soc/codecs/wm8995.c
@@ -0,0 +1,1818 @@
1/*
2 * wm8995.c -- WM8995 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * Based on wm8994.c and wm_hubs.c by Mark Brown
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/spi/spi.h>
22#include <linux/slab.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include "wm8995.h"
32
33static const u16 wm8995_reg_defs[WM8995_MAX_REGISTER + 1] __devinitconst = {
34 [0] = 0x8995, [5] = 0x0100, [16] = 0x000b, [17] = 0x000b,
35 [24] = 0x02c0, [25] = 0x02c0, [26] = 0x02c0, [27] = 0x02c0,
36 [28] = 0x000f, [32] = 0x0005, [33] = 0x0005, [40] = 0x0003,
37 [41] = 0x0013, [48] = 0x0004, [56] = 0x09f8, [64] = 0x1f25,
38 [69] = 0x0004, [82] = 0xaaaa, [84] = 0x2a2a, [146] = 0x0060,
39 [256] = 0x0002, [257] = 0x8004, [520] = 0x0010, [528] = 0x0083,
40 [529] = 0x0083, [548] = 0x0c80, [580] = 0x0c80, [768] = 0x4050,
41 [769] = 0x4000, [771] = 0x0040, [772] = 0x0040, [773] = 0x0040,
42 [774] = 0x0004, [775] = 0x0100, [784] = 0x4050, [785] = 0x4000,
43 [787] = 0x0040, [788] = 0x0040, [789] = 0x0040, [1024] = 0x00c0,
44 [1025] = 0x00c0, [1026] = 0x00c0, [1027] = 0x00c0, [1028] = 0x00c0,
45 [1029] = 0x00c0, [1030] = 0x00c0, [1031] = 0x00c0, [1056] = 0x0200,
46 [1057] = 0x0010, [1058] = 0x0200, [1059] = 0x0010, [1088] = 0x0098,
47 [1089] = 0x0845, [1104] = 0x0098, [1105] = 0x0845, [1152] = 0x6318,
48 [1153] = 0x6300, [1154] = 0x0fca, [1155] = 0x0400, [1156] = 0x00d8,
49 [1157] = 0x1eb5, [1158] = 0xf145, [1159] = 0x0b75, [1160] = 0x01c5,
50 [1161] = 0x1c58, [1162] = 0xf373, [1163] = 0x0a54, [1164] = 0x0558,
51 [1165] = 0x168e, [1166] = 0xf829, [1167] = 0x07ad, [1168] = 0x1103,
52 [1169] = 0x0564, [1170] = 0x0559, [1171] = 0x4000, [1184] = 0x6318,
53 [1185] = 0x6300, [1186] = 0x0fca, [1187] = 0x0400, [1188] = 0x00d8,
54 [1189] = 0x1eb5, [1190] = 0xf145, [1191] = 0x0b75, [1192] = 0x01c5,
55 [1193] = 0x1c58, [1194] = 0xf373, [1195] = 0x0a54, [1196] = 0x0558,
56 [1197] = 0x168e, [1198] = 0xf829, [1199] = 0x07ad, [1200] = 0x1103,
57 [1201] = 0x0564, [1202] = 0x0559, [1203] = 0x4000, [1280] = 0x00c0,
58 [1281] = 0x00c0, [1282] = 0x00c0, [1283] = 0x00c0, [1312] = 0x0200,
59 [1313] = 0x0010, [1344] = 0x0098, [1345] = 0x0845, [1408] = 0x6318,
60 [1409] = 0x6300, [1410] = 0x0fca, [1411] = 0x0400, [1412] = 0x00d8,
61 [1413] = 0x1eb5, [1414] = 0xf145, [1415] = 0x0b75, [1416] = 0x01c5,
62 [1417] = 0x1c58, [1418] = 0xf373, [1419] = 0x0a54, [1420] = 0x0558,
63 [1421] = 0x168e, [1422] = 0xf829, [1423] = 0x07ad, [1424] = 0x1103,
64 [1425] = 0x0564, [1426] = 0x0559, [1427] = 0x4000, [1568] = 0x0002,
65 [1792] = 0xa100, [1793] = 0xa101, [1794] = 0xa101, [1795] = 0xa101,
66 [1796] = 0xa101, [1797] = 0xa101, [1798] = 0xa101, [1799] = 0xa101,
67 [1800] = 0xa101, [1801] = 0xa101, [1802] = 0xa101, [1803] = 0xa101,
68 [1804] = 0xa101, [1805] = 0xa101, [1825] = 0x0055, [1848] = 0x3fff,
69 [1849] = 0x1fff, [2049] = 0x0001, [2050] = 0x0069, [2056] = 0x0002,
70 [2057] = 0x0003, [2058] = 0x0069, [12288] = 0x0001, [12289] = 0x0001,
71 [12291] = 0x0006, [12292] = 0x0040, [12293] = 0x0001, [12294] = 0x000f,
72 [12295] = 0x0006, [12296] = 0x0001, [12297] = 0x0003, [12298] = 0x0104,
73 [12300] = 0x0060, [12301] = 0x0011, [12302] = 0x0401, [12304] = 0x0050,
74 [12305] = 0x0003, [12306] = 0x0100, [12308] = 0x0051, [12309] = 0x0003,
75 [12310] = 0x0104, [12311] = 0x000a, [12312] = 0x0060, [12313] = 0x003b,
76 [12314] = 0x0502, [12315] = 0x0100, [12316] = 0x2fff, [12320] = 0x2fff,
77 [12324] = 0x2fff, [12328] = 0x2fff, [12332] = 0x2fff, [12336] = 0x2fff,
78 [12340] = 0x2fff, [12344] = 0x2fff, [12348] = 0x2fff, [12352] = 0x0001,
79 [12353] = 0x0001, [12355] = 0x0006, [12356] = 0x0040, [12357] = 0x0001,
80 [12358] = 0x000f, [12359] = 0x0006, [12360] = 0x0001, [12361] = 0x0003,
81 [12362] = 0x0104, [12364] = 0x0060, [12365] = 0x0011, [12366] = 0x0401,
82 [12368] = 0x0050, [12369] = 0x0003, [12370] = 0x0100, [12372] = 0x0060,
83 [12373] = 0x003b, [12374] = 0x0502, [12375] = 0x0100, [12376] = 0x2fff,
84 [12380] = 0x2fff, [12384] = 0x2fff, [12388] = 0x2fff, [12392] = 0x2fff,
85 [12396] = 0x2fff, [12400] = 0x2fff, [12404] = 0x2fff, [12408] = 0x2fff,
86 [12412] = 0x2fff, [12416] = 0x0001, [12417] = 0x0001, [12419] = 0x0006,
87 [12420] = 0x0040, [12421] = 0x0001, [12422] = 0x000f, [12423] = 0x0006,
88 [12424] = 0x0001, [12425] = 0x0003, [12426] = 0x0106, [12428] = 0x0061,
89 [12429] = 0x0011, [12430] = 0x0401, [12432] = 0x0050, [12433] = 0x0003,
90 [12434] = 0x0102, [12436] = 0x0051, [12437] = 0x0003, [12438] = 0x0106,
91 [12439] = 0x000a, [12440] = 0x0061, [12441] = 0x003b, [12442] = 0x0502,
92 [12443] = 0x0100, [12444] = 0x2fff, [12448] = 0x2fff, [12452] = 0x2fff,
93 [12456] = 0x2fff, [12460] = 0x2fff, [12464] = 0x2fff, [12468] = 0x2fff,
94 [12472] = 0x2fff, [12476] = 0x2fff, [12480] = 0x0001, [12481] = 0x0001,
95 [12483] = 0x0006, [12484] = 0x0040, [12485] = 0x0001, [12486] = 0x000f,
96 [12487] = 0x0006, [12488] = 0x0001, [12489] = 0x0003, [12490] = 0x0106,
97 [12492] = 0x0061, [12493] = 0x0011, [12494] = 0x0401, [12496] = 0x0050,
98 [12497] = 0x0003, [12498] = 0x0102, [12500] = 0x0061, [12501] = 0x003b,
99 [12502] = 0x0502, [12503] = 0x0100, [12504] = 0x2fff, [12508] = 0x2fff,
100 [12512] = 0x2fff, [12516] = 0x2fff, [12520] = 0x2fff, [12524] = 0x2fff,
101 [12528] = 0x2fff, [12532] = 0x2fff, [12536] = 0x2fff, [12540] = 0x2fff,
102 [12544] = 0x0060, [12546] = 0x0601, [12548] = 0x0050, [12550] = 0x0100,
103 [12552] = 0x0001, [12554] = 0x0104, [12555] = 0x0100, [12556] = 0x2fff,
104 [12560] = 0x2fff, [12564] = 0x2fff, [12568] = 0x2fff, [12572] = 0x2fff,
105 [12576] = 0x2fff, [12580] = 0x2fff, [12584] = 0x2fff, [12588] = 0x2fff,
106 [12592] = 0x2fff, [12596] = 0x2fff, [12600] = 0x2fff, [12604] = 0x2fff,
107 [12608] = 0x0061, [12610] = 0x0601, [12612] = 0x0050, [12614] = 0x0102,
108 [12616] = 0x0001, [12618] = 0x0106, [12619] = 0x0100, [12620] = 0x2fff,
109 [12624] = 0x2fff, [12628] = 0x2fff, [12632] = 0x2fff, [12636] = 0x2fff,
110 [12640] = 0x2fff, [12644] = 0x2fff, [12648] = 0x2fff, [12652] = 0x2fff,
111 [12656] = 0x2fff, [12660] = 0x2fff, [12664] = 0x2fff, [12668] = 0x2fff,
112 [12672] = 0x0060, [12674] = 0x0601, [12676] = 0x0061, [12678] = 0x0601,
113 [12680] = 0x0050, [12682] = 0x0300, [12684] = 0x0001, [12686] = 0x0304,
114 [12688] = 0x0040, [12690] = 0x000f, [12692] = 0x0001, [12695] = 0x0100
115};
116
117struct fll_config {
118 int src;
119 int in;
120 int out;
121};
122
123struct wm8995_priv {
124 enum snd_soc_control_type control_type;
125 int sysclk[2];
126 int mclk[2];
127 int aifclk[2];
128 struct fll_config fll[2], fll_suspend[2];
129};
130
131static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
132static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0);
133static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0);
134static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
135
136static const char *in1l_text[] = {
137 "Differential", "Single-ended IN1LN", "Single-ended IN1LP"
138};
139
140static const SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
141 2, in1l_text);
142
143static const char *in1r_text[] = {
144 "Differential", "Single-ended IN1RN", "Single-ended IN1RP"
145};
146
147static const SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
148 0, in1r_text);
149
150static const char *dmic_src_text[] = {
151 "DMICDAT1", "DMICDAT2", "DMICDAT3"
152};
153
154static const SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5,
155 8, dmic_src_text);
156static const SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5,
157 6, dmic_src_text);
158
159static const struct snd_kcontrol_new wm8995_snd_controls[] = {
160 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME,
161 WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
162 SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME,
163 WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1),
164
165 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME,
166 WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
167 SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME,
168 WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1),
169
170 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME,
171 WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
172 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME,
173 WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
174 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME,
175 WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
176
177 SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME,
178 WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv),
179
180 SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL,
181 4, 3, 0, in1l_boost_tlv),
182
183 SOC_ENUM("IN1L Mode", in1l_enum),
184 SOC_ENUM("IN1R Mode", in1r_enum),
185
186 SOC_ENUM("DMIC1 SRC", dmic_src1_enum),
187 SOC_ENUM("DMIC2 SRC", dmic_src2_enum),
188
189 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5,
190 24, 0, sidetone_tlv),
191 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5,
192 24, 0, sidetone_tlv),
193
194 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME,
195 WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
196 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME,
197 WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
198 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME,
199 WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv)
200};
201
202static void wm8995_update_class_w(struct snd_soc_codec *codec)
203{
204 int enable = 1;
205 int source = 0; /* GCC flow analysis can't track enable */
206 int reg, reg_r;
207
208 /* We also need the same setting for L/R and only one path */
209 reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING);
210 switch (reg) {
211 case WM8995_AIF2DACL_TO_DAC1L:
212 dev_dbg(codec->dev, "Class W source AIF2DAC\n");
213 source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT;
214 break;
215 case WM8995_AIF1DAC2L_TO_DAC1L:
216 dev_dbg(codec->dev, "Class W source AIF1DAC2\n");
217 source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT;
218 break;
219 case WM8995_AIF1DAC1L_TO_DAC1L:
220 dev_dbg(codec->dev, "Class W source AIF1DAC1\n");
221 source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT;
222 break;
223 default:
224 dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg);
225 enable = 0;
226 break;
227 }
228
229 reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING);
230 if (reg_r != reg) {
231 dev_dbg(codec->dev, "Left and right DAC mixers different\n");
232 enable = 0;
233 }
234
235 if (enable) {
236 dev_dbg(codec->dev, "Class W enabled\n");
237 snd_soc_update_bits(codec, WM8995_CLASS_W_1,
238 WM8995_CP_DYN_PWR_MASK |
239 WM8995_CP_DYN_SRC_SEL_MASK,
240 source | WM8995_CP_DYN_PWR);
241 } else {
242 dev_dbg(codec->dev, "Class W disabled\n");
243 snd_soc_update_bits(codec, WM8995_CLASS_W_1,
244 WM8995_CP_DYN_PWR_MASK, 0);
245 }
246}
247
248static int check_clk_sys(struct snd_soc_dapm_widget *source,
249 struct snd_soc_dapm_widget *sink)
250{
251 unsigned int reg;
252 const char *clk;
253
254 reg = snd_soc_read(source->codec, WM8995_CLOCKING_1);
255 /* Check what we're currently using for CLK_SYS */
256 if (reg & WM8995_SYSCLK_SRC)
257 clk = "AIF2CLK";
258 else
259 clk = "AIF1CLK";
260 return !strcmp(source->name, clk);
261}
262
263static int wm8995_put_class_w(struct snd_kcontrol *kcontrol,
264 struct snd_ctl_elem_value *ucontrol)
265{
266 struct snd_soc_dapm_widget *w;
267 struct snd_soc_codec *codec;
268 int ret;
269
270 w = snd_kcontrol_chip(kcontrol);
271 codec = w->codec;
272 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
273 wm8995_update_class_w(codec);
274 return ret;
275}
276
277static int hp_supply_event(struct snd_soc_dapm_widget *w,
278 struct snd_kcontrol *kcontrol, int event)
279{
280 struct snd_soc_codec *codec;
281 struct wm8995_priv *wm8995;
282
283 codec = w->codec;
284 wm8995 = snd_soc_codec_get_drvdata(codec);
285
286 switch (event) {
287 case SND_SOC_DAPM_PRE_PMU:
288 /* Enable the headphone amp */
289 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
290 WM8995_HPOUT1L_ENA_MASK |
291 WM8995_HPOUT1R_ENA_MASK,
292 WM8995_HPOUT1L_ENA |
293 WM8995_HPOUT1R_ENA);
294
295 /* Enable the second stage */
296 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
297 WM8995_HPOUT1L_DLY_MASK |
298 WM8995_HPOUT1R_DLY_MASK,
299 WM8995_HPOUT1L_DLY |
300 WM8995_HPOUT1R_DLY);
301 break;
302 case SND_SOC_DAPM_PRE_PMD:
303 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1,
304 WM8995_CP_ENA_MASK, 0);
305 break;
306 }
307
308 return 0;
309}
310
311static void dc_servo_cmd(struct snd_soc_codec *codec,
312 unsigned int reg, unsigned int val, unsigned int mask)
313{
314 int timeout = 10;
315
316 dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n",
317 __func__, reg, val, mask);
318
319 snd_soc_write(codec, reg, val);
320 while (timeout--) {
321 msleep(10);
322 val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0);
323 if ((val & mask) == mask)
324 return;
325 }
326
327 dev_err(codec->dev, "Timed out waiting for DC Servo\n");
328}
329
330static int hp_event(struct snd_soc_dapm_widget *w,
331 struct snd_kcontrol *kcontrol, int event)
332{
333 struct snd_soc_codec *codec;
334 unsigned int reg;
335
336 codec = w->codec;
337 reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1);
338
339 switch (event) {
340 case SND_SOC_DAPM_POST_PMU:
341 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1,
342 WM8995_CP_ENA_MASK, WM8995_CP_ENA);
343
344 msleep(5);
345
346 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
347 WM8995_HPOUT1L_ENA_MASK |
348 WM8995_HPOUT1R_ENA_MASK,
349 WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA);
350
351 udelay(20);
352
353 reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY;
354 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg);
355
356 snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 |
357 WM8995_DCS_ENA_CHAN_1);
358
359 dc_servo_cmd(codec, WM8995_DC_SERVO_2,
360 WM8995_DCS_TRIG_STARTUP_0 |
361 WM8995_DCS_TRIG_STARTUP_1,
362 WM8995_DCS_TRIG_DAC_WR_0 |
363 WM8995_DCS_TRIG_DAC_WR_1);
364
365 reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT |
366 WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT;
367 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg);
368
369 break;
370 case SND_SOC_DAPM_PRE_PMD:
371 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
372 WM8995_HPOUT1L_OUTP_MASK |
373 WM8995_HPOUT1R_OUTP_MASK |
374 WM8995_HPOUT1L_RMV_SHORT_MASK |
375 WM8995_HPOUT1R_RMV_SHORT_MASK, 0);
376
377 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
378 WM8995_HPOUT1L_DLY_MASK |
379 WM8995_HPOUT1R_DLY_MASK, 0);
380
381 snd_soc_write(codec, WM8995_DC_SERVO_1, 0);
382
383 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
384 WM8995_HPOUT1L_ENA_MASK |
385 WM8995_HPOUT1R_ENA_MASK,
386 0);
387 break;
388 }
389
390 return 0;
391}
392
393static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
394{
395 struct wm8995_priv *wm8995;
396 int rate;
397 int reg1 = 0;
398 int offset;
399
400 wm8995 = snd_soc_codec_get_drvdata(codec);
401
402 if (aif)
403 offset = 4;
404 else
405 offset = 0;
406
407 switch (wm8995->sysclk[aif]) {
408 case WM8995_SYSCLK_MCLK1:
409 rate = wm8995->mclk[0];
410 break;
411 case WM8995_SYSCLK_MCLK2:
412 reg1 |= 0x8;
413 rate = wm8995->mclk[1];
414 break;
415 case WM8995_SYSCLK_FLL1:
416 reg1 |= 0x10;
417 rate = wm8995->fll[0].out;
418 break;
419 case WM8995_SYSCLK_FLL2:
420 reg1 |= 0x18;
421 rate = wm8995->fll[1].out;
422 break;
423 default:
424 return -EINVAL;
425 }
426
427 if (rate >= 13500000) {
428 rate /= 2;
429 reg1 |= WM8995_AIF1CLK_DIV;
430
431 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
432 aif + 1, rate);
433 }
434
435 wm8995->aifclk[aif] = rate;
436
437 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset,
438 WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK,
439 reg1);
440 return 0;
441}
442
443static int configure_clock(struct snd_soc_codec *codec)
444{
445 struct wm8995_priv *wm8995;
446 int old, new;
447
448 wm8995 = snd_soc_codec_get_drvdata(codec);
449
450 /* Bring up the AIF clocks first */
451 configure_aif_clock(codec, 0);
452 configure_aif_clock(codec, 1);
453
454 /*
455 * Then switch CLK_SYS over to the higher of them; a change
456 * can only happen as a result of a clocking change which can
457 * only be made outside of DAPM so we can safely redo the
458 * clocking.
459 */
460
461 /* If they're equal it doesn't matter which is used */
462 if (wm8995->aifclk[0] == wm8995->aifclk[1])
463 return 0;
464
465 if (wm8995->aifclk[0] < wm8995->aifclk[1])
466 new = WM8995_SYSCLK_SRC;
467 else
468 new = 0;
469
470 old = snd_soc_read(codec, WM8995_CLOCKING_1) & WM8995_SYSCLK_SRC;
471
472 /* If there's no change then we're done. */
473 if (old == new)
474 return 0;
475
476 snd_soc_update_bits(codec, WM8995_CLOCKING_1,
477 WM8995_SYSCLK_SRC_MASK, new);
478
479 snd_soc_dapm_sync(&codec->dapm);
480
481 return 0;
482}
483
484static int clk_sys_event(struct snd_soc_dapm_widget *w,
485 struct snd_kcontrol *kcontrol, int event)
486{
487 struct snd_soc_codec *codec;
488
489 codec = w->codec;
490
491 switch (event) {
492 case SND_SOC_DAPM_PRE_PMU:
493 return configure_clock(codec);
494
495 case SND_SOC_DAPM_POST_PMD:
496 configure_clock(codec);
497 break;
498 }
499
500 return 0;
501}
502
503static const char *sidetone_text[] = {
504 "ADC/DMIC1", "DMIC2",
505};
506
507static const struct soc_enum sidetone1_enum =
508 SOC_ENUM_SINGLE(WM8995_SIDETONE, 0, 2, sidetone_text);
509
510static const struct snd_kcontrol_new sidetone1_mux =
511 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
512
513static const struct soc_enum sidetone2_enum =
514 SOC_ENUM_SINGLE(WM8995_SIDETONE, 1, 2, sidetone_text);
515
516static const struct snd_kcontrol_new sidetone2_mux =
517 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
518
519static const struct snd_kcontrol_new aif1adc1l_mix[] = {
520 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
521 1, 1, 0),
522 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
523 0, 1, 0),
524};
525
526static const struct snd_kcontrol_new aif1adc1r_mix[] = {
527 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
528 1, 1, 0),
529 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
530 0, 1, 0),
531};
532
533static const struct snd_kcontrol_new aif1adc2l_mix[] = {
534 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
535 1, 1, 0),
536 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
537 0, 1, 0),
538};
539
540static const struct snd_kcontrol_new aif1adc2r_mix[] = {
541 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
542 1, 1, 0),
543 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
544 0, 1, 0),
545};
546
547static const struct snd_kcontrol_new dac1l_mix[] = {
548 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
549 5, 1, 0),
550 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
551 4, 1, 0),
552 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
553 2, 1, 0),
554 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
555 1, 1, 0),
556 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
557 0, 1, 0),
558};
559
560static const struct snd_kcontrol_new dac1r_mix[] = {
561 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
562 5, 1, 0),
563 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
564 4, 1, 0),
565 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
566 2, 1, 0),
567 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
568 1, 1, 0),
569 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
570 0, 1, 0),
571};
572
573static const struct snd_kcontrol_new aif2dac2l_mix[] = {
574 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
575 5, 1, 0),
576 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
577 4, 1, 0),
578 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
579 2, 1, 0),
580 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
581 1, 1, 0),
582 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
583 0, 1, 0),
584};
585
586static const struct snd_kcontrol_new aif2dac2r_mix[] = {
587 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
588 5, 1, 0),
589 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
590 4, 1, 0),
591 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
592 2, 1, 0),
593 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
594 1, 1, 0),
595 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
596 0, 1, 0),
597};
598
599static const struct snd_kcontrol_new in1l_pga =
600 SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0);
601
602static const struct snd_kcontrol_new in1r_pga =
603 SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0);
604
605static const char *adc_mux_text[] = {
606 "ADC",
607 "DMIC",
608};
609
610static const struct soc_enum adc_enum =
611 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
612
613static const struct snd_kcontrol_new adcl_mux =
614 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
615
616static const struct snd_kcontrol_new adcr_mux =
617 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
618
619static const char *spk_src_text[] = {
620 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
621};
622
623static const SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1,
624 0, spk_src_text);
625static const SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1,
626 0, spk_src_text);
627static const SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2,
628 0, spk_src_text);
629static const SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2,
630 0, spk_src_text);
631
632static const struct snd_kcontrol_new spk1l_mux =
633 SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum);
634static const struct snd_kcontrol_new spk1r_mux =
635 SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum);
636static const struct snd_kcontrol_new spk2l_mux =
637 SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum);
638static const struct snd_kcontrol_new spk2r_mux =
639 SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum);
640
641static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = {
642 SND_SOC_DAPM_INPUT("DMIC1DAT"),
643 SND_SOC_DAPM_INPUT("DMIC2DAT"),
644
645 SND_SOC_DAPM_INPUT("IN1L"),
646 SND_SOC_DAPM_INPUT("IN1R"),
647
648 SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0,
649 &in1l_pga, 1),
650 SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0,
651 &in1r_pga, 1),
652
653 SND_SOC_DAPM_MICBIAS("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0),
654 SND_SOC_DAPM_MICBIAS("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0),
655
656 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0),
657 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0),
658 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0),
659 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0),
660 SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0),
661 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
662 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
663
664 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0,
665 WM8995_POWER_MANAGEMENT_3, 9, 0),
666 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0,
667 WM8995_POWER_MANAGEMENT_3, 8, 0),
668 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0,
669 SND_SOC_NOPM, 0, 0),
670 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
671 0, WM8995_POWER_MANAGEMENT_3, 11, 0),
672 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
673 0, WM8995_POWER_MANAGEMENT_3, 10, 0),
674
675 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0,
676 &adcl_mux),
677 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
678 &adcr_mux),
679
680 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0),
681 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0),
682 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0),
683 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0),
684
685 SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0),
686 SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0),
687
688 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
689 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
690 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
691 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
692 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
693 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
694 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
695 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
696
697 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
698 9, 0),
699 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
700 8, 0),
701 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM,
702 0, 0),
703
704 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
705 11, 0),
706 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
707 10, 0),
708
709 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
710 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
711 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
712 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
713
714 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0),
715 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0),
716 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0),
717 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0),
718
719 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix,
720 ARRAY_SIZE(dac1l_mix)),
721 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix,
722 ARRAY_SIZE(dac1r_mix)),
723
724 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
725 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
726
727 SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
728 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
729
730 SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0,
731 hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
732
733 SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1,
734 4, 0, &spk1l_mux),
735 SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1,
736 4, 0, &spk1r_mux),
737 SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2,
738 4, 0, &spk2l_mux),
739 SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2,
740 4, 0, &spk2r_mux),
741
742 SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
743
744 SND_SOC_DAPM_OUTPUT("HP1L"),
745 SND_SOC_DAPM_OUTPUT("HP1R"),
746 SND_SOC_DAPM_OUTPUT("SPK1L"),
747 SND_SOC_DAPM_OUTPUT("SPK1R"),
748 SND_SOC_DAPM_OUTPUT("SPK2L"),
749 SND_SOC_DAPM_OUTPUT("SPK2R")
750};
751
752static const struct snd_soc_dapm_route wm8995_intercon[] = {
753 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
754 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
755
756 { "DSP1CLK", NULL, "CLK_SYS" },
757 { "DSP2CLK", NULL, "CLK_SYS" },
758 { "SYSDSPCLK", NULL, "CLK_SYS" },
759
760 { "AIF1ADC1L", NULL, "AIF1CLK" },
761 { "AIF1ADC1L", NULL, "DSP1CLK" },
762 { "AIF1ADC1R", NULL, "AIF1CLK" },
763 { "AIF1ADC1R", NULL, "DSP1CLK" },
764 { "AIF1ADC1R", NULL, "SYSDSPCLK" },
765
766 { "AIF1ADC2L", NULL, "AIF1CLK" },
767 { "AIF1ADC2L", NULL, "DSP1CLK" },
768 { "AIF1ADC2R", NULL, "AIF1CLK" },
769 { "AIF1ADC2R", NULL, "DSP1CLK" },
770 { "AIF1ADC2R", NULL, "SYSDSPCLK" },
771
772 { "DMIC1L", NULL, "DMIC1DAT" },
773 { "DMIC1L", NULL, "CLK_SYS" },
774 { "DMIC1R", NULL, "DMIC1DAT" },
775 { "DMIC1R", NULL, "CLK_SYS" },
776 { "DMIC2L", NULL, "DMIC2DAT" },
777 { "DMIC2L", NULL, "CLK_SYS" },
778 { "DMIC2R", NULL, "DMIC2DAT" },
779 { "DMIC2R", NULL, "CLK_SYS" },
780
781 { "ADCL", NULL, "AIF1CLK" },
782 { "ADCL", NULL, "DSP1CLK" },
783 { "ADCL", NULL, "SYSDSPCLK" },
784
785 { "ADCR", NULL, "AIF1CLK" },
786 { "ADCR", NULL, "DSP1CLK" },
787 { "ADCR", NULL, "SYSDSPCLK" },
788
789 { "IN1L PGA", "IN1L Switch", "IN1L" },
790 { "IN1R PGA", "IN1R Switch", "IN1R" },
791 { "IN1L PGA", NULL, "LDO2" },
792 { "IN1R PGA", NULL, "LDO2" },
793
794 { "ADCL", NULL, "IN1L PGA" },
795 { "ADCR", NULL, "IN1R PGA" },
796
797 { "ADCL Mux", "ADC", "ADCL" },
798 { "ADCL Mux", "DMIC", "DMIC1L" },
799 { "ADCR Mux", "ADC", "ADCR" },
800 { "ADCR Mux", "DMIC", "DMIC1R" },
801
802 /* AIF1 outputs */
803 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
804 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
805
806 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
807 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
808
809 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
810 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
811
812 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
813 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
814
815 /* Sidetone */
816 { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" },
817 { "Left Sidetone", "DMIC2", "AIF1ADC2L" },
818 { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" },
819 { "Right Sidetone", "DMIC2", "AIF1ADC2R" },
820
821 { "AIF1DAC1L", NULL, "AIF1CLK" },
822 { "AIF1DAC1L", NULL, "DSP1CLK" },
823 { "AIF1DAC1R", NULL, "AIF1CLK" },
824 { "AIF1DAC1R", NULL, "DSP1CLK" },
825 { "AIF1DAC1R", NULL, "SYSDSPCLK" },
826
827 { "AIF1DAC2L", NULL, "AIF1CLK" },
828 { "AIF1DAC2L", NULL, "DSP1CLK" },
829 { "AIF1DAC2R", NULL, "AIF1CLK" },
830 { "AIF1DAC2R", NULL, "DSP1CLK" },
831 { "AIF1DAC2R", NULL, "SYSDSPCLK" },
832
833 { "DAC1L", NULL, "AIF1CLK" },
834 { "DAC1L", NULL, "DSP1CLK" },
835 { "DAC1L", NULL, "SYSDSPCLK" },
836
837 { "DAC1R", NULL, "AIF1CLK" },
838 { "DAC1R", NULL, "DSP1CLK" },
839 { "DAC1R", NULL, "SYSDSPCLK" },
840
841 { "AIF1DAC1L", NULL, "AIF1DACDAT" },
842 { "AIF1DAC1R", NULL, "AIF1DACDAT" },
843 { "AIF1DAC2L", NULL, "AIF1DACDAT" },
844 { "AIF1DAC2R", NULL, "AIF1DACDAT" },
845
846 /* DAC1 inputs */
847 { "DAC1L", NULL, "DAC1L Mixer" },
848 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
849 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
850 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
851 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
852
853 { "DAC1R", NULL, "DAC1R Mixer" },
854 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
855 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
856 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
857 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
858
859 /* DAC2/AIF2 outputs */
860 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
861 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
862 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
863
864 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
865 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
866 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
867
868 /* Output stages */
869 { "Headphone PGA", NULL, "DAC1L" },
870 { "Headphone PGA", NULL, "DAC1R" },
871
872 { "Headphone PGA", NULL, "DAC2L" },
873 { "Headphone PGA", NULL, "DAC2R" },
874
875 { "Headphone PGA", NULL, "Headphone Supply" },
876 { "Headphone PGA", NULL, "CLK_SYS" },
877 { "Headphone PGA", NULL, "LDO2" },
878
879 { "HP1L", NULL, "Headphone PGA" },
880 { "HP1R", NULL, "Headphone PGA" },
881
882 { "SPK1L Driver", "DAC1L", "DAC1L" },
883 { "SPK1L Driver", "DAC1R", "DAC1R" },
884 { "SPK1L Driver", "DAC2L", "DAC2L" },
885 { "SPK1L Driver", "DAC2R", "DAC2R" },
886 { "SPK1L Driver", NULL, "CLK_SYS" },
887
888 { "SPK1R Driver", "DAC1L", "DAC1L" },
889 { "SPK1R Driver", "DAC1R", "DAC1R" },
890 { "SPK1R Driver", "DAC2L", "DAC2L" },
891 { "SPK1R Driver", "DAC2R", "DAC2R" },
892 { "SPK1R Driver", NULL, "CLK_SYS" },
893
894 { "SPK2L Driver", "DAC1L", "DAC1L" },
895 { "SPK2L Driver", "DAC1R", "DAC1R" },
896 { "SPK2L Driver", "DAC2L", "DAC2L" },
897 { "SPK2L Driver", "DAC2R", "DAC2R" },
898 { "SPK2L Driver", NULL, "CLK_SYS" },
899
900 { "SPK2R Driver", "DAC1L", "DAC1L" },
901 { "SPK2R Driver", "DAC1R", "DAC1R" },
902 { "SPK2R Driver", "DAC2L", "DAC2L" },
903 { "SPK2R Driver", "DAC2R", "DAC2R" },
904 { "SPK2R Driver", NULL, "CLK_SYS" },
905
906 { "SPK1L", NULL, "SPK1L Driver" },
907 { "SPK1R", NULL, "SPK1R Driver" },
908 { "SPK2L", NULL, "SPK2L Driver" },
909 { "SPK2R", NULL, "SPK2R Driver" }
910};
911
912static int wm8995_volatile(unsigned int reg)
913{
914 /* out of bounds registers are generally considered
915 * volatile to support register banks that are partially
916 * owned by something else for e.g. a DSP
917 */
918 if (reg > WM8995_MAX_CACHED_REGISTER)
919 return 1;
920
921 switch (reg) {
922 case WM8995_SOFTWARE_RESET:
923 case WM8995_DC_SERVO_READBACK_0:
924 case WM8995_INTERRUPT_STATUS_1:
925 case WM8995_INTERRUPT_STATUS_2:
926 case WM8995_INTERRUPT_STATUS_1_MASK:
927 case WM8995_INTERRUPT_STATUS_2_MASK:
928 case WM8995_INTERRUPT_CONTROL:
929 case WM8995_ACCESSORY_DETECT_MODE1:
930 case WM8995_ACCESSORY_DETECT_MODE2:
931 case WM8995_HEADPHONE_DETECT1:
932 case WM8995_HEADPHONE_DETECT2:
933 return 1;
934 }
935
936 return 0;
937}
938
939static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute)
940{
941 struct snd_soc_codec *codec = dai->codec;
942 int mute_reg;
943
944 switch (dai->id) {
945 case 0:
946 mute_reg = WM8995_AIF1_DAC1_FILTERS_1;
947 break;
948 case 1:
949 mute_reg = WM8995_AIF2_DAC_FILTERS_1;
950 break;
951 default:
952 return -EINVAL;
953 }
954
955 snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK,
956 !!mute << WM8995_AIF1DAC1_MUTE_SHIFT);
957 return 0;
958}
959
960static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
961{
962 struct snd_soc_codec *codec;
963 int master;
964 int aif;
965
966 codec = dai->codec;
967
968 master = 0;
969 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
970 case SND_SOC_DAIFMT_CBS_CFS:
971 break;
972 case SND_SOC_DAIFMT_CBM_CFM:
973 master = WM8995_AIF1_MSTR;
974 break;
975 default:
976 dev_err(dai->dev, "Unknown master/slave configuration\n");
977 return -EINVAL;
978 }
979
980 aif = 0;
981 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
982 case SND_SOC_DAIFMT_DSP_B:
983 aif |= WM8995_AIF1_LRCLK_INV;
984 case SND_SOC_DAIFMT_DSP_A:
985 aif |= (0x3 << WM8995_AIF1_FMT_SHIFT);
986 break;
987 case SND_SOC_DAIFMT_I2S:
988 aif |= (0x2 << WM8995_AIF1_FMT_SHIFT);
989 break;
990 case SND_SOC_DAIFMT_RIGHT_J:
991 break;
992 case SND_SOC_DAIFMT_LEFT_J:
993 aif |= (0x1 << WM8995_AIF1_FMT_SHIFT);
994 break;
995 default:
996 dev_err(dai->dev, "Unknown dai format\n");
997 return -EINVAL;
998 }
999
1000 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1001 case SND_SOC_DAIFMT_DSP_A:
1002 case SND_SOC_DAIFMT_DSP_B:
1003 /* frame inversion not valid for DSP modes */
1004 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1005 case SND_SOC_DAIFMT_NB_NF:
1006 break;
1007 case SND_SOC_DAIFMT_IB_NF:
1008 aif |= WM8995_AIF1_BCLK_INV;
1009 break;
1010 default:
1011 return -EINVAL;
1012 }
1013 break;
1014
1015 case SND_SOC_DAIFMT_I2S:
1016 case SND_SOC_DAIFMT_RIGHT_J:
1017 case SND_SOC_DAIFMT_LEFT_J:
1018 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1019 case SND_SOC_DAIFMT_NB_NF:
1020 break;
1021 case SND_SOC_DAIFMT_IB_IF:
1022 aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV;
1023 break;
1024 case SND_SOC_DAIFMT_IB_NF:
1025 aif |= WM8995_AIF1_BCLK_INV;
1026 break;
1027 case SND_SOC_DAIFMT_NB_IF:
1028 aif |= WM8995_AIF1_LRCLK_INV;
1029 break;
1030 default:
1031 return -EINVAL;
1032 }
1033 break;
1034 default:
1035 return -EINVAL;
1036 }
1037
1038 snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1,
1039 WM8995_AIF1_BCLK_INV_MASK |
1040 WM8995_AIF1_LRCLK_INV_MASK |
1041 WM8995_AIF1_FMT_MASK, aif);
1042 snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE,
1043 WM8995_AIF1_MSTR_MASK, master);
1044 return 0;
1045}
1046
1047static const int srs[] = {
1048 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100,
1049 48000, 88200, 96000
1050};
1051
1052static const int fs_ratios[] = {
1053 -1 /* reserved */,
1054 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
1055};
1056
1057static const int bclk_divs[] = {
1058 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480
1059};
1060
1061static int wm8995_hw_params(struct snd_pcm_substream *substream,
1062 struct snd_pcm_hw_params *params,
1063 struct snd_soc_dai *dai)
1064{
1065 struct snd_soc_codec *codec;
1066 struct wm8995_priv *wm8995;
1067 int aif1_reg;
1068 int bclk_reg;
1069 int lrclk_reg;
1070 int rate_reg;
1071 int bclk_rate;
1072 int aif1;
1073 int lrclk, bclk;
1074 int i, rate_val, best, best_val, cur_val;
1075
1076 codec = dai->codec;
1077 wm8995 = snd_soc_codec_get_drvdata(codec);
1078
1079 switch (dai->id) {
1080 case 0:
1081 aif1_reg = WM8995_AIF1_CONTROL_1;
1082 bclk_reg = WM8995_AIF1_BCLK;
1083 rate_reg = WM8995_AIF1_RATE;
1084 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1085 wm8995->lrclk_shared[0] */) {
1086 lrclk_reg = WM8995_AIF1DAC_LRCLK;
1087 } else {
1088 lrclk_reg = WM8995_AIF1ADC_LRCLK;
1089 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
1090 }
1091 break;
1092 case 1:
1093 aif1_reg = WM8995_AIF2_CONTROL_1;
1094 bclk_reg = WM8995_AIF2_BCLK;
1095 rate_reg = WM8995_AIF2_RATE;
1096 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1097 wm8995->lrclk_shared[1] */) {
1098 lrclk_reg = WM8995_AIF2DAC_LRCLK;
1099 } else {
1100 lrclk_reg = WM8995_AIF2ADC_LRCLK;
1101 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
1102 }
1103 break;
1104 default:
1105 return -EINVAL;
1106 }
1107
1108 bclk_rate = snd_soc_params_to_bclk(params);
1109 if (bclk_rate < 0)
1110 return bclk_rate;
1111
1112 aif1 = 0;
1113 switch (params_format(params)) {
1114 case SNDRV_PCM_FORMAT_S16_LE:
1115 break;
1116 case SNDRV_PCM_FORMAT_S20_3LE:
1117 aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT);
1118 break;
1119 case SNDRV_PCM_FORMAT_S24_LE:
1120 aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT);
1121 break;
1122 case SNDRV_PCM_FORMAT_S32_LE:
1123 aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT);
1124 break;
1125 default:
1126 dev_err(dai->dev, "Unsupported word length %u\n",
1127 params_format(params));
1128 return -EINVAL;
1129 }
1130
1131 /* try to find a suitable sample rate */
1132 for (i = 0; i < ARRAY_SIZE(srs); ++i)
1133 if (srs[i] == params_rate(params))
1134 break;
1135 if (i == ARRAY_SIZE(srs)) {
1136 dev_err(dai->dev, "Sample rate %d is not supported\n",
1137 params_rate(params));
1138 return -EINVAL;
1139 }
1140 rate_val = i << WM8995_AIF1_SR_SHIFT;
1141
1142 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]);
1143 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
1144 dai->id + 1, wm8995->aifclk[dai->id], bclk_rate);
1145
1146 /* AIFCLK/fs ratio; look for a close match in either direction */
1147 best = 1;
1148 best_val = abs((fs_ratios[1] * params_rate(params))
1149 - wm8995->aifclk[dai->id]);
1150 for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) {
1151 cur_val = abs((fs_ratios[i] * params_rate(params))
1152 - wm8995->aifclk[dai->id]);
1153 if (cur_val >= best_val)
1154 continue;
1155 best = i;
1156 best_val = cur_val;
1157 }
1158 rate_val |= best;
1159
1160 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
1161 dai->id + 1, fs_ratios[best]);
1162
1163 /*
1164 * We may not get quite the right frequency if using
1165 * approximate clocks so look for the closest match that is
1166 * higher than the target (we need to ensure that there enough
1167 * BCLKs to clock out the samples).
1168 */
1169 best = 0;
1170 bclk = 0;
1171 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1172 cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate;
1173 if (cur_val < 0) /* BCLK table is sorted */
1174 break;
1175 best = i;
1176 }
1177 bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT;
1178
1179 bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best];
1180 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1181 bclk_divs[best], bclk_rate);
1182
1183 lrclk = bclk_rate / params_rate(params);
1184 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1185 lrclk, bclk_rate / lrclk);
1186
1187 snd_soc_update_bits(codec, aif1_reg,
1188 WM8995_AIF1_WL_MASK, aif1);
1189 snd_soc_update_bits(codec, bclk_reg,
1190 WM8995_AIF1_BCLK_DIV_MASK, bclk);
1191 snd_soc_update_bits(codec, lrclk_reg,
1192 WM8995_AIF1DAC_RATE_MASK, lrclk);
1193 snd_soc_update_bits(codec, rate_reg,
1194 WM8995_AIF1_SR_MASK |
1195 WM8995_AIF1CLK_RATE_MASK, rate_val);
1196 return 0;
1197}
1198
1199static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
1200{
1201 struct snd_soc_codec *codec = codec_dai->codec;
1202 int reg, val, mask;
1203
1204 switch (codec_dai->id) {
1205 case 0:
1206 reg = WM8995_AIF1_MASTER_SLAVE;
1207 mask = WM8995_AIF1_TRI;
1208 break;
1209 case 1:
1210 reg = WM8995_AIF2_MASTER_SLAVE;
1211 mask = WM8995_AIF2_TRI;
1212 break;
1213 case 2:
1214 reg = WM8995_POWER_MANAGEMENT_5;
1215 mask = WM8995_AIF3_TRI;
1216 break;
1217 default:
1218 return -EINVAL;
1219 }
1220
1221 if (tristate)
1222 val = mask;
1223 else
1224 val = 0;
1225
1226 return snd_soc_update_bits(codec, reg, mask, reg);
1227}
1228
1229/* The size in bits of the FLL divide multiplied by 10
1230 * to allow rounding later */
1231#define FIXED_FLL_SIZE ((1 << 16) * 10)
1232
1233struct fll_div {
1234 u16 outdiv;
1235 u16 n;
1236 u16 k;
1237 u16 clk_ref_div;
1238 u16 fll_fratio;
1239};
1240
1241static int wm8995_get_fll_config(struct fll_div *fll,
1242 int freq_in, int freq_out)
1243{
1244 u64 Kpart;
1245 unsigned int K, Ndiv, Nmod;
1246
1247 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1248
1249 /* Scale the input frequency down to <= 13.5MHz */
1250 fll->clk_ref_div = 0;
1251 while (freq_in > 13500000) {
1252 fll->clk_ref_div++;
1253 freq_in /= 2;
1254
1255 if (fll->clk_ref_div > 3)
1256 return -EINVAL;
1257 }
1258 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1259
1260 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1261 fll->outdiv = 3;
1262 while (freq_out * (fll->outdiv + 1) < 90000000) {
1263 fll->outdiv++;
1264 if (fll->outdiv > 63)
1265 return -EINVAL;
1266 }
1267 freq_out *= fll->outdiv + 1;
1268 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1269
1270 if (freq_in > 1000000) {
1271 fll->fll_fratio = 0;
1272 } else if (freq_in > 256000) {
1273 fll->fll_fratio = 1;
1274 freq_in *= 2;
1275 } else if (freq_in > 128000) {
1276 fll->fll_fratio = 2;
1277 freq_in *= 4;
1278 } else if (freq_in > 64000) {
1279 fll->fll_fratio = 3;
1280 freq_in *= 8;
1281 } else {
1282 fll->fll_fratio = 4;
1283 freq_in *= 16;
1284 }
1285 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1286
1287 /* Now, calculate N.K */
1288 Ndiv = freq_out / freq_in;
1289
1290 fll->n = Ndiv;
1291 Nmod = freq_out % freq_in;
1292 pr_debug("Nmod=%d\n", Nmod);
1293
1294 /* Calculate fractional part - scale up so we can round. */
1295 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1296
1297 do_div(Kpart, freq_in);
1298
1299 K = Kpart & 0xFFFFFFFF;
1300
1301 if ((K % 10) >= 5)
1302 K += 5;
1303
1304 /* Move down to proper range now rounding is done */
1305 fll->k = K / 10;
1306
1307 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1308
1309 return 0;
1310}
1311
1312static int wm8995_set_fll(struct snd_soc_dai *dai, int id,
1313 int src, unsigned int freq_in,
1314 unsigned int freq_out)
1315{
1316 struct snd_soc_codec *codec;
1317 struct wm8995_priv *wm8995;
1318 int reg_offset, ret;
1319 struct fll_div fll;
1320 u16 reg, aif1, aif2;
1321
1322 codec = dai->codec;
1323 wm8995 = snd_soc_codec_get_drvdata(codec);
1324
1325 aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1)
1326 & WM8995_AIF1CLK_ENA;
1327
1328 aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1)
1329 & WM8995_AIF2CLK_ENA;
1330
1331 switch (id) {
1332 case WM8995_FLL1:
1333 reg_offset = 0;
1334 id = 0;
1335 break;
1336 case WM8995_FLL2:
1337 reg_offset = 0x20;
1338 id = 1;
1339 break;
1340 default:
1341 return -EINVAL;
1342 }
1343
1344 switch (src) {
1345 case 0:
1346 /* Allow no source specification when stopping */
1347 if (freq_out)
1348 return -EINVAL;
1349 break;
1350 case WM8995_FLL_SRC_MCLK1:
1351 case WM8995_FLL_SRC_MCLK2:
1352 case WM8995_FLL_SRC_LRCLK:
1353 case WM8995_FLL_SRC_BCLK:
1354 break;
1355 default:
1356 return -EINVAL;
1357 }
1358
1359 /* Are we changing anything? */
1360 if (wm8995->fll[id].src == src &&
1361 wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out)
1362 return 0;
1363
1364 /* If we're stopping the FLL redo the old config - no
1365 * registers will actually be written but we avoid GCC flow
1366 * analysis bugs spewing warnings.
1367 */
1368 if (freq_out)
1369 ret = wm8995_get_fll_config(&fll, freq_in, freq_out);
1370 else
1371 ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in,
1372 wm8995->fll[id].out);
1373 if (ret < 0)
1374 return ret;
1375
1376 /* Gate the AIF clocks while we reclock */
1377 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1,
1378 WM8995_AIF1CLK_ENA_MASK, 0);
1379 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1,
1380 WM8995_AIF2CLK_ENA_MASK, 0);
1381
1382 /* We always need to disable the FLL while reconfiguring */
1383 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset,
1384 WM8995_FLL1_ENA_MASK, 0);
1385
1386 reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) |
1387 (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT);
1388 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset,
1389 WM8995_FLL1_OUTDIV_MASK |
1390 WM8995_FLL1_FRATIO_MASK, reg);
1391
1392 snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
1393
1394 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset,
1395 WM8995_FLL1_N_MASK,
1396 fll.n << WM8995_FLL1_N_SHIFT);
1397
1398 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset,
1399 WM8995_FLL1_REFCLK_DIV_MASK |
1400 WM8995_FLL1_REFCLK_SRC_MASK,
1401 (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) |
1402 (src - 1));
1403
1404 if (freq_out)
1405 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset,
1406 WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA);
1407
1408 wm8995->fll[id].in = freq_in;
1409 wm8995->fll[id].out = freq_out;
1410 wm8995->fll[id].src = src;
1411
1412 /* Enable any gated AIF clocks */
1413 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1,
1414 WM8995_AIF1CLK_ENA_MASK, aif1);
1415 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1,
1416 WM8995_AIF2CLK_ENA_MASK, aif2);
1417
1418 configure_clock(codec);
1419
1420 return 0;
1421}
1422
1423static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai,
1424 int clk_id, unsigned int freq, int dir)
1425{
1426 struct snd_soc_codec *codec;
1427 struct wm8995_priv *wm8995;
1428
1429 codec = dai->codec;
1430 wm8995 = snd_soc_codec_get_drvdata(codec);
1431
1432 switch (dai->id) {
1433 case 0:
1434 case 1:
1435 break;
1436 default:
1437 /* AIF3 shares clocking with AIF1/2 */
1438 return -EINVAL;
1439 }
1440
1441 switch (clk_id) {
1442 case WM8995_SYSCLK_MCLK1:
1443 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
1444 wm8995->mclk[0] = freq;
1445 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1446 dai->id + 1, freq);
1447 break;
1448 case WM8995_SYSCLK_MCLK2:
1449 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
1450 wm8995->mclk[1] = freq;
1451 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1452 dai->id + 1, freq);
1453 break;
1454 case WM8995_SYSCLK_FLL1:
1455 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1;
1456 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1);
1457 break;
1458 case WM8995_SYSCLK_FLL2:
1459 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2;
1460 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1);
1461 break;
1462 case WM8995_SYSCLK_OPCLK:
1463 default:
1464 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
1465 return -EINVAL;
1466 }
1467
1468 configure_clock(codec);
1469
1470 return 0;
1471}
1472
1473static int wm8995_set_bias_level(struct snd_soc_codec *codec,
1474 enum snd_soc_bias_level level)
1475{
1476 struct wm8995_priv *wm8995;
1477 int ret;
1478
1479 wm8995 = snd_soc_codec_get_drvdata(codec);
1480 switch (level) {
1481 case SND_SOC_BIAS_ON:
1482 case SND_SOC_BIAS_PREPARE:
1483 break;
1484 case SND_SOC_BIAS_STANDBY:
1485 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1486 ret = snd_soc_cache_sync(codec);
1487 if (ret) {
1488 dev_err(codec->dev,
1489 "Failed to sync cache: %d\n", ret);
1490 return ret;
1491 }
1492
1493 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
1494 WM8995_BG_ENA_MASK, WM8995_BG_ENA);
1495
1496 }
1497 break;
1498 case SND_SOC_BIAS_OFF:
1499 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
1500 WM8995_BG_ENA_MASK, 0);
1501 break;
1502 }
1503
1504 codec->dapm.bias_level = level;
1505 return 0;
1506}
1507
1508#ifdef CONFIG_PM
1509static int wm8995_suspend(struct snd_soc_codec *codec, pm_message_t state)
1510{
1511 wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF);
1512 return 0;
1513}
1514
1515static int wm8995_resume(struct snd_soc_codec *codec)
1516{
1517 wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1518 return 0;
1519}
1520#else
1521#define wm8995_suspend NULL
1522#define wm8995_resume NULL
1523#endif
1524
1525static int wm8995_remove(struct snd_soc_codec *codec)
1526{
1527 struct wm8995_priv *wm8995;
1528 struct i2c_client *i2c;
1529
1530 i2c = container_of(codec->dev, struct i2c_client, dev);
1531 wm8995 = snd_soc_codec_get_drvdata(codec);
1532 wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF);
1533 return 0;
1534}
1535
1536static int wm8995_probe(struct snd_soc_codec *codec)
1537{
1538 struct wm8995_priv *wm8995;
1539 int ret;
1540
1541 codec->dapm.idle_bias_off = 1;
1542 wm8995 = snd_soc_codec_get_drvdata(codec);
1543
1544 ret = snd_soc_codec_set_cache_io(codec, 16, 16, wm8995->control_type);
1545 if (ret < 0) {
1546 dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
1547 return ret;
1548 }
1549
1550 ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET);
1551 if (ret < 0) {
1552 dev_err(codec->dev, "Failed to read device ID: %d\n", ret);
1553 return ret;
1554 }
1555
1556 if (ret != 0x8995) {
1557 dev_err(codec->dev, "Invalid device ID: %#x\n", ret);
1558 return -EINVAL;
1559 }
1560
1561 ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0);
1562 if (ret < 0) {
1563 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1564 return ret;
1565 }
1566
1567 wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1568
1569 /* Latch volume updates (right only; we always do left then right). */
1570 snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME,
1571 WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU);
1572 snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME,
1573 WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU);
1574 snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME,
1575 WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU);
1576 snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME,
1577 WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU);
1578 snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME,
1579 WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU);
1580 snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME,
1581 WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU);
1582 snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME,
1583 WM8995_DAC1_VU_MASK, WM8995_DAC1_VU);
1584 snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME,
1585 WM8995_DAC2_VU_MASK, WM8995_DAC2_VU);
1586 snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME,
1587 WM8995_IN1_VU_MASK, WM8995_IN1_VU);
1588
1589 wm8995_update_class_w(codec);
1590
1591 snd_soc_add_controls(codec, wm8995_snd_controls,
1592 ARRAY_SIZE(wm8995_snd_controls));
1593 snd_soc_dapm_new_controls(&codec->dapm, wm8995_dapm_widgets,
1594 ARRAY_SIZE(wm8995_dapm_widgets));
1595 snd_soc_dapm_add_routes(&codec->dapm, wm8995_intercon,
1596 ARRAY_SIZE(wm8995_intercon));
1597
1598 return 0;
1599}
1600
1601#define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1602 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1603
1604static struct snd_soc_dai_ops wm8995_aif1_dai_ops = {
1605 .set_sysclk = wm8995_set_dai_sysclk,
1606 .set_fmt = wm8995_set_dai_fmt,
1607 .hw_params = wm8995_hw_params,
1608 .digital_mute = wm8995_aif_mute,
1609 .set_pll = wm8995_set_fll,
1610 .set_tristate = wm8995_set_tristate,
1611};
1612
1613static struct snd_soc_dai_ops wm8995_aif2_dai_ops = {
1614 .set_sysclk = wm8995_set_dai_sysclk,
1615 .set_fmt = wm8995_set_dai_fmt,
1616 .hw_params = wm8995_hw_params,
1617 .digital_mute = wm8995_aif_mute,
1618 .set_pll = wm8995_set_fll,
1619 .set_tristate = wm8995_set_tristate,
1620};
1621
1622static struct snd_soc_dai_ops wm8995_aif3_dai_ops = {
1623 .set_tristate = wm8995_set_tristate,
1624};
1625
1626static struct snd_soc_dai_driver wm8995_dai[] = {
1627 {
1628 .name = "wm8995-aif1",
1629 .playback = {
1630 .stream_name = "AIF1 Playback",
1631 .channels_min = 2,
1632 .channels_max = 2,
1633 .rates = SNDRV_PCM_RATE_8000_96000,
1634 .formats = WM8995_FORMATS
1635 },
1636 .capture = {
1637 .stream_name = "AIF1 Capture",
1638 .channels_min = 2,
1639 .channels_max = 2,
1640 .rates = SNDRV_PCM_RATE_8000_48000,
1641 .formats = WM8995_FORMATS
1642 },
1643 .ops = &wm8995_aif1_dai_ops
1644 },
1645 {
1646 .name = "wm8995-aif2",
1647 .playback = {
1648 .stream_name = "AIF2 Playback",
1649 .channels_min = 2,
1650 .channels_max = 2,
1651 .rates = SNDRV_PCM_RATE_8000_96000,
1652 .formats = WM8995_FORMATS
1653 },
1654 .capture = {
1655 .stream_name = "AIF2 Capture",
1656 .channels_min = 2,
1657 .channels_max = 2,
1658 .rates = SNDRV_PCM_RATE_8000_48000,
1659 .formats = WM8995_FORMATS
1660 },
1661 .ops = &wm8995_aif2_dai_ops
1662 },
1663 {
1664 .name = "wm8995-aif3",
1665 .playback = {
1666 .stream_name = "AIF3 Playback",
1667 .channels_min = 2,
1668 .channels_max = 2,
1669 .rates = SNDRV_PCM_RATE_8000_96000,
1670 .formats = WM8995_FORMATS
1671 },
1672 .capture = {
1673 .stream_name = "AIF3 Capture",
1674 .channels_min = 2,
1675 .channels_max = 2,
1676 .rates = SNDRV_PCM_RATE_8000_48000,
1677 .formats = WM8995_FORMATS
1678 },
1679 .ops = &wm8995_aif3_dai_ops
1680 }
1681};
1682
1683static struct snd_soc_codec_driver soc_codec_dev_wm8995 = {
1684 .probe = wm8995_probe,
1685 .remove = wm8995_remove,
1686 .suspend = wm8995_suspend,
1687 .resume = wm8995_resume,
1688 .set_bias_level = wm8995_set_bias_level,
1689 .reg_cache_size = ARRAY_SIZE(wm8995_reg_defs),
1690 .reg_word_size = sizeof(u16),
1691 .reg_cache_default = wm8995_reg_defs,
1692 .volatile_register = wm8995_volatile,
1693 .compress_type = SND_SOC_RBTREE_COMPRESSION
1694};
1695
1696#if defined(CONFIG_SPI_MASTER)
1697static int __devinit wm8995_spi_probe(struct spi_device *spi)
1698{
1699 struct wm8995_priv *wm8995;
1700 int ret;
1701
1702 wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL);
1703 if (!wm8995)
1704 return -ENOMEM;
1705
1706 wm8995->control_type = SND_SOC_SPI;
1707 spi_set_drvdata(spi, wm8995);
1708
1709 ret = snd_soc_register_codec(&spi->dev,
1710 &soc_codec_dev_wm8995, wm8995_dai,
1711 ARRAY_SIZE(wm8995_dai));
1712 if (ret < 0)
1713 kfree(wm8995);
1714 return ret;
1715}
1716
1717static int __devexit wm8995_spi_remove(struct spi_device *spi)
1718{
1719 snd_soc_unregister_codec(&spi->dev);
1720 kfree(spi_get_drvdata(spi));
1721 return 0;
1722}
1723
1724static struct spi_driver wm8995_spi_driver = {
1725 .driver = {
1726 .name = "wm8995",
1727 .owner = THIS_MODULE,
1728 },
1729 .probe = wm8995_spi_probe,
1730 .remove = __devexit_p(wm8995_spi_remove)
1731};
1732#endif
1733
1734#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1735static __devinit int wm8995_i2c_probe(struct i2c_client *i2c,
1736 const struct i2c_device_id *id)
1737{
1738 struct wm8995_priv *wm8995;
1739 int ret;
1740
1741 wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL);
1742 if (!wm8995)
1743 return -ENOMEM;
1744
1745 wm8995->control_type = SND_SOC_I2C;
1746 i2c_set_clientdata(i2c, wm8995);
1747
1748 ret = snd_soc_register_codec(&i2c->dev,
1749 &soc_codec_dev_wm8995, wm8995_dai,
1750 ARRAY_SIZE(wm8995_dai));
1751 if (ret < 0)
1752 kfree(wm8995);
1753 return ret;
1754}
1755
1756static __devexit int wm8995_i2c_remove(struct i2c_client *client)
1757{
1758 snd_soc_unregister_codec(&client->dev);
1759 kfree(i2c_get_clientdata(client));
1760 return 0;
1761}
1762
1763static const struct i2c_device_id wm8995_i2c_id[] = {
1764 {"wm8995", 0},
1765 {}
1766};
1767
1768MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id);
1769
1770static struct i2c_driver wm8995_i2c_driver = {
1771 .driver = {
1772 .name = "wm8995",
1773 .owner = THIS_MODULE,
1774 },
1775 .probe = wm8995_i2c_probe,
1776 .remove = __devexit_p(wm8995_i2c_remove),
1777 .id_table = wm8995_i2c_id
1778};
1779#endif
1780
1781static int __init wm8995_modinit(void)
1782{
1783 int ret = 0;
1784
1785#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1786 ret = i2c_add_driver(&wm8995_i2c_driver);
1787 if (ret) {
1788 printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n",
1789 ret);
1790 }
1791#endif
1792#if defined(CONFIG_SPI_MASTER)
1793 ret = spi_register_driver(&wm8995_spi_driver);
1794 if (ret) {
1795 printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n",
1796 ret);
1797 }
1798#endif
1799 return ret;
1800}
1801
1802module_init(wm8995_modinit);
1803
1804static void __exit wm8995_exit(void)
1805{
1806#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1807 i2c_del_driver(&wm8995_i2c_driver);
1808#endif
1809#if defined(CONFIG_SPI_MASTER)
1810 spi_unregister_driver(&wm8995_spi_driver);
1811#endif
1812}
1813
1814module_exit(wm8995_exit);
1815
1816MODULE_DESCRIPTION("ASoC WM8995 driver");
1817MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1818MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8995.h b/sound/soc/codecs/wm8995.h
new file mode 100644
index 000000000000..6409e5a6b574
--- /dev/null
+++ b/sound/soc/codecs/wm8995.h
@@ -0,0 +1,8749 @@
1/*
2 * wm8995.h -- WM8995 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _WM8995_H
14#define _WM8995_H
15
16#include <asm/types.h>
17
18/*
19 * Register values.
20 */
21#define WM8995_SOFTWARE_RESET 0x00
22#define WM8995_POWER_MANAGEMENT_1 0x01
23#define WM8995_POWER_MANAGEMENT_2 0x02
24#define WM8995_POWER_MANAGEMENT_3 0x03
25#define WM8995_POWER_MANAGEMENT_4 0x04
26#define WM8995_POWER_MANAGEMENT_5 0x05
27#define WM8995_LEFT_LINE_INPUT_1_VOLUME 0x10
28#define WM8995_RIGHT_LINE_INPUT_1_VOLUME 0x11
29#define WM8995_LEFT_LINE_INPUT_CONTROL 0x12
30#define WM8995_DAC1_LEFT_VOLUME 0x18
31#define WM8995_DAC1_RIGHT_VOLUME 0x19
32#define WM8995_DAC2_LEFT_VOLUME 0x1A
33#define WM8995_DAC2_RIGHT_VOLUME 0x1B
34#define WM8995_OUTPUT_VOLUME_ZC_1 0x1C
35#define WM8995_MICBIAS_1 0x20
36#define WM8995_MICBIAS_2 0x21
37#define WM8995_LDO_1 0x28
38#define WM8995_LDO_2 0x29
39#define WM8995_ACCESSORY_DETECT_MODE1 0x30
40#define WM8995_ACCESSORY_DETECT_MODE2 0x31
41#define WM8995_HEADPHONE_DETECT1 0x34
42#define WM8995_HEADPHONE_DETECT2 0x35
43#define WM8995_MIC_DETECT_1 0x38
44#define WM8995_MIC_DETECT_2 0x39
45#define WM8995_CHARGE_PUMP_1 0x40
46#define WM8995_CLASS_W_1 0x45
47#define WM8995_DC_SERVO_1 0x50
48#define WM8995_DC_SERVO_2 0x51
49#define WM8995_DC_SERVO_3 0x52
50#define WM8995_DC_SERVO_5 0x54
51#define WM8995_DC_SERVO_6 0x55
52#define WM8995_DC_SERVO_7 0x56
53#define WM8995_DC_SERVO_READBACK_0 0x57
54#define WM8995_ANALOGUE_HP_1 0x60
55#define WM8995_ANALOGUE_HP_2 0x61
56#define WM8995_CHIP_REVISION 0x100
57#define WM8995_CONTROL_INTERFACE_1 0x101
58#define WM8995_CONTROL_INTERFACE_2 0x102
59#define WM8995_WRITE_SEQUENCER_CTRL_1 0x110
60#define WM8995_WRITE_SEQUENCER_CTRL_2 0x111
61#define WM8995_AIF1_CLOCKING_1 0x200
62#define WM8995_AIF1_CLOCKING_2 0x201
63#define WM8995_AIF2_CLOCKING_1 0x204
64#define WM8995_AIF2_CLOCKING_2 0x205
65#define WM8995_CLOCKING_1 0x208
66#define WM8995_CLOCKING_2 0x209
67#define WM8995_AIF1_RATE 0x210
68#define WM8995_AIF2_RATE 0x211
69#define WM8995_RATE_STATUS 0x212
70#define WM8995_FLL1_CONTROL_1 0x220
71#define WM8995_FLL1_CONTROL_2 0x221
72#define WM8995_FLL1_CONTROL_3 0x222
73#define WM8995_FLL1_CONTROL_4 0x223
74#define WM8995_FLL1_CONTROL_5 0x224
75#define WM8995_FLL2_CONTROL_1 0x240
76#define WM8995_FLL2_CONTROL_2 0x241
77#define WM8995_FLL2_CONTROL_3 0x242
78#define WM8995_FLL2_CONTROL_4 0x243
79#define WM8995_FLL2_CONTROL_5 0x244
80#define WM8995_AIF1_CONTROL_1 0x300
81#define WM8995_AIF1_CONTROL_2 0x301
82#define WM8995_AIF1_MASTER_SLAVE 0x302
83#define WM8995_AIF1_BCLK 0x303
84#define WM8995_AIF1ADC_LRCLK 0x304
85#define WM8995_AIF1DAC_LRCLK 0x305
86#define WM8995_AIF1DAC_DATA 0x306
87#define WM8995_AIF1ADC_DATA 0x307
88#define WM8995_AIF2_CONTROL_1 0x310
89#define WM8995_AIF2_CONTROL_2 0x311
90#define WM8995_AIF2_MASTER_SLAVE 0x312
91#define WM8995_AIF2_BCLK 0x313
92#define WM8995_AIF2ADC_LRCLK 0x314
93#define WM8995_AIF2DAC_LRCLK 0x315
94#define WM8995_AIF2DAC_DATA 0x316
95#define WM8995_AIF2ADC_DATA 0x317
96#define WM8995_AIF1_ADC1_LEFT_VOLUME 0x400
97#define WM8995_AIF1_ADC1_RIGHT_VOLUME 0x401
98#define WM8995_AIF1_DAC1_LEFT_VOLUME 0x402
99#define WM8995_AIF1_DAC1_RIGHT_VOLUME 0x403
100#define WM8995_AIF1_ADC2_LEFT_VOLUME 0x404
101#define WM8995_AIF1_ADC2_RIGHT_VOLUME 0x405
102#define WM8995_AIF1_DAC2_LEFT_VOLUME 0x406
103#define WM8995_AIF1_DAC2_RIGHT_VOLUME 0x407
104#define WM8995_AIF1_ADC1_FILTERS 0x410
105#define WM8995_AIF1_ADC2_FILTERS 0x411
106#define WM8995_AIF1_DAC1_FILTERS_1 0x420
107#define WM8995_AIF1_DAC1_FILTERS_2 0x421
108#define WM8995_AIF1_DAC2_FILTERS_1 0x422
109#define WM8995_AIF1_DAC2_FILTERS_2 0x423
110#define WM8995_AIF1_DRC1_1 0x440
111#define WM8995_AIF1_DRC1_2 0x441
112#define WM8995_AIF1_DRC1_3 0x442
113#define WM8995_AIF1_DRC1_4 0x443
114#define WM8995_AIF1_DRC1_5 0x444
115#define WM8995_AIF1_DRC2_1 0x450
116#define WM8995_AIF1_DRC2_2 0x451
117#define WM8995_AIF1_DRC2_3 0x452
118#define WM8995_AIF1_DRC2_4 0x453
119#define WM8995_AIF1_DRC2_5 0x454
120#define WM8995_AIF1_DAC1_EQ_GAINS_1 0x480
121#define WM8995_AIF1_DAC1_EQ_GAINS_2 0x481
122#define WM8995_AIF1_DAC1_EQ_BAND_1_A 0x482
123#define WM8995_AIF1_DAC1_EQ_BAND_1_B 0x483
124#define WM8995_AIF1_DAC1_EQ_BAND_1_PG 0x484
125#define WM8995_AIF1_DAC1_EQ_BAND_2_A 0x485
126#define WM8995_AIF1_DAC1_EQ_BAND_2_B 0x486
127#define WM8995_AIF1_DAC1_EQ_BAND_2_C 0x487
128#define WM8995_AIF1_DAC1_EQ_BAND_2_PG 0x488
129#define WM8995_AIF1_DAC1_EQ_BAND_3_A 0x489
130#define WM8995_AIF1_DAC1_EQ_BAND_3_B 0x48A
131#define WM8995_AIF1_DAC1_EQ_BAND_3_C 0x48B
132#define WM8995_AIF1_DAC1_EQ_BAND_3_PG 0x48C
133#define WM8995_AIF1_DAC1_EQ_BAND_4_A 0x48D
134#define WM8995_AIF1_DAC1_EQ_BAND_4_B 0x48E
135#define WM8995_AIF1_DAC1_EQ_BAND_4_C 0x48F
136#define WM8995_AIF1_DAC1_EQ_BAND_4_PG 0x490
137#define WM8995_AIF1_DAC1_EQ_BAND_5_A 0x491
138#define WM8995_AIF1_DAC1_EQ_BAND_5_B 0x492
139#define WM8995_AIF1_DAC1_EQ_BAND_5_PG 0x493
140#define WM8995_AIF1_DAC2_EQ_GAINS_1 0x4A0
141#define WM8995_AIF1_DAC2_EQ_GAINS_2 0x4A1
142#define WM8995_AIF1_DAC2_EQ_BAND_1_A 0x4A2
143#define WM8995_AIF1_DAC2_EQ_BAND_1_B 0x4A3
144#define WM8995_AIF1_DAC2_EQ_BAND_1_PG 0x4A4
145#define WM8995_AIF1_DAC2_EQ_BAND_2_A 0x4A5
146#define WM8995_AIF1_DAC2_EQ_BAND_2_B 0x4A6
147#define WM8995_AIF1_DAC2_EQ_BAND_2_C 0x4A7
148#define WM8995_AIF1_DAC2_EQ_BAND_2_PG 0x4A8
149#define WM8995_AIF1_DAC2_EQ_BAND_3_A 0x4A9
150#define WM8995_AIF1_DAC2_EQ_BAND_3_B 0x4AA
151#define WM8995_AIF1_DAC2_EQ_BAND_3_C 0x4AB
152#define WM8995_AIF1_DAC2_EQ_BAND_3_PG 0x4AC
153#define WM8995_AIF1_DAC2_EQ_BAND_4_A 0x4AD
154#define WM8995_AIF1_DAC2_EQ_BAND_4_B 0x4AE
155#define WM8995_AIF1_DAC2_EQ_BAND_4_C 0x4AF
156#define WM8995_AIF1_DAC2_EQ_BAND_4_PG 0x4B0
157#define WM8995_AIF1_DAC2_EQ_BAND_5_A 0x4B1
158#define WM8995_AIF1_DAC2_EQ_BAND_5_B 0x4B2
159#define WM8995_AIF1_DAC2_EQ_BAND_5_PG 0x4B3
160#define WM8995_AIF2_ADC_LEFT_VOLUME 0x500
161#define WM8995_AIF2_ADC_RIGHT_VOLUME 0x501
162#define WM8995_AIF2_DAC_LEFT_VOLUME 0x502
163#define WM8995_AIF2_DAC_RIGHT_VOLUME 0x503
164#define WM8995_AIF2_ADC_FILTERS 0x510
165#define WM8995_AIF2_DAC_FILTERS_1 0x520
166#define WM8995_AIF2_DAC_FILTERS_2 0x521
167#define WM8995_AIF2_DRC_1 0x540
168#define WM8995_AIF2_DRC_2 0x541
169#define WM8995_AIF2_DRC_3 0x542
170#define WM8995_AIF2_DRC_4 0x543
171#define WM8995_AIF2_DRC_5 0x544
172#define WM8995_AIF2_EQ_GAINS_1 0x580
173#define WM8995_AIF2_EQ_GAINS_2 0x581
174#define WM8995_AIF2_EQ_BAND_1_A 0x582
175#define WM8995_AIF2_EQ_BAND_1_B 0x583
176#define WM8995_AIF2_EQ_BAND_1_PG 0x584
177#define WM8995_AIF2_EQ_BAND_2_A 0x585
178#define WM8995_AIF2_EQ_BAND_2_B 0x586
179#define WM8995_AIF2_EQ_BAND_2_C 0x587
180#define WM8995_AIF2_EQ_BAND_2_PG 0x588
181#define WM8995_AIF2_EQ_BAND_3_A 0x589
182#define WM8995_AIF2_EQ_BAND_3_B 0x58A
183#define WM8995_AIF2_EQ_BAND_3_C 0x58B
184#define WM8995_AIF2_EQ_BAND_3_PG 0x58C
185#define WM8995_AIF2_EQ_BAND_4_A 0x58D
186#define WM8995_AIF2_EQ_BAND_4_B 0x58E
187#define WM8995_AIF2_EQ_BAND_4_C 0x58F
188#define WM8995_AIF2_EQ_BAND_4_PG 0x590
189#define WM8995_AIF2_EQ_BAND_5_A 0x591
190#define WM8995_AIF2_EQ_BAND_5_B 0x592
191#define WM8995_AIF2_EQ_BAND_5_PG 0x593
192#define WM8995_DAC1_MIXER_VOLUMES 0x600
193#define WM8995_DAC1_LEFT_MIXER_ROUTING 0x601
194#define WM8995_DAC1_RIGHT_MIXER_ROUTING 0x602
195#define WM8995_DAC2_MIXER_VOLUMES 0x603
196#define WM8995_DAC2_LEFT_MIXER_ROUTING 0x604
197#define WM8995_DAC2_RIGHT_MIXER_ROUTING 0x605
198#define WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606
199#define WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607
200#define WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608
201#define WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609
202#define WM8995_DAC_SOFTMUTE 0x610
203#define WM8995_OVERSAMPLING 0x620
204#define WM8995_SIDETONE 0x621
205#define WM8995_GPIO_1 0x700
206#define WM8995_GPIO_2 0x701
207#define WM8995_GPIO_3 0x702
208#define WM8995_GPIO_4 0x703
209#define WM8995_GPIO_5 0x704
210#define WM8995_GPIO_6 0x705
211#define WM8995_GPIO_7 0x706
212#define WM8995_GPIO_8 0x707
213#define WM8995_GPIO_9 0x708
214#define WM8995_GPIO_10 0x709
215#define WM8995_GPIO_11 0x70A
216#define WM8995_GPIO_12 0x70B
217#define WM8995_GPIO_13 0x70C
218#define WM8995_GPIO_14 0x70D
219#define WM8995_PULL_CONTROL_1 0x720
220#define WM8995_PULL_CONTROL_2 0x721
221#define WM8995_INTERRUPT_STATUS_1 0x730
222#define WM8995_INTERRUPT_STATUS_2 0x731
223#define WM8995_INTERRUPT_RAW_STATUS_2 0x732
224#define WM8995_INTERRUPT_STATUS_1_MASK 0x738
225#define WM8995_INTERRUPT_STATUS_2_MASK 0x739
226#define WM8995_INTERRUPT_CONTROL 0x740
227#define WM8995_LEFT_PDM_SPEAKER_1 0x800
228#define WM8995_RIGHT_PDM_SPEAKER_1 0x801
229#define WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE 0x802
230#define WM8995_LEFT_PDM_SPEAKER_2 0x808
231#define WM8995_RIGHT_PDM_SPEAKER_2 0x809
232#define WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE 0x80A
233#define WM8995_WRITE_SEQUENCER_0 0x3000
234#define WM8995_WRITE_SEQUENCER_1 0x3001
235#define WM8995_WRITE_SEQUENCER_2 0x3002
236#define WM8995_WRITE_SEQUENCER_3 0x3003
237#define WM8995_WRITE_SEQUENCER_4 0x3004
238#define WM8995_WRITE_SEQUENCER_5 0x3005
239#define WM8995_WRITE_SEQUENCER_6 0x3006
240#define WM8995_WRITE_SEQUENCER_7 0x3007
241#define WM8995_WRITE_SEQUENCER_8 0x3008
242#define WM8995_WRITE_SEQUENCER_9 0x3009
243#define WM8995_WRITE_SEQUENCER_10 0x300A
244#define WM8995_WRITE_SEQUENCER_11 0x300B
245#define WM8995_WRITE_SEQUENCER_12 0x300C
246#define WM8995_WRITE_SEQUENCER_13 0x300D
247#define WM8995_WRITE_SEQUENCER_14 0x300E
248#define WM8995_WRITE_SEQUENCER_15 0x300F
249#define WM8995_WRITE_SEQUENCER_16 0x3010
250#define WM8995_WRITE_SEQUENCER_17 0x3011
251#define WM8995_WRITE_SEQUENCER_18 0x3012
252#define WM8995_WRITE_SEQUENCER_19 0x3013
253#define WM8995_WRITE_SEQUENCER_20 0x3014
254#define WM8995_WRITE_SEQUENCER_21 0x3015
255#define WM8995_WRITE_SEQUENCER_22 0x3016
256#define WM8995_WRITE_SEQUENCER_23 0x3017
257#define WM8995_WRITE_SEQUENCER_24 0x3018
258#define WM8995_WRITE_SEQUENCER_25 0x3019
259#define WM8995_WRITE_SEQUENCER_26 0x301A
260#define WM8995_WRITE_SEQUENCER_27 0x301B
261#define WM8995_WRITE_SEQUENCER_28 0x301C
262#define WM8995_WRITE_SEQUENCER_29 0x301D
263#define WM8995_WRITE_SEQUENCER_30 0x301E
264#define WM8995_WRITE_SEQUENCER_31 0x301F
265#define WM8995_WRITE_SEQUENCER_32 0x3020
266#define WM8995_WRITE_SEQUENCER_33 0x3021
267#define WM8995_WRITE_SEQUENCER_34 0x3022
268#define WM8995_WRITE_SEQUENCER_35 0x3023
269#define WM8995_WRITE_SEQUENCER_36 0x3024
270#define WM8995_WRITE_SEQUENCER_37 0x3025
271#define WM8995_WRITE_SEQUENCER_38 0x3026
272#define WM8995_WRITE_SEQUENCER_39 0x3027
273#define WM8995_WRITE_SEQUENCER_40 0x3028
274#define WM8995_WRITE_SEQUENCER_41 0x3029
275#define WM8995_WRITE_SEQUENCER_42 0x302A
276#define WM8995_WRITE_SEQUENCER_43 0x302B
277#define WM8995_WRITE_SEQUENCER_44 0x302C
278#define WM8995_WRITE_SEQUENCER_45 0x302D
279#define WM8995_WRITE_SEQUENCER_46 0x302E
280#define WM8995_WRITE_SEQUENCER_47 0x302F
281#define WM8995_WRITE_SEQUENCER_48 0x3030
282#define WM8995_WRITE_SEQUENCER_49 0x3031
283#define WM8995_WRITE_SEQUENCER_50 0x3032
284#define WM8995_WRITE_SEQUENCER_51 0x3033
285#define WM8995_WRITE_SEQUENCER_52 0x3034
286#define WM8995_WRITE_SEQUENCER_53 0x3035
287#define WM8995_WRITE_SEQUENCER_54 0x3036
288#define WM8995_WRITE_SEQUENCER_55 0x3037
289#define WM8995_WRITE_SEQUENCER_56 0x3038
290#define WM8995_WRITE_SEQUENCER_57 0x3039
291#define WM8995_WRITE_SEQUENCER_58 0x303A
292#define WM8995_WRITE_SEQUENCER_59 0x303B
293#define WM8995_WRITE_SEQUENCER_60 0x303C
294#define WM8995_WRITE_SEQUENCER_61 0x303D
295#define WM8995_WRITE_SEQUENCER_62 0x303E
296#define WM8995_WRITE_SEQUENCER_63 0x303F
297#define WM8995_WRITE_SEQUENCER_64 0x3040
298#define WM8995_WRITE_SEQUENCER_65 0x3041
299#define WM8995_WRITE_SEQUENCER_66 0x3042
300#define WM8995_WRITE_SEQUENCER_67 0x3043
301#define WM8995_WRITE_SEQUENCER_68 0x3044
302#define WM8995_WRITE_SEQUENCER_69 0x3045
303#define WM8995_WRITE_SEQUENCER_70 0x3046
304#define WM8995_WRITE_SEQUENCER_71 0x3047
305#define WM8995_WRITE_SEQUENCER_72 0x3048
306#define WM8995_WRITE_SEQUENCER_73 0x3049
307#define WM8995_WRITE_SEQUENCER_74 0x304A
308#define WM8995_WRITE_SEQUENCER_75 0x304B
309#define WM8995_WRITE_SEQUENCER_76 0x304C
310#define WM8995_WRITE_SEQUENCER_77 0x304D
311#define WM8995_WRITE_SEQUENCER_78 0x304E
312#define WM8995_WRITE_SEQUENCER_79 0x304F
313#define WM8995_WRITE_SEQUENCER_80 0x3050
314#define WM8995_WRITE_SEQUENCER_81 0x3051
315#define WM8995_WRITE_SEQUENCER_82 0x3052
316#define WM8995_WRITE_SEQUENCER_83 0x3053
317#define WM8995_WRITE_SEQUENCER_84 0x3054
318#define WM8995_WRITE_SEQUENCER_85 0x3055
319#define WM8995_WRITE_SEQUENCER_86 0x3056
320#define WM8995_WRITE_SEQUENCER_87 0x3057
321#define WM8995_WRITE_SEQUENCER_88 0x3058
322#define WM8995_WRITE_SEQUENCER_89 0x3059
323#define WM8995_WRITE_SEQUENCER_90 0x305A
324#define WM8995_WRITE_SEQUENCER_91 0x305B
325#define WM8995_WRITE_SEQUENCER_92 0x305C
326#define WM8995_WRITE_SEQUENCER_93 0x305D
327#define WM8995_WRITE_SEQUENCER_94 0x305E
328#define WM8995_WRITE_SEQUENCER_95 0x305F
329#define WM8995_WRITE_SEQUENCER_96 0x3060
330#define WM8995_WRITE_SEQUENCER_97 0x3061
331#define WM8995_WRITE_SEQUENCER_98 0x3062
332#define WM8995_WRITE_SEQUENCER_99 0x3063
333#define WM8995_WRITE_SEQUENCER_100 0x3064
334#define WM8995_WRITE_SEQUENCER_101 0x3065
335#define WM8995_WRITE_SEQUENCER_102 0x3066
336#define WM8995_WRITE_SEQUENCER_103 0x3067
337#define WM8995_WRITE_SEQUENCER_104 0x3068
338#define WM8995_WRITE_SEQUENCER_105 0x3069
339#define WM8995_WRITE_SEQUENCER_106 0x306A
340#define WM8995_WRITE_SEQUENCER_107 0x306B
341#define WM8995_WRITE_SEQUENCER_108 0x306C
342#define WM8995_WRITE_SEQUENCER_109 0x306D
343#define WM8995_WRITE_SEQUENCER_110 0x306E
344#define WM8995_WRITE_SEQUENCER_111 0x306F
345#define WM8995_WRITE_SEQUENCER_112 0x3070
346#define WM8995_WRITE_SEQUENCER_113 0x3071
347#define WM8995_WRITE_SEQUENCER_114 0x3072
348#define WM8995_WRITE_SEQUENCER_115 0x3073
349#define WM8995_WRITE_SEQUENCER_116 0x3074
350#define WM8995_WRITE_SEQUENCER_117 0x3075
351#define WM8995_WRITE_SEQUENCER_118 0x3076
352#define WM8995_WRITE_SEQUENCER_119 0x3077
353#define WM8995_WRITE_SEQUENCER_120 0x3078
354#define WM8995_WRITE_SEQUENCER_121 0x3079
355#define WM8995_WRITE_SEQUENCER_122 0x307A
356#define WM8995_WRITE_SEQUENCER_123 0x307B
357#define WM8995_WRITE_SEQUENCER_124 0x307C
358#define WM8995_WRITE_SEQUENCER_125 0x307D
359#define WM8995_WRITE_SEQUENCER_126 0x307E
360#define WM8995_WRITE_SEQUENCER_127 0x307F
361#define WM8995_WRITE_SEQUENCER_128 0x3080
362#define WM8995_WRITE_SEQUENCER_129 0x3081
363#define WM8995_WRITE_SEQUENCER_130 0x3082
364#define WM8995_WRITE_SEQUENCER_131 0x3083
365#define WM8995_WRITE_SEQUENCER_132 0x3084
366#define WM8995_WRITE_SEQUENCER_133 0x3085
367#define WM8995_WRITE_SEQUENCER_134 0x3086
368#define WM8995_WRITE_SEQUENCER_135 0x3087
369#define WM8995_WRITE_SEQUENCER_136 0x3088
370#define WM8995_WRITE_SEQUENCER_137 0x3089
371#define WM8995_WRITE_SEQUENCER_138 0x308A
372#define WM8995_WRITE_SEQUENCER_139 0x308B
373#define WM8995_WRITE_SEQUENCER_140 0x308C
374#define WM8995_WRITE_SEQUENCER_141 0x308D
375#define WM8995_WRITE_SEQUENCER_142 0x308E
376#define WM8995_WRITE_SEQUENCER_143 0x308F
377#define WM8995_WRITE_SEQUENCER_144 0x3090
378#define WM8995_WRITE_SEQUENCER_145 0x3091
379#define WM8995_WRITE_SEQUENCER_146 0x3092
380#define WM8995_WRITE_SEQUENCER_147 0x3093
381#define WM8995_WRITE_SEQUENCER_148 0x3094
382#define WM8995_WRITE_SEQUENCER_149 0x3095
383#define WM8995_WRITE_SEQUENCER_150 0x3096
384#define WM8995_WRITE_SEQUENCER_151 0x3097
385#define WM8995_WRITE_SEQUENCER_152 0x3098
386#define WM8995_WRITE_SEQUENCER_153 0x3099
387#define WM8995_WRITE_SEQUENCER_154 0x309A
388#define WM8995_WRITE_SEQUENCER_155 0x309B
389#define WM8995_WRITE_SEQUENCER_156 0x309C
390#define WM8995_WRITE_SEQUENCER_157 0x309D
391#define WM8995_WRITE_SEQUENCER_158 0x309E
392#define WM8995_WRITE_SEQUENCER_159 0x309F
393#define WM8995_WRITE_SEQUENCER_160 0x30A0
394#define WM8995_WRITE_SEQUENCER_161 0x30A1
395#define WM8995_WRITE_SEQUENCER_162 0x30A2
396#define WM8995_WRITE_SEQUENCER_163 0x30A3
397#define WM8995_WRITE_SEQUENCER_164 0x30A4
398#define WM8995_WRITE_SEQUENCER_165 0x30A5
399#define WM8995_WRITE_SEQUENCER_166 0x30A6
400#define WM8995_WRITE_SEQUENCER_167 0x30A7
401#define WM8995_WRITE_SEQUENCER_168 0x30A8
402#define WM8995_WRITE_SEQUENCER_169 0x30A9
403#define WM8995_WRITE_SEQUENCER_170 0x30AA
404#define WM8995_WRITE_SEQUENCER_171 0x30AB
405#define WM8995_WRITE_SEQUENCER_172 0x30AC
406#define WM8995_WRITE_SEQUENCER_173 0x30AD
407#define WM8995_WRITE_SEQUENCER_174 0x30AE
408#define WM8995_WRITE_SEQUENCER_175 0x30AF
409#define WM8995_WRITE_SEQUENCER_176 0x30B0
410#define WM8995_WRITE_SEQUENCER_177 0x30B1
411#define WM8995_WRITE_SEQUENCER_178 0x30B2
412#define WM8995_WRITE_SEQUENCER_179 0x30B3
413#define WM8995_WRITE_SEQUENCER_180 0x30B4
414#define WM8995_WRITE_SEQUENCER_181 0x30B5
415#define WM8995_WRITE_SEQUENCER_182 0x30B6
416#define WM8995_WRITE_SEQUENCER_183 0x30B7
417#define WM8995_WRITE_SEQUENCER_184 0x30B8
418#define WM8995_WRITE_SEQUENCER_185 0x30B9
419#define WM8995_WRITE_SEQUENCER_186 0x30BA
420#define WM8995_WRITE_SEQUENCER_187 0x30BB
421#define WM8995_WRITE_SEQUENCER_188 0x30BC
422#define WM8995_WRITE_SEQUENCER_189 0x30BD
423#define WM8995_WRITE_SEQUENCER_190 0x30BE
424#define WM8995_WRITE_SEQUENCER_191 0x30BF
425#define WM8995_WRITE_SEQUENCER_192 0x30C0
426#define WM8995_WRITE_SEQUENCER_193 0x30C1
427#define WM8995_WRITE_SEQUENCER_194 0x30C2
428#define WM8995_WRITE_SEQUENCER_195 0x30C3
429#define WM8995_WRITE_SEQUENCER_196 0x30C4
430#define WM8995_WRITE_SEQUENCER_197 0x30C5
431#define WM8995_WRITE_SEQUENCER_198 0x30C6
432#define WM8995_WRITE_SEQUENCER_199 0x30C7
433#define WM8995_WRITE_SEQUENCER_200 0x30C8
434#define WM8995_WRITE_SEQUENCER_201 0x30C9
435#define WM8995_WRITE_SEQUENCER_202 0x30CA
436#define WM8995_WRITE_SEQUENCER_203 0x30CB
437#define WM8995_WRITE_SEQUENCER_204 0x30CC
438#define WM8995_WRITE_SEQUENCER_205 0x30CD
439#define WM8995_WRITE_SEQUENCER_206 0x30CE
440#define WM8995_WRITE_SEQUENCER_207 0x30CF
441#define WM8995_WRITE_SEQUENCER_208 0x30D0
442#define WM8995_WRITE_SEQUENCER_209 0x30D1
443#define WM8995_WRITE_SEQUENCER_210 0x30D2
444#define WM8995_WRITE_SEQUENCER_211 0x30D3
445#define WM8995_WRITE_SEQUENCER_212 0x30D4
446#define WM8995_WRITE_SEQUENCER_213 0x30D5
447#define WM8995_WRITE_SEQUENCER_214 0x30D6
448#define WM8995_WRITE_SEQUENCER_215 0x30D7
449#define WM8995_WRITE_SEQUENCER_216 0x30D8
450#define WM8995_WRITE_SEQUENCER_217 0x30D9
451#define WM8995_WRITE_SEQUENCER_218 0x30DA
452#define WM8995_WRITE_SEQUENCER_219 0x30DB
453#define WM8995_WRITE_SEQUENCER_220 0x30DC
454#define WM8995_WRITE_SEQUENCER_221 0x30DD
455#define WM8995_WRITE_SEQUENCER_222 0x30DE
456#define WM8995_WRITE_SEQUENCER_223 0x30DF
457#define WM8995_WRITE_SEQUENCER_224 0x30E0
458#define WM8995_WRITE_SEQUENCER_225 0x30E1
459#define WM8995_WRITE_SEQUENCER_226 0x30E2
460#define WM8995_WRITE_SEQUENCER_227 0x30E3
461#define WM8995_WRITE_SEQUENCER_228 0x30E4
462#define WM8995_WRITE_SEQUENCER_229 0x30E5
463#define WM8995_WRITE_SEQUENCER_230 0x30E6
464#define WM8995_WRITE_SEQUENCER_231 0x30E7
465#define WM8995_WRITE_SEQUENCER_232 0x30E8
466#define WM8995_WRITE_SEQUENCER_233 0x30E9
467#define WM8995_WRITE_SEQUENCER_234 0x30EA
468#define WM8995_WRITE_SEQUENCER_235 0x30EB
469#define WM8995_WRITE_SEQUENCER_236 0x30EC
470#define WM8995_WRITE_SEQUENCER_237 0x30ED
471#define WM8995_WRITE_SEQUENCER_238 0x30EE
472#define WM8995_WRITE_SEQUENCER_239 0x30EF
473#define WM8995_WRITE_SEQUENCER_240 0x30F0
474#define WM8995_WRITE_SEQUENCER_241 0x30F1
475#define WM8995_WRITE_SEQUENCER_242 0x30F2
476#define WM8995_WRITE_SEQUENCER_243 0x30F3
477#define WM8995_WRITE_SEQUENCER_244 0x30F4
478#define WM8995_WRITE_SEQUENCER_245 0x30F5
479#define WM8995_WRITE_SEQUENCER_246 0x30F6
480#define WM8995_WRITE_SEQUENCER_247 0x30F7
481#define WM8995_WRITE_SEQUENCER_248 0x30F8
482#define WM8995_WRITE_SEQUENCER_249 0x30F9
483#define WM8995_WRITE_SEQUENCER_250 0x30FA
484#define WM8995_WRITE_SEQUENCER_251 0x30FB
485#define WM8995_WRITE_SEQUENCER_252 0x30FC
486#define WM8995_WRITE_SEQUENCER_253 0x30FD
487#define WM8995_WRITE_SEQUENCER_254 0x30FE
488#define WM8995_WRITE_SEQUENCER_255 0x30FF
489#define WM8995_WRITE_SEQUENCER_256 0x3100
490#define WM8995_WRITE_SEQUENCER_257 0x3101
491#define WM8995_WRITE_SEQUENCER_258 0x3102
492#define WM8995_WRITE_SEQUENCER_259 0x3103
493#define WM8995_WRITE_SEQUENCER_260 0x3104
494#define WM8995_WRITE_SEQUENCER_261 0x3105
495#define WM8995_WRITE_SEQUENCER_262 0x3106
496#define WM8995_WRITE_SEQUENCER_263 0x3107
497#define WM8995_WRITE_SEQUENCER_264 0x3108
498#define WM8995_WRITE_SEQUENCER_265 0x3109
499#define WM8995_WRITE_SEQUENCER_266 0x310A
500#define WM8995_WRITE_SEQUENCER_267 0x310B
501#define WM8995_WRITE_SEQUENCER_268 0x310C
502#define WM8995_WRITE_SEQUENCER_269 0x310D
503#define WM8995_WRITE_SEQUENCER_270 0x310E
504#define WM8995_WRITE_SEQUENCER_271 0x310F
505#define WM8995_WRITE_SEQUENCER_272 0x3110
506#define WM8995_WRITE_SEQUENCER_273 0x3111
507#define WM8995_WRITE_SEQUENCER_274 0x3112
508#define WM8995_WRITE_SEQUENCER_275 0x3113
509#define WM8995_WRITE_SEQUENCER_276 0x3114
510#define WM8995_WRITE_SEQUENCER_277 0x3115
511#define WM8995_WRITE_SEQUENCER_278 0x3116
512#define WM8995_WRITE_SEQUENCER_279 0x3117
513#define WM8995_WRITE_SEQUENCER_280 0x3118
514#define WM8995_WRITE_SEQUENCER_281 0x3119
515#define WM8995_WRITE_SEQUENCER_282 0x311A
516#define WM8995_WRITE_SEQUENCER_283 0x311B
517#define WM8995_WRITE_SEQUENCER_284 0x311C
518#define WM8995_WRITE_SEQUENCER_285 0x311D
519#define WM8995_WRITE_SEQUENCER_286 0x311E
520#define WM8995_WRITE_SEQUENCER_287 0x311F
521#define WM8995_WRITE_SEQUENCER_288 0x3120
522#define WM8995_WRITE_SEQUENCER_289 0x3121
523#define WM8995_WRITE_SEQUENCER_290 0x3122
524#define WM8995_WRITE_SEQUENCER_291 0x3123
525#define WM8995_WRITE_SEQUENCER_292 0x3124
526#define WM8995_WRITE_SEQUENCER_293 0x3125
527#define WM8995_WRITE_SEQUENCER_294 0x3126
528#define WM8995_WRITE_SEQUENCER_295 0x3127
529#define WM8995_WRITE_SEQUENCER_296 0x3128
530#define WM8995_WRITE_SEQUENCER_297 0x3129
531#define WM8995_WRITE_SEQUENCER_298 0x312A
532#define WM8995_WRITE_SEQUENCER_299 0x312B
533#define WM8995_WRITE_SEQUENCER_300 0x312C
534#define WM8995_WRITE_SEQUENCER_301 0x312D
535#define WM8995_WRITE_SEQUENCER_302 0x312E
536#define WM8995_WRITE_SEQUENCER_303 0x312F
537#define WM8995_WRITE_SEQUENCER_304 0x3130
538#define WM8995_WRITE_SEQUENCER_305 0x3131
539#define WM8995_WRITE_SEQUENCER_306 0x3132
540#define WM8995_WRITE_SEQUENCER_307 0x3133
541#define WM8995_WRITE_SEQUENCER_308 0x3134
542#define WM8995_WRITE_SEQUENCER_309 0x3135
543#define WM8995_WRITE_SEQUENCER_310 0x3136
544#define WM8995_WRITE_SEQUENCER_311 0x3137
545#define WM8995_WRITE_SEQUENCER_312 0x3138
546#define WM8995_WRITE_SEQUENCER_313 0x3139
547#define WM8995_WRITE_SEQUENCER_314 0x313A
548#define WM8995_WRITE_SEQUENCER_315 0x313B
549#define WM8995_WRITE_SEQUENCER_316 0x313C
550#define WM8995_WRITE_SEQUENCER_317 0x313D
551#define WM8995_WRITE_SEQUENCER_318 0x313E
552#define WM8995_WRITE_SEQUENCER_319 0x313F
553#define WM8995_WRITE_SEQUENCER_320 0x3140
554#define WM8995_WRITE_SEQUENCER_321 0x3141
555#define WM8995_WRITE_SEQUENCER_322 0x3142
556#define WM8995_WRITE_SEQUENCER_323 0x3143
557#define WM8995_WRITE_SEQUENCER_324 0x3144
558#define WM8995_WRITE_SEQUENCER_325 0x3145
559#define WM8995_WRITE_SEQUENCER_326 0x3146
560#define WM8995_WRITE_SEQUENCER_327 0x3147
561#define WM8995_WRITE_SEQUENCER_328 0x3148
562#define WM8995_WRITE_SEQUENCER_329 0x3149
563#define WM8995_WRITE_SEQUENCER_330 0x314A
564#define WM8995_WRITE_SEQUENCER_331 0x314B
565#define WM8995_WRITE_SEQUENCER_332 0x314C
566#define WM8995_WRITE_SEQUENCER_333 0x314D
567#define WM8995_WRITE_SEQUENCER_334 0x314E
568#define WM8995_WRITE_SEQUENCER_335 0x314F
569#define WM8995_WRITE_SEQUENCER_336 0x3150
570#define WM8995_WRITE_SEQUENCER_337 0x3151
571#define WM8995_WRITE_SEQUENCER_338 0x3152
572#define WM8995_WRITE_SEQUENCER_339 0x3153
573#define WM8995_WRITE_SEQUENCER_340 0x3154
574#define WM8995_WRITE_SEQUENCER_341 0x3155
575#define WM8995_WRITE_SEQUENCER_342 0x3156
576#define WM8995_WRITE_SEQUENCER_343 0x3157
577#define WM8995_WRITE_SEQUENCER_344 0x3158
578#define WM8995_WRITE_SEQUENCER_345 0x3159
579#define WM8995_WRITE_SEQUENCER_346 0x315A
580#define WM8995_WRITE_SEQUENCER_347 0x315B
581#define WM8995_WRITE_SEQUENCER_348 0x315C
582#define WM8995_WRITE_SEQUENCER_349 0x315D
583#define WM8995_WRITE_SEQUENCER_350 0x315E
584#define WM8995_WRITE_SEQUENCER_351 0x315F
585#define WM8995_WRITE_SEQUENCER_352 0x3160
586#define WM8995_WRITE_SEQUENCER_353 0x3161
587#define WM8995_WRITE_SEQUENCER_354 0x3162
588#define WM8995_WRITE_SEQUENCER_355 0x3163
589#define WM8995_WRITE_SEQUENCER_356 0x3164
590#define WM8995_WRITE_SEQUENCER_357 0x3165
591#define WM8995_WRITE_SEQUENCER_358 0x3166
592#define WM8995_WRITE_SEQUENCER_359 0x3167
593#define WM8995_WRITE_SEQUENCER_360 0x3168
594#define WM8995_WRITE_SEQUENCER_361 0x3169
595#define WM8995_WRITE_SEQUENCER_362 0x316A
596#define WM8995_WRITE_SEQUENCER_363 0x316B
597#define WM8995_WRITE_SEQUENCER_364 0x316C
598#define WM8995_WRITE_SEQUENCER_365 0x316D
599#define WM8995_WRITE_SEQUENCER_366 0x316E
600#define WM8995_WRITE_SEQUENCER_367 0x316F
601#define WM8995_WRITE_SEQUENCER_368 0x3170
602#define WM8995_WRITE_SEQUENCER_369 0x3171
603#define WM8995_WRITE_SEQUENCER_370 0x3172
604#define WM8995_WRITE_SEQUENCER_371 0x3173
605#define WM8995_WRITE_SEQUENCER_372 0x3174
606#define WM8995_WRITE_SEQUENCER_373 0x3175
607#define WM8995_WRITE_SEQUENCER_374 0x3176
608#define WM8995_WRITE_SEQUENCER_375 0x3177
609#define WM8995_WRITE_SEQUENCER_376 0x3178
610#define WM8995_WRITE_SEQUENCER_377 0x3179
611#define WM8995_WRITE_SEQUENCER_378 0x317A
612#define WM8995_WRITE_SEQUENCER_379 0x317B
613#define WM8995_WRITE_SEQUENCER_380 0x317C
614#define WM8995_WRITE_SEQUENCER_381 0x317D
615#define WM8995_WRITE_SEQUENCER_382 0x317E
616#define WM8995_WRITE_SEQUENCER_383 0x317F
617#define WM8995_WRITE_SEQUENCER_384 0x3180
618#define WM8995_WRITE_SEQUENCER_385 0x3181
619#define WM8995_WRITE_SEQUENCER_386 0x3182
620#define WM8995_WRITE_SEQUENCER_387 0x3183
621#define WM8995_WRITE_SEQUENCER_388 0x3184
622#define WM8995_WRITE_SEQUENCER_389 0x3185
623#define WM8995_WRITE_SEQUENCER_390 0x3186
624#define WM8995_WRITE_SEQUENCER_391 0x3187
625#define WM8995_WRITE_SEQUENCER_392 0x3188
626#define WM8995_WRITE_SEQUENCER_393 0x3189
627#define WM8995_WRITE_SEQUENCER_394 0x318A
628#define WM8995_WRITE_SEQUENCER_395 0x318B
629#define WM8995_WRITE_SEQUENCER_396 0x318C
630#define WM8995_WRITE_SEQUENCER_397 0x318D
631#define WM8995_WRITE_SEQUENCER_398 0x318E
632#define WM8995_WRITE_SEQUENCER_399 0x318F
633#define WM8995_WRITE_SEQUENCER_400 0x3190
634#define WM8995_WRITE_SEQUENCER_401 0x3191
635#define WM8995_WRITE_SEQUENCER_402 0x3192
636#define WM8995_WRITE_SEQUENCER_403 0x3193
637#define WM8995_WRITE_SEQUENCER_404 0x3194
638#define WM8995_WRITE_SEQUENCER_405 0x3195
639#define WM8995_WRITE_SEQUENCER_406 0x3196
640#define WM8995_WRITE_SEQUENCER_407 0x3197
641#define WM8995_WRITE_SEQUENCER_408 0x3198
642#define WM8995_WRITE_SEQUENCER_409 0x3199
643#define WM8995_WRITE_SEQUENCER_410 0x319A
644#define WM8995_WRITE_SEQUENCER_411 0x319B
645#define WM8995_WRITE_SEQUENCER_412 0x319C
646#define WM8995_WRITE_SEQUENCER_413 0x319D
647#define WM8995_WRITE_SEQUENCER_414 0x319E
648#define WM8995_WRITE_SEQUENCER_415 0x319F
649#define WM8995_WRITE_SEQUENCER_416 0x31A0
650#define WM8995_WRITE_SEQUENCER_417 0x31A1
651#define WM8995_WRITE_SEQUENCER_418 0x31A2
652#define WM8995_WRITE_SEQUENCER_419 0x31A3
653#define WM8995_WRITE_SEQUENCER_420 0x31A4
654#define WM8995_WRITE_SEQUENCER_421 0x31A5
655#define WM8995_WRITE_SEQUENCER_422 0x31A6
656#define WM8995_WRITE_SEQUENCER_423 0x31A7
657#define WM8995_WRITE_SEQUENCER_424 0x31A8
658#define WM8995_WRITE_SEQUENCER_425 0x31A9
659#define WM8995_WRITE_SEQUENCER_426 0x31AA
660#define WM8995_WRITE_SEQUENCER_427 0x31AB
661#define WM8995_WRITE_SEQUENCER_428 0x31AC
662#define WM8995_WRITE_SEQUENCER_429 0x31AD
663#define WM8995_WRITE_SEQUENCER_430 0x31AE
664#define WM8995_WRITE_SEQUENCER_431 0x31AF
665#define WM8995_WRITE_SEQUENCER_432 0x31B0
666#define WM8995_WRITE_SEQUENCER_433 0x31B1
667#define WM8995_WRITE_SEQUENCER_434 0x31B2
668#define WM8995_WRITE_SEQUENCER_435 0x31B3
669#define WM8995_WRITE_SEQUENCER_436 0x31B4
670#define WM8995_WRITE_SEQUENCER_437 0x31B5
671#define WM8995_WRITE_SEQUENCER_438 0x31B6
672#define WM8995_WRITE_SEQUENCER_439 0x31B7
673#define WM8995_WRITE_SEQUENCER_440 0x31B8
674#define WM8995_WRITE_SEQUENCER_441 0x31B9
675#define WM8995_WRITE_SEQUENCER_442 0x31BA
676#define WM8995_WRITE_SEQUENCER_443 0x31BB
677#define WM8995_WRITE_SEQUENCER_444 0x31BC
678#define WM8995_WRITE_SEQUENCER_445 0x31BD
679#define WM8995_WRITE_SEQUENCER_446 0x31BE
680#define WM8995_WRITE_SEQUENCER_447 0x31BF
681#define WM8995_WRITE_SEQUENCER_448 0x31C0
682#define WM8995_WRITE_SEQUENCER_449 0x31C1
683#define WM8995_WRITE_SEQUENCER_450 0x31C2
684#define WM8995_WRITE_SEQUENCER_451 0x31C3
685#define WM8995_WRITE_SEQUENCER_452 0x31C4
686#define WM8995_WRITE_SEQUENCER_453 0x31C5
687#define WM8995_WRITE_SEQUENCER_454 0x31C6
688#define WM8995_WRITE_SEQUENCER_455 0x31C7
689#define WM8995_WRITE_SEQUENCER_456 0x31C8
690#define WM8995_WRITE_SEQUENCER_457 0x31C9
691#define WM8995_WRITE_SEQUENCER_458 0x31CA
692#define WM8995_WRITE_SEQUENCER_459 0x31CB
693#define WM8995_WRITE_SEQUENCER_460 0x31CC
694#define WM8995_WRITE_SEQUENCER_461 0x31CD
695#define WM8995_WRITE_SEQUENCER_462 0x31CE
696#define WM8995_WRITE_SEQUENCER_463 0x31CF
697#define WM8995_WRITE_SEQUENCER_464 0x31D0
698#define WM8995_WRITE_SEQUENCER_465 0x31D1
699#define WM8995_WRITE_SEQUENCER_466 0x31D2
700#define WM8995_WRITE_SEQUENCER_467 0x31D3
701#define WM8995_WRITE_SEQUENCER_468 0x31D4
702#define WM8995_WRITE_SEQUENCER_469 0x31D5
703#define WM8995_WRITE_SEQUENCER_470 0x31D6
704#define WM8995_WRITE_SEQUENCER_471 0x31D7
705#define WM8995_WRITE_SEQUENCER_472 0x31D8
706#define WM8995_WRITE_SEQUENCER_473 0x31D9
707#define WM8995_WRITE_SEQUENCER_474 0x31DA
708#define WM8995_WRITE_SEQUENCER_475 0x31DB
709#define WM8995_WRITE_SEQUENCER_476 0x31DC
710#define WM8995_WRITE_SEQUENCER_477 0x31DD
711#define WM8995_WRITE_SEQUENCER_478 0x31DE
712#define WM8995_WRITE_SEQUENCER_479 0x31DF
713#define WM8995_WRITE_SEQUENCER_480 0x31E0
714#define WM8995_WRITE_SEQUENCER_481 0x31E1
715#define WM8995_WRITE_SEQUENCER_482 0x31E2
716#define WM8995_WRITE_SEQUENCER_483 0x31E3
717#define WM8995_WRITE_SEQUENCER_484 0x31E4
718#define WM8995_WRITE_SEQUENCER_485 0x31E5
719#define WM8995_WRITE_SEQUENCER_486 0x31E6
720#define WM8995_WRITE_SEQUENCER_487 0x31E7
721#define WM8995_WRITE_SEQUENCER_488 0x31E8
722#define WM8995_WRITE_SEQUENCER_489 0x31E9
723#define WM8995_WRITE_SEQUENCER_490 0x31EA
724#define WM8995_WRITE_SEQUENCER_491 0x31EB
725#define WM8995_WRITE_SEQUENCER_492 0x31EC
726#define WM8995_WRITE_SEQUENCER_493 0x31ED
727#define WM8995_WRITE_SEQUENCER_494 0x31EE
728#define WM8995_WRITE_SEQUENCER_495 0x31EF
729#define WM8995_WRITE_SEQUENCER_496 0x31F0
730#define WM8995_WRITE_SEQUENCER_497 0x31F1
731#define WM8995_WRITE_SEQUENCER_498 0x31F2
732#define WM8995_WRITE_SEQUENCER_499 0x31F3
733#define WM8995_WRITE_SEQUENCER_500 0x31F4
734#define WM8995_WRITE_SEQUENCER_501 0x31F5
735#define WM8995_WRITE_SEQUENCER_502 0x31F6
736#define WM8995_WRITE_SEQUENCER_503 0x31F7
737#define WM8995_WRITE_SEQUENCER_504 0x31F8
738#define WM8995_WRITE_SEQUENCER_505 0x31F9
739#define WM8995_WRITE_SEQUENCER_506 0x31FA
740#define WM8995_WRITE_SEQUENCER_507 0x31FB
741#define WM8995_WRITE_SEQUENCER_508 0x31FC
742#define WM8995_WRITE_SEQUENCER_509 0x31FD
743#define WM8995_WRITE_SEQUENCER_510 0x31FE
744#define WM8995_WRITE_SEQUENCER_511 0x31FF
745
746#define WM8995_REGISTER_COUNT 725
747#define WM8995_MAX_REGISTER 0x31FF
748
749#define WM8995_MAX_CACHED_REGISTER WM8995_MAX_REGISTER
750
751/*
752 * Field Definitions.
753 */
754
755/*
756 * R0 (0x00) - Software Reset
757 */
758#define WM8995_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
759#define WM8995_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
760#define WM8995_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
761
762/*
763 * R1 (0x01) - Power Management (1)
764 */
765#define WM8995_MICB2_ENA 0x0200 /* MICB2_ENA */
766#define WM8995_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */
767#define WM8995_MICB2_ENA_SHIFT 9 /* MICB2_ENA */
768#define WM8995_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
769#define WM8995_MICB1_ENA 0x0100 /* MICB1_ENA */
770#define WM8995_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */
771#define WM8995_MICB1_ENA_SHIFT 8 /* MICB1_ENA */
772#define WM8995_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
773#define WM8995_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */
774#define WM8995_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */
775#define WM8995_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */
776#define WM8995_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */
777#define WM8995_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */
778#define WM8995_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */
779#define WM8995_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */
780#define WM8995_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */
781#define WM8995_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */
782#define WM8995_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */
783#define WM8995_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */
784#define WM8995_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */
785#define WM8995_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */
786#define WM8995_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */
787#define WM8995_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */
788#define WM8995_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */
789#define WM8995_BG_ENA 0x0001 /* BG_ENA */
790#define WM8995_BG_ENA_MASK 0x0001 /* BG_ENA */
791#define WM8995_BG_ENA_SHIFT 0 /* BG_ENA */
792#define WM8995_BG_ENA_WIDTH 1 /* BG_ENA */
793
794/*
795 * R2 (0x02) - Power Management (2)
796 */
797#define WM8995_OPCLK_ENA 0x0800 /* OPCLK_ENA */
798#define WM8995_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */
799#define WM8995_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */
800#define WM8995_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
801#define WM8995_IN1L_ENA 0x0020 /* IN1L_ENA */
802#define WM8995_IN1L_ENA_MASK 0x0020 /* IN1L_ENA */
803#define WM8995_IN1L_ENA_SHIFT 5 /* IN1L_ENA */
804#define WM8995_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
805#define WM8995_IN1R_ENA 0x0010 /* IN1R_ENA */
806#define WM8995_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */
807#define WM8995_IN1R_ENA_SHIFT 4 /* IN1R_ENA */
808#define WM8995_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
809#define WM8995_LDO2_ENA 0x0002 /* LDO2_ENA */
810#define WM8995_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */
811#define WM8995_LDO2_ENA_SHIFT 1 /* LDO2_ENA */
812#define WM8995_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
813
814/*
815 * R3 (0x03) - Power Management (3)
816 */
817#define WM8995_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */
818#define WM8995_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */
819#define WM8995_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */
820#define WM8995_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */
821#define WM8995_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */
822#define WM8995_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */
823#define WM8995_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */
824#define WM8995_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */
825#define WM8995_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */
826#define WM8995_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */
827#define WM8995_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */
828#define WM8995_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */
829#define WM8995_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */
830#define WM8995_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */
831#define WM8995_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */
832#define WM8995_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */
833#define WM8995_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */
834#define WM8995_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */
835#define WM8995_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */
836#define WM8995_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */
837#define WM8995_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */
838#define WM8995_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */
839#define WM8995_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */
840#define WM8995_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */
841#define WM8995_DMIC3L_ENA 0x0080 /* DMIC3L_ENA */
842#define WM8995_DMIC3L_ENA_MASK 0x0080 /* DMIC3L_ENA */
843#define WM8995_DMIC3L_ENA_SHIFT 7 /* DMIC3L_ENA */
844#define WM8995_DMIC3L_ENA_WIDTH 1 /* DMIC3L_ENA */
845#define WM8995_DMIC3R_ENA 0x0040 /* DMIC3R_ENA */
846#define WM8995_DMIC3R_ENA_MASK 0x0040 /* DMIC3R_ENA */
847#define WM8995_DMIC3R_ENA_SHIFT 6 /* DMIC3R_ENA */
848#define WM8995_DMIC3R_ENA_WIDTH 1 /* DMIC3R_ENA */
849#define WM8995_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */
850#define WM8995_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */
851#define WM8995_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */
852#define WM8995_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */
853#define WM8995_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */
854#define WM8995_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */
855#define WM8995_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */
856#define WM8995_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */
857#define WM8995_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */
858#define WM8995_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */
859#define WM8995_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */
860#define WM8995_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */
861#define WM8995_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */
862#define WM8995_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */
863#define WM8995_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */
864#define WM8995_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */
865#define WM8995_ADCL_ENA 0x0002 /* ADCL_ENA */
866#define WM8995_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
867#define WM8995_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
868#define WM8995_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
869#define WM8995_ADCR_ENA 0x0001 /* ADCR_ENA */
870#define WM8995_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
871#define WM8995_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
872#define WM8995_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
873
874/*
875 * R4 (0x04) - Power Management (4)
876 */
877#define WM8995_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */
878#define WM8995_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */
879#define WM8995_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */
880#define WM8995_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */
881#define WM8995_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */
882#define WM8995_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */
883#define WM8995_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */
884#define WM8995_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */
885#define WM8995_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */
886#define WM8995_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */
887#define WM8995_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */
888#define WM8995_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */
889#define WM8995_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */
890#define WM8995_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */
891#define WM8995_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */
892#define WM8995_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */
893#define WM8995_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */
894#define WM8995_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */
895#define WM8995_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */
896#define WM8995_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */
897#define WM8995_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */
898#define WM8995_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */
899#define WM8995_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */
900#define WM8995_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */
901#define WM8995_DAC2L_ENA 0x0008 /* DAC2L_ENA */
902#define WM8995_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */
903#define WM8995_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */
904#define WM8995_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */
905#define WM8995_DAC2R_ENA 0x0004 /* DAC2R_ENA */
906#define WM8995_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */
907#define WM8995_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */
908#define WM8995_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */
909#define WM8995_DAC1L_ENA 0x0002 /* DAC1L_ENA */
910#define WM8995_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */
911#define WM8995_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */
912#define WM8995_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */
913#define WM8995_DAC1R_ENA 0x0001 /* DAC1R_ENA */
914#define WM8995_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */
915#define WM8995_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */
916#define WM8995_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */
917
918/*
919 * R5 (0x05) - Power Management (5)
920 */
921#define WM8995_DMIC_SRC2_MASK 0x0300 /* DMIC_SRC2 - [9:8] */
922#define WM8995_DMIC_SRC2_SHIFT 8 /* DMIC_SRC2 - [9:8] */
923#define WM8995_DMIC_SRC2_WIDTH 2 /* DMIC_SRC2 - [9:8] */
924#define WM8995_DMIC_SRC1_MASK 0x00C0 /* DMIC_SRC1 - [7:6] */
925#define WM8995_DMIC_SRC1_SHIFT 6 /* DMIC_SRC1 - [7:6] */
926#define WM8995_DMIC_SRC1_WIDTH 2 /* DMIC_SRC1 - [7:6] */
927#define WM8995_AIF3_TRI 0x0020 /* AIF3_TRI */
928#define WM8995_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */
929#define WM8995_AIF3_TRI_SHIFT 5 /* AIF3_TRI */
930#define WM8995_AIF3_TRI_WIDTH 1 /* AIF3_TRI */
931#define WM8995_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */
932#define WM8995_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */
933#define WM8995_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */
934#define WM8995_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */
935#define WM8995_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */
936#define WM8995_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */
937#define WM8995_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */
938#define WM8995_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */
939#define WM8995_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */
940#define WM8995_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */
941#define WM8995_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */
942#define WM8995_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */
943#define WM8995_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */
944#define WM8995_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */
945#define WM8995_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */
946
947/*
948 * R16 (0x10) - Left Line Input 1 Volume
949 */
950#define WM8995_IN1_VU 0x0080 /* IN1_VU */
951#define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */
952#define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */
953#define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */
954#define WM8995_IN1L_ZC 0x0020 /* IN1L_ZC */
955#define WM8995_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */
956#define WM8995_IN1L_ZC_SHIFT 5 /* IN1L_ZC */
957#define WM8995_IN1L_ZC_WIDTH 1 /* IN1L_ZC */
958#define WM8995_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */
959#define WM8995_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */
960#define WM8995_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */
961
962/*
963 * R17 (0x11) - Right Line Input 1 Volume
964 */
965#define WM8995_IN1_VU 0x0080 /* IN1_VU */
966#define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */
967#define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */
968#define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */
969#define WM8995_IN1R_ZC 0x0020 /* IN1R_ZC */
970#define WM8995_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */
971#define WM8995_IN1R_ZC_SHIFT 5 /* IN1R_ZC */
972#define WM8995_IN1R_ZC_WIDTH 1 /* IN1R_ZC */
973#define WM8995_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */
974#define WM8995_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */
975#define WM8995_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */
976
977/*
978 * R18 (0x12) - Left Line Input Control
979 */
980#define WM8995_IN1L_BOOST_MASK 0x0030 /* IN1L_BOOST - [5:4] */
981#define WM8995_IN1L_BOOST_SHIFT 4 /* IN1L_BOOST - [5:4] */
982#define WM8995_IN1L_BOOST_WIDTH 2 /* IN1L_BOOST - [5:4] */
983#define WM8995_IN1L_MODE_MASK 0x000C /* IN1L_MODE - [3:2] */
984#define WM8995_IN1L_MODE_SHIFT 2 /* IN1L_MODE - [3:2] */
985#define WM8995_IN1L_MODE_WIDTH 2 /* IN1L_MODE - [3:2] */
986#define WM8995_IN1R_MODE_MASK 0x0003 /* IN1R_MODE - [1:0] */
987#define WM8995_IN1R_MODE_SHIFT 0 /* IN1R_MODE - [1:0] */
988#define WM8995_IN1R_MODE_WIDTH 2 /* IN1R_MODE - [1:0] */
989
990/*
991 * R24 (0x18) - DAC1 Left Volume
992 */
993#define WM8995_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */
994#define WM8995_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */
995#define WM8995_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */
996#define WM8995_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */
997#define WM8995_DAC1_VU 0x0100 /* DAC1_VU */
998#define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */
999#define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */
1000#define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */
1001#define WM8995_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */
1002#define WM8995_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */
1003#define WM8995_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */
1004
1005/*
1006 * R25 (0x19) - DAC1 Right Volume
1007 */
1008#define WM8995_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */
1009#define WM8995_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */
1010#define WM8995_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */
1011#define WM8995_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */
1012#define WM8995_DAC1_VU 0x0100 /* DAC1_VU */
1013#define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */
1014#define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */
1015#define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */
1016#define WM8995_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */
1017#define WM8995_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */
1018#define WM8995_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */
1019
1020/*
1021 * R26 (0x1A) - DAC2 Left Volume
1022 */
1023#define WM8995_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */
1024#define WM8995_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */
1025#define WM8995_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */
1026#define WM8995_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */
1027#define WM8995_DAC2_VU 0x0100 /* DAC2_VU */
1028#define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1029#define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */
1030#define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */
1031#define WM8995_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */
1032#define WM8995_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */
1033#define WM8995_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */
1034
1035/*
1036 * R27 (0x1B) - DAC2 Right Volume
1037 */
1038#define WM8995_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */
1039#define WM8995_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */
1040#define WM8995_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */
1041#define WM8995_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */
1042#define WM8995_DAC2_VU 0x0100 /* DAC2_VU */
1043#define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1044#define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */
1045#define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */
1046#define WM8995_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */
1047#define WM8995_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */
1048#define WM8995_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */
1049
1050/*
1051 * R28 (0x1C) - Output Volume ZC (1)
1052 */
1053#define WM8995_HPOUT2L_ZC 0x0008 /* HPOUT2L_ZC */
1054#define WM8995_HPOUT2L_ZC_MASK 0x0008 /* HPOUT2L_ZC */
1055#define WM8995_HPOUT2L_ZC_SHIFT 3 /* HPOUT2L_ZC */
1056#define WM8995_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */
1057#define WM8995_HPOUT2R_ZC 0x0004 /* HPOUT2R_ZC */
1058#define WM8995_HPOUT2R_ZC_MASK 0x0004 /* HPOUT2R_ZC */
1059#define WM8995_HPOUT2R_ZC_SHIFT 2 /* HPOUT2R_ZC */
1060#define WM8995_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */
1061#define WM8995_HPOUT1L_ZC 0x0002 /* HPOUT1L_ZC */
1062#define WM8995_HPOUT1L_ZC_MASK 0x0002 /* HPOUT1L_ZC */
1063#define WM8995_HPOUT1L_ZC_SHIFT 1 /* HPOUT1L_ZC */
1064#define WM8995_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */
1065#define WM8995_HPOUT1R_ZC 0x0001 /* HPOUT1R_ZC */
1066#define WM8995_HPOUT1R_ZC_MASK 0x0001 /* HPOUT1R_ZC */
1067#define WM8995_HPOUT1R_ZC_SHIFT 0 /* HPOUT1R_ZC */
1068#define WM8995_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */
1069
1070/*
1071 * R32 (0x20) - MICBIAS (1)
1072 */
1073#define WM8995_MICB1_MODE 0x0008 /* MICB1_MODE */
1074#define WM8995_MICB1_MODE_MASK 0x0008 /* MICB1_MODE */
1075#define WM8995_MICB1_MODE_SHIFT 3 /* MICB1_MODE */
1076#define WM8995_MICB1_MODE_WIDTH 1 /* MICB1_MODE */
1077#define WM8995_MICB1_LVL_MASK 0x0006 /* MICB1_LVL - [2:1] */
1078#define WM8995_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [2:1] */
1079#define WM8995_MICB1_LVL_WIDTH 2 /* MICB1_LVL - [2:1] */
1080#define WM8995_MICB1_DISCH 0x0001 /* MICB1_DISCH */
1081#define WM8995_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */
1082#define WM8995_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */
1083#define WM8995_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
1084
1085/*
1086 * R33 (0x21) - MICBIAS (2)
1087 */
1088#define WM8995_MICB2_MODE 0x0008 /* MICB2_MODE */
1089#define WM8995_MICB2_MODE_MASK 0x0008 /* MICB2_MODE */
1090#define WM8995_MICB2_MODE_SHIFT 3 /* MICB2_MODE */
1091#define WM8995_MICB2_MODE_WIDTH 1 /* MICB2_MODE */
1092#define WM8995_MICB2_LVL_MASK 0x0006 /* MICB2_LVL - [2:1] */
1093#define WM8995_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [2:1] */
1094#define WM8995_MICB2_LVL_WIDTH 2 /* MICB2_LVL - [2:1] */
1095#define WM8995_MICB2_DISCH 0x0001 /* MICB2_DISCH */
1096#define WM8995_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */
1097#define WM8995_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */
1098#define WM8995_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
1099
1100/*
1101 * R40 (0x28) - LDO 1
1102 */
1103#define WM8995_LDO1_MODE 0x0020 /* LDO1_MODE */
1104#define WM8995_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */
1105#define WM8995_LDO1_MODE_SHIFT 5 /* LDO1_MODE */
1106#define WM8995_LDO1_MODE_WIDTH 1 /* LDO1_MODE */
1107#define WM8995_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */
1108#define WM8995_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */
1109#define WM8995_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */
1110#define WM8995_LDO1_DISCH 0x0001 /* LDO1_DISCH */
1111#define WM8995_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */
1112#define WM8995_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */
1113#define WM8995_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
1114
1115/*
1116 * R41 (0x29) - LDO 2
1117 */
1118#define WM8995_LDO2_MODE 0x0020 /* LDO2_MODE */
1119#define WM8995_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */
1120#define WM8995_LDO2_MODE_SHIFT 5 /* LDO2_MODE */
1121#define WM8995_LDO2_MODE_WIDTH 1 /* LDO2_MODE */
1122#define WM8995_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */
1123#define WM8995_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */
1124#define WM8995_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */
1125#define WM8995_LDO2_DISCH 0x0001 /* LDO2_DISCH */
1126#define WM8995_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */
1127#define WM8995_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */
1128#define WM8995_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
1129
1130/*
1131 * R48 (0x30) - Accessory Detect Mode1
1132 */
1133#define WM8995_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */
1134#define WM8995_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */
1135#define WM8995_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */
1136
1137/*
1138 * R49 (0x31) - Accessory Detect Mode2
1139 */
1140#define WM8995_VID_ENA 0x0001 /* VID_ENA */
1141#define WM8995_VID_ENA_MASK 0x0001 /* VID_ENA */
1142#define WM8995_VID_ENA_SHIFT 0 /* VID_ENA */
1143#define WM8995_VID_ENA_WIDTH 1 /* VID_ENA */
1144
1145/*
1146 * R52 (0x34) - Headphone Detect1
1147 */
1148#define WM8995_HP_RAMPRATE 0x0002 /* HP_RAMPRATE */
1149#define WM8995_HP_RAMPRATE_MASK 0x0002 /* HP_RAMPRATE */
1150#define WM8995_HP_RAMPRATE_SHIFT 1 /* HP_RAMPRATE */
1151#define WM8995_HP_RAMPRATE_WIDTH 1 /* HP_RAMPRATE */
1152#define WM8995_HP_POLL 0x0001 /* HP_POLL */
1153#define WM8995_HP_POLL_MASK 0x0001 /* HP_POLL */
1154#define WM8995_HP_POLL_SHIFT 0 /* HP_POLL */
1155#define WM8995_HP_POLL_WIDTH 1 /* HP_POLL */
1156
1157/*
1158 * R53 (0x35) - Headphone Detect2
1159 */
1160#define WM8995_HP_DONE 0x0080 /* HP_DONE */
1161#define WM8995_HP_DONE_MASK 0x0080 /* HP_DONE */
1162#define WM8995_HP_DONE_SHIFT 7 /* HP_DONE */
1163#define WM8995_HP_DONE_WIDTH 1 /* HP_DONE */
1164#define WM8995_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */
1165#define WM8995_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
1166#define WM8995_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
1167
1168/*
1169 * R56 (0x38) - Mic Detect (1)
1170 */
1171#define WM8995_MICD_RATE_MASK 0x7800 /* MICD_RATE - [14:11] */
1172#define WM8995_MICD_RATE_SHIFT 11 /* MICD_RATE - [14:11] */
1173#define WM8995_MICD_RATE_WIDTH 4 /* MICD_RATE - [14:11] */
1174#define WM8995_MICD_LVL_SEL_MASK 0x01F8 /* MICD_LVL_SEL - [8:3] */
1175#define WM8995_MICD_LVL_SEL_SHIFT 3 /* MICD_LVL_SEL - [8:3] */
1176#define WM8995_MICD_LVL_SEL_WIDTH 6 /* MICD_LVL_SEL - [8:3] */
1177#define WM8995_MICD_DBTIME 0x0002 /* MICD_DBTIME */
1178#define WM8995_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */
1179#define WM8995_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
1180#define WM8995_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
1181#define WM8995_MICD_ENA 0x0001 /* MICD_ENA */
1182#define WM8995_MICD_ENA_MASK 0x0001 /* MICD_ENA */
1183#define WM8995_MICD_ENA_SHIFT 0 /* MICD_ENA */
1184#define WM8995_MICD_ENA_WIDTH 1 /* MICD_ENA */
1185
1186/*
1187 * R57 (0x39) - Mic Detect (2)
1188 */
1189#define WM8995_MICD_LVL_MASK 0x01FC /* MICD_LVL - [8:2] */
1190#define WM8995_MICD_LVL_SHIFT 2 /* MICD_LVL - [8:2] */
1191#define WM8995_MICD_LVL_WIDTH 7 /* MICD_LVL - [8:2] */
1192#define WM8995_MICD_VALID 0x0002 /* MICD_VALID */
1193#define WM8995_MICD_VALID_MASK 0x0002 /* MICD_VALID */
1194#define WM8995_MICD_VALID_SHIFT 1 /* MICD_VALID */
1195#define WM8995_MICD_VALID_WIDTH 1 /* MICD_VALID */
1196#define WM8995_MICD_STS 0x0001 /* MICD_STS */
1197#define WM8995_MICD_STS_MASK 0x0001 /* MICD_STS */
1198#define WM8995_MICD_STS_SHIFT 0 /* MICD_STS */
1199#define WM8995_MICD_STS_WIDTH 1 /* MICD_STS */
1200
1201/*
1202 * R64 (0x40) - Charge Pump (1)
1203 */
1204#define WM8995_CP_ENA 0x8000 /* CP_ENA */
1205#define WM8995_CP_ENA_MASK 0x8000 /* CP_ENA */
1206#define WM8995_CP_ENA_SHIFT 15 /* CP_ENA */
1207#define WM8995_CP_ENA_WIDTH 1 /* CP_ENA */
1208
1209/*
1210 * R69 (0x45) - Class W (1)
1211 */
1212#define WM8995_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */
1213#define WM8995_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */
1214#define WM8995_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */
1215#define WM8995_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */
1216#define WM8995_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */
1217#define WM8995_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */
1218#define WM8995_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */
1219
1220/*
1221 * R80 (0x50) - DC Servo (1)
1222 */
1223#define WM8995_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */
1224#define WM8995_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */
1225#define WM8995_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */
1226#define WM8995_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */
1227#define WM8995_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */
1228#define WM8995_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */
1229#define WM8995_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */
1230#define WM8995_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */
1231#define WM8995_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */
1232#define WM8995_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */
1233#define WM8995_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */
1234#define WM8995_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */
1235#define WM8995_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
1236#define WM8995_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
1237#define WM8995_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */
1238#define WM8995_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */
1239
1240/*
1241 * R81 (0x51) - DC Servo (2)
1242 */
1243#define WM8995_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */
1244#define WM8995_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */
1245#define WM8995_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */
1246#define WM8995_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */
1247#define WM8995_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */
1248#define WM8995_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */
1249#define WM8995_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */
1250#define WM8995_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */
1251#define WM8995_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */
1252#define WM8995_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */
1253#define WM8995_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */
1254#define WM8995_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */
1255#define WM8995_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */
1256#define WM8995_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */
1257#define WM8995_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */
1258#define WM8995_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */
1259#define WM8995_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */
1260#define WM8995_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */
1261#define WM8995_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */
1262#define WM8995_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */
1263#define WM8995_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */
1264#define WM8995_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */
1265#define WM8995_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */
1266#define WM8995_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */
1267#define WM8995_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */
1268#define WM8995_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */
1269#define WM8995_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */
1270#define WM8995_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */
1271#define WM8995_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */
1272#define WM8995_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */
1273#define WM8995_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */
1274#define WM8995_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */
1275#define WM8995_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */
1276#define WM8995_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */
1277#define WM8995_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */
1278#define WM8995_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */
1279#define WM8995_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */
1280#define WM8995_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */
1281#define WM8995_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */
1282#define WM8995_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */
1283#define WM8995_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */
1284#define WM8995_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */
1285#define WM8995_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */
1286#define WM8995_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */
1287#define WM8995_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */
1288#define WM8995_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */
1289#define WM8995_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */
1290#define WM8995_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */
1291#define WM8995_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */
1292#define WM8995_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */
1293#define WM8995_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */
1294#define WM8995_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */
1295#define WM8995_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */
1296#define WM8995_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */
1297#define WM8995_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */
1298#define WM8995_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */
1299#define WM8995_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */
1300#define WM8995_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */
1301#define WM8995_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */
1302#define WM8995_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */
1303#define WM8995_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */
1304#define WM8995_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */
1305#define WM8995_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */
1306#define WM8995_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */
1307
1308/*
1309 * R82 (0x52) - DC Servo (3)
1310 */
1311#define WM8995_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */
1312#define WM8995_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */
1313#define WM8995_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */
1314#define WM8995_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
1315#define WM8995_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
1316#define WM8995_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
1317
1318/*
1319 * R84 (0x54) - DC Servo (5)
1320 */
1321#define WM8995_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */
1322#define WM8995_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */
1323#define WM8995_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */
1324#define WM8995_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */
1325#define WM8995_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */
1326#define WM8995_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */
1327
1328/*
1329 * R85 (0x55) - DC Servo (6)
1330 */
1331#define WM8995_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */
1332#define WM8995_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */
1333#define WM8995_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */
1334#define WM8995_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */
1335#define WM8995_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */
1336#define WM8995_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */
1337
1338/*
1339 * R86 (0x56) - DC Servo (7)
1340 */
1341#define WM8995_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */
1342#define WM8995_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
1343#define WM8995_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
1344#define WM8995_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
1345#define WM8995_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
1346#define WM8995_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
1347
1348/*
1349 * R87 (0x57) - DC Servo Readback 0
1350 */
1351#define WM8995_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */
1352#define WM8995_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */
1353#define WM8995_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */
1354#define WM8995_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */
1355#define WM8995_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
1356#define WM8995_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
1357#define WM8995_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */
1358#define WM8995_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */
1359#define WM8995_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */
1360
1361/*
1362 * R96 (0x60) - Analogue HP (1)
1363 */
1364#define WM8995_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */
1365#define WM8995_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */
1366#define WM8995_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */
1367#define WM8995_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */
1368#define WM8995_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */
1369#define WM8995_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */
1370#define WM8995_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */
1371#define WM8995_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */
1372#define WM8995_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */
1373#define WM8995_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */
1374#define WM8995_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */
1375#define WM8995_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */
1376#define WM8995_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */
1377#define WM8995_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */
1378#define WM8995_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */
1379#define WM8995_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */
1380#define WM8995_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */
1381#define WM8995_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */
1382#define WM8995_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */
1383#define WM8995_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */
1384#define WM8995_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */
1385#define WM8995_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */
1386#define WM8995_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */
1387#define WM8995_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
1388
1389/*
1390 * R97 (0x61) - Analogue HP (2)
1391 */
1392#define WM8995_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */
1393#define WM8995_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */
1394#define WM8995_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */
1395#define WM8995_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */
1396#define WM8995_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */
1397#define WM8995_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */
1398#define WM8995_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */
1399#define WM8995_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */
1400#define WM8995_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */
1401#define WM8995_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */
1402#define WM8995_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */
1403#define WM8995_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */
1404#define WM8995_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */
1405#define WM8995_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */
1406#define WM8995_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */
1407#define WM8995_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */
1408#define WM8995_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */
1409#define WM8995_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */
1410#define WM8995_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */
1411#define WM8995_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */
1412#define WM8995_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */
1413#define WM8995_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */
1414#define WM8995_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */
1415#define WM8995_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */
1416
1417/*
1418 * R256 (0x100) - Chip Revision
1419 */
1420#define WM8995_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */
1421#define WM8995_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */
1422#define WM8995_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */
1423
1424/*
1425 * R257 (0x101) - Control Interface (1)
1426 */
1427#define WM8995_REG_SYNC 0x8000 /* REG_SYNC */
1428#define WM8995_REG_SYNC_MASK 0x8000 /* REG_SYNC */
1429#define WM8995_REG_SYNC_SHIFT 15 /* REG_SYNC */
1430#define WM8995_REG_SYNC_WIDTH 1 /* REG_SYNC */
1431#define WM8995_SPI_CONTRD 0x0040 /* SPI_CONTRD */
1432#define WM8995_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */
1433#define WM8995_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */
1434#define WM8995_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */
1435#define WM8995_SPI_4WIRE 0x0020 /* SPI_4WIRE */
1436#define WM8995_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */
1437#define WM8995_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */
1438#define WM8995_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
1439#define WM8995_SPI_CFG 0x0010 /* SPI_CFG */
1440#define WM8995_SPI_CFG_MASK 0x0010 /* SPI_CFG */
1441#define WM8995_SPI_CFG_SHIFT 4 /* SPI_CFG */
1442#define WM8995_SPI_CFG_WIDTH 1 /* SPI_CFG */
1443#define WM8995_AUTO_INC 0x0004 /* AUTO_INC */
1444#define WM8995_AUTO_INC_MASK 0x0004 /* AUTO_INC */
1445#define WM8995_AUTO_INC_SHIFT 2 /* AUTO_INC */
1446#define WM8995_AUTO_INC_WIDTH 1 /* AUTO_INC */
1447
1448/*
1449 * R258 (0x102) - Control Interface (2)
1450 */
1451#define WM8995_CTRL_IF_SRC 0x0001 /* CTRL_IF_SRC */
1452#define WM8995_CTRL_IF_SRC_MASK 0x0001 /* CTRL_IF_SRC */
1453#define WM8995_CTRL_IF_SRC_SHIFT 0 /* CTRL_IF_SRC */
1454#define WM8995_CTRL_IF_SRC_WIDTH 1 /* CTRL_IF_SRC */
1455
1456/*
1457 * R272 (0x110) - Write Sequencer Ctrl (1)
1458 */
1459#define WM8995_WSEQ_ENA 0x8000 /* WSEQ_ENA */
1460#define WM8995_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
1461#define WM8995_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
1462#define WM8995_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
1463#define WM8995_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
1464#define WM8995_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
1465#define WM8995_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
1466#define WM8995_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
1467#define WM8995_WSEQ_START 0x0100 /* WSEQ_START */
1468#define WM8995_WSEQ_START_MASK 0x0100 /* WSEQ_START */
1469#define WM8995_WSEQ_START_SHIFT 8 /* WSEQ_START */
1470#define WM8995_WSEQ_START_WIDTH 1 /* WSEQ_START */
1471#define WM8995_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
1472#define WM8995_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
1473#define WM8995_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
1474
1475/*
1476 * R273 (0x111) - Write Sequencer Ctrl (2)
1477 */
1478#define WM8995_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */
1479#define WM8995_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */
1480#define WM8995_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */
1481#define WM8995_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
1482#define WM8995_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */
1483#define WM8995_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */
1484#define WM8995_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */
1485
1486/*
1487 * R512 (0x200) - AIF1 Clocking (1)
1488 */
1489#define WM8995_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */
1490#define WM8995_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */
1491#define WM8995_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */
1492#define WM8995_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */
1493#define WM8995_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */
1494#define WM8995_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */
1495#define WM8995_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */
1496#define WM8995_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */
1497#define WM8995_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */
1498#define WM8995_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */
1499#define WM8995_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */
1500#define WM8995_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */
1501#define WM8995_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */
1502#define WM8995_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */
1503#define WM8995_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */
1504
1505/*
1506 * R513 (0x201) - AIF1 Clocking (2)
1507 */
1508#define WM8995_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */
1509#define WM8995_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */
1510#define WM8995_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */
1511#define WM8995_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */
1512#define WM8995_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */
1513#define WM8995_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */
1514
1515/*
1516 * R516 (0x204) - AIF2 Clocking (1)
1517 */
1518#define WM8995_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */
1519#define WM8995_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */
1520#define WM8995_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */
1521#define WM8995_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */
1522#define WM8995_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */
1523#define WM8995_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */
1524#define WM8995_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */
1525#define WM8995_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */
1526#define WM8995_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */
1527#define WM8995_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */
1528#define WM8995_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */
1529#define WM8995_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */
1530#define WM8995_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */
1531#define WM8995_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */
1532#define WM8995_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */
1533
1534/*
1535 * R517 (0x205) - AIF2 Clocking (2)
1536 */
1537#define WM8995_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */
1538#define WM8995_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */
1539#define WM8995_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */
1540#define WM8995_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */
1541#define WM8995_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */
1542#define WM8995_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */
1543
1544/*
1545 * R520 (0x208) - Clocking (1)
1546 */
1547#define WM8995_LFCLK_ENA 0x0020 /* LFCLK_ENA */
1548#define WM8995_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */
1549#define WM8995_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */
1550#define WM8995_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */
1551#define WM8995_TOCLK_ENA 0x0010 /* TOCLK_ENA */
1552#define WM8995_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */
1553#define WM8995_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */
1554#define WM8995_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
1555#define WM8995_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */
1556#define WM8995_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */
1557#define WM8995_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */
1558#define WM8995_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */
1559#define WM8995_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */
1560#define WM8995_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */
1561#define WM8995_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */
1562#define WM8995_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */
1563#define WM8995_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */
1564#define WM8995_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */
1565#define WM8995_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */
1566#define WM8995_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */
1567#define WM8995_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */
1568#define WM8995_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */
1569#define WM8995_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */
1570#define WM8995_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */
1571
1572/*
1573 * R521 (0x209) - Clocking (2)
1574 */
1575#define WM8995_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */
1576#define WM8995_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */
1577#define WM8995_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */
1578#define WM8995_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */
1579#define WM8995_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */
1580#define WM8995_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */
1581#define WM8995_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */
1582#define WM8995_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */
1583#define WM8995_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */
1584
1585/*
1586 * R528 (0x210) - AIF1 Rate
1587 */
1588#define WM8995_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */
1589#define WM8995_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */
1590#define WM8995_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */
1591#define WM8995_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */
1592#define WM8995_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */
1593#define WM8995_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */
1594
1595/*
1596 * R529 (0x211) - AIF2 Rate
1597 */
1598#define WM8995_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */
1599#define WM8995_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */
1600#define WM8995_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */
1601#define WM8995_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */
1602#define WM8995_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */
1603#define WM8995_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */
1604
1605/*
1606 * R530 (0x212) - Rate Status
1607 */
1608#define WM8995_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */
1609#define WM8995_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */
1610#define WM8995_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */
1611
1612/*
1613 * R544 (0x220) - FLL1 Control (1)
1614 */
1615#define WM8995_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */
1616#define WM8995_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */
1617#define WM8995_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */
1618#define WM8995_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */
1619#define WM8995_FLL1_ENA 0x0001 /* FLL1_ENA */
1620#define WM8995_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */
1621#define WM8995_FLL1_ENA_SHIFT 0 /* FLL1_ENA */
1622#define WM8995_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
1623
1624/*
1625 * R545 (0x221) - FLL1 Control (2)
1626 */
1627#define WM8995_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */
1628#define WM8995_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */
1629#define WM8995_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */
1630#define WM8995_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */
1631#define WM8995_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */
1632#define WM8995_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */
1633#define WM8995_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */
1634#define WM8995_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */
1635#define WM8995_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */
1636
1637/*
1638 * R546 (0x222) - FLL1 Control (3)
1639 */
1640#define WM8995_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */
1641#define WM8995_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */
1642#define WM8995_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */
1643
1644/*
1645 * R547 (0x223) - FLL1 Control (4)
1646 */
1647#define WM8995_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */
1648#define WM8995_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */
1649#define WM8995_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */
1650#define WM8995_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */
1651#define WM8995_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */
1652#define WM8995_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */
1653
1654/*
1655 * R548 (0x224) - FLL1 Control (5)
1656 */
1657#define WM8995_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */
1658#define WM8995_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */
1659#define WM8995_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */
1660#define WM8995_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */
1661#define WM8995_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */
1662#define WM8995_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */
1663#define WM8995_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */
1664#define WM8995_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */
1665#define WM8995_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */
1666#define WM8995_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */
1667#define WM8995_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */
1668#define WM8995_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */
1669#define WM8995_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */
1670
1671/*
1672 * R576 (0x240) - FLL2 Control (1)
1673 */
1674#define WM8995_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */
1675#define WM8995_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */
1676#define WM8995_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */
1677#define WM8995_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */
1678#define WM8995_FLL2_ENA 0x0001 /* FLL2_ENA */
1679#define WM8995_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */
1680#define WM8995_FLL2_ENA_SHIFT 0 /* FLL2_ENA */
1681#define WM8995_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
1682
1683/*
1684 * R577 (0x241) - FLL2 Control (2)
1685 */
1686#define WM8995_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */
1687#define WM8995_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */
1688#define WM8995_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */
1689#define WM8995_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */
1690#define WM8995_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */
1691#define WM8995_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */
1692#define WM8995_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */
1693#define WM8995_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */
1694#define WM8995_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */
1695
1696/*
1697 * R578 (0x242) - FLL2 Control (3)
1698 */
1699#define WM8995_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */
1700#define WM8995_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */
1701#define WM8995_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */
1702
1703/*
1704 * R579 (0x243) - FLL2 Control (4)
1705 */
1706#define WM8995_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */
1707#define WM8995_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */
1708#define WM8995_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */
1709#define WM8995_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */
1710#define WM8995_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */
1711#define WM8995_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */
1712
1713/*
1714 * R580 (0x244) - FLL2 Control (5)
1715 */
1716#define WM8995_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */
1717#define WM8995_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */
1718#define WM8995_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */
1719#define WM8995_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */
1720#define WM8995_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */
1721#define WM8995_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */
1722#define WM8995_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */
1723#define WM8995_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */
1724#define WM8995_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */
1725#define WM8995_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */
1726#define WM8995_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */
1727#define WM8995_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */
1728#define WM8995_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */
1729
1730/*
1731 * R768 (0x300) - AIF1 Control (1)
1732 */
1733#define WM8995_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */
1734#define WM8995_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */
1735#define WM8995_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */
1736#define WM8995_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */
1737#define WM8995_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */
1738#define WM8995_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */
1739#define WM8995_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */
1740#define WM8995_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */
1741#define WM8995_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */
1742#define WM8995_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */
1743#define WM8995_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */
1744#define WM8995_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */
1745#define WM8995_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */
1746#define WM8995_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */
1747#define WM8995_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */
1748#define WM8995_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
1749#define WM8995_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */
1750#define WM8995_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */
1751#define WM8995_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */
1752#define WM8995_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */
1753#define WM8995_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */
1754#define WM8995_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */
1755#define WM8995_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */
1756#define WM8995_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */
1757#define WM8995_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */
1758#define WM8995_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */
1759
1760/*
1761 * R769 (0x301) - AIF1 Control (2)
1762 */
1763#define WM8995_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */
1764#define WM8995_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */
1765#define WM8995_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */
1766#define WM8995_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */
1767#define WM8995_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */
1768#define WM8995_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */
1769#define WM8995_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */
1770#define WM8995_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */
1771#define WM8995_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */
1772#define WM8995_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */
1773#define WM8995_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */
1774#define WM8995_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */
1775#define WM8995_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */
1776#define WM8995_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */
1777#define WM8995_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */
1778#define WM8995_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */
1779#define WM8995_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */
1780#define WM8995_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */
1781#define WM8995_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */
1782#define WM8995_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */
1783#define WM8995_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */
1784#define WM8995_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */
1785#define WM8995_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */
1786#define WM8995_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */
1787#define WM8995_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */
1788#define WM8995_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */
1789#define WM8995_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */
1790#define WM8995_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */
1791#define WM8995_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */
1792#define WM8995_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */
1793#define WM8995_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */
1794
1795/*
1796 * R770 (0x302) - AIF1 Master/Slave
1797 */
1798#define WM8995_AIF1_TRI 0x8000 /* AIF1_TRI */
1799#define WM8995_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */
1800#define WM8995_AIF1_TRI_SHIFT 15 /* AIF1_TRI */
1801#define WM8995_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
1802#define WM8995_AIF1_MSTR 0x4000 /* AIF1_MSTR */
1803#define WM8995_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */
1804#define WM8995_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */
1805#define WM8995_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */
1806#define WM8995_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */
1807#define WM8995_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */
1808#define WM8995_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */
1809#define WM8995_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */
1810#define WM8995_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */
1811#define WM8995_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */
1812#define WM8995_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */
1813#define WM8995_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */
1814
1815/*
1816 * R771 (0x303) - AIF1 BCLK
1817 */
1818#define WM8995_AIF1_BCLK_DIV_MASK 0x00F0 /* AIF1_BCLK_DIV - [7:4] */
1819#define WM8995_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [7:4] */
1820#define WM8995_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [7:4] */
1821
1822/*
1823 * R772 (0x304) - AIF1ADC LRCLK
1824 */
1825#define WM8995_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */
1826#define WM8995_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */
1827#define WM8995_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */
1828#define WM8995_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */
1829#define WM8995_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */
1830#define WM8995_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */
1831#define WM8995_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */
1832
1833/*
1834 * R773 (0x305) - AIF1DAC LRCLK
1835 */
1836#define WM8995_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */
1837#define WM8995_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */
1838#define WM8995_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */
1839#define WM8995_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */
1840#define WM8995_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */
1841#define WM8995_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */
1842#define WM8995_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */
1843
1844/*
1845 * R774 (0x306) - AIF1DAC Data
1846 */
1847#define WM8995_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */
1848#define WM8995_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */
1849#define WM8995_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */
1850#define WM8995_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */
1851#define WM8995_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */
1852#define WM8995_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */
1853#define WM8995_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */
1854#define WM8995_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */
1855
1856/*
1857 * R775 (0x307) - AIF1ADC Data
1858 */
1859#define WM8995_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */
1860#define WM8995_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */
1861#define WM8995_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */
1862#define WM8995_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */
1863#define WM8995_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */
1864#define WM8995_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */
1865#define WM8995_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */
1866#define WM8995_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */
1867
1868/*
1869 * R784 (0x310) - AIF2 Control (1)
1870 */
1871#define WM8995_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */
1872#define WM8995_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */
1873#define WM8995_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */
1874#define WM8995_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */
1875#define WM8995_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */
1876#define WM8995_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */
1877#define WM8995_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */
1878#define WM8995_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */
1879#define WM8995_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */
1880#define WM8995_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */
1881#define WM8995_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */
1882#define WM8995_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */
1883#define WM8995_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */
1884#define WM8995_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */
1885#define WM8995_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */
1886#define WM8995_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */
1887#define WM8995_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */
1888#define WM8995_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */
1889#define WM8995_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */
1890#define WM8995_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
1891#define WM8995_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */
1892#define WM8995_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */
1893#define WM8995_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */
1894#define WM8995_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */
1895#define WM8995_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */
1896#define WM8995_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */
1897#define WM8995_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */
1898#define WM8995_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */
1899#define WM8995_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */
1900#define WM8995_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */
1901
1902/*
1903 * R785 (0x311) - AIF2 Control (2)
1904 */
1905#define WM8995_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */
1906#define WM8995_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */
1907#define WM8995_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */
1908#define WM8995_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */
1909#define WM8995_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */
1910#define WM8995_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */
1911#define WM8995_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */
1912#define WM8995_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */
1913#define WM8995_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */
1914#define WM8995_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */
1915#define WM8995_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */
1916#define WM8995_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */
1917#define WM8995_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */
1918#define WM8995_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */
1919#define WM8995_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */
1920#define WM8995_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */
1921#define WM8995_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */
1922#define WM8995_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */
1923#define WM8995_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */
1924#define WM8995_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */
1925#define WM8995_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */
1926#define WM8995_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */
1927#define WM8995_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */
1928#define WM8995_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */
1929#define WM8995_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */
1930#define WM8995_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */
1931#define WM8995_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */
1932#define WM8995_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */
1933#define WM8995_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */
1934#define WM8995_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */
1935#define WM8995_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */
1936#define WM8995_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */
1937#define WM8995_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */
1938#define WM8995_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */
1939#define WM8995_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */
1940#define WM8995_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */
1941#define WM8995_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */
1942#define WM8995_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */
1943#define WM8995_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */
1944
1945/*
1946 * R786 (0x312) - AIF2 Master/Slave
1947 */
1948#define WM8995_AIF2_TRI 0x8000 /* AIF2_TRI */
1949#define WM8995_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */
1950#define WM8995_AIF2_TRI_SHIFT 15 /* AIF2_TRI */
1951#define WM8995_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
1952#define WM8995_AIF2_MSTR 0x4000 /* AIF2_MSTR */
1953#define WM8995_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */
1954#define WM8995_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */
1955#define WM8995_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */
1956#define WM8995_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */
1957#define WM8995_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */
1958#define WM8995_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */
1959#define WM8995_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */
1960#define WM8995_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */
1961#define WM8995_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */
1962#define WM8995_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */
1963#define WM8995_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */
1964
1965/*
1966 * R787 (0x313) - AIF2 BCLK
1967 */
1968#define WM8995_AIF2_BCLK_DIV_MASK 0x00F0 /* AIF2_BCLK_DIV - [7:4] */
1969#define WM8995_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [7:4] */
1970#define WM8995_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [7:4] */
1971
1972/*
1973 * R788 (0x314) - AIF2ADC LRCLK
1974 */
1975#define WM8995_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */
1976#define WM8995_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */
1977#define WM8995_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */
1978#define WM8995_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */
1979#define WM8995_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */
1980#define WM8995_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */
1981#define WM8995_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */
1982
1983/*
1984 * R789 (0x315) - AIF2DAC LRCLK
1985 */
1986#define WM8995_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */
1987#define WM8995_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */
1988#define WM8995_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */
1989#define WM8995_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */
1990#define WM8995_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */
1991#define WM8995_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */
1992#define WM8995_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */
1993
1994/*
1995 * R790 (0x316) - AIF2DAC Data
1996 */
1997#define WM8995_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */
1998#define WM8995_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */
1999#define WM8995_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */
2000#define WM8995_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */
2001#define WM8995_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */
2002#define WM8995_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */
2003#define WM8995_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */
2004#define WM8995_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */
2005
2006/*
2007 * R791 (0x317) - AIF2ADC Data
2008 */
2009#define WM8995_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */
2010#define WM8995_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */
2011#define WM8995_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */
2012#define WM8995_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */
2013#define WM8995_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */
2014#define WM8995_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */
2015#define WM8995_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */
2016#define WM8995_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */
2017
2018/*
2019 * R1024 (0x400) - AIF1 ADC1 Left Volume
2020 */
2021#define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
2022#define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */
2023#define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */
2024#define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
2025#define WM8995_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */
2026#define WM8995_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */
2027#define WM8995_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */
2028
2029/*
2030 * R1025 (0x401) - AIF1 ADC1 Right Volume
2031 */
2032#define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
2033#define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */
2034#define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */
2035#define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
2036#define WM8995_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */
2037#define WM8995_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */
2038#define WM8995_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */
2039
2040/*
2041 * R1026 (0x402) - AIF1 DAC1 Left Volume
2042 */
2043#define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */
2044#define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */
2045#define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */
2046#define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
2047#define WM8995_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */
2048#define WM8995_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */
2049#define WM8995_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */
2050
2051/*
2052 * R1027 (0x403) - AIF1 DAC1 Right Volume
2053 */
2054#define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */
2055#define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */
2056#define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */
2057#define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
2058#define WM8995_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */
2059#define WM8995_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */
2060#define WM8995_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */
2061
2062/*
2063 * R1028 (0x404) - AIF1 ADC2 Left Volume
2064 */
2065#define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */
2066#define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */
2067#define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */
2068#define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
2069#define WM8995_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */
2070#define WM8995_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */
2071#define WM8995_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */
2072
2073/*
2074 * R1029 (0x405) - AIF1 ADC2 Right Volume
2075 */
2076#define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */
2077#define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */
2078#define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */
2079#define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
2080#define WM8995_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */
2081#define WM8995_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */
2082#define WM8995_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */
2083
2084/*
2085 * R1030 (0x406) - AIF1 DAC2 Left Volume
2086 */
2087#define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */
2088#define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */
2089#define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */
2090#define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
2091#define WM8995_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */
2092#define WM8995_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */
2093#define WM8995_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */
2094
2095/*
2096 * R1031 (0x407) - AIF1 DAC2 Right Volume
2097 */
2098#define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */
2099#define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */
2100#define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */
2101#define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
2102#define WM8995_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */
2103#define WM8995_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */
2104#define WM8995_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */
2105
2106/*
2107 * R1040 (0x410) - AIF1 ADC1 Filters
2108 */
2109#define WM8995_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */
2110#define WM8995_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */
2111#define WM8995_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */
2112#define WM8995_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */
2113#define WM8995_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */
2114#define WM8995_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */
2115#define WM8995_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */
2116#define WM8995_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */
2117#define WM8995_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */
2118#define WM8995_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */
2119#define WM8995_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */
2120#define WM8995_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */
2121#define WM8995_AIF1ADC1_HPF_MODE 0x0008 /* AIF1ADC1_HPF_MODE */
2122#define WM8995_AIF1ADC1_HPF_MODE_MASK 0x0008 /* AIF1ADC1_HPF_MODE */
2123#define WM8995_AIF1ADC1_HPF_MODE_SHIFT 3 /* AIF1ADC1_HPF_MODE */
2124#define WM8995_AIF1ADC1_HPF_MODE_WIDTH 1 /* AIF1ADC1_HPF_MODE */
2125#define WM8995_AIF1ADC1_HPF_CUT_MASK 0x0007 /* AIF1ADC1_HPF_CUT - [2:0] */
2126#define WM8995_AIF1ADC1_HPF_CUT_SHIFT 0 /* AIF1ADC1_HPF_CUT - [2:0] */
2127#define WM8995_AIF1ADC1_HPF_CUT_WIDTH 3 /* AIF1ADC1_HPF_CUT - [2:0] */
2128
2129/*
2130 * R1041 (0x411) - AIF1 ADC2 Filters
2131 */
2132#define WM8995_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */
2133#define WM8995_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */
2134#define WM8995_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */
2135#define WM8995_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */
2136#define WM8995_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */
2137#define WM8995_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */
2138#define WM8995_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */
2139#define WM8995_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */
2140#define WM8995_AIF1ADC2_HPF_MODE 0x0008 /* AIF1ADC2_HPF_MODE */
2141#define WM8995_AIF1ADC2_HPF_MODE_MASK 0x0008 /* AIF1ADC2_HPF_MODE */
2142#define WM8995_AIF1ADC2_HPF_MODE_SHIFT 3 /* AIF1ADC2_HPF_MODE */
2143#define WM8995_AIF1ADC2_HPF_MODE_WIDTH 1 /* AIF1ADC2_HPF_MODE */
2144#define WM8995_AIF1ADC2_HPF_CUT_MASK 0x0007 /* AIF1ADC2_HPF_CUT - [2:0] */
2145#define WM8995_AIF1ADC2_HPF_CUT_SHIFT 0 /* AIF1ADC2_HPF_CUT - [2:0] */
2146#define WM8995_AIF1ADC2_HPF_CUT_WIDTH 3 /* AIF1ADC2_HPF_CUT - [2:0] */
2147
2148/*
2149 * R1056 (0x420) - AIF1 DAC1 Filters (1)
2150 */
2151#define WM8995_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */
2152#define WM8995_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */
2153#define WM8995_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */
2154#define WM8995_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */
2155#define WM8995_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */
2156#define WM8995_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */
2157#define WM8995_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */
2158#define WM8995_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */
2159#define WM8995_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */
2160#define WM8995_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */
2161#define WM8995_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */
2162#define WM8995_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */
2163#define WM8995_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */
2164#define WM8995_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */
2165#define WM8995_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */
2166#define WM8995_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */
2167#define WM8995_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */
2168#define WM8995_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */
2169#define WM8995_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */
2170
2171/*
2172 * R1057 (0x421) - AIF1 DAC1 Filters (2)
2173 */
2174#define WM8995_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */
2175#define WM8995_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */
2176#define WM8995_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */
2177#define WM8995_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */
2178#define WM8995_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */
2179#define WM8995_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */
2180#define WM8995_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */
2181
2182/*
2183 * R1058 (0x422) - AIF1 DAC2 Filters (1)
2184 */
2185#define WM8995_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */
2186#define WM8995_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */
2187#define WM8995_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */
2188#define WM8995_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */
2189#define WM8995_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */
2190#define WM8995_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */
2191#define WM8995_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */
2192#define WM8995_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */
2193#define WM8995_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */
2194#define WM8995_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */
2195#define WM8995_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */
2196#define WM8995_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */
2197#define WM8995_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */
2198#define WM8995_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */
2199#define WM8995_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */
2200#define WM8995_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */
2201#define WM8995_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */
2202#define WM8995_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */
2203#define WM8995_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */
2204
2205/*
2206 * R1059 (0x423) - AIF1 DAC2 Filters (2)
2207 */
2208#define WM8995_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */
2209#define WM8995_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */
2210#define WM8995_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */
2211#define WM8995_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */
2212#define WM8995_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */
2213#define WM8995_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */
2214#define WM8995_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */
2215
2216/*
2217 * R1088 (0x440) - AIF1 DRC1 (1)
2218 */
2219#define WM8995_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
2220#define WM8995_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
2221#define WM8995_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
2222#define WM8995_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */
2223#define WM8995_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */
2224#define WM8995_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */
2225#define WM8995_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */
2226#define WM8995_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */
2227#define WM8995_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */
2228#define WM8995_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */
2229#define WM8995_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */
2230#define WM8995_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */
2231#define WM8995_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */
2232#define WM8995_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */
2233#define WM8995_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */
2234#define WM8995_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */
2235#define WM8995_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */
2236#define WM8995_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */
2237#define WM8995_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */
2238#define WM8995_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */
2239#define WM8995_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */
2240#define WM8995_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */
2241#define WM8995_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */
2242#define WM8995_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */
2243#define WM8995_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */
2244#define WM8995_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */
2245#define WM8995_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */
2246#define WM8995_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */
2247#define WM8995_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */
2248#define WM8995_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */
2249#define WM8995_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */
2250#define WM8995_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */
2251#define WM8995_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */
2252#define WM8995_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */
2253#define WM8995_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */
2254#define WM8995_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */
2255#define WM8995_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */
2256#define WM8995_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */
2257#define WM8995_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */
2258#define WM8995_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */
2259#define WM8995_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */
2260#define WM8995_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */
2261
2262/*
2263 * R1089 (0x441) - AIF1 DRC1 (2)
2264 */
2265#define WM8995_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */
2266#define WM8995_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */
2267#define WM8995_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */
2268#define WM8995_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */
2269#define WM8995_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */
2270#define WM8995_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */
2271#define WM8995_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */
2272#define WM8995_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */
2273#define WM8995_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */
2274#define WM8995_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */
2275#define WM8995_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */
2276#define WM8995_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */
2277
2278/*
2279 * R1090 (0x442) - AIF1 DRC1 (3)
2280 */
2281#define WM8995_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */
2282#define WM8995_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */
2283#define WM8995_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */
2284#define WM8995_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */
2285#define WM8995_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */
2286#define WM8995_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */
2287#define WM8995_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */
2288#define WM8995_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */
2289#define WM8995_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */
2290#define WM8995_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */
2291#define WM8995_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */
2292#define WM8995_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */
2293#define WM8995_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */
2294#define WM8995_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */
2295#define WM8995_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */
2296#define WM8995_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */
2297#define WM8995_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */
2298#define WM8995_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */
2299
2300/*
2301 * R1091 (0x443) - AIF1 DRC1 (4)
2302 */
2303#define WM8995_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */
2304#define WM8995_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */
2305#define WM8995_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */
2306#define WM8995_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */
2307#define WM8995_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */
2308#define WM8995_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */
2309
2310/*
2311 * R1092 (0x444) - AIF1 DRC1 (5)
2312 */
2313#define WM8995_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */
2314#define WM8995_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
2315#define WM8995_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
2316#define WM8995_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */
2317#define WM8995_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */
2318#define WM8995_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */
2319
2320/*
2321 * R1104 (0x450) - AIF1 DRC2 (1)
2322 */
2323#define WM8995_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
2324#define WM8995_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
2325#define WM8995_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
2326#define WM8995_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */
2327#define WM8995_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */
2328#define WM8995_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */
2329#define WM8995_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */
2330#define WM8995_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */
2331#define WM8995_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */
2332#define WM8995_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */
2333#define WM8995_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */
2334#define WM8995_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */
2335#define WM8995_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */
2336#define WM8995_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */
2337#define WM8995_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */
2338#define WM8995_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */
2339#define WM8995_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */
2340#define WM8995_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */
2341#define WM8995_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */
2342#define WM8995_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */
2343#define WM8995_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */
2344#define WM8995_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */
2345#define WM8995_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */
2346#define WM8995_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */
2347#define WM8995_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */
2348#define WM8995_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */
2349#define WM8995_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */
2350#define WM8995_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */
2351#define WM8995_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */
2352#define WM8995_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */
2353#define WM8995_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */
2354#define WM8995_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */
2355#define WM8995_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */
2356#define WM8995_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */
2357#define WM8995_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */
2358#define WM8995_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */
2359#define WM8995_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */
2360#define WM8995_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */
2361#define WM8995_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */
2362#define WM8995_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */
2363#define WM8995_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */
2364#define WM8995_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */
2365
2366/*
2367 * R1105 (0x451) - AIF1 DRC2 (2)
2368 */
2369#define WM8995_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */
2370#define WM8995_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */
2371#define WM8995_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */
2372#define WM8995_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */
2373#define WM8995_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */
2374#define WM8995_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */
2375#define WM8995_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */
2376#define WM8995_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */
2377#define WM8995_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */
2378#define WM8995_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */
2379#define WM8995_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */
2380#define WM8995_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */
2381
2382/*
2383 * R1106 (0x452) - AIF1 DRC2 (3)
2384 */
2385#define WM8995_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */
2386#define WM8995_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */
2387#define WM8995_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */
2388#define WM8995_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */
2389#define WM8995_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */
2390#define WM8995_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */
2391#define WM8995_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */
2392#define WM8995_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */
2393#define WM8995_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */
2394#define WM8995_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */
2395#define WM8995_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */
2396#define WM8995_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */
2397#define WM8995_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */
2398#define WM8995_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */
2399#define WM8995_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */
2400#define WM8995_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */
2401#define WM8995_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */
2402#define WM8995_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */
2403
2404/*
2405 * R1107 (0x453) - AIF1 DRC2 (4)
2406 */
2407#define WM8995_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */
2408#define WM8995_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */
2409#define WM8995_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */
2410#define WM8995_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */
2411#define WM8995_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */
2412#define WM8995_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */
2413
2414/*
2415 * R1108 (0x454) - AIF1 DRC2 (5)
2416 */
2417#define WM8995_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */
2418#define WM8995_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
2419#define WM8995_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
2420#define WM8995_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */
2421#define WM8995_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */
2422#define WM8995_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */
2423
2424/*
2425 * R1152 (0x480) - AIF1 DAC1 EQ Gains (1)
2426 */
2427#define WM8995_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
2428#define WM8995_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
2429#define WM8995_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
2430#define WM8995_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
2431#define WM8995_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
2432#define WM8995_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
2433#define WM8995_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
2434#define WM8995_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
2435#define WM8995_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
2436#define WM8995_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */
2437#define WM8995_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */
2438#define WM8995_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */
2439#define WM8995_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */
2440
2441/*
2442 * R1153 (0x481) - AIF1 DAC1 EQ Gains (2)
2443 */
2444#define WM8995_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
2445#define WM8995_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
2446#define WM8995_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
2447#define WM8995_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
2448#define WM8995_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
2449#define WM8995_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
2450
2451/*
2452 * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A
2453 */
2454#define WM8995_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */
2455#define WM8995_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */
2456#define WM8995_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */
2457
2458/*
2459 * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B
2460 */
2461#define WM8995_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */
2462#define WM8995_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */
2463#define WM8995_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */
2464
2465/*
2466 * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG
2467 */
2468#define WM8995_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */
2469#define WM8995_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */
2470#define WM8995_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */
2471
2472/*
2473 * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A
2474 */
2475#define WM8995_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */
2476#define WM8995_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */
2477#define WM8995_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */
2478
2479/*
2480 * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B
2481 */
2482#define WM8995_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */
2483#define WM8995_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */
2484#define WM8995_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */
2485
2486/*
2487 * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C
2488 */
2489#define WM8995_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */
2490#define WM8995_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */
2491#define WM8995_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */
2492
2493/*
2494 * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG
2495 */
2496#define WM8995_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */
2497#define WM8995_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */
2498#define WM8995_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */
2499
2500/*
2501 * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A
2502 */
2503#define WM8995_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */
2504#define WM8995_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */
2505#define WM8995_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */
2506
2507/*
2508 * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B
2509 */
2510#define WM8995_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */
2511#define WM8995_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */
2512#define WM8995_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */
2513
2514/*
2515 * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C
2516 */
2517#define WM8995_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */
2518#define WM8995_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */
2519#define WM8995_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */
2520
2521/*
2522 * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG
2523 */
2524#define WM8995_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */
2525#define WM8995_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */
2526#define WM8995_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */
2527
2528/*
2529 * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A
2530 */
2531#define WM8995_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */
2532#define WM8995_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */
2533#define WM8995_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */
2534
2535/*
2536 * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B
2537 */
2538#define WM8995_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */
2539#define WM8995_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */
2540#define WM8995_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */
2541
2542/*
2543 * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C
2544 */
2545#define WM8995_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */
2546#define WM8995_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */
2547#define WM8995_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */
2548
2549/*
2550 * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG
2551 */
2552#define WM8995_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */
2553#define WM8995_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */
2554#define WM8995_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */
2555
2556/*
2557 * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A
2558 */
2559#define WM8995_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */
2560#define WM8995_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */
2561#define WM8995_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */
2562
2563/*
2564 * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B
2565 */
2566#define WM8995_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */
2567#define WM8995_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */
2568#define WM8995_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */
2569
2570/*
2571 * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG
2572 */
2573#define WM8995_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */
2574#define WM8995_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */
2575#define WM8995_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */
2576
2577/*
2578 * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1)
2579 */
2580#define WM8995_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
2581#define WM8995_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
2582#define WM8995_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
2583#define WM8995_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
2584#define WM8995_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
2585#define WM8995_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
2586#define WM8995_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
2587#define WM8995_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
2588#define WM8995_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
2589#define WM8995_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */
2590#define WM8995_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */
2591#define WM8995_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */
2592#define WM8995_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */
2593
2594/*
2595 * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2)
2596 */
2597#define WM8995_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
2598#define WM8995_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
2599#define WM8995_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
2600#define WM8995_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
2601#define WM8995_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
2602#define WM8995_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
2603
2604/*
2605 * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A
2606 */
2607#define WM8995_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */
2608#define WM8995_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */
2609#define WM8995_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */
2610
2611/*
2612 * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B
2613 */
2614#define WM8995_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */
2615#define WM8995_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */
2616#define WM8995_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */
2617
2618/*
2619 * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG
2620 */
2621#define WM8995_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */
2622#define WM8995_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */
2623#define WM8995_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */
2624
2625/*
2626 * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A
2627 */
2628#define WM8995_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */
2629#define WM8995_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */
2630#define WM8995_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */
2631
2632/*
2633 * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B
2634 */
2635#define WM8995_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */
2636#define WM8995_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */
2637#define WM8995_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */
2638
2639/*
2640 * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C
2641 */
2642#define WM8995_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */
2643#define WM8995_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */
2644#define WM8995_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */
2645
2646/*
2647 * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG
2648 */
2649#define WM8995_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */
2650#define WM8995_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */
2651#define WM8995_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */
2652
2653/*
2654 * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A
2655 */
2656#define WM8995_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */
2657#define WM8995_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */
2658#define WM8995_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */
2659
2660/*
2661 * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B
2662 */
2663#define WM8995_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */
2664#define WM8995_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */
2665#define WM8995_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */
2666
2667/*
2668 * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C
2669 */
2670#define WM8995_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */
2671#define WM8995_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */
2672#define WM8995_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */
2673
2674/*
2675 * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG
2676 */
2677#define WM8995_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */
2678#define WM8995_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */
2679#define WM8995_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */
2680
2681/*
2682 * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A
2683 */
2684#define WM8995_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */
2685#define WM8995_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */
2686#define WM8995_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */
2687
2688/*
2689 * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B
2690 */
2691#define WM8995_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */
2692#define WM8995_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */
2693#define WM8995_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */
2694
2695/*
2696 * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C
2697 */
2698#define WM8995_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */
2699#define WM8995_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */
2700#define WM8995_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */
2701
2702/*
2703 * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG
2704 */
2705#define WM8995_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */
2706#define WM8995_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */
2707#define WM8995_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */
2708
2709/*
2710 * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A
2711 */
2712#define WM8995_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */
2713#define WM8995_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */
2714#define WM8995_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */
2715
2716/*
2717 * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B
2718 */
2719#define WM8995_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */
2720#define WM8995_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */
2721#define WM8995_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */
2722
2723/*
2724 * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG
2725 */
2726#define WM8995_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */
2727#define WM8995_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */
2728#define WM8995_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */
2729
2730/*
2731 * R1280 (0x500) - AIF2 ADC Left Volume
2732 */
2733#define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */
2734#define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */
2735#define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */
2736#define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
2737#define WM8995_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */
2738#define WM8995_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */
2739#define WM8995_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */
2740
2741/*
2742 * R1281 (0x501) - AIF2 ADC Right Volume
2743 */
2744#define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */
2745#define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */
2746#define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */
2747#define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
2748#define WM8995_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */
2749#define WM8995_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */
2750#define WM8995_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */
2751
2752/*
2753 * R1282 (0x502) - AIF2 DAC Left Volume
2754 */
2755#define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */
2756#define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */
2757#define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */
2758#define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
2759#define WM8995_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */
2760#define WM8995_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */
2761#define WM8995_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */
2762
2763/*
2764 * R1283 (0x503) - AIF2 DAC Right Volume
2765 */
2766#define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */
2767#define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */
2768#define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */
2769#define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
2770#define WM8995_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */
2771#define WM8995_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */
2772#define WM8995_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */
2773
2774/*
2775 * R1296 (0x510) - AIF2 ADC Filters
2776 */
2777#define WM8995_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */
2778#define WM8995_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */
2779#define WM8995_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */
2780#define WM8995_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */
2781#define WM8995_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */
2782#define WM8995_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */
2783#define WM8995_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */
2784#define WM8995_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */
2785#define WM8995_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */
2786#define WM8995_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */
2787#define WM8995_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */
2788#define WM8995_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */
2789#define WM8995_AIF2ADC_HPF_MODE 0x0008 /* AIF2ADC_HPF_MODE */
2790#define WM8995_AIF2ADC_HPF_MODE_MASK 0x0008 /* AIF2ADC_HPF_MODE */
2791#define WM8995_AIF2ADC_HPF_MODE_SHIFT 3 /* AIF2ADC_HPF_MODE */
2792#define WM8995_AIF2ADC_HPF_MODE_WIDTH 1 /* AIF2ADC_HPF_MODE */
2793#define WM8995_AIF2ADC_HPF_CUT_MASK 0x0007 /* AIF2ADC_HPF_CUT - [2:0] */
2794#define WM8995_AIF2ADC_HPF_CUT_SHIFT 0 /* AIF2ADC_HPF_CUT - [2:0] */
2795#define WM8995_AIF2ADC_HPF_CUT_WIDTH 3 /* AIF2ADC_HPF_CUT - [2:0] */
2796
2797/*
2798 * R1312 (0x520) - AIF2 DAC Filters (1)
2799 */
2800#define WM8995_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */
2801#define WM8995_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */
2802#define WM8995_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */
2803#define WM8995_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */
2804#define WM8995_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */
2805#define WM8995_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */
2806#define WM8995_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */
2807#define WM8995_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */
2808#define WM8995_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */
2809#define WM8995_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */
2810#define WM8995_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */
2811#define WM8995_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */
2812#define WM8995_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */
2813#define WM8995_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */
2814#define WM8995_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */
2815#define WM8995_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */
2816#define WM8995_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */
2817#define WM8995_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */
2818#define WM8995_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */
2819
2820/*
2821 * R1313 (0x521) - AIF2 DAC Filters (2)
2822 */
2823#define WM8995_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */
2824#define WM8995_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */
2825#define WM8995_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */
2826#define WM8995_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */
2827#define WM8995_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */
2828#define WM8995_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */
2829#define WM8995_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */
2830
2831/*
2832 * R1344 (0x540) - AIF2 DRC (1)
2833 */
2834#define WM8995_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */
2835#define WM8995_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */
2836#define WM8995_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */
2837#define WM8995_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */
2838#define WM8995_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */
2839#define WM8995_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */
2840#define WM8995_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */
2841#define WM8995_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */
2842#define WM8995_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */
2843#define WM8995_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */
2844#define WM8995_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */
2845#define WM8995_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */
2846#define WM8995_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */
2847#define WM8995_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */
2848#define WM8995_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */
2849#define WM8995_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */
2850#define WM8995_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */
2851#define WM8995_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */
2852#define WM8995_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */
2853#define WM8995_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */
2854#define WM8995_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */
2855#define WM8995_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */
2856#define WM8995_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */
2857#define WM8995_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */
2858#define WM8995_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */
2859#define WM8995_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */
2860#define WM8995_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */
2861#define WM8995_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */
2862#define WM8995_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */
2863#define WM8995_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */
2864#define WM8995_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */
2865#define WM8995_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */
2866#define WM8995_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */
2867#define WM8995_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */
2868#define WM8995_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */
2869#define WM8995_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */
2870#define WM8995_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */
2871#define WM8995_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */
2872#define WM8995_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */
2873#define WM8995_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */
2874#define WM8995_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */
2875#define WM8995_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */
2876
2877/*
2878 * R1345 (0x541) - AIF2 DRC (2)
2879 */
2880#define WM8995_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */
2881#define WM8995_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */
2882#define WM8995_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */
2883#define WM8995_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */
2884#define WM8995_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */
2885#define WM8995_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */
2886#define WM8995_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */
2887#define WM8995_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */
2888#define WM8995_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */
2889#define WM8995_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */
2890#define WM8995_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */
2891#define WM8995_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */
2892
2893/*
2894 * R1346 (0x542) - AIF2 DRC (3)
2895 */
2896#define WM8995_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */
2897#define WM8995_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */
2898#define WM8995_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */
2899#define WM8995_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */
2900#define WM8995_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */
2901#define WM8995_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */
2902#define WM8995_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */
2903#define WM8995_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */
2904#define WM8995_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */
2905#define WM8995_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */
2906#define WM8995_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */
2907#define WM8995_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */
2908#define WM8995_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */
2909#define WM8995_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */
2910#define WM8995_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */
2911#define WM8995_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */
2912#define WM8995_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */
2913#define WM8995_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */
2914
2915/*
2916 * R1347 (0x543) - AIF2 DRC (4)
2917 */
2918#define WM8995_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */
2919#define WM8995_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */
2920#define WM8995_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */
2921#define WM8995_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */
2922#define WM8995_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */
2923#define WM8995_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */
2924
2925/*
2926 * R1348 (0x544) - AIF2 DRC (5)
2927 */
2928#define WM8995_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */
2929#define WM8995_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */
2930#define WM8995_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */
2931#define WM8995_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */
2932#define WM8995_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */
2933#define WM8995_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */
2934
2935/*
2936 * R1408 (0x580) - AIF2 EQ Gains (1)
2937 */
2938#define WM8995_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
2939#define WM8995_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
2940#define WM8995_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
2941#define WM8995_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
2942#define WM8995_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
2943#define WM8995_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
2944#define WM8995_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */
2945#define WM8995_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
2946#define WM8995_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
2947#define WM8995_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */
2948#define WM8995_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */
2949#define WM8995_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */
2950#define WM8995_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */
2951
2952/*
2953 * R1409 (0x581) - AIF2 EQ Gains (2)
2954 */
2955#define WM8995_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
2956#define WM8995_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
2957#define WM8995_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
2958#define WM8995_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
2959#define WM8995_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
2960#define WM8995_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
2961
2962/*
2963 * R1410 (0x582) - AIF2 EQ Band 1 A
2964 */
2965#define WM8995_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */
2966#define WM8995_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */
2967#define WM8995_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */
2968
2969/*
2970 * R1411 (0x583) - AIF2 EQ Band 1 B
2971 */
2972#define WM8995_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */
2973#define WM8995_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */
2974#define WM8995_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */
2975
2976/*
2977 * R1412 (0x584) - AIF2 EQ Band 1 PG
2978 */
2979#define WM8995_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */
2980#define WM8995_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */
2981#define WM8995_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */
2982
2983/*
2984 * R1413 (0x585) - AIF2 EQ Band 2 A
2985 */
2986#define WM8995_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */
2987#define WM8995_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */
2988#define WM8995_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */
2989
2990/*
2991 * R1414 (0x586) - AIF2 EQ Band 2 B
2992 */
2993#define WM8995_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */
2994#define WM8995_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */
2995#define WM8995_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */
2996
2997/*
2998 * R1415 (0x587) - AIF2 EQ Band 2 C
2999 */
3000#define WM8995_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */
3001#define WM8995_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */
3002#define WM8995_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */
3003
3004/*
3005 * R1416 (0x588) - AIF2 EQ Band 2 PG
3006 */
3007#define WM8995_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */
3008#define WM8995_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */
3009#define WM8995_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */
3010
3011/*
3012 * R1417 (0x589) - AIF2 EQ Band 3 A
3013 */
3014#define WM8995_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */
3015#define WM8995_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */
3016#define WM8995_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */
3017
3018/*
3019 * R1418 (0x58A) - AIF2 EQ Band 3 B
3020 */
3021#define WM8995_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */
3022#define WM8995_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */
3023#define WM8995_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */
3024
3025/*
3026 * R1419 (0x58B) - AIF2 EQ Band 3 C
3027 */
3028#define WM8995_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */
3029#define WM8995_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */
3030#define WM8995_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */
3031
3032/*
3033 * R1420 (0x58C) - AIF2 EQ Band 3 PG
3034 */
3035#define WM8995_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */
3036#define WM8995_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */
3037#define WM8995_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */
3038
3039/*
3040 * R1421 (0x58D) - AIF2 EQ Band 4 A
3041 */
3042#define WM8995_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */
3043#define WM8995_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */
3044#define WM8995_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */
3045
3046/*
3047 * R1422 (0x58E) - AIF2 EQ Band 4 B
3048 */
3049#define WM8995_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */
3050#define WM8995_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */
3051#define WM8995_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */
3052
3053/*
3054 * R1423 (0x58F) - AIF2 EQ Band 4 C
3055 */
3056#define WM8995_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */
3057#define WM8995_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */
3058#define WM8995_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */
3059
3060/*
3061 * R1424 (0x590) - AIF2 EQ Band 4 PG
3062 */
3063#define WM8995_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */
3064#define WM8995_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */
3065#define WM8995_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */
3066
3067/*
3068 * R1425 (0x591) - AIF2 EQ Band 5 A
3069 */
3070#define WM8995_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */
3071#define WM8995_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */
3072#define WM8995_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */
3073
3074/*
3075 * R1426 (0x592) - AIF2 EQ Band 5 B
3076 */
3077#define WM8995_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */
3078#define WM8995_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */
3079#define WM8995_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */
3080
3081/*
3082 * R1427 (0x593) - AIF2 EQ Band 5 PG
3083 */
3084#define WM8995_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */
3085#define WM8995_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */
3086#define WM8995_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */
3087
3088/*
3089 * R1536 (0x600) - DAC1 Mixer Volumes
3090 */
3091#define WM8995_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */
3092#define WM8995_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */
3093#define WM8995_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */
3094#define WM8995_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */
3095#define WM8995_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */
3096#define WM8995_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */
3097
3098/*
3099 * R1537 (0x601) - DAC1 Left Mixer Routing
3100 */
3101#define WM8995_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */
3102#define WM8995_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */
3103#define WM8995_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */
3104#define WM8995_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */
3105#define WM8995_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */
3106#define WM8995_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */
3107#define WM8995_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */
3108#define WM8995_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */
3109#define WM8995_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */
3110#define WM8995_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */
3111#define WM8995_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */
3112#define WM8995_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */
3113#define WM8995_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */
3114#define WM8995_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */
3115#define WM8995_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */
3116#define WM8995_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */
3117#define WM8995_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */
3118#define WM8995_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */
3119#define WM8995_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */
3120#define WM8995_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */
3121
3122/*
3123 * R1538 (0x602) - DAC1 Right Mixer Routing
3124 */
3125#define WM8995_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */
3126#define WM8995_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */
3127#define WM8995_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */
3128#define WM8995_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */
3129#define WM8995_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */
3130#define WM8995_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */
3131#define WM8995_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */
3132#define WM8995_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */
3133#define WM8995_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */
3134#define WM8995_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */
3135#define WM8995_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */
3136#define WM8995_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */
3137#define WM8995_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */
3138#define WM8995_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */
3139#define WM8995_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */
3140#define WM8995_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */
3141#define WM8995_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */
3142#define WM8995_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */
3143#define WM8995_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */
3144#define WM8995_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */
3145
3146/*
3147 * R1539 (0x603) - DAC2 Mixer Volumes
3148 */
3149#define WM8995_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */
3150#define WM8995_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */
3151#define WM8995_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */
3152#define WM8995_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */
3153#define WM8995_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */
3154#define WM8995_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */
3155
3156/*
3157 * R1540 (0x604) - DAC2 Left Mixer Routing
3158 */
3159#define WM8995_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */
3160#define WM8995_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */
3161#define WM8995_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */
3162#define WM8995_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */
3163#define WM8995_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */
3164#define WM8995_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */
3165#define WM8995_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */
3166#define WM8995_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */
3167#define WM8995_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */
3168#define WM8995_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */
3169#define WM8995_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */
3170#define WM8995_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */
3171#define WM8995_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */
3172#define WM8995_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */
3173#define WM8995_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */
3174#define WM8995_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */
3175#define WM8995_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */
3176#define WM8995_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */
3177#define WM8995_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */
3178#define WM8995_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */
3179
3180/*
3181 * R1541 (0x605) - DAC2 Right Mixer Routing
3182 */
3183#define WM8995_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */
3184#define WM8995_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */
3185#define WM8995_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */
3186#define WM8995_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */
3187#define WM8995_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */
3188#define WM8995_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */
3189#define WM8995_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */
3190#define WM8995_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */
3191#define WM8995_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */
3192#define WM8995_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */
3193#define WM8995_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */
3194#define WM8995_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */
3195#define WM8995_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */
3196#define WM8995_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */
3197#define WM8995_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */
3198#define WM8995_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */
3199#define WM8995_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */
3200#define WM8995_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */
3201#define WM8995_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */
3202#define WM8995_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */
3203
3204/*
3205 * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing
3206 */
3207#define WM8995_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */
3208#define WM8995_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */
3209#define WM8995_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */
3210#define WM8995_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */
3211#define WM8995_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */
3212#define WM8995_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */
3213#define WM8995_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */
3214#define WM8995_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */
3215
3216/*
3217 * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing
3218 */
3219#define WM8995_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */
3220#define WM8995_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */
3221#define WM8995_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */
3222#define WM8995_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */
3223#define WM8995_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */
3224#define WM8995_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */
3225#define WM8995_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */
3226#define WM8995_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */
3227
3228/*
3229 * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing
3230 */
3231#define WM8995_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */
3232#define WM8995_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */
3233#define WM8995_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */
3234#define WM8995_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */
3235#define WM8995_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */
3236#define WM8995_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */
3237#define WM8995_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */
3238#define WM8995_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */
3239
3240/*
3241 * R1545 (0x609) - AIF1 ADC2 Right mixer Routing
3242 */
3243#define WM8995_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */
3244#define WM8995_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */
3245#define WM8995_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */
3246#define WM8995_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */
3247#define WM8995_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */
3248#define WM8995_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */
3249#define WM8995_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */
3250#define WM8995_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */
3251
3252/*
3253 * R1552 (0x610) - DAC Softmute
3254 */
3255#define WM8995_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */
3256#define WM8995_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */
3257#define WM8995_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */
3258#define WM8995_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */
3259#define WM8995_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */
3260#define WM8995_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */
3261#define WM8995_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */
3262#define WM8995_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
3263
3264/*
3265 * R1568 (0x620) - Oversampling
3266 */
3267#define WM8995_ADC_OSR128 0x0002 /* ADC_OSR128 */
3268#define WM8995_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */
3269#define WM8995_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */
3270#define WM8995_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */
3271#define WM8995_DAC_OSR128 0x0001 /* DAC_OSR128 */
3272#define WM8995_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */
3273#define WM8995_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */
3274#define WM8995_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */
3275
3276/*
3277 * R1569 (0x621) - Sidetone
3278 */
3279#define WM8995_ST_LPF 0x1000 /* ST_LPF */
3280#define WM8995_ST_LPF_MASK 0x1000 /* ST_LPF */
3281#define WM8995_ST_LPF_SHIFT 12 /* ST_LPF */
3282#define WM8995_ST_LPF_WIDTH 1 /* ST_LPF */
3283#define WM8995_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */
3284#define WM8995_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */
3285#define WM8995_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */
3286#define WM8995_ST_HPF 0x0040 /* ST_HPF */
3287#define WM8995_ST_HPF_MASK 0x0040 /* ST_HPF */
3288#define WM8995_ST_HPF_SHIFT 6 /* ST_HPF */
3289#define WM8995_ST_HPF_WIDTH 1 /* ST_HPF */
3290#define WM8995_STR_SEL 0x0002 /* STR_SEL */
3291#define WM8995_STR_SEL_MASK 0x0002 /* STR_SEL */
3292#define WM8995_STR_SEL_SHIFT 1 /* STR_SEL */
3293#define WM8995_STR_SEL_WIDTH 1 /* STR_SEL */
3294#define WM8995_STL_SEL 0x0001 /* STL_SEL */
3295#define WM8995_STL_SEL_MASK 0x0001 /* STL_SEL */
3296#define WM8995_STL_SEL_SHIFT 0 /* STL_SEL */
3297#define WM8995_STL_SEL_WIDTH 1 /* STL_SEL */
3298
3299/*
3300 * R1792 (0x700) - GPIO 1
3301 */
3302#define WM8995_GP1_DIR 0x8000 /* GP1_DIR */
3303#define WM8995_GP1_DIR_MASK 0x8000 /* GP1_DIR */
3304#define WM8995_GP1_DIR_SHIFT 15 /* GP1_DIR */
3305#define WM8995_GP1_DIR_WIDTH 1 /* GP1_DIR */
3306#define WM8995_GP1_PU 0x4000 /* GP1_PU */
3307#define WM8995_GP1_PU_MASK 0x4000 /* GP1_PU */
3308#define WM8995_GP1_PU_SHIFT 14 /* GP1_PU */
3309#define WM8995_GP1_PU_WIDTH 1 /* GP1_PU */
3310#define WM8995_GP1_PD 0x2000 /* GP1_PD */
3311#define WM8995_GP1_PD_MASK 0x2000 /* GP1_PD */
3312#define WM8995_GP1_PD_SHIFT 13 /* GP1_PD */
3313#define WM8995_GP1_PD_WIDTH 1 /* GP1_PD */
3314#define WM8995_GP1_POL 0x0400 /* GP1_POL */
3315#define WM8995_GP1_POL_MASK 0x0400 /* GP1_POL */
3316#define WM8995_GP1_POL_SHIFT 10 /* GP1_POL */
3317#define WM8995_GP1_POL_WIDTH 1 /* GP1_POL */
3318#define WM8995_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */
3319#define WM8995_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */
3320#define WM8995_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */
3321#define WM8995_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
3322#define WM8995_GP1_DB 0x0100 /* GP1_DB */
3323#define WM8995_GP1_DB_MASK 0x0100 /* GP1_DB */
3324#define WM8995_GP1_DB_SHIFT 8 /* GP1_DB */
3325#define WM8995_GP1_DB_WIDTH 1 /* GP1_DB */
3326#define WM8995_GP1_LVL 0x0040 /* GP1_LVL */
3327#define WM8995_GP1_LVL_MASK 0x0040 /* GP1_LVL */
3328#define WM8995_GP1_LVL_SHIFT 6 /* GP1_LVL */
3329#define WM8995_GP1_LVL_WIDTH 1 /* GP1_LVL */
3330#define WM8995_GP1_FN_MASK 0x001F /* GP1_FN - [4:0] */
3331#define WM8995_GP1_FN_SHIFT 0 /* GP1_FN - [4:0] */
3332#define WM8995_GP1_FN_WIDTH 5 /* GP1_FN - [4:0] */
3333
3334/*
3335 * R1793 (0x701) - GPIO 2
3336 */
3337#define WM8995_GP2_DIR 0x8000 /* GP2_DIR */
3338#define WM8995_GP2_DIR_MASK 0x8000 /* GP2_DIR */
3339#define WM8995_GP2_DIR_SHIFT 15 /* GP2_DIR */
3340#define WM8995_GP2_DIR_WIDTH 1 /* GP2_DIR */
3341#define WM8995_GP2_PU 0x4000 /* GP2_PU */
3342#define WM8995_GP2_PU_MASK 0x4000 /* GP2_PU */
3343#define WM8995_GP2_PU_SHIFT 14 /* GP2_PU */
3344#define WM8995_GP2_PU_WIDTH 1 /* GP2_PU */
3345#define WM8995_GP2_PD 0x2000 /* GP2_PD */
3346#define WM8995_GP2_PD_MASK 0x2000 /* GP2_PD */
3347#define WM8995_GP2_PD_SHIFT 13 /* GP2_PD */
3348#define WM8995_GP2_PD_WIDTH 1 /* GP2_PD */
3349#define WM8995_GP2_POL 0x0400 /* GP2_POL */
3350#define WM8995_GP2_POL_MASK 0x0400 /* GP2_POL */
3351#define WM8995_GP2_POL_SHIFT 10 /* GP2_POL */
3352#define WM8995_GP2_POL_WIDTH 1 /* GP2_POL */
3353#define WM8995_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */
3354#define WM8995_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */
3355#define WM8995_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */
3356#define WM8995_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
3357#define WM8995_GP2_DB 0x0100 /* GP2_DB */
3358#define WM8995_GP2_DB_MASK 0x0100 /* GP2_DB */
3359#define WM8995_GP2_DB_SHIFT 8 /* GP2_DB */
3360#define WM8995_GP2_DB_WIDTH 1 /* GP2_DB */
3361#define WM8995_GP2_LVL 0x0040 /* GP2_LVL */
3362#define WM8995_GP2_LVL_MASK 0x0040 /* GP2_LVL */
3363#define WM8995_GP2_LVL_SHIFT 6 /* GP2_LVL */
3364#define WM8995_GP2_LVL_WIDTH 1 /* GP2_LVL */
3365#define WM8995_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */
3366#define WM8995_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */
3367#define WM8995_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */
3368
3369/*
3370 * R1794 (0x702) - GPIO 3
3371 */
3372#define WM8995_GP3_DIR 0x8000 /* GP3_DIR */
3373#define WM8995_GP3_DIR_MASK 0x8000 /* GP3_DIR */
3374#define WM8995_GP3_DIR_SHIFT 15 /* GP3_DIR */
3375#define WM8995_GP3_DIR_WIDTH 1 /* GP3_DIR */
3376#define WM8995_GP3_PU 0x4000 /* GP3_PU */
3377#define WM8995_GP3_PU_MASK 0x4000 /* GP3_PU */
3378#define WM8995_GP3_PU_SHIFT 14 /* GP3_PU */
3379#define WM8995_GP3_PU_WIDTH 1 /* GP3_PU */
3380#define WM8995_GP3_PD 0x2000 /* GP3_PD */
3381#define WM8995_GP3_PD_MASK 0x2000 /* GP3_PD */
3382#define WM8995_GP3_PD_SHIFT 13 /* GP3_PD */
3383#define WM8995_GP3_PD_WIDTH 1 /* GP3_PD */
3384#define WM8995_GP3_POL 0x0400 /* GP3_POL */
3385#define WM8995_GP3_POL_MASK 0x0400 /* GP3_POL */
3386#define WM8995_GP3_POL_SHIFT 10 /* GP3_POL */
3387#define WM8995_GP3_POL_WIDTH 1 /* GP3_POL */
3388#define WM8995_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */
3389#define WM8995_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */
3390#define WM8995_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */
3391#define WM8995_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
3392#define WM8995_GP3_DB 0x0100 /* GP3_DB */
3393#define WM8995_GP3_DB_MASK 0x0100 /* GP3_DB */
3394#define WM8995_GP3_DB_SHIFT 8 /* GP3_DB */
3395#define WM8995_GP3_DB_WIDTH 1 /* GP3_DB */
3396#define WM8995_GP3_LVL 0x0040 /* GP3_LVL */
3397#define WM8995_GP3_LVL_MASK 0x0040 /* GP3_LVL */
3398#define WM8995_GP3_LVL_SHIFT 6 /* GP3_LVL */
3399#define WM8995_GP3_LVL_WIDTH 1 /* GP3_LVL */
3400#define WM8995_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */
3401#define WM8995_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */
3402#define WM8995_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */
3403
3404/*
3405 * R1795 (0x703) - GPIO 4
3406 */
3407#define WM8995_GP4_DIR 0x8000 /* GP4_DIR */
3408#define WM8995_GP4_DIR_MASK 0x8000 /* GP4_DIR */
3409#define WM8995_GP4_DIR_SHIFT 15 /* GP4_DIR */
3410#define WM8995_GP4_DIR_WIDTH 1 /* GP4_DIR */
3411#define WM8995_GP4_PU 0x4000 /* GP4_PU */
3412#define WM8995_GP4_PU_MASK 0x4000 /* GP4_PU */
3413#define WM8995_GP4_PU_SHIFT 14 /* GP4_PU */
3414#define WM8995_GP4_PU_WIDTH 1 /* GP4_PU */
3415#define WM8995_GP4_PD 0x2000 /* GP4_PD */
3416#define WM8995_GP4_PD_MASK 0x2000 /* GP4_PD */
3417#define WM8995_GP4_PD_SHIFT 13 /* GP4_PD */
3418#define WM8995_GP4_PD_WIDTH 1 /* GP4_PD */
3419#define WM8995_GP4_POL 0x0400 /* GP4_POL */
3420#define WM8995_GP4_POL_MASK 0x0400 /* GP4_POL */
3421#define WM8995_GP4_POL_SHIFT 10 /* GP4_POL */
3422#define WM8995_GP4_POL_WIDTH 1 /* GP4_POL */
3423#define WM8995_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */
3424#define WM8995_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */
3425#define WM8995_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */
3426#define WM8995_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
3427#define WM8995_GP4_DB 0x0100 /* GP4_DB */
3428#define WM8995_GP4_DB_MASK 0x0100 /* GP4_DB */
3429#define WM8995_GP4_DB_SHIFT 8 /* GP4_DB */
3430#define WM8995_GP4_DB_WIDTH 1 /* GP4_DB */
3431#define WM8995_GP4_LVL 0x0040 /* GP4_LVL */
3432#define WM8995_GP4_LVL_MASK 0x0040 /* GP4_LVL */
3433#define WM8995_GP4_LVL_SHIFT 6 /* GP4_LVL */
3434#define WM8995_GP4_LVL_WIDTH 1 /* GP4_LVL */
3435#define WM8995_GP4_FN_MASK 0x001F /* GP4_FN - [4:0] */
3436#define WM8995_GP4_FN_SHIFT 0 /* GP4_FN - [4:0] */
3437#define WM8995_GP4_FN_WIDTH 5 /* GP4_FN - [4:0] */
3438
3439/*
3440 * R1796 (0x704) - GPIO 5
3441 */
3442#define WM8995_GP5_DIR 0x8000 /* GP5_DIR */
3443#define WM8995_GP5_DIR_MASK 0x8000 /* GP5_DIR */
3444#define WM8995_GP5_DIR_SHIFT 15 /* GP5_DIR */
3445#define WM8995_GP5_DIR_WIDTH 1 /* GP5_DIR */
3446#define WM8995_GP5_PU 0x4000 /* GP5_PU */
3447#define WM8995_GP5_PU_MASK 0x4000 /* GP5_PU */
3448#define WM8995_GP5_PU_SHIFT 14 /* GP5_PU */
3449#define WM8995_GP5_PU_WIDTH 1 /* GP5_PU */
3450#define WM8995_GP5_PD 0x2000 /* GP5_PD */
3451#define WM8995_GP5_PD_MASK 0x2000 /* GP5_PD */
3452#define WM8995_GP5_PD_SHIFT 13 /* GP5_PD */
3453#define WM8995_GP5_PD_WIDTH 1 /* GP5_PD */
3454#define WM8995_GP5_POL 0x0400 /* GP5_POL */
3455#define WM8995_GP5_POL_MASK 0x0400 /* GP5_POL */
3456#define WM8995_GP5_POL_SHIFT 10 /* GP5_POL */
3457#define WM8995_GP5_POL_WIDTH 1 /* GP5_POL */
3458#define WM8995_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */
3459#define WM8995_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */
3460#define WM8995_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */
3461#define WM8995_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
3462#define WM8995_GP5_DB 0x0100 /* GP5_DB */
3463#define WM8995_GP5_DB_MASK 0x0100 /* GP5_DB */
3464#define WM8995_GP5_DB_SHIFT 8 /* GP5_DB */
3465#define WM8995_GP5_DB_WIDTH 1 /* GP5_DB */
3466#define WM8995_GP5_LVL 0x0040 /* GP5_LVL */
3467#define WM8995_GP5_LVL_MASK 0x0040 /* GP5_LVL */
3468#define WM8995_GP5_LVL_SHIFT 6 /* GP5_LVL */
3469#define WM8995_GP5_LVL_WIDTH 1 /* GP5_LVL */
3470#define WM8995_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */
3471#define WM8995_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */
3472#define WM8995_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */
3473
3474/*
3475 * R1797 (0x705) - GPIO 6
3476 */
3477#define WM8995_GP6_DIR 0x8000 /* GP6_DIR */
3478#define WM8995_GP6_DIR_MASK 0x8000 /* GP6_DIR */
3479#define WM8995_GP6_DIR_SHIFT 15 /* GP6_DIR */
3480#define WM8995_GP6_DIR_WIDTH 1 /* GP6_DIR */
3481#define WM8995_GP6_PU 0x4000 /* GP6_PU */
3482#define WM8995_GP6_PU_MASK 0x4000 /* GP6_PU */
3483#define WM8995_GP6_PU_SHIFT 14 /* GP6_PU */
3484#define WM8995_GP6_PU_WIDTH 1 /* GP6_PU */
3485#define WM8995_GP6_PD 0x2000 /* GP6_PD */
3486#define WM8995_GP6_PD_MASK 0x2000 /* GP6_PD */
3487#define WM8995_GP6_PD_SHIFT 13 /* GP6_PD */
3488#define WM8995_GP6_PD_WIDTH 1 /* GP6_PD */
3489#define WM8995_GP6_POL 0x0400 /* GP6_POL */
3490#define WM8995_GP6_POL_MASK 0x0400 /* GP6_POL */
3491#define WM8995_GP6_POL_SHIFT 10 /* GP6_POL */
3492#define WM8995_GP6_POL_WIDTH 1 /* GP6_POL */
3493#define WM8995_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */
3494#define WM8995_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */
3495#define WM8995_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */
3496#define WM8995_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */
3497#define WM8995_GP6_DB 0x0100 /* GP6_DB */
3498#define WM8995_GP6_DB_MASK 0x0100 /* GP6_DB */
3499#define WM8995_GP6_DB_SHIFT 8 /* GP6_DB */
3500#define WM8995_GP6_DB_WIDTH 1 /* GP6_DB */
3501#define WM8995_GP6_LVL 0x0040 /* GP6_LVL */
3502#define WM8995_GP6_LVL_MASK 0x0040 /* GP6_LVL */
3503#define WM8995_GP6_LVL_SHIFT 6 /* GP6_LVL */
3504#define WM8995_GP6_LVL_WIDTH 1 /* GP6_LVL */
3505#define WM8995_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */
3506#define WM8995_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */
3507#define WM8995_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */
3508
3509/*
3510 * R1798 (0x706) - GPIO 7
3511 */
3512#define WM8995_GP7_DIR 0x8000 /* GP7_DIR */
3513#define WM8995_GP7_DIR_MASK 0x8000 /* GP7_DIR */
3514#define WM8995_GP7_DIR_SHIFT 15 /* GP7_DIR */
3515#define WM8995_GP7_DIR_WIDTH 1 /* GP7_DIR */
3516#define WM8995_GP7_PU 0x4000 /* GP7_PU */
3517#define WM8995_GP7_PU_MASK 0x4000 /* GP7_PU */
3518#define WM8995_GP7_PU_SHIFT 14 /* GP7_PU */
3519#define WM8995_GP7_PU_WIDTH 1 /* GP7_PU */
3520#define WM8995_GP7_PD 0x2000 /* GP7_PD */
3521#define WM8995_GP7_PD_MASK 0x2000 /* GP7_PD */
3522#define WM8995_GP7_PD_SHIFT 13 /* GP7_PD */
3523#define WM8995_GP7_PD_WIDTH 1 /* GP7_PD */
3524#define WM8995_GP7_POL 0x0400 /* GP7_POL */
3525#define WM8995_GP7_POL_MASK 0x0400 /* GP7_POL */
3526#define WM8995_GP7_POL_SHIFT 10 /* GP7_POL */
3527#define WM8995_GP7_POL_WIDTH 1 /* GP7_POL */
3528#define WM8995_GP7_OP_CFG 0x0200 /* GP7_OP_CFG */
3529#define WM8995_GP7_OP_CFG_MASK 0x0200 /* GP7_OP_CFG */
3530#define WM8995_GP7_OP_CFG_SHIFT 9 /* GP7_OP_CFG */
3531#define WM8995_GP7_OP_CFG_WIDTH 1 /* GP7_OP_CFG */
3532#define WM8995_GP7_DB 0x0100 /* GP7_DB */
3533#define WM8995_GP7_DB_MASK 0x0100 /* GP7_DB */
3534#define WM8995_GP7_DB_SHIFT 8 /* GP7_DB */
3535#define WM8995_GP7_DB_WIDTH 1 /* GP7_DB */
3536#define WM8995_GP7_LVL 0x0040 /* GP7_LVL */
3537#define WM8995_GP7_LVL_MASK 0x0040 /* GP7_LVL */
3538#define WM8995_GP7_LVL_SHIFT 6 /* GP7_LVL */
3539#define WM8995_GP7_LVL_WIDTH 1 /* GP7_LVL */
3540#define WM8995_GP7_FN_MASK 0x001F /* GP7_FN - [4:0] */
3541#define WM8995_GP7_FN_SHIFT 0 /* GP7_FN - [4:0] */
3542#define WM8995_GP7_FN_WIDTH 5 /* GP7_FN - [4:0] */
3543
3544/*
3545 * R1799 (0x707) - GPIO 8
3546 */
3547#define WM8995_GP8_DIR 0x8000 /* GP8_DIR */
3548#define WM8995_GP8_DIR_MASK 0x8000 /* GP8_DIR */
3549#define WM8995_GP8_DIR_SHIFT 15 /* GP8_DIR */
3550#define WM8995_GP8_DIR_WIDTH 1 /* GP8_DIR */
3551#define WM8995_GP8_PU 0x4000 /* GP8_PU */
3552#define WM8995_GP8_PU_MASK 0x4000 /* GP8_PU */
3553#define WM8995_GP8_PU_SHIFT 14 /* GP8_PU */
3554#define WM8995_GP8_PU_WIDTH 1 /* GP8_PU */
3555#define WM8995_GP8_PD 0x2000 /* GP8_PD */
3556#define WM8995_GP8_PD_MASK 0x2000 /* GP8_PD */
3557#define WM8995_GP8_PD_SHIFT 13 /* GP8_PD */
3558#define WM8995_GP8_PD_WIDTH 1 /* GP8_PD */
3559#define WM8995_GP8_POL 0x0400 /* GP8_POL */
3560#define WM8995_GP8_POL_MASK 0x0400 /* GP8_POL */
3561#define WM8995_GP8_POL_SHIFT 10 /* GP8_POL */
3562#define WM8995_GP8_POL_WIDTH 1 /* GP8_POL */
3563#define WM8995_GP8_OP_CFG 0x0200 /* GP8_OP_CFG */
3564#define WM8995_GP8_OP_CFG_MASK 0x0200 /* GP8_OP_CFG */
3565#define WM8995_GP8_OP_CFG_SHIFT 9 /* GP8_OP_CFG */
3566#define WM8995_GP8_OP_CFG_WIDTH 1 /* GP8_OP_CFG */
3567#define WM8995_GP8_DB 0x0100 /* GP8_DB */
3568#define WM8995_GP8_DB_MASK 0x0100 /* GP8_DB */
3569#define WM8995_GP8_DB_SHIFT 8 /* GP8_DB */
3570#define WM8995_GP8_DB_WIDTH 1 /* GP8_DB */
3571#define WM8995_GP8_LVL 0x0040 /* GP8_LVL */
3572#define WM8995_GP8_LVL_MASK 0x0040 /* GP8_LVL */
3573#define WM8995_GP8_LVL_SHIFT 6 /* GP8_LVL */
3574#define WM8995_GP8_LVL_WIDTH 1 /* GP8_LVL */
3575#define WM8995_GP8_FN_MASK 0x001F /* GP8_FN - [4:0] */
3576#define WM8995_GP8_FN_SHIFT 0 /* GP8_FN - [4:0] */
3577#define WM8995_GP8_FN_WIDTH 5 /* GP8_FN - [4:0] */
3578
3579/*
3580 * R1800 (0x708) - GPIO 9
3581 */
3582#define WM8995_GP9_DIR 0x8000 /* GP9_DIR */
3583#define WM8995_GP9_DIR_MASK 0x8000 /* GP9_DIR */
3584#define WM8995_GP9_DIR_SHIFT 15 /* GP9_DIR */
3585#define WM8995_GP9_DIR_WIDTH 1 /* GP9_DIR */
3586#define WM8995_GP9_PU 0x4000 /* GP9_PU */
3587#define WM8995_GP9_PU_MASK 0x4000 /* GP9_PU */
3588#define WM8995_GP9_PU_SHIFT 14 /* GP9_PU */
3589#define WM8995_GP9_PU_WIDTH 1 /* GP9_PU */
3590#define WM8995_GP9_PD 0x2000 /* GP9_PD */
3591#define WM8995_GP9_PD_MASK 0x2000 /* GP9_PD */
3592#define WM8995_GP9_PD_SHIFT 13 /* GP9_PD */
3593#define WM8995_GP9_PD_WIDTH 1 /* GP9_PD */
3594#define WM8995_GP9_POL 0x0400 /* GP9_POL */
3595#define WM8995_GP9_POL_MASK 0x0400 /* GP9_POL */
3596#define WM8995_GP9_POL_SHIFT 10 /* GP9_POL */
3597#define WM8995_GP9_POL_WIDTH 1 /* GP9_POL */
3598#define WM8995_GP9_OP_CFG 0x0200 /* GP9_OP_CFG */
3599#define WM8995_GP9_OP_CFG_MASK 0x0200 /* GP9_OP_CFG */
3600#define WM8995_GP9_OP_CFG_SHIFT 9 /* GP9_OP_CFG */
3601#define WM8995_GP9_OP_CFG_WIDTH 1 /* GP9_OP_CFG */
3602#define WM8995_GP9_DB 0x0100 /* GP9_DB */
3603#define WM8995_GP9_DB_MASK 0x0100 /* GP9_DB */
3604#define WM8995_GP9_DB_SHIFT 8 /* GP9_DB */
3605#define WM8995_GP9_DB_WIDTH 1 /* GP9_DB */
3606#define WM8995_GP9_LVL 0x0040 /* GP9_LVL */
3607#define WM8995_GP9_LVL_MASK 0x0040 /* GP9_LVL */
3608#define WM8995_GP9_LVL_SHIFT 6 /* GP9_LVL */
3609#define WM8995_GP9_LVL_WIDTH 1 /* GP9_LVL */
3610#define WM8995_GP9_FN_MASK 0x001F /* GP9_FN - [4:0] */
3611#define WM8995_GP9_FN_SHIFT 0 /* GP9_FN - [4:0] */
3612#define WM8995_GP9_FN_WIDTH 5 /* GP9_FN - [4:0] */
3613
3614/*
3615 * R1801 (0x709) - GPIO 10
3616 */
3617#define WM8995_GP10_DIR 0x8000 /* GP10_DIR */
3618#define WM8995_GP10_DIR_MASK 0x8000 /* GP10_DIR */
3619#define WM8995_GP10_DIR_SHIFT 15 /* GP10_DIR */
3620#define WM8995_GP10_DIR_WIDTH 1 /* GP10_DIR */
3621#define WM8995_GP10_PU 0x4000 /* GP10_PU */
3622#define WM8995_GP10_PU_MASK 0x4000 /* GP10_PU */
3623#define WM8995_GP10_PU_SHIFT 14 /* GP10_PU */
3624#define WM8995_GP10_PU_WIDTH 1 /* GP10_PU */
3625#define WM8995_GP10_PD 0x2000 /* GP10_PD */
3626#define WM8995_GP10_PD_MASK 0x2000 /* GP10_PD */
3627#define WM8995_GP10_PD_SHIFT 13 /* GP10_PD */
3628#define WM8995_GP10_PD_WIDTH 1 /* GP10_PD */
3629#define WM8995_GP10_POL 0x0400 /* GP10_POL */
3630#define WM8995_GP10_POL_MASK 0x0400 /* GP10_POL */
3631#define WM8995_GP10_POL_SHIFT 10 /* GP10_POL */
3632#define WM8995_GP10_POL_WIDTH 1 /* GP10_POL */
3633#define WM8995_GP10_OP_CFG 0x0200 /* GP10_OP_CFG */
3634#define WM8995_GP10_OP_CFG_MASK 0x0200 /* GP10_OP_CFG */
3635#define WM8995_GP10_OP_CFG_SHIFT 9 /* GP10_OP_CFG */
3636#define WM8995_GP10_OP_CFG_WIDTH 1 /* GP10_OP_CFG */
3637#define WM8995_GP10_DB 0x0100 /* GP10_DB */
3638#define WM8995_GP10_DB_MASK 0x0100 /* GP10_DB */
3639#define WM8995_GP10_DB_SHIFT 8 /* GP10_DB */
3640#define WM8995_GP10_DB_WIDTH 1 /* GP10_DB */
3641#define WM8995_GP10_LVL 0x0040 /* GP10_LVL */
3642#define WM8995_GP10_LVL_MASK 0x0040 /* GP10_LVL */
3643#define WM8995_GP10_LVL_SHIFT 6 /* GP10_LVL */
3644#define WM8995_GP10_LVL_WIDTH 1 /* GP10_LVL */
3645#define WM8995_GP10_FN_MASK 0x001F /* GP10_FN - [4:0] */
3646#define WM8995_GP10_FN_SHIFT 0 /* GP10_FN - [4:0] */
3647#define WM8995_GP10_FN_WIDTH 5 /* GP10_FN - [4:0] */
3648
3649/*
3650 * R1802 (0x70A) - GPIO 11
3651 */
3652#define WM8995_GP11_DIR 0x8000 /* GP11_DIR */
3653#define WM8995_GP11_DIR_MASK 0x8000 /* GP11_DIR */
3654#define WM8995_GP11_DIR_SHIFT 15 /* GP11_DIR */
3655#define WM8995_GP11_DIR_WIDTH 1 /* GP11_DIR */
3656#define WM8995_GP11_PU 0x4000 /* GP11_PU */
3657#define WM8995_GP11_PU_MASK 0x4000 /* GP11_PU */
3658#define WM8995_GP11_PU_SHIFT 14 /* GP11_PU */
3659#define WM8995_GP11_PU_WIDTH 1 /* GP11_PU */
3660#define WM8995_GP11_PD 0x2000 /* GP11_PD */
3661#define WM8995_GP11_PD_MASK 0x2000 /* GP11_PD */
3662#define WM8995_GP11_PD_SHIFT 13 /* GP11_PD */
3663#define WM8995_GP11_PD_WIDTH 1 /* GP11_PD */
3664#define WM8995_GP11_POL 0x0400 /* GP11_POL */
3665#define WM8995_GP11_POL_MASK 0x0400 /* GP11_POL */
3666#define WM8995_GP11_POL_SHIFT 10 /* GP11_POL */
3667#define WM8995_GP11_POL_WIDTH 1 /* GP11_POL */
3668#define WM8995_GP11_OP_CFG 0x0200 /* GP11_OP_CFG */
3669#define WM8995_GP11_OP_CFG_MASK 0x0200 /* GP11_OP_CFG */
3670#define WM8995_GP11_OP_CFG_SHIFT 9 /* GP11_OP_CFG */
3671#define WM8995_GP11_OP_CFG_WIDTH 1 /* GP11_OP_CFG */
3672#define WM8995_GP11_DB 0x0100 /* GP11_DB */
3673#define WM8995_GP11_DB_MASK 0x0100 /* GP11_DB */
3674#define WM8995_GP11_DB_SHIFT 8 /* GP11_DB */
3675#define WM8995_GP11_DB_WIDTH 1 /* GP11_DB */
3676#define WM8995_GP11_LVL 0x0040 /* GP11_LVL */
3677#define WM8995_GP11_LVL_MASK 0x0040 /* GP11_LVL */
3678#define WM8995_GP11_LVL_SHIFT 6 /* GP11_LVL */
3679#define WM8995_GP11_LVL_WIDTH 1 /* GP11_LVL */
3680#define WM8995_GP11_FN_MASK 0x001F /* GP11_FN - [4:0] */
3681#define WM8995_GP11_FN_SHIFT 0 /* GP11_FN - [4:0] */
3682#define WM8995_GP11_FN_WIDTH 5 /* GP11_FN - [4:0] */
3683
3684/*
3685 * R1803 (0x70B) - GPIO 12
3686 */
3687#define WM8995_GP12_DIR 0x8000 /* GP12_DIR */
3688#define WM8995_GP12_DIR_MASK 0x8000 /* GP12_DIR */
3689#define WM8995_GP12_DIR_SHIFT 15 /* GP12_DIR */
3690#define WM8995_GP12_DIR_WIDTH 1 /* GP12_DIR */
3691#define WM8995_GP12_PU 0x4000 /* GP12_PU */
3692#define WM8995_GP12_PU_MASK 0x4000 /* GP12_PU */
3693#define WM8995_GP12_PU_SHIFT 14 /* GP12_PU */
3694#define WM8995_GP12_PU_WIDTH 1 /* GP12_PU */
3695#define WM8995_GP12_PD 0x2000 /* GP12_PD */
3696#define WM8995_GP12_PD_MASK 0x2000 /* GP12_PD */
3697#define WM8995_GP12_PD_SHIFT 13 /* GP12_PD */
3698#define WM8995_GP12_PD_WIDTH 1 /* GP12_PD */
3699#define WM8995_GP12_POL 0x0400 /* GP12_POL */
3700#define WM8995_GP12_POL_MASK 0x0400 /* GP12_POL */
3701#define WM8995_GP12_POL_SHIFT 10 /* GP12_POL */
3702#define WM8995_GP12_POL_WIDTH 1 /* GP12_POL */
3703#define WM8995_GP12_OP_CFG 0x0200 /* GP12_OP_CFG */
3704#define WM8995_GP12_OP_CFG_MASK 0x0200 /* GP12_OP_CFG */
3705#define WM8995_GP12_OP_CFG_SHIFT 9 /* GP12_OP_CFG */
3706#define WM8995_GP12_OP_CFG_WIDTH 1 /* GP12_OP_CFG */
3707#define WM8995_GP12_DB 0x0100 /* GP12_DB */
3708#define WM8995_GP12_DB_MASK 0x0100 /* GP12_DB */
3709#define WM8995_GP12_DB_SHIFT 8 /* GP12_DB */
3710#define WM8995_GP12_DB_WIDTH 1 /* GP12_DB */
3711#define WM8995_GP12_LVL 0x0040 /* GP12_LVL */
3712#define WM8995_GP12_LVL_MASK 0x0040 /* GP12_LVL */
3713#define WM8995_GP12_LVL_SHIFT 6 /* GP12_LVL */
3714#define WM8995_GP12_LVL_WIDTH 1 /* GP12_LVL */
3715#define WM8995_GP12_FN_MASK 0x001F /* GP12_FN - [4:0] */
3716#define WM8995_GP12_FN_SHIFT 0 /* GP12_FN - [4:0] */
3717#define WM8995_GP12_FN_WIDTH 5 /* GP12_FN - [4:0] */
3718
3719/*
3720 * R1804 (0x70C) - GPIO 13
3721 */
3722#define WM8995_GP13_DIR 0x8000 /* GP13_DIR */
3723#define WM8995_GP13_DIR_MASK 0x8000 /* GP13_DIR */
3724#define WM8995_GP13_DIR_SHIFT 15 /* GP13_DIR */
3725#define WM8995_GP13_DIR_WIDTH 1 /* GP13_DIR */
3726#define WM8995_GP13_PU 0x4000 /* GP13_PU */
3727#define WM8995_GP13_PU_MASK 0x4000 /* GP13_PU */
3728#define WM8995_GP13_PU_SHIFT 14 /* GP13_PU */
3729#define WM8995_GP13_PU_WIDTH 1 /* GP13_PU */
3730#define WM8995_GP13_PD 0x2000 /* GP13_PD */
3731#define WM8995_GP13_PD_MASK 0x2000 /* GP13_PD */
3732#define WM8995_GP13_PD_SHIFT 13 /* GP13_PD */
3733#define WM8995_GP13_PD_WIDTH 1 /* GP13_PD */
3734#define WM8995_GP13_POL 0x0400 /* GP13_POL */
3735#define WM8995_GP13_POL_MASK 0x0400 /* GP13_POL */
3736#define WM8995_GP13_POL_SHIFT 10 /* GP13_POL */
3737#define WM8995_GP13_POL_WIDTH 1 /* GP13_POL */
3738#define WM8995_GP13_OP_CFG 0x0200 /* GP13_OP_CFG */
3739#define WM8995_GP13_OP_CFG_MASK 0x0200 /* GP13_OP_CFG */
3740#define WM8995_GP13_OP_CFG_SHIFT 9 /* GP13_OP_CFG */
3741#define WM8995_GP13_OP_CFG_WIDTH 1 /* GP13_OP_CFG */
3742#define WM8995_GP13_DB 0x0100 /* GP13_DB */
3743#define WM8995_GP13_DB_MASK 0x0100 /* GP13_DB */
3744#define WM8995_GP13_DB_SHIFT 8 /* GP13_DB */
3745#define WM8995_GP13_DB_WIDTH 1 /* GP13_DB */
3746#define WM8995_GP13_LVL 0x0040 /* GP13_LVL */
3747#define WM8995_GP13_LVL_MASK 0x0040 /* GP13_LVL */
3748#define WM8995_GP13_LVL_SHIFT 6 /* GP13_LVL */
3749#define WM8995_GP13_LVL_WIDTH 1 /* GP13_LVL */
3750#define WM8995_GP13_FN_MASK 0x001F /* GP13_FN - [4:0] */
3751#define WM8995_GP13_FN_SHIFT 0 /* GP13_FN - [4:0] */
3752#define WM8995_GP13_FN_WIDTH 5 /* GP13_FN - [4:0] */
3753
3754/*
3755 * R1805 (0x70D) - GPIO 14
3756 */
3757#define WM8995_GP14_DIR 0x8000 /* GP14_DIR */
3758#define WM8995_GP14_DIR_MASK 0x8000 /* GP14_DIR */
3759#define WM8995_GP14_DIR_SHIFT 15 /* GP14_DIR */
3760#define WM8995_GP14_DIR_WIDTH 1 /* GP14_DIR */
3761#define WM8995_GP14_PU 0x4000 /* GP14_PU */
3762#define WM8995_GP14_PU_MASK 0x4000 /* GP14_PU */
3763#define WM8995_GP14_PU_SHIFT 14 /* GP14_PU */
3764#define WM8995_GP14_PU_WIDTH 1 /* GP14_PU */
3765#define WM8995_GP14_PD 0x2000 /* GP14_PD */
3766#define WM8995_GP14_PD_MASK 0x2000 /* GP14_PD */
3767#define WM8995_GP14_PD_SHIFT 13 /* GP14_PD */
3768#define WM8995_GP14_PD_WIDTH 1 /* GP14_PD */
3769#define WM8995_GP14_POL 0x0400 /* GP14_POL */
3770#define WM8995_GP14_POL_MASK 0x0400 /* GP14_POL */
3771#define WM8995_GP14_POL_SHIFT 10 /* GP14_POL */
3772#define WM8995_GP14_POL_WIDTH 1 /* GP14_POL */
3773#define WM8995_GP14_OP_CFG 0x0200 /* GP14_OP_CFG */
3774#define WM8995_GP14_OP_CFG_MASK 0x0200 /* GP14_OP_CFG */
3775#define WM8995_GP14_OP_CFG_SHIFT 9 /* GP14_OP_CFG */
3776#define WM8995_GP14_OP_CFG_WIDTH 1 /* GP14_OP_CFG */
3777#define WM8995_GP14_DB 0x0100 /* GP14_DB */
3778#define WM8995_GP14_DB_MASK 0x0100 /* GP14_DB */
3779#define WM8995_GP14_DB_SHIFT 8 /* GP14_DB */
3780#define WM8995_GP14_DB_WIDTH 1 /* GP14_DB */
3781#define WM8995_GP14_LVL 0x0040 /* GP14_LVL */
3782#define WM8995_GP14_LVL_MASK 0x0040 /* GP14_LVL */
3783#define WM8995_GP14_LVL_SHIFT 6 /* GP14_LVL */
3784#define WM8995_GP14_LVL_WIDTH 1 /* GP14_LVL */
3785#define WM8995_GP14_FN_MASK 0x001F /* GP14_FN - [4:0] */
3786#define WM8995_GP14_FN_SHIFT 0 /* GP14_FN - [4:0] */
3787#define WM8995_GP14_FN_WIDTH 5 /* GP14_FN - [4:0] */
3788
3789/*
3790 * R1824 (0x720) - Pull Control (1)
3791 */
3792#define WM8995_DMICDAT3_PD 0x4000 /* DMICDAT3_PD */
3793#define WM8995_DMICDAT3_PD_MASK 0x4000 /* DMICDAT3_PD */
3794#define WM8995_DMICDAT3_PD_SHIFT 14 /* DMICDAT3_PD */
3795#define WM8995_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */
3796#define WM8995_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */
3797#define WM8995_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */
3798#define WM8995_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */
3799#define WM8995_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
3800#define WM8995_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */
3801#define WM8995_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */
3802#define WM8995_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */
3803#define WM8995_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
3804#define WM8995_MCLK2_PU 0x0200 /* MCLK2_PU */
3805#define WM8995_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */
3806#define WM8995_MCLK2_PU_SHIFT 9 /* MCLK2_PU */
3807#define WM8995_MCLK2_PU_WIDTH 1 /* MCLK2_PU */
3808#define WM8995_MCLK2_PD 0x0100 /* MCLK2_PD */
3809#define WM8995_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */
3810#define WM8995_MCLK2_PD_SHIFT 8 /* MCLK2_PD */
3811#define WM8995_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
3812#define WM8995_MCLK1_PU 0x0080 /* MCLK1_PU */
3813#define WM8995_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */
3814#define WM8995_MCLK1_PU_SHIFT 7 /* MCLK1_PU */
3815#define WM8995_MCLK1_PU_WIDTH 1 /* MCLK1_PU */
3816#define WM8995_MCLK1_PD 0x0040 /* MCLK1_PD */
3817#define WM8995_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */
3818#define WM8995_MCLK1_PD_SHIFT 6 /* MCLK1_PD */
3819#define WM8995_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
3820#define WM8995_DACDAT1_PU 0x0020 /* DACDAT1_PU */
3821#define WM8995_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */
3822#define WM8995_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */
3823#define WM8995_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */
3824#define WM8995_DACDAT1_PD 0x0010 /* DACDAT1_PD */
3825#define WM8995_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */
3826#define WM8995_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */
3827#define WM8995_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */
3828#define WM8995_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */
3829#define WM8995_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */
3830#define WM8995_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */
3831#define WM8995_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */
3832#define WM8995_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */
3833#define WM8995_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */
3834#define WM8995_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */
3835#define WM8995_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */
3836#define WM8995_BCLK1_PU 0x0002 /* BCLK1_PU */
3837#define WM8995_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */
3838#define WM8995_BCLK1_PU_SHIFT 1 /* BCLK1_PU */
3839#define WM8995_BCLK1_PU_WIDTH 1 /* BCLK1_PU */
3840#define WM8995_BCLK1_PD 0x0001 /* BCLK1_PD */
3841#define WM8995_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */
3842#define WM8995_BCLK1_PD_SHIFT 0 /* BCLK1_PD */
3843#define WM8995_BCLK1_PD_WIDTH 1 /* BCLK1_PD */
3844
3845/*
3846 * R1825 (0x721) - Pull Control (2)
3847 */
3848#define WM8995_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */
3849#define WM8995_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */
3850#define WM8995_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */
3851#define WM8995_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
3852#define WM8995_MODE_PD 0x0004 /* MODE_PD */
3853#define WM8995_MODE_PD_MASK 0x0004 /* MODE_PD */
3854#define WM8995_MODE_PD_SHIFT 2 /* MODE_PD */
3855#define WM8995_MODE_PD_WIDTH 1 /* MODE_PD */
3856#define WM8995_CSNADDR_PD 0x0001 /* CSNADDR_PD */
3857#define WM8995_CSNADDR_PD_MASK 0x0001 /* CSNADDR_PD */
3858#define WM8995_CSNADDR_PD_SHIFT 0 /* CSNADDR_PD */
3859#define WM8995_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */
3860
3861/*
3862 * R1840 (0x730) - Interrupt Status 1
3863 */
3864#define WM8995_GP14_EINT 0x2000 /* GP14_EINT */
3865#define WM8995_GP14_EINT_MASK 0x2000 /* GP14_EINT */
3866#define WM8995_GP14_EINT_SHIFT 13 /* GP14_EINT */
3867#define WM8995_GP14_EINT_WIDTH 1 /* GP14_EINT */
3868#define WM8995_GP13_EINT 0x1000 /* GP13_EINT */
3869#define WM8995_GP13_EINT_MASK 0x1000 /* GP13_EINT */
3870#define WM8995_GP13_EINT_SHIFT 12 /* GP13_EINT */
3871#define WM8995_GP13_EINT_WIDTH 1 /* GP13_EINT */
3872#define WM8995_GP12_EINT 0x0800 /* GP12_EINT */
3873#define WM8995_GP12_EINT_MASK 0x0800 /* GP12_EINT */
3874#define WM8995_GP12_EINT_SHIFT 11 /* GP12_EINT */
3875#define WM8995_GP12_EINT_WIDTH 1 /* GP12_EINT */
3876#define WM8995_GP11_EINT 0x0400 /* GP11_EINT */
3877#define WM8995_GP11_EINT_MASK 0x0400 /* GP11_EINT */
3878#define WM8995_GP11_EINT_SHIFT 10 /* GP11_EINT */
3879#define WM8995_GP11_EINT_WIDTH 1 /* GP11_EINT */
3880#define WM8995_GP10_EINT 0x0200 /* GP10_EINT */
3881#define WM8995_GP10_EINT_MASK 0x0200 /* GP10_EINT */
3882#define WM8995_GP10_EINT_SHIFT 9 /* GP10_EINT */
3883#define WM8995_GP10_EINT_WIDTH 1 /* GP10_EINT */
3884#define WM8995_GP9_EINT 0x0100 /* GP9_EINT */
3885#define WM8995_GP9_EINT_MASK 0x0100 /* GP9_EINT */
3886#define WM8995_GP9_EINT_SHIFT 8 /* GP9_EINT */
3887#define WM8995_GP9_EINT_WIDTH 1 /* GP9_EINT */
3888#define WM8995_GP8_EINT 0x0080 /* GP8_EINT */
3889#define WM8995_GP8_EINT_MASK 0x0080 /* GP8_EINT */
3890#define WM8995_GP8_EINT_SHIFT 7 /* GP8_EINT */
3891#define WM8995_GP8_EINT_WIDTH 1 /* GP8_EINT */
3892#define WM8995_GP7_EINT 0x0040 /* GP7_EINT */
3893#define WM8995_GP7_EINT_MASK 0x0040 /* GP7_EINT */
3894#define WM8995_GP7_EINT_SHIFT 6 /* GP7_EINT */
3895#define WM8995_GP7_EINT_WIDTH 1 /* GP7_EINT */
3896#define WM8995_GP6_EINT 0x0020 /* GP6_EINT */
3897#define WM8995_GP6_EINT_MASK 0x0020 /* GP6_EINT */
3898#define WM8995_GP6_EINT_SHIFT 5 /* GP6_EINT */
3899#define WM8995_GP6_EINT_WIDTH 1 /* GP6_EINT */
3900#define WM8995_GP5_EINT 0x0010 /* GP5_EINT */
3901#define WM8995_GP5_EINT_MASK 0x0010 /* GP5_EINT */
3902#define WM8995_GP5_EINT_SHIFT 4 /* GP5_EINT */
3903#define WM8995_GP5_EINT_WIDTH 1 /* GP5_EINT */
3904#define WM8995_GP4_EINT 0x0008 /* GP4_EINT */
3905#define WM8995_GP4_EINT_MASK 0x0008 /* GP4_EINT */
3906#define WM8995_GP4_EINT_SHIFT 3 /* GP4_EINT */
3907#define WM8995_GP4_EINT_WIDTH 1 /* GP4_EINT */
3908#define WM8995_GP3_EINT 0x0004 /* GP3_EINT */
3909#define WM8995_GP3_EINT_MASK 0x0004 /* GP3_EINT */
3910#define WM8995_GP3_EINT_SHIFT 2 /* GP3_EINT */
3911#define WM8995_GP3_EINT_WIDTH 1 /* GP3_EINT */
3912#define WM8995_GP2_EINT 0x0002 /* GP2_EINT */
3913#define WM8995_GP2_EINT_MASK 0x0002 /* GP2_EINT */
3914#define WM8995_GP2_EINT_SHIFT 1 /* GP2_EINT */
3915#define WM8995_GP2_EINT_WIDTH 1 /* GP2_EINT */
3916#define WM8995_GP1_EINT 0x0001 /* GP1_EINT */
3917#define WM8995_GP1_EINT_MASK 0x0001 /* GP1_EINT */
3918#define WM8995_GP1_EINT_SHIFT 0 /* GP1_EINT */
3919#define WM8995_GP1_EINT_WIDTH 1 /* GP1_EINT */
3920
3921/*
3922 * R1841 (0x731) - Interrupt Status 2
3923 */
3924#define WM8995_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */
3925#define WM8995_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */
3926#define WM8995_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */
3927#define WM8995_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */
3928#define WM8995_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */
3929#define WM8995_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */
3930#define WM8995_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */
3931#define WM8995_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */
3932#define WM8995_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */
3933#define WM8995_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */
3934#define WM8995_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */
3935#define WM8995_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */
3936#define WM8995_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */
3937#define WM8995_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */
3938#define WM8995_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */
3939#define WM8995_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */
3940#define WM8995_AIF2DRC_SIG_DET_EINT 0x0100 /* AIF2DRC_SIG_DET_EINT */
3941#define WM8995_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* AIF2DRC_SIG_DET_EINT */
3942#define WM8995_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* AIF2DRC_SIG_DET_EINT */
3943#define WM8995_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */
3944#define WM8995_AIF1DRC2_SIG_DET_EINT 0x0080 /* AIF1DRC2_SIG_DET_EINT */
3945#define WM8995_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* AIF1DRC2_SIG_DET_EINT */
3946#define WM8995_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* AIF1DRC2_SIG_DET_EINT */
3947#define WM8995_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */
3948#define WM8995_AIF1DRC1_SIG_DET_EINT 0x0040 /* AIF1DRC1_SIG_DET_EINT */
3949#define WM8995_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* AIF1DRC1_SIG_DET_EINT */
3950#define WM8995_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* AIF1DRC1_SIG_DET_EINT */
3951#define WM8995_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */
3952#define WM8995_SRC2_LOCK_EINT 0x0020 /* SRC2_LOCK_EINT */
3953#define WM8995_SRC2_LOCK_EINT_MASK 0x0020 /* SRC2_LOCK_EINT */
3954#define WM8995_SRC2_LOCK_EINT_SHIFT 5 /* SRC2_LOCK_EINT */
3955#define WM8995_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */
3956#define WM8995_SRC1_LOCK_EINT 0x0010 /* SRC1_LOCK_EINT */
3957#define WM8995_SRC1_LOCK_EINT_MASK 0x0010 /* SRC1_LOCK_EINT */
3958#define WM8995_SRC1_LOCK_EINT_SHIFT 4 /* SRC1_LOCK_EINT */
3959#define WM8995_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */
3960#define WM8995_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */
3961#define WM8995_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */
3962#define WM8995_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */
3963#define WM8995_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */
3964#define WM8995_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */
3965#define WM8995_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */
3966#define WM8995_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */
3967#define WM8995_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */
3968#define WM8995_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */
3969#define WM8995_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */
3970#define WM8995_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */
3971#define WM8995_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */
3972#define WM8995_MICD_EINT 0x0001 /* MICD_EINT */
3973#define WM8995_MICD_EINT_MASK 0x0001 /* MICD_EINT */
3974#define WM8995_MICD_EINT_SHIFT 0 /* MICD_EINT */
3975#define WM8995_MICD_EINT_WIDTH 1 /* MICD_EINT */
3976
3977/*
3978 * R1842 (0x732) - Interrupt Raw Status 2
3979 */
3980#define WM8995_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */
3981#define WM8995_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */
3982#define WM8995_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */
3983#define WM8995_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */
3984#define WM8995_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */
3985#define WM8995_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */
3986#define WM8995_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */
3987#define WM8995_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */
3988#define WM8995_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */
3989#define WM8995_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */
3990#define WM8995_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */
3991#define WM8995_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */
3992#define WM8995_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */
3993#define WM8995_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */
3994#define WM8995_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */
3995#define WM8995_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */
3996#define WM8995_AIF2DRC_SIG_DET_STS 0x0100 /* AIF2DRC_SIG_DET_STS */
3997#define WM8995_AIF2DRC_SIG_DET_STS_MASK 0x0100 /* AIF2DRC_SIG_DET_STS */
3998#define WM8995_AIF2DRC_SIG_DET_STS_SHIFT 8 /* AIF2DRC_SIG_DET_STS */
3999#define WM8995_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */
4000#define WM8995_AIF1DRC2_SIG_DET_STS 0x0080 /* AIF1DRC2_SIG_DET_STS */
4001#define WM8995_AIF1DRC2_SIG_DET_STS_MASK 0x0080 /* AIF1DRC2_SIG_DET_STS */
4002#define WM8995_AIF1DRC2_SIG_DET_STS_SHIFT 7 /* AIF1DRC2_SIG_DET_STS */
4003#define WM8995_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */
4004#define WM8995_AIF1DRC1_SIG_DET_STS 0x0040 /* AIF1DRC1_SIG_DET_STS */
4005#define WM8995_AIF1DRC1_SIG_DET_STS_MASK 0x0040 /* AIF1DRC1_SIG_DET_STS */
4006#define WM8995_AIF1DRC1_SIG_DET_STS_SHIFT 6 /* AIF1DRC1_SIG_DET_STS */
4007#define WM8995_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */
4008#define WM8995_SRC2_LOCK_STS 0x0020 /* SRC2_LOCK_STS */
4009#define WM8995_SRC2_LOCK_STS_MASK 0x0020 /* SRC2_LOCK_STS */
4010#define WM8995_SRC2_LOCK_STS_SHIFT 5 /* SRC2_LOCK_STS */
4011#define WM8995_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */
4012#define WM8995_SRC1_LOCK_STS 0x0010 /* SRC1_LOCK_STS */
4013#define WM8995_SRC1_LOCK_STS_MASK 0x0010 /* SRC1_LOCK_STS */
4014#define WM8995_SRC1_LOCK_STS_SHIFT 4 /* SRC1_LOCK_STS */
4015#define WM8995_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */
4016#define WM8995_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */
4017#define WM8995_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */
4018#define WM8995_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */
4019#define WM8995_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */
4020#define WM8995_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */
4021#define WM8995_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */
4022#define WM8995_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */
4023#define WM8995_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */
4024
4025/*
4026 * R1848 (0x738) - Interrupt Status 1 Mask
4027 */
4028#define WM8995_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */
4029#define WM8995_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */
4030#define WM8995_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */
4031#define WM8995_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */
4032#define WM8995_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */
4033#define WM8995_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */
4034#define WM8995_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */
4035#define WM8995_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */
4036#define WM8995_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */
4037#define WM8995_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */
4038#define WM8995_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */
4039#define WM8995_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */
4040#define WM8995_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
4041#define WM8995_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
4042#define WM8995_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */
4043#define WM8995_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
4044#define WM8995_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
4045#define WM8995_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
4046#define WM8995_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */
4047#define WM8995_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
4048#define WM8995_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
4049#define WM8995_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
4050#define WM8995_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */
4051#define WM8995_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
4052#define WM8995_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
4053#define WM8995_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
4054#define WM8995_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */
4055#define WM8995_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
4056#define WM8995_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
4057#define WM8995_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
4058#define WM8995_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */
4059#define WM8995_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
4060#define WM8995_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
4061#define WM8995_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
4062#define WM8995_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
4063#define WM8995_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
4064#define WM8995_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
4065#define WM8995_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
4066#define WM8995_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
4067#define WM8995_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
4068#define WM8995_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
4069#define WM8995_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
4070#define WM8995_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
4071#define WM8995_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
4072#define WM8995_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
4073#define WM8995_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
4074#define WM8995_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
4075#define WM8995_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
4076#define WM8995_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
4077#define WM8995_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
4078#define WM8995_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
4079#define WM8995_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
4080#define WM8995_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
4081#define WM8995_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
4082#define WM8995_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
4083#define WM8995_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
4084
4085/*
4086 * R1849 (0x739) - Interrupt Status 2 Mask
4087 */
4088#define WM8995_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */
4089#define WM8995_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */
4090#define WM8995_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */
4091#define WM8995_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */
4092#define WM8995_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */
4093#define WM8995_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */
4094#define WM8995_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */
4095#define WM8995_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */
4096#define WM8995_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */
4097#define WM8995_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */
4098#define WM8995_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */
4099#define WM8995_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */
4100#define WM8995_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */
4101#define WM8995_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */
4102#define WM8995_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */
4103#define WM8995_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */
4104#define WM8995_IM_AIF2DRC_SIG_DET_EINT 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */
4105#define WM8995_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */
4106#define WM8995_IM_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* IM_AIF2DRC_SIG_DET_EINT */
4107#define WM8995_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */
4108#define WM8995_IM_AIF1DRC2_SIG_DET_EINT 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */
4109#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */
4110#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* IM_AIF1DRC2_SIG_DET_EINT */
4111#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */
4112#define WM8995_IM_AIF1DRC1_SIG_DET_EINT 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */
4113#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */
4114#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* IM_AIF1DRC1_SIG_DET_EINT */
4115#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */
4116#define WM8995_IM_SRC2_LOCK_EINT 0x0020 /* IM_SRC2_LOCK_EINT */
4117#define WM8995_IM_SRC2_LOCK_EINT_MASK 0x0020 /* IM_SRC2_LOCK_EINT */
4118#define WM8995_IM_SRC2_LOCK_EINT_SHIFT 5 /* IM_SRC2_LOCK_EINT */
4119#define WM8995_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */
4120#define WM8995_IM_SRC1_LOCK_EINT 0x0010 /* IM_SRC1_LOCK_EINT */
4121#define WM8995_IM_SRC1_LOCK_EINT_MASK 0x0010 /* IM_SRC1_LOCK_EINT */
4122#define WM8995_IM_SRC1_LOCK_EINT_SHIFT 4 /* IM_SRC1_LOCK_EINT */
4123#define WM8995_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */
4124#define WM8995_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */
4125#define WM8995_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */
4126#define WM8995_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */
4127#define WM8995_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */
4128#define WM8995_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */
4129#define WM8995_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */
4130#define WM8995_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */
4131#define WM8995_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */
4132#define WM8995_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */
4133#define WM8995_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */
4134#define WM8995_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */
4135#define WM8995_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */
4136#define WM8995_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */
4137#define WM8995_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */
4138#define WM8995_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */
4139#define WM8995_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */
4140
4141/*
4142 * R1856 (0x740) - Interrupt Control
4143 */
4144#define WM8995_IM_IRQ 0x0001 /* IM_IRQ */
4145#define WM8995_IM_IRQ_MASK 0x0001 /* IM_IRQ */
4146#define WM8995_IM_IRQ_SHIFT 0 /* IM_IRQ */
4147#define WM8995_IM_IRQ_WIDTH 1 /* IM_IRQ */
4148
4149/*
4150 * R2048 (0x800) - Left PDM Speaker 1
4151 */
4152#define WM8995_SPK1L_ENA 0x0010 /* SPK1L_ENA */
4153#define WM8995_SPK1L_ENA_MASK 0x0010 /* SPK1L_ENA */
4154#define WM8995_SPK1L_ENA_SHIFT 4 /* SPK1L_ENA */
4155#define WM8995_SPK1L_ENA_WIDTH 1 /* SPK1L_ENA */
4156#define WM8995_SPK1L_MUTE 0x0008 /* SPK1L_MUTE */
4157#define WM8995_SPK1L_MUTE_MASK 0x0008 /* SPK1L_MUTE */
4158#define WM8995_SPK1L_MUTE_SHIFT 3 /* SPK1L_MUTE */
4159#define WM8995_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */
4160#define WM8995_SPK1L_MUTE_ZC 0x0004 /* SPK1L_MUTE_ZC */
4161#define WM8995_SPK1L_MUTE_ZC_MASK 0x0004 /* SPK1L_MUTE_ZC */
4162#define WM8995_SPK1L_MUTE_ZC_SHIFT 2 /* SPK1L_MUTE_ZC */
4163#define WM8995_SPK1L_MUTE_ZC_WIDTH 1 /* SPK1L_MUTE_ZC */
4164#define WM8995_SPK1L_SRC_MASK 0x0003 /* SPK1L_SRC - [1:0] */
4165#define WM8995_SPK1L_SRC_SHIFT 0 /* SPK1L_SRC - [1:0] */
4166#define WM8995_SPK1L_SRC_WIDTH 2 /* SPK1L_SRC - [1:0] */
4167
4168/*
4169 * R2049 (0x801) - Right PDM Speaker 1
4170 */
4171#define WM8995_SPK1R_ENA 0x0010 /* SPK1R_ENA */
4172#define WM8995_SPK1R_ENA_MASK 0x0010 /* SPK1R_ENA */
4173#define WM8995_SPK1R_ENA_SHIFT 4 /* SPK1R_ENA */
4174#define WM8995_SPK1R_ENA_WIDTH 1 /* SPK1R_ENA */
4175#define WM8995_SPK1R_MUTE 0x0008 /* SPK1R_MUTE */
4176#define WM8995_SPK1R_MUTE_MASK 0x0008 /* SPK1R_MUTE */
4177#define WM8995_SPK1R_MUTE_SHIFT 3 /* SPK1R_MUTE */
4178#define WM8995_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */
4179#define WM8995_SPK1R_MUTE_ZC 0x0004 /* SPK1R_MUTE_ZC */
4180#define WM8995_SPK1R_MUTE_ZC_MASK 0x0004 /* SPK1R_MUTE_ZC */
4181#define WM8995_SPK1R_MUTE_ZC_SHIFT 2 /* SPK1R_MUTE_ZC */
4182#define WM8995_SPK1R_MUTE_ZC_WIDTH 1 /* SPK1R_MUTE_ZC */
4183#define WM8995_SPK1R_SRC_MASK 0x0003 /* SPK1R_SRC - [1:0] */
4184#define WM8995_SPK1R_SRC_SHIFT 0 /* SPK1R_SRC - [1:0] */
4185#define WM8995_SPK1R_SRC_WIDTH 2 /* SPK1R_SRC - [1:0] */
4186
4187/*
4188 * R2050 (0x802) - PDM Speaker 1 Mute Sequence
4189 */
4190#define WM8995_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */
4191#define WM8995_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */
4192#define WM8995_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */
4193
4194/*
4195 * R2056 (0x808) - Left PDM Speaker 2
4196 */
4197#define WM8995_SPK2L_ENA 0x0010 /* SPK2L_ENA */
4198#define WM8995_SPK2L_ENA_MASK 0x0010 /* SPK2L_ENA */
4199#define WM8995_SPK2L_ENA_SHIFT 4 /* SPK2L_ENA */
4200#define WM8995_SPK2L_ENA_WIDTH 1 /* SPK2L_ENA */
4201#define WM8995_SPK2L_MUTE 0x0008 /* SPK2L_MUTE */
4202#define WM8995_SPK2L_MUTE_MASK 0x0008 /* SPK2L_MUTE */
4203#define WM8995_SPK2L_MUTE_SHIFT 3 /* SPK2L_MUTE */
4204#define WM8995_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */
4205#define WM8995_SPK2L_MUTE_ZC 0x0004 /* SPK2L_MUTE_ZC */
4206#define WM8995_SPK2L_MUTE_ZC_MASK 0x0004 /* SPK2L_MUTE_ZC */
4207#define WM8995_SPK2L_MUTE_ZC_SHIFT 2 /* SPK2L_MUTE_ZC */
4208#define WM8995_SPK2L_MUTE_ZC_WIDTH 1 /* SPK2L_MUTE_ZC */
4209#define WM8995_SPK2L_SRC_MASK 0x0003 /* SPK2L_SRC - [1:0] */
4210#define WM8995_SPK2L_SRC_SHIFT 0 /* SPK2L_SRC - [1:0] */
4211#define WM8995_SPK2L_SRC_WIDTH 2 /* SPK2L_SRC - [1:0] */
4212
4213/*
4214 * R2057 (0x809) - Right PDM Speaker 2
4215 */
4216#define WM8995_SPK2R_ENA 0x0010 /* SPK2R_ENA */
4217#define WM8995_SPK2R_ENA_MASK 0x0010 /* SPK2R_ENA */
4218#define WM8995_SPK2R_ENA_SHIFT 4 /* SPK2R_ENA */
4219#define WM8995_SPK2R_ENA_WIDTH 1 /* SPK2R_ENA */
4220#define WM8995_SPK2R_MUTE 0x0008 /* SPK2R_MUTE */
4221#define WM8995_SPK2R_MUTE_MASK 0x0008 /* SPK2R_MUTE */
4222#define WM8995_SPK2R_MUTE_SHIFT 3 /* SPK2R_MUTE */
4223#define WM8995_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */
4224#define WM8995_SPK2R_MUTE_ZC 0x0004 /* SPK2R_MUTE_ZC */
4225#define WM8995_SPK2R_MUTE_ZC_MASK 0x0004 /* SPK2R_MUTE_ZC */
4226#define WM8995_SPK2R_MUTE_ZC_SHIFT 2 /* SPK2R_MUTE_ZC */
4227#define WM8995_SPK2R_MUTE_ZC_WIDTH 1 /* SPK2R_MUTE_ZC */
4228#define WM8995_SPK2R_SRC_MASK 0x0003 /* SPK2R_SRC - [1:0] */
4229#define WM8995_SPK2R_SRC_SHIFT 0 /* SPK2R_SRC - [1:0] */
4230#define WM8995_SPK2R_SRC_WIDTH 2 /* SPK2R_SRC - [1:0] */
4231
4232/*
4233 * R2058 (0x80A) - PDM Speaker 2 Mute Sequence
4234 */
4235#define WM8995_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */
4236#define WM8995_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */
4237#define WM8995_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */
4238
4239/*
4240 * R12288 (0x3000) - Write Sequencer 0
4241 */
4242#define WM8995_WSEQ_ADDR0_MASK 0x3FFF /* WSEQ_ADDR0 - [13:0] */
4243#define WM8995_WSEQ_ADDR0_SHIFT 0 /* WSEQ_ADDR0 - [13:0] */
4244#define WM8995_WSEQ_ADDR0_WIDTH 14 /* WSEQ_ADDR0 - [13:0] */
4245
4246/*
4247 * R12289 (0x3001) - Write Sequencer 1
4248 */
4249#define WM8995_WSEQ_DATA0_MASK 0x00FF /* WSEQ_DATA0 - [7:0] */
4250#define WM8995_WSEQ_DATA0_SHIFT 0 /* WSEQ_DATA0 - [7:0] */
4251#define WM8995_WSEQ_DATA0_WIDTH 8 /* WSEQ_DATA0 - [7:0] */
4252
4253/*
4254 * R12290 (0x3002) - Write Sequencer 2
4255 */
4256#define WM8995_WSEQ_DATA_WIDTH0_MASK 0x0700 /* WSEQ_DATA_WIDTH0 - [10:8] */
4257#define WM8995_WSEQ_DATA_WIDTH0_SHIFT 8 /* WSEQ_DATA_WIDTH0 - [10:8] */
4258#define WM8995_WSEQ_DATA_WIDTH0_WIDTH 3 /* WSEQ_DATA_WIDTH0 - [10:8] */
4259#define WM8995_WSEQ_DATA_START0_MASK 0x000F /* WSEQ_DATA_START0 - [3:0] */
4260#define WM8995_WSEQ_DATA_START0_SHIFT 0 /* WSEQ_DATA_START0 - [3:0] */
4261#define WM8995_WSEQ_DATA_START0_WIDTH 4 /* WSEQ_DATA_START0 - [3:0] */
4262
4263/*
4264 * R12291 (0x3003) - Write Sequencer 3
4265 */
4266#define WM8995_WSEQ_EOS0 0x0100 /* WSEQ_EOS0 */
4267#define WM8995_WSEQ_EOS0_MASK 0x0100 /* WSEQ_EOS0 */
4268#define WM8995_WSEQ_EOS0_SHIFT 8 /* WSEQ_EOS0 */
4269#define WM8995_WSEQ_EOS0_WIDTH 1 /* WSEQ_EOS0 */
4270#define WM8995_WSEQ_DELAY0_MASK 0x000F /* WSEQ_DELAY0 - [3:0] */
4271#define WM8995_WSEQ_DELAY0_SHIFT 0 /* WSEQ_DELAY0 - [3:0] */
4272#define WM8995_WSEQ_DELAY0_WIDTH 4 /* WSEQ_DELAY0 - [3:0] */
4273
4274/*
4275 * R12292 (0x3004) - Write Sequencer 4
4276 */
4277#define WM8995_WSEQ_ADDR1_MASK 0x3FFF /* WSEQ_ADDR1 - [13:0] */
4278#define WM8995_WSEQ_ADDR1_SHIFT 0 /* WSEQ_ADDR1 - [13:0] */
4279#define WM8995_WSEQ_ADDR1_WIDTH 14 /* WSEQ_ADDR1 - [13:0] */
4280
4281/*
4282 * R12293 (0x3005) - Write Sequencer 5
4283 */
4284#define WM8995_WSEQ_DATA1_MASK 0x00FF /* WSEQ_DATA1 - [7:0] */
4285#define WM8995_WSEQ_DATA1_SHIFT 0 /* WSEQ_DATA1 - [7:0] */
4286#define WM8995_WSEQ_DATA1_WIDTH 8 /* WSEQ_DATA1 - [7:0] */
4287
4288/*
4289 * R12294 (0x3006) - Write Sequencer 6
4290 */
4291#define WM8995_WSEQ_DATA_WIDTH1_MASK 0x0700 /* WSEQ_DATA_WIDTH1 - [10:8] */
4292#define WM8995_WSEQ_DATA_WIDTH1_SHIFT 8 /* WSEQ_DATA_WIDTH1 - [10:8] */
4293#define WM8995_WSEQ_DATA_WIDTH1_WIDTH 3 /* WSEQ_DATA_WIDTH1 - [10:8] */
4294#define WM8995_WSEQ_DATA_START1_MASK 0x000F /* WSEQ_DATA_START1 - [3:0] */
4295#define WM8995_WSEQ_DATA_START1_SHIFT 0 /* WSEQ_DATA_START1 - [3:0] */
4296#define WM8995_WSEQ_DATA_START1_WIDTH 4 /* WSEQ_DATA_START1 - [3:0] */
4297
4298/*
4299 * R12295 (0x3007) - Write Sequencer 7
4300 */
4301#define WM8995_WSEQ_EOS1 0x0100 /* WSEQ_EOS1 */
4302#define WM8995_WSEQ_EOS1_MASK 0x0100 /* WSEQ_EOS1 */
4303#define WM8995_WSEQ_EOS1_SHIFT 8 /* WSEQ_EOS1 */
4304#define WM8995_WSEQ_EOS1_WIDTH 1 /* WSEQ_EOS1 */
4305#define WM8995_WSEQ_DELAY1_MASK 0x000F /* WSEQ_DELAY1 - [3:0] */
4306#define WM8995_WSEQ_DELAY1_SHIFT 0 /* WSEQ_DELAY1 - [3:0] */
4307#define WM8995_WSEQ_DELAY1_WIDTH 4 /* WSEQ_DELAY1 - [3:0] */
4308
4309/*
4310 * R12296 (0x3008) - Write Sequencer 8
4311 */
4312#define WM8995_WSEQ_ADDR2_MASK 0x3FFF /* WSEQ_ADDR2 - [13:0] */
4313#define WM8995_WSEQ_ADDR2_SHIFT 0 /* WSEQ_ADDR2 - [13:0] */
4314#define WM8995_WSEQ_ADDR2_WIDTH 14 /* WSEQ_ADDR2 - [13:0] */
4315
4316/*
4317 * R12297 (0x3009) - Write Sequencer 9
4318 */
4319#define WM8995_WSEQ_DATA2_MASK 0x00FF /* WSEQ_DATA2 - [7:0] */
4320#define WM8995_WSEQ_DATA2_SHIFT 0 /* WSEQ_DATA2 - [7:0] */
4321#define WM8995_WSEQ_DATA2_WIDTH 8 /* WSEQ_DATA2 - [7:0] */
4322
4323/*
4324 * R12298 (0x300A) - Write Sequencer 10
4325 */
4326#define WM8995_WSEQ_DATA_WIDTH2_MASK 0x0700 /* WSEQ_DATA_WIDTH2 - [10:8] */
4327#define WM8995_WSEQ_DATA_WIDTH2_SHIFT 8 /* WSEQ_DATA_WIDTH2 - [10:8] */
4328#define WM8995_WSEQ_DATA_WIDTH2_WIDTH 3 /* WSEQ_DATA_WIDTH2 - [10:8] */
4329#define WM8995_WSEQ_DATA_START2_MASK 0x000F /* WSEQ_DATA_START2 - [3:0] */
4330#define WM8995_WSEQ_DATA_START2_SHIFT 0 /* WSEQ_DATA_START2 - [3:0] */
4331#define WM8995_WSEQ_DATA_START2_WIDTH 4 /* WSEQ_DATA_START2 - [3:0] */
4332
4333/*
4334 * R12299 (0x300B) - Write Sequencer 11
4335 */
4336#define WM8995_WSEQ_EOS2 0x0100 /* WSEQ_EOS2 */
4337#define WM8995_WSEQ_EOS2_MASK 0x0100 /* WSEQ_EOS2 */
4338#define WM8995_WSEQ_EOS2_SHIFT 8 /* WSEQ_EOS2 */
4339#define WM8995_WSEQ_EOS2_WIDTH 1 /* WSEQ_EOS2 */
4340#define WM8995_WSEQ_DELAY2_MASK 0x000F /* WSEQ_DELAY2 - [3:0] */
4341#define WM8995_WSEQ_DELAY2_SHIFT 0 /* WSEQ_DELAY2 - [3:0] */
4342#define WM8995_WSEQ_DELAY2_WIDTH 4 /* WSEQ_DELAY2 - [3:0] */
4343
4344/*
4345 * R12300 (0x300C) - Write Sequencer 12
4346 */
4347#define WM8995_WSEQ_ADDR3_MASK 0x3FFF /* WSEQ_ADDR3 - [13:0] */
4348#define WM8995_WSEQ_ADDR3_SHIFT 0 /* WSEQ_ADDR3 - [13:0] */
4349#define WM8995_WSEQ_ADDR3_WIDTH 14 /* WSEQ_ADDR3 - [13:0] */
4350
4351/*
4352 * R12301 (0x300D) - Write Sequencer 13
4353 */
4354#define WM8995_WSEQ_DATA3_MASK 0x00FF /* WSEQ_DATA3 - [7:0] */
4355#define WM8995_WSEQ_DATA3_SHIFT 0 /* WSEQ_DATA3 - [7:0] */
4356#define WM8995_WSEQ_DATA3_WIDTH 8 /* WSEQ_DATA3 - [7:0] */
4357
4358/*
4359 * R12302 (0x300E) - Write Sequencer 14
4360 */
4361#define WM8995_WSEQ_DATA_WIDTH3_MASK 0x0700 /* WSEQ_DATA_WIDTH3 - [10:8] */
4362#define WM8995_WSEQ_DATA_WIDTH3_SHIFT 8 /* WSEQ_DATA_WIDTH3 - [10:8] */
4363#define WM8995_WSEQ_DATA_WIDTH3_WIDTH 3 /* WSEQ_DATA_WIDTH3 - [10:8] */
4364#define WM8995_WSEQ_DATA_START3_MASK 0x000F /* WSEQ_DATA_START3 - [3:0] */
4365#define WM8995_WSEQ_DATA_START3_SHIFT 0 /* WSEQ_DATA_START3 - [3:0] */
4366#define WM8995_WSEQ_DATA_START3_WIDTH 4 /* WSEQ_DATA_START3 - [3:0] */
4367
4368/*
4369 * R12303 (0x300F) - Write Sequencer 15
4370 */
4371#define WM8995_WSEQ_EOS3 0x0100 /* WSEQ_EOS3 */
4372#define WM8995_WSEQ_EOS3_MASK 0x0100 /* WSEQ_EOS3 */
4373#define WM8995_WSEQ_EOS3_SHIFT 8 /* WSEQ_EOS3 */
4374#define WM8995_WSEQ_EOS3_WIDTH 1 /* WSEQ_EOS3 */
4375#define WM8995_WSEQ_DELAY3_MASK 0x000F /* WSEQ_DELAY3 - [3:0] */
4376#define WM8995_WSEQ_DELAY3_SHIFT 0 /* WSEQ_DELAY3 - [3:0] */
4377#define WM8995_WSEQ_DELAY3_WIDTH 4 /* WSEQ_DELAY3 - [3:0] */
4378
4379/*
4380 * R12304 (0x3010) - Write Sequencer 16
4381 */
4382#define WM8995_WSEQ_ADDR4_MASK 0x3FFF /* WSEQ_ADDR4 - [13:0] */
4383#define WM8995_WSEQ_ADDR4_SHIFT 0 /* WSEQ_ADDR4 - [13:0] */
4384#define WM8995_WSEQ_ADDR4_WIDTH 14 /* WSEQ_ADDR4 - [13:0] */
4385
4386/*
4387 * R12305 (0x3011) - Write Sequencer 17
4388 */
4389#define WM8995_WSEQ_DATA4_MASK 0x00FF /* WSEQ_DATA4 - [7:0] */
4390#define WM8995_WSEQ_DATA4_SHIFT 0 /* WSEQ_DATA4 - [7:0] */
4391#define WM8995_WSEQ_DATA4_WIDTH 8 /* WSEQ_DATA4 - [7:0] */
4392
4393/*
4394 * R12306 (0x3012) - Write Sequencer 18
4395 */
4396#define WM8995_WSEQ_DATA_WIDTH4_MASK 0x0700 /* WSEQ_DATA_WIDTH4 - [10:8] */
4397#define WM8995_WSEQ_DATA_WIDTH4_SHIFT 8 /* WSEQ_DATA_WIDTH4 - [10:8] */
4398#define WM8995_WSEQ_DATA_WIDTH4_WIDTH 3 /* WSEQ_DATA_WIDTH4 - [10:8] */
4399#define WM8995_WSEQ_DATA_START4_MASK 0x000F /* WSEQ_DATA_START4 - [3:0] */
4400#define WM8995_WSEQ_DATA_START4_SHIFT 0 /* WSEQ_DATA_START4 - [3:0] */
4401#define WM8995_WSEQ_DATA_START4_WIDTH 4 /* WSEQ_DATA_START4 - [3:0] */
4402
4403/*
4404 * R12307 (0x3013) - Write Sequencer 19
4405 */
4406#define WM8995_WSEQ_EOS4 0x0100 /* WSEQ_EOS4 */
4407#define WM8995_WSEQ_EOS4_MASK 0x0100 /* WSEQ_EOS4 */
4408#define WM8995_WSEQ_EOS4_SHIFT 8 /* WSEQ_EOS4 */
4409#define WM8995_WSEQ_EOS4_WIDTH 1 /* WSEQ_EOS4 */
4410#define WM8995_WSEQ_DELAY4_MASK 0x000F /* WSEQ_DELAY4 - [3:0] */
4411#define WM8995_WSEQ_DELAY4_SHIFT 0 /* WSEQ_DELAY4 - [3:0] */
4412#define WM8995_WSEQ_DELAY4_WIDTH 4 /* WSEQ_DELAY4 - [3:0] */
4413
4414/*
4415 * R12308 (0x3014) - Write Sequencer 20
4416 */
4417#define WM8995_WSEQ_ADDR5_MASK 0x3FFF /* WSEQ_ADDR5 - [13:0] */
4418#define WM8995_WSEQ_ADDR5_SHIFT 0 /* WSEQ_ADDR5 - [13:0] */
4419#define WM8995_WSEQ_ADDR5_WIDTH 14 /* WSEQ_ADDR5 - [13:0] */
4420
4421/*
4422 * R12309 (0x3015) - Write Sequencer 21
4423 */
4424#define WM8995_WSEQ_DATA5_MASK 0x00FF /* WSEQ_DATA5 - [7:0] */
4425#define WM8995_WSEQ_DATA5_SHIFT 0 /* WSEQ_DATA5 - [7:0] */
4426#define WM8995_WSEQ_DATA5_WIDTH 8 /* WSEQ_DATA5 - [7:0] */
4427
4428/*
4429 * R12310 (0x3016) - Write Sequencer 22
4430 */
4431#define WM8995_WSEQ_DATA_WIDTH5_MASK 0x0700 /* WSEQ_DATA_WIDTH5 - [10:8] */
4432#define WM8995_WSEQ_DATA_WIDTH5_SHIFT 8 /* WSEQ_DATA_WIDTH5 - [10:8] */
4433#define WM8995_WSEQ_DATA_WIDTH5_WIDTH 3 /* WSEQ_DATA_WIDTH5 - [10:8] */
4434#define WM8995_WSEQ_DATA_START5_MASK 0x000F /* WSEQ_DATA_START5 - [3:0] */
4435#define WM8995_WSEQ_DATA_START5_SHIFT 0 /* WSEQ_DATA_START5 - [3:0] */
4436#define WM8995_WSEQ_DATA_START5_WIDTH 4 /* WSEQ_DATA_START5 - [3:0] */
4437
4438/*
4439 * R12311 (0x3017) - Write Sequencer 23
4440 */
4441#define WM8995_WSEQ_EOS5 0x0100 /* WSEQ_EOS5 */
4442#define WM8995_WSEQ_EOS5_MASK 0x0100 /* WSEQ_EOS5 */
4443#define WM8995_WSEQ_EOS5_SHIFT 8 /* WSEQ_EOS5 */
4444#define WM8995_WSEQ_EOS5_WIDTH 1 /* WSEQ_EOS5 */
4445#define WM8995_WSEQ_DELAY5_MASK 0x000F /* WSEQ_DELAY5 - [3:0] */
4446#define WM8995_WSEQ_DELAY5_SHIFT 0 /* WSEQ_DELAY5 - [3:0] */
4447#define WM8995_WSEQ_DELAY5_WIDTH 4 /* WSEQ_DELAY5 - [3:0] */
4448
4449/*
4450 * R12312 (0x3018) - Write Sequencer 24
4451 */
4452#define WM8995_WSEQ_ADDR6_MASK 0x3FFF /* WSEQ_ADDR6 - [13:0] */
4453#define WM8995_WSEQ_ADDR6_SHIFT 0 /* WSEQ_ADDR6 - [13:0] */
4454#define WM8995_WSEQ_ADDR6_WIDTH 14 /* WSEQ_ADDR6 - [13:0] */
4455
4456/*
4457 * R12313 (0x3019) - Write Sequencer 25
4458 */
4459#define WM8995_WSEQ_DATA6_MASK 0x00FF /* WSEQ_DATA6 - [7:0] */
4460#define WM8995_WSEQ_DATA6_SHIFT 0 /* WSEQ_DATA6 - [7:0] */
4461#define WM8995_WSEQ_DATA6_WIDTH 8 /* WSEQ_DATA6 - [7:0] */
4462
4463/*
4464 * R12314 (0x301A) - Write Sequencer 26
4465 */
4466#define WM8995_WSEQ_DATA_WIDTH6_MASK 0x0700 /* WSEQ_DATA_WIDTH6 - [10:8] */
4467#define WM8995_WSEQ_DATA_WIDTH6_SHIFT 8 /* WSEQ_DATA_WIDTH6 - [10:8] */
4468#define WM8995_WSEQ_DATA_WIDTH6_WIDTH 3 /* WSEQ_DATA_WIDTH6 - [10:8] */
4469#define WM8995_WSEQ_DATA_START6_MASK 0x000F /* WSEQ_DATA_START6 - [3:0] */
4470#define WM8995_WSEQ_DATA_START6_SHIFT 0 /* WSEQ_DATA_START6 - [3:0] */
4471#define WM8995_WSEQ_DATA_START6_WIDTH 4 /* WSEQ_DATA_START6 - [3:0] */
4472
4473/*
4474 * R12315 (0x301B) - Write Sequencer 27
4475 */
4476#define WM8995_WSEQ_EOS6 0x0100 /* WSEQ_EOS6 */
4477#define WM8995_WSEQ_EOS6_MASK 0x0100 /* WSEQ_EOS6 */
4478#define WM8995_WSEQ_EOS6_SHIFT 8 /* WSEQ_EOS6 */
4479#define WM8995_WSEQ_EOS6_WIDTH 1 /* WSEQ_EOS6 */
4480#define WM8995_WSEQ_DELAY6_MASK 0x000F /* WSEQ_DELAY6 - [3:0] */
4481#define WM8995_WSEQ_DELAY6_SHIFT 0 /* WSEQ_DELAY6 - [3:0] */
4482#define WM8995_WSEQ_DELAY6_WIDTH 4 /* WSEQ_DELAY6 - [3:0] */
4483
4484/*
4485 * R12316 (0x301C) - Write Sequencer 28
4486 */
4487#define WM8995_WSEQ_ADDR7_MASK 0x3FFF /* WSEQ_ADDR7 - [13:0] */
4488#define WM8995_WSEQ_ADDR7_SHIFT 0 /* WSEQ_ADDR7 - [13:0] */
4489#define WM8995_WSEQ_ADDR7_WIDTH 14 /* WSEQ_ADDR7 - [13:0] */
4490
4491/*
4492 * R12317 (0x301D) - Write Sequencer 29
4493 */
4494#define WM8995_WSEQ_DATA7_MASK 0x00FF /* WSEQ_DATA7 - [7:0] */
4495#define WM8995_WSEQ_DATA7_SHIFT 0 /* WSEQ_DATA7 - [7:0] */
4496#define WM8995_WSEQ_DATA7_WIDTH 8 /* WSEQ_DATA7 - [7:0] */
4497
4498/*
4499 * R12318 (0x301E) - Write Sequencer 30
4500 */
4501#define WM8995_WSEQ_DATA_WIDTH7_MASK 0x0700 /* WSEQ_DATA_WIDTH7 - [10:8] */
4502#define WM8995_WSEQ_DATA_WIDTH7_SHIFT 8 /* WSEQ_DATA_WIDTH7 - [10:8] */
4503#define WM8995_WSEQ_DATA_WIDTH7_WIDTH 3 /* WSEQ_DATA_WIDTH7 - [10:8] */
4504#define WM8995_WSEQ_DATA_START7_MASK 0x000F /* WSEQ_DATA_START7 - [3:0] */
4505#define WM8995_WSEQ_DATA_START7_SHIFT 0 /* WSEQ_DATA_START7 - [3:0] */
4506#define WM8995_WSEQ_DATA_START7_WIDTH 4 /* WSEQ_DATA_START7 - [3:0] */
4507
4508/*
4509 * R12319 (0x301F) - Write Sequencer 31
4510 */
4511#define WM8995_WSEQ_EOS7 0x0100 /* WSEQ_EOS7 */
4512#define WM8995_WSEQ_EOS7_MASK 0x0100 /* WSEQ_EOS7 */
4513#define WM8995_WSEQ_EOS7_SHIFT 8 /* WSEQ_EOS7 */
4514#define WM8995_WSEQ_EOS7_WIDTH 1 /* WSEQ_EOS7 */
4515#define WM8995_WSEQ_DELAY7_MASK 0x000F /* WSEQ_DELAY7 - [3:0] */
4516#define WM8995_WSEQ_DELAY7_SHIFT 0 /* WSEQ_DELAY7 - [3:0] */
4517#define WM8995_WSEQ_DELAY7_WIDTH 4 /* WSEQ_DELAY7 - [3:0] */
4518
4519/*
4520 * R12320 (0x3020) - Write Sequencer 32
4521 */
4522#define WM8995_WSEQ_ADDR8_MASK 0x3FFF /* WSEQ_ADDR8 - [13:0] */
4523#define WM8995_WSEQ_ADDR8_SHIFT 0 /* WSEQ_ADDR8 - [13:0] */
4524#define WM8995_WSEQ_ADDR8_WIDTH 14 /* WSEQ_ADDR8 - [13:0] */
4525
4526/*
4527 * R12321 (0x3021) - Write Sequencer 33
4528 */
4529#define WM8995_WSEQ_DATA8_MASK 0x00FF /* WSEQ_DATA8 - [7:0] */
4530#define WM8995_WSEQ_DATA8_SHIFT 0 /* WSEQ_DATA8 - [7:0] */
4531#define WM8995_WSEQ_DATA8_WIDTH 8 /* WSEQ_DATA8 - [7:0] */
4532
4533/*
4534 * R12322 (0x3022) - Write Sequencer 34
4535 */
4536#define WM8995_WSEQ_DATA_WIDTH8_MASK 0x0700 /* WSEQ_DATA_WIDTH8 - [10:8] */
4537#define WM8995_WSEQ_DATA_WIDTH8_SHIFT 8 /* WSEQ_DATA_WIDTH8 - [10:8] */
4538#define WM8995_WSEQ_DATA_WIDTH8_WIDTH 3 /* WSEQ_DATA_WIDTH8 - [10:8] */
4539#define WM8995_WSEQ_DATA_START8_MASK 0x000F /* WSEQ_DATA_START8 - [3:0] */
4540#define WM8995_WSEQ_DATA_START8_SHIFT 0 /* WSEQ_DATA_START8 - [3:0] */
4541#define WM8995_WSEQ_DATA_START8_WIDTH 4 /* WSEQ_DATA_START8 - [3:0] */
4542
4543/*
4544 * R12323 (0x3023) - Write Sequencer 35
4545 */
4546#define WM8995_WSEQ_EOS8 0x0100 /* WSEQ_EOS8 */
4547#define WM8995_WSEQ_EOS8_MASK 0x0100 /* WSEQ_EOS8 */
4548#define WM8995_WSEQ_EOS8_SHIFT 8 /* WSEQ_EOS8 */
4549#define WM8995_WSEQ_EOS8_WIDTH 1 /* WSEQ_EOS8 */
4550#define WM8995_WSEQ_DELAY8_MASK 0x000F /* WSEQ_DELAY8 - [3:0] */
4551#define WM8995_WSEQ_DELAY8_SHIFT 0 /* WSEQ_DELAY8 - [3:0] */
4552#define WM8995_WSEQ_DELAY8_WIDTH 4 /* WSEQ_DELAY8 - [3:0] */
4553
4554/*
4555 * R12324 (0x3024) - Write Sequencer 36
4556 */
4557#define WM8995_WSEQ_ADDR9_MASK 0x3FFF /* WSEQ_ADDR9 - [13:0] */
4558#define WM8995_WSEQ_ADDR9_SHIFT 0 /* WSEQ_ADDR9 - [13:0] */
4559#define WM8995_WSEQ_ADDR9_WIDTH 14 /* WSEQ_ADDR9 - [13:0] */
4560
4561/*
4562 * R12325 (0x3025) - Write Sequencer 37
4563 */
4564#define WM8995_WSEQ_DATA9_MASK 0x00FF /* WSEQ_DATA9 - [7:0] */
4565#define WM8995_WSEQ_DATA9_SHIFT 0 /* WSEQ_DATA9 - [7:0] */
4566#define WM8995_WSEQ_DATA9_WIDTH 8 /* WSEQ_DATA9 - [7:0] */
4567
4568/*
4569 * R12326 (0x3026) - Write Sequencer 38
4570 */
4571#define WM8995_WSEQ_DATA_WIDTH9_MASK 0x0700 /* WSEQ_DATA_WIDTH9 - [10:8] */
4572#define WM8995_WSEQ_DATA_WIDTH9_SHIFT 8 /* WSEQ_DATA_WIDTH9 - [10:8] */
4573#define WM8995_WSEQ_DATA_WIDTH9_WIDTH 3 /* WSEQ_DATA_WIDTH9 - [10:8] */
4574#define WM8995_WSEQ_DATA_START9_MASK 0x000F /* WSEQ_DATA_START9 - [3:0] */
4575#define WM8995_WSEQ_DATA_START9_SHIFT 0 /* WSEQ_DATA_START9 - [3:0] */
4576#define WM8995_WSEQ_DATA_START9_WIDTH 4 /* WSEQ_DATA_START9 - [3:0] */
4577
4578/*
4579 * R12327 (0x3027) - Write Sequencer 39
4580 */
4581#define WM8995_WSEQ_EOS9 0x0100 /* WSEQ_EOS9 */
4582#define WM8995_WSEQ_EOS9_MASK 0x0100 /* WSEQ_EOS9 */
4583#define WM8995_WSEQ_EOS9_SHIFT 8 /* WSEQ_EOS9 */
4584#define WM8995_WSEQ_EOS9_WIDTH 1 /* WSEQ_EOS9 */
4585#define WM8995_WSEQ_DELAY9_MASK 0x000F /* WSEQ_DELAY9 - [3:0] */
4586#define WM8995_WSEQ_DELAY9_SHIFT 0 /* WSEQ_DELAY9 - [3:0] */
4587#define WM8995_WSEQ_DELAY9_WIDTH 4 /* WSEQ_DELAY9 - [3:0] */
4588
4589/*
4590 * R12328 (0x3028) - Write Sequencer 40
4591 */
4592#define WM8995_WSEQ_ADDR10_MASK 0x3FFF /* WSEQ_ADDR10 - [13:0] */
4593#define WM8995_WSEQ_ADDR10_SHIFT 0 /* WSEQ_ADDR10 - [13:0] */
4594#define WM8995_WSEQ_ADDR10_WIDTH 14 /* WSEQ_ADDR10 - [13:0] */
4595
4596/*
4597 * R12329 (0x3029) - Write Sequencer 41
4598 */
4599#define WM8995_WSEQ_DATA10_MASK 0x00FF /* WSEQ_DATA10 - [7:0] */
4600#define WM8995_WSEQ_DATA10_SHIFT 0 /* WSEQ_DATA10 - [7:0] */
4601#define WM8995_WSEQ_DATA10_WIDTH 8 /* WSEQ_DATA10 - [7:0] */
4602
4603/*
4604 * R12330 (0x302A) - Write Sequencer 42
4605 */
4606#define WM8995_WSEQ_DATA_WIDTH10_MASK 0x0700 /* WSEQ_DATA_WIDTH10 - [10:8] */
4607#define WM8995_WSEQ_DATA_WIDTH10_SHIFT 8 /* WSEQ_DATA_WIDTH10 - [10:8] */
4608#define WM8995_WSEQ_DATA_WIDTH10_WIDTH 3 /* WSEQ_DATA_WIDTH10 - [10:8] */
4609#define WM8995_WSEQ_DATA_START10_MASK 0x000F /* WSEQ_DATA_START10 - [3:0] */
4610#define WM8995_WSEQ_DATA_START10_SHIFT 0 /* WSEQ_DATA_START10 - [3:0] */
4611#define WM8995_WSEQ_DATA_START10_WIDTH 4 /* WSEQ_DATA_START10 - [3:0] */
4612
4613/*
4614 * R12331 (0x302B) - Write Sequencer 43
4615 */
4616#define WM8995_WSEQ_EOS10 0x0100 /* WSEQ_EOS10 */
4617#define WM8995_WSEQ_EOS10_MASK 0x0100 /* WSEQ_EOS10 */
4618#define WM8995_WSEQ_EOS10_SHIFT 8 /* WSEQ_EOS10 */
4619#define WM8995_WSEQ_EOS10_WIDTH 1 /* WSEQ_EOS10 */
4620#define WM8995_WSEQ_DELAY10_MASK 0x000F /* WSEQ_DELAY10 - [3:0] */
4621#define WM8995_WSEQ_DELAY10_SHIFT 0 /* WSEQ_DELAY10 - [3:0] */
4622#define WM8995_WSEQ_DELAY10_WIDTH 4 /* WSEQ_DELAY10 - [3:0] */
4623
4624/*
4625 * R12332 (0x302C) - Write Sequencer 44
4626 */
4627#define WM8995_WSEQ_ADDR11_MASK 0x3FFF /* WSEQ_ADDR11 - [13:0] */
4628#define WM8995_WSEQ_ADDR11_SHIFT 0 /* WSEQ_ADDR11 - [13:0] */
4629#define WM8995_WSEQ_ADDR11_WIDTH 14 /* WSEQ_ADDR11 - [13:0] */
4630
4631/*
4632 * R12333 (0x302D) - Write Sequencer 45
4633 */
4634#define WM8995_WSEQ_DATA11_MASK 0x00FF /* WSEQ_DATA11 - [7:0] */
4635#define WM8995_WSEQ_DATA11_SHIFT 0 /* WSEQ_DATA11 - [7:0] */
4636#define WM8995_WSEQ_DATA11_WIDTH 8 /* WSEQ_DATA11 - [7:0] */
4637
4638/*
4639 * R12334 (0x302E) - Write Sequencer 46
4640 */
4641#define WM8995_WSEQ_DATA_WIDTH11_MASK 0x0700 /* WSEQ_DATA_WIDTH11 - [10:8] */
4642#define WM8995_WSEQ_DATA_WIDTH11_SHIFT 8 /* WSEQ_DATA_WIDTH11 - [10:8] */
4643#define WM8995_WSEQ_DATA_WIDTH11_WIDTH 3 /* WSEQ_DATA_WIDTH11 - [10:8] */
4644#define WM8995_WSEQ_DATA_START11_MASK 0x000F /* WSEQ_DATA_START11 - [3:0] */
4645#define WM8995_WSEQ_DATA_START11_SHIFT 0 /* WSEQ_DATA_START11 - [3:0] */
4646#define WM8995_WSEQ_DATA_START11_WIDTH 4 /* WSEQ_DATA_START11 - [3:0] */
4647
4648/*
4649 * R12335 (0x302F) - Write Sequencer 47
4650 */
4651#define WM8995_WSEQ_EOS11 0x0100 /* WSEQ_EOS11 */
4652#define WM8995_WSEQ_EOS11_MASK 0x0100 /* WSEQ_EOS11 */
4653#define WM8995_WSEQ_EOS11_SHIFT 8 /* WSEQ_EOS11 */
4654#define WM8995_WSEQ_EOS11_WIDTH 1 /* WSEQ_EOS11 */
4655#define WM8995_WSEQ_DELAY11_MASK 0x000F /* WSEQ_DELAY11 - [3:0] */
4656#define WM8995_WSEQ_DELAY11_SHIFT 0 /* WSEQ_DELAY11 - [3:0] */
4657#define WM8995_WSEQ_DELAY11_WIDTH 4 /* WSEQ_DELAY11 - [3:0] */
4658
4659/*
4660 * R12336 (0x3030) - Write Sequencer 48
4661 */
4662#define WM8995_WSEQ_ADDR12_MASK 0x3FFF /* WSEQ_ADDR12 - [13:0] */
4663#define WM8995_WSEQ_ADDR12_SHIFT 0 /* WSEQ_ADDR12 - [13:0] */
4664#define WM8995_WSEQ_ADDR12_WIDTH 14 /* WSEQ_ADDR12 - [13:0] */
4665
4666/*
4667 * R12337 (0x3031) - Write Sequencer 49
4668 */
4669#define WM8995_WSEQ_DATA12_MASK 0x00FF /* WSEQ_DATA12 - [7:0] */
4670#define WM8995_WSEQ_DATA12_SHIFT 0 /* WSEQ_DATA12 - [7:0] */
4671#define WM8995_WSEQ_DATA12_WIDTH 8 /* WSEQ_DATA12 - [7:0] */
4672
4673/*
4674 * R12338 (0x3032) - Write Sequencer 50
4675 */
4676#define WM8995_WSEQ_DATA_WIDTH12_MASK 0x0700 /* WSEQ_DATA_WIDTH12 - [10:8] */
4677#define WM8995_WSEQ_DATA_WIDTH12_SHIFT 8 /* WSEQ_DATA_WIDTH12 - [10:8] */
4678#define WM8995_WSEQ_DATA_WIDTH12_WIDTH 3 /* WSEQ_DATA_WIDTH12 - [10:8] */
4679#define WM8995_WSEQ_DATA_START12_MASK 0x000F /* WSEQ_DATA_START12 - [3:0] */
4680#define WM8995_WSEQ_DATA_START12_SHIFT 0 /* WSEQ_DATA_START12 - [3:0] */
4681#define WM8995_WSEQ_DATA_START12_WIDTH 4 /* WSEQ_DATA_START12 - [3:0] */
4682
4683/*
4684 * R12339 (0x3033) - Write Sequencer 51
4685 */
4686#define WM8995_WSEQ_EOS12 0x0100 /* WSEQ_EOS12 */
4687#define WM8995_WSEQ_EOS12_MASK 0x0100 /* WSEQ_EOS12 */
4688#define WM8995_WSEQ_EOS12_SHIFT 8 /* WSEQ_EOS12 */
4689#define WM8995_WSEQ_EOS12_WIDTH 1 /* WSEQ_EOS12 */
4690#define WM8995_WSEQ_DELAY12_MASK 0x000F /* WSEQ_DELAY12 - [3:0] */
4691#define WM8995_WSEQ_DELAY12_SHIFT 0 /* WSEQ_DELAY12 - [3:0] */
4692#define WM8995_WSEQ_DELAY12_WIDTH 4 /* WSEQ_DELAY12 - [3:0] */
4693
4694/*
4695 * R12340 (0x3034) - Write Sequencer 52
4696 */
4697#define WM8995_WSEQ_ADDR13_MASK 0x3FFF /* WSEQ_ADDR13 - [13:0] */
4698#define WM8995_WSEQ_ADDR13_SHIFT 0 /* WSEQ_ADDR13 - [13:0] */
4699#define WM8995_WSEQ_ADDR13_WIDTH 14 /* WSEQ_ADDR13 - [13:0] */
4700
4701/*
4702 * R12341 (0x3035) - Write Sequencer 53
4703 */
4704#define WM8995_WSEQ_DATA13_MASK 0x00FF /* WSEQ_DATA13 - [7:0] */
4705#define WM8995_WSEQ_DATA13_SHIFT 0 /* WSEQ_DATA13 - [7:0] */
4706#define WM8995_WSEQ_DATA13_WIDTH 8 /* WSEQ_DATA13 - [7:0] */
4707
4708/*
4709 * R12342 (0x3036) - Write Sequencer 54
4710 */
4711#define WM8995_WSEQ_DATA_WIDTH13_MASK 0x0700 /* WSEQ_DATA_WIDTH13 - [10:8] */
4712#define WM8995_WSEQ_DATA_WIDTH13_SHIFT 8 /* WSEQ_DATA_WIDTH13 - [10:8] */
4713#define WM8995_WSEQ_DATA_WIDTH13_WIDTH 3 /* WSEQ_DATA_WIDTH13 - [10:8] */
4714#define WM8995_WSEQ_DATA_START13_MASK 0x000F /* WSEQ_DATA_START13 - [3:0] */
4715#define WM8995_WSEQ_DATA_START13_SHIFT 0 /* WSEQ_DATA_START13 - [3:0] */
4716#define WM8995_WSEQ_DATA_START13_WIDTH 4 /* WSEQ_DATA_START13 - [3:0] */
4717
4718/*
4719 * R12343 (0x3037) - Write Sequencer 55
4720 */
4721#define WM8995_WSEQ_EOS13 0x0100 /* WSEQ_EOS13 */
4722#define WM8995_WSEQ_EOS13_MASK 0x0100 /* WSEQ_EOS13 */
4723#define WM8995_WSEQ_EOS13_SHIFT 8 /* WSEQ_EOS13 */
4724#define WM8995_WSEQ_EOS13_WIDTH 1 /* WSEQ_EOS13 */
4725#define WM8995_WSEQ_DELAY13_MASK 0x000F /* WSEQ_DELAY13 - [3:0] */
4726#define WM8995_WSEQ_DELAY13_SHIFT 0 /* WSEQ_DELAY13 - [3:0] */
4727#define WM8995_WSEQ_DELAY13_WIDTH 4 /* WSEQ_DELAY13 - [3:0] */
4728
4729/*
4730 * R12344 (0x3038) - Write Sequencer 56
4731 */
4732#define WM8995_WSEQ_ADDR14_MASK 0x3FFF /* WSEQ_ADDR14 - [13:0] */
4733#define WM8995_WSEQ_ADDR14_SHIFT 0 /* WSEQ_ADDR14 - [13:0] */
4734#define WM8995_WSEQ_ADDR14_WIDTH 14 /* WSEQ_ADDR14 - [13:0] */
4735
4736/*
4737 * R12345 (0x3039) - Write Sequencer 57
4738 */
4739#define WM8995_WSEQ_DATA14_MASK 0x00FF /* WSEQ_DATA14 - [7:0] */
4740#define WM8995_WSEQ_DATA14_SHIFT 0 /* WSEQ_DATA14 - [7:0] */
4741#define WM8995_WSEQ_DATA14_WIDTH 8 /* WSEQ_DATA14 - [7:0] */
4742
4743/*
4744 * R12346 (0x303A) - Write Sequencer 58
4745 */
4746#define WM8995_WSEQ_DATA_WIDTH14_MASK 0x0700 /* WSEQ_DATA_WIDTH14 - [10:8] */
4747#define WM8995_WSEQ_DATA_WIDTH14_SHIFT 8 /* WSEQ_DATA_WIDTH14 - [10:8] */
4748#define WM8995_WSEQ_DATA_WIDTH14_WIDTH 3 /* WSEQ_DATA_WIDTH14 - [10:8] */
4749#define WM8995_WSEQ_DATA_START14_MASK 0x000F /* WSEQ_DATA_START14 - [3:0] */
4750#define WM8995_WSEQ_DATA_START14_SHIFT 0 /* WSEQ_DATA_START14 - [3:0] */
4751#define WM8995_WSEQ_DATA_START14_WIDTH 4 /* WSEQ_DATA_START14 - [3:0] */
4752
4753/*
4754 * R12347 (0x303B) - Write Sequencer 59
4755 */
4756#define WM8995_WSEQ_EOS14 0x0100 /* WSEQ_EOS14 */
4757#define WM8995_WSEQ_EOS14_MASK 0x0100 /* WSEQ_EOS14 */
4758#define WM8995_WSEQ_EOS14_SHIFT 8 /* WSEQ_EOS14 */
4759#define WM8995_WSEQ_EOS14_WIDTH 1 /* WSEQ_EOS14 */
4760#define WM8995_WSEQ_DELAY14_MASK 0x000F /* WSEQ_DELAY14 - [3:0] */
4761#define WM8995_WSEQ_DELAY14_SHIFT 0 /* WSEQ_DELAY14 - [3:0] */
4762#define WM8995_WSEQ_DELAY14_WIDTH 4 /* WSEQ_DELAY14 - [3:0] */
4763
4764/*
4765 * R12348 (0x303C) - Write Sequencer 60
4766 */
4767#define WM8995_WSEQ_ADDR15_MASK 0x3FFF /* WSEQ_ADDR15 - [13:0] */
4768#define WM8995_WSEQ_ADDR15_SHIFT 0 /* WSEQ_ADDR15 - [13:0] */
4769#define WM8995_WSEQ_ADDR15_WIDTH 14 /* WSEQ_ADDR15 - [13:0] */
4770
4771/*
4772 * R12349 (0x303D) - Write Sequencer 61
4773 */
4774#define WM8995_WSEQ_DATA15_MASK 0x00FF /* WSEQ_DATA15 - [7:0] */
4775#define WM8995_WSEQ_DATA15_SHIFT 0 /* WSEQ_DATA15 - [7:0] */
4776#define WM8995_WSEQ_DATA15_WIDTH 8 /* WSEQ_DATA15 - [7:0] */
4777
4778/*
4779 * R12350 (0x303E) - Write Sequencer 62
4780 */
4781#define WM8995_WSEQ_DATA_WIDTH15_MASK 0x0700 /* WSEQ_DATA_WIDTH15 - [10:8] */
4782#define WM8995_WSEQ_DATA_WIDTH15_SHIFT 8 /* WSEQ_DATA_WIDTH15 - [10:8] */
4783#define WM8995_WSEQ_DATA_WIDTH15_WIDTH 3 /* WSEQ_DATA_WIDTH15 - [10:8] */
4784#define WM8995_WSEQ_DATA_START15_MASK 0x000F /* WSEQ_DATA_START15 - [3:0] */
4785#define WM8995_WSEQ_DATA_START15_SHIFT 0 /* WSEQ_DATA_START15 - [3:0] */
4786#define WM8995_WSEQ_DATA_START15_WIDTH 4 /* WSEQ_DATA_START15 - [3:0] */
4787
4788/*
4789 * R12351 (0x303F) - Write Sequencer 63
4790 */
4791#define WM8995_WSEQ_EOS15 0x0100 /* WSEQ_EOS15 */
4792#define WM8995_WSEQ_EOS15_MASK 0x0100 /* WSEQ_EOS15 */
4793#define WM8995_WSEQ_EOS15_SHIFT 8 /* WSEQ_EOS15 */
4794#define WM8995_WSEQ_EOS15_WIDTH 1 /* WSEQ_EOS15 */
4795#define WM8995_WSEQ_DELAY15_MASK 0x000F /* WSEQ_DELAY15 - [3:0] */
4796#define WM8995_WSEQ_DELAY15_SHIFT 0 /* WSEQ_DELAY15 - [3:0] */
4797#define WM8995_WSEQ_DELAY15_WIDTH 4 /* WSEQ_DELAY15 - [3:0] */
4798
4799/*
4800 * R12352 (0x3040) - Write Sequencer 64
4801 */
4802#define WM8995_WSEQ_ADDR16_MASK 0x3FFF /* WSEQ_ADDR16 - [13:0] */
4803#define WM8995_WSEQ_ADDR16_SHIFT 0 /* WSEQ_ADDR16 - [13:0] */
4804#define WM8995_WSEQ_ADDR16_WIDTH 14 /* WSEQ_ADDR16 - [13:0] */
4805
4806/*
4807 * R12353 (0x3041) - Write Sequencer 65
4808 */
4809#define WM8995_WSEQ_DATA16_MASK 0x00FF /* WSEQ_DATA16 - [7:0] */
4810#define WM8995_WSEQ_DATA16_SHIFT 0 /* WSEQ_DATA16 - [7:0] */
4811#define WM8995_WSEQ_DATA16_WIDTH 8 /* WSEQ_DATA16 - [7:0] */
4812
4813/*
4814 * R12354 (0x3042) - Write Sequencer 66
4815 */
4816#define WM8995_WSEQ_DATA_WIDTH16_MASK 0x0700 /* WSEQ_DATA_WIDTH16 - [10:8] */
4817#define WM8995_WSEQ_DATA_WIDTH16_SHIFT 8 /* WSEQ_DATA_WIDTH16 - [10:8] */
4818#define WM8995_WSEQ_DATA_WIDTH16_WIDTH 3 /* WSEQ_DATA_WIDTH16 - [10:8] */
4819#define WM8995_WSEQ_DATA_START16_MASK 0x000F /* WSEQ_DATA_START16 - [3:0] */
4820#define WM8995_WSEQ_DATA_START16_SHIFT 0 /* WSEQ_DATA_START16 - [3:0] */
4821#define WM8995_WSEQ_DATA_START16_WIDTH 4 /* WSEQ_DATA_START16 - [3:0] */
4822
4823/*
4824 * R12355 (0x3043) - Write Sequencer 67
4825 */
4826#define WM8995_WSEQ_EOS16 0x0100 /* WSEQ_EOS16 */
4827#define WM8995_WSEQ_EOS16_MASK 0x0100 /* WSEQ_EOS16 */
4828#define WM8995_WSEQ_EOS16_SHIFT 8 /* WSEQ_EOS16 */
4829#define WM8995_WSEQ_EOS16_WIDTH 1 /* WSEQ_EOS16 */
4830#define WM8995_WSEQ_DELAY16_MASK 0x000F /* WSEQ_DELAY16 - [3:0] */
4831#define WM8995_WSEQ_DELAY16_SHIFT 0 /* WSEQ_DELAY16 - [3:0] */
4832#define WM8995_WSEQ_DELAY16_WIDTH 4 /* WSEQ_DELAY16 - [3:0] */
4833
4834/*
4835 * R12356 (0x3044) - Write Sequencer 68
4836 */
4837#define WM8995_WSEQ_ADDR17_MASK 0x3FFF /* WSEQ_ADDR17 - [13:0] */
4838#define WM8995_WSEQ_ADDR17_SHIFT 0 /* WSEQ_ADDR17 - [13:0] */
4839#define WM8995_WSEQ_ADDR17_WIDTH 14 /* WSEQ_ADDR17 - [13:0] */
4840
4841/*
4842 * R12357 (0x3045) - Write Sequencer 69
4843 */
4844#define WM8995_WSEQ_DATA17_MASK 0x00FF /* WSEQ_DATA17 - [7:0] */
4845#define WM8995_WSEQ_DATA17_SHIFT 0 /* WSEQ_DATA17 - [7:0] */
4846#define WM8995_WSEQ_DATA17_WIDTH 8 /* WSEQ_DATA17 - [7:0] */
4847
4848/*
4849 * R12358 (0x3046) - Write Sequencer 70
4850 */
4851#define WM8995_WSEQ_DATA_WIDTH17_MASK 0x0700 /* WSEQ_DATA_WIDTH17 - [10:8] */
4852#define WM8995_WSEQ_DATA_WIDTH17_SHIFT 8 /* WSEQ_DATA_WIDTH17 - [10:8] */
4853#define WM8995_WSEQ_DATA_WIDTH17_WIDTH 3 /* WSEQ_DATA_WIDTH17 - [10:8] */
4854#define WM8995_WSEQ_DATA_START17_MASK 0x000F /* WSEQ_DATA_START17 - [3:0] */
4855#define WM8995_WSEQ_DATA_START17_SHIFT 0 /* WSEQ_DATA_START17 - [3:0] */
4856#define WM8995_WSEQ_DATA_START17_WIDTH 4 /* WSEQ_DATA_START17 - [3:0] */
4857
4858/*
4859 * R12359 (0x3047) - Write Sequencer 71
4860 */
4861#define WM8995_WSEQ_EOS17 0x0100 /* WSEQ_EOS17 */
4862#define WM8995_WSEQ_EOS17_MASK 0x0100 /* WSEQ_EOS17 */
4863#define WM8995_WSEQ_EOS17_SHIFT 8 /* WSEQ_EOS17 */
4864#define WM8995_WSEQ_EOS17_WIDTH 1 /* WSEQ_EOS17 */
4865#define WM8995_WSEQ_DELAY17_MASK 0x000F /* WSEQ_DELAY17 - [3:0] */
4866#define WM8995_WSEQ_DELAY17_SHIFT 0 /* WSEQ_DELAY17 - [3:0] */
4867#define WM8995_WSEQ_DELAY17_WIDTH 4 /* WSEQ_DELAY17 - [3:0] */
4868
4869/*
4870 * R12360 (0x3048) - Write Sequencer 72
4871 */
4872#define WM8995_WSEQ_ADDR18_MASK 0x3FFF /* WSEQ_ADDR18 - [13:0] */
4873#define WM8995_WSEQ_ADDR18_SHIFT 0 /* WSEQ_ADDR18 - [13:0] */
4874#define WM8995_WSEQ_ADDR18_WIDTH 14 /* WSEQ_ADDR18 - [13:0] */
4875
4876/*
4877 * R12361 (0x3049) - Write Sequencer 73
4878 */
4879#define WM8995_WSEQ_DATA18_MASK 0x00FF /* WSEQ_DATA18 - [7:0] */
4880#define WM8995_WSEQ_DATA18_SHIFT 0 /* WSEQ_DATA18 - [7:0] */
4881#define WM8995_WSEQ_DATA18_WIDTH 8 /* WSEQ_DATA18 - [7:0] */
4882
4883/*
4884 * R12362 (0x304A) - Write Sequencer 74
4885 */
4886#define WM8995_WSEQ_DATA_WIDTH18_MASK 0x0700 /* WSEQ_DATA_WIDTH18 - [10:8] */
4887#define WM8995_WSEQ_DATA_WIDTH18_SHIFT 8 /* WSEQ_DATA_WIDTH18 - [10:8] */
4888#define WM8995_WSEQ_DATA_WIDTH18_WIDTH 3 /* WSEQ_DATA_WIDTH18 - [10:8] */
4889#define WM8995_WSEQ_DATA_START18_MASK 0x000F /* WSEQ_DATA_START18 - [3:0] */
4890#define WM8995_WSEQ_DATA_START18_SHIFT 0 /* WSEQ_DATA_START18 - [3:0] */
4891#define WM8995_WSEQ_DATA_START18_WIDTH 4 /* WSEQ_DATA_START18 - [3:0] */
4892
4893/*
4894 * R12363 (0x304B) - Write Sequencer 75
4895 */
4896#define WM8995_WSEQ_EOS18 0x0100 /* WSEQ_EOS18 */
4897#define WM8995_WSEQ_EOS18_MASK 0x0100 /* WSEQ_EOS18 */
4898#define WM8995_WSEQ_EOS18_SHIFT 8 /* WSEQ_EOS18 */
4899#define WM8995_WSEQ_EOS18_WIDTH 1 /* WSEQ_EOS18 */
4900#define WM8995_WSEQ_DELAY18_MASK 0x000F /* WSEQ_DELAY18 - [3:0] */
4901#define WM8995_WSEQ_DELAY18_SHIFT 0 /* WSEQ_DELAY18 - [3:0] */
4902#define WM8995_WSEQ_DELAY18_WIDTH 4 /* WSEQ_DELAY18 - [3:0] */
4903
4904/*
4905 * R12364 (0x304C) - Write Sequencer 76
4906 */
4907#define WM8995_WSEQ_ADDR19_MASK 0x3FFF /* WSEQ_ADDR19 - [13:0] */
4908#define WM8995_WSEQ_ADDR19_SHIFT 0 /* WSEQ_ADDR19 - [13:0] */
4909#define WM8995_WSEQ_ADDR19_WIDTH 14 /* WSEQ_ADDR19 - [13:0] */
4910
4911/*
4912 * R12365 (0x304D) - Write Sequencer 77
4913 */
4914#define WM8995_WSEQ_DATA19_MASK 0x00FF /* WSEQ_DATA19 - [7:0] */
4915#define WM8995_WSEQ_DATA19_SHIFT 0 /* WSEQ_DATA19 - [7:0] */
4916#define WM8995_WSEQ_DATA19_WIDTH 8 /* WSEQ_DATA19 - [7:0] */
4917
4918/*
4919 * R12366 (0x304E) - Write Sequencer 78
4920 */
4921#define WM8995_WSEQ_DATA_WIDTH19_MASK 0x0700 /* WSEQ_DATA_WIDTH19 - [10:8] */
4922#define WM8995_WSEQ_DATA_WIDTH19_SHIFT 8 /* WSEQ_DATA_WIDTH19 - [10:8] */
4923#define WM8995_WSEQ_DATA_WIDTH19_WIDTH 3 /* WSEQ_DATA_WIDTH19 - [10:8] */
4924#define WM8995_WSEQ_DATA_START19_MASK 0x000F /* WSEQ_DATA_START19 - [3:0] */
4925#define WM8995_WSEQ_DATA_START19_SHIFT 0 /* WSEQ_DATA_START19 - [3:0] */
4926#define WM8995_WSEQ_DATA_START19_WIDTH 4 /* WSEQ_DATA_START19 - [3:0] */
4927
4928/*
4929 * R12367 (0x304F) - Write Sequencer 79
4930 */
4931#define WM8995_WSEQ_EOS19 0x0100 /* WSEQ_EOS19 */
4932#define WM8995_WSEQ_EOS19_MASK 0x0100 /* WSEQ_EOS19 */
4933#define WM8995_WSEQ_EOS19_SHIFT 8 /* WSEQ_EOS19 */
4934#define WM8995_WSEQ_EOS19_WIDTH 1 /* WSEQ_EOS19 */
4935#define WM8995_WSEQ_DELAY19_MASK 0x000F /* WSEQ_DELAY19 - [3:0] */
4936#define WM8995_WSEQ_DELAY19_SHIFT 0 /* WSEQ_DELAY19 - [3:0] */
4937#define WM8995_WSEQ_DELAY19_WIDTH 4 /* WSEQ_DELAY19 - [3:0] */
4938
4939/*
4940 * R12368 (0x3050) - Write Sequencer 80
4941 */
4942#define WM8995_WSEQ_ADDR20_MASK 0x3FFF /* WSEQ_ADDR20 - [13:0] */
4943#define WM8995_WSEQ_ADDR20_SHIFT 0 /* WSEQ_ADDR20 - [13:0] */
4944#define WM8995_WSEQ_ADDR20_WIDTH 14 /* WSEQ_ADDR20 - [13:0] */
4945
4946/*
4947 * R12369 (0x3051) - Write Sequencer 81
4948 */
4949#define WM8995_WSEQ_DATA20_MASK 0x00FF /* WSEQ_DATA20 - [7:0] */
4950#define WM8995_WSEQ_DATA20_SHIFT 0 /* WSEQ_DATA20 - [7:0] */
4951#define WM8995_WSEQ_DATA20_WIDTH 8 /* WSEQ_DATA20 - [7:0] */
4952
4953/*
4954 * R12370 (0x3052) - Write Sequencer 82
4955 */
4956#define WM8995_WSEQ_DATA_WIDTH20_MASK 0x0700 /* WSEQ_DATA_WIDTH20 - [10:8] */
4957#define WM8995_WSEQ_DATA_WIDTH20_SHIFT 8 /* WSEQ_DATA_WIDTH20 - [10:8] */
4958#define WM8995_WSEQ_DATA_WIDTH20_WIDTH 3 /* WSEQ_DATA_WIDTH20 - [10:8] */
4959#define WM8995_WSEQ_DATA_START20_MASK 0x000F /* WSEQ_DATA_START20 - [3:0] */
4960#define WM8995_WSEQ_DATA_START20_SHIFT 0 /* WSEQ_DATA_START20 - [3:0] */
4961#define WM8995_WSEQ_DATA_START20_WIDTH 4 /* WSEQ_DATA_START20 - [3:0] */
4962
4963/*
4964 * R12371 (0x3053) - Write Sequencer 83
4965 */
4966#define WM8995_WSEQ_EOS20 0x0100 /* WSEQ_EOS20 */
4967#define WM8995_WSEQ_EOS20_MASK 0x0100 /* WSEQ_EOS20 */
4968#define WM8995_WSEQ_EOS20_SHIFT 8 /* WSEQ_EOS20 */
4969#define WM8995_WSEQ_EOS20_WIDTH 1 /* WSEQ_EOS20 */
4970#define WM8995_WSEQ_DELAY20_MASK 0x000F /* WSEQ_DELAY20 - [3:0] */
4971#define WM8995_WSEQ_DELAY20_SHIFT 0 /* WSEQ_DELAY20 - [3:0] */
4972#define WM8995_WSEQ_DELAY20_WIDTH 4 /* WSEQ_DELAY20 - [3:0] */
4973
4974/*
4975 * R12372 (0x3054) - Write Sequencer 84
4976 */
4977#define WM8995_WSEQ_ADDR21_MASK 0x3FFF /* WSEQ_ADDR21 - [13:0] */
4978#define WM8995_WSEQ_ADDR21_SHIFT 0 /* WSEQ_ADDR21 - [13:0] */
4979#define WM8995_WSEQ_ADDR21_WIDTH 14 /* WSEQ_ADDR21 - [13:0] */
4980
4981/*
4982 * R12373 (0x3055) - Write Sequencer 85
4983 */
4984#define WM8995_WSEQ_DATA21_MASK 0x00FF /* WSEQ_DATA21 - [7:0] */
4985#define WM8995_WSEQ_DATA21_SHIFT 0 /* WSEQ_DATA21 - [7:0] */
4986#define WM8995_WSEQ_DATA21_WIDTH 8 /* WSEQ_DATA21 - [7:0] */
4987
4988/*
4989 * R12374 (0x3056) - Write Sequencer 86
4990 */
4991#define WM8995_WSEQ_DATA_WIDTH21_MASK 0x0700 /* WSEQ_DATA_WIDTH21 - [10:8] */
4992#define WM8995_WSEQ_DATA_WIDTH21_SHIFT 8 /* WSEQ_DATA_WIDTH21 - [10:8] */
4993#define WM8995_WSEQ_DATA_WIDTH21_WIDTH 3 /* WSEQ_DATA_WIDTH21 - [10:8] */
4994#define WM8995_WSEQ_DATA_START21_MASK 0x000F /* WSEQ_DATA_START21 - [3:0] */
4995#define WM8995_WSEQ_DATA_START21_SHIFT 0 /* WSEQ_DATA_START21 - [3:0] */
4996#define WM8995_WSEQ_DATA_START21_WIDTH 4 /* WSEQ_DATA_START21 - [3:0] */
4997
4998/*
4999 * R12375 (0x3057) - Write Sequencer 87
5000 */
5001#define WM8995_WSEQ_EOS21 0x0100 /* WSEQ_EOS21 */
5002#define WM8995_WSEQ_EOS21_MASK 0x0100 /* WSEQ_EOS21 */
5003#define WM8995_WSEQ_EOS21_SHIFT 8 /* WSEQ_EOS21 */
5004#define WM8995_WSEQ_EOS21_WIDTH 1 /* WSEQ_EOS21 */
5005#define WM8995_WSEQ_DELAY21_MASK 0x000F /* WSEQ_DELAY21 - [3:0] */
5006#define WM8995_WSEQ_DELAY21_SHIFT 0 /* WSEQ_DELAY21 - [3:0] */
5007#define WM8995_WSEQ_DELAY21_WIDTH 4 /* WSEQ_DELAY21 - [3:0] */
5008
5009/*
5010 * R12376 (0x3058) - Write Sequencer 88
5011 */
5012#define WM8995_WSEQ_ADDR22_MASK 0x3FFF /* WSEQ_ADDR22 - [13:0] */
5013#define WM8995_WSEQ_ADDR22_SHIFT 0 /* WSEQ_ADDR22 - [13:0] */
5014#define WM8995_WSEQ_ADDR22_WIDTH 14 /* WSEQ_ADDR22 - [13:0] */
5015
5016/*
5017 * R12377 (0x3059) - Write Sequencer 89
5018 */
5019#define WM8995_WSEQ_DATA22_MASK 0x00FF /* WSEQ_DATA22 - [7:0] */
5020#define WM8995_WSEQ_DATA22_SHIFT 0 /* WSEQ_DATA22 - [7:0] */
5021#define WM8995_WSEQ_DATA22_WIDTH 8 /* WSEQ_DATA22 - [7:0] */
5022
5023/*
5024 * R12378 (0x305A) - Write Sequencer 90
5025 */
5026#define WM8995_WSEQ_DATA_WIDTH22_MASK 0x0700 /* WSEQ_DATA_WIDTH22 - [10:8] */
5027#define WM8995_WSEQ_DATA_WIDTH22_SHIFT 8 /* WSEQ_DATA_WIDTH22 - [10:8] */
5028#define WM8995_WSEQ_DATA_WIDTH22_WIDTH 3 /* WSEQ_DATA_WIDTH22 - [10:8] */
5029#define WM8995_WSEQ_DATA_START22_MASK 0x000F /* WSEQ_DATA_START22 - [3:0] */
5030#define WM8995_WSEQ_DATA_START22_SHIFT 0 /* WSEQ_DATA_START22 - [3:0] */
5031#define WM8995_WSEQ_DATA_START22_WIDTH 4 /* WSEQ_DATA_START22 - [3:0] */
5032
5033/*
5034 * R12379 (0x305B) - Write Sequencer 91
5035 */
5036#define WM8995_WSEQ_EOS22 0x0100 /* WSEQ_EOS22 */
5037#define WM8995_WSEQ_EOS22_MASK 0x0100 /* WSEQ_EOS22 */
5038#define WM8995_WSEQ_EOS22_SHIFT 8 /* WSEQ_EOS22 */
5039#define WM8995_WSEQ_EOS22_WIDTH 1 /* WSEQ_EOS22 */
5040#define WM8995_WSEQ_DELAY22_MASK 0x000F /* WSEQ_DELAY22 - [3:0] */
5041#define WM8995_WSEQ_DELAY22_SHIFT 0 /* WSEQ_DELAY22 - [3:0] */
5042#define WM8995_WSEQ_DELAY22_WIDTH 4 /* WSEQ_DELAY22 - [3:0] */
5043
5044/*
5045 * R12380 (0x305C) - Write Sequencer 92
5046 */
5047#define WM8995_WSEQ_ADDR23_MASK 0x3FFF /* WSEQ_ADDR23 - [13:0] */
5048#define WM8995_WSEQ_ADDR23_SHIFT 0 /* WSEQ_ADDR23 - [13:0] */
5049#define WM8995_WSEQ_ADDR23_WIDTH 14 /* WSEQ_ADDR23 - [13:0] */
5050
5051/*
5052 * R12381 (0x305D) - Write Sequencer 93
5053 */
5054#define WM8995_WSEQ_DATA23_MASK 0x00FF /* WSEQ_DATA23 - [7:0] */
5055#define WM8995_WSEQ_DATA23_SHIFT 0 /* WSEQ_DATA23 - [7:0] */
5056#define WM8995_WSEQ_DATA23_WIDTH 8 /* WSEQ_DATA23 - [7:0] */
5057
5058/*
5059 * R12382 (0x305E) - Write Sequencer 94
5060 */
5061#define WM8995_WSEQ_DATA_WIDTH23_MASK 0x0700 /* WSEQ_DATA_WIDTH23 - [10:8] */
5062#define WM8995_WSEQ_DATA_WIDTH23_SHIFT 8 /* WSEQ_DATA_WIDTH23 - [10:8] */
5063#define WM8995_WSEQ_DATA_WIDTH23_WIDTH 3 /* WSEQ_DATA_WIDTH23 - [10:8] */
5064#define WM8995_WSEQ_DATA_START23_MASK 0x000F /* WSEQ_DATA_START23 - [3:0] */
5065#define WM8995_WSEQ_DATA_START23_SHIFT 0 /* WSEQ_DATA_START23 - [3:0] */
5066#define WM8995_WSEQ_DATA_START23_WIDTH 4 /* WSEQ_DATA_START23 - [3:0] */
5067
5068/*
5069 * R12383 (0x305F) - Write Sequencer 95
5070 */
5071#define WM8995_WSEQ_EOS23 0x0100 /* WSEQ_EOS23 */
5072#define WM8995_WSEQ_EOS23_MASK 0x0100 /* WSEQ_EOS23 */
5073#define WM8995_WSEQ_EOS23_SHIFT 8 /* WSEQ_EOS23 */
5074#define WM8995_WSEQ_EOS23_WIDTH 1 /* WSEQ_EOS23 */
5075#define WM8995_WSEQ_DELAY23_MASK 0x000F /* WSEQ_DELAY23 - [3:0] */
5076#define WM8995_WSEQ_DELAY23_SHIFT 0 /* WSEQ_DELAY23 - [3:0] */
5077#define WM8995_WSEQ_DELAY23_WIDTH 4 /* WSEQ_DELAY23 - [3:0] */
5078
5079/*
5080 * R12384 (0x3060) - Write Sequencer 96
5081 */
5082#define WM8995_WSEQ_ADDR24_MASK 0x3FFF /* WSEQ_ADDR24 - [13:0] */
5083#define WM8995_WSEQ_ADDR24_SHIFT 0 /* WSEQ_ADDR24 - [13:0] */
5084#define WM8995_WSEQ_ADDR24_WIDTH 14 /* WSEQ_ADDR24 - [13:0] */
5085
5086/*
5087 * R12385 (0x3061) - Write Sequencer 97
5088 */
5089#define WM8995_WSEQ_DATA24_MASK 0x00FF /* WSEQ_DATA24 - [7:0] */
5090#define WM8995_WSEQ_DATA24_SHIFT 0 /* WSEQ_DATA24 - [7:0] */
5091#define WM8995_WSEQ_DATA24_WIDTH 8 /* WSEQ_DATA24 - [7:0] */
5092
5093/*
5094 * R12386 (0x3062) - Write Sequencer 98
5095 */
5096#define WM8995_WSEQ_DATA_WIDTH24_MASK 0x0700 /* WSEQ_DATA_WIDTH24 - [10:8] */
5097#define WM8995_WSEQ_DATA_WIDTH24_SHIFT 8 /* WSEQ_DATA_WIDTH24 - [10:8] */
5098#define WM8995_WSEQ_DATA_WIDTH24_WIDTH 3 /* WSEQ_DATA_WIDTH24 - [10:8] */
5099#define WM8995_WSEQ_DATA_START24_MASK 0x000F /* WSEQ_DATA_START24 - [3:0] */
5100#define WM8995_WSEQ_DATA_START24_SHIFT 0 /* WSEQ_DATA_START24 - [3:0] */
5101#define WM8995_WSEQ_DATA_START24_WIDTH 4 /* WSEQ_DATA_START24 - [3:0] */
5102
5103/*
5104 * R12387 (0x3063) - Write Sequencer 99
5105 */
5106#define WM8995_WSEQ_EOS24 0x0100 /* WSEQ_EOS24 */
5107#define WM8995_WSEQ_EOS24_MASK 0x0100 /* WSEQ_EOS24 */
5108#define WM8995_WSEQ_EOS24_SHIFT 8 /* WSEQ_EOS24 */
5109#define WM8995_WSEQ_EOS24_WIDTH 1 /* WSEQ_EOS24 */
5110#define WM8995_WSEQ_DELAY24_MASK 0x000F /* WSEQ_DELAY24 - [3:0] */
5111#define WM8995_WSEQ_DELAY24_SHIFT 0 /* WSEQ_DELAY24 - [3:0] */
5112#define WM8995_WSEQ_DELAY24_WIDTH 4 /* WSEQ_DELAY24 - [3:0] */
5113
5114/*
5115 * R12388 (0x3064) - Write Sequencer 100
5116 */
5117#define WM8995_WSEQ_ADDR25_MASK 0x3FFF /* WSEQ_ADDR25 - [13:0] */
5118#define WM8995_WSEQ_ADDR25_SHIFT 0 /* WSEQ_ADDR25 - [13:0] */
5119#define WM8995_WSEQ_ADDR25_WIDTH 14 /* WSEQ_ADDR25 - [13:0] */
5120
5121/*
5122 * R12389 (0x3065) - Write Sequencer 101
5123 */
5124#define WM8995_WSEQ_DATA25_MASK 0x00FF /* WSEQ_DATA25 - [7:0] */
5125#define WM8995_WSEQ_DATA25_SHIFT 0 /* WSEQ_DATA25 - [7:0] */
5126#define WM8995_WSEQ_DATA25_WIDTH 8 /* WSEQ_DATA25 - [7:0] */
5127
5128/*
5129 * R12390 (0x3066) - Write Sequencer 102
5130 */
5131#define WM8995_WSEQ_DATA_WIDTH25_MASK 0x0700 /* WSEQ_DATA_WIDTH25 - [10:8] */
5132#define WM8995_WSEQ_DATA_WIDTH25_SHIFT 8 /* WSEQ_DATA_WIDTH25 - [10:8] */
5133#define WM8995_WSEQ_DATA_WIDTH25_WIDTH 3 /* WSEQ_DATA_WIDTH25 - [10:8] */
5134#define WM8995_WSEQ_DATA_START25_MASK 0x000F /* WSEQ_DATA_START25 - [3:0] */
5135#define WM8995_WSEQ_DATA_START25_SHIFT 0 /* WSEQ_DATA_START25 - [3:0] */
5136#define WM8995_WSEQ_DATA_START25_WIDTH 4 /* WSEQ_DATA_START25 - [3:0] */
5137
5138/*
5139 * R12391 (0x3067) - Write Sequencer 103
5140 */
5141#define WM8995_WSEQ_EOS25 0x0100 /* WSEQ_EOS25 */
5142#define WM8995_WSEQ_EOS25_MASK 0x0100 /* WSEQ_EOS25 */
5143#define WM8995_WSEQ_EOS25_SHIFT 8 /* WSEQ_EOS25 */
5144#define WM8995_WSEQ_EOS25_WIDTH 1 /* WSEQ_EOS25 */
5145#define WM8995_WSEQ_DELAY25_MASK 0x000F /* WSEQ_DELAY25 - [3:0] */
5146#define WM8995_WSEQ_DELAY25_SHIFT 0 /* WSEQ_DELAY25 - [3:0] */
5147#define WM8995_WSEQ_DELAY25_WIDTH 4 /* WSEQ_DELAY25 - [3:0] */
5148
5149/*
5150 * R12392 (0x3068) - Write Sequencer 104
5151 */
5152#define WM8995_WSEQ_ADDR26_MASK 0x3FFF /* WSEQ_ADDR26 - [13:0] */
5153#define WM8995_WSEQ_ADDR26_SHIFT 0 /* WSEQ_ADDR26 - [13:0] */
5154#define WM8995_WSEQ_ADDR26_WIDTH 14 /* WSEQ_ADDR26 - [13:0] */
5155
5156/*
5157 * R12393 (0x3069) - Write Sequencer 105
5158 */
5159#define WM8995_WSEQ_DATA26_MASK 0x00FF /* WSEQ_DATA26 - [7:0] */
5160#define WM8995_WSEQ_DATA26_SHIFT 0 /* WSEQ_DATA26 - [7:0] */
5161#define WM8995_WSEQ_DATA26_WIDTH 8 /* WSEQ_DATA26 - [7:0] */
5162
5163/*
5164 * R12394 (0x306A) - Write Sequencer 106
5165 */
5166#define WM8995_WSEQ_DATA_WIDTH26_MASK 0x0700 /* WSEQ_DATA_WIDTH26 - [10:8] */
5167#define WM8995_WSEQ_DATA_WIDTH26_SHIFT 8 /* WSEQ_DATA_WIDTH26 - [10:8] */
5168#define WM8995_WSEQ_DATA_WIDTH26_WIDTH 3 /* WSEQ_DATA_WIDTH26 - [10:8] */
5169#define WM8995_WSEQ_DATA_START26_MASK 0x000F /* WSEQ_DATA_START26 - [3:0] */
5170#define WM8995_WSEQ_DATA_START26_SHIFT 0 /* WSEQ_DATA_START26 - [3:0] */
5171#define WM8995_WSEQ_DATA_START26_WIDTH 4 /* WSEQ_DATA_START26 - [3:0] */
5172
5173/*
5174 * R12395 (0x306B) - Write Sequencer 107
5175 */
5176#define WM8995_WSEQ_EOS26 0x0100 /* WSEQ_EOS26 */
5177#define WM8995_WSEQ_EOS26_MASK 0x0100 /* WSEQ_EOS26 */
5178#define WM8995_WSEQ_EOS26_SHIFT 8 /* WSEQ_EOS26 */
5179#define WM8995_WSEQ_EOS26_WIDTH 1 /* WSEQ_EOS26 */
5180#define WM8995_WSEQ_DELAY26_MASK 0x000F /* WSEQ_DELAY26 - [3:0] */
5181#define WM8995_WSEQ_DELAY26_SHIFT 0 /* WSEQ_DELAY26 - [3:0] */
5182#define WM8995_WSEQ_DELAY26_WIDTH 4 /* WSEQ_DELAY26 - [3:0] */
5183
5184/*
5185 * R12396 (0x306C) - Write Sequencer 108
5186 */
5187#define WM8995_WSEQ_ADDR27_MASK 0x3FFF /* WSEQ_ADDR27 - [13:0] */
5188#define WM8995_WSEQ_ADDR27_SHIFT 0 /* WSEQ_ADDR27 - [13:0] */
5189#define WM8995_WSEQ_ADDR27_WIDTH 14 /* WSEQ_ADDR27 - [13:0] */
5190
5191/*
5192 * R12397 (0x306D) - Write Sequencer 109
5193 */
5194#define WM8995_WSEQ_DATA27_MASK 0x00FF /* WSEQ_DATA27 - [7:0] */
5195#define WM8995_WSEQ_DATA27_SHIFT 0 /* WSEQ_DATA27 - [7:0] */
5196#define WM8995_WSEQ_DATA27_WIDTH 8 /* WSEQ_DATA27 - [7:0] */
5197
5198/*
5199 * R12398 (0x306E) - Write Sequencer 110
5200 */
5201#define WM8995_WSEQ_DATA_WIDTH27_MASK 0x0700 /* WSEQ_DATA_WIDTH27 - [10:8] */
5202#define WM8995_WSEQ_DATA_WIDTH27_SHIFT 8 /* WSEQ_DATA_WIDTH27 - [10:8] */
5203#define WM8995_WSEQ_DATA_WIDTH27_WIDTH 3 /* WSEQ_DATA_WIDTH27 - [10:8] */
5204#define WM8995_WSEQ_DATA_START27_MASK 0x000F /* WSEQ_DATA_START27 - [3:0] */
5205#define WM8995_WSEQ_DATA_START27_SHIFT 0 /* WSEQ_DATA_START27 - [3:0] */
5206#define WM8995_WSEQ_DATA_START27_WIDTH 4 /* WSEQ_DATA_START27 - [3:0] */
5207
5208/*
5209 * R12399 (0x306F) - Write Sequencer 111
5210 */
5211#define WM8995_WSEQ_EOS27 0x0100 /* WSEQ_EOS27 */
5212#define WM8995_WSEQ_EOS27_MASK 0x0100 /* WSEQ_EOS27 */
5213#define WM8995_WSEQ_EOS27_SHIFT 8 /* WSEQ_EOS27 */
5214#define WM8995_WSEQ_EOS27_WIDTH 1 /* WSEQ_EOS27 */
5215#define WM8995_WSEQ_DELAY27_MASK 0x000F /* WSEQ_DELAY27 - [3:0] */
5216#define WM8995_WSEQ_DELAY27_SHIFT 0 /* WSEQ_DELAY27 - [3:0] */
5217#define WM8995_WSEQ_DELAY27_WIDTH 4 /* WSEQ_DELAY27 - [3:0] */
5218
5219/*
5220 * R12400 (0x3070) - Write Sequencer 112
5221 */
5222#define WM8995_WSEQ_ADDR28_MASK 0x3FFF /* WSEQ_ADDR28 - [13:0] */
5223#define WM8995_WSEQ_ADDR28_SHIFT 0 /* WSEQ_ADDR28 - [13:0] */
5224#define WM8995_WSEQ_ADDR28_WIDTH 14 /* WSEQ_ADDR28 - [13:0] */
5225
5226/*
5227 * R12401 (0x3071) - Write Sequencer 113
5228 */
5229#define WM8995_WSEQ_DATA28_MASK 0x00FF /* WSEQ_DATA28 - [7:0] */
5230#define WM8995_WSEQ_DATA28_SHIFT 0 /* WSEQ_DATA28 - [7:0] */
5231#define WM8995_WSEQ_DATA28_WIDTH 8 /* WSEQ_DATA28 - [7:0] */
5232
5233/*
5234 * R12402 (0x3072) - Write Sequencer 114
5235 */
5236#define WM8995_WSEQ_DATA_WIDTH28_MASK 0x0700 /* WSEQ_DATA_WIDTH28 - [10:8] */
5237#define WM8995_WSEQ_DATA_WIDTH28_SHIFT 8 /* WSEQ_DATA_WIDTH28 - [10:8] */
5238#define WM8995_WSEQ_DATA_WIDTH28_WIDTH 3 /* WSEQ_DATA_WIDTH28 - [10:8] */
5239#define WM8995_WSEQ_DATA_START28_MASK 0x000F /* WSEQ_DATA_START28 - [3:0] */
5240#define WM8995_WSEQ_DATA_START28_SHIFT 0 /* WSEQ_DATA_START28 - [3:0] */
5241#define WM8995_WSEQ_DATA_START28_WIDTH 4 /* WSEQ_DATA_START28 - [3:0] */
5242
5243/*
5244 * R12403 (0x3073) - Write Sequencer 115
5245 */
5246#define WM8995_WSEQ_EOS28 0x0100 /* WSEQ_EOS28 */
5247#define WM8995_WSEQ_EOS28_MASK 0x0100 /* WSEQ_EOS28 */
5248#define WM8995_WSEQ_EOS28_SHIFT 8 /* WSEQ_EOS28 */
5249#define WM8995_WSEQ_EOS28_WIDTH 1 /* WSEQ_EOS28 */
5250#define WM8995_WSEQ_DELAY28_MASK 0x000F /* WSEQ_DELAY28 - [3:0] */
5251#define WM8995_WSEQ_DELAY28_SHIFT 0 /* WSEQ_DELAY28 - [3:0] */
5252#define WM8995_WSEQ_DELAY28_WIDTH 4 /* WSEQ_DELAY28 - [3:0] */
5253
5254/*
5255 * R12404 (0x3074) - Write Sequencer 116
5256 */
5257#define WM8995_WSEQ_ADDR29_MASK 0x3FFF /* WSEQ_ADDR29 - [13:0] */
5258#define WM8995_WSEQ_ADDR29_SHIFT 0 /* WSEQ_ADDR29 - [13:0] */
5259#define WM8995_WSEQ_ADDR29_WIDTH 14 /* WSEQ_ADDR29 - [13:0] */
5260
5261/*
5262 * R12405 (0x3075) - Write Sequencer 117
5263 */
5264#define WM8995_WSEQ_DATA29_MASK 0x00FF /* WSEQ_DATA29 - [7:0] */
5265#define WM8995_WSEQ_DATA29_SHIFT 0 /* WSEQ_DATA29 - [7:0] */
5266#define WM8995_WSEQ_DATA29_WIDTH 8 /* WSEQ_DATA29 - [7:0] */
5267
5268/*
5269 * R12406 (0x3076) - Write Sequencer 118
5270 */
5271#define WM8995_WSEQ_DATA_WIDTH29_MASK 0x0700 /* WSEQ_DATA_WIDTH29 - [10:8] */
5272#define WM8995_WSEQ_DATA_WIDTH29_SHIFT 8 /* WSEQ_DATA_WIDTH29 - [10:8] */
5273#define WM8995_WSEQ_DATA_WIDTH29_WIDTH 3 /* WSEQ_DATA_WIDTH29 - [10:8] */
5274#define WM8995_WSEQ_DATA_START29_MASK 0x000F /* WSEQ_DATA_START29 - [3:0] */
5275#define WM8995_WSEQ_DATA_START29_SHIFT 0 /* WSEQ_DATA_START29 - [3:0] */
5276#define WM8995_WSEQ_DATA_START29_WIDTH 4 /* WSEQ_DATA_START29 - [3:0] */
5277
5278/*
5279 * R12407 (0x3077) - Write Sequencer 119
5280 */
5281#define WM8995_WSEQ_EOS29 0x0100 /* WSEQ_EOS29 */
5282#define WM8995_WSEQ_EOS29_MASK 0x0100 /* WSEQ_EOS29 */
5283#define WM8995_WSEQ_EOS29_SHIFT 8 /* WSEQ_EOS29 */
5284#define WM8995_WSEQ_EOS29_WIDTH 1 /* WSEQ_EOS29 */
5285#define WM8995_WSEQ_DELAY29_MASK 0x000F /* WSEQ_DELAY29 - [3:0] */
5286#define WM8995_WSEQ_DELAY29_SHIFT 0 /* WSEQ_DELAY29 - [3:0] */
5287#define WM8995_WSEQ_DELAY29_WIDTH 4 /* WSEQ_DELAY29 - [3:0] */
5288
5289/*
5290 * R12408 (0x3078) - Write Sequencer 120
5291 */
5292#define WM8995_WSEQ_ADDR30_MASK 0x3FFF /* WSEQ_ADDR30 - [13:0] */
5293#define WM8995_WSEQ_ADDR30_SHIFT 0 /* WSEQ_ADDR30 - [13:0] */
5294#define WM8995_WSEQ_ADDR30_WIDTH 14 /* WSEQ_ADDR30 - [13:0] */
5295
5296/*
5297 * R12409 (0x3079) - Write Sequencer 121
5298 */
5299#define WM8995_WSEQ_DATA30_MASK 0x00FF /* WSEQ_DATA30 - [7:0] */
5300#define WM8995_WSEQ_DATA30_SHIFT 0 /* WSEQ_DATA30 - [7:0] */
5301#define WM8995_WSEQ_DATA30_WIDTH 8 /* WSEQ_DATA30 - [7:0] */
5302
5303/*
5304 * R12410 (0x307A) - Write Sequencer 122
5305 */
5306#define WM8995_WSEQ_DATA_WIDTH30_MASK 0x0700 /* WSEQ_DATA_WIDTH30 - [10:8] */
5307#define WM8995_WSEQ_DATA_WIDTH30_SHIFT 8 /* WSEQ_DATA_WIDTH30 - [10:8] */
5308#define WM8995_WSEQ_DATA_WIDTH30_WIDTH 3 /* WSEQ_DATA_WIDTH30 - [10:8] */
5309#define WM8995_WSEQ_DATA_START30_MASK 0x000F /* WSEQ_DATA_START30 - [3:0] */
5310#define WM8995_WSEQ_DATA_START30_SHIFT 0 /* WSEQ_DATA_START30 - [3:0] */
5311#define WM8995_WSEQ_DATA_START30_WIDTH 4 /* WSEQ_DATA_START30 - [3:0] */
5312
5313/*
5314 * R12411 (0x307B) - Write Sequencer 123
5315 */
5316#define WM8995_WSEQ_EOS30 0x0100 /* WSEQ_EOS30 */
5317#define WM8995_WSEQ_EOS30_MASK 0x0100 /* WSEQ_EOS30 */
5318#define WM8995_WSEQ_EOS30_SHIFT 8 /* WSEQ_EOS30 */
5319#define WM8995_WSEQ_EOS30_WIDTH 1 /* WSEQ_EOS30 */
5320#define WM8995_WSEQ_DELAY30_MASK 0x000F /* WSEQ_DELAY30 - [3:0] */
5321#define WM8995_WSEQ_DELAY30_SHIFT 0 /* WSEQ_DELAY30 - [3:0] */
5322#define WM8995_WSEQ_DELAY30_WIDTH 4 /* WSEQ_DELAY30 - [3:0] */
5323
5324/*
5325 * R12412 (0x307C) - Write Sequencer 124
5326 */
5327#define WM8995_WSEQ_ADDR31_MASK 0x3FFF /* WSEQ_ADDR31 - [13:0] */
5328#define WM8995_WSEQ_ADDR31_SHIFT 0 /* WSEQ_ADDR31 - [13:0] */
5329#define WM8995_WSEQ_ADDR31_WIDTH 14 /* WSEQ_ADDR31 - [13:0] */
5330
5331/*
5332 * R12413 (0x307D) - Write Sequencer 125
5333 */
5334#define WM8995_WSEQ_DATA31_MASK 0x00FF /* WSEQ_DATA31 - [7:0] */
5335#define WM8995_WSEQ_DATA31_SHIFT 0 /* WSEQ_DATA31 - [7:0] */
5336#define WM8995_WSEQ_DATA31_WIDTH 8 /* WSEQ_DATA31 - [7:0] */
5337
5338/*
5339 * R12414 (0x307E) - Write Sequencer 126
5340 */
5341#define WM8995_WSEQ_DATA_WIDTH31_MASK 0x0700 /* WSEQ_DATA_WIDTH31 - [10:8] */
5342#define WM8995_WSEQ_DATA_WIDTH31_SHIFT 8 /* WSEQ_DATA_WIDTH31 - [10:8] */
5343#define WM8995_WSEQ_DATA_WIDTH31_WIDTH 3 /* WSEQ_DATA_WIDTH31 - [10:8] */
5344#define WM8995_WSEQ_DATA_START31_MASK 0x000F /* WSEQ_DATA_START31 - [3:0] */
5345#define WM8995_WSEQ_DATA_START31_SHIFT 0 /* WSEQ_DATA_START31 - [3:0] */
5346#define WM8995_WSEQ_DATA_START31_WIDTH 4 /* WSEQ_DATA_START31 - [3:0] */
5347
5348/*
5349 * R12415 (0x307F) - Write Sequencer 127
5350 */
5351#define WM8995_WSEQ_EOS31 0x0100 /* WSEQ_EOS31 */
5352#define WM8995_WSEQ_EOS31_MASK 0x0100 /* WSEQ_EOS31 */
5353#define WM8995_WSEQ_EOS31_SHIFT 8 /* WSEQ_EOS31 */
5354#define WM8995_WSEQ_EOS31_WIDTH 1 /* WSEQ_EOS31 */
5355#define WM8995_WSEQ_DELAY31_MASK 0x000F /* WSEQ_DELAY31 - [3:0] */
5356#define WM8995_WSEQ_DELAY31_SHIFT 0 /* WSEQ_DELAY31 - [3:0] */
5357#define WM8995_WSEQ_DELAY31_WIDTH 4 /* WSEQ_DELAY31 - [3:0] */
5358
5359/*
5360 * R12416 (0x3080) - Write Sequencer 128
5361 */
5362#define WM8995_WSEQ_ADDR32_MASK 0x3FFF /* WSEQ_ADDR32 - [13:0] */
5363#define WM8995_WSEQ_ADDR32_SHIFT 0 /* WSEQ_ADDR32 - [13:0] */
5364#define WM8995_WSEQ_ADDR32_WIDTH 14 /* WSEQ_ADDR32 - [13:0] */
5365
5366/*
5367 * R12417 (0x3081) - Write Sequencer 129
5368 */
5369#define WM8995_WSEQ_DATA32_MASK 0x00FF /* WSEQ_DATA32 - [7:0] */
5370#define WM8995_WSEQ_DATA32_SHIFT 0 /* WSEQ_DATA32 - [7:0] */
5371#define WM8995_WSEQ_DATA32_WIDTH 8 /* WSEQ_DATA32 - [7:0] */
5372
5373/*
5374 * R12418 (0x3082) - Write Sequencer 130
5375 */
5376#define WM8995_WSEQ_DATA_WIDTH32_MASK 0x0700 /* WSEQ_DATA_WIDTH32 - [10:8] */
5377#define WM8995_WSEQ_DATA_WIDTH32_SHIFT 8 /* WSEQ_DATA_WIDTH32 - [10:8] */
5378#define WM8995_WSEQ_DATA_WIDTH32_WIDTH 3 /* WSEQ_DATA_WIDTH32 - [10:8] */
5379#define WM8995_WSEQ_DATA_START32_MASK 0x000F /* WSEQ_DATA_START32 - [3:0] */
5380#define WM8995_WSEQ_DATA_START32_SHIFT 0 /* WSEQ_DATA_START32 - [3:0] */
5381#define WM8995_WSEQ_DATA_START32_WIDTH 4 /* WSEQ_DATA_START32 - [3:0] */
5382
5383/*
5384 * R12419 (0x3083) - Write Sequencer 131
5385 */
5386#define WM8995_WSEQ_EOS32 0x0100 /* WSEQ_EOS32 */
5387#define WM8995_WSEQ_EOS32_MASK 0x0100 /* WSEQ_EOS32 */
5388#define WM8995_WSEQ_EOS32_SHIFT 8 /* WSEQ_EOS32 */
5389#define WM8995_WSEQ_EOS32_WIDTH 1 /* WSEQ_EOS32 */
5390#define WM8995_WSEQ_DELAY32_MASK 0x000F /* WSEQ_DELAY32 - [3:0] */
5391#define WM8995_WSEQ_DELAY32_SHIFT 0 /* WSEQ_DELAY32 - [3:0] */
5392#define WM8995_WSEQ_DELAY32_WIDTH 4 /* WSEQ_DELAY32 - [3:0] */
5393
5394/*
5395 * R12420 (0x3084) - Write Sequencer 132
5396 */
5397#define WM8995_WSEQ_ADDR33_MASK 0x3FFF /* WSEQ_ADDR33 - [13:0] */
5398#define WM8995_WSEQ_ADDR33_SHIFT 0 /* WSEQ_ADDR33 - [13:0] */
5399#define WM8995_WSEQ_ADDR33_WIDTH 14 /* WSEQ_ADDR33 - [13:0] */
5400
5401/*
5402 * R12421 (0x3085) - Write Sequencer 133
5403 */
5404#define WM8995_WSEQ_DATA33_MASK 0x00FF /* WSEQ_DATA33 - [7:0] */
5405#define WM8995_WSEQ_DATA33_SHIFT 0 /* WSEQ_DATA33 - [7:0] */
5406#define WM8995_WSEQ_DATA33_WIDTH 8 /* WSEQ_DATA33 - [7:0] */
5407
5408/*
5409 * R12422 (0x3086) - Write Sequencer 134
5410 */
5411#define WM8995_WSEQ_DATA_WIDTH33_MASK 0x0700 /* WSEQ_DATA_WIDTH33 - [10:8] */
5412#define WM8995_WSEQ_DATA_WIDTH33_SHIFT 8 /* WSEQ_DATA_WIDTH33 - [10:8] */
5413#define WM8995_WSEQ_DATA_WIDTH33_WIDTH 3 /* WSEQ_DATA_WIDTH33 - [10:8] */
5414#define WM8995_WSEQ_DATA_START33_MASK 0x000F /* WSEQ_DATA_START33 - [3:0] */
5415#define WM8995_WSEQ_DATA_START33_SHIFT 0 /* WSEQ_DATA_START33 - [3:0] */
5416#define WM8995_WSEQ_DATA_START33_WIDTH 4 /* WSEQ_DATA_START33 - [3:0] */
5417
5418/*
5419 * R12423 (0x3087) - Write Sequencer 135
5420 */
5421#define WM8995_WSEQ_EOS33 0x0100 /* WSEQ_EOS33 */
5422#define WM8995_WSEQ_EOS33_MASK 0x0100 /* WSEQ_EOS33 */
5423#define WM8995_WSEQ_EOS33_SHIFT 8 /* WSEQ_EOS33 */
5424#define WM8995_WSEQ_EOS33_WIDTH 1 /* WSEQ_EOS33 */
5425#define WM8995_WSEQ_DELAY33_MASK 0x000F /* WSEQ_DELAY33 - [3:0] */
5426#define WM8995_WSEQ_DELAY33_SHIFT 0 /* WSEQ_DELAY33 - [3:0] */
5427#define WM8995_WSEQ_DELAY33_WIDTH 4 /* WSEQ_DELAY33 - [3:0] */
5428
5429/*
5430 * R12424 (0x3088) - Write Sequencer 136
5431 */
5432#define WM8995_WSEQ_ADDR34_MASK 0x3FFF /* WSEQ_ADDR34 - [13:0] */
5433#define WM8995_WSEQ_ADDR34_SHIFT 0 /* WSEQ_ADDR34 - [13:0] */
5434#define WM8995_WSEQ_ADDR34_WIDTH 14 /* WSEQ_ADDR34 - [13:0] */
5435
5436/*
5437 * R12425 (0x3089) - Write Sequencer 137
5438 */
5439#define WM8995_WSEQ_DATA34_MASK 0x00FF /* WSEQ_DATA34 - [7:0] */
5440#define WM8995_WSEQ_DATA34_SHIFT 0 /* WSEQ_DATA34 - [7:0] */
5441#define WM8995_WSEQ_DATA34_WIDTH 8 /* WSEQ_DATA34 - [7:0] */
5442
5443/*
5444 * R12426 (0x308A) - Write Sequencer 138
5445 */
5446#define WM8995_WSEQ_DATA_WIDTH34_MASK 0x0700 /* WSEQ_DATA_WIDTH34 - [10:8] */
5447#define WM8995_WSEQ_DATA_WIDTH34_SHIFT 8 /* WSEQ_DATA_WIDTH34 - [10:8] */
5448#define WM8995_WSEQ_DATA_WIDTH34_WIDTH 3 /* WSEQ_DATA_WIDTH34 - [10:8] */
5449#define WM8995_WSEQ_DATA_START34_MASK 0x000F /* WSEQ_DATA_START34 - [3:0] */
5450#define WM8995_WSEQ_DATA_START34_SHIFT 0 /* WSEQ_DATA_START34 - [3:0] */
5451#define WM8995_WSEQ_DATA_START34_WIDTH 4 /* WSEQ_DATA_START34 - [3:0] */
5452
5453/*
5454 * R12427 (0x308B) - Write Sequencer 139
5455 */
5456#define WM8995_WSEQ_EOS34 0x0100 /* WSEQ_EOS34 */
5457#define WM8995_WSEQ_EOS34_MASK 0x0100 /* WSEQ_EOS34 */
5458#define WM8995_WSEQ_EOS34_SHIFT 8 /* WSEQ_EOS34 */
5459#define WM8995_WSEQ_EOS34_WIDTH 1 /* WSEQ_EOS34 */
5460#define WM8995_WSEQ_DELAY34_MASK 0x000F /* WSEQ_DELAY34 - [3:0] */
5461#define WM8995_WSEQ_DELAY34_SHIFT 0 /* WSEQ_DELAY34 - [3:0] */
5462#define WM8995_WSEQ_DELAY34_WIDTH 4 /* WSEQ_DELAY34 - [3:0] */
5463
5464/*
5465 * R12428 (0x308C) - Write Sequencer 140
5466 */
5467#define WM8995_WSEQ_ADDR35_MASK 0x3FFF /* WSEQ_ADDR35 - [13:0] */
5468#define WM8995_WSEQ_ADDR35_SHIFT 0 /* WSEQ_ADDR35 - [13:0] */
5469#define WM8995_WSEQ_ADDR35_WIDTH 14 /* WSEQ_ADDR35 - [13:0] */
5470
5471/*
5472 * R12429 (0x308D) - Write Sequencer 141
5473 */
5474#define WM8995_WSEQ_DATA35_MASK 0x00FF /* WSEQ_DATA35 - [7:0] */
5475#define WM8995_WSEQ_DATA35_SHIFT 0 /* WSEQ_DATA35 - [7:0] */
5476#define WM8995_WSEQ_DATA35_WIDTH 8 /* WSEQ_DATA35 - [7:0] */
5477
5478/*
5479 * R12430 (0x308E) - Write Sequencer 142
5480 */
5481#define WM8995_WSEQ_DATA_WIDTH35_MASK 0x0700 /* WSEQ_DATA_WIDTH35 - [10:8] */
5482#define WM8995_WSEQ_DATA_WIDTH35_SHIFT 8 /* WSEQ_DATA_WIDTH35 - [10:8] */
5483#define WM8995_WSEQ_DATA_WIDTH35_WIDTH 3 /* WSEQ_DATA_WIDTH35 - [10:8] */
5484#define WM8995_WSEQ_DATA_START35_MASK 0x000F /* WSEQ_DATA_START35 - [3:0] */
5485#define WM8995_WSEQ_DATA_START35_SHIFT 0 /* WSEQ_DATA_START35 - [3:0] */
5486#define WM8995_WSEQ_DATA_START35_WIDTH 4 /* WSEQ_DATA_START35 - [3:0] */
5487
5488/*
5489 * R12431 (0x308F) - Write Sequencer 143
5490 */
5491#define WM8995_WSEQ_EOS35 0x0100 /* WSEQ_EOS35 */
5492#define WM8995_WSEQ_EOS35_MASK 0x0100 /* WSEQ_EOS35 */
5493#define WM8995_WSEQ_EOS35_SHIFT 8 /* WSEQ_EOS35 */
5494#define WM8995_WSEQ_EOS35_WIDTH 1 /* WSEQ_EOS35 */
5495#define WM8995_WSEQ_DELAY35_MASK 0x000F /* WSEQ_DELAY35 - [3:0] */
5496#define WM8995_WSEQ_DELAY35_SHIFT 0 /* WSEQ_DELAY35 - [3:0] */
5497#define WM8995_WSEQ_DELAY35_WIDTH 4 /* WSEQ_DELAY35 - [3:0] */
5498
5499/*
5500 * R12432 (0x3090) - Write Sequencer 144
5501 */
5502#define WM8995_WSEQ_ADDR36_MASK 0x3FFF /* WSEQ_ADDR36 - [13:0] */
5503#define WM8995_WSEQ_ADDR36_SHIFT 0 /* WSEQ_ADDR36 - [13:0] */
5504#define WM8995_WSEQ_ADDR36_WIDTH 14 /* WSEQ_ADDR36 - [13:0] */
5505
5506/*
5507 * R12433 (0x3091) - Write Sequencer 145
5508 */
5509#define WM8995_WSEQ_DATA36_MASK 0x00FF /* WSEQ_DATA36 - [7:0] */
5510#define WM8995_WSEQ_DATA36_SHIFT 0 /* WSEQ_DATA36 - [7:0] */
5511#define WM8995_WSEQ_DATA36_WIDTH 8 /* WSEQ_DATA36 - [7:0] */
5512
5513/*
5514 * R12434 (0x3092) - Write Sequencer 146
5515 */
5516#define WM8995_WSEQ_DATA_WIDTH36_MASK 0x0700 /* WSEQ_DATA_WIDTH36 - [10:8] */
5517#define WM8995_WSEQ_DATA_WIDTH36_SHIFT 8 /* WSEQ_DATA_WIDTH36 - [10:8] */
5518#define WM8995_WSEQ_DATA_WIDTH36_WIDTH 3 /* WSEQ_DATA_WIDTH36 - [10:8] */
5519#define WM8995_WSEQ_DATA_START36_MASK 0x000F /* WSEQ_DATA_START36 - [3:0] */
5520#define WM8995_WSEQ_DATA_START36_SHIFT 0 /* WSEQ_DATA_START36 - [3:0] */
5521#define WM8995_WSEQ_DATA_START36_WIDTH 4 /* WSEQ_DATA_START36 - [3:0] */
5522
5523/*
5524 * R12435 (0x3093) - Write Sequencer 147
5525 */
5526#define WM8995_WSEQ_EOS36 0x0100 /* WSEQ_EOS36 */
5527#define WM8995_WSEQ_EOS36_MASK 0x0100 /* WSEQ_EOS36 */
5528#define WM8995_WSEQ_EOS36_SHIFT 8 /* WSEQ_EOS36 */
5529#define WM8995_WSEQ_EOS36_WIDTH 1 /* WSEQ_EOS36 */
5530#define WM8995_WSEQ_DELAY36_MASK 0x000F /* WSEQ_DELAY36 - [3:0] */
5531#define WM8995_WSEQ_DELAY36_SHIFT 0 /* WSEQ_DELAY36 - [3:0] */
5532#define WM8995_WSEQ_DELAY36_WIDTH 4 /* WSEQ_DELAY36 - [3:0] */
5533
5534/*
5535 * R12436 (0x3094) - Write Sequencer 148
5536 */
5537#define WM8995_WSEQ_ADDR37_MASK 0x3FFF /* WSEQ_ADDR37 - [13:0] */
5538#define WM8995_WSEQ_ADDR37_SHIFT 0 /* WSEQ_ADDR37 - [13:0] */
5539#define WM8995_WSEQ_ADDR37_WIDTH 14 /* WSEQ_ADDR37 - [13:0] */
5540
5541/*
5542 * R12437 (0x3095) - Write Sequencer 149
5543 */
5544#define WM8995_WSEQ_DATA37_MASK 0x00FF /* WSEQ_DATA37 - [7:0] */
5545#define WM8995_WSEQ_DATA37_SHIFT 0 /* WSEQ_DATA37 - [7:0] */
5546#define WM8995_WSEQ_DATA37_WIDTH 8 /* WSEQ_DATA37 - [7:0] */
5547
5548/*
5549 * R12438 (0x3096) - Write Sequencer 150
5550 */
5551#define WM8995_WSEQ_DATA_WIDTH37_MASK 0x0700 /* WSEQ_DATA_WIDTH37 - [10:8] */
5552#define WM8995_WSEQ_DATA_WIDTH37_SHIFT 8 /* WSEQ_DATA_WIDTH37 - [10:8] */
5553#define WM8995_WSEQ_DATA_WIDTH37_WIDTH 3 /* WSEQ_DATA_WIDTH37 - [10:8] */
5554#define WM8995_WSEQ_DATA_START37_MASK 0x000F /* WSEQ_DATA_START37 - [3:0] */
5555#define WM8995_WSEQ_DATA_START37_SHIFT 0 /* WSEQ_DATA_START37 - [3:0] */
5556#define WM8995_WSEQ_DATA_START37_WIDTH 4 /* WSEQ_DATA_START37 - [3:0] */
5557
5558/*
5559 * R12439 (0x3097) - Write Sequencer 151
5560 */
5561#define WM8995_WSEQ_EOS37 0x0100 /* WSEQ_EOS37 */
5562#define WM8995_WSEQ_EOS37_MASK 0x0100 /* WSEQ_EOS37 */
5563#define WM8995_WSEQ_EOS37_SHIFT 8 /* WSEQ_EOS37 */
5564#define WM8995_WSEQ_EOS37_WIDTH 1 /* WSEQ_EOS37 */
5565#define WM8995_WSEQ_DELAY37_MASK 0x000F /* WSEQ_DELAY37 - [3:0] */
5566#define WM8995_WSEQ_DELAY37_SHIFT 0 /* WSEQ_DELAY37 - [3:0] */
5567#define WM8995_WSEQ_DELAY37_WIDTH 4 /* WSEQ_DELAY37 - [3:0] */
5568
5569/*
5570 * R12440 (0x3098) - Write Sequencer 152
5571 */
5572#define WM8995_WSEQ_ADDR38_MASK 0x3FFF /* WSEQ_ADDR38 - [13:0] */
5573#define WM8995_WSEQ_ADDR38_SHIFT 0 /* WSEQ_ADDR38 - [13:0] */
5574#define WM8995_WSEQ_ADDR38_WIDTH 14 /* WSEQ_ADDR38 - [13:0] */
5575
5576/*
5577 * R12441 (0x3099) - Write Sequencer 153
5578 */
5579#define WM8995_WSEQ_DATA38_MASK 0x00FF /* WSEQ_DATA38 - [7:0] */
5580#define WM8995_WSEQ_DATA38_SHIFT 0 /* WSEQ_DATA38 - [7:0] */
5581#define WM8995_WSEQ_DATA38_WIDTH 8 /* WSEQ_DATA38 - [7:0] */
5582
5583/*
5584 * R12442 (0x309A) - Write Sequencer 154
5585 */
5586#define WM8995_WSEQ_DATA_WIDTH38_MASK 0x0700 /* WSEQ_DATA_WIDTH38 - [10:8] */
5587#define WM8995_WSEQ_DATA_WIDTH38_SHIFT 8 /* WSEQ_DATA_WIDTH38 - [10:8] */
5588#define WM8995_WSEQ_DATA_WIDTH38_WIDTH 3 /* WSEQ_DATA_WIDTH38 - [10:8] */
5589#define WM8995_WSEQ_DATA_START38_MASK 0x000F /* WSEQ_DATA_START38 - [3:0] */
5590#define WM8995_WSEQ_DATA_START38_SHIFT 0 /* WSEQ_DATA_START38 - [3:0] */
5591#define WM8995_WSEQ_DATA_START38_WIDTH 4 /* WSEQ_DATA_START38 - [3:0] */
5592
5593/*
5594 * R12443 (0x309B) - Write Sequencer 155
5595 */
5596#define WM8995_WSEQ_EOS38 0x0100 /* WSEQ_EOS38 */
5597#define WM8995_WSEQ_EOS38_MASK 0x0100 /* WSEQ_EOS38 */
5598#define WM8995_WSEQ_EOS38_SHIFT 8 /* WSEQ_EOS38 */
5599#define WM8995_WSEQ_EOS38_WIDTH 1 /* WSEQ_EOS38 */
5600#define WM8995_WSEQ_DELAY38_MASK 0x000F /* WSEQ_DELAY38 - [3:0] */
5601#define WM8995_WSEQ_DELAY38_SHIFT 0 /* WSEQ_DELAY38 - [3:0] */
5602#define WM8995_WSEQ_DELAY38_WIDTH 4 /* WSEQ_DELAY38 - [3:0] */
5603
5604/*
5605 * R12444 (0x309C) - Write Sequencer 156
5606 */
5607#define WM8995_WSEQ_ADDR39_MASK 0x3FFF /* WSEQ_ADDR39 - [13:0] */
5608#define WM8995_WSEQ_ADDR39_SHIFT 0 /* WSEQ_ADDR39 - [13:0] */
5609#define WM8995_WSEQ_ADDR39_WIDTH 14 /* WSEQ_ADDR39 - [13:0] */
5610
5611/*
5612 * R12445 (0x309D) - Write Sequencer 157
5613 */
5614#define WM8995_WSEQ_DATA39_MASK 0x00FF /* WSEQ_DATA39 - [7:0] */
5615#define WM8995_WSEQ_DATA39_SHIFT 0 /* WSEQ_DATA39 - [7:0] */
5616#define WM8995_WSEQ_DATA39_WIDTH 8 /* WSEQ_DATA39 - [7:0] */
5617
5618/*
5619 * R12446 (0x309E) - Write Sequencer 158
5620 */
5621#define WM8995_WSEQ_DATA_WIDTH39_MASK 0x0700 /* WSEQ_DATA_WIDTH39 - [10:8] */
5622#define WM8995_WSEQ_DATA_WIDTH39_SHIFT 8 /* WSEQ_DATA_WIDTH39 - [10:8] */
5623#define WM8995_WSEQ_DATA_WIDTH39_WIDTH 3 /* WSEQ_DATA_WIDTH39 - [10:8] */
5624#define WM8995_WSEQ_DATA_START39_MASK 0x000F /* WSEQ_DATA_START39 - [3:0] */
5625#define WM8995_WSEQ_DATA_START39_SHIFT 0 /* WSEQ_DATA_START39 - [3:0] */
5626#define WM8995_WSEQ_DATA_START39_WIDTH 4 /* WSEQ_DATA_START39 - [3:0] */
5627
5628/*
5629 * R12447 (0x309F) - Write Sequencer 159
5630 */
5631#define WM8995_WSEQ_EOS39 0x0100 /* WSEQ_EOS39 */
5632#define WM8995_WSEQ_EOS39_MASK 0x0100 /* WSEQ_EOS39 */
5633#define WM8995_WSEQ_EOS39_SHIFT 8 /* WSEQ_EOS39 */
5634#define WM8995_WSEQ_EOS39_WIDTH 1 /* WSEQ_EOS39 */
5635#define WM8995_WSEQ_DELAY39_MASK 0x000F /* WSEQ_DELAY39 - [3:0] */
5636#define WM8995_WSEQ_DELAY39_SHIFT 0 /* WSEQ_DELAY39 - [3:0] */
5637#define WM8995_WSEQ_DELAY39_WIDTH 4 /* WSEQ_DELAY39 - [3:0] */
5638
5639/*
5640 * R12448 (0x30A0) - Write Sequencer 160
5641 */
5642#define WM8995_WSEQ_ADDR40_MASK 0x3FFF /* WSEQ_ADDR40 - [13:0] */
5643#define WM8995_WSEQ_ADDR40_SHIFT 0 /* WSEQ_ADDR40 - [13:0] */
5644#define WM8995_WSEQ_ADDR40_WIDTH 14 /* WSEQ_ADDR40 - [13:0] */
5645
5646/*
5647 * R12449 (0x30A1) - Write Sequencer 161
5648 */
5649#define WM8995_WSEQ_DATA40_MASK 0x00FF /* WSEQ_DATA40 - [7:0] */
5650#define WM8995_WSEQ_DATA40_SHIFT 0 /* WSEQ_DATA40 - [7:0] */
5651#define WM8995_WSEQ_DATA40_WIDTH 8 /* WSEQ_DATA40 - [7:0] */
5652
5653/*
5654 * R12450 (0x30A2) - Write Sequencer 162
5655 */
5656#define WM8995_WSEQ_DATA_WIDTH40_MASK 0x0700 /* WSEQ_DATA_WIDTH40 - [10:8] */
5657#define WM8995_WSEQ_DATA_WIDTH40_SHIFT 8 /* WSEQ_DATA_WIDTH40 - [10:8] */
5658#define WM8995_WSEQ_DATA_WIDTH40_WIDTH 3 /* WSEQ_DATA_WIDTH40 - [10:8] */
5659#define WM8995_WSEQ_DATA_START40_MASK 0x000F /* WSEQ_DATA_START40 - [3:0] */
5660#define WM8995_WSEQ_DATA_START40_SHIFT 0 /* WSEQ_DATA_START40 - [3:0] */
5661#define WM8995_WSEQ_DATA_START40_WIDTH 4 /* WSEQ_DATA_START40 - [3:0] */
5662
5663/*
5664 * R12451 (0x30A3) - Write Sequencer 163
5665 */
5666#define WM8995_WSEQ_EOS40 0x0100 /* WSEQ_EOS40 */
5667#define WM8995_WSEQ_EOS40_MASK 0x0100 /* WSEQ_EOS40 */
5668#define WM8995_WSEQ_EOS40_SHIFT 8 /* WSEQ_EOS40 */
5669#define WM8995_WSEQ_EOS40_WIDTH 1 /* WSEQ_EOS40 */
5670#define WM8995_WSEQ_DELAY40_MASK 0x000F /* WSEQ_DELAY40 - [3:0] */
5671#define WM8995_WSEQ_DELAY40_SHIFT 0 /* WSEQ_DELAY40 - [3:0] */
5672#define WM8995_WSEQ_DELAY40_WIDTH 4 /* WSEQ_DELAY40 - [3:0] */
5673
5674/*
5675 * R12452 (0x30A4) - Write Sequencer 164
5676 */
5677#define WM8995_WSEQ_ADDR41_MASK 0x3FFF /* WSEQ_ADDR41 - [13:0] */
5678#define WM8995_WSEQ_ADDR41_SHIFT 0 /* WSEQ_ADDR41 - [13:0] */
5679#define WM8995_WSEQ_ADDR41_WIDTH 14 /* WSEQ_ADDR41 - [13:0] */
5680
5681/*
5682 * R12453 (0x30A5) - Write Sequencer 165
5683 */
5684#define WM8995_WSEQ_DATA41_MASK 0x00FF /* WSEQ_DATA41 - [7:0] */
5685#define WM8995_WSEQ_DATA41_SHIFT 0 /* WSEQ_DATA41 - [7:0] */
5686#define WM8995_WSEQ_DATA41_WIDTH 8 /* WSEQ_DATA41 - [7:0] */
5687
5688/*
5689 * R12454 (0x30A6) - Write Sequencer 166
5690 */
5691#define WM8995_WSEQ_DATA_WIDTH41_MASK 0x0700 /* WSEQ_DATA_WIDTH41 - [10:8] */
5692#define WM8995_WSEQ_DATA_WIDTH41_SHIFT 8 /* WSEQ_DATA_WIDTH41 - [10:8] */
5693#define WM8995_WSEQ_DATA_WIDTH41_WIDTH 3 /* WSEQ_DATA_WIDTH41 - [10:8] */
5694#define WM8995_WSEQ_DATA_START41_MASK 0x000F /* WSEQ_DATA_START41 - [3:0] */
5695#define WM8995_WSEQ_DATA_START41_SHIFT 0 /* WSEQ_DATA_START41 - [3:0] */
5696#define WM8995_WSEQ_DATA_START41_WIDTH 4 /* WSEQ_DATA_START41 - [3:0] */
5697
5698/*
5699 * R12455 (0x30A7) - Write Sequencer 167
5700 */
5701#define WM8995_WSEQ_EOS41 0x0100 /* WSEQ_EOS41 */
5702#define WM8995_WSEQ_EOS41_MASK 0x0100 /* WSEQ_EOS41 */
5703#define WM8995_WSEQ_EOS41_SHIFT 8 /* WSEQ_EOS41 */
5704#define WM8995_WSEQ_EOS41_WIDTH 1 /* WSEQ_EOS41 */
5705#define WM8995_WSEQ_DELAY41_MASK 0x000F /* WSEQ_DELAY41 - [3:0] */
5706#define WM8995_WSEQ_DELAY41_SHIFT 0 /* WSEQ_DELAY41 - [3:0] */
5707#define WM8995_WSEQ_DELAY41_WIDTH 4 /* WSEQ_DELAY41 - [3:0] */
5708
5709/*
5710 * R12456 (0x30A8) - Write Sequencer 168
5711 */
5712#define WM8995_WSEQ_ADDR42_MASK 0x3FFF /* WSEQ_ADDR42 - [13:0] */
5713#define WM8995_WSEQ_ADDR42_SHIFT 0 /* WSEQ_ADDR42 - [13:0] */
5714#define WM8995_WSEQ_ADDR42_WIDTH 14 /* WSEQ_ADDR42 - [13:0] */
5715
5716/*
5717 * R12457 (0x30A9) - Write Sequencer 169
5718 */
5719#define WM8995_WSEQ_DATA42_MASK 0x00FF /* WSEQ_DATA42 - [7:0] */
5720#define WM8995_WSEQ_DATA42_SHIFT 0 /* WSEQ_DATA42 - [7:0] */
5721#define WM8995_WSEQ_DATA42_WIDTH 8 /* WSEQ_DATA42 - [7:0] */
5722
5723/*
5724 * R12458 (0x30AA) - Write Sequencer 170
5725 */
5726#define WM8995_WSEQ_DATA_WIDTH42_MASK 0x0700 /* WSEQ_DATA_WIDTH42 - [10:8] */
5727#define WM8995_WSEQ_DATA_WIDTH42_SHIFT 8 /* WSEQ_DATA_WIDTH42 - [10:8] */
5728#define WM8995_WSEQ_DATA_WIDTH42_WIDTH 3 /* WSEQ_DATA_WIDTH42 - [10:8] */
5729#define WM8995_WSEQ_DATA_START42_MASK 0x000F /* WSEQ_DATA_START42 - [3:0] */
5730#define WM8995_WSEQ_DATA_START42_SHIFT 0 /* WSEQ_DATA_START42 - [3:0] */
5731#define WM8995_WSEQ_DATA_START42_WIDTH 4 /* WSEQ_DATA_START42 - [3:0] */
5732
5733/*
5734 * R12459 (0x30AB) - Write Sequencer 171
5735 */
5736#define WM8995_WSEQ_EOS42 0x0100 /* WSEQ_EOS42 */
5737#define WM8995_WSEQ_EOS42_MASK 0x0100 /* WSEQ_EOS42 */
5738#define WM8995_WSEQ_EOS42_SHIFT 8 /* WSEQ_EOS42 */
5739#define WM8995_WSEQ_EOS42_WIDTH 1 /* WSEQ_EOS42 */
5740#define WM8995_WSEQ_DELAY42_MASK 0x000F /* WSEQ_DELAY42 - [3:0] */
5741#define WM8995_WSEQ_DELAY42_SHIFT 0 /* WSEQ_DELAY42 - [3:0] */
5742#define WM8995_WSEQ_DELAY42_WIDTH 4 /* WSEQ_DELAY42 - [3:0] */
5743
5744/*
5745 * R12460 (0x30AC) - Write Sequencer 172
5746 */
5747#define WM8995_WSEQ_ADDR43_MASK 0x3FFF /* WSEQ_ADDR43 - [13:0] */
5748#define WM8995_WSEQ_ADDR43_SHIFT 0 /* WSEQ_ADDR43 - [13:0] */
5749#define WM8995_WSEQ_ADDR43_WIDTH 14 /* WSEQ_ADDR43 - [13:0] */
5750
5751/*
5752 * R12461 (0x30AD) - Write Sequencer 173
5753 */
5754#define WM8995_WSEQ_DATA43_MASK 0x00FF /* WSEQ_DATA43 - [7:0] */
5755#define WM8995_WSEQ_DATA43_SHIFT 0 /* WSEQ_DATA43 - [7:0] */
5756#define WM8995_WSEQ_DATA43_WIDTH 8 /* WSEQ_DATA43 - [7:0] */
5757
5758/*
5759 * R12462 (0x30AE) - Write Sequencer 174
5760 */
5761#define WM8995_WSEQ_DATA_WIDTH43_MASK 0x0700 /* WSEQ_DATA_WIDTH43 - [10:8] */
5762#define WM8995_WSEQ_DATA_WIDTH43_SHIFT 8 /* WSEQ_DATA_WIDTH43 - [10:8] */
5763#define WM8995_WSEQ_DATA_WIDTH43_WIDTH 3 /* WSEQ_DATA_WIDTH43 - [10:8] */
5764#define WM8995_WSEQ_DATA_START43_MASK 0x000F /* WSEQ_DATA_START43 - [3:0] */
5765#define WM8995_WSEQ_DATA_START43_SHIFT 0 /* WSEQ_DATA_START43 - [3:0] */
5766#define WM8995_WSEQ_DATA_START43_WIDTH 4 /* WSEQ_DATA_START43 - [3:0] */
5767
5768/*
5769 * R12463 (0x30AF) - Write Sequencer 175
5770 */
5771#define WM8995_WSEQ_EOS43 0x0100 /* WSEQ_EOS43 */
5772#define WM8995_WSEQ_EOS43_MASK 0x0100 /* WSEQ_EOS43 */
5773#define WM8995_WSEQ_EOS43_SHIFT 8 /* WSEQ_EOS43 */
5774#define WM8995_WSEQ_EOS43_WIDTH 1 /* WSEQ_EOS43 */
5775#define WM8995_WSEQ_DELAY43_MASK 0x000F /* WSEQ_DELAY43 - [3:0] */
5776#define WM8995_WSEQ_DELAY43_SHIFT 0 /* WSEQ_DELAY43 - [3:0] */
5777#define WM8995_WSEQ_DELAY43_WIDTH 4 /* WSEQ_DELAY43 - [3:0] */
5778
5779/*
5780 * R12464 (0x30B0) - Write Sequencer 176
5781 */
5782#define WM8995_WSEQ_ADDR44_MASK 0x3FFF /* WSEQ_ADDR44 - [13:0] */
5783#define WM8995_WSEQ_ADDR44_SHIFT 0 /* WSEQ_ADDR44 - [13:0] */
5784#define WM8995_WSEQ_ADDR44_WIDTH 14 /* WSEQ_ADDR44 - [13:0] */
5785
5786/*
5787 * R12465 (0x30B1) - Write Sequencer 177
5788 */
5789#define WM8995_WSEQ_DATA44_MASK 0x00FF /* WSEQ_DATA44 - [7:0] */
5790#define WM8995_WSEQ_DATA44_SHIFT 0 /* WSEQ_DATA44 - [7:0] */
5791#define WM8995_WSEQ_DATA44_WIDTH 8 /* WSEQ_DATA44 - [7:0] */
5792
5793/*
5794 * R12466 (0x30B2) - Write Sequencer 178
5795 */
5796#define WM8995_WSEQ_DATA_WIDTH44_MASK 0x0700 /* WSEQ_DATA_WIDTH44 - [10:8] */
5797#define WM8995_WSEQ_DATA_WIDTH44_SHIFT 8 /* WSEQ_DATA_WIDTH44 - [10:8] */
5798#define WM8995_WSEQ_DATA_WIDTH44_WIDTH 3 /* WSEQ_DATA_WIDTH44 - [10:8] */
5799#define WM8995_WSEQ_DATA_START44_MASK 0x000F /* WSEQ_DATA_START44 - [3:0] */
5800#define WM8995_WSEQ_DATA_START44_SHIFT 0 /* WSEQ_DATA_START44 - [3:0] */
5801#define WM8995_WSEQ_DATA_START44_WIDTH 4 /* WSEQ_DATA_START44 - [3:0] */
5802
5803/*
5804 * R12467 (0x30B3) - Write Sequencer 179
5805 */
5806#define WM8995_WSEQ_EOS44 0x0100 /* WSEQ_EOS44 */
5807#define WM8995_WSEQ_EOS44_MASK 0x0100 /* WSEQ_EOS44 */
5808#define WM8995_WSEQ_EOS44_SHIFT 8 /* WSEQ_EOS44 */
5809#define WM8995_WSEQ_EOS44_WIDTH 1 /* WSEQ_EOS44 */
5810#define WM8995_WSEQ_DELAY44_MASK 0x000F /* WSEQ_DELAY44 - [3:0] */
5811#define WM8995_WSEQ_DELAY44_SHIFT 0 /* WSEQ_DELAY44 - [3:0] */
5812#define WM8995_WSEQ_DELAY44_WIDTH 4 /* WSEQ_DELAY44 - [3:0] */
5813
5814/*
5815 * R12468 (0x30B4) - Write Sequencer 180
5816 */
5817#define WM8995_WSEQ_ADDR45_MASK 0x3FFF /* WSEQ_ADDR45 - [13:0] */
5818#define WM8995_WSEQ_ADDR45_SHIFT 0 /* WSEQ_ADDR45 - [13:0] */
5819#define WM8995_WSEQ_ADDR45_WIDTH 14 /* WSEQ_ADDR45 - [13:0] */
5820
5821/*
5822 * R12469 (0x30B5) - Write Sequencer 181
5823 */
5824#define WM8995_WSEQ_DATA45_MASK 0x00FF /* WSEQ_DATA45 - [7:0] */
5825#define WM8995_WSEQ_DATA45_SHIFT 0 /* WSEQ_DATA45 - [7:0] */
5826#define WM8995_WSEQ_DATA45_WIDTH 8 /* WSEQ_DATA45 - [7:0] */
5827
5828/*
5829 * R12470 (0x30B6) - Write Sequencer 182
5830 */
5831#define WM8995_WSEQ_DATA_WIDTH45_MASK 0x0700 /* WSEQ_DATA_WIDTH45 - [10:8] */
5832#define WM8995_WSEQ_DATA_WIDTH45_SHIFT 8 /* WSEQ_DATA_WIDTH45 - [10:8] */
5833#define WM8995_WSEQ_DATA_WIDTH45_WIDTH 3 /* WSEQ_DATA_WIDTH45 - [10:8] */
5834#define WM8995_WSEQ_DATA_START45_MASK 0x000F /* WSEQ_DATA_START45 - [3:0] */
5835#define WM8995_WSEQ_DATA_START45_SHIFT 0 /* WSEQ_DATA_START45 - [3:0] */
5836#define WM8995_WSEQ_DATA_START45_WIDTH 4 /* WSEQ_DATA_START45 - [3:0] */
5837
5838/*
5839 * R12471 (0x30B7) - Write Sequencer 183
5840 */
5841#define WM8995_WSEQ_EOS45 0x0100 /* WSEQ_EOS45 */
5842#define WM8995_WSEQ_EOS45_MASK 0x0100 /* WSEQ_EOS45 */
5843#define WM8995_WSEQ_EOS45_SHIFT 8 /* WSEQ_EOS45 */
5844#define WM8995_WSEQ_EOS45_WIDTH 1 /* WSEQ_EOS45 */
5845#define WM8995_WSEQ_DELAY45_MASK 0x000F /* WSEQ_DELAY45 - [3:0] */
5846#define WM8995_WSEQ_DELAY45_SHIFT 0 /* WSEQ_DELAY45 - [3:0] */
5847#define WM8995_WSEQ_DELAY45_WIDTH 4 /* WSEQ_DELAY45 - [3:0] */
5848
5849/*
5850 * R12472 (0x30B8) - Write Sequencer 184
5851 */
5852#define WM8995_WSEQ_ADDR46_MASK 0x3FFF /* WSEQ_ADDR46 - [13:0] */
5853#define WM8995_WSEQ_ADDR46_SHIFT 0 /* WSEQ_ADDR46 - [13:0] */
5854#define WM8995_WSEQ_ADDR46_WIDTH 14 /* WSEQ_ADDR46 - [13:0] */
5855
5856/*
5857 * R12473 (0x30B9) - Write Sequencer 185
5858 */
5859#define WM8995_WSEQ_DATA46_MASK 0x00FF /* WSEQ_DATA46 - [7:0] */
5860#define WM8995_WSEQ_DATA46_SHIFT 0 /* WSEQ_DATA46 - [7:0] */
5861#define WM8995_WSEQ_DATA46_WIDTH 8 /* WSEQ_DATA46 - [7:0] */
5862
5863/*
5864 * R12474 (0x30BA) - Write Sequencer 186
5865 */
5866#define WM8995_WSEQ_DATA_WIDTH46_MASK 0x0700 /* WSEQ_DATA_WIDTH46 - [10:8] */
5867#define WM8995_WSEQ_DATA_WIDTH46_SHIFT 8 /* WSEQ_DATA_WIDTH46 - [10:8] */
5868#define WM8995_WSEQ_DATA_WIDTH46_WIDTH 3 /* WSEQ_DATA_WIDTH46 - [10:8] */
5869#define WM8995_WSEQ_DATA_START46_MASK 0x000F /* WSEQ_DATA_START46 - [3:0] */
5870#define WM8995_WSEQ_DATA_START46_SHIFT 0 /* WSEQ_DATA_START46 - [3:0] */
5871#define WM8995_WSEQ_DATA_START46_WIDTH 4 /* WSEQ_DATA_START46 - [3:0] */
5872
5873/*
5874 * R12475 (0x30BB) - Write Sequencer 187
5875 */
5876#define WM8995_WSEQ_EOS46 0x0100 /* WSEQ_EOS46 */
5877#define WM8995_WSEQ_EOS46_MASK 0x0100 /* WSEQ_EOS46 */
5878#define WM8995_WSEQ_EOS46_SHIFT 8 /* WSEQ_EOS46 */
5879#define WM8995_WSEQ_EOS46_WIDTH 1 /* WSEQ_EOS46 */
5880#define WM8995_WSEQ_DELAY46_MASK 0x000F /* WSEQ_DELAY46 - [3:0] */
5881#define WM8995_WSEQ_DELAY46_SHIFT 0 /* WSEQ_DELAY46 - [3:0] */
5882#define WM8995_WSEQ_DELAY46_WIDTH 4 /* WSEQ_DELAY46 - [3:0] */
5883
5884/*
5885 * R12476 (0x30BC) - Write Sequencer 188
5886 */
5887#define WM8995_WSEQ_ADDR47_MASK 0x3FFF /* WSEQ_ADDR47 - [13:0] */
5888#define WM8995_WSEQ_ADDR47_SHIFT 0 /* WSEQ_ADDR47 - [13:0] */
5889#define WM8995_WSEQ_ADDR47_WIDTH 14 /* WSEQ_ADDR47 - [13:0] */
5890
5891/*
5892 * R12477 (0x30BD) - Write Sequencer 189
5893 */
5894#define WM8995_WSEQ_DATA47_MASK 0x00FF /* WSEQ_DATA47 - [7:0] */
5895#define WM8995_WSEQ_DATA47_SHIFT 0 /* WSEQ_DATA47 - [7:0] */
5896#define WM8995_WSEQ_DATA47_WIDTH 8 /* WSEQ_DATA47 - [7:0] */
5897
5898/*
5899 * R12478 (0x30BE) - Write Sequencer 190
5900 */
5901#define WM8995_WSEQ_DATA_WIDTH47_MASK 0x0700 /* WSEQ_DATA_WIDTH47 - [10:8] */
5902#define WM8995_WSEQ_DATA_WIDTH47_SHIFT 8 /* WSEQ_DATA_WIDTH47 - [10:8] */
5903#define WM8995_WSEQ_DATA_WIDTH47_WIDTH 3 /* WSEQ_DATA_WIDTH47 - [10:8] */
5904#define WM8995_WSEQ_DATA_START47_MASK 0x000F /* WSEQ_DATA_START47 - [3:0] */
5905#define WM8995_WSEQ_DATA_START47_SHIFT 0 /* WSEQ_DATA_START47 - [3:0] */
5906#define WM8995_WSEQ_DATA_START47_WIDTH 4 /* WSEQ_DATA_START47 - [3:0] */
5907
5908/*
5909 * R12479 (0x30BF) - Write Sequencer 191
5910 */
5911#define WM8995_WSEQ_EOS47 0x0100 /* WSEQ_EOS47 */
5912#define WM8995_WSEQ_EOS47_MASK 0x0100 /* WSEQ_EOS47 */
5913#define WM8995_WSEQ_EOS47_SHIFT 8 /* WSEQ_EOS47 */
5914#define WM8995_WSEQ_EOS47_WIDTH 1 /* WSEQ_EOS47 */
5915#define WM8995_WSEQ_DELAY47_MASK 0x000F /* WSEQ_DELAY47 - [3:0] */
5916#define WM8995_WSEQ_DELAY47_SHIFT 0 /* WSEQ_DELAY47 - [3:0] */
5917#define WM8995_WSEQ_DELAY47_WIDTH 4 /* WSEQ_DELAY47 - [3:0] */
5918
5919/*
5920 * R12480 (0x30C0) - Write Sequencer 192
5921 */
5922#define WM8995_WSEQ_ADDR48_MASK 0x3FFF /* WSEQ_ADDR48 - [13:0] */
5923#define WM8995_WSEQ_ADDR48_SHIFT 0 /* WSEQ_ADDR48 - [13:0] */
5924#define WM8995_WSEQ_ADDR48_WIDTH 14 /* WSEQ_ADDR48 - [13:0] */
5925
5926/*
5927 * R12481 (0x30C1) - Write Sequencer 193
5928 */
5929#define WM8995_WSEQ_DATA48_MASK 0x00FF /* WSEQ_DATA48 - [7:0] */
5930#define WM8995_WSEQ_DATA48_SHIFT 0 /* WSEQ_DATA48 - [7:0] */
5931#define WM8995_WSEQ_DATA48_WIDTH 8 /* WSEQ_DATA48 - [7:0] */
5932
5933/*
5934 * R12482 (0x30C2) - Write Sequencer 194
5935 */
5936#define WM8995_WSEQ_DATA_WIDTH48_MASK 0x0700 /* WSEQ_DATA_WIDTH48 - [10:8] */
5937#define WM8995_WSEQ_DATA_WIDTH48_SHIFT 8 /* WSEQ_DATA_WIDTH48 - [10:8] */
5938#define WM8995_WSEQ_DATA_WIDTH48_WIDTH 3 /* WSEQ_DATA_WIDTH48 - [10:8] */
5939#define WM8995_WSEQ_DATA_START48_MASK 0x000F /* WSEQ_DATA_START48 - [3:0] */
5940#define WM8995_WSEQ_DATA_START48_SHIFT 0 /* WSEQ_DATA_START48 - [3:0] */
5941#define WM8995_WSEQ_DATA_START48_WIDTH 4 /* WSEQ_DATA_START48 - [3:0] */
5942
5943/*
5944 * R12483 (0x30C3) - Write Sequencer 195
5945 */
5946#define WM8995_WSEQ_EOS48 0x0100 /* WSEQ_EOS48 */
5947#define WM8995_WSEQ_EOS48_MASK 0x0100 /* WSEQ_EOS48 */
5948#define WM8995_WSEQ_EOS48_SHIFT 8 /* WSEQ_EOS48 */
5949#define WM8995_WSEQ_EOS48_WIDTH 1 /* WSEQ_EOS48 */
5950#define WM8995_WSEQ_DELAY48_MASK 0x000F /* WSEQ_DELAY48 - [3:0] */
5951#define WM8995_WSEQ_DELAY48_SHIFT 0 /* WSEQ_DELAY48 - [3:0] */
5952#define WM8995_WSEQ_DELAY48_WIDTH 4 /* WSEQ_DELAY48 - [3:0] */
5953
5954/*
5955 * R12484 (0x30C4) - Write Sequencer 196
5956 */
5957#define WM8995_WSEQ_ADDR49_MASK 0x3FFF /* WSEQ_ADDR49 - [13:0] */
5958#define WM8995_WSEQ_ADDR49_SHIFT 0 /* WSEQ_ADDR49 - [13:0] */
5959#define WM8995_WSEQ_ADDR49_WIDTH 14 /* WSEQ_ADDR49 - [13:0] */
5960
5961/*
5962 * R12485 (0x30C5) - Write Sequencer 197
5963 */
5964#define WM8995_WSEQ_DATA49_MASK 0x00FF /* WSEQ_DATA49 - [7:0] */
5965#define WM8995_WSEQ_DATA49_SHIFT 0 /* WSEQ_DATA49 - [7:0] */
5966#define WM8995_WSEQ_DATA49_WIDTH 8 /* WSEQ_DATA49 - [7:0] */
5967
5968/*
5969 * R12486 (0x30C6) - Write Sequencer 198
5970 */
5971#define WM8995_WSEQ_DATA_WIDTH49_MASK 0x0700 /* WSEQ_DATA_WIDTH49 - [10:8] */
5972#define WM8995_WSEQ_DATA_WIDTH49_SHIFT 8 /* WSEQ_DATA_WIDTH49 - [10:8] */
5973#define WM8995_WSEQ_DATA_WIDTH49_WIDTH 3 /* WSEQ_DATA_WIDTH49 - [10:8] */
5974#define WM8995_WSEQ_DATA_START49_MASK 0x000F /* WSEQ_DATA_START49 - [3:0] */
5975#define WM8995_WSEQ_DATA_START49_SHIFT 0 /* WSEQ_DATA_START49 - [3:0] */
5976#define WM8995_WSEQ_DATA_START49_WIDTH 4 /* WSEQ_DATA_START49 - [3:0] */
5977
5978/*
5979 * R12487 (0x30C7) - Write Sequencer 199
5980 */
5981#define WM8995_WSEQ_EOS49 0x0100 /* WSEQ_EOS49 */
5982#define WM8995_WSEQ_EOS49_MASK 0x0100 /* WSEQ_EOS49 */
5983#define WM8995_WSEQ_EOS49_SHIFT 8 /* WSEQ_EOS49 */
5984#define WM8995_WSEQ_EOS49_WIDTH 1 /* WSEQ_EOS49 */
5985#define WM8995_WSEQ_DELAY49_MASK 0x000F /* WSEQ_DELAY49 - [3:0] */
5986#define WM8995_WSEQ_DELAY49_SHIFT 0 /* WSEQ_DELAY49 - [3:0] */
5987#define WM8995_WSEQ_DELAY49_WIDTH 4 /* WSEQ_DELAY49 - [3:0] */
5988
5989/*
5990 * R12488 (0x30C8) - Write Sequencer 200
5991 */
5992#define WM8995_WSEQ_ADDR50_MASK 0x3FFF /* WSEQ_ADDR50 - [13:0] */
5993#define WM8995_WSEQ_ADDR50_SHIFT 0 /* WSEQ_ADDR50 - [13:0] */
5994#define WM8995_WSEQ_ADDR50_WIDTH 14 /* WSEQ_ADDR50 - [13:0] */
5995
5996/*
5997 * R12489 (0x30C9) - Write Sequencer 201
5998 */
5999#define WM8995_WSEQ_DATA50_MASK 0x00FF /* WSEQ_DATA50 - [7:0] */
6000#define WM8995_WSEQ_DATA50_SHIFT 0 /* WSEQ_DATA50 - [7:0] */
6001#define WM8995_WSEQ_DATA50_WIDTH 8 /* WSEQ_DATA50 - [7:0] */
6002
6003/*
6004 * R12490 (0x30CA) - Write Sequencer 202
6005 */
6006#define WM8995_WSEQ_DATA_WIDTH50_MASK 0x0700 /* WSEQ_DATA_WIDTH50 - [10:8] */
6007#define WM8995_WSEQ_DATA_WIDTH50_SHIFT 8 /* WSEQ_DATA_WIDTH50 - [10:8] */
6008#define WM8995_WSEQ_DATA_WIDTH50_WIDTH 3 /* WSEQ_DATA_WIDTH50 - [10:8] */
6009#define WM8995_WSEQ_DATA_START50_MASK 0x000F /* WSEQ_DATA_START50 - [3:0] */
6010#define WM8995_WSEQ_DATA_START50_SHIFT 0 /* WSEQ_DATA_START50 - [3:0] */
6011#define WM8995_WSEQ_DATA_START50_WIDTH 4 /* WSEQ_DATA_START50 - [3:0] */
6012
6013/*
6014 * R12491 (0x30CB) - Write Sequencer 203
6015 */
6016#define WM8995_WSEQ_EOS50 0x0100 /* WSEQ_EOS50 */
6017#define WM8995_WSEQ_EOS50_MASK 0x0100 /* WSEQ_EOS50 */
6018#define WM8995_WSEQ_EOS50_SHIFT 8 /* WSEQ_EOS50 */
6019#define WM8995_WSEQ_EOS50_WIDTH 1 /* WSEQ_EOS50 */
6020#define WM8995_WSEQ_DELAY50_MASK 0x000F /* WSEQ_DELAY50 - [3:0] */
6021#define WM8995_WSEQ_DELAY50_SHIFT 0 /* WSEQ_DELAY50 - [3:0] */
6022#define WM8995_WSEQ_DELAY50_WIDTH 4 /* WSEQ_DELAY50 - [3:0] */
6023
6024/*
6025 * R12492 (0x30CC) - Write Sequencer 204
6026 */
6027#define WM8995_WSEQ_ADDR51_MASK 0x3FFF /* WSEQ_ADDR51 - [13:0] */
6028#define WM8995_WSEQ_ADDR51_SHIFT 0 /* WSEQ_ADDR51 - [13:0] */
6029#define WM8995_WSEQ_ADDR51_WIDTH 14 /* WSEQ_ADDR51 - [13:0] */
6030
6031/*
6032 * R12493 (0x30CD) - Write Sequencer 205
6033 */
6034#define WM8995_WSEQ_DATA51_MASK 0x00FF /* WSEQ_DATA51 - [7:0] */
6035#define WM8995_WSEQ_DATA51_SHIFT 0 /* WSEQ_DATA51 - [7:0] */
6036#define WM8995_WSEQ_DATA51_WIDTH 8 /* WSEQ_DATA51 - [7:0] */
6037
6038/*
6039 * R12494 (0x30CE) - Write Sequencer 206
6040 */
6041#define WM8995_WSEQ_DATA_WIDTH51_MASK 0x0700 /* WSEQ_DATA_WIDTH51 - [10:8] */
6042#define WM8995_WSEQ_DATA_WIDTH51_SHIFT 8 /* WSEQ_DATA_WIDTH51 - [10:8] */
6043#define WM8995_WSEQ_DATA_WIDTH51_WIDTH 3 /* WSEQ_DATA_WIDTH51 - [10:8] */
6044#define WM8995_WSEQ_DATA_START51_MASK 0x000F /* WSEQ_DATA_START51 - [3:0] */
6045#define WM8995_WSEQ_DATA_START51_SHIFT 0 /* WSEQ_DATA_START51 - [3:0] */
6046#define WM8995_WSEQ_DATA_START51_WIDTH 4 /* WSEQ_DATA_START51 - [3:0] */
6047
6048/*
6049 * R12495 (0x30CF) - Write Sequencer 207
6050 */
6051#define WM8995_WSEQ_EOS51 0x0100 /* WSEQ_EOS51 */
6052#define WM8995_WSEQ_EOS51_MASK 0x0100 /* WSEQ_EOS51 */
6053#define WM8995_WSEQ_EOS51_SHIFT 8 /* WSEQ_EOS51 */
6054#define WM8995_WSEQ_EOS51_WIDTH 1 /* WSEQ_EOS51 */
6055#define WM8995_WSEQ_DELAY51_MASK 0x000F /* WSEQ_DELAY51 - [3:0] */
6056#define WM8995_WSEQ_DELAY51_SHIFT 0 /* WSEQ_DELAY51 - [3:0] */
6057#define WM8995_WSEQ_DELAY51_WIDTH 4 /* WSEQ_DELAY51 - [3:0] */
6058
6059/*
6060 * R12496 (0x30D0) - Write Sequencer 208
6061 */
6062#define WM8995_WSEQ_ADDR52_MASK 0x3FFF /* WSEQ_ADDR52 - [13:0] */
6063#define WM8995_WSEQ_ADDR52_SHIFT 0 /* WSEQ_ADDR52 - [13:0] */
6064#define WM8995_WSEQ_ADDR52_WIDTH 14 /* WSEQ_ADDR52 - [13:0] */
6065
6066/*
6067 * R12497 (0x30D1) - Write Sequencer 209
6068 */
6069#define WM8995_WSEQ_DATA52_MASK 0x00FF /* WSEQ_DATA52 - [7:0] */
6070#define WM8995_WSEQ_DATA52_SHIFT 0 /* WSEQ_DATA52 - [7:0] */
6071#define WM8995_WSEQ_DATA52_WIDTH 8 /* WSEQ_DATA52 - [7:0] */
6072
6073/*
6074 * R12498 (0x30D2) - Write Sequencer 210
6075 */
6076#define WM8995_WSEQ_DATA_WIDTH52_MASK 0x0700 /* WSEQ_DATA_WIDTH52 - [10:8] */
6077#define WM8995_WSEQ_DATA_WIDTH52_SHIFT 8 /* WSEQ_DATA_WIDTH52 - [10:8] */
6078#define WM8995_WSEQ_DATA_WIDTH52_WIDTH 3 /* WSEQ_DATA_WIDTH52 - [10:8] */
6079#define WM8995_WSEQ_DATA_START52_MASK 0x000F /* WSEQ_DATA_START52 - [3:0] */
6080#define WM8995_WSEQ_DATA_START52_SHIFT 0 /* WSEQ_DATA_START52 - [3:0] */
6081#define WM8995_WSEQ_DATA_START52_WIDTH 4 /* WSEQ_DATA_START52 - [3:0] */
6082
6083/*
6084 * R12499 (0x30D3) - Write Sequencer 211
6085 */
6086#define WM8995_WSEQ_EOS52 0x0100 /* WSEQ_EOS52 */
6087#define WM8995_WSEQ_EOS52_MASK 0x0100 /* WSEQ_EOS52 */
6088#define WM8995_WSEQ_EOS52_SHIFT 8 /* WSEQ_EOS52 */
6089#define WM8995_WSEQ_EOS52_WIDTH 1 /* WSEQ_EOS52 */
6090#define WM8995_WSEQ_DELAY52_MASK 0x000F /* WSEQ_DELAY52 - [3:0] */
6091#define WM8995_WSEQ_DELAY52_SHIFT 0 /* WSEQ_DELAY52 - [3:0] */
6092#define WM8995_WSEQ_DELAY52_WIDTH 4 /* WSEQ_DELAY52 - [3:0] */
6093
6094/*
6095 * R12500 (0x30D4) - Write Sequencer 212
6096 */
6097#define WM8995_WSEQ_ADDR53_MASK 0x3FFF /* WSEQ_ADDR53 - [13:0] */
6098#define WM8995_WSEQ_ADDR53_SHIFT 0 /* WSEQ_ADDR53 - [13:0] */
6099#define WM8995_WSEQ_ADDR53_WIDTH 14 /* WSEQ_ADDR53 - [13:0] */
6100
6101/*
6102 * R12501 (0x30D5) - Write Sequencer 213
6103 */
6104#define WM8995_WSEQ_DATA53_MASK 0x00FF /* WSEQ_DATA53 - [7:0] */
6105#define WM8995_WSEQ_DATA53_SHIFT 0 /* WSEQ_DATA53 - [7:0] */
6106#define WM8995_WSEQ_DATA53_WIDTH 8 /* WSEQ_DATA53 - [7:0] */
6107
6108/*
6109 * R12502 (0x30D6) - Write Sequencer 214
6110 */
6111#define WM8995_WSEQ_DATA_WIDTH53_MASK 0x0700 /* WSEQ_DATA_WIDTH53 - [10:8] */
6112#define WM8995_WSEQ_DATA_WIDTH53_SHIFT 8 /* WSEQ_DATA_WIDTH53 - [10:8] */
6113#define WM8995_WSEQ_DATA_WIDTH53_WIDTH 3 /* WSEQ_DATA_WIDTH53 - [10:8] */
6114#define WM8995_WSEQ_DATA_START53_MASK 0x000F /* WSEQ_DATA_START53 - [3:0] */
6115#define WM8995_WSEQ_DATA_START53_SHIFT 0 /* WSEQ_DATA_START53 - [3:0] */
6116#define WM8995_WSEQ_DATA_START53_WIDTH 4 /* WSEQ_DATA_START53 - [3:0] */
6117
6118/*
6119 * R12503 (0x30D7) - Write Sequencer 215
6120 */
6121#define WM8995_WSEQ_EOS53 0x0100 /* WSEQ_EOS53 */
6122#define WM8995_WSEQ_EOS53_MASK 0x0100 /* WSEQ_EOS53 */
6123#define WM8995_WSEQ_EOS53_SHIFT 8 /* WSEQ_EOS53 */
6124#define WM8995_WSEQ_EOS53_WIDTH 1 /* WSEQ_EOS53 */
6125#define WM8995_WSEQ_DELAY53_MASK 0x000F /* WSEQ_DELAY53 - [3:0] */
6126#define WM8995_WSEQ_DELAY53_SHIFT 0 /* WSEQ_DELAY53 - [3:0] */
6127#define WM8995_WSEQ_DELAY53_WIDTH 4 /* WSEQ_DELAY53 - [3:0] */
6128
6129/*
6130 * R12504 (0x30D8) - Write Sequencer 216
6131 */
6132#define WM8995_WSEQ_ADDR54_MASK 0x3FFF /* WSEQ_ADDR54 - [13:0] */
6133#define WM8995_WSEQ_ADDR54_SHIFT 0 /* WSEQ_ADDR54 - [13:0] */
6134#define WM8995_WSEQ_ADDR54_WIDTH 14 /* WSEQ_ADDR54 - [13:0] */
6135
6136/*
6137 * R12505 (0x30D9) - Write Sequencer 217
6138 */
6139#define WM8995_WSEQ_DATA54_MASK 0x00FF /* WSEQ_DATA54 - [7:0] */
6140#define WM8995_WSEQ_DATA54_SHIFT 0 /* WSEQ_DATA54 - [7:0] */
6141#define WM8995_WSEQ_DATA54_WIDTH 8 /* WSEQ_DATA54 - [7:0] */
6142
6143/*
6144 * R12506 (0x30DA) - Write Sequencer 218
6145 */
6146#define WM8995_WSEQ_DATA_WIDTH54_MASK 0x0700 /* WSEQ_DATA_WIDTH54 - [10:8] */
6147#define WM8995_WSEQ_DATA_WIDTH54_SHIFT 8 /* WSEQ_DATA_WIDTH54 - [10:8] */
6148#define WM8995_WSEQ_DATA_WIDTH54_WIDTH 3 /* WSEQ_DATA_WIDTH54 - [10:8] */
6149#define WM8995_WSEQ_DATA_START54_MASK 0x000F /* WSEQ_DATA_START54 - [3:0] */
6150#define WM8995_WSEQ_DATA_START54_SHIFT 0 /* WSEQ_DATA_START54 - [3:0] */
6151#define WM8995_WSEQ_DATA_START54_WIDTH 4 /* WSEQ_DATA_START54 - [3:0] */
6152
6153/*
6154 * R12507 (0x30DB) - Write Sequencer 219
6155 */
6156#define WM8995_WSEQ_EOS54 0x0100 /* WSEQ_EOS54 */
6157#define WM8995_WSEQ_EOS54_MASK 0x0100 /* WSEQ_EOS54 */
6158#define WM8995_WSEQ_EOS54_SHIFT 8 /* WSEQ_EOS54 */
6159#define WM8995_WSEQ_EOS54_WIDTH 1 /* WSEQ_EOS54 */
6160#define WM8995_WSEQ_DELAY54_MASK 0x000F /* WSEQ_DELAY54 - [3:0] */
6161#define WM8995_WSEQ_DELAY54_SHIFT 0 /* WSEQ_DELAY54 - [3:0] */
6162#define WM8995_WSEQ_DELAY54_WIDTH 4 /* WSEQ_DELAY54 - [3:0] */
6163
6164/*
6165 * R12508 (0x30DC) - Write Sequencer 220
6166 */
6167#define WM8995_WSEQ_ADDR55_MASK 0x3FFF /* WSEQ_ADDR55 - [13:0] */
6168#define WM8995_WSEQ_ADDR55_SHIFT 0 /* WSEQ_ADDR55 - [13:0] */
6169#define WM8995_WSEQ_ADDR55_WIDTH 14 /* WSEQ_ADDR55 - [13:0] */
6170
6171/*
6172 * R12509 (0x30DD) - Write Sequencer 221
6173 */
6174#define WM8995_WSEQ_DATA55_MASK 0x00FF /* WSEQ_DATA55 - [7:0] */
6175#define WM8995_WSEQ_DATA55_SHIFT 0 /* WSEQ_DATA55 - [7:0] */
6176#define WM8995_WSEQ_DATA55_WIDTH 8 /* WSEQ_DATA55 - [7:0] */
6177
6178/*
6179 * R12510 (0x30DE) - Write Sequencer 222
6180 */
6181#define WM8995_WSEQ_DATA_WIDTH55_MASK 0x0700 /* WSEQ_DATA_WIDTH55 - [10:8] */
6182#define WM8995_WSEQ_DATA_WIDTH55_SHIFT 8 /* WSEQ_DATA_WIDTH55 - [10:8] */
6183#define WM8995_WSEQ_DATA_WIDTH55_WIDTH 3 /* WSEQ_DATA_WIDTH55 - [10:8] */
6184#define WM8995_WSEQ_DATA_START55_MASK 0x000F /* WSEQ_DATA_START55 - [3:0] */
6185#define WM8995_WSEQ_DATA_START55_SHIFT 0 /* WSEQ_DATA_START55 - [3:0] */
6186#define WM8995_WSEQ_DATA_START55_WIDTH 4 /* WSEQ_DATA_START55 - [3:0] */
6187
6188/*
6189 * R12511 (0x30DF) - Write Sequencer 223
6190 */
6191#define WM8995_WSEQ_EOS55 0x0100 /* WSEQ_EOS55 */
6192#define WM8995_WSEQ_EOS55_MASK 0x0100 /* WSEQ_EOS55 */
6193#define WM8995_WSEQ_EOS55_SHIFT 8 /* WSEQ_EOS55 */
6194#define WM8995_WSEQ_EOS55_WIDTH 1 /* WSEQ_EOS55 */
6195#define WM8995_WSEQ_DELAY55_MASK 0x000F /* WSEQ_DELAY55 - [3:0] */
6196#define WM8995_WSEQ_DELAY55_SHIFT 0 /* WSEQ_DELAY55 - [3:0] */
6197#define WM8995_WSEQ_DELAY55_WIDTH 4 /* WSEQ_DELAY55 - [3:0] */
6198
6199/*
6200 * R12512 (0x30E0) - Write Sequencer 224
6201 */
6202#define WM8995_WSEQ_ADDR56_MASK 0x3FFF /* WSEQ_ADDR56 - [13:0] */
6203#define WM8995_WSEQ_ADDR56_SHIFT 0 /* WSEQ_ADDR56 - [13:0] */
6204#define WM8995_WSEQ_ADDR56_WIDTH 14 /* WSEQ_ADDR56 - [13:0] */
6205
6206/*
6207 * R12513 (0x30E1) - Write Sequencer 225
6208 */
6209#define WM8995_WSEQ_DATA56_MASK 0x00FF /* WSEQ_DATA56 - [7:0] */
6210#define WM8995_WSEQ_DATA56_SHIFT 0 /* WSEQ_DATA56 - [7:0] */
6211#define WM8995_WSEQ_DATA56_WIDTH 8 /* WSEQ_DATA56 - [7:0] */
6212
6213/*
6214 * R12514 (0x30E2) - Write Sequencer 226
6215 */
6216#define WM8995_WSEQ_DATA_WIDTH56_MASK 0x0700 /* WSEQ_DATA_WIDTH56 - [10:8] */
6217#define WM8995_WSEQ_DATA_WIDTH56_SHIFT 8 /* WSEQ_DATA_WIDTH56 - [10:8] */
6218#define WM8995_WSEQ_DATA_WIDTH56_WIDTH 3 /* WSEQ_DATA_WIDTH56 - [10:8] */
6219#define WM8995_WSEQ_DATA_START56_MASK 0x000F /* WSEQ_DATA_START56 - [3:0] */
6220#define WM8995_WSEQ_DATA_START56_SHIFT 0 /* WSEQ_DATA_START56 - [3:0] */
6221#define WM8995_WSEQ_DATA_START56_WIDTH 4 /* WSEQ_DATA_START56 - [3:0] */
6222
6223/*
6224 * R12515 (0x30E3) - Write Sequencer 227
6225 */
6226#define WM8995_WSEQ_EOS56 0x0100 /* WSEQ_EOS56 */
6227#define WM8995_WSEQ_EOS56_MASK 0x0100 /* WSEQ_EOS56 */
6228#define WM8995_WSEQ_EOS56_SHIFT 8 /* WSEQ_EOS56 */
6229#define WM8995_WSEQ_EOS56_WIDTH 1 /* WSEQ_EOS56 */
6230#define WM8995_WSEQ_DELAY56_MASK 0x000F /* WSEQ_DELAY56 - [3:0] */
6231#define WM8995_WSEQ_DELAY56_SHIFT 0 /* WSEQ_DELAY56 - [3:0] */
6232#define WM8995_WSEQ_DELAY56_WIDTH 4 /* WSEQ_DELAY56 - [3:0] */
6233
6234/*
6235 * R12516 (0x30E4) - Write Sequencer 228
6236 */
6237#define WM8995_WSEQ_ADDR57_MASK 0x3FFF /* WSEQ_ADDR57 - [13:0] */
6238#define WM8995_WSEQ_ADDR57_SHIFT 0 /* WSEQ_ADDR57 - [13:0] */
6239#define WM8995_WSEQ_ADDR57_WIDTH 14 /* WSEQ_ADDR57 - [13:0] */
6240
6241/*
6242 * R12517 (0x30E5) - Write Sequencer 229
6243 */
6244#define WM8995_WSEQ_DATA57_MASK 0x00FF /* WSEQ_DATA57 - [7:0] */
6245#define WM8995_WSEQ_DATA57_SHIFT 0 /* WSEQ_DATA57 - [7:0] */
6246#define WM8995_WSEQ_DATA57_WIDTH 8 /* WSEQ_DATA57 - [7:0] */
6247
6248/*
6249 * R12518 (0x30E6) - Write Sequencer 230
6250 */
6251#define WM8995_WSEQ_DATA_WIDTH57_MASK 0x0700 /* WSEQ_DATA_WIDTH57 - [10:8] */
6252#define WM8995_WSEQ_DATA_WIDTH57_SHIFT 8 /* WSEQ_DATA_WIDTH57 - [10:8] */
6253#define WM8995_WSEQ_DATA_WIDTH57_WIDTH 3 /* WSEQ_DATA_WIDTH57 - [10:8] */
6254#define WM8995_WSEQ_DATA_START57_MASK 0x000F /* WSEQ_DATA_START57 - [3:0] */
6255#define WM8995_WSEQ_DATA_START57_SHIFT 0 /* WSEQ_DATA_START57 - [3:0] */
6256#define WM8995_WSEQ_DATA_START57_WIDTH 4 /* WSEQ_DATA_START57 - [3:0] */
6257
6258/*
6259 * R12519 (0x30E7) - Write Sequencer 231
6260 */
6261#define WM8995_WSEQ_EOS57 0x0100 /* WSEQ_EOS57 */
6262#define WM8995_WSEQ_EOS57_MASK 0x0100 /* WSEQ_EOS57 */
6263#define WM8995_WSEQ_EOS57_SHIFT 8 /* WSEQ_EOS57 */
6264#define WM8995_WSEQ_EOS57_WIDTH 1 /* WSEQ_EOS57 */
6265#define WM8995_WSEQ_DELAY57_MASK 0x000F /* WSEQ_DELAY57 - [3:0] */
6266#define WM8995_WSEQ_DELAY57_SHIFT 0 /* WSEQ_DELAY57 - [3:0] */
6267#define WM8995_WSEQ_DELAY57_WIDTH 4 /* WSEQ_DELAY57 - [3:0] */
6268
6269/*
6270 * R12520 (0x30E8) - Write Sequencer 232
6271 */
6272#define WM8995_WSEQ_ADDR58_MASK 0x3FFF /* WSEQ_ADDR58 - [13:0] */
6273#define WM8995_WSEQ_ADDR58_SHIFT 0 /* WSEQ_ADDR58 - [13:0] */
6274#define WM8995_WSEQ_ADDR58_WIDTH 14 /* WSEQ_ADDR58 - [13:0] */
6275
6276/*
6277 * R12521 (0x30E9) - Write Sequencer 233
6278 */
6279#define WM8995_WSEQ_DATA58_MASK 0x00FF /* WSEQ_DATA58 - [7:0] */
6280#define WM8995_WSEQ_DATA58_SHIFT 0 /* WSEQ_DATA58 - [7:0] */
6281#define WM8995_WSEQ_DATA58_WIDTH 8 /* WSEQ_DATA58 - [7:0] */
6282
6283/*
6284 * R12522 (0x30EA) - Write Sequencer 234
6285 */
6286#define WM8995_WSEQ_DATA_WIDTH58_MASK 0x0700 /* WSEQ_DATA_WIDTH58 - [10:8] */
6287#define WM8995_WSEQ_DATA_WIDTH58_SHIFT 8 /* WSEQ_DATA_WIDTH58 - [10:8] */
6288#define WM8995_WSEQ_DATA_WIDTH58_WIDTH 3 /* WSEQ_DATA_WIDTH58 - [10:8] */
6289#define WM8995_WSEQ_DATA_START58_MASK 0x000F /* WSEQ_DATA_START58 - [3:0] */
6290#define WM8995_WSEQ_DATA_START58_SHIFT 0 /* WSEQ_DATA_START58 - [3:0] */
6291#define WM8995_WSEQ_DATA_START58_WIDTH 4 /* WSEQ_DATA_START58 - [3:0] */
6292
6293/*
6294 * R12523 (0x30EB) - Write Sequencer 235
6295 */
6296#define WM8995_WSEQ_EOS58 0x0100 /* WSEQ_EOS58 */
6297#define WM8995_WSEQ_EOS58_MASK 0x0100 /* WSEQ_EOS58 */
6298#define WM8995_WSEQ_EOS58_SHIFT 8 /* WSEQ_EOS58 */
6299#define WM8995_WSEQ_EOS58_WIDTH 1 /* WSEQ_EOS58 */
6300#define WM8995_WSEQ_DELAY58_MASK 0x000F /* WSEQ_DELAY58 - [3:0] */
6301#define WM8995_WSEQ_DELAY58_SHIFT 0 /* WSEQ_DELAY58 - [3:0] */
6302#define WM8995_WSEQ_DELAY58_WIDTH 4 /* WSEQ_DELAY58 - [3:0] */
6303
6304/*
6305 * R12524 (0x30EC) - Write Sequencer 236
6306 */
6307#define WM8995_WSEQ_ADDR59_MASK 0x3FFF /* WSEQ_ADDR59 - [13:0] */
6308#define WM8995_WSEQ_ADDR59_SHIFT 0 /* WSEQ_ADDR59 - [13:0] */
6309#define WM8995_WSEQ_ADDR59_WIDTH 14 /* WSEQ_ADDR59 - [13:0] */
6310
6311/*
6312 * R12525 (0x30ED) - Write Sequencer 237
6313 */
6314#define WM8995_WSEQ_DATA59_MASK 0x00FF /* WSEQ_DATA59 - [7:0] */
6315#define WM8995_WSEQ_DATA59_SHIFT 0 /* WSEQ_DATA59 - [7:0] */
6316#define WM8995_WSEQ_DATA59_WIDTH 8 /* WSEQ_DATA59 - [7:0] */
6317
6318/*
6319 * R12526 (0x30EE) - Write Sequencer 238
6320 */
6321#define WM8995_WSEQ_DATA_WIDTH59_MASK 0x0700 /* WSEQ_DATA_WIDTH59 - [10:8] */
6322#define WM8995_WSEQ_DATA_WIDTH59_SHIFT 8 /* WSEQ_DATA_WIDTH59 - [10:8] */
6323#define WM8995_WSEQ_DATA_WIDTH59_WIDTH 3 /* WSEQ_DATA_WIDTH59 - [10:8] */
6324#define WM8995_WSEQ_DATA_START59_MASK 0x000F /* WSEQ_DATA_START59 - [3:0] */
6325#define WM8995_WSEQ_DATA_START59_SHIFT 0 /* WSEQ_DATA_START59 - [3:0] */
6326#define WM8995_WSEQ_DATA_START59_WIDTH 4 /* WSEQ_DATA_START59 - [3:0] */
6327
6328/*
6329 * R12527 (0x30EF) - Write Sequencer 239
6330 */
6331#define WM8995_WSEQ_EOS59 0x0100 /* WSEQ_EOS59 */
6332#define WM8995_WSEQ_EOS59_MASK 0x0100 /* WSEQ_EOS59 */
6333#define WM8995_WSEQ_EOS59_SHIFT 8 /* WSEQ_EOS59 */
6334#define WM8995_WSEQ_EOS59_WIDTH 1 /* WSEQ_EOS59 */
6335#define WM8995_WSEQ_DELAY59_MASK 0x000F /* WSEQ_DELAY59 - [3:0] */
6336#define WM8995_WSEQ_DELAY59_SHIFT 0 /* WSEQ_DELAY59 - [3:0] */
6337#define WM8995_WSEQ_DELAY59_WIDTH 4 /* WSEQ_DELAY59 - [3:0] */
6338
6339/*
6340 * R12528 (0x30F0) - Write Sequencer 240
6341 */
6342#define WM8995_WSEQ_ADDR60_MASK 0x3FFF /* WSEQ_ADDR60 - [13:0] */
6343#define WM8995_WSEQ_ADDR60_SHIFT 0 /* WSEQ_ADDR60 - [13:0] */
6344#define WM8995_WSEQ_ADDR60_WIDTH 14 /* WSEQ_ADDR60 - [13:0] */
6345
6346/*
6347 * R12529 (0x30F1) - Write Sequencer 241
6348 */
6349#define WM8995_WSEQ_DATA60_MASK 0x00FF /* WSEQ_DATA60 - [7:0] */
6350#define WM8995_WSEQ_DATA60_SHIFT 0 /* WSEQ_DATA60 - [7:0] */
6351#define WM8995_WSEQ_DATA60_WIDTH 8 /* WSEQ_DATA60 - [7:0] */
6352
6353/*
6354 * R12530 (0x30F2) - Write Sequencer 242
6355 */
6356#define WM8995_WSEQ_DATA_WIDTH60_MASK 0x0700 /* WSEQ_DATA_WIDTH60 - [10:8] */
6357#define WM8995_WSEQ_DATA_WIDTH60_SHIFT 8 /* WSEQ_DATA_WIDTH60 - [10:8] */
6358#define WM8995_WSEQ_DATA_WIDTH60_WIDTH 3 /* WSEQ_DATA_WIDTH60 - [10:8] */
6359#define WM8995_WSEQ_DATA_START60_MASK 0x000F /* WSEQ_DATA_START60 - [3:0] */
6360#define WM8995_WSEQ_DATA_START60_SHIFT 0 /* WSEQ_DATA_START60 - [3:0] */
6361#define WM8995_WSEQ_DATA_START60_WIDTH 4 /* WSEQ_DATA_START60 - [3:0] */
6362
6363/*
6364 * R12531 (0x30F3) - Write Sequencer 243
6365 */
6366#define WM8995_WSEQ_EOS60 0x0100 /* WSEQ_EOS60 */
6367#define WM8995_WSEQ_EOS60_MASK 0x0100 /* WSEQ_EOS60 */
6368#define WM8995_WSEQ_EOS60_SHIFT 8 /* WSEQ_EOS60 */
6369#define WM8995_WSEQ_EOS60_WIDTH 1 /* WSEQ_EOS60 */
6370#define WM8995_WSEQ_DELAY60_MASK 0x000F /* WSEQ_DELAY60 - [3:0] */
6371#define WM8995_WSEQ_DELAY60_SHIFT 0 /* WSEQ_DELAY60 - [3:0] */
6372#define WM8995_WSEQ_DELAY60_WIDTH 4 /* WSEQ_DELAY60 - [3:0] */
6373
6374/*
6375 * R12532 (0x30F4) - Write Sequencer 244
6376 */
6377#define WM8995_WSEQ_ADDR61_MASK 0x3FFF /* WSEQ_ADDR61 - [13:0] */
6378#define WM8995_WSEQ_ADDR61_SHIFT 0 /* WSEQ_ADDR61 - [13:0] */
6379#define WM8995_WSEQ_ADDR61_WIDTH 14 /* WSEQ_ADDR61 - [13:0] */
6380
6381/*
6382 * R12533 (0x30F5) - Write Sequencer 245
6383 */
6384#define WM8995_WSEQ_DATA61_MASK 0x00FF /* WSEQ_DATA61 - [7:0] */
6385#define WM8995_WSEQ_DATA61_SHIFT 0 /* WSEQ_DATA61 - [7:0] */
6386#define WM8995_WSEQ_DATA61_WIDTH 8 /* WSEQ_DATA61 - [7:0] */
6387
6388/*
6389 * R12534 (0x30F6) - Write Sequencer 246
6390 */
6391#define WM8995_WSEQ_DATA_WIDTH61_MASK 0x0700 /* WSEQ_DATA_WIDTH61 - [10:8] */
6392#define WM8995_WSEQ_DATA_WIDTH61_SHIFT 8 /* WSEQ_DATA_WIDTH61 - [10:8] */
6393#define WM8995_WSEQ_DATA_WIDTH61_WIDTH 3 /* WSEQ_DATA_WIDTH61 - [10:8] */
6394#define WM8995_WSEQ_DATA_START61_MASK 0x000F /* WSEQ_DATA_START61 - [3:0] */
6395#define WM8995_WSEQ_DATA_START61_SHIFT 0 /* WSEQ_DATA_START61 - [3:0] */
6396#define WM8995_WSEQ_DATA_START61_WIDTH 4 /* WSEQ_DATA_START61 - [3:0] */
6397
6398/*
6399 * R12535 (0x30F7) - Write Sequencer 247
6400 */
6401#define WM8995_WSEQ_EOS61 0x0100 /* WSEQ_EOS61 */
6402#define WM8995_WSEQ_EOS61_MASK 0x0100 /* WSEQ_EOS61 */
6403#define WM8995_WSEQ_EOS61_SHIFT 8 /* WSEQ_EOS61 */
6404#define WM8995_WSEQ_EOS61_WIDTH 1 /* WSEQ_EOS61 */
6405#define WM8995_WSEQ_DELAY61_MASK 0x000F /* WSEQ_DELAY61 - [3:0] */
6406#define WM8995_WSEQ_DELAY61_SHIFT 0 /* WSEQ_DELAY61 - [3:0] */
6407#define WM8995_WSEQ_DELAY61_WIDTH 4 /* WSEQ_DELAY61 - [3:0] */
6408
6409/*
6410 * R12536 (0x30F8) - Write Sequencer 248
6411 */
6412#define WM8995_WSEQ_ADDR62_MASK 0x3FFF /* WSEQ_ADDR62 - [13:0] */
6413#define WM8995_WSEQ_ADDR62_SHIFT 0 /* WSEQ_ADDR62 - [13:0] */
6414#define WM8995_WSEQ_ADDR62_WIDTH 14 /* WSEQ_ADDR62 - [13:0] */
6415
6416/*
6417 * R12537 (0x30F9) - Write Sequencer 249
6418 */
6419#define WM8995_WSEQ_DATA62_MASK 0x00FF /* WSEQ_DATA62 - [7:0] */
6420#define WM8995_WSEQ_DATA62_SHIFT 0 /* WSEQ_DATA62 - [7:0] */
6421#define WM8995_WSEQ_DATA62_WIDTH 8 /* WSEQ_DATA62 - [7:0] */
6422
6423/*
6424 * R12538 (0x30FA) - Write Sequencer 250
6425 */
6426#define WM8995_WSEQ_DATA_WIDTH62_MASK 0x0700 /* WSEQ_DATA_WIDTH62 - [10:8] */
6427#define WM8995_WSEQ_DATA_WIDTH62_SHIFT 8 /* WSEQ_DATA_WIDTH62 - [10:8] */
6428#define WM8995_WSEQ_DATA_WIDTH62_WIDTH 3 /* WSEQ_DATA_WIDTH62 - [10:8] */
6429#define WM8995_WSEQ_DATA_START62_MASK 0x000F /* WSEQ_DATA_START62 - [3:0] */
6430#define WM8995_WSEQ_DATA_START62_SHIFT 0 /* WSEQ_DATA_START62 - [3:0] */
6431#define WM8995_WSEQ_DATA_START62_WIDTH 4 /* WSEQ_DATA_START62 - [3:0] */
6432
6433/*
6434 * R12539 (0x30FB) - Write Sequencer 251
6435 */
6436#define WM8995_WSEQ_EOS62 0x0100 /* WSEQ_EOS62 */
6437#define WM8995_WSEQ_EOS62_MASK 0x0100 /* WSEQ_EOS62 */
6438#define WM8995_WSEQ_EOS62_SHIFT 8 /* WSEQ_EOS62 */
6439#define WM8995_WSEQ_EOS62_WIDTH 1 /* WSEQ_EOS62 */
6440#define WM8995_WSEQ_DELAY62_MASK 0x000F /* WSEQ_DELAY62 - [3:0] */
6441#define WM8995_WSEQ_DELAY62_SHIFT 0 /* WSEQ_DELAY62 - [3:0] */
6442#define WM8995_WSEQ_DELAY62_WIDTH 4 /* WSEQ_DELAY62 - [3:0] */
6443
6444/*
6445 * R12540 (0x30FC) - Write Sequencer 252
6446 */
6447#define WM8995_WSEQ_ADDR63_MASK 0x3FFF /* WSEQ_ADDR63 - [13:0] */
6448#define WM8995_WSEQ_ADDR63_SHIFT 0 /* WSEQ_ADDR63 - [13:0] */
6449#define WM8995_WSEQ_ADDR63_WIDTH 14 /* WSEQ_ADDR63 - [13:0] */
6450
6451/*
6452 * R12541 (0x30FD) - Write Sequencer 253
6453 */
6454#define WM8995_WSEQ_DATA63_MASK 0x00FF /* WSEQ_DATA63 - [7:0] */
6455#define WM8995_WSEQ_DATA63_SHIFT 0 /* WSEQ_DATA63 - [7:0] */
6456#define WM8995_WSEQ_DATA63_WIDTH 8 /* WSEQ_DATA63 - [7:0] */
6457
6458/*
6459 * R12542 (0x30FE) - Write Sequencer 254
6460 */
6461#define WM8995_WSEQ_DATA_WIDTH63_MASK 0x0700 /* WSEQ_DATA_WIDTH63 - [10:8] */
6462#define WM8995_WSEQ_DATA_WIDTH63_SHIFT 8 /* WSEQ_DATA_WIDTH63 - [10:8] */
6463#define WM8995_WSEQ_DATA_WIDTH63_WIDTH 3 /* WSEQ_DATA_WIDTH63 - [10:8] */
6464#define WM8995_WSEQ_DATA_START63_MASK 0x000F /* WSEQ_DATA_START63 - [3:0] */
6465#define WM8995_WSEQ_DATA_START63_SHIFT 0 /* WSEQ_DATA_START63 - [3:0] */
6466#define WM8995_WSEQ_DATA_START63_WIDTH 4 /* WSEQ_DATA_START63 - [3:0] */
6467
6468/*
6469 * R12543 (0x30FF) - Write Sequencer 255
6470 */
6471#define WM8995_WSEQ_EOS63 0x0100 /* WSEQ_EOS63 */
6472#define WM8995_WSEQ_EOS63_MASK 0x0100 /* WSEQ_EOS63 */
6473#define WM8995_WSEQ_EOS63_SHIFT 8 /* WSEQ_EOS63 */
6474#define WM8995_WSEQ_EOS63_WIDTH 1 /* WSEQ_EOS63 */
6475#define WM8995_WSEQ_DELAY63_MASK 0x000F /* WSEQ_DELAY63 - [3:0] */
6476#define WM8995_WSEQ_DELAY63_SHIFT 0 /* WSEQ_DELAY63 - [3:0] */
6477#define WM8995_WSEQ_DELAY63_WIDTH 4 /* WSEQ_DELAY63 - [3:0] */
6478
6479/*
6480 * R12544 (0x3100) - Write Sequencer 256
6481 */
6482#define WM8995_WSEQ_ADDR64_MASK 0x3FFF /* WSEQ_ADDR64 - [13:0] */
6483#define WM8995_WSEQ_ADDR64_SHIFT 0 /* WSEQ_ADDR64 - [13:0] */
6484#define WM8995_WSEQ_ADDR64_WIDTH 14 /* WSEQ_ADDR64 - [13:0] */
6485
6486/*
6487 * R12545 (0x3101) - Write Sequencer 257
6488 */
6489#define WM8995_WSEQ_DATA64_MASK 0x00FF /* WSEQ_DATA64 - [7:0] */
6490#define WM8995_WSEQ_DATA64_SHIFT 0 /* WSEQ_DATA64 - [7:0] */
6491#define WM8995_WSEQ_DATA64_WIDTH 8 /* WSEQ_DATA64 - [7:0] */
6492
6493/*
6494 * R12546 (0x3102) - Write Sequencer 258
6495 */
6496#define WM8995_WSEQ_DATA_WIDTH64_MASK 0x0700 /* WSEQ_DATA_WIDTH64 - [10:8] */
6497#define WM8995_WSEQ_DATA_WIDTH64_SHIFT 8 /* WSEQ_DATA_WIDTH64 - [10:8] */
6498#define WM8995_WSEQ_DATA_WIDTH64_WIDTH 3 /* WSEQ_DATA_WIDTH64 - [10:8] */
6499#define WM8995_WSEQ_DATA_START64_MASK 0x000F /* WSEQ_DATA_START64 - [3:0] */
6500#define WM8995_WSEQ_DATA_START64_SHIFT 0 /* WSEQ_DATA_START64 - [3:0] */
6501#define WM8995_WSEQ_DATA_START64_WIDTH 4 /* WSEQ_DATA_START64 - [3:0] */
6502
6503/*
6504 * R12547 (0x3103) - Write Sequencer 259
6505 */
6506#define WM8995_WSEQ_EOS64 0x0100 /* WSEQ_EOS64 */
6507#define WM8995_WSEQ_EOS64_MASK 0x0100 /* WSEQ_EOS64 */
6508#define WM8995_WSEQ_EOS64_SHIFT 8 /* WSEQ_EOS64 */
6509#define WM8995_WSEQ_EOS64_WIDTH 1 /* WSEQ_EOS64 */
6510#define WM8995_WSEQ_DELAY64_MASK 0x000F /* WSEQ_DELAY64 - [3:0] */
6511#define WM8995_WSEQ_DELAY64_SHIFT 0 /* WSEQ_DELAY64 - [3:0] */
6512#define WM8995_WSEQ_DELAY64_WIDTH 4 /* WSEQ_DELAY64 - [3:0] */
6513
6514/*
6515 * R12548 (0x3104) - Write Sequencer 260
6516 */
6517#define WM8995_WSEQ_ADDR65_MASK 0x3FFF /* WSEQ_ADDR65 - [13:0] */
6518#define WM8995_WSEQ_ADDR65_SHIFT 0 /* WSEQ_ADDR65 - [13:0] */
6519#define WM8995_WSEQ_ADDR65_WIDTH 14 /* WSEQ_ADDR65 - [13:0] */
6520
6521/*
6522 * R12549 (0x3105) - Write Sequencer 261
6523 */
6524#define WM8995_WSEQ_DATA65_MASK 0x00FF /* WSEQ_DATA65 - [7:0] */
6525#define WM8995_WSEQ_DATA65_SHIFT 0 /* WSEQ_DATA65 - [7:0] */
6526#define WM8995_WSEQ_DATA65_WIDTH 8 /* WSEQ_DATA65 - [7:0] */
6527
6528/*
6529 * R12550 (0x3106) - Write Sequencer 262
6530 */
6531#define WM8995_WSEQ_DATA_WIDTH65_MASK 0x0700 /* WSEQ_DATA_WIDTH65 - [10:8] */
6532#define WM8995_WSEQ_DATA_WIDTH65_SHIFT 8 /* WSEQ_DATA_WIDTH65 - [10:8] */
6533#define WM8995_WSEQ_DATA_WIDTH65_WIDTH 3 /* WSEQ_DATA_WIDTH65 - [10:8] */
6534#define WM8995_WSEQ_DATA_START65_MASK 0x000F /* WSEQ_DATA_START65 - [3:0] */
6535#define WM8995_WSEQ_DATA_START65_SHIFT 0 /* WSEQ_DATA_START65 - [3:0] */
6536#define WM8995_WSEQ_DATA_START65_WIDTH 4 /* WSEQ_DATA_START65 - [3:0] */
6537
6538/*
6539 * R12551 (0x3107) - Write Sequencer 263
6540 */
6541#define WM8995_WSEQ_EOS65 0x0100 /* WSEQ_EOS65 */
6542#define WM8995_WSEQ_EOS65_MASK 0x0100 /* WSEQ_EOS65 */
6543#define WM8995_WSEQ_EOS65_SHIFT 8 /* WSEQ_EOS65 */
6544#define WM8995_WSEQ_EOS65_WIDTH 1 /* WSEQ_EOS65 */
6545#define WM8995_WSEQ_DELAY65_MASK 0x000F /* WSEQ_DELAY65 - [3:0] */
6546#define WM8995_WSEQ_DELAY65_SHIFT 0 /* WSEQ_DELAY65 - [3:0] */
6547#define WM8995_WSEQ_DELAY65_WIDTH 4 /* WSEQ_DELAY65 - [3:0] */
6548
6549/*
6550 * R12552 (0x3108) - Write Sequencer 264
6551 */
6552#define WM8995_WSEQ_ADDR66_MASK 0x3FFF /* WSEQ_ADDR66 - [13:0] */
6553#define WM8995_WSEQ_ADDR66_SHIFT 0 /* WSEQ_ADDR66 - [13:0] */
6554#define WM8995_WSEQ_ADDR66_WIDTH 14 /* WSEQ_ADDR66 - [13:0] */
6555
6556/*
6557 * R12553 (0x3109) - Write Sequencer 265
6558 */
6559#define WM8995_WSEQ_DATA66_MASK 0x00FF /* WSEQ_DATA66 - [7:0] */
6560#define WM8995_WSEQ_DATA66_SHIFT 0 /* WSEQ_DATA66 - [7:0] */
6561#define WM8995_WSEQ_DATA66_WIDTH 8 /* WSEQ_DATA66 - [7:0] */
6562
6563/*
6564 * R12554 (0x310A) - Write Sequencer 266
6565 */
6566#define WM8995_WSEQ_DATA_WIDTH66_MASK 0x0700 /* WSEQ_DATA_WIDTH66 - [10:8] */
6567#define WM8995_WSEQ_DATA_WIDTH66_SHIFT 8 /* WSEQ_DATA_WIDTH66 - [10:8] */
6568#define WM8995_WSEQ_DATA_WIDTH66_WIDTH 3 /* WSEQ_DATA_WIDTH66 - [10:8] */
6569#define WM8995_WSEQ_DATA_START66_MASK 0x000F /* WSEQ_DATA_START66 - [3:0] */
6570#define WM8995_WSEQ_DATA_START66_SHIFT 0 /* WSEQ_DATA_START66 - [3:0] */
6571#define WM8995_WSEQ_DATA_START66_WIDTH 4 /* WSEQ_DATA_START66 - [3:0] */
6572
6573/*
6574 * R12555 (0x310B) - Write Sequencer 267
6575 */
6576#define WM8995_WSEQ_EOS66 0x0100 /* WSEQ_EOS66 */
6577#define WM8995_WSEQ_EOS66_MASK 0x0100 /* WSEQ_EOS66 */
6578#define WM8995_WSEQ_EOS66_SHIFT 8 /* WSEQ_EOS66 */
6579#define WM8995_WSEQ_EOS66_WIDTH 1 /* WSEQ_EOS66 */
6580#define WM8995_WSEQ_DELAY66_MASK 0x000F /* WSEQ_DELAY66 - [3:0] */
6581#define WM8995_WSEQ_DELAY66_SHIFT 0 /* WSEQ_DELAY66 - [3:0] */
6582#define WM8995_WSEQ_DELAY66_WIDTH 4 /* WSEQ_DELAY66 - [3:0] */
6583
6584/*
6585 * R12556 (0x310C) - Write Sequencer 268
6586 */
6587#define WM8995_WSEQ_ADDR67_MASK 0x3FFF /* WSEQ_ADDR67 - [13:0] */
6588#define WM8995_WSEQ_ADDR67_SHIFT 0 /* WSEQ_ADDR67 - [13:0] */
6589#define WM8995_WSEQ_ADDR67_WIDTH 14 /* WSEQ_ADDR67 - [13:0] */
6590
6591/*
6592 * R12557 (0x310D) - Write Sequencer 269
6593 */
6594#define WM8995_WSEQ_DATA67_MASK 0x00FF /* WSEQ_DATA67 - [7:0] */
6595#define WM8995_WSEQ_DATA67_SHIFT 0 /* WSEQ_DATA67 - [7:0] */
6596#define WM8995_WSEQ_DATA67_WIDTH 8 /* WSEQ_DATA67 - [7:0] */
6597
6598/*
6599 * R12558 (0x310E) - Write Sequencer 270
6600 */
6601#define WM8995_WSEQ_DATA_WIDTH67_MASK 0x0700 /* WSEQ_DATA_WIDTH67 - [10:8] */
6602#define WM8995_WSEQ_DATA_WIDTH67_SHIFT 8 /* WSEQ_DATA_WIDTH67 - [10:8] */
6603#define WM8995_WSEQ_DATA_WIDTH67_WIDTH 3 /* WSEQ_DATA_WIDTH67 - [10:8] */
6604#define WM8995_WSEQ_DATA_START67_MASK 0x000F /* WSEQ_DATA_START67 - [3:0] */
6605#define WM8995_WSEQ_DATA_START67_SHIFT 0 /* WSEQ_DATA_START67 - [3:0] */
6606#define WM8995_WSEQ_DATA_START67_WIDTH 4 /* WSEQ_DATA_START67 - [3:0] */
6607
6608/*
6609 * R12559 (0x310F) - Write Sequencer 271
6610 */
6611#define WM8995_WSEQ_EOS67 0x0100 /* WSEQ_EOS67 */
6612#define WM8995_WSEQ_EOS67_MASK 0x0100 /* WSEQ_EOS67 */
6613#define WM8995_WSEQ_EOS67_SHIFT 8 /* WSEQ_EOS67 */
6614#define WM8995_WSEQ_EOS67_WIDTH 1 /* WSEQ_EOS67 */
6615#define WM8995_WSEQ_DELAY67_MASK 0x000F /* WSEQ_DELAY67 - [3:0] */
6616#define WM8995_WSEQ_DELAY67_SHIFT 0 /* WSEQ_DELAY67 - [3:0] */
6617#define WM8995_WSEQ_DELAY67_WIDTH 4 /* WSEQ_DELAY67 - [3:0] */
6618
6619/*
6620 * R12560 (0x3110) - Write Sequencer 272
6621 */
6622#define WM8995_WSEQ_ADDR68_MASK 0x3FFF /* WSEQ_ADDR68 - [13:0] */
6623#define WM8995_WSEQ_ADDR68_SHIFT 0 /* WSEQ_ADDR68 - [13:0] */
6624#define WM8995_WSEQ_ADDR68_WIDTH 14 /* WSEQ_ADDR68 - [13:0] */
6625
6626/*
6627 * R12561 (0x3111) - Write Sequencer 273
6628 */
6629#define WM8995_WSEQ_DATA68_MASK 0x00FF /* WSEQ_DATA68 - [7:0] */
6630#define WM8995_WSEQ_DATA68_SHIFT 0 /* WSEQ_DATA68 - [7:0] */
6631#define WM8995_WSEQ_DATA68_WIDTH 8 /* WSEQ_DATA68 - [7:0] */
6632
6633/*
6634 * R12562 (0x3112) - Write Sequencer 274
6635 */
6636#define WM8995_WSEQ_DATA_WIDTH68_MASK 0x0700 /* WSEQ_DATA_WIDTH68 - [10:8] */
6637#define WM8995_WSEQ_DATA_WIDTH68_SHIFT 8 /* WSEQ_DATA_WIDTH68 - [10:8] */
6638#define WM8995_WSEQ_DATA_WIDTH68_WIDTH 3 /* WSEQ_DATA_WIDTH68 - [10:8] */
6639#define WM8995_WSEQ_DATA_START68_MASK 0x000F /* WSEQ_DATA_START68 - [3:0] */
6640#define WM8995_WSEQ_DATA_START68_SHIFT 0 /* WSEQ_DATA_START68 - [3:0] */
6641#define WM8995_WSEQ_DATA_START68_WIDTH 4 /* WSEQ_DATA_START68 - [3:0] */
6642
6643/*
6644 * R12563 (0x3113) - Write Sequencer 275
6645 */
6646#define WM8995_WSEQ_EOS68 0x0100 /* WSEQ_EOS68 */
6647#define WM8995_WSEQ_EOS68_MASK 0x0100 /* WSEQ_EOS68 */
6648#define WM8995_WSEQ_EOS68_SHIFT 8 /* WSEQ_EOS68 */
6649#define WM8995_WSEQ_EOS68_WIDTH 1 /* WSEQ_EOS68 */
6650#define WM8995_WSEQ_DELAY68_MASK 0x000F /* WSEQ_DELAY68 - [3:0] */
6651#define WM8995_WSEQ_DELAY68_SHIFT 0 /* WSEQ_DELAY68 - [3:0] */
6652#define WM8995_WSEQ_DELAY68_WIDTH 4 /* WSEQ_DELAY68 - [3:0] */
6653
6654/*
6655 * R12564 (0x3114) - Write Sequencer 276
6656 */
6657#define WM8995_WSEQ_ADDR69_MASK 0x3FFF /* WSEQ_ADDR69 - [13:0] */
6658#define WM8995_WSEQ_ADDR69_SHIFT 0 /* WSEQ_ADDR69 - [13:0] */
6659#define WM8995_WSEQ_ADDR69_WIDTH 14 /* WSEQ_ADDR69 - [13:0] */
6660
6661/*
6662 * R12565 (0x3115) - Write Sequencer 277
6663 */
6664#define WM8995_WSEQ_DATA69_MASK 0x00FF /* WSEQ_DATA69 - [7:0] */
6665#define WM8995_WSEQ_DATA69_SHIFT 0 /* WSEQ_DATA69 - [7:0] */
6666#define WM8995_WSEQ_DATA69_WIDTH 8 /* WSEQ_DATA69 - [7:0] */
6667
6668/*
6669 * R12566 (0x3116) - Write Sequencer 278
6670 */
6671#define WM8995_WSEQ_DATA_WIDTH69_MASK 0x0700 /* WSEQ_DATA_WIDTH69 - [10:8] */
6672#define WM8995_WSEQ_DATA_WIDTH69_SHIFT 8 /* WSEQ_DATA_WIDTH69 - [10:8] */
6673#define WM8995_WSEQ_DATA_WIDTH69_WIDTH 3 /* WSEQ_DATA_WIDTH69 - [10:8] */
6674#define WM8995_WSEQ_DATA_START69_MASK 0x000F /* WSEQ_DATA_START69 - [3:0] */
6675#define WM8995_WSEQ_DATA_START69_SHIFT 0 /* WSEQ_DATA_START69 - [3:0] */
6676#define WM8995_WSEQ_DATA_START69_WIDTH 4 /* WSEQ_DATA_START69 - [3:0] */
6677
6678/*
6679 * R12567 (0x3117) - Write Sequencer 279
6680 */
6681#define WM8995_WSEQ_EOS69 0x0100 /* WSEQ_EOS69 */
6682#define WM8995_WSEQ_EOS69_MASK 0x0100 /* WSEQ_EOS69 */
6683#define WM8995_WSEQ_EOS69_SHIFT 8 /* WSEQ_EOS69 */
6684#define WM8995_WSEQ_EOS69_WIDTH 1 /* WSEQ_EOS69 */
6685#define WM8995_WSEQ_DELAY69_MASK 0x000F /* WSEQ_DELAY69 - [3:0] */
6686#define WM8995_WSEQ_DELAY69_SHIFT 0 /* WSEQ_DELAY69 - [3:0] */
6687#define WM8995_WSEQ_DELAY69_WIDTH 4 /* WSEQ_DELAY69 - [3:0] */
6688
6689/*
6690 * R12568 (0x3118) - Write Sequencer 280
6691 */
6692#define WM8995_WSEQ_ADDR70_MASK 0x3FFF /* WSEQ_ADDR70 - [13:0] */
6693#define WM8995_WSEQ_ADDR70_SHIFT 0 /* WSEQ_ADDR70 - [13:0] */
6694#define WM8995_WSEQ_ADDR70_WIDTH 14 /* WSEQ_ADDR70 - [13:0] */
6695
6696/*
6697 * R12569 (0x3119) - Write Sequencer 281
6698 */
6699#define WM8995_WSEQ_DATA70_MASK 0x00FF /* WSEQ_DATA70 - [7:0] */
6700#define WM8995_WSEQ_DATA70_SHIFT 0 /* WSEQ_DATA70 - [7:0] */
6701#define WM8995_WSEQ_DATA70_WIDTH 8 /* WSEQ_DATA70 - [7:0] */
6702
6703/*
6704 * R12570 (0x311A) - Write Sequencer 282
6705 */
6706#define WM8995_WSEQ_DATA_WIDTH70_MASK 0x0700 /* WSEQ_DATA_WIDTH70 - [10:8] */
6707#define WM8995_WSEQ_DATA_WIDTH70_SHIFT 8 /* WSEQ_DATA_WIDTH70 - [10:8] */
6708#define WM8995_WSEQ_DATA_WIDTH70_WIDTH 3 /* WSEQ_DATA_WIDTH70 - [10:8] */
6709#define WM8995_WSEQ_DATA_START70_MASK 0x000F /* WSEQ_DATA_START70 - [3:0] */
6710#define WM8995_WSEQ_DATA_START70_SHIFT 0 /* WSEQ_DATA_START70 - [3:0] */
6711#define WM8995_WSEQ_DATA_START70_WIDTH 4 /* WSEQ_DATA_START70 - [3:0] */
6712
6713/*
6714 * R12571 (0x311B) - Write Sequencer 283
6715 */
6716#define WM8995_WSEQ_EOS70 0x0100 /* WSEQ_EOS70 */
6717#define WM8995_WSEQ_EOS70_MASK 0x0100 /* WSEQ_EOS70 */
6718#define WM8995_WSEQ_EOS70_SHIFT 8 /* WSEQ_EOS70 */
6719#define WM8995_WSEQ_EOS70_WIDTH 1 /* WSEQ_EOS70 */
6720#define WM8995_WSEQ_DELAY70_MASK 0x000F /* WSEQ_DELAY70 - [3:0] */
6721#define WM8995_WSEQ_DELAY70_SHIFT 0 /* WSEQ_DELAY70 - [3:0] */
6722#define WM8995_WSEQ_DELAY70_WIDTH 4 /* WSEQ_DELAY70 - [3:0] */
6723
6724/*
6725 * R12572 (0x311C) - Write Sequencer 284
6726 */
6727#define WM8995_WSEQ_ADDR71_MASK 0x3FFF /* WSEQ_ADDR71 - [13:0] */
6728#define WM8995_WSEQ_ADDR71_SHIFT 0 /* WSEQ_ADDR71 - [13:0] */
6729#define WM8995_WSEQ_ADDR71_WIDTH 14 /* WSEQ_ADDR71 - [13:0] */
6730
6731/*
6732 * R12573 (0x311D) - Write Sequencer 285
6733 */
6734#define WM8995_WSEQ_DATA71_MASK 0x00FF /* WSEQ_DATA71 - [7:0] */
6735#define WM8995_WSEQ_DATA71_SHIFT 0 /* WSEQ_DATA71 - [7:0] */
6736#define WM8995_WSEQ_DATA71_WIDTH 8 /* WSEQ_DATA71 - [7:0] */
6737
6738/*
6739 * R12574 (0x311E) - Write Sequencer 286
6740 */
6741#define WM8995_WSEQ_DATA_WIDTH71_MASK 0x0700 /* WSEQ_DATA_WIDTH71 - [10:8] */
6742#define WM8995_WSEQ_DATA_WIDTH71_SHIFT 8 /* WSEQ_DATA_WIDTH71 - [10:8] */
6743#define WM8995_WSEQ_DATA_WIDTH71_WIDTH 3 /* WSEQ_DATA_WIDTH71 - [10:8] */
6744#define WM8995_WSEQ_DATA_START71_MASK 0x000F /* WSEQ_DATA_START71 - [3:0] */
6745#define WM8995_WSEQ_DATA_START71_SHIFT 0 /* WSEQ_DATA_START71 - [3:0] */
6746#define WM8995_WSEQ_DATA_START71_WIDTH 4 /* WSEQ_DATA_START71 - [3:0] */
6747
6748/*
6749 * R12575 (0x311F) - Write Sequencer 287
6750 */
6751#define WM8995_WSEQ_EOS71 0x0100 /* WSEQ_EOS71 */
6752#define WM8995_WSEQ_EOS71_MASK 0x0100 /* WSEQ_EOS71 */
6753#define WM8995_WSEQ_EOS71_SHIFT 8 /* WSEQ_EOS71 */
6754#define WM8995_WSEQ_EOS71_WIDTH 1 /* WSEQ_EOS71 */
6755#define WM8995_WSEQ_DELAY71_MASK 0x000F /* WSEQ_DELAY71 - [3:0] */
6756#define WM8995_WSEQ_DELAY71_SHIFT 0 /* WSEQ_DELAY71 - [3:0] */
6757#define WM8995_WSEQ_DELAY71_WIDTH 4 /* WSEQ_DELAY71 - [3:0] */
6758
6759/*
6760 * R12576 (0x3120) - Write Sequencer 288
6761 */
6762#define WM8995_WSEQ_ADDR72_MASK 0x3FFF /* WSEQ_ADDR72 - [13:0] */
6763#define WM8995_WSEQ_ADDR72_SHIFT 0 /* WSEQ_ADDR72 - [13:0] */
6764#define WM8995_WSEQ_ADDR72_WIDTH 14 /* WSEQ_ADDR72 - [13:0] */
6765
6766/*
6767 * R12577 (0x3121) - Write Sequencer 289
6768 */
6769#define WM8995_WSEQ_DATA72_MASK 0x00FF /* WSEQ_DATA72 - [7:0] */
6770#define WM8995_WSEQ_DATA72_SHIFT 0 /* WSEQ_DATA72 - [7:0] */
6771#define WM8995_WSEQ_DATA72_WIDTH 8 /* WSEQ_DATA72 - [7:0] */
6772
6773/*
6774 * R12578 (0x3122) - Write Sequencer 290
6775 */
6776#define WM8995_WSEQ_DATA_WIDTH72_MASK 0x0700 /* WSEQ_DATA_WIDTH72 - [10:8] */
6777#define WM8995_WSEQ_DATA_WIDTH72_SHIFT 8 /* WSEQ_DATA_WIDTH72 - [10:8] */
6778#define WM8995_WSEQ_DATA_WIDTH72_WIDTH 3 /* WSEQ_DATA_WIDTH72 - [10:8] */
6779#define WM8995_WSEQ_DATA_START72_MASK 0x000F /* WSEQ_DATA_START72 - [3:0] */
6780#define WM8995_WSEQ_DATA_START72_SHIFT 0 /* WSEQ_DATA_START72 - [3:0] */
6781#define WM8995_WSEQ_DATA_START72_WIDTH 4 /* WSEQ_DATA_START72 - [3:0] */
6782
6783/*
6784 * R12579 (0x3123) - Write Sequencer 291
6785 */
6786#define WM8995_WSEQ_EOS72 0x0100 /* WSEQ_EOS72 */
6787#define WM8995_WSEQ_EOS72_MASK 0x0100 /* WSEQ_EOS72 */
6788#define WM8995_WSEQ_EOS72_SHIFT 8 /* WSEQ_EOS72 */
6789#define WM8995_WSEQ_EOS72_WIDTH 1 /* WSEQ_EOS72 */
6790#define WM8995_WSEQ_DELAY72_MASK 0x000F /* WSEQ_DELAY72 - [3:0] */
6791#define WM8995_WSEQ_DELAY72_SHIFT 0 /* WSEQ_DELAY72 - [3:0] */
6792#define WM8995_WSEQ_DELAY72_WIDTH 4 /* WSEQ_DELAY72 - [3:0] */
6793
6794/*
6795 * R12580 (0x3124) - Write Sequencer 292
6796 */
6797#define WM8995_WSEQ_ADDR73_MASK 0x3FFF /* WSEQ_ADDR73 - [13:0] */
6798#define WM8995_WSEQ_ADDR73_SHIFT 0 /* WSEQ_ADDR73 - [13:0] */
6799#define WM8995_WSEQ_ADDR73_WIDTH 14 /* WSEQ_ADDR73 - [13:0] */
6800
6801/*
6802 * R12581 (0x3125) - Write Sequencer 293
6803 */
6804#define WM8995_WSEQ_DATA73_MASK 0x00FF /* WSEQ_DATA73 - [7:0] */
6805#define WM8995_WSEQ_DATA73_SHIFT 0 /* WSEQ_DATA73 - [7:0] */
6806#define WM8995_WSEQ_DATA73_WIDTH 8 /* WSEQ_DATA73 - [7:0] */
6807
6808/*
6809 * R12582 (0x3126) - Write Sequencer 294
6810 */
6811#define WM8995_WSEQ_DATA_WIDTH73_MASK 0x0700 /* WSEQ_DATA_WIDTH73 - [10:8] */
6812#define WM8995_WSEQ_DATA_WIDTH73_SHIFT 8 /* WSEQ_DATA_WIDTH73 - [10:8] */
6813#define WM8995_WSEQ_DATA_WIDTH73_WIDTH 3 /* WSEQ_DATA_WIDTH73 - [10:8] */
6814#define WM8995_WSEQ_DATA_START73_MASK 0x000F /* WSEQ_DATA_START73 - [3:0] */
6815#define WM8995_WSEQ_DATA_START73_SHIFT 0 /* WSEQ_DATA_START73 - [3:0] */
6816#define WM8995_WSEQ_DATA_START73_WIDTH 4 /* WSEQ_DATA_START73 - [3:0] */
6817
6818/*
6819 * R12583 (0x3127) - Write Sequencer 295
6820 */
6821#define WM8995_WSEQ_EOS73 0x0100 /* WSEQ_EOS73 */
6822#define WM8995_WSEQ_EOS73_MASK 0x0100 /* WSEQ_EOS73 */
6823#define WM8995_WSEQ_EOS73_SHIFT 8 /* WSEQ_EOS73 */
6824#define WM8995_WSEQ_EOS73_WIDTH 1 /* WSEQ_EOS73 */
6825#define WM8995_WSEQ_DELAY73_MASK 0x000F /* WSEQ_DELAY73 - [3:0] */
6826#define WM8995_WSEQ_DELAY73_SHIFT 0 /* WSEQ_DELAY73 - [3:0] */
6827#define WM8995_WSEQ_DELAY73_WIDTH 4 /* WSEQ_DELAY73 - [3:0] */
6828
6829/*
6830 * R12584 (0x3128) - Write Sequencer 296
6831 */
6832#define WM8995_WSEQ_ADDR74_MASK 0x3FFF /* WSEQ_ADDR74 - [13:0] */
6833#define WM8995_WSEQ_ADDR74_SHIFT 0 /* WSEQ_ADDR74 - [13:0] */
6834#define WM8995_WSEQ_ADDR74_WIDTH 14 /* WSEQ_ADDR74 - [13:0] */
6835
6836/*
6837 * R12585 (0x3129) - Write Sequencer 297
6838 */
6839#define WM8995_WSEQ_DATA74_MASK 0x00FF /* WSEQ_DATA74 - [7:0] */
6840#define WM8995_WSEQ_DATA74_SHIFT 0 /* WSEQ_DATA74 - [7:0] */
6841#define WM8995_WSEQ_DATA74_WIDTH 8 /* WSEQ_DATA74 - [7:0] */
6842
6843/*
6844 * R12586 (0x312A) - Write Sequencer 298
6845 */
6846#define WM8995_WSEQ_DATA_WIDTH74_MASK 0x0700 /* WSEQ_DATA_WIDTH74 - [10:8] */
6847#define WM8995_WSEQ_DATA_WIDTH74_SHIFT 8 /* WSEQ_DATA_WIDTH74 - [10:8] */
6848#define WM8995_WSEQ_DATA_WIDTH74_WIDTH 3 /* WSEQ_DATA_WIDTH74 - [10:8] */
6849#define WM8995_WSEQ_DATA_START74_MASK 0x000F /* WSEQ_DATA_START74 - [3:0] */
6850#define WM8995_WSEQ_DATA_START74_SHIFT 0 /* WSEQ_DATA_START74 - [3:0] */
6851#define WM8995_WSEQ_DATA_START74_WIDTH 4 /* WSEQ_DATA_START74 - [3:0] */
6852
6853/*
6854 * R12587 (0x312B) - Write Sequencer 299
6855 */
6856#define WM8995_WSEQ_EOS74 0x0100 /* WSEQ_EOS74 */
6857#define WM8995_WSEQ_EOS74_MASK 0x0100 /* WSEQ_EOS74 */
6858#define WM8995_WSEQ_EOS74_SHIFT 8 /* WSEQ_EOS74 */
6859#define WM8995_WSEQ_EOS74_WIDTH 1 /* WSEQ_EOS74 */
6860#define WM8995_WSEQ_DELAY74_MASK 0x000F /* WSEQ_DELAY74 - [3:0] */
6861#define WM8995_WSEQ_DELAY74_SHIFT 0 /* WSEQ_DELAY74 - [3:0] */
6862#define WM8995_WSEQ_DELAY74_WIDTH 4 /* WSEQ_DELAY74 - [3:0] */
6863
6864/*
6865 * R12588 (0x312C) - Write Sequencer 300
6866 */
6867#define WM8995_WSEQ_ADDR75_MASK 0x3FFF /* WSEQ_ADDR75 - [13:0] */
6868#define WM8995_WSEQ_ADDR75_SHIFT 0 /* WSEQ_ADDR75 - [13:0] */
6869#define WM8995_WSEQ_ADDR75_WIDTH 14 /* WSEQ_ADDR75 - [13:0] */
6870
6871/*
6872 * R12589 (0x312D) - Write Sequencer 301
6873 */
6874#define WM8995_WSEQ_DATA75_MASK 0x00FF /* WSEQ_DATA75 - [7:0] */
6875#define WM8995_WSEQ_DATA75_SHIFT 0 /* WSEQ_DATA75 - [7:0] */
6876#define WM8995_WSEQ_DATA75_WIDTH 8 /* WSEQ_DATA75 - [7:0] */
6877
6878/*
6879 * R12590 (0x312E) - Write Sequencer 302
6880 */
6881#define WM8995_WSEQ_DATA_WIDTH75_MASK 0x0700 /* WSEQ_DATA_WIDTH75 - [10:8] */
6882#define WM8995_WSEQ_DATA_WIDTH75_SHIFT 8 /* WSEQ_DATA_WIDTH75 - [10:8] */
6883#define WM8995_WSEQ_DATA_WIDTH75_WIDTH 3 /* WSEQ_DATA_WIDTH75 - [10:8] */
6884#define WM8995_WSEQ_DATA_START75_MASK 0x000F /* WSEQ_DATA_START75 - [3:0] */
6885#define WM8995_WSEQ_DATA_START75_SHIFT 0 /* WSEQ_DATA_START75 - [3:0] */
6886#define WM8995_WSEQ_DATA_START75_WIDTH 4 /* WSEQ_DATA_START75 - [3:0] */
6887
6888/*
6889 * R12591 (0x312F) - Write Sequencer 303
6890 */
6891#define WM8995_WSEQ_EOS75 0x0100 /* WSEQ_EOS75 */
6892#define WM8995_WSEQ_EOS75_MASK 0x0100 /* WSEQ_EOS75 */
6893#define WM8995_WSEQ_EOS75_SHIFT 8 /* WSEQ_EOS75 */
6894#define WM8995_WSEQ_EOS75_WIDTH 1 /* WSEQ_EOS75 */
6895#define WM8995_WSEQ_DELAY75_MASK 0x000F /* WSEQ_DELAY75 - [3:0] */
6896#define WM8995_WSEQ_DELAY75_SHIFT 0 /* WSEQ_DELAY75 - [3:0] */
6897#define WM8995_WSEQ_DELAY75_WIDTH 4 /* WSEQ_DELAY75 - [3:0] */
6898
6899/*
6900 * R12592 (0x3130) - Write Sequencer 304
6901 */
6902#define WM8995_WSEQ_ADDR76_MASK 0x3FFF /* WSEQ_ADDR76 - [13:0] */
6903#define WM8995_WSEQ_ADDR76_SHIFT 0 /* WSEQ_ADDR76 - [13:0] */
6904#define WM8995_WSEQ_ADDR76_WIDTH 14 /* WSEQ_ADDR76 - [13:0] */
6905
6906/*
6907 * R12593 (0x3131) - Write Sequencer 305
6908 */
6909#define WM8995_WSEQ_DATA76_MASK 0x00FF /* WSEQ_DATA76 - [7:0] */
6910#define WM8995_WSEQ_DATA76_SHIFT 0 /* WSEQ_DATA76 - [7:0] */
6911#define WM8995_WSEQ_DATA76_WIDTH 8 /* WSEQ_DATA76 - [7:0] */
6912
6913/*
6914 * R12594 (0x3132) - Write Sequencer 306
6915 */
6916#define WM8995_WSEQ_DATA_WIDTH76_MASK 0x0700 /* WSEQ_DATA_WIDTH76 - [10:8] */
6917#define WM8995_WSEQ_DATA_WIDTH76_SHIFT 8 /* WSEQ_DATA_WIDTH76 - [10:8] */
6918#define WM8995_WSEQ_DATA_WIDTH76_WIDTH 3 /* WSEQ_DATA_WIDTH76 - [10:8] */
6919#define WM8995_WSEQ_DATA_START76_MASK 0x000F /* WSEQ_DATA_START76 - [3:0] */
6920#define WM8995_WSEQ_DATA_START76_SHIFT 0 /* WSEQ_DATA_START76 - [3:0] */
6921#define WM8995_WSEQ_DATA_START76_WIDTH 4 /* WSEQ_DATA_START76 - [3:0] */
6922
6923/*
6924 * R12595 (0x3133) - Write Sequencer 307
6925 */
6926#define WM8995_WSEQ_EOS76 0x0100 /* WSEQ_EOS76 */
6927#define WM8995_WSEQ_EOS76_MASK 0x0100 /* WSEQ_EOS76 */
6928#define WM8995_WSEQ_EOS76_SHIFT 8 /* WSEQ_EOS76 */
6929#define WM8995_WSEQ_EOS76_WIDTH 1 /* WSEQ_EOS76 */
6930#define WM8995_WSEQ_DELAY76_MASK 0x000F /* WSEQ_DELAY76 - [3:0] */
6931#define WM8995_WSEQ_DELAY76_SHIFT 0 /* WSEQ_DELAY76 - [3:0] */
6932#define WM8995_WSEQ_DELAY76_WIDTH 4 /* WSEQ_DELAY76 - [3:0] */
6933
6934/*
6935 * R12596 (0x3134) - Write Sequencer 308
6936 */
6937#define WM8995_WSEQ_ADDR77_MASK 0x3FFF /* WSEQ_ADDR77 - [13:0] */
6938#define WM8995_WSEQ_ADDR77_SHIFT 0 /* WSEQ_ADDR77 - [13:0] */
6939#define WM8995_WSEQ_ADDR77_WIDTH 14 /* WSEQ_ADDR77 - [13:0] */
6940
6941/*
6942 * R12597 (0x3135) - Write Sequencer 309
6943 */
6944#define WM8995_WSEQ_DATA77_MASK 0x00FF /* WSEQ_DATA77 - [7:0] */
6945#define WM8995_WSEQ_DATA77_SHIFT 0 /* WSEQ_DATA77 - [7:0] */
6946#define WM8995_WSEQ_DATA77_WIDTH 8 /* WSEQ_DATA77 - [7:0] */
6947
6948/*
6949 * R12598 (0x3136) - Write Sequencer 310
6950 */
6951#define WM8995_WSEQ_DATA_WIDTH77_MASK 0x0700 /* WSEQ_DATA_WIDTH77 - [10:8] */
6952#define WM8995_WSEQ_DATA_WIDTH77_SHIFT 8 /* WSEQ_DATA_WIDTH77 - [10:8] */
6953#define WM8995_WSEQ_DATA_WIDTH77_WIDTH 3 /* WSEQ_DATA_WIDTH77 - [10:8] */
6954#define WM8995_WSEQ_DATA_START77_MASK 0x000F /* WSEQ_DATA_START77 - [3:0] */
6955#define WM8995_WSEQ_DATA_START77_SHIFT 0 /* WSEQ_DATA_START77 - [3:0] */
6956#define WM8995_WSEQ_DATA_START77_WIDTH 4 /* WSEQ_DATA_START77 - [3:0] */
6957
6958/*
6959 * R12599 (0x3137) - Write Sequencer 311
6960 */
6961#define WM8995_WSEQ_EOS77 0x0100 /* WSEQ_EOS77 */
6962#define WM8995_WSEQ_EOS77_MASK 0x0100 /* WSEQ_EOS77 */
6963#define WM8995_WSEQ_EOS77_SHIFT 8 /* WSEQ_EOS77 */
6964#define WM8995_WSEQ_EOS77_WIDTH 1 /* WSEQ_EOS77 */
6965#define WM8995_WSEQ_DELAY77_MASK 0x000F /* WSEQ_DELAY77 - [3:0] */
6966#define WM8995_WSEQ_DELAY77_SHIFT 0 /* WSEQ_DELAY77 - [3:0] */
6967#define WM8995_WSEQ_DELAY77_WIDTH 4 /* WSEQ_DELAY77 - [3:0] */
6968
6969/*
6970 * R12600 (0x3138) - Write Sequencer 312
6971 */
6972#define WM8995_WSEQ_ADDR78_MASK 0x3FFF /* WSEQ_ADDR78 - [13:0] */
6973#define WM8995_WSEQ_ADDR78_SHIFT 0 /* WSEQ_ADDR78 - [13:0] */
6974#define WM8995_WSEQ_ADDR78_WIDTH 14 /* WSEQ_ADDR78 - [13:0] */
6975
6976/*
6977 * R12601 (0x3139) - Write Sequencer 313
6978 */
6979#define WM8995_WSEQ_DATA78_MASK 0x00FF /* WSEQ_DATA78 - [7:0] */
6980#define WM8995_WSEQ_DATA78_SHIFT 0 /* WSEQ_DATA78 - [7:0] */
6981#define WM8995_WSEQ_DATA78_WIDTH 8 /* WSEQ_DATA78 - [7:0] */
6982
6983/*
6984 * R12602 (0x313A) - Write Sequencer 314
6985 */
6986#define WM8995_WSEQ_DATA_WIDTH78_MASK 0x0700 /* WSEQ_DATA_WIDTH78 - [10:8] */
6987#define WM8995_WSEQ_DATA_WIDTH78_SHIFT 8 /* WSEQ_DATA_WIDTH78 - [10:8] */
6988#define WM8995_WSEQ_DATA_WIDTH78_WIDTH 3 /* WSEQ_DATA_WIDTH78 - [10:8] */
6989#define WM8995_WSEQ_DATA_START78_MASK 0x000F /* WSEQ_DATA_START78 - [3:0] */
6990#define WM8995_WSEQ_DATA_START78_SHIFT 0 /* WSEQ_DATA_START78 - [3:0] */
6991#define WM8995_WSEQ_DATA_START78_WIDTH 4 /* WSEQ_DATA_START78 - [3:0] */
6992
6993/*
6994 * R12603 (0x313B) - Write Sequencer 315
6995 */
6996#define WM8995_WSEQ_EOS78 0x0100 /* WSEQ_EOS78 */
6997#define WM8995_WSEQ_EOS78_MASK 0x0100 /* WSEQ_EOS78 */
6998#define WM8995_WSEQ_EOS78_SHIFT 8 /* WSEQ_EOS78 */
6999#define WM8995_WSEQ_EOS78_WIDTH 1 /* WSEQ_EOS78 */
7000#define WM8995_WSEQ_DELAY78_MASK 0x000F /* WSEQ_DELAY78 - [3:0] */
7001#define WM8995_WSEQ_DELAY78_SHIFT 0 /* WSEQ_DELAY78 - [3:0] */
7002#define WM8995_WSEQ_DELAY78_WIDTH 4 /* WSEQ_DELAY78 - [3:0] */
7003
7004/*
7005 * R12604 (0x313C) - Write Sequencer 316
7006 */
7007#define WM8995_WSEQ_ADDR79_MASK 0x3FFF /* WSEQ_ADDR79 - [13:0] */
7008#define WM8995_WSEQ_ADDR79_SHIFT 0 /* WSEQ_ADDR79 - [13:0] */
7009#define WM8995_WSEQ_ADDR79_WIDTH 14 /* WSEQ_ADDR79 - [13:0] */
7010
7011/*
7012 * R12605 (0x313D) - Write Sequencer 317
7013 */
7014#define WM8995_WSEQ_DATA79_MASK 0x00FF /* WSEQ_DATA79 - [7:0] */
7015#define WM8995_WSEQ_DATA79_SHIFT 0 /* WSEQ_DATA79 - [7:0] */
7016#define WM8995_WSEQ_DATA79_WIDTH 8 /* WSEQ_DATA79 - [7:0] */
7017
7018/*
7019 * R12606 (0x313E) - Write Sequencer 318
7020 */
7021#define WM8995_WSEQ_DATA_WIDTH79_MASK 0x0700 /* WSEQ_DATA_WIDTH79 - [10:8] */
7022#define WM8995_WSEQ_DATA_WIDTH79_SHIFT 8 /* WSEQ_DATA_WIDTH79 - [10:8] */
7023#define WM8995_WSEQ_DATA_WIDTH79_WIDTH 3 /* WSEQ_DATA_WIDTH79 - [10:8] */
7024#define WM8995_WSEQ_DATA_START79_MASK 0x000F /* WSEQ_DATA_START79 - [3:0] */
7025#define WM8995_WSEQ_DATA_START79_SHIFT 0 /* WSEQ_DATA_START79 - [3:0] */
7026#define WM8995_WSEQ_DATA_START79_WIDTH 4 /* WSEQ_DATA_START79 - [3:0] */
7027
7028/*
7029 * R12607 (0x313F) - Write Sequencer 319
7030 */
7031#define WM8995_WSEQ_EOS79 0x0100 /* WSEQ_EOS79 */
7032#define WM8995_WSEQ_EOS79_MASK 0x0100 /* WSEQ_EOS79 */
7033#define WM8995_WSEQ_EOS79_SHIFT 8 /* WSEQ_EOS79 */
7034#define WM8995_WSEQ_EOS79_WIDTH 1 /* WSEQ_EOS79 */
7035#define WM8995_WSEQ_DELAY79_MASK 0x000F /* WSEQ_DELAY79 - [3:0] */
7036#define WM8995_WSEQ_DELAY79_SHIFT 0 /* WSEQ_DELAY79 - [3:0] */
7037#define WM8995_WSEQ_DELAY79_WIDTH 4 /* WSEQ_DELAY79 - [3:0] */
7038
7039/*
7040 * R12608 (0x3140) - Write Sequencer 320
7041 */
7042#define WM8995_WSEQ_ADDR80_MASK 0x3FFF /* WSEQ_ADDR80 - [13:0] */
7043#define WM8995_WSEQ_ADDR80_SHIFT 0 /* WSEQ_ADDR80 - [13:0] */
7044#define WM8995_WSEQ_ADDR80_WIDTH 14 /* WSEQ_ADDR80 - [13:0] */
7045
7046/*
7047 * R12609 (0x3141) - Write Sequencer 321
7048 */
7049#define WM8995_WSEQ_DATA80_MASK 0x00FF /* WSEQ_DATA80 - [7:0] */
7050#define WM8995_WSEQ_DATA80_SHIFT 0 /* WSEQ_DATA80 - [7:0] */
7051#define WM8995_WSEQ_DATA80_WIDTH 8 /* WSEQ_DATA80 - [7:0] */
7052
7053/*
7054 * R12610 (0x3142) - Write Sequencer 322
7055 */
7056#define WM8995_WSEQ_DATA_WIDTH80_MASK 0x0700 /* WSEQ_DATA_WIDTH80 - [10:8] */
7057#define WM8995_WSEQ_DATA_WIDTH80_SHIFT 8 /* WSEQ_DATA_WIDTH80 - [10:8] */
7058#define WM8995_WSEQ_DATA_WIDTH80_WIDTH 3 /* WSEQ_DATA_WIDTH80 - [10:8] */
7059#define WM8995_WSEQ_DATA_START80_MASK 0x000F /* WSEQ_DATA_START80 - [3:0] */
7060#define WM8995_WSEQ_DATA_START80_SHIFT 0 /* WSEQ_DATA_START80 - [3:0] */
7061#define WM8995_WSEQ_DATA_START80_WIDTH 4 /* WSEQ_DATA_START80 - [3:0] */
7062
7063/*
7064 * R12611 (0x3143) - Write Sequencer 323
7065 */
7066#define WM8995_WSEQ_EOS80 0x0100 /* WSEQ_EOS80 */
7067#define WM8995_WSEQ_EOS80_MASK 0x0100 /* WSEQ_EOS80 */
7068#define WM8995_WSEQ_EOS80_SHIFT 8 /* WSEQ_EOS80 */
7069#define WM8995_WSEQ_EOS80_WIDTH 1 /* WSEQ_EOS80 */
7070#define WM8995_WSEQ_DELAY80_MASK 0x000F /* WSEQ_DELAY80 - [3:0] */
7071#define WM8995_WSEQ_DELAY80_SHIFT 0 /* WSEQ_DELAY80 - [3:0] */
7072#define WM8995_WSEQ_DELAY80_WIDTH 4 /* WSEQ_DELAY80 - [3:0] */
7073
7074/*
7075 * R12612 (0x3144) - Write Sequencer 324
7076 */
7077#define WM8995_WSEQ_ADDR81_MASK 0x3FFF /* WSEQ_ADDR81 - [13:0] */
7078#define WM8995_WSEQ_ADDR81_SHIFT 0 /* WSEQ_ADDR81 - [13:0] */
7079#define WM8995_WSEQ_ADDR81_WIDTH 14 /* WSEQ_ADDR81 - [13:0] */
7080
7081/*
7082 * R12613 (0x3145) - Write Sequencer 325
7083 */
7084#define WM8995_WSEQ_DATA81_MASK 0x00FF /* WSEQ_DATA81 - [7:0] */
7085#define WM8995_WSEQ_DATA81_SHIFT 0 /* WSEQ_DATA81 - [7:0] */
7086#define WM8995_WSEQ_DATA81_WIDTH 8 /* WSEQ_DATA81 - [7:0] */
7087
7088/*
7089 * R12614 (0x3146) - Write Sequencer 326
7090 */
7091#define WM8995_WSEQ_DATA_WIDTH81_MASK 0x0700 /* WSEQ_DATA_WIDTH81 - [10:8] */
7092#define WM8995_WSEQ_DATA_WIDTH81_SHIFT 8 /* WSEQ_DATA_WIDTH81 - [10:8] */
7093#define WM8995_WSEQ_DATA_WIDTH81_WIDTH 3 /* WSEQ_DATA_WIDTH81 - [10:8] */
7094#define WM8995_WSEQ_DATA_START81_MASK 0x000F /* WSEQ_DATA_START81 - [3:0] */
7095#define WM8995_WSEQ_DATA_START81_SHIFT 0 /* WSEQ_DATA_START81 - [3:0] */
7096#define WM8995_WSEQ_DATA_START81_WIDTH 4 /* WSEQ_DATA_START81 - [3:0] */
7097
7098/*
7099 * R12615 (0x3147) - Write Sequencer 327
7100 */
7101#define WM8995_WSEQ_EOS81 0x0100 /* WSEQ_EOS81 */
7102#define WM8995_WSEQ_EOS81_MASK 0x0100 /* WSEQ_EOS81 */
7103#define WM8995_WSEQ_EOS81_SHIFT 8 /* WSEQ_EOS81 */
7104#define WM8995_WSEQ_EOS81_WIDTH 1 /* WSEQ_EOS81 */
7105#define WM8995_WSEQ_DELAY81_MASK 0x000F /* WSEQ_DELAY81 - [3:0] */
7106#define WM8995_WSEQ_DELAY81_SHIFT 0 /* WSEQ_DELAY81 - [3:0] */
7107#define WM8995_WSEQ_DELAY81_WIDTH 4 /* WSEQ_DELAY81 - [3:0] */
7108
7109/*
7110 * R12616 (0x3148) - Write Sequencer 328
7111 */
7112#define WM8995_WSEQ_ADDR82_MASK 0x3FFF /* WSEQ_ADDR82 - [13:0] */
7113#define WM8995_WSEQ_ADDR82_SHIFT 0 /* WSEQ_ADDR82 - [13:0] */
7114#define WM8995_WSEQ_ADDR82_WIDTH 14 /* WSEQ_ADDR82 - [13:0] */
7115
7116/*
7117 * R12617 (0x3149) - Write Sequencer 329
7118 */
7119#define WM8995_WSEQ_DATA82_MASK 0x00FF /* WSEQ_DATA82 - [7:0] */
7120#define WM8995_WSEQ_DATA82_SHIFT 0 /* WSEQ_DATA82 - [7:0] */
7121#define WM8995_WSEQ_DATA82_WIDTH 8 /* WSEQ_DATA82 - [7:0] */
7122
7123/*
7124 * R12618 (0x314A) - Write Sequencer 330
7125 */
7126#define WM8995_WSEQ_DATA_WIDTH82_MASK 0x0700 /* WSEQ_DATA_WIDTH82 - [10:8] */
7127#define WM8995_WSEQ_DATA_WIDTH82_SHIFT 8 /* WSEQ_DATA_WIDTH82 - [10:8] */
7128#define WM8995_WSEQ_DATA_WIDTH82_WIDTH 3 /* WSEQ_DATA_WIDTH82 - [10:8] */
7129#define WM8995_WSEQ_DATA_START82_MASK 0x000F /* WSEQ_DATA_START82 - [3:0] */
7130#define WM8995_WSEQ_DATA_START82_SHIFT 0 /* WSEQ_DATA_START82 - [3:0] */
7131#define WM8995_WSEQ_DATA_START82_WIDTH 4 /* WSEQ_DATA_START82 - [3:0] */
7132
7133/*
7134 * R12619 (0x314B) - Write Sequencer 331
7135 */
7136#define WM8995_WSEQ_EOS82 0x0100 /* WSEQ_EOS82 */
7137#define WM8995_WSEQ_EOS82_MASK 0x0100 /* WSEQ_EOS82 */
7138#define WM8995_WSEQ_EOS82_SHIFT 8 /* WSEQ_EOS82 */
7139#define WM8995_WSEQ_EOS82_WIDTH 1 /* WSEQ_EOS82 */
7140#define WM8995_WSEQ_DELAY82_MASK 0x000F /* WSEQ_DELAY82 - [3:0] */
7141#define WM8995_WSEQ_DELAY82_SHIFT 0 /* WSEQ_DELAY82 - [3:0] */
7142#define WM8995_WSEQ_DELAY82_WIDTH 4 /* WSEQ_DELAY82 - [3:0] */
7143
7144/*
7145 * R12620 (0x314C) - Write Sequencer 332
7146 */
7147#define WM8995_WSEQ_ADDR83_MASK 0x3FFF /* WSEQ_ADDR83 - [13:0] */
7148#define WM8995_WSEQ_ADDR83_SHIFT 0 /* WSEQ_ADDR83 - [13:0] */
7149#define WM8995_WSEQ_ADDR83_WIDTH 14 /* WSEQ_ADDR83 - [13:0] */
7150
7151/*
7152 * R12621 (0x314D) - Write Sequencer 333
7153 */
7154#define WM8995_WSEQ_DATA83_MASK 0x00FF /* WSEQ_DATA83 - [7:0] */
7155#define WM8995_WSEQ_DATA83_SHIFT 0 /* WSEQ_DATA83 - [7:0] */
7156#define WM8995_WSEQ_DATA83_WIDTH 8 /* WSEQ_DATA83 - [7:0] */
7157
7158/*
7159 * R12622 (0x314E) - Write Sequencer 334
7160 */
7161#define WM8995_WSEQ_DATA_WIDTH83_MASK 0x0700 /* WSEQ_DATA_WIDTH83 - [10:8] */
7162#define WM8995_WSEQ_DATA_WIDTH83_SHIFT 8 /* WSEQ_DATA_WIDTH83 - [10:8] */
7163#define WM8995_WSEQ_DATA_WIDTH83_WIDTH 3 /* WSEQ_DATA_WIDTH83 - [10:8] */
7164#define WM8995_WSEQ_DATA_START83_MASK 0x000F /* WSEQ_DATA_START83 - [3:0] */
7165#define WM8995_WSEQ_DATA_START83_SHIFT 0 /* WSEQ_DATA_START83 - [3:0] */
7166#define WM8995_WSEQ_DATA_START83_WIDTH 4 /* WSEQ_DATA_START83 - [3:0] */
7167
7168/*
7169 * R12623 (0x314F) - Write Sequencer 335
7170 */
7171#define WM8995_WSEQ_EOS83 0x0100 /* WSEQ_EOS83 */
7172#define WM8995_WSEQ_EOS83_MASK 0x0100 /* WSEQ_EOS83 */
7173#define WM8995_WSEQ_EOS83_SHIFT 8 /* WSEQ_EOS83 */
7174#define WM8995_WSEQ_EOS83_WIDTH 1 /* WSEQ_EOS83 */
7175#define WM8995_WSEQ_DELAY83_MASK 0x000F /* WSEQ_DELAY83 - [3:0] */
7176#define WM8995_WSEQ_DELAY83_SHIFT 0 /* WSEQ_DELAY83 - [3:0] */
7177#define WM8995_WSEQ_DELAY83_WIDTH 4 /* WSEQ_DELAY83 - [3:0] */
7178
7179/*
7180 * R12624 (0x3150) - Write Sequencer 336
7181 */
7182#define WM8995_WSEQ_ADDR84_MASK 0x3FFF /* WSEQ_ADDR84 - [13:0] */
7183#define WM8995_WSEQ_ADDR84_SHIFT 0 /* WSEQ_ADDR84 - [13:0] */
7184#define WM8995_WSEQ_ADDR84_WIDTH 14 /* WSEQ_ADDR84 - [13:0] */
7185
7186/*
7187 * R12625 (0x3151) - Write Sequencer 337
7188 */
7189#define WM8995_WSEQ_DATA84_MASK 0x00FF /* WSEQ_DATA84 - [7:0] */
7190#define WM8995_WSEQ_DATA84_SHIFT 0 /* WSEQ_DATA84 - [7:0] */
7191#define WM8995_WSEQ_DATA84_WIDTH 8 /* WSEQ_DATA84 - [7:0] */
7192
7193/*
7194 * R12626 (0x3152) - Write Sequencer 338
7195 */
7196#define WM8995_WSEQ_DATA_WIDTH84_MASK 0x0700 /* WSEQ_DATA_WIDTH84 - [10:8] */
7197#define WM8995_WSEQ_DATA_WIDTH84_SHIFT 8 /* WSEQ_DATA_WIDTH84 - [10:8] */
7198#define WM8995_WSEQ_DATA_WIDTH84_WIDTH 3 /* WSEQ_DATA_WIDTH84 - [10:8] */
7199#define WM8995_WSEQ_DATA_START84_MASK 0x000F /* WSEQ_DATA_START84 - [3:0] */
7200#define WM8995_WSEQ_DATA_START84_SHIFT 0 /* WSEQ_DATA_START84 - [3:0] */
7201#define WM8995_WSEQ_DATA_START84_WIDTH 4 /* WSEQ_DATA_START84 - [3:0] */
7202
7203/*
7204 * R12627 (0x3153) - Write Sequencer 339
7205 */
7206#define WM8995_WSEQ_EOS84 0x0100 /* WSEQ_EOS84 */
7207#define WM8995_WSEQ_EOS84_MASK 0x0100 /* WSEQ_EOS84 */
7208#define WM8995_WSEQ_EOS84_SHIFT 8 /* WSEQ_EOS84 */
7209#define WM8995_WSEQ_EOS84_WIDTH 1 /* WSEQ_EOS84 */
7210#define WM8995_WSEQ_DELAY84_MASK 0x000F /* WSEQ_DELAY84 - [3:0] */
7211#define WM8995_WSEQ_DELAY84_SHIFT 0 /* WSEQ_DELAY84 - [3:0] */
7212#define WM8995_WSEQ_DELAY84_WIDTH 4 /* WSEQ_DELAY84 - [3:0] */
7213
7214/*
7215 * R12628 (0x3154) - Write Sequencer 340
7216 */
7217#define WM8995_WSEQ_ADDR85_MASK 0x3FFF /* WSEQ_ADDR85 - [13:0] */
7218#define WM8995_WSEQ_ADDR85_SHIFT 0 /* WSEQ_ADDR85 - [13:0] */
7219#define WM8995_WSEQ_ADDR85_WIDTH 14 /* WSEQ_ADDR85 - [13:0] */
7220
7221/*
7222 * R12629 (0x3155) - Write Sequencer 341
7223 */
7224#define WM8995_WSEQ_DATA85_MASK 0x00FF /* WSEQ_DATA85 - [7:0] */
7225#define WM8995_WSEQ_DATA85_SHIFT 0 /* WSEQ_DATA85 - [7:0] */
7226#define WM8995_WSEQ_DATA85_WIDTH 8 /* WSEQ_DATA85 - [7:0] */
7227
7228/*
7229 * R12630 (0x3156) - Write Sequencer 342
7230 */
7231#define WM8995_WSEQ_DATA_WIDTH85_MASK 0x0700 /* WSEQ_DATA_WIDTH85 - [10:8] */
7232#define WM8995_WSEQ_DATA_WIDTH85_SHIFT 8 /* WSEQ_DATA_WIDTH85 - [10:8] */
7233#define WM8995_WSEQ_DATA_WIDTH85_WIDTH 3 /* WSEQ_DATA_WIDTH85 - [10:8] */
7234#define WM8995_WSEQ_DATA_START85_MASK 0x000F /* WSEQ_DATA_START85 - [3:0] */
7235#define WM8995_WSEQ_DATA_START85_SHIFT 0 /* WSEQ_DATA_START85 - [3:0] */
7236#define WM8995_WSEQ_DATA_START85_WIDTH 4 /* WSEQ_DATA_START85 - [3:0] */
7237
7238/*
7239 * R12631 (0x3157) - Write Sequencer 343
7240 */
7241#define WM8995_WSEQ_EOS85 0x0100 /* WSEQ_EOS85 */
7242#define WM8995_WSEQ_EOS85_MASK 0x0100 /* WSEQ_EOS85 */
7243#define WM8995_WSEQ_EOS85_SHIFT 8 /* WSEQ_EOS85 */
7244#define WM8995_WSEQ_EOS85_WIDTH 1 /* WSEQ_EOS85 */
7245#define WM8995_WSEQ_DELAY85_MASK 0x000F /* WSEQ_DELAY85 - [3:0] */
7246#define WM8995_WSEQ_DELAY85_SHIFT 0 /* WSEQ_DELAY85 - [3:0] */
7247#define WM8995_WSEQ_DELAY85_WIDTH 4 /* WSEQ_DELAY85 - [3:0] */
7248
7249/*
7250 * R12632 (0x3158) - Write Sequencer 344
7251 */
7252#define WM8995_WSEQ_ADDR86_MASK 0x3FFF /* WSEQ_ADDR86 - [13:0] */
7253#define WM8995_WSEQ_ADDR86_SHIFT 0 /* WSEQ_ADDR86 - [13:0] */
7254#define WM8995_WSEQ_ADDR86_WIDTH 14 /* WSEQ_ADDR86 - [13:0] */
7255
7256/*
7257 * R12633 (0x3159) - Write Sequencer 345
7258 */
7259#define WM8995_WSEQ_DATA86_MASK 0x00FF /* WSEQ_DATA86 - [7:0] */
7260#define WM8995_WSEQ_DATA86_SHIFT 0 /* WSEQ_DATA86 - [7:0] */
7261#define WM8995_WSEQ_DATA86_WIDTH 8 /* WSEQ_DATA86 - [7:0] */
7262
7263/*
7264 * R12634 (0x315A) - Write Sequencer 346
7265 */
7266#define WM8995_WSEQ_DATA_WIDTH86_MASK 0x0700 /* WSEQ_DATA_WIDTH86 - [10:8] */
7267#define WM8995_WSEQ_DATA_WIDTH86_SHIFT 8 /* WSEQ_DATA_WIDTH86 - [10:8] */
7268#define WM8995_WSEQ_DATA_WIDTH86_WIDTH 3 /* WSEQ_DATA_WIDTH86 - [10:8] */
7269#define WM8995_WSEQ_DATA_START86_MASK 0x000F /* WSEQ_DATA_START86 - [3:0] */
7270#define WM8995_WSEQ_DATA_START86_SHIFT 0 /* WSEQ_DATA_START86 - [3:0] */
7271#define WM8995_WSEQ_DATA_START86_WIDTH 4 /* WSEQ_DATA_START86 - [3:0] */
7272
7273/*
7274 * R12635 (0x315B) - Write Sequencer 347
7275 */
7276#define WM8995_WSEQ_EOS86 0x0100 /* WSEQ_EOS86 */
7277#define WM8995_WSEQ_EOS86_MASK 0x0100 /* WSEQ_EOS86 */
7278#define WM8995_WSEQ_EOS86_SHIFT 8 /* WSEQ_EOS86 */
7279#define WM8995_WSEQ_EOS86_WIDTH 1 /* WSEQ_EOS86 */
7280#define WM8995_WSEQ_DELAY86_MASK 0x000F /* WSEQ_DELAY86 - [3:0] */
7281#define WM8995_WSEQ_DELAY86_SHIFT 0 /* WSEQ_DELAY86 - [3:0] */
7282#define WM8995_WSEQ_DELAY86_WIDTH 4 /* WSEQ_DELAY86 - [3:0] */
7283
7284/*
7285 * R12636 (0x315C) - Write Sequencer 348
7286 */
7287#define WM8995_WSEQ_ADDR87_MASK 0x3FFF /* WSEQ_ADDR87 - [13:0] */
7288#define WM8995_WSEQ_ADDR87_SHIFT 0 /* WSEQ_ADDR87 - [13:0] */
7289#define WM8995_WSEQ_ADDR87_WIDTH 14 /* WSEQ_ADDR87 - [13:0] */
7290
7291/*
7292 * R12637 (0x315D) - Write Sequencer 349
7293 */
7294#define WM8995_WSEQ_DATA87_MASK 0x00FF /* WSEQ_DATA87 - [7:0] */
7295#define WM8995_WSEQ_DATA87_SHIFT 0 /* WSEQ_DATA87 - [7:0] */
7296#define WM8995_WSEQ_DATA87_WIDTH 8 /* WSEQ_DATA87 - [7:0] */
7297
7298/*
7299 * R12638 (0x315E) - Write Sequencer 350
7300 */
7301#define WM8995_WSEQ_DATA_WIDTH87_MASK 0x0700 /* WSEQ_DATA_WIDTH87 - [10:8] */
7302#define WM8995_WSEQ_DATA_WIDTH87_SHIFT 8 /* WSEQ_DATA_WIDTH87 - [10:8] */
7303#define WM8995_WSEQ_DATA_WIDTH87_WIDTH 3 /* WSEQ_DATA_WIDTH87 - [10:8] */
7304#define WM8995_WSEQ_DATA_START87_MASK 0x000F /* WSEQ_DATA_START87 - [3:0] */
7305#define WM8995_WSEQ_DATA_START87_SHIFT 0 /* WSEQ_DATA_START87 - [3:0] */
7306#define WM8995_WSEQ_DATA_START87_WIDTH 4 /* WSEQ_DATA_START87 - [3:0] */
7307
7308/*
7309 * R12639 (0x315F) - Write Sequencer 351
7310 */
7311#define WM8995_WSEQ_EOS87 0x0100 /* WSEQ_EOS87 */
7312#define WM8995_WSEQ_EOS87_MASK 0x0100 /* WSEQ_EOS87 */
7313#define WM8995_WSEQ_EOS87_SHIFT 8 /* WSEQ_EOS87 */
7314#define WM8995_WSEQ_EOS87_WIDTH 1 /* WSEQ_EOS87 */
7315#define WM8995_WSEQ_DELAY87_MASK 0x000F /* WSEQ_DELAY87 - [3:0] */
7316#define WM8995_WSEQ_DELAY87_SHIFT 0 /* WSEQ_DELAY87 - [3:0] */
7317#define WM8995_WSEQ_DELAY87_WIDTH 4 /* WSEQ_DELAY87 - [3:0] */
7318
7319/*
7320 * R12640 (0x3160) - Write Sequencer 352
7321 */
7322#define WM8995_WSEQ_ADDR88_MASK 0x3FFF /* WSEQ_ADDR88 - [13:0] */
7323#define WM8995_WSEQ_ADDR88_SHIFT 0 /* WSEQ_ADDR88 - [13:0] */
7324#define WM8995_WSEQ_ADDR88_WIDTH 14 /* WSEQ_ADDR88 - [13:0] */
7325
7326/*
7327 * R12641 (0x3161) - Write Sequencer 353
7328 */
7329#define WM8995_WSEQ_DATA88_MASK 0x00FF /* WSEQ_DATA88 - [7:0] */
7330#define WM8995_WSEQ_DATA88_SHIFT 0 /* WSEQ_DATA88 - [7:0] */
7331#define WM8995_WSEQ_DATA88_WIDTH 8 /* WSEQ_DATA88 - [7:0] */
7332
7333/*
7334 * R12642 (0x3162) - Write Sequencer 354
7335 */
7336#define WM8995_WSEQ_DATA_WIDTH88_MASK 0x0700 /* WSEQ_DATA_WIDTH88 - [10:8] */
7337#define WM8995_WSEQ_DATA_WIDTH88_SHIFT 8 /* WSEQ_DATA_WIDTH88 - [10:8] */
7338#define WM8995_WSEQ_DATA_WIDTH88_WIDTH 3 /* WSEQ_DATA_WIDTH88 - [10:8] */
7339#define WM8995_WSEQ_DATA_START88_MASK 0x000F /* WSEQ_DATA_START88 - [3:0] */
7340#define WM8995_WSEQ_DATA_START88_SHIFT 0 /* WSEQ_DATA_START88 - [3:0] */
7341#define WM8995_WSEQ_DATA_START88_WIDTH 4 /* WSEQ_DATA_START88 - [3:0] */
7342
7343/*
7344 * R12643 (0x3163) - Write Sequencer 355
7345 */
7346#define WM8995_WSEQ_EOS88 0x0100 /* WSEQ_EOS88 */
7347#define WM8995_WSEQ_EOS88_MASK 0x0100 /* WSEQ_EOS88 */
7348#define WM8995_WSEQ_EOS88_SHIFT 8 /* WSEQ_EOS88 */
7349#define WM8995_WSEQ_EOS88_WIDTH 1 /* WSEQ_EOS88 */
7350#define WM8995_WSEQ_DELAY88_MASK 0x000F /* WSEQ_DELAY88 - [3:0] */
7351#define WM8995_WSEQ_DELAY88_SHIFT 0 /* WSEQ_DELAY88 - [3:0] */
7352#define WM8995_WSEQ_DELAY88_WIDTH 4 /* WSEQ_DELAY88 - [3:0] */
7353
7354/*
7355 * R12644 (0x3164) - Write Sequencer 356
7356 */
7357#define WM8995_WSEQ_ADDR89_MASK 0x3FFF /* WSEQ_ADDR89 - [13:0] */
7358#define WM8995_WSEQ_ADDR89_SHIFT 0 /* WSEQ_ADDR89 - [13:0] */
7359#define WM8995_WSEQ_ADDR89_WIDTH 14 /* WSEQ_ADDR89 - [13:0] */
7360
7361/*
7362 * R12645 (0x3165) - Write Sequencer 357
7363 */
7364#define WM8995_WSEQ_DATA89_MASK 0x00FF /* WSEQ_DATA89 - [7:0] */
7365#define WM8995_WSEQ_DATA89_SHIFT 0 /* WSEQ_DATA89 - [7:0] */
7366#define WM8995_WSEQ_DATA89_WIDTH 8 /* WSEQ_DATA89 - [7:0] */
7367
7368/*
7369 * R12646 (0x3166) - Write Sequencer 358
7370 */
7371#define WM8995_WSEQ_DATA_WIDTH89_MASK 0x0700 /* WSEQ_DATA_WIDTH89 - [10:8] */
7372#define WM8995_WSEQ_DATA_WIDTH89_SHIFT 8 /* WSEQ_DATA_WIDTH89 - [10:8] */
7373#define WM8995_WSEQ_DATA_WIDTH89_WIDTH 3 /* WSEQ_DATA_WIDTH89 - [10:8] */
7374#define WM8995_WSEQ_DATA_START89_MASK 0x000F /* WSEQ_DATA_START89 - [3:0] */
7375#define WM8995_WSEQ_DATA_START89_SHIFT 0 /* WSEQ_DATA_START89 - [3:0] */
7376#define WM8995_WSEQ_DATA_START89_WIDTH 4 /* WSEQ_DATA_START89 - [3:0] */
7377
7378/*
7379 * R12647 (0x3167) - Write Sequencer 359
7380 */
7381#define WM8995_WSEQ_EOS89 0x0100 /* WSEQ_EOS89 */
7382#define WM8995_WSEQ_EOS89_MASK 0x0100 /* WSEQ_EOS89 */
7383#define WM8995_WSEQ_EOS89_SHIFT 8 /* WSEQ_EOS89 */
7384#define WM8995_WSEQ_EOS89_WIDTH 1 /* WSEQ_EOS89 */
7385#define WM8995_WSEQ_DELAY89_MASK 0x000F /* WSEQ_DELAY89 - [3:0] */
7386#define WM8995_WSEQ_DELAY89_SHIFT 0 /* WSEQ_DELAY89 - [3:0] */
7387#define WM8995_WSEQ_DELAY89_WIDTH 4 /* WSEQ_DELAY89 - [3:0] */
7388
7389/*
7390 * R12648 (0x3168) - Write Sequencer 360
7391 */
7392#define WM8995_WSEQ_ADDR90_MASK 0x3FFF /* WSEQ_ADDR90 - [13:0] */
7393#define WM8995_WSEQ_ADDR90_SHIFT 0 /* WSEQ_ADDR90 - [13:0] */
7394#define WM8995_WSEQ_ADDR90_WIDTH 14 /* WSEQ_ADDR90 - [13:0] */
7395
7396/*
7397 * R12649 (0x3169) - Write Sequencer 361
7398 */
7399#define WM8995_WSEQ_DATA90_MASK 0x00FF /* WSEQ_DATA90 - [7:0] */
7400#define WM8995_WSEQ_DATA90_SHIFT 0 /* WSEQ_DATA90 - [7:0] */
7401#define WM8995_WSEQ_DATA90_WIDTH 8 /* WSEQ_DATA90 - [7:0] */
7402
7403/*
7404 * R12650 (0x316A) - Write Sequencer 362
7405 */
7406#define WM8995_WSEQ_DATA_WIDTH90_MASK 0x0700 /* WSEQ_DATA_WIDTH90 - [10:8] */
7407#define WM8995_WSEQ_DATA_WIDTH90_SHIFT 8 /* WSEQ_DATA_WIDTH90 - [10:8] */
7408#define WM8995_WSEQ_DATA_WIDTH90_WIDTH 3 /* WSEQ_DATA_WIDTH90 - [10:8] */
7409#define WM8995_WSEQ_DATA_START90_MASK 0x000F /* WSEQ_DATA_START90 - [3:0] */
7410#define WM8995_WSEQ_DATA_START90_SHIFT 0 /* WSEQ_DATA_START90 - [3:0] */
7411#define WM8995_WSEQ_DATA_START90_WIDTH 4 /* WSEQ_DATA_START90 - [3:0] */
7412
7413/*
7414 * R12651 (0x316B) - Write Sequencer 363
7415 */
7416#define WM8995_WSEQ_EOS90 0x0100 /* WSEQ_EOS90 */
7417#define WM8995_WSEQ_EOS90_MASK 0x0100 /* WSEQ_EOS90 */
7418#define WM8995_WSEQ_EOS90_SHIFT 8 /* WSEQ_EOS90 */
7419#define WM8995_WSEQ_EOS90_WIDTH 1 /* WSEQ_EOS90 */
7420#define WM8995_WSEQ_DELAY90_MASK 0x000F /* WSEQ_DELAY90 - [3:0] */
7421#define WM8995_WSEQ_DELAY90_SHIFT 0 /* WSEQ_DELAY90 - [3:0] */
7422#define WM8995_WSEQ_DELAY90_WIDTH 4 /* WSEQ_DELAY90 - [3:0] */
7423
7424/*
7425 * R12652 (0x316C) - Write Sequencer 364
7426 */
7427#define WM8995_WSEQ_ADDR91_MASK 0x3FFF /* WSEQ_ADDR91 - [13:0] */
7428#define WM8995_WSEQ_ADDR91_SHIFT 0 /* WSEQ_ADDR91 - [13:0] */
7429#define WM8995_WSEQ_ADDR91_WIDTH 14 /* WSEQ_ADDR91 - [13:0] */
7430
7431/*
7432 * R12653 (0x316D) - Write Sequencer 365
7433 */
7434#define WM8995_WSEQ_DATA91_MASK 0x00FF /* WSEQ_DATA91 - [7:0] */
7435#define WM8995_WSEQ_DATA91_SHIFT 0 /* WSEQ_DATA91 - [7:0] */
7436#define WM8995_WSEQ_DATA91_WIDTH 8 /* WSEQ_DATA91 - [7:0] */
7437
7438/*
7439 * R12654 (0x316E) - Write Sequencer 366
7440 */
7441#define WM8995_WSEQ_DATA_WIDTH91_MASK 0x0700 /* WSEQ_DATA_WIDTH91 - [10:8] */
7442#define WM8995_WSEQ_DATA_WIDTH91_SHIFT 8 /* WSEQ_DATA_WIDTH91 - [10:8] */
7443#define WM8995_WSEQ_DATA_WIDTH91_WIDTH 3 /* WSEQ_DATA_WIDTH91 - [10:8] */
7444#define WM8995_WSEQ_DATA_START91_MASK 0x000F /* WSEQ_DATA_START91 - [3:0] */
7445#define WM8995_WSEQ_DATA_START91_SHIFT 0 /* WSEQ_DATA_START91 - [3:0] */
7446#define WM8995_WSEQ_DATA_START91_WIDTH 4 /* WSEQ_DATA_START91 - [3:0] */
7447
7448/*
7449 * R12655 (0x316F) - Write Sequencer 367
7450 */
7451#define WM8995_WSEQ_EOS91 0x0100 /* WSEQ_EOS91 */
7452#define WM8995_WSEQ_EOS91_MASK 0x0100 /* WSEQ_EOS91 */
7453#define WM8995_WSEQ_EOS91_SHIFT 8 /* WSEQ_EOS91 */
7454#define WM8995_WSEQ_EOS91_WIDTH 1 /* WSEQ_EOS91 */
7455#define WM8995_WSEQ_DELAY91_MASK 0x000F /* WSEQ_DELAY91 - [3:0] */
7456#define WM8995_WSEQ_DELAY91_SHIFT 0 /* WSEQ_DELAY91 - [3:0] */
7457#define WM8995_WSEQ_DELAY91_WIDTH 4 /* WSEQ_DELAY91 - [3:0] */
7458
7459/*
7460 * R12656 (0x3170) - Write Sequencer 368
7461 */
7462#define WM8995_WSEQ_ADDR92_MASK 0x3FFF /* WSEQ_ADDR92 - [13:0] */
7463#define WM8995_WSEQ_ADDR92_SHIFT 0 /* WSEQ_ADDR92 - [13:0] */
7464#define WM8995_WSEQ_ADDR92_WIDTH 14 /* WSEQ_ADDR92 - [13:0] */
7465
7466/*
7467 * R12657 (0x3171) - Write Sequencer 369
7468 */
7469#define WM8995_WSEQ_DATA92_MASK 0x00FF /* WSEQ_DATA92 - [7:0] */
7470#define WM8995_WSEQ_DATA92_SHIFT 0 /* WSEQ_DATA92 - [7:0] */
7471#define WM8995_WSEQ_DATA92_WIDTH 8 /* WSEQ_DATA92 - [7:0] */
7472
7473/*
7474 * R12658 (0x3172) - Write Sequencer 370
7475 */
7476#define WM8995_WSEQ_DATA_WIDTH92_MASK 0x0700 /* WSEQ_DATA_WIDTH92 - [10:8] */
7477#define WM8995_WSEQ_DATA_WIDTH92_SHIFT 8 /* WSEQ_DATA_WIDTH92 - [10:8] */
7478#define WM8995_WSEQ_DATA_WIDTH92_WIDTH 3 /* WSEQ_DATA_WIDTH92 - [10:8] */
7479#define WM8995_WSEQ_DATA_START92_MASK 0x000F /* WSEQ_DATA_START92 - [3:0] */
7480#define WM8995_WSEQ_DATA_START92_SHIFT 0 /* WSEQ_DATA_START92 - [3:0] */
7481#define WM8995_WSEQ_DATA_START92_WIDTH 4 /* WSEQ_DATA_START92 - [3:0] */
7482
7483/*
7484 * R12659 (0x3173) - Write Sequencer 371
7485 */
7486#define WM8995_WSEQ_EOS92 0x0100 /* WSEQ_EOS92 */
7487#define WM8995_WSEQ_EOS92_MASK 0x0100 /* WSEQ_EOS92 */
7488#define WM8995_WSEQ_EOS92_SHIFT 8 /* WSEQ_EOS92 */
7489#define WM8995_WSEQ_EOS92_WIDTH 1 /* WSEQ_EOS92 */
7490#define WM8995_WSEQ_DELAY92_MASK 0x000F /* WSEQ_DELAY92 - [3:0] */
7491#define WM8995_WSEQ_DELAY92_SHIFT 0 /* WSEQ_DELAY92 - [3:0] */
7492#define WM8995_WSEQ_DELAY92_WIDTH 4 /* WSEQ_DELAY92 - [3:0] */
7493
7494/*
7495 * R12660 (0x3174) - Write Sequencer 372
7496 */
7497#define WM8995_WSEQ_ADDR93_MASK 0x3FFF /* WSEQ_ADDR93 - [13:0] */
7498#define WM8995_WSEQ_ADDR93_SHIFT 0 /* WSEQ_ADDR93 - [13:0] */
7499#define WM8995_WSEQ_ADDR93_WIDTH 14 /* WSEQ_ADDR93 - [13:0] */
7500
7501/*
7502 * R12661 (0x3175) - Write Sequencer 373
7503 */
7504#define WM8995_WSEQ_DATA93_MASK 0x00FF /* WSEQ_DATA93 - [7:0] */
7505#define WM8995_WSEQ_DATA93_SHIFT 0 /* WSEQ_DATA93 - [7:0] */
7506#define WM8995_WSEQ_DATA93_WIDTH 8 /* WSEQ_DATA93 - [7:0] */
7507
7508/*
7509 * R12662 (0x3176) - Write Sequencer 374
7510 */
7511#define WM8995_WSEQ_DATA_WIDTH93_MASK 0x0700 /* WSEQ_DATA_WIDTH93 - [10:8] */
7512#define WM8995_WSEQ_DATA_WIDTH93_SHIFT 8 /* WSEQ_DATA_WIDTH93 - [10:8] */
7513#define WM8995_WSEQ_DATA_WIDTH93_WIDTH 3 /* WSEQ_DATA_WIDTH93 - [10:8] */
7514#define WM8995_WSEQ_DATA_START93_MASK 0x000F /* WSEQ_DATA_START93 - [3:0] */
7515#define WM8995_WSEQ_DATA_START93_SHIFT 0 /* WSEQ_DATA_START93 - [3:0] */
7516#define WM8995_WSEQ_DATA_START93_WIDTH 4 /* WSEQ_DATA_START93 - [3:0] */
7517
7518/*
7519 * R12663 (0x3177) - Write Sequencer 375
7520 */
7521#define WM8995_WSEQ_EOS93 0x0100 /* WSEQ_EOS93 */
7522#define WM8995_WSEQ_EOS93_MASK 0x0100 /* WSEQ_EOS93 */
7523#define WM8995_WSEQ_EOS93_SHIFT 8 /* WSEQ_EOS93 */
7524#define WM8995_WSEQ_EOS93_WIDTH 1 /* WSEQ_EOS93 */
7525#define WM8995_WSEQ_DELAY93_MASK 0x000F /* WSEQ_DELAY93 - [3:0] */
7526#define WM8995_WSEQ_DELAY93_SHIFT 0 /* WSEQ_DELAY93 - [3:0] */
7527#define WM8995_WSEQ_DELAY93_WIDTH 4 /* WSEQ_DELAY93 - [3:0] */
7528
7529/*
7530 * R12664 (0x3178) - Write Sequencer 376
7531 */
7532#define WM8995_WSEQ_ADDR94_MASK 0x3FFF /* WSEQ_ADDR94 - [13:0] */
7533#define WM8995_WSEQ_ADDR94_SHIFT 0 /* WSEQ_ADDR94 - [13:0] */
7534#define WM8995_WSEQ_ADDR94_WIDTH 14 /* WSEQ_ADDR94 - [13:0] */
7535
7536/*
7537 * R12665 (0x3179) - Write Sequencer 377
7538 */
7539#define WM8995_WSEQ_DATA94_MASK 0x00FF /* WSEQ_DATA94 - [7:0] */
7540#define WM8995_WSEQ_DATA94_SHIFT 0 /* WSEQ_DATA94 - [7:0] */
7541#define WM8995_WSEQ_DATA94_WIDTH 8 /* WSEQ_DATA94 - [7:0] */
7542
7543/*
7544 * R12666 (0x317A) - Write Sequencer 378
7545 */
7546#define WM8995_WSEQ_DATA_WIDTH94_MASK 0x0700 /* WSEQ_DATA_WIDTH94 - [10:8] */
7547#define WM8995_WSEQ_DATA_WIDTH94_SHIFT 8 /* WSEQ_DATA_WIDTH94 - [10:8] */
7548#define WM8995_WSEQ_DATA_WIDTH94_WIDTH 3 /* WSEQ_DATA_WIDTH94 - [10:8] */
7549#define WM8995_WSEQ_DATA_START94_MASK 0x000F /* WSEQ_DATA_START94 - [3:0] */
7550#define WM8995_WSEQ_DATA_START94_SHIFT 0 /* WSEQ_DATA_START94 - [3:0] */
7551#define WM8995_WSEQ_DATA_START94_WIDTH 4 /* WSEQ_DATA_START94 - [3:0] */
7552
7553/*
7554 * R12667 (0x317B) - Write Sequencer 379
7555 */
7556#define WM8995_WSEQ_EOS94 0x0100 /* WSEQ_EOS94 */
7557#define WM8995_WSEQ_EOS94_MASK 0x0100 /* WSEQ_EOS94 */
7558#define WM8995_WSEQ_EOS94_SHIFT 8 /* WSEQ_EOS94 */
7559#define WM8995_WSEQ_EOS94_WIDTH 1 /* WSEQ_EOS94 */
7560#define WM8995_WSEQ_DELAY94_MASK 0x000F /* WSEQ_DELAY94 - [3:0] */
7561#define WM8995_WSEQ_DELAY94_SHIFT 0 /* WSEQ_DELAY94 - [3:0] */
7562#define WM8995_WSEQ_DELAY94_WIDTH 4 /* WSEQ_DELAY94 - [3:0] */
7563
7564/*
7565 * R12668 (0x317C) - Write Sequencer 380
7566 */
7567#define WM8995_WSEQ_ADDR95_MASK 0x3FFF /* WSEQ_ADDR95 - [13:0] */
7568#define WM8995_WSEQ_ADDR95_SHIFT 0 /* WSEQ_ADDR95 - [13:0] */
7569#define WM8995_WSEQ_ADDR95_WIDTH 14 /* WSEQ_ADDR95 - [13:0] */
7570
7571/*
7572 * R12669 (0x317D) - Write Sequencer 381
7573 */
7574#define WM8995_WSEQ_DATA95_MASK 0x00FF /* WSEQ_DATA95 - [7:0] */
7575#define WM8995_WSEQ_DATA95_SHIFT 0 /* WSEQ_DATA95 - [7:0] */
7576#define WM8995_WSEQ_DATA95_WIDTH 8 /* WSEQ_DATA95 - [7:0] */
7577
7578/*
7579 * R12670 (0x317E) - Write Sequencer 382
7580 */
7581#define WM8995_WSEQ_DATA_WIDTH95_MASK 0x0700 /* WSEQ_DATA_WIDTH95 - [10:8] */
7582#define WM8995_WSEQ_DATA_WIDTH95_SHIFT 8 /* WSEQ_DATA_WIDTH95 - [10:8] */
7583#define WM8995_WSEQ_DATA_WIDTH95_WIDTH 3 /* WSEQ_DATA_WIDTH95 - [10:8] */
7584#define WM8995_WSEQ_DATA_START95_MASK 0x000F /* WSEQ_DATA_START95 - [3:0] */
7585#define WM8995_WSEQ_DATA_START95_SHIFT 0 /* WSEQ_DATA_START95 - [3:0] */
7586#define WM8995_WSEQ_DATA_START95_WIDTH 4 /* WSEQ_DATA_START95 - [3:0] */
7587
7588/*
7589 * R12671 (0x317F) - Write Sequencer 383
7590 */
7591#define WM8995_WSEQ_EOS95 0x0100 /* WSEQ_EOS95 */
7592#define WM8995_WSEQ_EOS95_MASK 0x0100 /* WSEQ_EOS95 */
7593#define WM8995_WSEQ_EOS95_SHIFT 8 /* WSEQ_EOS95 */
7594#define WM8995_WSEQ_EOS95_WIDTH 1 /* WSEQ_EOS95 */
7595#define WM8995_WSEQ_DELAY95_MASK 0x000F /* WSEQ_DELAY95 - [3:0] */
7596#define WM8995_WSEQ_DELAY95_SHIFT 0 /* WSEQ_DELAY95 - [3:0] */
7597#define WM8995_WSEQ_DELAY95_WIDTH 4 /* WSEQ_DELAY95 - [3:0] */
7598
7599/*
7600 * R12672 (0x3180) - Write Sequencer 384
7601 */
7602#define WM8995_WSEQ_ADDR96_MASK 0x3FFF /* WSEQ_ADDR96 - [13:0] */
7603#define WM8995_WSEQ_ADDR96_SHIFT 0 /* WSEQ_ADDR96 - [13:0] */
7604#define WM8995_WSEQ_ADDR96_WIDTH 14 /* WSEQ_ADDR96 - [13:0] */
7605
7606/*
7607 * R12673 (0x3181) - Write Sequencer 385
7608 */
7609#define WM8995_WSEQ_DATA96_MASK 0x00FF /* WSEQ_DATA96 - [7:0] */
7610#define WM8995_WSEQ_DATA96_SHIFT 0 /* WSEQ_DATA96 - [7:0] */
7611#define WM8995_WSEQ_DATA96_WIDTH 8 /* WSEQ_DATA96 - [7:0] */
7612
7613/*
7614 * R12674 (0x3182) - Write Sequencer 386
7615 */
7616#define WM8995_WSEQ_DATA_WIDTH96_MASK 0x0700 /* WSEQ_DATA_WIDTH96 - [10:8] */
7617#define WM8995_WSEQ_DATA_WIDTH96_SHIFT 8 /* WSEQ_DATA_WIDTH96 - [10:8] */
7618#define WM8995_WSEQ_DATA_WIDTH96_WIDTH 3 /* WSEQ_DATA_WIDTH96 - [10:8] */
7619#define WM8995_WSEQ_DATA_START96_MASK 0x000F /* WSEQ_DATA_START96 - [3:0] */
7620#define WM8995_WSEQ_DATA_START96_SHIFT 0 /* WSEQ_DATA_START96 - [3:0] */
7621#define WM8995_WSEQ_DATA_START96_WIDTH 4 /* WSEQ_DATA_START96 - [3:0] */
7622
7623/*
7624 * R12675 (0x3183) - Write Sequencer 387
7625 */
7626#define WM8995_WSEQ_EOS96 0x0100 /* WSEQ_EOS96 */
7627#define WM8995_WSEQ_EOS96_MASK 0x0100 /* WSEQ_EOS96 */
7628#define WM8995_WSEQ_EOS96_SHIFT 8 /* WSEQ_EOS96 */
7629#define WM8995_WSEQ_EOS96_WIDTH 1 /* WSEQ_EOS96 */
7630#define WM8995_WSEQ_DELAY96_MASK 0x000F /* WSEQ_DELAY96 - [3:0] */
7631#define WM8995_WSEQ_DELAY96_SHIFT 0 /* WSEQ_DELAY96 - [3:0] */
7632#define WM8995_WSEQ_DELAY96_WIDTH 4 /* WSEQ_DELAY96 - [3:0] */
7633
7634/*
7635 * R12676 (0x3184) - Write Sequencer 388
7636 */
7637#define WM8995_WSEQ_ADDR97_MASK 0x3FFF /* WSEQ_ADDR97 - [13:0] */
7638#define WM8995_WSEQ_ADDR97_SHIFT 0 /* WSEQ_ADDR97 - [13:0] */
7639#define WM8995_WSEQ_ADDR97_WIDTH 14 /* WSEQ_ADDR97 - [13:0] */
7640
7641/*
7642 * R12677 (0x3185) - Write Sequencer 389
7643 */
7644#define WM8995_WSEQ_DATA97_MASK 0x00FF /* WSEQ_DATA97 - [7:0] */
7645#define WM8995_WSEQ_DATA97_SHIFT 0 /* WSEQ_DATA97 - [7:0] */
7646#define WM8995_WSEQ_DATA97_WIDTH 8 /* WSEQ_DATA97 - [7:0] */
7647
7648/*
7649 * R12678 (0x3186) - Write Sequencer 390
7650 */
7651#define WM8995_WSEQ_DATA_WIDTH97_MASK 0x0700 /* WSEQ_DATA_WIDTH97 - [10:8] */
7652#define WM8995_WSEQ_DATA_WIDTH97_SHIFT 8 /* WSEQ_DATA_WIDTH97 - [10:8] */
7653#define WM8995_WSEQ_DATA_WIDTH97_WIDTH 3 /* WSEQ_DATA_WIDTH97 - [10:8] */
7654#define WM8995_WSEQ_DATA_START97_MASK 0x000F /* WSEQ_DATA_START97 - [3:0] */
7655#define WM8995_WSEQ_DATA_START97_SHIFT 0 /* WSEQ_DATA_START97 - [3:0] */
7656#define WM8995_WSEQ_DATA_START97_WIDTH 4 /* WSEQ_DATA_START97 - [3:0] */
7657
7658/*
7659 * R12679 (0x3187) - Write Sequencer 391
7660 */
7661#define WM8995_WSEQ_EOS97 0x0100 /* WSEQ_EOS97 */
7662#define WM8995_WSEQ_EOS97_MASK 0x0100 /* WSEQ_EOS97 */
7663#define WM8995_WSEQ_EOS97_SHIFT 8 /* WSEQ_EOS97 */
7664#define WM8995_WSEQ_EOS97_WIDTH 1 /* WSEQ_EOS97 */
7665#define WM8995_WSEQ_DELAY97_MASK 0x000F /* WSEQ_DELAY97 - [3:0] */
7666#define WM8995_WSEQ_DELAY97_SHIFT 0 /* WSEQ_DELAY97 - [3:0] */
7667#define WM8995_WSEQ_DELAY97_WIDTH 4 /* WSEQ_DELAY97 - [3:0] */
7668
7669/*
7670 * R12680 (0x3188) - Write Sequencer 392
7671 */
7672#define WM8995_WSEQ_ADDR98_MASK 0x3FFF /* WSEQ_ADDR98 - [13:0] */
7673#define WM8995_WSEQ_ADDR98_SHIFT 0 /* WSEQ_ADDR98 - [13:0] */
7674#define WM8995_WSEQ_ADDR98_WIDTH 14 /* WSEQ_ADDR98 - [13:0] */
7675
7676/*
7677 * R12681 (0x3189) - Write Sequencer 393
7678 */
7679#define WM8995_WSEQ_DATA98_MASK 0x00FF /* WSEQ_DATA98 - [7:0] */
7680#define WM8995_WSEQ_DATA98_SHIFT 0 /* WSEQ_DATA98 - [7:0] */
7681#define WM8995_WSEQ_DATA98_WIDTH 8 /* WSEQ_DATA98 - [7:0] */
7682
7683/*
7684 * R12682 (0x318A) - Write Sequencer 394
7685 */
7686#define WM8995_WSEQ_DATA_WIDTH98_MASK 0x0700 /* WSEQ_DATA_WIDTH98 - [10:8] */
7687#define WM8995_WSEQ_DATA_WIDTH98_SHIFT 8 /* WSEQ_DATA_WIDTH98 - [10:8] */
7688#define WM8995_WSEQ_DATA_WIDTH98_WIDTH 3 /* WSEQ_DATA_WIDTH98 - [10:8] */
7689#define WM8995_WSEQ_DATA_START98_MASK 0x000F /* WSEQ_DATA_START98 - [3:0] */
7690#define WM8995_WSEQ_DATA_START98_SHIFT 0 /* WSEQ_DATA_START98 - [3:0] */
7691#define WM8995_WSEQ_DATA_START98_WIDTH 4 /* WSEQ_DATA_START98 - [3:0] */
7692
7693/*
7694 * R12683 (0x318B) - Write Sequencer 395
7695 */
7696#define WM8995_WSEQ_EOS98 0x0100 /* WSEQ_EOS98 */
7697#define WM8995_WSEQ_EOS98_MASK 0x0100 /* WSEQ_EOS98 */
7698#define WM8995_WSEQ_EOS98_SHIFT 8 /* WSEQ_EOS98 */
7699#define WM8995_WSEQ_EOS98_WIDTH 1 /* WSEQ_EOS98 */
7700#define WM8995_WSEQ_DELAY98_MASK 0x000F /* WSEQ_DELAY98 - [3:0] */
7701#define WM8995_WSEQ_DELAY98_SHIFT 0 /* WSEQ_DELAY98 - [3:0] */
7702#define WM8995_WSEQ_DELAY98_WIDTH 4 /* WSEQ_DELAY98 - [3:0] */
7703
7704/*
7705 * R12684 (0x318C) - Write Sequencer 396
7706 */
7707#define WM8995_WSEQ_ADDR99_MASK 0x3FFF /* WSEQ_ADDR99 - [13:0] */
7708#define WM8995_WSEQ_ADDR99_SHIFT 0 /* WSEQ_ADDR99 - [13:0] */
7709#define WM8995_WSEQ_ADDR99_WIDTH 14 /* WSEQ_ADDR99 - [13:0] */
7710
7711/*
7712 * R12685 (0x318D) - Write Sequencer 397
7713 */
7714#define WM8995_WSEQ_DATA99_MASK 0x00FF /* WSEQ_DATA99 - [7:0] */
7715#define WM8995_WSEQ_DATA99_SHIFT 0 /* WSEQ_DATA99 - [7:0] */
7716#define WM8995_WSEQ_DATA99_WIDTH 8 /* WSEQ_DATA99 - [7:0] */
7717
7718/*
7719 * R12686 (0x318E) - Write Sequencer 398
7720 */
7721#define WM8995_WSEQ_DATA_WIDTH99_MASK 0x0700 /* WSEQ_DATA_WIDTH99 - [10:8] */
7722#define WM8995_WSEQ_DATA_WIDTH99_SHIFT 8 /* WSEQ_DATA_WIDTH99 - [10:8] */
7723#define WM8995_WSEQ_DATA_WIDTH99_WIDTH 3 /* WSEQ_DATA_WIDTH99 - [10:8] */
7724#define WM8995_WSEQ_DATA_START99_MASK 0x000F /* WSEQ_DATA_START99 - [3:0] */
7725#define WM8995_WSEQ_DATA_START99_SHIFT 0 /* WSEQ_DATA_START99 - [3:0] */
7726#define WM8995_WSEQ_DATA_START99_WIDTH 4 /* WSEQ_DATA_START99 - [3:0] */
7727
7728/*
7729 * R12687 (0x318F) - Write Sequencer 399
7730 */
7731#define WM8995_WSEQ_EOS99 0x0100 /* WSEQ_EOS99 */
7732#define WM8995_WSEQ_EOS99_MASK 0x0100 /* WSEQ_EOS99 */
7733#define WM8995_WSEQ_EOS99_SHIFT 8 /* WSEQ_EOS99 */
7734#define WM8995_WSEQ_EOS99_WIDTH 1 /* WSEQ_EOS99 */
7735#define WM8995_WSEQ_DELAY99_MASK 0x000F /* WSEQ_DELAY99 - [3:0] */
7736#define WM8995_WSEQ_DELAY99_SHIFT 0 /* WSEQ_DELAY99 - [3:0] */
7737#define WM8995_WSEQ_DELAY99_WIDTH 4 /* WSEQ_DELAY99 - [3:0] */
7738
7739/*
7740 * R12688 (0x3190) - Write Sequencer 400
7741 */
7742#define WM8995_WSEQ_ADDR100_MASK 0x3FFF /* WSEQ_ADDR100 - [13:0] */
7743#define WM8995_WSEQ_ADDR100_SHIFT 0 /* WSEQ_ADDR100 - [13:0] */
7744#define WM8995_WSEQ_ADDR100_WIDTH 14 /* WSEQ_ADDR100 - [13:0] */
7745
7746/*
7747 * R12689 (0x3191) - Write Sequencer 401
7748 */
7749#define WM8995_WSEQ_DATA100_MASK 0x00FF /* WSEQ_DATA100 - [7:0] */
7750#define WM8995_WSEQ_DATA100_SHIFT 0 /* WSEQ_DATA100 - [7:0] */
7751#define WM8995_WSEQ_DATA100_WIDTH 8 /* WSEQ_DATA100 - [7:0] */
7752
7753/*
7754 * R12690 (0x3192) - Write Sequencer 402
7755 */
7756#define WM8995_WSEQ_DATA_WIDTH100_MASK 0x0700 /* WSEQ_DATA_WIDTH100 - [10:8] */
7757#define WM8995_WSEQ_DATA_WIDTH100_SHIFT 8 /* WSEQ_DATA_WIDTH100 - [10:8] */
7758#define WM8995_WSEQ_DATA_WIDTH100_WIDTH 3 /* WSEQ_DATA_WIDTH100 - [10:8] */
7759#define WM8995_WSEQ_DATA_START100_MASK 0x000F /* WSEQ_DATA_START100 - [3:0] */
7760#define WM8995_WSEQ_DATA_START100_SHIFT 0 /* WSEQ_DATA_START100 - [3:0] */
7761#define WM8995_WSEQ_DATA_START100_WIDTH 4 /* WSEQ_DATA_START100 - [3:0] */
7762
7763/*
7764 * R12691 (0x3193) - Write Sequencer 403
7765 */
7766#define WM8995_WSEQ_EOS100 0x0100 /* WSEQ_EOS100 */
7767#define WM8995_WSEQ_EOS100_MASK 0x0100 /* WSEQ_EOS100 */
7768#define WM8995_WSEQ_EOS100_SHIFT 8 /* WSEQ_EOS100 */
7769#define WM8995_WSEQ_EOS100_WIDTH 1 /* WSEQ_EOS100 */
7770#define WM8995_WSEQ_DELAY100_MASK 0x000F /* WSEQ_DELAY100 - [3:0] */
7771#define WM8995_WSEQ_DELAY100_SHIFT 0 /* WSEQ_DELAY100 - [3:0] */
7772#define WM8995_WSEQ_DELAY100_WIDTH 4 /* WSEQ_DELAY100 - [3:0] */
7773
7774/*
7775 * R12692 (0x3194) - Write Sequencer 404
7776 */
7777#define WM8995_WSEQ_ADDR101_MASK 0x3FFF /* WSEQ_ADDR101 - [13:0] */
7778#define WM8995_WSEQ_ADDR101_SHIFT 0 /* WSEQ_ADDR101 - [13:0] */
7779#define WM8995_WSEQ_ADDR101_WIDTH 14 /* WSEQ_ADDR101 - [13:0] */
7780
7781/*
7782 * R12693 (0x3195) - Write Sequencer 405
7783 */
7784#define WM8995_WSEQ_DATA101_MASK 0x00FF /* WSEQ_DATA101 - [7:0] */
7785#define WM8995_WSEQ_DATA101_SHIFT 0 /* WSEQ_DATA101 - [7:0] */
7786#define WM8995_WSEQ_DATA101_WIDTH 8 /* WSEQ_DATA101 - [7:0] */
7787
7788/*
7789 * R12694 (0x3196) - Write Sequencer 406
7790 */
7791#define WM8995_WSEQ_DATA_WIDTH101_MASK 0x0700 /* WSEQ_DATA_WIDTH101 - [10:8] */
7792#define WM8995_WSEQ_DATA_WIDTH101_SHIFT 8 /* WSEQ_DATA_WIDTH101 - [10:8] */
7793#define WM8995_WSEQ_DATA_WIDTH101_WIDTH 3 /* WSEQ_DATA_WIDTH101 - [10:8] */
7794#define WM8995_WSEQ_DATA_START101_MASK 0x000F /* WSEQ_DATA_START101 - [3:0] */
7795#define WM8995_WSEQ_DATA_START101_SHIFT 0 /* WSEQ_DATA_START101 - [3:0] */
7796#define WM8995_WSEQ_DATA_START101_WIDTH 4 /* WSEQ_DATA_START101 - [3:0] */
7797
7798/*
7799 * R12695 (0x3197) - Write Sequencer 407
7800 */
7801#define WM8995_WSEQ_EOS101 0x0100 /* WSEQ_EOS101 */
7802#define WM8995_WSEQ_EOS101_MASK 0x0100 /* WSEQ_EOS101 */
7803#define WM8995_WSEQ_EOS101_SHIFT 8 /* WSEQ_EOS101 */
7804#define WM8995_WSEQ_EOS101_WIDTH 1 /* WSEQ_EOS101 */
7805#define WM8995_WSEQ_DELAY101_MASK 0x000F /* WSEQ_DELAY101 - [3:0] */
7806#define WM8995_WSEQ_DELAY101_SHIFT 0 /* WSEQ_DELAY101 - [3:0] */
7807#define WM8995_WSEQ_DELAY101_WIDTH 4 /* WSEQ_DELAY101 - [3:0] */
7808
7809/*
7810 * R12696 (0x3198) - Write Sequencer 408
7811 */
7812#define WM8995_WSEQ_ADDR102_MASK 0x3FFF /* WSEQ_ADDR102 - [13:0] */
7813#define WM8995_WSEQ_ADDR102_SHIFT 0 /* WSEQ_ADDR102 - [13:0] */
7814#define WM8995_WSEQ_ADDR102_WIDTH 14 /* WSEQ_ADDR102 - [13:0] */
7815
7816/*
7817 * R12697 (0x3199) - Write Sequencer 409
7818 */
7819#define WM8995_WSEQ_DATA102_MASK 0x00FF /* WSEQ_DATA102 - [7:0] */
7820#define WM8995_WSEQ_DATA102_SHIFT 0 /* WSEQ_DATA102 - [7:0] */
7821#define WM8995_WSEQ_DATA102_WIDTH 8 /* WSEQ_DATA102 - [7:0] */
7822
7823/*
7824 * R12698 (0x319A) - Write Sequencer 410
7825 */
7826#define WM8995_WSEQ_DATA_WIDTH102_MASK 0x0700 /* WSEQ_DATA_WIDTH102 - [10:8] */
7827#define WM8995_WSEQ_DATA_WIDTH102_SHIFT 8 /* WSEQ_DATA_WIDTH102 - [10:8] */
7828#define WM8995_WSEQ_DATA_WIDTH102_WIDTH 3 /* WSEQ_DATA_WIDTH102 - [10:8] */
7829#define WM8995_WSEQ_DATA_START102_MASK 0x000F /* WSEQ_DATA_START102 - [3:0] */
7830#define WM8995_WSEQ_DATA_START102_SHIFT 0 /* WSEQ_DATA_START102 - [3:0] */
7831#define WM8995_WSEQ_DATA_START102_WIDTH 4 /* WSEQ_DATA_START102 - [3:0] */
7832
7833/*
7834 * R12699 (0x319B) - Write Sequencer 411
7835 */
7836#define WM8995_WSEQ_EOS102 0x0100 /* WSEQ_EOS102 */
7837#define WM8995_WSEQ_EOS102_MASK 0x0100 /* WSEQ_EOS102 */
7838#define WM8995_WSEQ_EOS102_SHIFT 8 /* WSEQ_EOS102 */
7839#define WM8995_WSEQ_EOS102_WIDTH 1 /* WSEQ_EOS102 */
7840#define WM8995_WSEQ_DELAY102_MASK 0x000F /* WSEQ_DELAY102 - [3:0] */
7841#define WM8995_WSEQ_DELAY102_SHIFT 0 /* WSEQ_DELAY102 - [3:0] */
7842#define WM8995_WSEQ_DELAY102_WIDTH 4 /* WSEQ_DELAY102 - [3:0] */
7843
7844/*
7845 * R12700 (0x319C) - Write Sequencer 412
7846 */
7847#define WM8995_WSEQ_ADDR103_MASK 0x3FFF /* WSEQ_ADDR103 - [13:0] */
7848#define WM8995_WSEQ_ADDR103_SHIFT 0 /* WSEQ_ADDR103 - [13:0] */
7849#define WM8995_WSEQ_ADDR103_WIDTH 14 /* WSEQ_ADDR103 - [13:0] */
7850
7851/*
7852 * R12701 (0x319D) - Write Sequencer 413
7853 */
7854#define WM8995_WSEQ_DATA103_MASK 0x00FF /* WSEQ_DATA103 - [7:0] */
7855#define WM8995_WSEQ_DATA103_SHIFT 0 /* WSEQ_DATA103 - [7:0] */
7856#define WM8995_WSEQ_DATA103_WIDTH 8 /* WSEQ_DATA103 - [7:0] */
7857
7858/*
7859 * R12702 (0x319E) - Write Sequencer 414
7860 */
7861#define WM8995_WSEQ_DATA_WIDTH103_MASK 0x0700 /* WSEQ_DATA_WIDTH103 - [10:8] */
7862#define WM8995_WSEQ_DATA_WIDTH103_SHIFT 8 /* WSEQ_DATA_WIDTH103 - [10:8] */
7863#define WM8995_WSEQ_DATA_WIDTH103_WIDTH 3 /* WSEQ_DATA_WIDTH103 - [10:8] */
7864#define WM8995_WSEQ_DATA_START103_MASK 0x000F /* WSEQ_DATA_START103 - [3:0] */
7865#define WM8995_WSEQ_DATA_START103_SHIFT 0 /* WSEQ_DATA_START103 - [3:0] */
7866#define WM8995_WSEQ_DATA_START103_WIDTH 4 /* WSEQ_DATA_START103 - [3:0] */
7867
7868/*
7869 * R12703 (0x319F) - Write Sequencer 415
7870 */
7871#define WM8995_WSEQ_EOS103 0x0100 /* WSEQ_EOS103 */
7872#define WM8995_WSEQ_EOS103_MASK 0x0100 /* WSEQ_EOS103 */
7873#define WM8995_WSEQ_EOS103_SHIFT 8 /* WSEQ_EOS103 */
7874#define WM8995_WSEQ_EOS103_WIDTH 1 /* WSEQ_EOS103 */
7875#define WM8995_WSEQ_DELAY103_MASK 0x000F /* WSEQ_DELAY103 - [3:0] */
7876#define WM8995_WSEQ_DELAY103_SHIFT 0 /* WSEQ_DELAY103 - [3:0] */
7877#define WM8995_WSEQ_DELAY103_WIDTH 4 /* WSEQ_DELAY103 - [3:0] */
7878
7879/*
7880 * R12704 (0x31A0) - Write Sequencer 416
7881 */
7882#define WM8995_WSEQ_ADDR104_MASK 0x3FFF /* WSEQ_ADDR104 - [13:0] */
7883#define WM8995_WSEQ_ADDR104_SHIFT 0 /* WSEQ_ADDR104 - [13:0] */
7884#define WM8995_WSEQ_ADDR104_WIDTH 14 /* WSEQ_ADDR104 - [13:0] */
7885
7886/*
7887 * R12705 (0x31A1) - Write Sequencer 417
7888 */
7889#define WM8995_WSEQ_DATA104_MASK 0x00FF /* WSEQ_DATA104 - [7:0] */
7890#define WM8995_WSEQ_DATA104_SHIFT 0 /* WSEQ_DATA104 - [7:0] */
7891#define WM8995_WSEQ_DATA104_WIDTH 8 /* WSEQ_DATA104 - [7:0] */
7892
7893/*
7894 * R12706 (0x31A2) - Write Sequencer 418
7895 */
7896#define WM8995_WSEQ_DATA_WIDTH104_MASK 0x0700 /* WSEQ_DATA_WIDTH104 - [10:8] */
7897#define WM8995_WSEQ_DATA_WIDTH104_SHIFT 8 /* WSEQ_DATA_WIDTH104 - [10:8] */
7898#define WM8995_WSEQ_DATA_WIDTH104_WIDTH 3 /* WSEQ_DATA_WIDTH104 - [10:8] */
7899#define WM8995_WSEQ_DATA_START104_MASK 0x000F /* WSEQ_DATA_START104 - [3:0] */
7900#define WM8995_WSEQ_DATA_START104_SHIFT 0 /* WSEQ_DATA_START104 - [3:0] */
7901#define WM8995_WSEQ_DATA_START104_WIDTH 4 /* WSEQ_DATA_START104 - [3:0] */
7902
7903/*
7904 * R12707 (0x31A3) - Write Sequencer 419
7905 */
7906#define WM8995_WSEQ_EOS104 0x0100 /* WSEQ_EOS104 */
7907#define WM8995_WSEQ_EOS104_MASK 0x0100 /* WSEQ_EOS104 */
7908#define WM8995_WSEQ_EOS104_SHIFT 8 /* WSEQ_EOS104 */
7909#define WM8995_WSEQ_EOS104_WIDTH 1 /* WSEQ_EOS104 */
7910#define WM8995_WSEQ_DELAY104_MASK 0x000F /* WSEQ_DELAY104 - [3:0] */
7911#define WM8995_WSEQ_DELAY104_SHIFT 0 /* WSEQ_DELAY104 - [3:0] */
7912#define WM8995_WSEQ_DELAY104_WIDTH 4 /* WSEQ_DELAY104 - [3:0] */
7913
7914/*
7915 * R12708 (0x31A4) - Write Sequencer 420
7916 */
7917#define WM8995_WSEQ_ADDR105_MASK 0x3FFF /* WSEQ_ADDR105 - [13:0] */
7918#define WM8995_WSEQ_ADDR105_SHIFT 0 /* WSEQ_ADDR105 - [13:0] */
7919#define WM8995_WSEQ_ADDR105_WIDTH 14 /* WSEQ_ADDR105 - [13:0] */
7920
7921/*
7922 * R12709 (0x31A5) - Write Sequencer 421
7923 */
7924#define WM8995_WSEQ_DATA105_MASK 0x00FF /* WSEQ_DATA105 - [7:0] */
7925#define WM8995_WSEQ_DATA105_SHIFT 0 /* WSEQ_DATA105 - [7:0] */
7926#define WM8995_WSEQ_DATA105_WIDTH 8 /* WSEQ_DATA105 - [7:0] */
7927
7928/*
7929 * R12710 (0x31A6) - Write Sequencer 422
7930 */
7931#define WM8995_WSEQ_DATA_WIDTH105_MASK 0x0700 /* WSEQ_DATA_WIDTH105 - [10:8] */
7932#define WM8995_WSEQ_DATA_WIDTH105_SHIFT 8 /* WSEQ_DATA_WIDTH105 - [10:8] */
7933#define WM8995_WSEQ_DATA_WIDTH105_WIDTH 3 /* WSEQ_DATA_WIDTH105 - [10:8] */
7934#define WM8995_WSEQ_DATA_START105_MASK 0x000F /* WSEQ_DATA_START105 - [3:0] */
7935#define WM8995_WSEQ_DATA_START105_SHIFT 0 /* WSEQ_DATA_START105 - [3:0] */
7936#define WM8995_WSEQ_DATA_START105_WIDTH 4 /* WSEQ_DATA_START105 - [3:0] */
7937
7938/*
7939 * R12711 (0x31A7) - Write Sequencer 423
7940 */
7941#define WM8995_WSEQ_EOS105 0x0100 /* WSEQ_EOS105 */
7942#define WM8995_WSEQ_EOS105_MASK 0x0100 /* WSEQ_EOS105 */
7943#define WM8995_WSEQ_EOS105_SHIFT 8 /* WSEQ_EOS105 */
7944#define WM8995_WSEQ_EOS105_WIDTH 1 /* WSEQ_EOS105 */
7945#define WM8995_WSEQ_DELAY105_MASK 0x000F /* WSEQ_DELAY105 - [3:0] */
7946#define WM8995_WSEQ_DELAY105_SHIFT 0 /* WSEQ_DELAY105 - [3:0] */
7947#define WM8995_WSEQ_DELAY105_WIDTH 4 /* WSEQ_DELAY105 - [3:0] */
7948
7949/*
7950 * R12712 (0x31A8) - Write Sequencer 424
7951 */
7952#define WM8995_WSEQ_ADDR106_MASK 0x3FFF /* WSEQ_ADDR106 - [13:0] */
7953#define WM8995_WSEQ_ADDR106_SHIFT 0 /* WSEQ_ADDR106 - [13:0] */
7954#define WM8995_WSEQ_ADDR106_WIDTH 14 /* WSEQ_ADDR106 - [13:0] */
7955
7956/*
7957 * R12713 (0x31A9) - Write Sequencer 425
7958 */
7959#define WM8995_WSEQ_DATA106_MASK 0x00FF /* WSEQ_DATA106 - [7:0] */
7960#define WM8995_WSEQ_DATA106_SHIFT 0 /* WSEQ_DATA106 - [7:0] */
7961#define WM8995_WSEQ_DATA106_WIDTH 8 /* WSEQ_DATA106 - [7:0] */
7962
7963/*
7964 * R12714 (0x31AA) - Write Sequencer 426
7965 */
7966#define WM8995_WSEQ_DATA_WIDTH106_MASK 0x0700 /* WSEQ_DATA_WIDTH106 - [10:8] */
7967#define WM8995_WSEQ_DATA_WIDTH106_SHIFT 8 /* WSEQ_DATA_WIDTH106 - [10:8] */
7968#define WM8995_WSEQ_DATA_WIDTH106_WIDTH 3 /* WSEQ_DATA_WIDTH106 - [10:8] */
7969#define WM8995_WSEQ_DATA_START106_MASK 0x000F /* WSEQ_DATA_START106 - [3:0] */
7970#define WM8995_WSEQ_DATA_START106_SHIFT 0 /* WSEQ_DATA_START106 - [3:0] */
7971#define WM8995_WSEQ_DATA_START106_WIDTH 4 /* WSEQ_DATA_START106 - [3:0] */
7972
7973/*
7974 * R12715 (0x31AB) - Write Sequencer 427
7975 */
7976#define WM8995_WSEQ_EOS106 0x0100 /* WSEQ_EOS106 */
7977#define WM8995_WSEQ_EOS106_MASK 0x0100 /* WSEQ_EOS106 */
7978#define WM8995_WSEQ_EOS106_SHIFT 8 /* WSEQ_EOS106 */
7979#define WM8995_WSEQ_EOS106_WIDTH 1 /* WSEQ_EOS106 */
7980#define WM8995_WSEQ_DELAY106_MASK 0x000F /* WSEQ_DELAY106 - [3:0] */
7981#define WM8995_WSEQ_DELAY106_SHIFT 0 /* WSEQ_DELAY106 - [3:0] */
7982#define WM8995_WSEQ_DELAY106_WIDTH 4 /* WSEQ_DELAY106 - [3:0] */
7983
7984/*
7985 * R12716 (0x31AC) - Write Sequencer 428
7986 */
7987#define WM8995_WSEQ_ADDR107_MASK 0x3FFF /* WSEQ_ADDR107 - [13:0] */
7988#define WM8995_WSEQ_ADDR107_SHIFT 0 /* WSEQ_ADDR107 - [13:0] */
7989#define WM8995_WSEQ_ADDR107_WIDTH 14 /* WSEQ_ADDR107 - [13:0] */
7990
7991/*
7992 * R12717 (0x31AD) - Write Sequencer 429
7993 */
7994#define WM8995_WSEQ_DATA107_MASK 0x00FF /* WSEQ_DATA107 - [7:0] */
7995#define WM8995_WSEQ_DATA107_SHIFT 0 /* WSEQ_DATA107 - [7:0] */
7996#define WM8995_WSEQ_DATA107_WIDTH 8 /* WSEQ_DATA107 - [7:0] */
7997
7998/*
7999 * R12718 (0x31AE) - Write Sequencer 430
8000 */
8001#define WM8995_WSEQ_DATA_WIDTH107_MASK 0x0700 /* WSEQ_DATA_WIDTH107 - [10:8] */
8002#define WM8995_WSEQ_DATA_WIDTH107_SHIFT 8 /* WSEQ_DATA_WIDTH107 - [10:8] */
8003#define WM8995_WSEQ_DATA_WIDTH107_WIDTH 3 /* WSEQ_DATA_WIDTH107 - [10:8] */
8004#define WM8995_WSEQ_DATA_START107_MASK 0x000F /* WSEQ_DATA_START107 - [3:0] */
8005#define WM8995_WSEQ_DATA_START107_SHIFT 0 /* WSEQ_DATA_START107 - [3:0] */
8006#define WM8995_WSEQ_DATA_START107_WIDTH 4 /* WSEQ_DATA_START107 - [3:0] */
8007
8008/*
8009 * R12719 (0x31AF) - Write Sequencer 431
8010 */
8011#define WM8995_WSEQ_EOS107 0x0100 /* WSEQ_EOS107 */
8012#define WM8995_WSEQ_EOS107_MASK 0x0100 /* WSEQ_EOS107 */
8013#define WM8995_WSEQ_EOS107_SHIFT 8 /* WSEQ_EOS107 */
8014#define WM8995_WSEQ_EOS107_WIDTH 1 /* WSEQ_EOS107 */
8015#define WM8995_WSEQ_DELAY107_MASK 0x000F /* WSEQ_DELAY107 - [3:0] */
8016#define WM8995_WSEQ_DELAY107_SHIFT 0 /* WSEQ_DELAY107 - [3:0] */
8017#define WM8995_WSEQ_DELAY107_WIDTH 4 /* WSEQ_DELAY107 - [3:0] */
8018
8019/*
8020 * R12720 (0x31B0) - Write Sequencer 432
8021 */
8022#define WM8995_WSEQ_ADDR108_MASK 0x3FFF /* WSEQ_ADDR108 - [13:0] */
8023#define WM8995_WSEQ_ADDR108_SHIFT 0 /* WSEQ_ADDR108 - [13:0] */
8024#define WM8995_WSEQ_ADDR108_WIDTH 14 /* WSEQ_ADDR108 - [13:0] */
8025
8026/*
8027 * R12721 (0x31B1) - Write Sequencer 433
8028 */
8029#define WM8995_WSEQ_DATA108_MASK 0x00FF /* WSEQ_DATA108 - [7:0] */
8030#define WM8995_WSEQ_DATA108_SHIFT 0 /* WSEQ_DATA108 - [7:0] */
8031#define WM8995_WSEQ_DATA108_WIDTH 8 /* WSEQ_DATA108 - [7:0] */
8032
8033/*
8034 * R12722 (0x31B2) - Write Sequencer 434
8035 */
8036#define WM8995_WSEQ_DATA_WIDTH108_MASK 0x0700 /* WSEQ_DATA_WIDTH108 - [10:8] */
8037#define WM8995_WSEQ_DATA_WIDTH108_SHIFT 8 /* WSEQ_DATA_WIDTH108 - [10:8] */
8038#define WM8995_WSEQ_DATA_WIDTH108_WIDTH 3 /* WSEQ_DATA_WIDTH108 - [10:8] */
8039#define WM8995_WSEQ_DATA_START108_MASK 0x000F /* WSEQ_DATA_START108 - [3:0] */
8040#define WM8995_WSEQ_DATA_START108_SHIFT 0 /* WSEQ_DATA_START108 - [3:0] */
8041#define WM8995_WSEQ_DATA_START108_WIDTH 4 /* WSEQ_DATA_START108 - [3:0] */
8042
8043/*
8044 * R12723 (0x31B3) - Write Sequencer 435
8045 */
8046#define WM8995_WSEQ_EOS108 0x0100 /* WSEQ_EOS108 */
8047#define WM8995_WSEQ_EOS108_MASK 0x0100 /* WSEQ_EOS108 */
8048#define WM8995_WSEQ_EOS108_SHIFT 8 /* WSEQ_EOS108 */
8049#define WM8995_WSEQ_EOS108_WIDTH 1 /* WSEQ_EOS108 */
8050#define WM8995_WSEQ_DELAY108_MASK 0x000F /* WSEQ_DELAY108 - [3:0] */
8051#define WM8995_WSEQ_DELAY108_SHIFT 0 /* WSEQ_DELAY108 - [3:0] */
8052#define WM8995_WSEQ_DELAY108_WIDTH 4 /* WSEQ_DELAY108 - [3:0] */
8053
8054/*
8055 * R12724 (0x31B4) - Write Sequencer 436
8056 */
8057#define WM8995_WSEQ_ADDR109_MASK 0x3FFF /* WSEQ_ADDR109 - [13:0] */
8058#define WM8995_WSEQ_ADDR109_SHIFT 0 /* WSEQ_ADDR109 - [13:0] */
8059#define WM8995_WSEQ_ADDR109_WIDTH 14 /* WSEQ_ADDR109 - [13:0] */
8060
8061/*
8062 * R12725 (0x31B5) - Write Sequencer 437
8063 */
8064#define WM8995_WSEQ_DATA109_MASK 0x00FF /* WSEQ_DATA109 - [7:0] */
8065#define WM8995_WSEQ_DATA109_SHIFT 0 /* WSEQ_DATA109 - [7:0] */
8066#define WM8995_WSEQ_DATA109_WIDTH 8 /* WSEQ_DATA109 - [7:0] */
8067
8068/*
8069 * R12726 (0x31B6) - Write Sequencer 438
8070 */
8071#define WM8995_WSEQ_DATA_WIDTH109_MASK 0x0700 /* WSEQ_DATA_WIDTH109 - [10:8] */
8072#define WM8995_WSEQ_DATA_WIDTH109_SHIFT 8 /* WSEQ_DATA_WIDTH109 - [10:8] */
8073#define WM8995_WSEQ_DATA_WIDTH109_WIDTH 3 /* WSEQ_DATA_WIDTH109 - [10:8] */
8074#define WM8995_WSEQ_DATA_START109_MASK 0x000F /* WSEQ_DATA_START109 - [3:0] */
8075#define WM8995_WSEQ_DATA_START109_SHIFT 0 /* WSEQ_DATA_START109 - [3:0] */
8076#define WM8995_WSEQ_DATA_START109_WIDTH 4 /* WSEQ_DATA_START109 - [3:0] */
8077
8078/*
8079 * R12727 (0x31B7) - Write Sequencer 439
8080 */
8081#define WM8995_WSEQ_EOS109 0x0100 /* WSEQ_EOS109 */
8082#define WM8995_WSEQ_EOS109_MASK 0x0100 /* WSEQ_EOS109 */
8083#define WM8995_WSEQ_EOS109_SHIFT 8 /* WSEQ_EOS109 */
8084#define WM8995_WSEQ_EOS109_WIDTH 1 /* WSEQ_EOS109 */
8085#define WM8995_WSEQ_DELAY109_MASK 0x000F /* WSEQ_DELAY109 - [3:0] */
8086#define WM8995_WSEQ_DELAY109_SHIFT 0 /* WSEQ_DELAY109 - [3:0] */
8087#define WM8995_WSEQ_DELAY109_WIDTH 4 /* WSEQ_DELAY109 - [3:0] */
8088
8089/*
8090 * R12728 (0x31B8) - Write Sequencer 440
8091 */
8092#define WM8995_WSEQ_ADDR110_MASK 0x3FFF /* WSEQ_ADDR110 - [13:0] */
8093#define WM8995_WSEQ_ADDR110_SHIFT 0 /* WSEQ_ADDR110 - [13:0] */
8094#define WM8995_WSEQ_ADDR110_WIDTH 14 /* WSEQ_ADDR110 - [13:0] */
8095
8096/*
8097 * R12729 (0x31B9) - Write Sequencer 441
8098 */
8099#define WM8995_WSEQ_DATA110_MASK 0x00FF /* WSEQ_DATA110 - [7:0] */
8100#define WM8995_WSEQ_DATA110_SHIFT 0 /* WSEQ_DATA110 - [7:0] */
8101#define WM8995_WSEQ_DATA110_WIDTH 8 /* WSEQ_DATA110 - [7:0] */
8102
8103/*
8104 * R12730 (0x31BA) - Write Sequencer 442
8105 */
8106#define WM8995_WSEQ_DATA_WIDTH110_MASK 0x0700 /* WSEQ_DATA_WIDTH110 - [10:8] */
8107#define WM8995_WSEQ_DATA_WIDTH110_SHIFT 8 /* WSEQ_DATA_WIDTH110 - [10:8] */
8108#define WM8995_WSEQ_DATA_WIDTH110_WIDTH 3 /* WSEQ_DATA_WIDTH110 - [10:8] */
8109#define WM8995_WSEQ_DATA_START110_MASK 0x000F /* WSEQ_DATA_START110 - [3:0] */
8110#define WM8995_WSEQ_DATA_START110_SHIFT 0 /* WSEQ_DATA_START110 - [3:0] */
8111#define WM8995_WSEQ_DATA_START110_WIDTH 4 /* WSEQ_DATA_START110 - [3:0] */
8112
8113/*
8114 * R12731 (0x31BB) - Write Sequencer 443
8115 */
8116#define WM8995_WSEQ_EOS110 0x0100 /* WSEQ_EOS110 */
8117#define WM8995_WSEQ_EOS110_MASK 0x0100 /* WSEQ_EOS110 */
8118#define WM8995_WSEQ_EOS110_SHIFT 8 /* WSEQ_EOS110 */
8119#define WM8995_WSEQ_EOS110_WIDTH 1 /* WSEQ_EOS110 */
8120#define WM8995_WSEQ_DELAY110_MASK 0x000F /* WSEQ_DELAY110 - [3:0] */
8121#define WM8995_WSEQ_DELAY110_SHIFT 0 /* WSEQ_DELAY110 - [3:0] */
8122#define WM8995_WSEQ_DELAY110_WIDTH 4 /* WSEQ_DELAY110 - [3:0] */
8123
8124/*
8125 * R12732 (0x31BC) - Write Sequencer 444
8126 */
8127#define WM8995_WSEQ_ADDR111_MASK 0x3FFF /* WSEQ_ADDR111 - [13:0] */
8128#define WM8995_WSEQ_ADDR111_SHIFT 0 /* WSEQ_ADDR111 - [13:0] */
8129#define WM8995_WSEQ_ADDR111_WIDTH 14 /* WSEQ_ADDR111 - [13:0] */
8130
8131/*
8132 * R12733 (0x31BD) - Write Sequencer 445
8133 */
8134#define WM8995_WSEQ_DATA111_MASK 0x00FF /* WSEQ_DATA111 - [7:0] */
8135#define WM8995_WSEQ_DATA111_SHIFT 0 /* WSEQ_DATA111 - [7:0] */
8136#define WM8995_WSEQ_DATA111_WIDTH 8 /* WSEQ_DATA111 - [7:0] */
8137
8138/*
8139 * R12734 (0x31BE) - Write Sequencer 446
8140 */
8141#define WM8995_WSEQ_DATA_WIDTH111_MASK 0x0700 /* WSEQ_DATA_WIDTH111 - [10:8] */
8142#define WM8995_WSEQ_DATA_WIDTH111_SHIFT 8 /* WSEQ_DATA_WIDTH111 - [10:8] */
8143#define WM8995_WSEQ_DATA_WIDTH111_WIDTH 3 /* WSEQ_DATA_WIDTH111 - [10:8] */
8144#define WM8995_WSEQ_DATA_START111_MASK 0x000F /* WSEQ_DATA_START111 - [3:0] */
8145#define WM8995_WSEQ_DATA_START111_SHIFT 0 /* WSEQ_DATA_START111 - [3:0] */
8146#define WM8995_WSEQ_DATA_START111_WIDTH 4 /* WSEQ_DATA_START111 - [3:0] */
8147
8148/*
8149 * R12735 (0x31BF) - Write Sequencer 447
8150 */
8151#define WM8995_WSEQ_EOS111 0x0100 /* WSEQ_EOS111 */
8152#define WM8995_WSEQ_EOS111_MASK 0x0100 /* WSEQ_EOS111 */
8153#define WM8995_WSEQ_EOS111_SHIFT 8 /* WSEQ_EOS111 */
8154#define WM8995_WSEQ_EOS111_WIDTH 1 /* WSEQ_EOS111 */
8155#define WM8995_WSEQ_DELAY111_MASK 0x000F /* WSEQ_DELAY111 - [3:0] */
8156#define WM8995_WSEQ_DELAY111_SHIFT 0 /* WSEQ_DELAY111 - [3:0] */
8157#define WM8995_WSEQ_DELAY111_WIDTH 4 /* WSEQ_DELAY111 - [3:0] */
8158
8159/*
8160 * R12736 (0x31C0) - Write Sequencer 448
8161 */
8162#define WM8995_WSEQ_ADDR112_MASK 0x3FFF /* WSEQ_ADDR112 - [13:0] */
8163#define WM8995_WSEQ_ADDR112_SHIFT 0 /* WSEQ_ADDR112 - [13:0] */
8164#define WM8995_WSEQ_ADDR112_WIDTH 14 /* WSEQ_ADDR112 - [13:0] */
8165
8166/*
8167 * R12737 (0x31C1) - Write Sequencer 449
8168 */
8169#define WM8995_WSEQ_DATA112_MASK 0x00FF /* WSEQ_DATA112 - [7:0] */
8170#define WM8995_WSEQ_DATA112_SHIFT 0 /* WSEQ_DATA112 - [7:0] */
8171#define WM8995_WSEQ_DATA112_WIDTH 8 /* WSEQ_DATA112 - [7:0] */
8172
8173/*
8174 * R12738 (0x31C2) - Write Sequencer 450
8175 */
8176#define WM8995_WSEQ_DATA_WIDTH112_MASK 0x0700 /* WSEQ_DATA_WIDTH112 - [10:8] */
8177#define WM8995_WSEQ_DATA_WIDTH112_SHIFT 8 /* WSEQ_DATA_WIDTH112 - [10:8] */
8178#define WM8995_WSEQ_DATA_WIDTH112_WIDTH 3 /* WSEQ_DATA_WIDTH112 - [10:8] */
8179#define WM8995_WSEQ_DATA_START112_MASK 0x000F /* WSEQ_DATA_START112 - [3:0] */
8180#define WM8995_WSEQ_DATA_START112_SHIFT 0 /* WSEQ_DATA_START112 - [3:0] */
8181#define WM8995_WSEQ_DATA_START112_WIDTH 4 /* WSEQ_DATA_START112 - [3:0] */
8182
8183/*
8184 * R12739 (0x31C3) - Write Sequencer 451
8185 */
8186#define WM8995_WSEQ_EOS112 0x0100 /* WSEQ_EOS112 */
8187#define WM8995_WSEQ_EOS112_MASK 0x0100 /* WSEQ_EOS112 */
8188#define WM8995_WSEQ_EOS112_SHIFT 8 /* WSEQ_EOS112 */
8189#define WM8995_WSEQ_EOS112_WIDTH 1 /* WSEQ_EOS112 */
8190#define WM8995_WSEQ_DELAY112_MASK 0x000F /* WSEQ_DELAY112 - [3:0] */
8191#define WM8995_WSEQ_DELAY112_SHIFT 0 /* WSEQ_DELAY112 - [3:0] */
8192#define WM8995_WSEQ_DELAY112_WIDTH 4 /* WSEQ_DELAY112 - [3:0] */
8193
8194/*
8195 * R12740 (0x31C4) - Write Sequencer 452
8196 */
8197#define WM8995_WSEQ_ADDR113_MASK 0x3FFF /* WSEQ_ADDR113 - [13:0] */
8198#define WM8995_WSEQ_ADDR113_SHIFT 0 /* WSEQ_ADDR113 - [13:0] */
8199#define WM8995_WSEQ_ADDR113_WIDTH 14 /* WSEQ_ADDR113 - [13:0] */
8200
8201/*
8202 * R12741 (0x31C5) - Write Sequencer 453
8203 */
8204#define WM8995_WSEQ_DATA113_MASK 0x00FF /* WSEQ_DATA113 - [7:0] */
8205#define WM8995_WSEQ_DATA113_SHIFT 0 /* WSEQ_DATA113 - [7:0] */
8206#define WM8995_WSEQ_DATA113_WIDTH 8 /* WSEQ_DATA113 - [7:0] */
8207
8208/*
8209 * R12742 (0x31C6) - Write Sequencer 454
8210 */
8211#define WM8995_WSEQ_DATA_WIDTH113_MASK 0x0700 /* WSEQ_DATA_WIDTH113 - [10:8] */
8212#define WM8995_WSEQ_DATA_WIDTH113_SHIFT 8 /* WSEQ_DATA_WIDTH113 - [10:8] */
8213#define WM8995_WSEQ_DATA_WIDTH113_WIDTH 3 /* WSEQ_DATA_WIDTH113 - [10:8] */
8214#define WM8995_WSEQ_DATA_START113_MASK 0x000F /* WSEQ_DATA_START113 - [3:0] */
8215#define WM8995_WSEQ_DATA_START113_SHIFT 0 /* WSEQ_DATA_START113 - [3:0] */
8216#define WM8995_WSEQ_DATA_START113_WIDTH 4 /* WSEQ_DATA_START113 - [3:0] */
8217
8218/*
8219 * R12743 (0x31C7) - Write Sequencer 455
8220 */
8221#define WM8995_WSEQ_EOS113 0x0100 /* WSEQ_EOS113 */
8222#define WM8995_WSEQ_EOS113_MASK 0x0100 /* WSEQ_EOS113 */
8223#define WM8995_WSEQ_EOS113_SHIFT 8 /* WSEQ_EOS113 */
8224#define WM8995_WSEQ_EOS113_WIDTH 1 /* WSEQ_EOS113 */
8225#define WM8995_WSEQ_DELAY113_MASK 0x000F /* WSEQ_DELAY113 - [3:0] */
8226#define WM8995_WSEQ_DELAY113_SHIFT 0 /* WSEQ_DELAY113 - [3:0] */
8227#define WM8995_WSEQ_DELAY113_WIDTH 4 /* WSEQ_DELAY113 - [3:0] */
8228
8229/*
8230 * R12744 (0x31C8) - Write Sequencer 456
8231 */
8232#define WM8995_WSEQ_ADDR114_MASK 0x3FFF /* WSEQ_ADDR114 - [13:0] */
8233#define WM8995_WSEQ_ADDR114_SHIFT 0 /* WSEQ_ADDR114 - [13:0] */
8234#define WM8995_WSEQ_ADDR114_WIDTH 14 /* WSEQ_ADDR114 - [13:0] */
8235
8236/*
8237 * R12745 (0x31C9) - Write Sequencer 457
8238 */
8239#define WM8995_WSEQ_DATA114_MASK 0x00FF /* WSEQ_DATA114 - [7:0] */
8240#define WM8995_WSEQ_DATA114_SHIFT 0 /* WSEQ_DATA114 - [7:0] */
8241#define WM8995_WSEQ_DATA114_WIDTH 8 /* WSEQ_DATA114 - [7:0] */
8242
8243/*
8244 * R12746 (0x31CA) - Write Sequencer 458
8245 */
8246#define WM8995_WSEQ_DATA_WIDTH114_MASK 0x0700 /* WSEQ_DATA_WIDTH114 - [10:8] */
8247#define WM8995_WSEQ_DATA_WIDTH114_SHIFT 8 /* WSEQ_DATA_WIDTH114 - [10:8] */
8248#define WM8995_WSEQ_DATA_WIDTH114_WIDTH 3 /* WSEQ_DATA_WIDTH114 - [10:8] */
8249#define WM8995_WSEQ_DATA_START114_MASK 0x000F /* WSEQ_DATA_START114 - [3:0] */
8250#define WM8995_WSEQ_DATA_START114_SHIFT 0 /* WSEQ_DATA_START114 - [3:0] */
8251#define WM8995_WSEQ_DATA_START114_WIDTH 4 /* WSEQ_DATA_START114 - [3:0] */
8252
8253/*
8254 * R12747 (0x31CB) - Write Sequencer 459
8255 */
8256#define WM8995_WSEQ_EOS114 0x0100 /* WSEQ_EOS114 */
8257#define WM8995_WSEQ_EOS114_MASK 0x0100 /* WSEQ_EOS114 */
8258#define WM8995_WSEQ_EOS114_SHIFT 8 /* WSEQ_EOS114 */
8259#define WM8995_WSEQ_EOS114_WIDTH 1 /* WSEQ_EOS114 */
8260#define WM8995_WSEQ_DELAY114_MASK 0x000F /* WSEQ_DELAY114 - [3:0] */
8261#define WM8995_WSEQ_DELAY114_SHIFT 0 /* WSEQ_DELAY114 - [3:0] */
8262#define WM8995_WSEQ_DELAY114_WIDTH 4 /* WSEQ_DELAY114 - [3:0] */
8263
8264/*
8265 * R12748 (0x31CC) - Write Sequencer 460
8266 */
8267#define WM8995_WSEQ_ADDR115_MASK 0x3FFF /* WSEQ_ADDR115 - [13:0] */
8268#define WM8995_WSEQ_ADDR115_SHIFT 0 /* WSEQ_ADDR115 - [13:0] */
8269#define WM8995_WSEQ_ADDR115_WIDTH 14 /* WSEQ_ADDR115 - [13:0] */
8270
8271/*
8272 * R12749 (0x31CD) - Write Sequencer 461
8273 */
8274#define WM8995_WSEQ_DATA115_MASK 0x00FF /* WSEQ_DATA115 - [7:0] */
8275#define WM8995_WSEQ_DATA115_SHIFT 0 /* WSEQ_DATA115 - [7:0] */
8276#define WM8995_WSEQ_DATA115_WIDTH 8 /* WSEQ_DATA115 - [7:0] */
8277
8278/*
8279 * R12750 (0x31CE) - Write Sequencer 462
8280 */
8281#define WM8995_WSEQ_DATA_WIDTH115_MASK 0x0700 /* WSEQ_DATA_WIDTH115 - [10:8] */
8282#define WM8995_WSEQ_DATA_WIDTH115_SHIFT 8 /* WSEQ_DATA_WIDTH115 - [10:8] */
8283#define WM8995_WSEQ_DATA_WIDTH115_WIDTH 3 /* WSEQ_DATA_WIDTH115 - [10:8] */
8284#define WM8995_WSEQ_DATA_START115_MASK 0x000F /* WSEQ_DATA_START115 - [3:0] */
8285#define WM8995_WSEQ_DATA_START115_SHIFT 0 /* WSEQ_DATA_START115 - [3:0] */
8286#define WM8995_WSEQ_DATA_START115_WIDTH 4 /* WSEQ_DATA_START115 - [3:0] */
8287
8288/*
8289 * R12751 (0x31CF) - Write Sequencer 463
8290 */
8291#define WM8995_WSEQ_EOS115 0x0100 /* WSEQ_EOS115 */
8292#define WM8995_WSEQ_EOS115_MASK 0x0100 /* WSEQ_EOS115 */
8293#define WM8995_WSEQ_EOS115_SHIFT 8 /* WSEQ_EOS115 */
8294#define WM8995_WSEQ_EOS115_WIDTH 1 /* WSEQ_EOS115 */
8295#define WM8995_WSEQ_DELAY115_MASK 0x000F /* WSEQ_DELAY115 - [3:0] */
8296#define WM8995_WSEQ_DELAY115_SHIFT 0 /* WSEQ_DELAY115 - [3:0] */
8297#define WM8995_WSEQ_DELAY115_WIDTH 4 /* WSEQ_DELAY115 - [3:0] */
8298
8299/*
8300 * R12752 (0x31D0) - Write Sequencer 464
8301 */
8302#define WM8995_WSEQ_ADDR116_MASK 0x3FFF /* WSEQ_ADDR116 - [13:0] */
8303#define WM8995_WSEQ_ADDR116_SHIFT 0 /* WSEQ_ADDR116 - [13:0] */
8304#define WM8995_WSEQ_ADDR116_WIDTH 14 /* WSEQ_ADDR116 - [13:0] */
8305
8306/*
8307 * R12753 (0x31D1) - Write Sequencer 465
8308 */
8309#define WM8995_WSEQ_DATA116_MASK 0x00FF /* WSEQ_DATA116 - [7:0] */
8310#define WM8995_WSEQ_DATA116_SHIFT 0 /* WSEQ_DATA116 - [7:0] */
8311#define WM8995_WSEQ_DATA116_WIDTH 8 /* WSEQ_DATA116 - [7:0] */
8312
8313/*
8314 * R12754 (0x31D2) - Write Sequencer 466
8315 */
8316#define WM8995_WSEQ_DATA_WIDTH116_MASK 0x0700 /* WSEQ_DATA_WIDTH116 - [10:8] */
8317#define WM8995_WSEQ_DATA_WIDTH116_SHIFT 8 /* WSEQ_DATA_WIDTH116 - [10:8] */
8318#define WM8995_WSEQ_DATA_WIDTH116_WIDTH 3 /* WSEQ_DATA_WIDTH116 - [10:8] */
8319#define WM8995_WSEQ_DATA_START116_MASK 0x000F /* WSEQ_DATA_START116 - [3:0] */
8320#define WM8995_WSEQ_DATA_START116_SHIFT 0 /* WSEQ_DATA_START116 - [3:0] */
8321#define WM8995_WSEQ_DATA_START116_WIDTH 4 /* WSEQ_DATA_START116 - [3:0] */
8322
8323/*
8324 * R12755 (0x31D3) - Write Sequencer 467
8325 */
8326#define WM8995_WSEQ_EOS116 0x0100 /* WSEQ_EOS116 */
8327#define WM8995_WSEQ_EOS116_MASK 0x0100 /* WSEQ_EOS116 */
8328#define WM8995_WSEQ_EOS116_SHIFT 8 /* WSEQ_EOS116 */
8329#define WM8995_WSEQ_EOS116_WIDTH 1 /* WSEQ_EOS116 */
8330#define WM8995_WSEQ_DELAY116_MASK 0x000F /* WSEQ_DELAY116 - [3:0] */
8331#define WM8995_WSEQ_DELAY116_SHIFT 0 /* WSEQ_DELAY116 - [3:0] */
8332#define WM8995_WSEQ_DELAY116_WIDTH 4 /* WSEQ_DELAY116 - [3:0] */
8333
8334/*
8335 * R12756 (0x31D4) - Write Sequencer 468
8336 */
8337#define WM8995_WSEQ_ADDR117_MASK 0x3FFF /* WSEQ_ADDR117 - [13:0] */
8338#define WM8995_WSEQ_ADDR117_SHIFT 0 /* WSEQ_ADDR117 - [13:0] */
8339#define WM8995_WSEQ_ADDR117_WIDTH 14 /* WSEQ_ADDR117 - [13:0] */
8340
8341/*
8342 * R12757 (0x31D5) - Write Sequencer 469
8343 */
8344#define WM8995_WSEQ_DATA117_MASK 0x00FF /* WSEQ_DATA117 - [7:0] */
8345#define WM8995_WSEQ_DATA117_SHIFT 0 /* WSEQ_DATA117 - [7:0] */
8346#define WM8995_WSEQ_DATA117_WIDTH 8 /* WSEQ_DATA117 - [7:0] */
8347
8348/*
8349 * R12758 (0x31D6) - Write Sequencer 470
8350 */
8351#define WM8995_WSEQ_DATA_WIDTH117_MASK 0x0700 /* WSEQ_DATA_WIDTH117 - [10:8] */
8352#define WM8995_WSEQ_DATA_WIDTH117_SHIFT 8 /* WSEQ_DATA_WIDTH117 - [10:8] */
8353#define WM8995_WSEQ_DATA_WIDTH117_WIDTH 3 /* WSEQ_DATA_WIDTH117 - [10:8] */
8354#define WM8995_WSEQ_DATA_START117_MASK 0x000F /* WSEQ_DATA_START117 - [3:0] */
8355#define WM8995_WSEQ_DATA_START117_SHIFT 0 /* WSEQ_DATA_START117 - [3:0] */
8356#define WM8995_WSEQ_DATA_START117_WIDTH 4 /* WSEQ_DATA_START117 - [3:0] */
8357
8358/*
8359 * R12759 (0x31D7) - Write Sequencer 471
8360 */
8361#define WM8995_WSEQ_EOS117 0x0100 /* WSEQ_EOS117 */
8362#define WM8995_WSEQ_EOS117_MASK 0x0100 /* WSEQ_EOS117 */
8363#define WM8995_WSEQ_EOS117_SHIFT 8 /* WSEQ_EOS117 */
8364#define WM8995_WSEQ_EOS117_WIDTH 1 /* WSEQ_EOS117 */
8365#define WM8995_WSEQ_DELAY117_MASK 0x000F /* WSEQ_DELAY117 - [3:0] */
8366#define WM8995_WSEQ_DELAY117_SHIFT 0 /* WSEQ_DELAY117 - [3:0] */
8367#define WM8995_WSEQ_DELAY117_WIDTH 4 /* WSEQ_DELAY117 - [3:0] */
8368
8369/*
8370 * R12760 (0x31D8) - Write Sequencer 472
8371 */
8372#define WM8995_WSEQ_ADDR118_MASK 0x3FFF /* WSEQ_ADDR118 - [13:0] */
8373#define WM8995_WSEQ_ADDR118_SHIFT 0 /* WSEQ_ADDR118 - [13:0] */
8374#define WM8995_WSEQ_ADDR118_WIDTH 14 /* WSEQ_ADDR118 - [13:0] */
8375
8376/*
8377 * R12761 (0x31D9) - Write Sequencer 473
8378 */
8379#define WM8995_WSEQ_DATA118_MASK 0x00FF /* WSEQ_DATA118 - [7:0] */
8380#define WM8995_WSEQ_DATA118_SHIFT 0 /* WSEQ_DATA118 - [7:0] */
8381#define WM8995_WSEQ_DATA118_WIDTH 8 /* WSEQ_DATA118 - [7:0] */
8382
8383/*
8384 * R12762 (0x31DA) - Write Sequencer 474
8385 */
8386#define WM8995_WSEQ_DATA_WIDTH118_MASK 0x0700 /* WSEQ_DATA_WIDTH118 - [10:8] */
8387#define WM8995_WSEQ_DATA_WIDTH118_SHIFT 8 /* WSEQ_DATA_WIDTH118 - [10:8] */
8388#define WM8995_WSEQ_DATA_WIDTH118_WIDTH 3 /* WSEQ_DATA_WIDTH118 - [10:8] */
8389#define WM8995_WSEQ_DATA_START118_MASK 0x000F /* WSEQ_DATA_START118 - [3:0] */
8390#define WM8995_WSEQ_DATA_START118_SHIFT 0 /* WSEQ_DATA_START118 - [3:0] */
8391#define WM8995_WSEQ_DATA_START118_WIDTH 4 /* WSEQ_DATA_START118 - [3:0] */
8392
8393/*
8394 * R12763 (0x31DB) - Write Sequencer 475
8395 */
8396#define WM8995_WSEQ_EOS118 0x0100 /* WSEQ_EOS118 */
8397#define WM8995_WSEQ_EOS118_MASK 0x0100 /* WSEQ_EOS118 */
8398#define WM8995_WSEQ_EOS118_SHIFT 8 /* WSEQ_EOS118 */
8399#define WM8995_WSEQ_EOS118_WIDTH 1 /* WSEQ_EOS118 */
8400#define WM8995_WSEQ_DELAY118_MASK 0x000F /* WSEQ_DELAY118 - [3:0] */
8401#define WM8995_WSEQ_DELAY118_SHIFT 0 /* WSEQ_DELAY118 - [3:0] */
8402#define WM8995_WSEQ_DELAY118_WIDTH 4 /* WSEQ_DELAY118 - [3:0] */
8403
8404/*
8405 * R12764 (0x31DC) - Write Sequencer 476
8406 */
8407#define WM8995_WSEQ_ADDR119_MASK 0x3FFF /* WSEQ_ADDR119 - [13:0] */
8408#define WM8995_WSEQ_ADDR119_SHIFT 0 /* WSEQ_ADDR119 - [13:0] */
8409#define WM8995_WSEQ_ADDR119_WIDTH 14 /* WSEQ_ADDR119 - [13:0] */
8410
8411/*
8412 * R12765 (0x31DD) - Write Sequencer 477
8413 */
8414#define WM8995_WSEQ_DATA119_MASK 0x00FF /* WSEQ_DATA119 - [7:0] */
8415#define WM8995_WSEQ_DATA119_SHIFT 0 /* WSEQ_DATA119 - [7:0] */
8416#define WM8995_WSEQ_DATA119_WIDTH 8 /* WSEQ_DATA119 - [7:0] */
8417
8418/*
8419 * R12766 (0x31DE) - Write Sequencer 478
8420 */
8421#define WM8995_WSEQ_DATA_WIDTH119_MASK 0x0700 /* WSEQ_DATA_WIDTH119 - [10:8] */
8422#define WM8995_WSEQ_DATA_WIDTH119_SHIFT 8 /* WSEQ_DATA_WIDTH119 - [10:8] */
8423#define WM8995_WSEQ_DATA_WIDTH119_WIDTH 3 /* WSEQ_DATA_WIDTH119 - [10:8] */
8424#define WM8995_WSEQ_DATA_START119_MASK 0x000F /* WSEQ_DATA_START119 - [3:0] */
8425#define WM8995_WSEQ_DATA_START119_SHIFT 0 /* WSEQ_DATA_START119 - [3:0] */
8426#define WM8995_WSEQ_DATA_START119_WIDTH 4 /* WSEQ_DATA_START119 - [3:0] */
8427
8428/*
8429 * R12767 (0x31DF) - Write Sequencer 479
8430 */
8431#define WM8995_WSEQ_EOS119 0x0100 /* WSEQ_EOS119 */
8432#define WM8995_WSEQ_EOS119_MASK 0x0100 /* WSEQ_EOS119 */
8433#define WM8995_WSEQ_EOS119_SHIFT 8 /* WSEQ_EOS119 */
8434#define WM8995_WSEQ_EOS119_WIDTH 1 /* WSEQ_EOS119 */
8435#define WM8995_WSEQ_DELAY119_MASK 0x000F /* WSEQ_DELAY119 - [3:0] */
8436#define WM8995_WSEQ_DELAY119_SHIFT 0 /* WSEQ_DELAY119 - [3:0] */
8437#define WM8995_WSEQ_DELAY119_WIDTH 4 /* WSEQ_DELAY119 - [3:0] */
8438
8439/*
8440 * R12768 (0x31E0) - Write Sequencer 480
8441 */
8442#define WM8995_WSEQ_ADDR120_MASK 0x3FFF /* WSEQ_ADDR120 - [13:0] */
8443#define WM8995_WSEQ_ADDR120_SHIFT 0 /* WSEQ_ADDR120 - [13:0] */
8444#define WM8995_WSEQ_ADDR120_WIDTH 14 /* WSEQ_ADDR120 - [13:0] */
8445
8446/*
8447 * R12769 (0x31E1) - Write Sequencer 481
8448 */
8449#define WM8995_WSEQ_DATA120_MASK 0x00FF /* WSEQ_DATA120 - [7:0] */
8450#define WM8995_WSEQ_DATA120_SHIFT 0 /* WSEQ_DATA120 - [7:0] */
8451#define WM8995_WSEQ_DATA120_WIDTH 8 /* WSEQ_DATA120 - [7:0] */
8452
8453/*
8454 * R12770 (0x31E2) - Write Sequencer 482
8455 */
8456#define WM8995_WSEQ_DATA_WIDTH120_MASK 0x0700 /* WSEQ_DATA_WIDTH120 - [10:8] */
8457#define WM8995_WSEQ_DATA_WIDTH120_SHIFT 8 /* WSEQ_DATA_WIDTH120 - [10:8] */
8458#define WM8995_WSEQ_DATA_WIDTH120_WIDTH 3 /* WSEQ_DATA_WIDTH120 - [10:8] */
8459#define WM8995_WSEQ_DATA_START120_MASK 0x000F /* WSEQ_DATA_START120 - [3:0] */
8460#define WM8995_WSEQ_DATA_START120_SHIFT 0 /* WSEQ_DATA_START120 - [3:0] */
8461#define WM8995_WSEQ_DATA_START120_WIDTH 4 /* WSEQ_DATA_START120 - [3:0] */
8462
8463/*
8464 * R12771 (0x31E3) - Write Sequencer 483
8465 */
8466#define WM8995_WSEQ_EOS120 0x0100 /* WSEQ_EOS120 */
8467#define WM8995_WSEQ_EOS120_MASK 0x0100 /* WSEQ_EOS120 */
8468#define WM8995_WSEQ_EOS120_SHIFT 8 /* WSEQ_EOS120 */
8469#define WM8995_WSEQ_EOS120_WIDTH 1 /* WSEQ_EOS120 */
8470#define WM8995_WSEQ_DELAY120_MASK 0x000F /* WSEQ_DELAY120 - [3:0] */
8471#define WM8995_WSEQ_DELAY120_SHIFT 0 /* WSEQ_DELAY120 - [3:0] */
8472#define WM8995_WSEQ_DELAY120_WIDTH 4 /* WSEQ_DELAY120 - [3:0] */
8473
8474/*
8475 * R12772 (0x31E4) - Write Sequencer 484
8476 */
8477#define WM8995_WSEQ_ADDR121_MASK 0x3FFF /* WSEQ_ADDR121 - [13:0] */
8478#define WM8995_WSEQ_ADDR121_SHIFT 0 /* WSEQ_ADDR121 - [13:0] */
8479#define WM8995_WSEQ_ADDR121_WIDTH 14 /* WSEQ_ADDR121 - [13:0] */
8480
8481/*
8482 * R12773 (0x31E5) - Write Sequencer 485
8483 */
8484#define WM8995_WSEQ_DATA121_MASK 0x00FF /* WSEQ_DATA121 - [7:0] */
8485#define WM8995_WSEQ_DATA121_SHIFT 0 /* WSEQ_DATA121 - [7:0] */
8486#define WM8995_WSEQ_DATA121_WIDTH 8 /* WSEQ_DATA121 - [7:0] */
8487
8488/*
8489 * R12774 (0x31E6) - Write Sequencer 486
8490 */
8491#define WM8995_WSEQ_DATA_WIDTH121_MASK 0x0700 /* WSEQ_DATA_WIDTH121 - [10:8] */
8492#define WM8995_WSEQ_DATA_WIDTH121_SHIFT 8 /* WSEQ_DATA_WIDTH121 - [10:8] */
8493#define WM8995_WSEQ_DATA_WIDTH121_WIDTH 3 /* WSEQ_DATA_WIDTH121 - [10:8] */
8494#define WM8995_WSEQ_DATA_START121_MASK 0x000F /* WSEQ_DATA_START121 - [3:0] */
8495#define WM8995_WSEQ_DATA_START121_SHIFT 0 /* WSEQ_DATA_START121 - [3:0] */
8496#define WM8995_WSEQ_DATA_START121_WIDTH 4 /* WSEQ_DATA_START121 - [3:0] */
8497
8498/*
8499 * R12775 (0x31E7) - Write Sequencer 487
8500 */
8501#define WM8995_WSEQ_EOS121 0x0100 /* WSEQ_EOS121 */
8502#define WM8995_WSEQ_EOS121_MASK 0x0100 /* WSEQ_EOS121 */
8503#define WM8995_WSEQ_EOS121_SHIFT 8 /* WSEQ_EOS121 */
8504#define WM8995_WSEQ_EOS121_WIDTH 1 /* WSEQ_EOS121 */
8505#define WM8995_WSEQ_DELAY121_MASK 0x000F /* WSEQ_DELAY121 - [3:0] */
8506#define WM8995_WSEQ_DELAY121_SHIFT 0 /* WSEQ_DELAY121 - [3:0] */
8507#define WM8995_WSEQ_DELAY121_WIDTH 4 /* WSEQ_DELAY121 - [3:0] */
8508
8509/*
8510 * R12776 (0x31E8) - Write Sequencer 488
8511 */
8512#define WM8995_WSEQ_ADDR122_MASK 0x3FFF /* WSEQ_ADDR122 - [13:0] */
8513#define WM8995_WSEQ_ADDR122_SHIFT 0 /* WSEQ_ADDR122 - [13:0] */
8514#define WM8995_WSEQ_ADDR122_WIDTH 14 /* WSEQ_ADDR122 - [13:0] */
8515
8516/*
8517 * R12777 (0x31E9) - Write Sequencer 489
8518 */
8519#define WM8995_WSEQ_DATA122_MASK 0x00FF /* WSEQ_DATA122 - [7:0] */
8520#define WM8995_WSEQ_DATA122_SHIFT 0 /* WSEQ_DATA122 - [7:0] */
8521#define WM8995_WSEQ_DATA122_WIDTH 8 /* WSEQ_DATA122 - [7:0] */
8522
8523/*
8524 * R12778 (0x31EA) - Write Sequencer 490
8525 */
8526#define WM8995_WSEQ_DATA_WIDTH122_MASK 0x0700 /* WSEQ_DATA_WIDTH122 - [10:8] */
8527#define WM8995_WSEQ_DATA_WIDTH122_SHIFT 8 /* WSEQ_DATA_WIDTH122 - [10:8] */
8528#define WM8995_WSEQ_DATA_WIDTH122_WIDTH 3 /* WSEQ_DATA_WIDTH122 - [10:8] */
8529#define WM8995_WSEQ_DATA_START122_MASK 0x000F /* WSEQ_DATA_START122 - [3:0] */
8530#define WM8995_WSEQ_DATA_START122_SHIFT 0 /* WSEQ_DATA_START122 - [3:0] */
8531#define WM8995_WSEQ_DATA_START122_WIDTH 4 /* WSEQ_DATA_START122 - [3:0] */
8532
8533/*
8534 * R12779 (0x31EB) - Write Sequencer 491
8535 */
8536#define WM8995_WSEQ_EOS122 0x0100 /* WSEQ_EOS122 */
8537#define WM8995_WSEQ_EOS122_MASK 0x0100 /* WSEQ_EOS122 */
8538#define WM8995_WSEQ_EOS122_SHIFT 8 /* WSEQ_EOS122 */
8539#define WM8995_WSEQ_EOS122_WIDTH 1 /* WSEQ_EOS122 */
8540#define WM8995_WSEQ_DELAY122_MASK 0x000F /* WSEQ_DELAY122 - [3:0] */
8541#define WM8995_WSEQ_DELAY122_SHIFT 0 /* WSEQ_DELAY122 - [3:0] */
8542#define WM8995_WSEQ_DELAY122_WIDTH 4 /* WSEQ_DELAY122 - [3:0] */
8543
8544/*
8545 * R12780 (0x31EC) - Write Sequencer 492
8546 */
8547#define WM8995_WSEQ_ADDR123_MASK 0x3FFF /* WSEQ_ADDR123 - [13:0] */
8548#define WM8995_WSEQ_ADDR123_SHIFT 0 /* WSEQ_ADDR123 - [13:0] */
8549#define WM8995_WSEQ_ADDR123_WIDTH 14 /* WSEQ_ADDR123 - [13:0] */
8550
8551/*
8552 * R12781 (0x31ED) - Write Sequencer 493
8553 */
8554#define WM8995_WSEQ_DATA123_MASK 0x00FF /* WSEQ_DATA123 - [7:0] */
8555#define WM8995_WSEQ_DATA123_SHIFT 0 /* WSEQ_DATA123 - [7:0] */
8556#define WM8995_WSEQ_DATA123_WIDTH 8 /* WSEQ_DATA123 - [7:0] */
8557
8558/*
8559 * R12782 (0x31EE) - Write Sequencer 494
8560 */
8561#define WM8995_WSEQ_DATA_WIDTH123_MASK 0x0700 /* WSEQ_DATA_WIDTH123 - [10:8] */
8562#define WM8995_WSEQ_DATA_WIDTH123_SHIFT 8 /* WSEQ_DATA_WIDTH123 - [10:8] */
8563#define WM8995_WSEQ_DATA_WIDTH123_WIDTH 3 /* WSEQ_DATA_WIDTH123 - [10:8] */
8564#define WM8995_WSEQ_DATA_START123_MASK 0x000F /* WSEQ_DATA_START123 - [3:0] */
8565#define WM8995_WSEQ_DATA_START123_SHIFT 0 /* WSEQ_DATA_START123 - [3:0] */
8566#define WM8995_WSEQ_DATA_START123_WIDTH 4 /* WSEQ_DATA_START123 - [3:0] */
8567
8568/*
8569 * R12783 (0x31EF) - Write Sequencer 495
8570 */
8571#define WM8995_WSEQ_EOS123 0x0100 /* WSEQ_EOS123 */
8572#define WM8995_WSEQ_EOS123_MASK 0x0100 /* WSEQ_EOS123 */
8573#define WM8995_WSEQ_EOS123_SHIFT 8 /* WSEQ_EOS123 */
8574#define WM8995_WSEQ_EOS123_WIDTH 1 /* WSEQ_EOS123 */
8575#define WM8995_WSEQ_DELAY123_MASK 0x000F /* WSEQ_DELAY123 - [3:0] */
8576#define WM8995_WSEQ_DELAY123_SHIFT 0 /* WSEQ_DELAY123 - [3:0] */
8577#define WM8995_WSEQ_DELAY123_WIDTH 4 /* WSEQ_DELAY123 - [3:0] */
8578
8579/*
8580 * R12784 (0x31F0) - Write Sequencer 496
8581 */
8582#define WM8995_WSEQ_ADDR124_MASK 0x3FFF /* WSEQ_ADDR124 - [13:0] */
8583#define WM8995_WSEQ_ADDR124_SHIFT 0 /* WSEQ_ADDR124 - [13:0] */
8584#define WM8995_WSEQ_ADDR124_WIDTH 14 /* WSEQ_ADDR124 - [13:0] */
8585
8586/*
8587 * R12785 (0x31F1) - Write Sequencer 497
8588 */
8589#define WM8995_WSEQ_DATA124_MASK 0x00FF /* WSEQ_DATA124 - [7:0] */
8590#define WM8995_WSEQ_DATA124_SHIFT 0 /* WSEQ_DATA124 - [7:0] */
8591#define WM8995_WSEQ_DATA124_WIDTH 8 /* WSEQ_DATA124 - [7:0] */
8592
8593/*
8594 * R12786 (0x31F2) - Write Sequencer 498
8595 */
8596#define WM8995_WSEQ_DATA_WIDTH124_MASK 0x0700 /* WSEQ_DATA_WIDTH124 - [10:8] */
8597#define WM8995_WSEQ_DATA_WIDTH124_SHIFT 8 /* WSEQ_DATA_WIDTH124 - [10:8] */
8598#define WM8995_WSEQ_DATA_WIDTH124_WIDTH 3 /* WSEQ_DATA_WIDTH124 - [10:8] */
8599#define WM8995_WSEQ_DATA_START124_MASK 0x000F /* WSEQ_DATA_START124 - [3:0] */
8600#define WM8995_WSEQ_DATA_START124_SHIFT 0 /* WSEQ_DATA_START124 - [3:0] */
8601#define WM8995_WSEQ_DATA_START124_WIDTH 4 /* WSEQ_DATA_START124 - [3:0] */
8602
8603/*
8604 * R12787 (0x31F3) - Write Sequencer 499
8605 */
8606#define WM8995_WSEQ_EOS124 0x0100 /* WSEQ_EOS124 */
8607#define WM8995_WSEQ_EOS124_MASK 0x0100 /* WSEQ_EOS124 */
8608#define WM8995_WSEQ_EOS124_SHIFT 8 /* WSEQ_EOS124 */
8609#define WM8995_WSEQ_EOS124_WIDTH 1 /* WSEQ_EOS124 */
8610#define WM8995_WSEQ_DELAY124_MASK 0x000F /* WSEQ_DELAY124 - [3:0] */
8611#define WM8995_WSEQ_DELAY124_SHIFT 0 /* WSEQ_DELAY124 - [3:0] */
8612#define WM8995_WSEQ_DELAY124_WIDTH 4 /* WSEQ_DELAY124 - [3:0] */
8613
8614/*
8615 * R12788 (0x31F4) - Write Sequencer 500
8616 */
8617#define WM8995_WSEQ_ADDR125_MASK 0x3FFF /* WSEQ_ADDR125 - [13:0] */
8618#define WM8995_WSEQ_ADDR125_SHIFT 0 /* WSEQ_ADDR125 - [13:0] */
8619#define WM8995_WSEQ_ADDR125_WIDTH 14 /* WSEQ_ADDR125 - [13:0] */
8620
8621/*
8622 * R12789 (0x31F5) - Write Sequencer 501
8623 */
8624#define WM8995_WSEQ_DATA125_MASK 0x00FF /* WSEQ_DATA125 - [7:0] */
8625#define WM8995_WSEQ_DATA125_SHIFT 0 /* WSEQ_DATA125 - [7:0] */
8626#define WM8995_WSEQ_DATA125_WIDTH 8 /* WSEQ_DATA125 - [7:0] */
8627
8628/*
8629 * R12790 (0x31F6) - Write Sequencer 502
8630 */
8631#define WM8995_WSEQ_DATA_WIDTH125_MASK 0x0700 /* WSEQ_DATA_WIDTH125 - [10:8] */
8632#define WM8995_WSEQ_DATA_WIDTH125_SHIFT 8 /* WSEQ_DATA_WIDTH125 - [10:8] */
8633#define WM8995_WSEQ_DATA_WIDTH125_WIDTH 3 /* WSEQ_DATA_WIDTH125 - [10:8] */
8634#define WM8995_WSEQ_DATA_START125_MASK 0x000F /* WSEQ_DATA_START125 - [3:0] */
8635#define WM8995_WSEQ_DATA_START125_SHIFT 0 /* WSEQ_DATA_START125 - [3:0] */
8636#define WM8995_WSEQ_DATA_START125_WIDTH 4 /* WSEQ_DATA_START125 - [3:0] */
8637
8638/*
8639 * R12791 (0x31F7) - Write Sequencer 503
8640 */
8641#define WM8995_WSEQ_EOS125 0x0100 /* WSEQ_EOS125 */
8642#define WM8995_WSEQ_EOS125_MASK 0x0100 /* WSEQ_EOS125 */
8643#define WM8995_WSEQ_EOS125_SHIFT 8 /* WSEQ_EOS125 */
8644#define WM8995_WSEQ_EOS125_WIDTH 1 /* WSEQ_EOS125 */
8645#define WM8995_WSEQ_DELAY125_MASK 0x000F /* WSEQ_DELAY125 - [3:0] */
8646#define WM8995_WSEQ_DELAY125_SHIFT 0 /* WSEQ_DELAY125 - [3:0] */
8647#define WM8995_WSEQ_DELAY125_WIDTH 4 /* WSEQ_DELAY125 - [3:0] */
8648
8649/*
8650 * R12792 (0x31F8) - Write Sequencer 504
8651 */
8652#define WM8995_WSEQ_ADDR126_MASK 0x3FFF /* WSEQ_ADDR126 - [13:0] */
8653#define WM8995_WSEQ_ADDR126_SHIFT 0 /* WSEQ_ADDR126 - [13:0] */
8654#define WM8995_WSEQ_ADDR126_WIDTH 14 /* WSEQ_ADDR126 - [13:0] */
8655
8656/*
8657 * R12793 (0x31F9) - Write Sequencer 505
8658 */
8659#define WM8995_WSEQ_DATA126_MASK 0x00FF /* WSEQ_DATA126 - [7:0] */
8660#define WM8995_WSEQ_DATA126_SHIFT 0 /* WSEQ_DATA126 - [7:0] */
8661#define WM8995_WSEQ_DATA126_WIDTH 8 /* WSEQ_DATA126 - [7:0] */
8662
8663/*
8664 * R12794 (0x31FA) - Write Sequencer 506
8665 */
8666#define WM8995_WSEQ_DATA_WIDTH126_MASK 0x0700 /* WSEQ_DATA_WIDTH126 - [10:8] */
8667#define WM8995_WSEQ_DATA_WIDTH126_SHIFT 8 /* WSEQ_DATA_WIDTH126 - [10:8] */
8668#define WM8995_WSEQ_DATA_WIDTH126_WIDTH 3 /* WSEQ_DATA_WIDTH126 - [10:8] */
8669#define WM8995_WSEQ_DATA_START126_MASK 0x000F /* WSEQ_DATA_START126 - [3:0] */
8670#define WM8995_WSEQ_DATA_START126_SHIFT 0 /* WSEQ_DATA_START126 - [3:0] */
8671#define WM8995_WSEQ_DATA_START126_WIDTH 4 /* WSEQ_DATA_START126 - [3:0] */
8672
8673/*
8674 * R12795 (0x31FB) - Write Sequencer 507
8675 */
8676#define WM8995_WSEQ_EOS126 0x0100 /* WSEQ_EOS126 */
8677#define WM8995_WSEQ_EOS126_MASK 0x0100 /* WSEQ_EOS126 */
8678#define WM8995_WSEQ_EOS126_SHIFT 8 /* WSEQ_EOS126 */
8679#define WM8995_WSEQ_EOS126_WIDTH 1 /* WSEQ_EOS126 */
8680#define WM8995_WSEQ_DELAY126_MASK 0x000F /* WSEQ_DELAY126 - [3:0] */
8681#define WM8995_WSEQ_DELAY126_SHIFT 0 /* WSEQ_DELAY126 - [3:0] */
8682#define WM8995_WSEQ_DELAY126_WIDTH 4 /* WSEQ_DELAY126 - [3:0] */
8683
8684/*
8685 * R12796 (0x31FC) - Write Sequencer 508
8686 */
8687#define WM8995_WSEQ_ADDR127_MASK 0x3FFF /* WSEQ_ADDR127 - [13:0] */
8688#define WM8995_WSEQ_ADDR127_SHIFT 0 /* WSEQ_ADDR127 - [13:0] */
8689#define WM8995_WSEQ_ADDR127_WIDTH 14 /* WSEQ_ADDR127 - [13:0] */
8690
8691/*
8692 * R12797 (0x31FD) - Write Sequencer 509
8693 */
8694#define WM8995_WSEQ_DATA127_MASK 0x00FF /* WSEQ_DATA127 - [7:0] */
8695#define WM8995_WSEQ_DATA127_SHIFT 0 /* WSEQ_DATA127 - [7:0] */
8696#define WM8995_WSEQ_DATA127_WIDTH 8 /* WSEQ_DATA127 - [7:0] */
8697
8698/*
8699 * R12798 (0x31FE) - Write Sequencer 510
8700 */
8701#define WM8995_WSEQ_DATA_WIDTH127_MASK 0x0700 /* WSEQ_DATA_WIDTH127 - [10:8] */
8702#define WM8995_WSEQ_DATA_WIDTH127_SHIFT 8 /* WSEQ_DATA_WIDTH127 - [10:8] */
8703#define WM8995_WSEQ_DATA_WIDTH127_WIDTH 3 /* WSEQ_DATA_WIDTH127 - [10:8] */
8704#define WM8995_WSEQ_DATA_START127_MASK 0x000F /* WSEQ_DATA_START127 - [3:0] */
8705#define WM8995_WSEQ_DATA_START127_SHIFT 0 /* WSEQ_DATA_START127 - [3:0] */
8706#define WM8995_WSEQ_DATA_START127_WIDTH 4 /* WSEQ_DATA_START127 - [3:0] */
8707
8708/*
8709 * R12799 (0x31FF) - Write Sequencer 511
8710 */
8711#define WM8995_WSEQ_EOS127 0x0100 /* WSEQ_EOS127 */
8712#define WM8995_WSEQ_EOS127_MASK 0x0100 /* WSEQ_EOS127 */
8713#define WM8995_WSEQ_EOS127_SHIFT 8 /* WSEQ_EOS127 */
8714#define WM8995_WSEQ_EOS127_WIDTH 1 /* WSEQ_EOS127 */
8715#define WM8995_WSEQ_DELAY127_MASK 0x000F /* WSEQ_DELAY127 - [3:0] */
8716#define WM8995_WSEQ_DELAY127_SHIFT 0 /* WSEQ_DELAY127 - [3:0] */
8717#define WM8995_WSEQ_DELAY127_WIDTH 4 /* WSEQ_DELAY127 - [3:0] */
8718
8719#define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
8720{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
8721 .info = snd_soc_info_volsw, \
8722 .get = snd_soc_dapm_get_volsw, .put = wm8995_put_class_w, \
8723 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) \
8724}
8725
8726struct wm8995_reg_access {
8727 u16 read;
8728 u16 write;
8729 u16 vol;
8730};
8731
8732/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
8733enum clk_src {
8734 WM8995_SYSCLK_MCLK1 = 1,
8735 WM8995_SYSCLK_MCLK2,
8736 WM8995_SYSCLK_FLL1,
8737 WM8995_SYSCLK_FLL2,
8738 WM8995_SYSCLK_OPCLK
8739};
8740
8741#define WM8995_FLL1 1
8742#define WM8995_FLL2 2
8743
8744#define WM8995_FLL_SRC_MCLK1 1
8745#define WM8995_FLL_SRC_MCLK2 2
8746#define WM8995_FLL_SRC_LRCLK 3
8747#define WM8995_FLL_SRC_BCLK 4
8748
8749#endif /* _WM8995_H */
diff --git a/sound/soc/samsung/goni_wm8994.c b/sound/soc/samsung/goni_wm8994.c
index cc8528c0a49a..34dd9ef1b9c0 100644
--- a/sound/soc/samsung/goni_wm8994.c
+++ b/sound/soc/samsung/goni_wm8994.c
@@ -131,7 +131,7 @@ static int goni_wm8994_init(struct snd_soc_pcm_runtime *rtd)
131 snd_soc_dapm_sync(dapm); 131 snd_soc_dapm_sync(dapm);
132 132
133 /* Headset jack detection */ 133 /* Headset jack detection */
134 ret = snd_soc_jack_new(&goni, "Headset Jack", 134 ret = snd_soc_jack_new(codec, "Headset Jack",
135 SND_JACK_HEADSET | SND_JACK_MECHANICAL | SND_JACK_AVOUT, 135 SND_JACK_HEADSET | SND_JACK_MECHANICAL | SND_JACK_AVOUT,
136 &jack); 136 &jack);
137 if (ret) 137 if (ret)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 03:53:08 -0500