diff options
-rw-r--r-- | arch/ppc/mm/init.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c index 334ef4150d92..6164a2b34733 100644 --- a/arch/ppc/mm/init.c +++ b/arch/ppc/mm/init.c | |||
@@ -606,9 +606,19 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, | |||
606 | struct page *page = pfn_to_page(pfn); | 606 | struct page *page = pfn_to_page(pfn); |
607 | if (!PageReserved(page) | 607 | if (!PageReserved(page) |
608 | && !test_bit(PG_arch_1, &page->flags)) { | 608 | && !test_bit(PG_arch_1, &page->flags)) { |
609 | if (vma->vm_mm == current->active_mm) | 609 | if (vma->vm_mm == current->active_mm) { |
610 | #ifdef CONFIG_8xx | ||
611 | /* On 8xx, cache control instructions (particularly | ||
612 | * "dcbst" from flush_dcache_icache) fault as write | ||
613 | * operation if there is an unpopulated TLB entry | ||
614 | * for the address in question. To workaround that, | ||
615 | * we invalidate the TLB here, thus avoiding dcbst | ||
616 | * misbehaviour. | ||
617 | */ | ||
618 | _tlbie(address); | ||
619 | #endif | ||
610 | __flush_dcache_icache((void *) address); | 620 | __flush_dcache_icache((void *) address); |
611 | else | 621 | } else |
612 | flush_dcache_icache_page(page); | 622 | flush_dcache_icache_page(page); |
613 | set_bit(PG_arch_1, &page->flags); | 623 | set_bit(PG_arch_1, &page->flags); |
614 | } | 624 | } |