313 files changed, 21899 insertions, 7192 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 73883b8bbd76..d1c7be38b10a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -480,6 +480,12 @@ M:	kernel@wantstofly.org
 L:      linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
 S:      Maintained
 
+ARM/GUMSTIX MACHINE SUPPORT
+P:      Steve Sakoman
+M:      sakoman@gmail.com
+L:      linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
+S:      Maintained
+
 ARM/HP JORNADA 7XX MACHINE SUPPORT
 P:      Kristoffer Ericson
 M:      kristoffer.ericson@gmail.com
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4039a133006e..ac1bef1797e6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -255,6 +255,7 @@ config ARCH_EP93XX
         select ARM_AMBA
         select ARM_VIC
         select GENERIC_GPIO
+        select HAVE_GPIO_LIB
         help
           This enables support for the Cirrus EP93xx series of CPUs.
 
@@ -377,15 +378,17 @@ config ARCH_MXC
         help
           Support for Freescale MXC/iMX-based family of processors
 
-config ARCH_ORION
+config ARCH_ORION5X
         bool "Marvell Orion"
         depends on MMU
         select PCI
         select GENERIC_GPIO
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
+        select PLAT_ORION
         help
-          Support for Marvell Orion System on Chip family.
+          Support for the following Marvell Orion 5x series SoCs:
+          Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.)
 
 config ARCH_PNX4008
         bool "Philips Nexperia PNX4008 Mobile"
@@ -422,10 +425,15 @@ config ARCH_SA1100
         bool "SA1100-based"
         select ISA
         select ARCH_DISCONTIGMEM_ENABLE
+        select ARCH_SPARSEMEM_ENABLE
+        select ARCH_SELECT_MEMORY_MODEL
         select ARCH_MTD_XIP
         select GENERIC_GPIO
         select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select TICK_ONESHOT
         select HAVE_IDE
+        select HAVE_GPIO_LIB
         help
           Support for StrongARM 11x0 based boards.
 
@@ -516,7 +524,7 @@ source "arch/arm/mach-omap1/Kconfig"
 
 source "arch/arm/mach-omap2/Kconfig"
 
-source "arch/arm/mach-orion/Kconfig"
+source "arch/arm/mach-orion5x/Kconfig"
 
 source "arch/arm/plat-s3c24xx/Kconfig"
 source "arch/arm/plat-s3c/Kconfig"
@@ -563,6 +571,9 @@ config ARCH_ACORN
 config PLAT_IOP
         bool
 
+config PLAT_ORION
+        bool
+
 source arch/arm/mm/Kconfig
 
 config IWMMXT
@@ -650,7 +661,7 @@ source "kernel/time/Kconfig"
 
 config SMP
         bool "Symmetric Multi-Processing (EXPERIMENTAL)"
-        depends on EXPERIMENTAL && REALVIEW_EB_ARM11MP
+        depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP)
         help
           This enables support for systems with more than one CPU. If you have
           a system with only one CPU, like most personal computers, say N. If
@@ -683,7 +694,7 @@ config HOTPLUG_CPU
 
 config LOCAL_TIMERS
         bool "Use local timer interrupts"
-        depends on SMP && REALVIEW_EB_ARM11MP
+        depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP)
         default y
         help
           Enable support for local timers on SMP platforms, rather then the
@@ -774,6 +785,12 @@ config ARCH_DISCONTIGMEM_ENABLE
           or have huge holes in the physical address space for other reasons.
           See <file:Documentation/vm/numa> for more.
 
+config ARCH_SPARSEMEM_ENABLE
+        bool
+
+config ARCH_SELECT_MEMORY_MODEL
+        bool
+
 config NODES_SHIFT
         int
         default "4" if ARCH_LH7A40X
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1a4649667ec8..e72db27e0ba0 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -134,12 +134,11 @@ endif
  machine-$(CONFIG_ARCH_PNX4008)    := pnx4008
  machine-$(CONFIG_ARCH_NETX)       := netx
  machine-$(CONFIG_ARCH_NS9XXX)     := ns9xxx
- textofs-$(CONFIG_ARCH_NS9XXX)     := 0x00108000
  machine-$(CONFIG_ARCH_DAVINCI)    := davinci
  machine-$(CONFIG_ARCH_KS8695)     := ks8695
   incdir-$(CONFIG_ARCH_MXC)        := mxc
  machine-$(CONFIG_ARCH_MX3)        := mx3
- machine-$(CONFIG_ARCH_ORION)      := orion
+ machine-$(CONFIG_ARCH_ORION5X)    := orion5x
  machine-$(CONFIG_ARCH_MSM7X00A)   := msm
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)
@@ -185,6 +184,7 @@ core-$(CONFIG_VFP)		+= arch/arm/vfp/
 
 # If we have a common platform directory, then include it in the build.
 core-$(CONFIG_PLAT_IOP)         += arch/arm/plat-iop/
+core-$(CONFIG_PLAT_ORION)               += arch/arm/plat-orion/
 core-$(CONFIG_ARCH_OMAP)        += arch/arm/plat-omap/
 core-$(CONFIG_PLAT_S3C24XX)             += arch/arm/plat-s3c24xx/
 core-$(CONFIG_ARCH_MXC)         += arch/arm/plat-mxc/
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 25f12303b106..da226abce2d0 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -61,9 +61,15 @@ endif
 
 quiet_cmd_uimage = UIMAGE  $@
       cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
-                   -C none -a $(ZRELADDR) -e $(ZRELADDR) \
+                   -C none -a $(LOADADDR) -e $(LOADADDR) \
                    -n 'Linux-$(KERNELRELEASE)' -d $< $@
 
+ifeq ($(CONFIG_ZBOOT_ROM),y)
+$(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
+else
+$(obj)/uImage: LOADADDR=$(ZRELADDR)
+endif
+
 $(obj)/uImage:  $(obj)/zImage FORCE
         $(call if_changed,uimage)
         @echo '  Image $@ is ready'
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index 314ebd3a1d71..bc299b07a6fa 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -16,6 +16,7 @@
 #include <linux/slab.h>
 #include <linux/platform_device.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/hardware/scoop.h>
 
 /* PCMCIA to Scoop linkage
@@ -30,10 +31,9 @@
 struct scoop_pcmcia_config *platform_scoop_config;
 EXPORT_SYMBOL(platform_scoop_config);
 
-#define SCOOP_REG(d,adr) (*(volatile unsigned short*)(d +(adr)))
-
 struct  scoop_dev {
-        void  *base;
+        void __iomem *base;
+        struct gpio_chip gpio;
         spinlock_t scoop_lock;
         unsigned short suspend_clr;
         unsigned short suspend_set;
@@ -44,13 +44,84 @@ void reset_scoop(struct device *dev)
 {
         struct scoop_dev *sdev = dev_get_drvdata(dev);
 
-        SCOOP_REG(sdev->base,SCOOP_MCR) = 0x0100;  // 00
-        SCOOP_REG(sdev->base,SCOOP_CDR) = 0x0000;  // 04
-        SCOOP_REG(sdev->base,SCOOP_CCR) = 0x0000;  // 10
-        SCOOP_REG(sdev->base,SCOOP_IMR) = 0x0000;  // 18
-        SCOOP_REG(sdev->base,SCOOP_IRM) = 0x00FF;  // 14
-        SCOOP_REG(sdev->base,SCOOP_ISR) = 0x0000;  // 1C
-        SCOOP_REG(sdev->base,SCOOP_IRM) = 0x0000;
+        iowrite16(0x0100, sdev->base + SCOOP_MCR);  // 00
+        iowrite16(0x0000, sdev->base + SCOOP_CDR);  // 04
+        iowrite16(0x0000, sdev->base + SCOOP_CCR);  // 10
+        iowrite16(0x0000, sdev->base + SCOOP_IMR);  // 18
+        iowrite16(0x00FF, sdev->base + SCOOP_IRM);  // 14
+        iowrite16(0x0000, sdev->base + SCOOP_ISR);  // 1C
+        iowrite16(0x0000, sdev->base + SCOOP_IRM);
+}
+
+static void __scoop_gpio_set(struct scoop_dev *sdev,
+                        unsigned offset, int value)
+{
+        unsigned short gpwr;
+
+        gpwr = ioread16(sdev->base + SCOOP_GPWR);
+        if (value)
+                gpwr |= 1 << (offset + 1);
+        else
+                gpwr &= ~(1 << (offset + 1));
+        iowrite16(gpwr, sdev->base + SCOOP_GPWR);
+}
+
+static void scoop_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
+        unsigned long flags;
+
+        spin_lock_irqsave(&sdev->scoop_lock, flags);
+
+        __scoop_gpio_set(sdev, offset, value);
+
+        spin_unlock_irqrestore(&sdev->scoop_lock, flags);
+}
+
+static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
+
+        /* XXX: I'm usure,  but it seems so */
+        return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1));
+}
+
+static int scoop_gpio_direction_input(struct gpio_chip *chip,
+                        unsigned offset)
+{
+        struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
+        unsigned long flags;
+        unsigned short gpcr;
+
+        spin_lock_irqsave(&sdev->scoop_lock, flags);
+
+        gpcr = ioread16(sdev->base + SCOOP_GPCR);
+        gpcr &= ~(1 << (offset + 1));
+        iowrite16(gpcr, sdev->base + SCOOP_GPCR);
+
+        spin_unlock_irqrestore(&sdev->scoop_lock, flags);
+
+        return 0;
+}
+
+static int scoop_gpio_direction_output(struct gpio_chip *chip,
+                        unsigned offset, int value)
+{
+        struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
+        unsigned long flags;
+        unsigned short gpcr;
+
+        spin_lock_irqsave(&sdev->scoop_lock, flags);
+
+        __scoop_gpio_set(sdev, offset, value);
+
+        gpcr = ioread16(sdev->base + SCOOP_GPCR);
+        gpcr |= 1 << (offset + 1);
+        iowrite16(gpcr, sdev->base + SCOOP_GPCR);
+
+        spin_unlock_irqrestore(&sdev->scoop_lock, flags);
+
+        return 0;
 }
 
 unsigned short set_scoop_gpio(struct device *dev, unsigned short bit)
@@ -60,8 +131,8 @@ unsigned short set_scoop_gpio(struct device *dev, unsigned short bit)
         struct scoop_dev *sdev = dev_get_drvdata(dev);
 
         spin_lock_irqsave(&sdev->scoop_lock, flag);
-        gpio_bit = SCOOP_REG(sdev->base, SCOOP_GPWR) | bit;
-        SCOOP_REG(sdev->base, SCOOP_GPWR) = gpio_bit;
+        gpio_bit = ioread16(sdev->base + SCOOP_GPWR) | bit;
+        iowrite16(gpio_bit, sdev->base + SCOOP_GPWR);
         spin_unlock_irqrestore(&sdev->scoop_lock, flag);
 
         return gpio_bit;
@@ -74,8 +145,8 @@ unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit)
         struct scoop_dev *sdev = dev_get_drvdata(dev);
 
         spin_lock_irqsave(&sdev->scoop_lock, flag);
-        gpio_bit = SCOOP_REG(sdev->base, SCOOP_GPWR) & ~bit;
-        SCOOP_REG(sdev->base,SCOOP_GPWR) = gpio_bit;
+        gpio_bit = ioread16(sdev->base + SCOOP_GPWR) & ~bit;
+        iowrite16(gpio_bit, sdev->base + SCOOP_GPWR);
         spin_unlock_irqrestore(&sdev->scoop_lock, flag);
 
         return gpio_bit;
@@ -87,13 +158,13 @@ EXPORT_SYMBOL(reset_scoop_gpio);
 unsigned short read_scoop_reg(struct device *dev, unsigned short reg)
 {
         struct scoop_dev *sdev = dev_get_drvdata(dev);
-        return SCOOP_REG(sdev->base,reg);
+        return ioread16(sdev->base + reg);
 }
 
 void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data)
 {
         struct scoop_dev *sdev = dev_get_drvdata(dev);
-        SCOOP_REG(sdev->base,reg)=data;
+        iowrite16(data, sdev->base + reg);
 }
 
 EXPORT_SYMBOL(reset_scoop);
@@ -104,9 +175,9 @@ static void check_scoop_reg(struct scoop_dev *sdev)
 {
         unsigned short mcr;
 
-        mcr = SCOOP_REG(sdev->base, SCOOP_MCR);
+        mcr = ioread16(sdev->base + SCOOP_MCR);
         if ((mcr & 0x100) == 0)
-                SCOOP_REG(sdev->base, SCOOP_MCR) = 0x0101;
+                iowrite16(0x0101, sdev->base + SCOOP_MCR);
 }
 
 #ifdef CONFIG_PM
@@ -115,8 +186,8 @@ static int scoop_suspend(struct platform_device *dev, pm_message_t state)
         struct scoop_dev *sdev = platform_get_drvdata(dev);
 
         check_scoop_reg(sdev);
-        sdev->scoop_gpwr = SCOOP_REG(sdev->base, SCOOP_GPWR);
-        SCOOP_REG(sdev->base, SCOOP_GPWR) = (sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set;
+        sdev->scoop_gpwr = ioread16(sdev->base + SCOOP_GPWR);
+        iowrite16((sdev->scoop_gpwr & ~sdev->suspend_clr) | sdev->suspend_set, sdev->base + SCOOP_GPWR);
 
         return 0;
 }
@@ -126,7 +197,7 @@ static int scoop_resume(struct platform_device *dev)
         struct scoop_dev *sdev = platform_get_drvdata(dev);
 
         check_scoop_reg(sdev);
-        SCOOP_REG(sdev->base,SCOOP_GPWR) = sdev->scoop_gpwr;
+        iowrite16(sdev->scoop_gpwr, sdev->base + SCOOP_GPWR);
 
         return 0;
 }
@@ -135,11 +206,13 @@ static int scoop_resume(struct platform_device *dev)
 #define scoop_resume    NULL
 #endif
 
-int __init scoop_probe(struct platform_device *pdev)
+static int __devinit scoop_probe(struct platform_device *pdev)
 {
         struct scoop_dev *devptr;
         struct scoop_config *inf;
         struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        int ret;
+        int temp;
 
         if (!mem)
                 return -EINVAL;
@@ -154,40 +227,78 @@ int __init scoop_probe(struct platform_device *pdev)
         devptr->base = ioremap(mem->start, mem->end - mem->start + 1);
 
         if (!devptr->base) {
-                kfree(devptr);
-                return -ENOMEM;
+                ret = -ENOMEM;
+                goto err_ioremap;
         }
 
         platform_set_drvdata(pdev, devptr);
 
-        printk("Sharp Scoop Device found at 0x%08x -> 0x%08x\n",(unsigned int)mem->start,(unsigned int)devptr->base);
+        printk("Sharp Scoop Device found at 0x%08x -> 0x%8p\n",(unsigned int)mem->start, devptr->base);
 
-        SCOOP_REG(devptr->base, SCOOP_MCR) = 0x0140;
+        iowrite16(0x0140, devptr->base + SCOOP_MCR);
         reset_scoop(&pdev->dev);
-        SCOOP_REG(devptr->base, SCOOP_CPR) = 0x0000;
-        SCOOP_REG(devptr->base, SCOOP_GPCR) = inf->io_dir & 0xffff;
-        SCOOP_REG(devptr->base, SCOOP_GPWR) = inf->io_out & 0xffff;
+        iowrite16(0x0000, devptr->base + SCOOP_CPR);
+        iowrite16(inf->io_dir & 0xffff, devptr->base + SCOOP_GPCR);
+        iowrite16(inf->io_out & 0xffff, devptr->base + SCOOP_GPWR);
 
         devptr->suspend_clr = inf->suspend_clr;
         devptr->suspend_set = inf->suspend_set;
 
+        devptr->gpio.base = -1;
+
+        if (inf->gpio_base != 0) {
+                devptr->gpio.label = pdev->dev.bus_id;
+                devptr->gpio.base = inf->gpio_base;
+                devptr->gpio.ngpio = 12; /* PA11 = 0, PA12 = 1, etc. up to PA22 = 11 */
+                devptr->gpio.set = scoop_gpio_set;
+                devptr->gpio.get = scoop_gpio_get;
+                devptr->gpio.direction_input = scoop_gpio_direction_input;
+                devptr->gpio.direction_output = scoop_gpio_direction_output;
+
+                ret = gpiochip_add(&devptr->gpio);
+                if (ret)
+                        goto err_gpio;
+        }
+
         return 0;
+
+        if (devptr->gpio.base != -1)
+                temp = gpiochip_remove(&devptr->gpio);
+err_gpio:
+        platform_set_drvdata(pdev, NULL);
+err_ioremap:
+        iounmap(devptr->base);
+        kfree(devptr);
+
+        return ret;
 }
 
-static int scoop_remove(struct platform_device *pdev)
+static int __devexit scoop_remove(struct platform_device *pdev)
 {
         struct scoop_dev *sdev = platform_get_drvdata(pdev);
-        if (sdev) {
-                iounmap(sdev->base);
-                kfree(sdev);
-                platform_set_drvdata(pdev, NULL);
+        int ret;
+
+        if (!sdev)
+                return -EINVAL;
+
+        if (sdev->gpio.base != -1) {
+                ret = gpiochip_remove(&sdev->gpio);
+                if (ret) {
+                        dev_err(&pdev->dev, "Can't remove gpio chip: %d\n", ret);
+                        return ret;
+                }
         }
+
+        platform_set_drvdata(pdev, NULL);
+        iounmap(sdev->base);
+        kfree(sdev);
+
         return 0;
 }
 
 static struct platform_driver scoop_driver = {
         .probe          = scoop_probe,
-        .remove         = scoop_remove,
+        .remove         = __devexit_p(scoop_remove),
         .suspend        = scoop_suspend,
         .resume         = scoop_resume,
         .driver         = {
@@ -195,7 +306,7 @@ static struct platform_driver scoop_driver = {
         },
 };
 
-int __init scoop_init(void)
+static int __init scoop_init(void)
 {
         return platform_driver_register(&scoop_driver);
 }
diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig
new file mode 100644
index 000000000000..dc030cfe5009
--- /dev/null
+++ b/arch/arm/configs/am200epdkit_defconfig
@@ -0,0 +1,1149 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.25-rc3
+# Sun Mar  9 06:33:33 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="gum"
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+# CONFIG_EPOLL is not set
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+# CONFIG_SHMEM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+CONFIG_ARCH_GUMSTIX=y
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_PCM027 is not set
+CONFIG_MACH_GUMSTIX_F=y
+CONFIG_PXA25x=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+# CONFIG_IWMMXT is not set
+CONFIG_XSCALE_PMU=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+# CONFIG_PCMCIA_IOCTL is not set
+
+#
+# PC-card bridges
+#
+CONFIG_PCMCIA_PXA2XX=y
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200n8 root=1f01 rootfstype=jffs2"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=m
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+# CONFIG_BT_HIDP is not set
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_LL is not set
+# CONFIG_BT_HCIDTL1 is not set
+# CONFIG_BT_HCIBT3C is not set
+# CONFIG_BT_HCIBLUECARD is not set
+# CONFIG_BT_HCIBTUART is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_IEEE80211_SOFTMAC is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PXA2XX=y
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=m
+CONFIG_IDE_MAX_HWIFS=2
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=m
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=m
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+CONFIG_IDE_ARCH_OBSOLETE_INIT=y
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=m
+# CONFIG_DM9000 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_NET_PCMCIA is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+CONFIG_HAVE_GPIO_LIB=y
+
+#
+# GPIO Support
+#
+# CONFIG_DEBUG_GPIO is not set
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_SA1100_WATCHDOG=m
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+CONFIG_FB_SYS_FOPS=m
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+CONFIG_FB_PXA_PARAMETERS=y
+CONFIG_FB_MBX=m
+CONFIG_FB_VIRTUAL=m
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+
+#
+# Sound
+#
+CONFIG_SOUND=m
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+CONFIG_SND_AC97_CODEC=m
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# ALSA ARM devices
+#
+CONFIG_SND_PXA2XX_PCM=m
+CONFIG_SND_PXA2XX_AC97=m
+
+#
+# PCMCIA devices
+#
+# CONFIG_SND_VXPOCKET is not set
+# CONFIG_SND_PDAUDIOCF is not set
+
+#
+# System on Chip audio support
+#
+# CONFIG_SND_SOC is not set
+
+#
+# SoC Audio support for SuperH
+#
+
+#
+# ALSA SoC audio for Freescale SOCs
+#
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+CONFIG_USB_GADGET_PXA2XX=y
+CONFIG_USB_PXA2XX=y
+# CONFIG_USB_PXA2XX_SMALL is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig
index e10d003566d6..2dbbbc3d4ac3 100644
--- a/arch/arm/configs/at91rm9200dk_defconfig
+++ b/arch/arm/configs/at91rm9200dk_defconfig
@@ -620,14 +620,14 @@ CONFIG_I2C_CHARDEV=y
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_STUB is not set
 # CONFIG_I2C_PCA_ISA is not set
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
index 834dddb51314..6e994f7820c6 100644
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ b/arch/arm/configs/at91rm9200ek_defconfig
@@ -594,14 +594,14 @@ CONFIG_I2C_CHARDEV=y
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_STUB is not set
 # CONFIG_I2C_PCA_ISA is not set
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig
index 46b0c734aeb9..f659c938473f 100644
--- a/arch/arm/configs/at91sam9260ek_defconfig
+++ b/arch/arm/configs/at91sam9260ek_defconfig
@@ -1,43 +1,56 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.19-rc6
-# Fri Nov 17 18:42:21 2006
+# Linux kernel version: 2.6.24-rc7
+# Tue Jan  8 22:20:50 2008
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
 # CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
@@ -53,30 +66,30 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
+# CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -108,12 +121,16 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
 # CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
@@ -121,29 +138,52 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
 
 #
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
 # Atmel AT91 System-on-Chip
 #
 # CONFIG_ARCH_AT91RM9200 is not set
 CONFIG_ARCH_AT91SAM9260=y
 # CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
 
 #
-# AT91SAM9260 Board Type
+# AT91SAM9260 / AT91SAM9XE Board Type
 #
 CONFIG_MACH_AT91SAM9260EK=y
+# CONFIG_MACH_CAM60 is not set
+# CONFIG_MACH_SAM9_L9260 is not set
 
 #
 # AT91 Board Options
 #
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
 # CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
 
 #
 # AT91 Feature Selections
 #
-# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=100
 
 #
 # Processor Type
@@ -166,19 +206,19 @@ CONFIG_CPU_CP15_MMU=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
 
 #
 # Bus support
 #
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
@@ -191,8 +231,12 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -203,6 +247,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
 
 #
 # Floating point emulation
@@ -228,7 +273,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
-# CONFIG_APM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
 
 #
 # Networking
@@ -238,13 +283,9 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -263,33 +304,23 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
 # CONFIG_INET6_XFRM_TUNNEL is not set
 # CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -302,10 +333,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -315,7 +342,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -324,34 +361,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 # CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
@@ -360,15 +380,19 @@ CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 
@@ -388,6 +412,8 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
 # SCSI Transports
@@ -395,43 +421,72 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_ATA is not set
 # CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
+# USB Network Adapters
 #
-# CONFIG_NETDEVICES is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
@@ -439,6 +494,7 @@ CONFIG_SCSI_MULTI_LUN=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -448,7 +504,6 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -458,6 +513,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -492,114 +548,131 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
 
 #
-# Ftape, the floppy tape device driver
+# I2C Algorithms
 #
-# CONFIG_RAW_DRIVER is not set
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
 
 #
-# TPM devices
+# I2C Hardware Bus support
 #
-# CONFIG_TCG_TPM is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
 
 #
-# I2C support
+# Miscellaneous I2C Chip support
 #
-# CONFIG_I2C is not set
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 
 #
 # SPI support
 #
 # CONFIG_SPI is not set
 # CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
 # CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Misc devices
+# Watchdog Device Drivers
 #
-# CONFIG_TIFM_CORE is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9_WATCHDOG=y
 
 #
-# LED devices
+# USB-based Watchdog Cards
 #
-# CONFIG_NEW_LEDS is not set
+# CONFIG_USBPCWATCHDOG is not set
 
 #
-# LED drivers
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# LED Triggers
+# Multifunction device drivers
 #
+# CONFIG_MFD_SM501 is not set
 
 #
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Graphics support
 #
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Graphics support
+# Display device support
 #
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 
 #
-# USB support
+# USB Input Devices
 #
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
@@ -610,7 +683,7 @@ CONFIG_USB=y
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
 
@@ -619,9 +692,11 @@ CONFIG_USB_DEVICEFS=y
 #
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
@@ -640,6 +715,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DEBUG=y
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
@@ -650,43 +726,10 @@ CONFIG_USB_STORAGE_DEBUG=y
 # CONFIG_USB_LIBUSUAL is not set
 
 #
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
-#
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
 CONFIG_USB_MON=y
 
 #
@@ -708,6 +751,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
@@ -717,6 +761,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_APPLEDISPLAY is not set
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 
 #
@@ -727,13 +772,19 @@ CONFIG_USB_MON=y
 # USB Gadget Support
 #
 CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
 CONFIG_USB_GADGET_AT91=y
 CONFIG_USB_AT91=y
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
@@ -745,17 +796,56 @@ CONFIG_USB_FILE_STORAGE=m
 # CONFIG_USB_FILE_STORAGE_TEST is not set
 CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# MMC/SD Card support
+# RTC interfaces
 #
-# CONFIG_MMC is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# Real Time Clock
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
 #
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
 
 #
 # File systems
@@ -806,7 +896,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -825,10 +914,7 @@ CONFIG_CRAMFS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 # CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
 # CONFIG_SMB_FS is not set
@@ -836,17 +922,12 @@ CONFIG_CRAMFS=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -887,41 +968,49 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Profiling support
-#
+# CONFIG_DLM is not set
+CONFIG_INSTRUMENTATION=y
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
-# CONFIG_HEADERS_CHECK is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
@@ -932,18 +1021,21 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig
index fcd8fa091e9d..3802e85f7483 100644
--- a/arch/arm/configs/at91sam9261ek_defconfig
+++ b/arch/arm/configs/at91sam9261ek_defconfig
@@ -1,43 +1,56 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.19-rc6
-# Fri Nov 17 18:00:38 2006
+# Linux kernel version: 2.6.24-rc7
+# Tue Jan  8 22:21:49 2008
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
 # CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
@@ -53,30 +66,30 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
+# CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -108,12 +121,16 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
 # CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
@@ -121,14 +138,27 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
 
 #
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
 # Atmel AT91 System-on-Chip
 #
 # CONFIG_ARCH_AT91RM9200 is not set
 # CONFIG_ARCH_AT91SAM9260 is not set
 CONFIG_ARCH_AT91SAM9261=y
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
 
 #
 # AT91SAM9261 Board Type
@@ -138,12 +168,15 @@ CONFIG_MACH_AT91SAM9261EK=y
 #
 # AT91 Board Options
 #
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
 # CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
 
 #
 # AT91 Feature Selections
 #
-# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=100
 
 #
 # Processor Type
@@ -166,19 +199,19 @@ CONFIG_CPU_CP15_MMU=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
 
 #
 # Bus support
 #
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
@@ -191,8 +224,12 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -203,6 +240,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
 
 #
 # Floating point emulation
@@ -228,7 +266,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
-# CONFIG_APM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
 
 #
 # Networking
@@ -238,13 +276,13 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
 CONFIG_XFRM=y
 # CONFIG_XFRM_USER is not set
 # CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -266,30 +304,20 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_INET_XFRM_MODE_TRANSPORT=y
 CONFIG_INET_XFRM_MODE_TUNNEL=y
 CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
 # CONFIG_INET6_XFRM_TUNNEL is not set
 # CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -302,10 +330,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -315,7 +339,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -324,20 +358,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -350,12 +378,14 @@ CONFIG_MTD_CMDLINE_PARTS=y
 # User Modules And Translation Layers
 #
 # CONFIG_MTD_CHAR is not set
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -375,7 +405,6 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
@@ -386,6 +415,8 @@ CONFIG_MTD_CFI_I2=y
 #
 # Self-contained MTD device drivers
 #
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -397,35 +428,24 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 CONFIG_MTD_NAND_AT91=y
 # CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 # CONFIG_BLK_DEV_LOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
@@ -434,15 +454,19 @@ CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 
@@ -462,6 +486,8 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
 # SCSI Transports
@@ -469,75 +495,49 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_ATA is not set
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+# CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
 CONFIG_DM9000=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 
 #
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -545,10 +545,6 @@ CONFIG_DM9000=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
@@ -556,6 +552,7 @@ CONFIG_DM9000=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -565,23 +562,43 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
 #
 # Input Device Drivers
 #
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
-# CONFIG_SERIO is not set
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_RAW is not set
 # CONFIG_GAMEPORT is not set
 
 #
@@ -609,75 +626,47 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
 CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
 # CONFIG_I2C_PCA is not set
-# CONFIG_I2C_PCA_ISA is not set
 
 #
 # Miscellaneous I2C Chip support
 #
 # CONFIG_SENSORS_DS1337 is not set
 # CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -686,70 +675,125 @@ CONFIG_I2C_AT91=y
 #
 # SPI support
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
 
 #
-# Dallas's 1-wire bus
+# SPI Master Controller Drivers
 #
-# CONFIG_W1 is not set
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
 
 #
-# Hardware Monitoring support
+# SPI Protocol Masters
 #
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Misc devices
+# Watchdog Device Drivers
 #
-# CONFIG_TIFM_CORE is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9_WATCHDOG=y
 
 #
-# LED devices
+# USB-based Watchdog Cards
 #
-# CONFIG_NEW_LEDS is not set
+# CONFIG_USBPCWATCHDOG is not set
 
 #
-# LED drivers
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# LED Triggers
+# Multifunction device drivers
 #
+# CONFIG_MFD_SM501 is not set
 
 #
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
 # CONFIG_USB_DABUSB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D15605 is not set
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_ATMEL=y
+# CONFIG_FB_INTSRAM is not set
+# CONFIG_FB_ATMEL_STN is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 
 #
-# USB support
+# USB Input Devices
 #
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
@@ -760,7 +804,7 @@ CONFIG_USB=y
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
 
@@ -769,9 +813,11 @@ CONFIG_USB_DEVICEFS=y
 #
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
@@ -790,6 +836,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DEBUG=y
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
@@ -800,43 +847,10 @@ CONFIG_USB_STORAGE_DEBUG=y
 # CONFIG_USB_LIBUSUAL is not set
 
 #
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
-#
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
 CONFIG_USB_MON=y
 
 #
@@ -858,6 +872,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
@@ -867,6 +882,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_APPLEDISPLAY is not set
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 
 #
@@ -877,13 +893,19 @@ CONFIG_USB_MON=y
 # USB Gadget Support
 #
 CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
 CONFIG_USB_GADGET_AT91=y
 CONFIG_USB_AT91=y
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
@@ -895,21 +917,73 @@ CONFIG_USB_FILE_STORAGE=m
 # CONFIG_USB_FILE_STORAGE_TEST is not set
 CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card support
+# MMC/SD Card Drivers
 #
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
 CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AT91=m
-# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
 
 #
-# Real Time Clock
+# MMC/SD Host Controller Drivers
 #
+CONFIG_MMC_AT91=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
 CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
 
 #
 # File systems
@@ -960,7 +1034,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -973,7 +1046,6 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
 # CONFIG_JFFS2_FS is not set
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
@@ -981,10 +1053,7 @@ CONFIG_CRAMFS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 # CONFIG_NFS_FS is not set
 # CONFIG_NFSD is not set
 # CONFIG_SMB_FS is not set
@@ -992,17 +1061,12 @@ CONFIG_CRAMFS=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -1043,41 +1107,49 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Profiling support
-#
+# CONFIG_DLM is not set
+CONFIG_INSTRUMENTATION=y
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
-# CONFIG_HEADERS_CHECK is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
@@ -1088,18 +1160,21 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig
index c72ab82873d5..32a0d74e0c89 100644
--- a/arch/arm/configs/at91sam9263ek_defconfig
+++ b/arch/arm/configs/at91sam9263ek_defconfig
@@ -1,12 +1,18 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20-rc1
-# Mon Jan  8 16:06:54 2007
+# Linux kernel version: 2.6.24-rc7
+# Tue Jan  8 22:12:20 2008
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
 # CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
@@ -15,32 +21,36 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
@@ -56,32 +66,30 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -113,13 +121,16 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
 # CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
@@ -127,15 +138,27 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
 
 #
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
 # Atmel AT91 System-on-Chip
 #
 # CONFIG_ARCH_AT91RM9200 is not set
 # CONFIG_ARCH_AT91SAM9260 is not set
 # CONFIG_ARCH_AT91SAM9261 is not set
 CONFIG_ARCH_AT91SAM9263=y
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
 
 #
 # AT91SAM9263 Board Type
@@ -152,6 +175,8 @@ CONFIG_MTD_AT91_DATAFLASH_CARD=y
 # AT91 Feature Selections
 #
 # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=100
 
 #
 # Processor Type
@@ -174,19 +199,19 @@ CONFIG_CPU_CP15_MMU=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
 # CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
 
 #
 # Bus support
 #
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
@@ -199,8 +224,12 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -211,6 +240,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
 
 #
 # Floating point emulation
@@ -236,7 +266,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
-# CONFIG_APM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
 
 #
 # Networking
@@ -246,7 +276,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -271,6 +300,7 @@ CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
@@ -281,20 +311,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_INET6_TUNNEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -307,10 +325,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -320,7 +334,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -329,20 +353,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -362,6 +380,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -381,7 +400,6 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
@@ -405,35 +423,24 @@ CONFIG_MTD_DATAFLASH=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 CONFIG_MTD_NAND_AT91=y
 # CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -443,15 +450,18 @@ CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
@@ -473,6 +483,7 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
 # CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
 # SCSI Transports
@@ -480,80 +491,65 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
 
 #
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
+# Wireless LAN
 #
-# CONFIG_NET_RADIO is not set
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Wan interfaces
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -561,10 +557,6 @@ CONFIG_MII=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
@@ -572,6 +564,7 @@ CONFIG_MII=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -581,20 +574,26 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_TSDEV=y
-CONFIG_INPUT_TSDEV_SCREEN_X=240
-CONFIG_INPUT_TSDEV_SCREEN_Y=320
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
 #
 # Input Device Drivers
 #
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
@@ -603,6 +602,7 @@ CONFIG_TOUCHSCREEN_ADS7846=y
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
 # CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -636,71 +636,47 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
 CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
 # CONFIG_I2C_PCA is not set
-# CONFIG_I2C_PCA_ISA is not set
 
 #
 # Miscellaneous I2C Chip support
 #
 # CONFIG_SENSORS_DS1337 is not set
 # CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
@@ -722,61 +698,80 @@ CONFIG_SPI_ATMEL=y
 #
 # SPI Protocol Masters
 #
-
-#
-# Dallas's 1-wire bus
-#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
 # CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Misc devices
+# Watchdog Device Drivers
 #
-# CONFIG_TIFM_CORE is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9_WATCHDOG=y
 
 #
-# LED devices
+# USB-based Watchdog Cards
 #
-# CONFIG_NEW_LEDS is not set
+# CONFIG_USBPCWATCHDOG is not set
 
 #
-# LED drivers
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# LED Triggers
+# Multifunction device drivers
 #
+# CONFIG_MFD_SM501 is not set
 
 #
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
-# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
 # CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D15605 is not set
 # CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_ATMEL=y
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -784,26 +779,28 @@ CONFIG_FB=y
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
 # CONFIG_FRAMEBUFFER_CONSOLE is not set
-
-#
-# Logo configuration
-#
 # CONFIG_LOGO is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
 # Sound
 #
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
 
 #
-# HID Devices
+# USB Input Devices
 #
-CONFIG_HID=y
+# CONFIG_USB_HID is not set
 
 #
-# USB support
+# USB HID Boot Protocol drivers
 #
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
@@ -814,9 +811,8 @@ CONFIG_USB=y
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_MULTITHREAD_PROBE is not set
 # CONFIG_USB_OTG is not set
 
 #
@@ -824,9 +820,11 @@ CONFIG_USB_DEVICEFS=y
 #
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
@@ -845,6 +843,7 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
@@ -856,43 +855,10 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_LIBUSUAL is not set
 
 #
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-
-#
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
 CONFIG_USB_MON=y
 
 #
@@ -914,6 +880,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
@@ -923,6 +890,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_APPLEDISPLAY is not set
 # CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 
 #
@@ -933,13 +901,19 @@ CONFIG_USB_MON=y
 # USB Gadget Support
 #
 CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
 CONFIG_USB_GADGET_AT91=y
 CONFIG_USB_AT91=y
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
@@ -951,21 +925,73 @@ CONFIG_USB_FILE_STORAGE=m
 # CONFIG_USB_FILE_STORAGE_TEST is not set
 CONFIG_USB_G_SERIAL=m
 # CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card support
+# MMC/SD Card Drivers
 #
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
 CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AT91=m
-# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
 
 #
-# Real Time Clock
+# MMC/SD Host Controller Drivers
 #
+CONFIG_MMC_AT91=m
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
 CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
 
 #
 # File systems
@@ -1016,7 +1042,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -1032,10 +1057,12 @@ CONFIG_RAMFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
 # CONFIG_JFFS2_SUMMARY is not set
 # CONFIG_JFFS2_FS_XATTR is not set
 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
 CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
 CONFIG_JFFS2_RTIME=y
 # CONFIG_JFFS2_RUBIN is not set
 CONFIG_CRAMFS=y
@@ -1044,10 +1071,7 @@ CONFIG_CRAMFS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 # CONFIG_NFS_V3 is not set
 # CONFIG_NFS_V4 is not set
@@ -1057,6 +1081,7 @@ CONFIG_ROOT_NFS=y
 CONFIG_LOCKD=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1064,17 +1089,12 @@ CONFIG_SUNRPC=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -1115,36 +1135,35 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
 # CONFIG_DLM is not set
-
-#
-# Profiling support
-#
+CONFIG_INSTRUMENTATION=y
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
@@ -1152,9 +1171,13 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
@@ -1165,10 +1188,7 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
 
 #
@@ -1177,8 +1197,13 @@ CONFIG_DEBUG_LL=y
 CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
 CONFIG_PLIST=y
-CONFIG_IOMAP_COPY=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/at91sam9rlek_defconfig b/arch/arm/configs/at91sam9rlek_defconfig
index fbe8b3049343..98e6746d02be 100644
--- a/arch/arm/configs/at91sam9rlek_defconfig
+++ b/arch/arm/configs/at91sam9rlek_defconfig
@@ -1,15 +1,18 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21
-# Mon May  7 16:30:40 2007
+# Linux kernel version: 2.6.24-rc7
+# Tue Jan  8 22:24:14 2008
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 # CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
 CONFIG_MMU=y
 # CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
@@ -23,27 +26,28 @@ CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
 CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -62,32 +66,30 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
 CONFIG_BLOCK=y
 # CONFIG_LBD is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -119,14 +121,16 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
 # CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
@@ -134,9 +138,18 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
 
 #
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
 # Atmel AT91 System-on-Chip
 #
 # CONFIG_ARCH_AT91RM9200 is not set
@@ -144,6 +157,8 @@ CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_AT91SAM9261 is not set
 # CONFIG_ARCH_AT91SAM9263 is not set
 CONFIG_ARCH_AT91SAM9RL=y
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
 
 #
 # AT91SAM9RL Board Type
@@ -157,7 +172,9 @@ CONFIG_MACH_AT91SAM9RLEK=y
 #
 # AT91 Feature Selections
 #
-# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=100
 
 #
 # Processor Type
@@ -185,15 +202,14 @@ CONFIG_CPU_CP15_MMU=y
 #
 # Bus support
 #
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 # CONFIG_PCCARD is not set
 
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_NO_IDLE_HZ is not set
 CONFIG_HZ=100
@@ -206,9 +222,12 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
 # CONFIG_RESOURCES_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -245,6 +264,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
 
 #
 # Networking
@@ -254,7 +274,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 # CONFIG_PACKET is not set
 CONFIG_UNIX=y
 # CONFIG_NET_KEY is not set
@@ -271,10 +290,6 @@ CONFIG_UNIX=y
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -284,7 +299,16 @@ CONFIG_UNIX=y
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -293,21 +317,14 @@ CONFIG_UNIX=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
 # CONFIG_DEBUG_DRIVER is not set
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 CONFIG_MTD_CONCAT=y
@@ -327,6 +344,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -346,7 +364,6 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
@@ -370,36 +387,23 @@ CONFIG_MTD_DATAFLASH=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 CONFIG_MTD_NAND_AT91=y
 # CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -410,12 +414,16 @@ CONFIG_BLK_DEV_RAM_SIZE=24576
 CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
 # CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
@@ -437,6 +445,7 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
 # CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
 # SCSI Transports
@@ -444,47 +453,13 @@ CONFIG_SCSI_MULTI_LUN=y
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 # CONFIG_NETDEVICES is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
@@ -492,6 +467,7 @@ CONFIG_SCSI_MULTI_LUN=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -501,7 +477,6 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -511,8 +486,10 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
@@ -521,6 +498,7 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
 # CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_INPUT_MISC is not set
 
 #
@@ -554,37 +532,50 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
 
 #
-# TPM devices
+# I2C Algorithms
 #
-# CONFIG_TCG_TPM is not set
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C support
+# I2C Hardware Bus support
 #
-# CONFIG_I2C is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_PCA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 
 #
 # SPI support
@@ -603,21 +594,25 @@ CONFIG_SPI_ATMEL=y
 # SPI Protocol Masters
 #
 # CONFIG_SPI_AT25 is not set
-
-#
-# Dallas's 1-wire bus
-#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
 # CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Hardware Monitoring support
+# Watchdog Device Drivers
 #
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9_WATCHDOG=y
 
 #
-# Misc devices
+# Sonics Silicon Backplane
 #
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
 # Multifunction device drivers
@@ -625,37 +620,28 @@ CONFIG_SPI_ATMEL=y
 # CONFIG_MFD_SM501 is not set
 
 #
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -665,9 +651,16 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 #
 # Frame buffer hardware drivers
 #
+# CONFIG_FB_S1D15605 is not set
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_ATMEL=y
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -675,97 +668,97 @@ CONFIG_FB_ATMEL=y
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
 # CONFIG_FRAMEBUFFER_CONSOLE is not set
-
-#
-# Logo configuration
-#
 # CONFIG_LOGO is not set
 
 #
 # Sound
 #
-CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_SEQUENCER=y
-CONFIG_SND_SEQ_DUMMY=y
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_SEQUENCER_OSS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_VERBOSE_PRINTK=y
-CONFIG_SND_DEBUG=y
-CONFIG_SND_DEBUG_DETECT=y
-# CONFIG_SND_PCM_XRUN_DEBUG is not set
-
-#
-# Generic devices
-#
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_VIRMIDI is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
 
 #
-# ALSA ARM devices
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
 
 #
-# SoC audio support
+# USB Gadget Support
 #
-# CONFIG_SND_SOC is not set
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# Open Sound System
+# MMC/SD Card Drivers
 #
-# CONFIG_SOUND_PRIME is not set
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
 
 #
-# HID Devices
+# MMC/SD Host Controller Drivers
 #
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
+CONFIG_MMC_AT91=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# USB support
+# RTC interfaces
 #
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# I2C RTC drivers
 #
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
 
 #
-# USB Gadget Support
+# SPI RTC drivers
 #
-# CONFIG_USB_GADGET is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
 
 #
-# MMC/SD Card support
+# Platform RTC drivers
 #
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AT91=y
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# Real Time Clock
+# on-CPU RTC drivers
 #
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_DRV_AT91SAM9=y
 
 #
 # File systems
@@ -816,7 +809,6 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
 
 #
@@ -836,20 +828,13 @@ CONFIG_CRAMFS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -890,16 +875,15 @@ CONFIG_NLS_ISO8859_15=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 CONFIG_NLS_UTF8=y
-
-#
-# Profiling support
-#
+CONFIG_INSTRUMENTATION=y
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
@@ -907,8 +891,8 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_SLAB is not set
@@ -916,6 +900,9 @@ CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
@@ -923,10 +910,13 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
@@ -937,10 +927,7 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 # CONFIG_CRYPTO is not set
 
 #
@@ -949,9 +936,12 @@ CONFIG_DEBUG_LL=y
 CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ateb9200_defconfig b/arch/arm/configs/ateb9200_defconfig
index baa97698c744..d846a492e5ce 100644
--- a/arch/arm/configs/ateb9200_defconfig
+++ b/arch/arm/configs/ateb9200_defconfig
@@ -714,7 +714,7 @@ CONFIG_I2C_ALGOPCA=m
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=m
+CONFIG_I2C_GPIO=m
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_STUB is not set
 # CONFIG_I2C_PCA_ISA is not set
diff --git a/arch/arm/configs/cam60_defconfig b/arch/arm/configs/cam60_defconfig
new file mode 100644
index 000000000000..f3cd4a95373a
--- /dev/null
+++ b/arch/arm/configs/cam60_defconfig
@@ -0,0 +1,1228 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24
+# Thu Mar  6 10:07:26 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_AUDIT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+CONFIG_MACH_CAM60=y
+# CONFIG_MACH_SAM9_L9260 is not set
+
+#
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0x20004000
+# CONFIG_ZBOOT_ROM is not set
+CONFIG_CMDLINE="console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_AOUT=y
+CONFIG_BINFMT_MISC=y
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_NETWORK_SECMARK=y
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+CONFIG_CFG80211=m
+CONFIG_NL80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_RCSIMPLE=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_RAM=m
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_PLATRAM=m
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+# CONFIG_MTD_NAND_AT91_ECC_SOFT is not set
+CONFIG_MTD_NAND_AT91_ECC_HW=y
+# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=y
+CONFIG_SCSI_NETLINK=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_ATTRS=m
+# CONFIG_SCSI_FC_TGT_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+CONFIG_SCSI_SAS_ATTRS=m
+CONFIG_SCSI_SAS_LIBSAS=m
+# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+# CONFIG_ICPLUS_PHY is not set
+CONFIG_FIXED_PHY=m
+# CONFIG_FIXED_MII_10_FDX is not set
+# CONFIG_FIXED_MII_100_FDX is not set
+# CONFIG_FIXED_MII_1000_FDX is not set
+CONFIG_FIXED_MII_AMNT=1
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_STOWAWAY=m
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_SERIAL=m
+CONFIG_MOUSE_APPLETOUCH=m
+CONFIG_MOUSE_VSXXXAA=m
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_NONSTANDARD=y
+# CONFIG_MOXA_SMARTIO is not set
+# CONFIG_N_HDLC is not set
+# CONFIG_RISCOM8 is not set
+# CONFIG_SPECIALIX is not set
+# CONFIG_RIO is not set
+# CONFIG_STALDRV is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_BITBANG is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_TEST=m
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_RTC_DRV_AT91SAM9_RTT=0
+CONFIG_RTC_DRV_AT91SAM9_GPBR=0
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+CONFIG_DNOTIFY=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_YAFFS_FS=y
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_9BYTE_TAGS is not set
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+# CONFIG_INSTRUMENTATION is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_FORCED_INLINING is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ABLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_NULL=m
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+# CONFIG_CRYPTO_XTS is not set
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_ANUBIS=m
+# CONFIG_CRYPTO_SEED is not set
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_TEST=m
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=m
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=m
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/csb337_defconfig b/arch/arm/configs/csb337_defconfig
index 88e5d28aeec7..67e65e4f0cdc 100644
--- a/arch/arm/configs/csb337_defconfig
+++ b/arch/arm/configs/csb337_defconfig
@@ -1,69 +1,96 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.15
-# Mon Jan  9 21:51:31 2006
+# Linux kernel version: 2.6.24-rc7
+# Wed Jan  9 22:19:24 2008
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-CONFIG_UID16=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
 # CONFIG_AUDIT is not set
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -81,62 +108,101 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 #
 # System Type
 #
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_IOP3XX is not set
-# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
 # CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_AAEC2000 is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91RM9200=y
 
 #
-# AT91RM9200 Implementations
+# Boot options
 #
 
 #
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
 # AT91RM9200 Board Type
 #
+# CONFIG_MACH_ONEARM is not set
 # CONFIG_ARCH_AT91RM9200DK is not set
 # CONFIG_MACH_AT91RM9200EK is not set
 CONFIG_MACH_CSB337=y
 # CONFIG_MACH_CSB637 is not set
 # CONFIG_MACH_CARMEVA is not set
-# CONFIG_MACH_KB9200 is not set
 # CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
+# CONFIG_MACH_CHUB is not set
+# CONFIG_MACH_HOMEMATIC is not set
+# CONFIG_MACH_ECBAT91 is not set
+# CONFIG_MACH_SWEDATMS is not set
+
+#
+# AT91 Board Options
+#
 
 #
-# AT91RM9200 Feature Selections
+# AT91 Feature Selections
 #
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+CONFIG_AT91_TIMER_HZ=128
 
 #
 # Processor Type
 #
 CONFIG_CPU_32=y
 CONFIG_CPU_ARM920T=y
-CONFIG_CPU_32v4=y
+CONFIG_CPU_32v4T=y
 CONFIG_CPU_ABRT_EV4T=y
 CONFIG_CPU_CACHE_V4WT=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_COPY_V4WB=y
 CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
 
 #
 # Processor Features
@@ -145,15 +211,13 @@ CONFIG_CPU_TLB_V4WBI=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
 
 #
 # Bus support
 #
-CONFIG_ISA_DMA_API=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_PCCARD=y
 # CONFIG_PCMCIA_DEBUG is not set
 CONFIG_PCMCIA=y
@@ -168,8 +232,13 @@ CONFIG_AT91_CF=y
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=128
+# CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
@@ -178,9 +247,13 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 CONFIG_LEDS=y
-CONFIG_LEDS_TIMER=y
 CONFIG_LEDS_CPU=y
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -191,6 +264,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw"
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
 
 #
 # Floating point emulation
@@ -215,6 +289,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
 
 #
 # Networking
@@ -227,6 +302,10 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -243,23 +322,26 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
@@ -269,13 +351,8 @@ CONFIG_TCP_CONG_BIC=y
 # CONFIG_ATALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -285,7 +362,17 @@ CONFIG_TCP_CONG_BIC=y
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -294,19 +381,14 @@ CONFIG_TCP_CONG_BIC=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
 # CONFIG_DEBUG_DRIVER is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -319,11 +401,14 @@ CONFIG_MTD_CMDLINE_PARTS=y
 # User Modules And Translation Layers
 #
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -349,15 +434,14 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0
-CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
 CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 # CONFIG_MTD_PLATRAM is not set
@@ -368,7 +452,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
 # CONFIG_MTD_BLOCK2MTD is not set
 
 #
@@ -378,29 +461,15 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
 # CONFIG_MTD_AT91_DATAFLASH is not set
-
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -409,13 +478,12 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_INITRD=y
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=y
 # CONFIG_IDE is not set
 
 #
@@ -423,6 +491,9 @@ CONFIG_BLK_DEV_INITRD=y
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 
 #
@@ -441,97 +512,61 @@ CONFIG_SCSI_PROC_FS=y
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
-# SCSI Transport Attributes
+# SCSI Transports
 #
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_SATA is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# PCMCIA SCSI adapter support
-#
-# CONFIG_PCMCIA_AHA152X is not set
-# CONFIG_PCMCIA_FDOMAIN is not set
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-# CONFIG_PCMCIA_QLOGIC is not set
-# CONFIG_PCMCIA_SYM53C500 is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_ATA is not set
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_ARM_AT91_ETHER=y
+# CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
 
 #
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# PCMCIA network device support
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_NET_PCMCIA is not set
-
-#
-# Wan interfaces
-#
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -539,26 +574,23 @@ CONFIG_ARM_AT91_ETHER=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
 #
 CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -568,6 +600,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -583,6 +616,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -601,152 +635,114 @@ CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_AT91RM9200_WATCHDOG=y
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
 #
-# Ftape, the floppy tape device driver
-#
-
-#
 # PCMCIA character devices
 #
 # CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
 CONFIG_AT91_SPI=y
 CONFIG_AT91_SPIDEV=y
-
-#
-# I2C support
-#
 CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_STUB is not set
-# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
 
 #
 # Miscellaneous I2C Chip support
 #
 # CONFIG_SENSORS_DS1337 is not set
 # CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_SENSORS_PCA9539 is not set
 # CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_RTC8564 is not set
 # CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_RTC_X1205_I2C is not set
+# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
 
 #
-# Hardware Monitoring support
-#
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia Capabilities Port drivers
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Multimedia devices
+# Watchdog Device Drivers
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91RM9200_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -758,12 +754,25 @@ CONFIG_DUMMY_CONSOLE=y
 # Sound
 #
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
 
 #
-# USB support
+# USB HID Boot Protocol drivers
 #
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
 CONFIG_USB=y
 CONFIG_USB_DEBUG=y
 
@@ -771,7 +780,7 @@ CONFIG_USB_DEBUG=y
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
 
@@ -780,9 +789,11 @@ CONFIG_USB_DEVICEFS=y
 #
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
@@ -801,59 +812,21 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_MTOUCH is not set
-# CONFIG_USB_ITMTOUCH is not set
-# CONFIG_USB_EGALAX is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
 
 #
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-
-#
-# USB Multimedia devices
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# Video4Linux support is needed for USB Multimedia device support
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
 CONFIG_USB_MON=y
 
 #
@@ -866,15 +839,18 @@ CONFIG_USB_MON=y
 CONFIG_USB_SERIAL=y
 CONFIG_USB_SERIAL_CONSOLE=y
 CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
 # CONFIG_USB_SERIAL_AIRPRIME is not set
-# CONFIG_USB_SERIAL_ANYDATA is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
 # CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
 # CONFIG_USB_SERIAL_WHITEHEAT is not set
 # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
 # CONFIG_USB_SERIAL_CP2101 is not set
 # CONFIG_USB_SERIAL_CYPRESS_M8 is not set
 # CONFIG_USB_SERIAL_EMPEG is not set
 CONFIG_USB_SERIAL_FTDI_SIO=y
+# CONFIG_USB_SERIAL_FUNSOFT is not set
 # CONFIG_USB_SERIAL_VISOR is not set
 # CONFIG_USB_SERIAL_IPAQ is not set
 # CONFIG_USB_SERIAL_IR is not set
@@ -899,14 +875,20 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
 # CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_KOBIL_SCT is not set
 CONFIG_USB_SERIAL_MCT_U232=y
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
 # CONFIG_USB_SERIAL_HP4X is not set
 # CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
 # CONFIG_USB_SERIAL_TI is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
 # CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_OPTION is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
 CONFIG_USB_EZUSB=y
 
 #
@@ -914,16 +896,22 @@ CONFIG_USB_EZUSB=y
 #
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
 # CONFIG_USB_AUERSWALD is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGETKIT is not set
-# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
 # CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
 
 #
@@ -934,13 +922,19 @@ CONFIG_USB_EZUSB=y
 # USB Gadget Support
 #
 CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
 CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
 CONFIG_USB_GADGET_AT91=y
 CONFIG_USB_AT91=y
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
@@ -950,22 +944,28 @@ CONFIG_USB_AT91=y
 # CONFIG_USB_GADGETFS is not set
 # CONFIG_USB_FILE_STORAGE is not set
 # CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# MMC/SD Card support
+# MMC/SD Card Drivers
 #
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
 CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AT91RM9200=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
 
 #
-# Real Time Clock
+# MMC/SD Host Controller Drivers
 #
+# CONFIG_MMC_AT91 is not set
+# CONFIG_NEW_LEDS is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_HCTOSYS=y
 CONFIG_RTC_HCTOSYS_DEVICE="rtc1"
+# CONFIG_RTC_DEBUG is not set
 
 #
 # RTC interfaces
@@ -974,39 +974,60 @@ CONFIG_RTC_HCTOSYS_DEVICE="rtc1"
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# RTC drivers
+# I2C RTC drivers
 #
-# CONFIG_RTC_DRV_X1205 is not set
 CONFIG_RTC_DRV_DS1307=y
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
 # CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_PCF8563 is not set
 # CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
-CONFIG_RTC_DRV_AT91RM9200=y
-# CONFIG_RTC_DRV_TEST is not set
+# CONFIG_RTC_DRV_M48T59 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 
 #
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91RM9200=y
+
+#
 # File systems
 #
 CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
+# CONFIG_EXT4DEV_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_ROMFS_FS is not set
 CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
 CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
@@ -1030,11 +1051,12 @@ CONFIG_DNOTIFY=y
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
+# CONFIG_CONFIGFS_FS is not set
 
 #
 # Miscellaneous filesystems
@@ -1046,7 +1068,6 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
 # CONFIG_JFFS2_FS is not set
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
@@ -1054,10 +1075,7 @@ CONFIG_CRAMFS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
@@ -1070,6 +1088,7 @@ CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1077,43 +1096,56 @@ CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 # CONFIG_NLS is not set
-
-#
-# Profiling support
-#
+# CONFIG_DLM is not set
+CONFIG_INSTRUMENTATION=y
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
 CONFIG_DEBUG_LL=y
@@ -1124,12 +1156,13 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
 # CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
@@ -1138,7 +1171,15 @@ CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_SHA512 is not set
 # CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
 CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_BLOWFISH is not set
 # CONFIG_CRYPTO_TWOFISH is not set
 # CONFIG_CRYPTO_SERPENT is not set
@@ -1149,20 +1190,27 @@ CONFIG_CRYPTO_DES=y
 # CONFIG_CRYPTO_ARC4 is not set
 # CONFIG_CRYPTO_KHAZAD is not set
 # CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
 # CONFIG_CRYPTO_DEFLATE is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/csb637_defconfig b/arch/arm/configs/csb637_defconfig
index 669f035896f9..99702146c9fc 100644
--- a/arch/arm/configs/csb637_defconfig
+++ b/arch/arm/configs/csb637_defconfig
@@ -1,69 +1,112 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.15
-# Mon Jan  9 21:52:00 2006
+# Linux kernel version: 2.6.25-rc8
+# Fri Apr  4 22:06:15 2008
 #
 CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-CONFIG_UID16=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
 # CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
 # CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_KMOD=y
-
-#
-# Block layer
-#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
 
 #
 # IO Schedulers
@@ -77,66 +120,111 @@ CONFIG_DEFAULT_AS=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_CLASSIC_RCU=y
 
 #
 # System Type
 #
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
 # CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_IOP3XX is not set
-# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
 # CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION is not set
+# CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_AAEC2000 is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
 
 #
-# AT91RM9200 Implementations
+# Atmel AT91 System-on-Chip
 #
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
 
 #
 # AT91RM9200 Board Type
 #
+# CONFIG_MACH_ONEARM is not set
 # CONFIG_ARCH_AT91RM9200DK is not set
 # CONFIG_MACH_AT91RM9200EK is not set
 # CONFIG_MACH_CSB337 is not set
 CONFIG_MACH_CSB637=y
 # CONFIG_MACH_CARMEVA is not set
-# CONFIG_MACH_KB9200 is not set
 # CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
 
 #
-# AT91RM9200 Feature Selections
+# AT91 Board Options
+#
+
+#
+# AT91 Feature Selections
 #
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_TIMER_HZ=128
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
 
 #
 # Processor Type
 #
 CONFIG_CPU_32=y
 CONFIG_CPU_ARM920T=y
-CONFIG_CPU_32v4=y
+CONFIG_CPU_32v4T=y
 CONFIG_CPU_ABRT_EV4T=y
 CONFIG_CPU_CACHE_V4WT=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_COPY_V4WB=y
 CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
 
 #
 # Processor Features
@@ -145,15 +233,13 @@ CONFIG_CPU_TLB_V4WBI=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
 
 #
 # Bus support
 #
-CONFIG_ISA_DMA_API=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_PCCARD=y
 # CONFIG_PCMCIA_DEBUG is not set
 CONFIG_PCMCIA=y
@@ -168,8 +254,13 @@ CONFIG_AT91_CF=y
 #
 # Kernel Features
 #
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=128
+# CONFIG_AEABI is not set
 # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
@@ -178,9 +269,13 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 # CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
 CONFIG_LEDS=y
-CONFIG_LEDS_TIMER=y
 CONFIG_LEDS_CPU=y
 CONFIG_ALIGNMENT_TRAP=y
 
@@ -191,6 +286,7 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw"
 # CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
 
 #
 # Floating point emulation
@@ -215,6 +311,7 @@ CONFIG_BINFMT_ELF=y
 # Power management options
 #
 # CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 
 #
 # Networking
@@ -227,6 +324,11 @@ CONFIG_NET=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
 # CONFIG_IP_MULTICAST is not set
@@ -243,23 +345,26 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
 CONFIG_INET_DIAG=y
 CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_VLAN_8021Q is not set
@@ -269,13 +374,8 @@ CONFIG_TCP_CONG_BIC=y
 # CONFIG_ATALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
 # CONFIG_NET_SCHED is not set
 
 #
@@ -283,9 +383,20 @@ CONFIG_TCP_CONG_BIC=y
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -294,19 +405,14 @@ CONFIG_TCP_CONG_BIC=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
 # CONFIG_DEBUG_DRIVER is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -319,11 +425,14 @@ CONFIG_MTD_CMDLINE_PARTS=y
 # User Modules And Translation Layers
 #
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -349,15 +458,14 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
 CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0
-CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_MTD_PHYSMAP_LEN=0x0
 CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_ARM_INTEGRATOR is not set
 # CONFIG_MTD_PLATRAM is not set
@@ -368,7 +476,6 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
 # CONFIG_MTD_BLOCK2MTD is not set
 
 #
@@ -377,30 +484,15 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=0
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_AT91_DATAFLASH is not set
-
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -409,13 +501,15 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_INITRD=y
+# CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+CONFIG_MISC_DEVICES=y
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
@@ -423,6 +517,9 @@ CONFIG_BLK_DEV_INITRD=y
 #
 # CONFIG_RAID_ATTRS is not set
 CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
 CONFIG_SCSI_PROC_FS=y
 
 #
@@ -441,114 +538,78 @@ CONFIG_SCSI_PROC_FS=y
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 
 #
-# SCSI Transport Attributes
+# SCSI Transports
 #
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
 # CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-
-#
-# SCSI low-level drivers
-#
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
 # CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_SATA is not set
 # CONFIG_SCSI_DEBUG is not set
-
-#
-# PCMCIA SCSI adapter support
-#
-# CONFIG_PCMCIA_AHA152X is not set
-# CONFIG_PCMCIA_FDOMAIN is not set
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-# CONFIG_PCMCIA_QLOGIC is not set
-# CONFIG_PCMCIA_SYM53C500 is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_ATA is not set
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_ARM_AT91_ETHER=y
+# CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
+# CONFIG_SMSC911X is not set
 # CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_CS89x0 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_E1000E_ENABLED is not set
+CONFIG_NETDEV_10000=y
 
 #
-# Ethernet (1000 Mbit)
+# Wireless LAN
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 
 #
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# PCMCIA network device support
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_NET_PCMCIA is not set
-
-#
-# Wan interfaces
-#
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 
 #
 # Userland interfaces
@@ -558,7 +619,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 # CONFIG_INPUT_EVDEV is not set
 # CONFIG_INPUT_EVBUG is not set
 
@@ -568,6 +628,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
@@ -583,6 +644,7 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
@@ -595,64 +657,29 @@ CONFIG_HW_CONSOLE=y
 #
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
 # CONFIG_SERIAL_ATMEL_TTYAT is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_AT91RM9200_WATCHDOG=y
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=m
 # CONFIG_NVRAM is not set
-CONFIG_RTC=y
-# CONFIG_AT91RM9200_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
 #
-# Ftape, the floppy tape device driver
-#
-
-#
 # PCMCIA character devices
 #
 # CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
-CONFIG_AT91_SPI=y
-CONFIG_AT91_SPIDEV=y
-
-#
-# I2C support
-#
 CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 
 #
@@ -665,43 +692,53 @@ CONFIG_I2C_CHARDEV=y
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
 # CONFIG_I2C_STUB is not set
-# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_TINY_USB is not set
 
 #
 # Miscellaneous I2C Chip support
 #
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
 # CONFIG_SENSORS_EEPROM is not set
 # CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_RTC8564 is not set
+# CONFIG_TPS65010 is not set
 # CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_RTC_X1205_I2C is not set
+# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
 
 #
-# Hardware Monitoring support
+# SPI support
 #
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7418 is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
 # CONFIG_SENSORS_ADM1031 is not set
 # CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
 # CONFIG_SENSORS_ATXP1 is not set
 # CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
@@ -715,39 +752,72 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM87 is not set
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
 # CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
 # CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
 # CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
 # CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
 # CONFIG_SENSORS_W83627HF is not set
 # CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
-# Misc devices
+# Watchdog Device Drivers
 #
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91RM9200_WATCHDOG=y
 
 #
-# Multimedia Capabilities Port drivers
+# USB-based Watchdog Cards
 #
+# CONFIG_USBPCWATCHDOG is not set
 
 #
-# Multimedia devices
+# Sonics Silicon Backplane
 #
-# CONFIG_VIDEO_DEV is not set
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -759,20 +829,34 @@ CONFIG_DUMMY_CONSOLE=y
 # Sound
 #
 # CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
 
 #
-# USB support
+# USB Input Devices
 #
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
 CONFIG_USB=y
 CONFIG_USB_DEBUG=y
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
 #
 CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
+CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
 
@@ -781,9 +865,11 @@ CONFIG_USB_DEVICEFS=y
 #
 # CONFIG_USB_ISP116X_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
 
 #
 # USB Device Class drivers
@@ -802,80 +888,42 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
 # CONFIG_USB_STORAGE_DPCM is not set
 # CONFIG_USB_STORAGE_USBAT is not set
 # CONFIG_USB_STORAGE_SDDR09 is not set
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_MTOUCH is not set
-# CONFIG_USB_ITMTOUCH is not set
-# CONFIG_USB_EGALAX is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
 
 #
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 # CONFIG_USB_MICROTEK is not set
-
-#
-# USB Multimedia devices
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# Video4Linux support is needed for USB Multimedia device support
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
 CONFIG_USB_MON=y
 
 #
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 CONFIG_USB_SERIAL=y
 CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_EZUSB=y
 CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
 # CONFIG_USB_SERIAL_AIRPRIME is not set
-# CONFIG_USB_SERIAL_ANYDATA is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
 # CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
 # CONFIG_USB_SERIAL_WHITEHEAT is not set
 # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
 # CONFIG_USB_SERIAL_CP2101 is not set
 # CONFIG_USB_SERIAL_CYPRESS_M8 is not set
 # CONFIG_USB_SERIAL_EMPEG is not set
 CONFIG_USB_SERIAL_FTDI_SIO=y
+# CONFIG_USB_SERIAL_FUNSOFT is not set
 # CONFIG_USB_SERIAL_VISOR is not set
 # CONFIG_USB_SERIAL_IPAQ is not set
 # CONFIG_USB_SERIAL_IR is not set
@@ -883,6 +931,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=y
 # CONFIG_USB_SERIAL_EDGEPORT_TI is not set
 # CONFIG_USB_SERIAL_GARMIN is not set
 # CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
 CONFIG_USB_SERIAL_KEYSPAN=y
 CONFIG_USB_SERIAL_KEYSPAN_MPR=y
@@ -900,46 +949,66 @@ CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
 # CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_KOBIL_SCT is not set
 CONFIG_USB_SERIAL_MCT_U232=y
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
 # CONFIG_USB_SERIAL_HP4X is not set
 # CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
 # CONFIG_USB_SERIAL_TI is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
 # CONFIG_USB_SERIAL_XIRCOM is not set
 # CONFIG_USB_SERIAL_OPTION is not set
 # CONFIG_USB_SERIAL_OMNINET is not set
-CONFIG_USB_EZUSB=y
+# CONFIG_USB_SERIAL_DEBUG is not set
 
 #
 # USB Miscellaneous drivers
 #
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
 # CONFIG_USB_AUERSWALD is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
 # CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGETKIT is not set
-# CONFIG_USB_PHIDGETSERVO is not set
+# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
 # CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
 # CONFIG_USB_TEST is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 
 #
-# USB DSL modem support
+# LED drivers
 #
+CONFIG_LEDS_GPIO=y
 
 #
-# USB Gadget Support
+# LED Triggers
 #
-# CONFIG_USB_GADGET is not set
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
 
 #
-# MMC/SD Card support
+# Userspace I/O
 #
-# CONFIG_MMC is not set
+# CONFIG_UIO is not set
 
 #
 # File systems
@@ -948,16 +1017,17 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
+# CONFIG_EXT4DEV_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
@@ -979,11 +1049,12 @@ CONFIG_DNOTIFY=y
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_RELAYFS_FS is not set
+# CONFIG_CONFIGFS_FS is not set
 
 #
 # Miscellaneous filesystems
@@ -995,18 +1066,16 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
 # CONFIG_JFFS2_FS is not set
 CONFIG_CRAMFS=y
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
@@ -1019,6 +1088,7 @@ CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -1026,45 +1096,57 @@ CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
 # CONFIG_NLS is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
 CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_FS is not set
 # CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
 CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
 CONFIG_DEBUG_USER=y
 # CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_ICEDCC is not set
 
@@ -1073,12 +1155,14 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_MANAGER=y
 # CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
@@ -1087,7 +1171,18 @@ CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_SHA512 is not set
 # CONFIG_CRYPTO_WP512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
 CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_BLOWFISH is not set
 # CONFIG_CRYPTO_TWOFISH is not set
 # CONFIG_CRYPTO_SERPENT is not set
@@ -1098,20 +1193,29 @@ CONFIG_CRYPTO_DES=y
 # CONFIG_CRYPTO_ARC4 is not set
 # CONFIG_CRYPTO_KHAZAD is not set
 # CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
 # CONFIG_CRYPTO_DEFLATE is not set
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
 
 #
 # Library routines
 #
+CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ecbat91_defconfig b/arch/arm/configs/ecbat91_defconfig
new file mode 100644
index 000000000000..90ed214e3673
--- /dev/null
+++ b/arch/arm/configs/ecbat91_defconfig
@@ -0,0 +1,1315 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.22-rc4
+# Sat Jun  9 01:30:18 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+
+#
+# AT91RM9200 Board Type
+#
+# CONFIG_MACH_ONEARM is not set
+# CONFIG_ARCH_AT91RM9200DK is not set
+# CONFIG_MACH_AT91RM9200EK is not set
+# CONFIG_MACH_CSB337 is not set
+# CONFIG_MACH_CSB637 is not set
+# CONFIG_MACH_CARMEVA is not set
+# CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
+# CONFIG_MACH_CHUB is not set
+CONFIG_MACH_ECBAT91=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
+
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+# CONFIG_ATMEL_TCLIB is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_PCMCIA_IOCTL=y
+
+#
+# PC-card bridges
+#
+CONFIG_AT91_CF=y
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+CONFIG_PREEMPT=y
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="rootfstype=reiserfs root=/dev/mmcblk0p1 console=ttyS0,115200n8 rootdelay=1"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+CONFIG_CFG80211=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_MAC80211=y
+# CONFIG_MAC80211_DEBUG is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+CONFIG_IEEE80211_SOFTMAC=y
+CONFIG_IEEE80211_SOFTMAC_DEBUG=y
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_AFS_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNPACPI is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# PCMCIA SCSI adapter support
+#
+# CONFIG_PCMCIA_AHA152X is not set
+# CONFIG_PCMCIA_FDOMAIN is not set
+# CONFIG_PCMCIA_NINJA_SCSI is not set
+# CONFIG_PCMCIA_QLOGIC is not set
+# CONFIG_PCMCIA_SYM53C500 is not set
+# CONFIG_ATA is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_AT91_ETHER=y
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_NET_PCMCIA is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_AT91RM9200_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_AT91_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_PCA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ATMEL is not set
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_AT91=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Misc devices
+#
+# CONFIG_BLINK is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# LED devices
+#
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGERS is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# HID Devices
+#
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB Input Devices
+#
+# CONFIG_USB_HID is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+CONFIG_USB_PRINTER=y
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_AT91=y
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91RM9200=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+CONFIG_CONFIGFS_FS=y
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_FRAME_POINTER=y
+CONFIG_DEBUG_USER=y
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/kafa_defconfig b/arch/arm/configs/kafa_defconfig
index a0f48d54fbcc..ae51a40db6f9 100644
--- a/arch/arm/configs/kafa_defconfig
+++ b/arch/arm/configs/kafa_defconfig
@@ -587,14 +587,14 @@ CONFIG_I2C_CHARDEV=y
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=y
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=y
+CONFIG_I2C_GPIO=y
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_STUB is not set
 # CONFIG_I2C_PCA_ISA is not set
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
new file mode 100644
index 000000000000..4d11678584db
--- /dev/null
+++ b/arch/arm/configs/magician_defconfig
@@ -0,0 +1,1182 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc6
+# Sun Dec 30 13:02:54 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_CGROUPS is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+# CONFIG_UID16 is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_ARMCORE is not set
+CONFIG_MACH_MAGICIAN=y
+CONFIG_PXA27x=y
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="keepinitrd"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_LEGACY is not set
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_SUSPEND=y
+CONFIG_APM_EMULATION=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+# CONFIG_IRNET is not set
+CONFIG_IRCOMM=m
+CONFIG_IRDA_ULTRA=y
+
+#
+# IrDA options
+#
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRDA_FAST_RR=y
+CONFIG_IRDA_DEBUG=y
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+CONFIG_IRTTY_SIR=m
+
+#
+# Dongle support
+#
+# CONFIG_DONGLE is not set
+
+#
+# Old SIR device drivers
+#
+# CONFIG_IRPORT_SIR is not set
+
+#
+# Old Serial dongle support
+#
+
+#
+# FIR device drivers
+#
+CONFIG_PXA_FICP=m
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=0
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x00000000
+CONFIG_MTD_PHYSMAP_LEN=0x04000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=4
+# CONFIG_MTD_PXA2XX is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_NET_ETHERNET is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_PXA27x is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+# CONFIG_SERIAL_PXA_CONSOLE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_PXA=m
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+CONFIG_W1=y
+
+#
+# 1-wire Bus Masters
+#
+# CONFIG_W1_MASTER_DS2482 is not set
+CONFIG_W1_MASTER_DS1WM=y
+
+#
+# 1-wire Slaves
+#
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+CONFIG_W1_SLAVE_DS2760=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PDA_POWER=y
+# CONFIG_APM_POWER is not set
+CONFIG_BATTERY_DS2760=y
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+CONFIG_HTC_EGPIO=y
+CONFIG_HTC_PASIC3=y
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_PARAMETERS is not set
+# CONFIG_FB_MBX is not set
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CORGI=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_8x16 is not set
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+CONFIG_FONT_MINI_4x6=y
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+
+#
+# ALSA ARM devices
+#
+# CONFIG_SND_PXA2XX_AC97 is not set
+
+#
+# System on Chip audio support
+#
+CONFIG_SND_SOC=m
+CONFIG_SND_PXA2XX_SOC=m
+
+#
+# SoC Audio support for SuperH
+#
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_HID=m
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=m
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+CONFIG_NEW_LEDS=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+CONFIG_RTC_DEBUG=y
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+CONFIG_NLS_CODEPAGE_1251=m
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_MANAGER=m
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_CBC is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ns9xxx_defconfig b/arch/arm/configs/ns9xxx_defconfig
index 0e5794c6a48e..7dc1580e4d99 100644
--- a/arch/arm/configs/ns9xxx_defconfig
+++ b/arch/arm/configs/ns9xxx_defconfig
@@ -1,621 +1,79 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Thu Feb 15 20:51:47 2007
-#
-CONFIG_ARM=y
-# CONFIG_GENERIC_TIME is not set
-CONFIG_MMU=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_UTS_NS is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
-CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLAB=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
 # CONFIG_IOSCHED_AS is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_DEFAULT_IOSCHED="noop"
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_L7200 is not set
 CONFIG_ARCH_NS9XXX=y
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_OMAP is not set
-
-#
-# NS9xxx Implementations
-#
+CONFIG_MACH_A9M9360=y
+CONFIG_MACH_A9M9750=y
+CONFIG_MACH_CC7UCAMRY=y
+CONFIG_MACH_CC9C=y
+CONFIG_MACH_CC9P9210=y
+CONFIG_MACH_CC9P9210JS=y
+CONFIG_MACH_CC9P9215=y
+CONFIG_MACH_CC9P9215JS=y
 CONFIG_MACH_CC9P9360DEV=y
-CONFIG_PROCESSOR_NS9360=y
-CONFIG_BOARD_A9M9750DEV=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_32=y
-CONFIG_CPU_ARM926T=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-# CONFIG_ARM_THUMB is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-
-#
-# Bus support
-#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-# CONFIG_PREEMPT is not set
-# CONFIG_NO_IDLE_HZ is not set
-CONFIG_HZ=100
-# CONFIG_AEABI is not set
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
+CONFIG_MACH_CC9P9360JS=y
+CONFIG_MACH_CC9P9360VAL=y
+CONFIG_MACH_CC9P9750DEV=y
+CONFIG_MACH_CC9P9750VAL=y
+CONFIG_MACH_CCW9C=y
+CONFIG_MACH_INC20OTTER=y
+CONFIG_MACH_OTTER=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-# CONFIG_VFP is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-# CONFIG_ARTHUR is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-# CONFIG_APM is not set
-
-#
-# Networking
-#
-# CONFIG_NET is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CDROM_PKTCDVD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# ISDN subsystem
-#
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
+CONFIG_NET=y
+CONFIG_PACKET=m
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_SYN_COOKIES=y
+CONFIG_MTD=m
+CONFIG_MTD_CONCAT=m
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_CFI=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP_START=0x0
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NS9XXX_ETH=y
 # CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_EXTENDED=y
-# CONFIG_SERIAL_8250_MANY_PORTS is not set
-# CONFIG_SERIAL_8250_SHARE_IRQ is not set
-# CONFIG_SERIAL_8250_DETECT_IRQ is not set
-# CONFIG_SERIAL_8250_RSA is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
+CONFIG_SERIAL_NS921X=y
+CONFIG_SERIAL_NS921X_CONSOLE=y
 # CONFIG_LEGACY_PTYS is not set
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+CONFIG_ADC_NS9215=m
+CONFIG_I2C=m
+CONFIG_I2C_GPIO=m
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-
-#
-# Misc devices
-#
-# CONFIG_TIFM_CORE is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-
-#
-# Graphics support
-#
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
 # CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
-CONFIG_HID=y
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# Real Time Clock
-#
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_RTC_CLASS=m
+CONFIG_RTC_DRV_NS9215=m
+CONFIG_EXT2_FS=m
 CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
+CONFIG_JFFS2_FS=m
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 # CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_LIST is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
 CONFIG_DEBUG_USER=y
 CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_ICEDCC=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-# CONFIG_CRYPTO is not set
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC32 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-CONFIG_IOMAP_COPY=y
diff --git a/arch/arm/configs/orion_defconfig b/arch/arm/configs/orion5x_defconfig
index 1e5aaa645fcd..52cd99bd52fb 100644
--- a/arch/arm/configs/orion_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -140,7 +140,7 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_MXC is not set
-CONFIG_ARCH_ORION=y
+CONFIG_ARCH_ORION5X=y
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set
diff --git a/arch/arm/configs/picotux200_defconfig b/arch/arm/configs/picotux200_defconfig
index 3c0c4f192dc1..95a22f512805 100644
--- a/arch/arm/configs/picotux200_defconfig
+++ b/arch/arm/configs/picotux200_defconfig
@@ -727,14 +727,14 @@ CONFIG_I2C_CHARDEV=m
 #
 # I2C Algorithms
 #
-# CONFIG_I2C_ALGOBIT is not set
+CONFIG_I2C_ALGOBIT=m
 # CONFIG_I2C_ALGOPCF is not set
 # CONFIG_I2C_ALGOPCA is not set
 
 #
 # I2C Hardware Bus support
 #
-CONFIG_I2C_AT91=m
+CONFIG_I2C_GPIO=m
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_STUB is not set
diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
new file mode 100644
index 000000000000..484dc9739dfc
--- /dev/null
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -0,0 +1,1098 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.23
+# Sun Oct 14 02:01:07 2007
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_GENERIC_TIME is not set
+# CONFIG_GENERIC_CLOCKEVENTS is not set
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+CONFIG_AUDIT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LSF=y
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+# CONFIG_MACH_CAM60 is not set
+CONFIG_MACH_SAM9_L9260=y
+
+#
+# AT91 Board Options
+#
+CONFIG_MTD_AT91_DATAFLASH_CARD=y
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+# CONFIG_ATMEL_TCLIB is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+CONFIG_PREEMPT=y
+# CONFIG_NO_IDLE_HZ is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_LEDS=y
+CONFIG_LEDS_TIMER=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200 mem=64M initrd=0x21100000,4194304 root=/dev/ram0 rw"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_BLOCK2MTD=y
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_AT91=y
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=3
+CONFIG_MTD_UBI_GLUEBI=y
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=y
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET_MII is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_HWMON is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_AT91=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_DS1553=y
+# CONFIG_RTC_DRV_STK17TA8 is not set
+CONFIG_RTC_DRV_DS1742=y
+CONFIG_RTC_DRV_M48T86=y
+# CONFIG_RTC_DRV_M48T59 is not set
+CONFIG_RTC_DRV_V3020=y
+
+#
+# on-CPU RTC drivers
+#
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_NFS_DIRECTIO=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Profiling support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/yl9200_defconfig b/arch/arm/configs/yl9200_defconfig
new file mode 100644
index 000000000000..26de37f74686
--- /dev/null
+++ b/arch/arm/configs/yl9200_defconfig
@@ -0,0 +1,1216 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc6
+# Fri Jan 11 09:53:59 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CO285 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT91RM9200 Board Type
+#
+# CONFIG_MACH_ONEARM is not set
+CONFIG_ARCH_AT91RM9200DK=y
+# CONFIG_MACH_AT91RM9200EK is not set
+# CONFIG_MACH_CSB337 is not set
+# CONFIG_MACH_CSB637 is not set
+# CONFIG_MACH_CARMEVA is not set
+# CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
+CONFIG_MACH_YL9200=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
+
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
+# CONFIG_XIP_KERNEL is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x0000000
+CONFIG_MTD_PHYSMAP_LEN=0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+CONFIG_MTD_PLATRAM=y
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_AT91=y
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=3
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+CONFIG_DAVICOM_PHY=y
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_AT91_ETHER=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_CHARDEV is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+CONFIG_SPI=y
+CONFIG_SPI_DEBUG=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_S1D135XX=y
+# CONFIG_FB_VIRTUAL is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_LTV350QV is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_CORGI is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_PXA2XX is not set
+CONFIG_USB_GADGET_M66592=y
+CONFIG_USB_M66592=y
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+CONFIG_USB_FILE_STORAGE=y
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_AT91=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_GPIO=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AT91RM9200=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=y
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+# CONFIG_REISERFS_FS_XATTR is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_HFSPLUS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=1
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+CONFIG_INSTRUMENTATION=y
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+CONFIG_SLUB_DEBUG_ON=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_DEBUG_KOBJECT=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+CONFIG_DEBUG_LIST=y
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 00d44c6fbfe9..d5be3f7ac0e3 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_KEXEC)		+= machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_KPROBES)           += kprobes.o kprobes-decode.o
 obj-$(CONFIG_ATAGS_PROC)        += atags.o
 obj-$(CONFIG_OABI_COMPAT)       += sys_oabi-compat.o
+obj-$(CONFIG_ARM_THUMBEE)       += thumbee.o
 
 obj-$(CONFIG_CRUNCH)            += crunch.o crunch-bits.o
 AFLAGS_crunch-bits.o            := -Wa,-mcpu=ep9312
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 3278e713c32a..0a0d2479274b 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -58,6 +58,9 @@ int main(void)
   DEFINE(TI_TP_VALUE,           offsetof(struct thread_info, tp_value));
   DEFINE(TI_FPSTATE,            offsetof(struct thread_info, fpstate));
   DEFINE(TI_VFPSTATE,           offsetof(struct thread_info, vfpstate));
+#ifdef CONFIG_ARM_THUMBEE
+  DEFINE(TI_THUMBEE_STATE,      offsetof(struct thread_info, thumbee_state));
+#endif
 #ifdef CONFIG_IWMMXT
   DEFINE(TI_IWMMXT_STATE,       offsetof(struct thread_info, fpstate.iwmmxt));
 #endif
@@ -108,5 +111,12 @@ int main(void)
   DEFINE(PROCINFO_INITFUNC,     offsetof(struct proc_info_list, __cpu_flush));
   DEFINE(PROCINFO_MM_MMUFLAGS,  offsetof(struct proc_info_list, __cpu_mm_mmu_flags));
   DEFINE(PROCINFO_IO_MMUFLAGS,  offsetof(struct proc_info_list, __cpu_io_mmu_flags));
+  BLANK();
+#ifdef MULTI_DABORT
+  DEFINE(PROCESSOR_DABT_FUNC,   offsetof(struct processor, _data_abort));
+#endif
+#ifdef MULTI_PABORT
+  DEFINE(PROCESSOR_PABT_FUNC,   offsetof(struct processor, _prefetch_abort));
+#endif
   return 0; 
 }
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 283e14fff993..95f1c121cb30 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -359,9 +359,11 @@
                 CALL(sys_kexec_load)
                 CALL(sys_utimensat)
                 CALL(sys_signalfd)
-/* 350 */       CALL(sys_ni_syscall)
+/* 350 */       CALL(sys_timerfd_create)
                 CALL(sys_eventfd)
                 CALL(sys_fallocate)
+                CALL(sys_timerfd_settime)
+                CALL(sys_timerfd_gettime)
 #ifndef syscalls_counted
 .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
 #define syscalls_counted
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index a46d5b456765..7dca225752c1 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -166,12 +166,12 @@ __dabt_svc:
         @ The abort handler must return the aborted address in r0, and
         @ the fault status register in r1.  r9 must be preserved.
         @
-#ifdef MULTI_ABORT
+#ifdef MULTI_DABORT
         ldr     r4, .LCprocfns
         mov     lr, pc
-        ldr     pc, [r4]
+        ldr     pc, [r4, #PROCESSOR_DABT_FUNC]
 #else
-        bl      CPU_ABORT_HANDLER
+        bl      CPU_DABORT_HANDLER
 #endif
 
         @
@@ -209,14 +209,12 @@ __irq_svc:
 
         irq_handler
 #ifdef CONFIG_PREEMPT
+        str     r8, [tsk, #TI_PREEMPT]          @ restore preempt count
         ldr     r0, [tsk, #TI_FLAGS]            @ get flags
+        teq     r8, #0                          @ if preempt count != 0
+        movne   r0, #0                          @ force flags to 0
         tst     r0, #_TIF_NEED_RESCHED
         blne    svc_preempt
-preempt_return:
-        ldr     r0, [tsk, #TI_PREEMPT]          @ read preempt value
-        str     r8, [tsk, #TI_PREEMPT]          @ restore preempt count
-        teq     r0, r7
-        strne   r0, [r0, -r0]                   @ bug()
 #endif
         ldr     r0, [sp, #S_PSR]                @ irqs are already disabled
         msr     spsr_cxsf, r0
@@ -230,19 +228,11 @@ preempt_return:
 
 #ifdef CONFIG_PREEMPT
 svc_preempt:
-        teq     r8, #0                          @ was preempt count = 0
-        ldreq   r6, .LCirq_stat
-        movne   pc, lr                          @ no
-        ldr     r0, [r6, #4]                    @ local_irq_count
-        ldr     r1, [r6, #8]                    @ local_bh_count
-        adds    r0, r0, r1
-        movne   pc, lr
-        mov     r7, #0                          @ preempt_schedule_irq
-        str     r7, [tsk, #TI_PREEMPT]          @ expects preempt_count == 0
+        mov     r8, lr
 1:      bl      preempt_schedule_irq            @ irq en/disable is done inside
         ldr     r0, [tsk, #TI_FLAGS]            @ get new tasks TI_FLAGS
         tst     r0, #_TIF_NEED_RESCHED
-        beq     preempt_return                  @ go again
+        moveq   pc, r8                          @ go again
         b       1b
 #endif
 
@@ -293,7 +283,6 @@ __pabt_svc:
         mrs     r9, cpsr
         tst     r3, #PSR_I_BIT
         biceq   r9, r9, #PSR_I_BIT
-        msr     cpsr_c, r9
 
         @
         @ set args, then call main handler
@@ -301,7 +290,15 @@ __pabt_svc:
         @  r0 - address of faulting instruction
         @  r1 - pointer to registers on stack
         @
-        mov     r0, r2                          @ address (pc)
+#ifdef MULTI_PABORT
+        mov     r0, r2                  @ pass address of aborted instruction.
+        ldr     r4, .LCprocfns
+        mov     lr, pc
+        ldr     pc, [r4, #PROCESSOR_PABT_FUNC]
+#else
+        CPU_PABORT_HANDLER(r0, r2)
+#endif
+        msr     cpsr_c, r9                      @ Maybe enable interrupts
         mov     r1, sp                          @ regs
         bl      do_PrefetchAbort                @ call abort handler
 
@@ -320,16 +317,12 @@ __pabt_svc:
         .align  5
 .LCcralign:
         .word   cr_alignment
-#ifdef MULTI_ABORT
+#ifdef MULTI_DABORT
 .LCprocfns:
         .word   processor
 #endif
 .LCfp:
         .word   fp_enter
-#ifdef CONFIG_PREEMPT
-.LCirq_stat:
-        .word   irq_stat
-#endif
 
 /*
  * User mode handlers
@@ -404,12 +397,12 @@ __dabt_usr:
         @ The abort handler must return the aborted address in r0, and
         @ the fault status register in r1.
         @
-#ifdef MULTI_ABORT
+#ifdef MULTI_DABORT
         ldr     r4, .LCprocfns
         mov     lr, pc
-        ldr     pc, [r4]
+        ldr     pc, [r4, #PROCESSOR_DABT_FUNC]
 #else
-        bl      CPU_ABORT_HANDLER
+        bl      CPU_DABORT_HANDLER
 #endif
 
         @
@@ -455,10 +448,6 @@ __irq_usr:
 __und_usr:
         usr_entry
 
-        tst     r3, #PSR_T_BIT                  @ Thumb mode?
-        bne     __und_usr_unknown               @ ignore FP
-        sub     r4, r2, #4
-
         @
         @ fall through to the emulation code, which returns using r9 if
         @ it has emulated the instruction, or the more conventional lr
@@ -468,7 +457,24 @@ __und_usr:
         @
         adr     r9, ret_from_exception
         adr     lr, __und_usr_unknown
-1:      ldrt    r0, [r4]
+        tst     r3, #PSR_T_BIT                  @ Thumb mode?
+        subeq   r4, r2, #4                      @ ARM instr at LR - 4
+        subne   r4, r2, #2                      @ Thumb instr at LR - 2
+1:      ldreqt  r0, [r4]
+        beq     call_fpe
+        @ Thumb instruction
+#if __LINUX_ARM_ARCH__ >= 7
+2:      ldrht   r5, [r4], #2
+        and     r0, r5, #0xf800                 @ mask bits 111x x... .... ....
+        cmp     r0, #0xe800                     @ 32bit instruction if xx != 0
+        blo     __und_usr_unknown
+3:      ldrht   r0, [r4]
+        add     r2, r2, #2                      @ r2 is PC + 2, make it PC + 4
+        orr     r0, r0, r5, lsl #16
+#else
+        b       __und_usr_unknown
+#endif
+
         @
         @ fallthrough to call_fpe
         @
@@ -477,10 +483,14 @@ __und_usr:
  * The out of line fixup for the ldrt above.
  */
         .section .fixup, "ax"
-2:      mov     pc, r9
+4:      mov     pc, r9
         .previous
         .section __ex_table,"a"
-        .long   1b, 2b
+        .long   1b, 4b
+#if __LINUX_ARM_ARCH__ >= 7
+        .long   2b, 4b
+        .long   3b, 4b
+#endif
         .previous
 
 /*
@@ -507,9 +517,16 @@ __und_usr:
  *  r10 = this threads thread_info structure.
  *  lr  = unrecognised instruction return address
  */
+        @
+        @ Fall-through from Thumb-2 __und_usr
+        @
+#ifdef CONFIG_NEON
+        adr     r6, .LCneon_thumb_opcodes
+        b       2f
+#endif
 call_fpe:
 #ifdef CONFIG_NEON
-        adr     r6, .LCneon_opcodes
+        adr     r6, .LCneon_arm_opcodes
 2:
         ldr     r7, [r6], #4                    @ mask value
         cmp     r7, #0                          @ end mask?
@@ -526,6 +543,7 @@ call_fpe:
 1:
 #endif
         tst     r0, #0x08000000                 @ only CDP/CPRT/LDC/STC have bit 27
+        tstne   r0, #0x04000000                 @ bit 26 set on both ARM and Thumb-2
 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
         and     r8, r0, #0x0f000000             @ mask out op-code bits
         teqne   r8, #0x0f000000                 @ SWI (ARM6/7 bug)?
@@ -577,7 +595,7 @@ call_fpe:
 #ifdef CONFIG_NEON
         .align  6
 
-.LCneon_opcodes:
+.LCneon_arm_opcodes:
         .word   0xfe000000                      @ mask
         .word   0xf2000000                      @ opcode
 
@@ -586,6 +604,16 @@ call_fpe:
 
         .word   0x00000000                      @ mask
         .word   0x00000000                      @ opcode
+
+.LCneon_thumb_opcodes:
+        .word   0xef000000                      @ mask
+        .word   0xef000000                      @ opcode
+
+        .word   0xff100000                      @ mask
+        .word   0xf9000000                      @ opcode
+
+        .word   0x00000000                      @ mask
+        .word   0x00000000                      @ opcode
 #endif
 
 do_fpe:
@@ -619,8 +647,15 @@ __und_usr_unknown:
 __pabt_usr:
         usr_entry
 
+#ifdef MULTI_PABORT
+        mov     r0, r2                  @ pass address of aborted instruction.
+        ldr     r4, .LCprocfns
+        mov     lr, pc
+        ldr     pc, [r4, #PROCESSOR_PABT_FUNC]
+#else
+        CPU_PABORT_HANDLER(r0, r2)
+#endif
         enable_irq                              @ Enable interrupts
-        mov     r0, r2                          @ address (pc)
         mov     r1, sp                          @ regs
         bl      do_PrefetchAbort                @ call abort handler
         /* fall through */
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 6c90c50a9ee3..597ed00a08d8 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -352,6 +352,11 @@ sys_mmap2:
                 b       do_mmap2
 #endif
 
+ENTRY(pabort_ifar)
+                mrc     p15, 0, r0, cr6, cr0, 2
+ENTRY(pabort_noifar)
+                mov     pc, lr
+
 #ifdef CONFIG_OABI_COMPAT
 
 /*
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 50f667febe29..7e9c00a8a412 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -75,8 +75,13 @@ __error_p:
 #ifdef CONFIG_DEBUG_LL
         adr     r0, str_p1
         bl      printascii
+        mov     r0, r9
+        bl      printhex8
+        adr     r0, str_p2
+        bl      printascii
         b       __error
-str_p1: .asciz  "\nError: unrecognized/unsupported processor variant.\n"
+str_p1: .asciz  "\nError: unrecognized/unsupported processor variant (0x"
+str_p2: .asciz  ").\n"
         .align
 #endif
 
diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c
new file mode 100644
index 000000000000..df3f6b7ebcea
--- /dev/null
+++ b/arch/arm/kernel/thumbee.c
@@ -0,0 +1,81 @@
+/*
+ * arch/arm/kernel/thumbee.c
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/thread_notify.h>
+
+/*
+ * Access to the ThumbEE Handler Base register
+ */
+static inline unsigned long teehbr_read()
+{
+        unsigned long v;
+        asm("mrc        p14, 6, %0, c1, c0, 0\n" : "=r" (v));
+        return v;
+}
+
+static inline void teehbr_write(unsigned long v)
+{
+        asm("mcr        p14, 6, %0, c1, c0, 0\n" : : "r" (v));
+}
+
+static int thumbee_notifier(struct notifier_block *self, unsigned long cmd, void *t)
+{
+        struct thread_info *thread = t;
+
+        switch (cmd) {
+        case THREAD_NOTIFY_FLUSH:
+                thread->thumbee_state = 0;
+                break;
+        case THREAD_NOTIFY_SWITCH:
+                current_thread_info()->thumbee_state = teehbr_read();
+                teehbr_write(thread->thumbee_state);
+                break;
+        }
+
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block thumbee_notifier_block = {
+        .notifier_call  = thumbee_notifier,
+};
+
+static int __init thumbee_init(void)
+{
+        unsigned long pfr0;
+        unsigned int cpu_arch = cpu_architecture();
+
+        if (cpu_arch < CPU_ARCH_ARMv7)
+                return 0;
+
+        /* processor feature register 0 */
+        asm("mrc        p15, 0, %0, c0, c1, 0\n" : "=r" (pfr0));
+        if ((pfr0 & 0x0000f000) != 0x00001000)
+                return 0;
+
+        printk(KERN_INFO "ThumbEE CPU extension supported.\n");
+        elf_hwcap |= HWCAP_THUMBEE;
+        thread_register_notifier(&thumbee_notifier_block);
+
+        return 0;
+}
+
+late_initcall(thumbee_init);
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 074dcd5d9a7e..0fc07b6db749 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -12,18 +12,28 @@ config ARCH_AT91RM9200
 
 config ARCH_AT91SAM9260
         bool "AT91SAM9260 or AT91SAM9XE"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 
 config ARCH_AT91SAM9261
         bool "AT91SAM9261"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 
 config ARCH_AT91SAM9263
         bool "AT91SAM9263"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 
 config ARCH_AT91SAM9RL
         bool "AT91SAM9RL"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 
 config ARCH_AT91CAP9
         bool "AT91CAP9"
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 
 config ARCH_AT91X40
         bool "AT91x40"
@@ -109,6 +119,13 @@ config MACH_KAFA
         help
           Select this if you are using Sperry-Sun's KAFA board.
 
+config MACH_ECBAT91
+        bool "emQbit ECB_AT91 SBC"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using emQbit's ECB_AT91 board.
+          <http://wiki.emqbit.com/free-ecb-at91>
+
 endif
 
 # ----------------------------------------------------------
@@ -133,6 +150,20 @@ config MACH_AT91SAM9260EK
           Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
           <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
 
+config MACH_CAM60
+        bool "KwikByte KB9260 (CAM60) board"
+        depends on ARCH_AT91SAM9260
+        help
+          Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
+          <http://www.kwikbyte.com/KB9260.html>
+
+config MACH_SAM9_L9260
+        bool "Olimex SAM9-L9260 board"
+        depends on ARCH_AT91SAM9260
+        help
+          Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
+          <http://www.olimex.com/dev/sam9-L9260.html>
+
 endif
 
 # ----------------------------------------------------------
@@ -216,7 +247,7 @@ comment "AT91 Board Options"
 
 config MTD_AT91_DATAFLASH_CARD
         bool "Enable DataFlash Card support"
-        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK)
+        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK || MACH_SAM9_L9260 || MACH_ECBAT91)
         help
           Enable support for the DataFlash card.
 
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index bf5f293dccf8..8d9bc0153b18 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -29,9 +29,12 @@ obj-$(CONFIG_MACH_KB9200)	+= board-kb9202.o
 obj-$(CONFIG_MACH_ATEB9200)     += board-eb9200.o
 obj-$(CONFIG_MACH_KAFA)         += board-kafa.o
 obj-$(CONFIG_MACH_PICOTUX2XX)   += board-picotux200.o
+obj-$(CONFIG_MACH_ECBAT91)      += board-ecbat91.o
 
 # AT91SAM9260 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
+obj-$(CONFIG_MACH_CAM60)        += board-cam60.o
+obj-$(CONFIG_MACH_SAM9_L9260)   += board-sam9-l9260.o
 
 # AT91SAM9261 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index 48d27d8000b0..933fa8f55cbc 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -13,12 +13,14 @@
  */
 
 #include <linux/module.h>
+#include <linux/pm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/arch/at91cap9.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -288,6 +290,12 @@ static void at91cap9_reset(void)
         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
+static void at91cap9_poweroff(void)
+{
+        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
+
 /* --------------------------------------------------------------------
  *  AT91CAP9 processor initialization
  * -------------------------------------------------------------------- */
@@ -298,6 +306,7 @@ void __init at91cap9_initialize(unsigned long main_clock)
         iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
 
         at91_arch_reset = at91cap9_reset;
+        pm_power_off = at91cap9_poweroff;
         at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
 
         /* Init clock subsystem */
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index c50fad9cd143..f1a80d74a4b6 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -16,15 +16,15 @@
 
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
+#include <linux/i2c-gpio.h>
 
 #include <video/atmel_lcdc.h>
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91cap9.h>
-#include <asm/arch/at91sam926x_mc.h>
 #include <asm/arch/at91cap9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
@@ -283,10 +283,15 @@ static struct at91_nand_data nand_data;
 #define NAND_BASE       AT91_CHIPSELECT_3
 
 static struct resource nand_resources[] = {
-        {
+        [0] = {
                 .start  = NAND_BASE,
                 .end    = NAND_BASE + SZ_256M - 1,
                 .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_BASE_SYS + AT91_ECC,
+                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -344,6 +349,7 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
 void __init at91_add_device_nand(struct at91_nand_data *data) {}
 #endif
 
+
 /* --------------------------------------------------------------------
  *  TWI (i2c)
  * -------------------------------------------------------------------- */
@@ -532,13 +538,59 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 
 
 /* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+        [0] = {
+                .start  = AT91CAP9_BASE_TCB0,
+                .end    = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91CAP9_ID_TCB,
+                .end    = AT91CAP9_ID_TCB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91cap9_tcb_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb_resources,
+        .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has one clock and irq for all three TC channels */
+        at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk");
+        platform_device_register(&at91cap9_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTT
  * -------------------------------------------------------------------- */
 
+static struct resource rtt_resources[] = {
+        {
+                .start  = AT91_BASE_SYS + AT91_RTT,
+                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
 static struct platform_device at91cap9_rtt_device = {
         .name           = "at91_rtt",
-        .id             = -1,
-        .num_resources  = 0,
+        .id             = 0,
+        .resource       = rtt_resources,
+        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
 
 static void __init at91_add_device_rtt(void)
@@ -990,7 +1042,7 @@ static inline void configure_usart2_pins(unsigned pins)
                 at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
 }
 
-static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
@@ -1031,8 +1083,6 @@ void __init at91_set_serial_console(unsigned portnr)
 {
         if (portnr < ATMEL_MAX_UART)
                 atmel_default_console_device = at91_uarts[portnr];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 
 void __init at91_add_device_serial(void)
@@ -1043,6 +1093,9 @@ void __init at91_add_device_serial(void)
                 if (at91_uarts[i])
                         platform_device_register(at91_uarts[i]);
         }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
@@ -1060,6 +1113,7 @@ static int __init at91_add_standard_devices(void)
 {
         at91_add_device_rtt();
         at91_add_device_watchdog();
+        at91_add_device_tc();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index ef6aeb86e980..de19bee83f75 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -577,6 +577,90 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 
 
 /* --------------------------------------------------------------------
+ *  Timer/Counter blocks
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb0_resources[] = {
+        [0] = {
+                .start  = AT91RM9200_BASE_TCB0,
+                .end    = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91RM9200_ID_TC0,
+                .end    = AT91RM9200_ID_TC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT91RM9200_ID_TC1,
+                .end    = AT91RM9200_ID_TC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT91RM9200_ID_TC2,
+                .end    = AT91RM9200_ID_TC2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91rm9200_tcb0_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb0_resources,
+        .num_resources  = ARRAY_SIZE(tcb0_resources),
+};
+
+static struct resource tcb1_resources[] = {
+        [0] = {
+                .start  = AT91RM9200_BASE_TCB1,
+                .end    = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91RM9200_ID_TC3,
+                .end    = AT91RM9200_ID_TC3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT91RM9200_ID_TC4,
+                .end    = AT91RM9200_ID_TC4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT91RM9200_ID_TC5,
+                .end    = AT91RM9200_ID_TC5,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91rm9200_tcb1_device = {
+        .name           = "atmel_tcb",
+        .id             = 1,
+        .resource       = tcb1_resources,
+        .num_resources  = ARRAY_SIZE(tcb1_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has a separate clock and irq for each TC channel */
+        at91_clock_associate("tc0_clk", &at91rm9200_tcb0_device.dev, "t0_clk");
+        at91_clock_associate("tc1_clk", &at91rm9200_tcb0_device.dev, "t1_clk");
+        at91_clock_associate("tc2_clk", &at91rm9200_tcb0_device.dev, "t2_clk");
+        platform_device_register(&at91rm9200_tcb0_device);
+
+        at91_clock_associate("tc3_clk", &at91rm9200_tcb1_device.dev, "t0_clk");
+        at91_clock_associate("tc4_clk", &at91rm9200_tcb1_device.dev, "t1_clk");
+        at91_clock_associate("tc5_clk", &at91rm9200_tcb1_device.dev, "t2_clk");
+        platform_device_register(&at91rm9200_tcb1_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTC
  * -------------------------------------------------------------------- */
 
@@ -1019,7 +1103,7 @@ static inline void configure_usart3_pins(unsigned pins)
                 at91_set_B_periph(AT91_PIN_PB0, 0);     /* RTS3 */
 }
 
-static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
 
 void __init __deprecated at91_init_serial(struct at91_uart_config *config)
@@ -1110,8 +1194,6 @@ void __init at91_set_serial_console(unsigned portnr)
 {
         if (portnr < ATMEL_MAX_UART)
                 atmel_default_console_device = at91_uarts[portnr];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 
 void __init at91_add_device_serial(void)
@@ -1122,6 +1204,9 @@ void __init at91_add_device_serial(void)
                 if (at91_uarts[i])
                         platform_device_register(at91_uarts[i]);
         }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
 void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
@@ -1141,6 +1226,7 @@ static int __init at91_add_standard_devices(void)
 {
         at91_add_device_rtc();
         at91_add_device_watchdog();
+        at91_add_device_tc();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 18d06612ce8a..ee26550cdc21 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/pm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -18,6 +19,7 @@
 #include <asm/arch/at91sam9260.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -267,6 +269,11 @@ static void at91sam9260_reset(void)
         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
+static void at91sam9260_poweroff(void)
+{
+        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
 
 /* --------------------------------------------------------------------
  *  AT91SAM9260 processor initialization
@@ -304,6 +311,7 @@ void __init at91sam9260_initialize(unsigned long main_clock)
                 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
 
         at91_arch_reset = at91sam9260_reset;
+        pm_power_off = at91sam9260_poweroff;
         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
                         | (1 << AT91SAM9260_ID_IRQ2);
 
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 105f8403860b..393a32aefce5 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -19,8 +19,8 @@
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91sam926x_mc.h>
 #include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
@@ -288,10 +288,15 @@ static struct at91_nand_data nand_data;
 #define NAND_BASE       AT91_CHIPSELECT_3
 
 static struct resource nand_resources[] = {
-        {
+        [0] = {
                 .start  = NAND_BASE,
                 .end    = NAND_BASE + SZ_256M - 1,
                 .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_BASE_SYS + AT91_ECC,
+                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -540,6 +545,90 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 
 
 /* --------------------------------------------------------------------
+ *  Timer/Counter blocks
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_TCB0,
+                .end    = AT91SAM9260_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_TC0,
+                .end    = AT91SAM9260_ID_TC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT91SAM9260_ID_TC1,
+                .end    = AT91SAM9260_ID_TC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT91SAM9260_ID_TC2,
+                .end    = AT91SAM9260_ID_TC2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9260_tcb0_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb0_resources,
+        .num_resources  = ARRAY_SIZE(tcb0_resources),
+};
+
+static struct resource tcb1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_TCB1,
+                .end    = AT91SAM9260_BASE_TCB1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_TC3,
+                .end    = AT91SAM9260_ID_TC3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT91SAM9260_ID_TC4,
+                .end    = AT91SAM9260_ID_TC4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT91SAM9260_ID_TC5,
+                .end    = AT91SAM9260_ID_TC5,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9260_tcb1_device = {
+        .name           = "atmel_tcb",
+        .id             = 1,
+        .resource       = tcb1_resources,
+        .num_resources  = ARRAY_SIZE(tcb1_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has a separate clock and irq for each TC channel */
+        at91_clock_associate("tc0_clk", &at91sam9260_tcb0_device.dev, "t0_clk");
+        at91_clock_associate("tc1_clk", &at91sam9260_tcb0_device.dev, "t1_clk");
+        at91_clock_associate("tc2_clk", &at91sam9260_tcb0_device.dev, "t2_clk");
+        platform_device_register(&at91sam9260_tcb0_device);
+
+        at91_clock_associate("tc3_clk", &at91sam9260_tcb1_device.dev, "t0_clk");
+        at91_clock_associate("tc4_clk", &at91sam9260_tcb1_device.dev, "t1_clk");
+        at91_clock_associate("tc5_clk", &at91sam9260_tcb1_device.dev, "t2_clk");
+        platform_device_register(&at91sam9260_tcb1_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTT
  * -------------------------------------------------------------------- */
 
@@ -553,7 +642,7 @@ static struct resource rtt_resources[] = {
 
 static struct platform_device at91sam9260_rtt_device = {
         .name           = "at91_rtt",
-        .id             = -1,
+        .id             = 0,
         .resource       = rtt_resources,
         .num_resources  = ARRAY_SIZE(rtt_resources),
 };
@@ -962,64 +1051,9 @@ static inline void configure_usart5_pins(void)
         at91_set_A_periph(AT91_PIN_PB13, 0);            /* RXD5 */
 }
 
-static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
 
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
-        int i;
-
-        /* Fill in list of supported UARTs */
-        for (i = 0; i < config->nr_tty; i++) {
-                switch (config->tty_map[i]) {
-                        case 0:
-                                configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DSR | ATMEL_UART_DTR | ATMEL_UART_DCD | ATMEL_UART_RI);
-                                at91_uarts[i] = &at91sam9260_uart0_device;
-                                at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart");
-                                break;
-                        case 1:
-                                configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91sam9260_uart1_device;
-                                at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart");
-                                break;
-                        case 2:
-                                configure_usart2_pins(0);
-                                at91_uarts[i] = &at91sam9260_uart2_device;
-                                at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart");
-                                break;
-                        case 3:
-                                configure_usart3_pins(0);
-                                at91_uarts[i] = &at91sam9260_uart3_device;
-                                at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart");
-                                break;
-                        case 4:
-                                configure_usart4_pins();
-                                at91_uarts[i] = &at91sam9260_uart4_device;
-                                at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart");
-                                break;
-                        case 5:
-                                configure_usart5_pins();
-                                at91_uarts[i] = &at91sam9260_uart5_device;
-                                at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart");
-                                break;
-                        case 6:
-                                configure_dbgu_pins();
-                                at91_uarts[i] = &at91sam9260_dbgu_device;
-                                at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart");
-                                break;
-                        default:
-                                continue;
-                }
-                at91_uarts[i]->id = i;          /* update ID number to mapped ID */
-        }
-
-        /* Set serial console device */
-        if (config->console_tty < ATMEL_MAX_UART)
-                atmel_default_console_device = at91_uarts[config->console_tty];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
@@ -1073,8 +1107,6 @@ void __init at91_set_serial_console(unsigned portnr)
 {
         if (portnr < ATMEL_MAX_UART)
                 atmel_default_console_device = at91_uarts[portnr];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 
 void __init at91_add_device_serial(void)
@@ -1085,9 +1117,11 @@ void __init at91_add_device_serial(void)
                 if (at91_uarts[i])
                         platform_device_register(at91_uarts[i]);
         }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
-void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
 void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
@@ -1103,6 +1137,7 @@ static int __init at91_add_standard_devices(void)
 {
         at91_add_device_rtt();
         at91_add_device_watchdog();
+        at91_add_device_tc();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 90b87e1877d9..35bf6fd52516 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,12 +11,14 @@
  */
 
 #include <linux/module.h>
+#include <linux/pm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/arch/at91sam9261.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -245,6 +247,11 @@ static void at91sam9261_reset(void)
         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
+static void at91sam9261_poweroff(void)
+{
+        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
 
 /* --------------------------------------------------------------------
  *  AT91SAM9261 processor initialization
@@ -256,6 +263,7 @@ void __init at91sam9261_initialize(unsigned long main_clock)
         iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
 
         at91_arch_reset = at91sam9261_reset;
+        pm_power_off = at91sam9261_poweroff;
         at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
                         | (1 << AT91SAM9261_ID_IRQ2);
 
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 245641263fce..37cd547855b1 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -24,7 +24,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91sam9261.h>
 #include <asm/arch/at91sam9261_matrix.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
@@ -548,6 +548,55 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 
 
 /* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+        [0] = {
+                .start  = AT91SAM9261_BASE_TCB0,
+                .end    = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9261_ID_TC0,
+                .end    = AT91SAM9261_ID_TC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT91SAM9261_ID_TC1,
+                .end    = AT91SAM9261_ID_TC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT91SAM9261_ID_TC2,
+                .end    = AT91SAM9261_ID_TC2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9261_tcb_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb_resources,
+        .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has a separate clock and irq for each TC channel */
+        at91_clock_associate("tc0_clk", &at91sam9261_tcb_device.dev, "t0_clk");
+        at91_clock_associate("tc1_clk", &at91sam9261_tcb_device.dev, "t1_clk");
+        at91_clock_associate("tc2_clk", &at91sam9261_tcb_device.dev, "t2_clk");
+        platform_device_register(&at91sam9261_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTT
  * -------------------------------------------------------------------- */
 
@@ -561,7 +610,7 @@ static struct resource rtt_resources[] = {
 
 static struct platform_device at91sam9261_rtt_device = {
         .name           = "at91_rtt",
-        .id             = -1,
+        .id             = 0,
         .resource       = rtt_resources,
         .num_resources  = ARRAY_SIZE(rtt_resources),
 };
@@ -938,49 +987,9 @@ static inline void configure_usart2_pins(unsigned pins)
                 at91_set_B_periph(AT91_PIN_PA16, 0);    /* CTS2 */
 }
 
-static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
 
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
-        int i;
-
-        /* Fill in list of supported UARTs */
-        for (i = 0; i < config->nr_tty; i++) {
-                switch (config->tty_map[i]) {
-                        case 0:
-                                configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91sam9261_uart0_device;
-                                at91_clock_associate("usart0_clk", &at91sam9261_uart0_device.dev, "usart");
-                                break;
-                        case 1:
-                                configure_usart1_pins(0);
-                                at91_uarts[i] = &at91sam9261_uart1_device;
-                                at91_clock_associate("usart1_clk", &at91sam9261_uart1_device.dev, "usart");
-                                break;
-                        case 2:
-                                configure_usart2_pins(0);
-                                at91_uarts[i] = &at91sam9261_uart2_device;
-                                at91_clock_associate("usart2_clk", &at91sam9261_uart2_device.dev, "usart");
-                                break;
-                        case 3:
-                                configure_dbgu_pins();
-                                at91_uarts[i] = &at91sam9261_dbgu_device;
-                                at91_clock_associate("mck", &at91sam9261_dbgu_device.dev, "usart");
-                                break;
-                        default:
-                                continue;
-                }
-                at91_uarts[i]->id = i;          /* update ID number to mapped ID */
-        }
-
-        /* Set serial console device */
-        if (config->console_tty < ATMEL_MAX_UART)
-                atmel_default_console_device = at91_uarts[config->console_tty];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
@@ -1019,8 +1028,6 @@ void __init at91_set_serial_console(unsigned portnr)
 {
         if (portnr < ATMEL_MAX_UART)
                 atmel_default_console_device = at91_uarts[portnr];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 
 void __init at91_add_device_serial(void)
@@ -1031,9 +1038,11 @@ void __init at91_add_device_serial(void)
                 if (at91_uarts[i])
                         platform_device_register(at91_uarts[i]);
         }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
-void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
 void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
@@ -1050,6 +1059,7 @@ static int __init at91_add_standard_devices(void)
 {
         at91_add_device_rtt();
         at91_add_device_watchdog();
+        at91_add_device_tc();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index a53ba0f74351..052074a9f2d3 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,12 +11,14 @@
  */
 
 #include <linux/module.h>
+#include <linux/pm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/arch/at91sam9263.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -271,6 +273,11 @@ static void at91sam9263_reset(void)
         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
+static void at91sam9263_poweroff(void)
+{
+        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
 
 /* --------------------------------------------------------------------
  *  AT91SAM9263 processor initialization
@@ -282,6 +289,7 @@ void __init at91sam9263_initialize(unsigned long main_clock)
         iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
 
         at91_arch_reset = at91sam9263_reset;
+        pm_power_off = at91sam9263_poweroff;
         at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
 
         /* Init clock subsystem */
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 0b12e1adcc8e..b6454c525962 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -22,8 +22,8 @@
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91sam9263.h>
-#include <asm/arch/at91sam926x_mc.h>
 #include <asm/arch/at91sam9263_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
@@ -358,10 +358,15 @@ static struct at91_nand_data nand_data;
 #define NAND_BASE       AT91_CHIPSELECT_3
 
 static struct resource nand_resources[] = {
-        {
+        [0] = {
                 .start  = NAND_BASE,
                 .end    = NAND_BASE + SZ_256M - 1,
                 .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_BASE_SYS + AT91_ECC0,
+                .end    = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -783,6 +788,43 @@ void __init at91_add_device_isi(void) {}
 
 
 /* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+        [0] = {
+                .start  = AT91SAM9263_BASE_TCB0,
+                .end    = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9263_ID_TCB,
+                .end    = AT91SAM9263_ID_TCB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9263_tcb_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb_resources,
+        .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has one clock and irq for all three TC channels */
+        at91_clock_associate("tcb_clk", &at91sam9263_tcb_device.dev, "t0_clk");
+        platform_device_register(&at91sam9263_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTT
  * -------------------------------------------------------------------- */
 
@@ -933,9 +975,6 @@ static inline void configure_ssc1_pins(unsigned pins)
 }
 
 /*
- * Return the device node so that board init code can use it as the
- * parent for the device node reflecting how it's used on this board.
- *
  * SSC controllers are accessed through library code, instead of any
  * kind of all-singing/all-dancing driver.  For example one could be
  * used by a particular I2S audio codec's driver, while another one
@@ -1146,49 +1185,9 @@ static inline void configure_usart2_pins(unsigned pins)
                 at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
 }
 
-static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
 
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
-        int i;
-
-        /* Fill in list of supported UARTs */
-        for (i = 0; i < config->nr_tty; i++) {
-                switch (config->tty_map[i]) {
-                        case 0:
-                                configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91sam9263_uart0_device;
-                                at91_clock_associate("usart0_clk", &at91sam9263_uart0_device.dev, "usart");
-                                break;
-                        case 1:
-                                configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91sam9263_uart1_device;
-                                at91_clock_associate("usart1_clk", &at91sam9263_uart1_device.dev, "usart");
-                                break;
-                        case 2:
-                                configure_usart2_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91sam9263_uart2_device;
-                                at91_clock_associate("usart2_clk", &at91sam9263_uart2_device.dev, "usart");
-                                break;
-                        case 3:
-                                configure_dbgu_pins();
-                                at91_uarts[i] = &at91sam9263_dbgu_device;
-                                at91_clock_associate("mck", &at91sam9263_dbgu_device.dev, "usart");
-                                break;
-                        default:
-                                continue;
-                }
-                at91_uarts[i]->id = i;          /* update ID number to mapped ID */
-        }
-
-        /* Set serial console device */
-        if (config->console_tty < ATMEL_MAX_UART)
-                atmel_default_console_device = at91_uarts[config->console_tty];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
@@ -1227,8 +1226,6 @@ void __init at91_set_serial_console(unsigned portnr)
 {
         if (portnr < ATMEL_MAX_UART)
                 atmel_default_console_device = at91_uarts[portnr];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 
 void __init at91_add_device_serial(void)
@@ -1239,9 +1236,11 @@ void __init at91_add_device_serial(void)
                 if (at91_uarts[i])
                         platform_device_register(at91_uarts[i]);
         }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
-void __init at91_init_serial(struct at91_uart_config *config) {}
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
 void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
@@ -1257,6 +1256,7 @@ static int __init at91_add_standard_devices(void)
 {
         at91_add_device_rtt();
         at91_add_device_watchdog();
+        at91_add_device_tc();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index e38d23770992..5cecbd7de6a6 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -1,23 +1,20 @@
 /*
- * linux/arch/arm/mach-at91/at91sam926x_time.c
+ * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
  *
  * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
  * Revision      2005 M. Nicolas Diremdjian, ATMEL Rousset, France
+ * Converted to ClockSource/ClockEvents by David Brownell.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-
-#include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/time.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
 
-#include <asm/hardware.h>
-#include <asm/io.h>
 #include <asm/mach/time.h>
 
 #include <asm/arch/at91_pit.h>
@@ -26,85 +23,167 @@
 #define PIT_CPIV(x)     ((x) & AT91_PIT_CPIV)
 #define PIT_PICNT(x)    (((x) & AT91_PIT_PICNT) >> 20)
 
+static u32 pit_cycle;           /* write-once */
+static u32 pit_cnt;             /* access only w/system irq blocked */
+
+
 /*
- * Returns number of microseconds since last timer interrupt.  Note that interrupts
- * will have been disabled by do_gettimeofday()
- *  'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
+ * Clocksource:  just a monotonic counter of MCK/16 cycles.
+ * We don't care whether or not PIT irqs are enabled.
  */
-static unsigned long at91sam926x_gettimeoffset(void)
+static cycle_t read_pit_clk(void)
 {
-        unsigned long elapsed;
-        unsigned long t = at91_sys_read(AT91_PIT_PIIR);
+        unsigned long flags;
+        u32 elapsed;
+        u32 t;
+
+        raw_local_irq_save(flags);
+        elapsed = pit_cnt;
+        t = at91_sys_read(AT91_PIT_PIIR);
+        raw_local_irq_restore(flags);
+
+        elapsed += PIT_PICNT(t) * pit_cycle;
+        elapsed += PIT_CPIV(t);
+        return elapsed;
+}
+
+static struct clocksource pit_clk = {
+        .name           = "pit",
+        .rating         = 175,
+        .read           = read_pit_clk,
+        .shift          = 20,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
 
-        elapsed = (PIT_PICNT(t) * LATCH) + PIT_CPIV(t);         /* hardware clock cycles */
 
-        return (unsigned long)(elapsed * jiffies_to_usecs(1)) / LATCH;
+/*
+ * Clockevent device:  interrupts every 1/HZ (== pit_cycles * MCK/16)
+ */
+static void
+pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
+{
+        unsigned long   flags;
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                /* update clocksource counter, then enable the IRQ */
+                raw_local_irq_save(flags);
+                pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+                at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
+                                | AT91_PIT_PITIEN);
+                raw_local_irq_restore(flags);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                BUG();
+                /* FALLTHROUGH */
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+                /* disable irq, leaving the clocksource active */
+                at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
 }
 
+static struct clock_event_device pit_clkevt = {
+        .name           = "pit",
+        .features       = CLOCK_EVT_FEAT_PERIODIC,
+        .shift          = 32,
+        .rating         = 100,
+        .cpumask        = CPU_MASK_CPU0,
+        .set_mode       = pit_clkevt_mode,
+};
+
+
 /*
  * IRQ handler for the timer.
  */
-static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
+static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 {
-        volatile long nr_ticks;
 
-        if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) {       /* This is a shared interrupt */
-                /* Get number to ticks performed before interrupt and clear PIT interrupt */
+        /* The PIT interrupt may be disabled, and is shared */
+        if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
+                        && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
+                unsigned nr_ticks;
+
+                /* Get number of ticks performed before irq, and ack it */
                 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
                 do {
-                        timer_tick();
+                        pit_cnt += pit_cycle;
+                        pit_clkevt.event_handler(&pit_clkevt);
                         nr_ticks--;
                 } while (nr_ticks);
 
                 return IRQ_HANDLED;
-        } else
-                return IRQ_NONE;                /* not handled */
+        }
+
+        return IRQ_NONE;
 }
 
-static struct irqaction at91sam926x_timer_irq = {
+static struct irqaction at91sam926x_pit_irq = {
         .name           = "at91_tick",
         .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = at91sam926x_timer_interrupt
+        .handler        = at91sam926x_pit_interrupt
 };
 
-void at91sam926x_timer_reset(void)
+static void at91sam926x_pit_reset(void)
 {
-        /* Disable timer */
+        /* Disable timer and irqs */
         at91_sys_write(AT91_PIT_MR, 0);
 
-        /* Clear any pending interrupts */
-        (void) at91_sys_read(AT91_PIT_PIVR);
+        /* Clear any pending interrupts, wait for PIT to stop counting */
+        while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
+                cpu_relax();
 
-        /* Set Period Interval timer and enable its interrupt */
-        at91_sys_write(AT91_PIT_MR, (LATCH & AT91_PIT_PIV) | AT91_PIT_PITIEN | AT91_PIT_PITEN);
+        /* Start PIT but don't enable IRQ */
+        at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
 
 /*
- * Set up timer interrupt.
+ * Set up both clocksource and clockevent support.
  */
-void __init at91sam926x_timer_init(void)
+static void __init at91sam926x_pit_init(void)
 {
-        /* Initialize and enable the timer */
-        at91sam926x_timer_reset();
+        unsigned long   pit_rate;
+        unsigned        bits;
+
+        /*
+         * Use our actual MCK to figure out how many MCK/16 ticks per
+         * 1/HZ period (instead of a compile-time constant LATCH).
+         */
+        pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
+        pit_cycle = (pit_rate + HZ/2) / HZ;
+        WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
 
-        /* Make IRQs happen for the system timer. */
-        setup_irq(AT91_ID_SYS, &at91sam926x_timer_irq);
+        /* Initialize and enable the timer */
+        at91sam926x_pit_reset();
+
+        /*
+         * Register clocksource.  The high order bits of PIV are unused,
+         * so this isn't a 32-bit counter unless we get clockevent irqs.
+         */
+        pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
+        bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
+        pit_clk.mask = CLOCKSOURCE_MASK(bits);
+        clocksource_register(&pit_clk);
+
+        /* Set up irq handler */
+        setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+
+        /* Set up and register clockevents */
+        pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
+        clockevents_register_device(&pit_clkevt);
 }
 
-#ifdef CONFIG_PM
-static void at91sam926x_timer_suspend(void)
+static void at91sam926x_pit_suspend(void)
 {
         /* Disable timer */
         at91_sys_write(AT91_PIT_MR, 0);
 }
-#else
-#define at91sam926x_timer_suspend       NULL
-#endif
 
 struct sys_timer at91sam926x_timer = {
-        .init           = at91sam926x_timer_init,
-        .offset         = at91sam926x_gettimeoffset,
-        .suspend        = at91sam926x_timer_suspend,
-        .resume         = at91sam926x_timer_reset,
+        .init           = at91sam926x_pit_init,
+        .suspend        = at91sam926x_pit_suspend,
+        .resume         = at91sam926x_pit_reset,
 };
-
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 4813a35f6cf5..902c79893ec7 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/module.h>
+#include <linux/pm.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -17,6 +18,7 @@
 #include <asm/arch/at91sam9rl.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -244,6 +246,11 @@ static void at91sam9rl_reset(void)
         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
+static void at91sam9rl_poweroff(void)
+{
+        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
 
 /* --------------------------------------------------------------------
  *  AT91SAM9RL processor initialization
@@ -274,6 +281,7 @@ void __init at91sam9rl_initialize(unsigned long main_clock)
         iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
 
         at91_arch_reset = at91sam9rl_reset;
+        pm_power_off = at91sam9rl_poweroff;
         at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
 
         /* Init clock subsystem */
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index f43b5c33e45d..dbb9a5fc2090 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -20,7 +20,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91sam9rl.h>
 #include <asm/arch/at91sam9rl_matrix.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
@@ -105,10 +105,15 @@ static struct at91_nand_data nand_data;
 #define NAND_BASE       AT91_CHIPSELECT_3
 
 static struct resource nand_resources[] = {
-        {
+        [0] = {
                 .start  = NAND_BASE,
                 .end    = NAND_BASE + SZ_256M - 1,
                 .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_BASE_SYS + AT91_ECC,
+                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
         }
 };
 
@@ -385,6 +390,55 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 
 
 /* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+        [0] = {
+                .start  = AT91SAM9RL_BASE_TCB0,
+                .end    = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9RL_ID_TC0,
+                .end    = AT91SAM9RL_ID_TC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT91SAM9RL_ID_TC1,
+                .end    = AT91SAM9RL_ID_TC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT91SAM9RL_ID_TC2,
+                .end    = AT91SAM9RL_ID_TC2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9rl_tcb_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb_resources,
+        .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has a separate clock and irq for each TC channel */
+        at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
+        at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
+        at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
+        platform_device_register(&at91sam9rl_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
  *  RTC
  * -------------------------------------------------------------------- */
 
@@ -418,7 +472,7 @@ static struct resource rtt_resources[] = {
 
 static struct platform_device at91sam9rl_rtt_device = {
         .name           = "at91_rtt",
-        .id             = -1,
+        .id             = 0,
         .resource       = rtt_resources,
         .num_resources  = ARRAY_SIZE(rtt_resources),
 };
@@ -539,9 +593,6 @@ static inline void configure_ssc1_pins(unsigned pins)
 }
 
 /*
- * Return the device node so that board init code can use it as the
- * parent for the device node reflecting how it's used on this board.
- *
  * SSC controllers are accessed through library code, instead of any
  * kind of all-singing/all-dancing driver.  For example one could be
  * used by a particular I2S audio codec's driver, while another one
@@ -802,54 +853,9 @@ static inline void configure_usart3_pins(unsigned pins)
                 at91_set_B_periph(AT91_PIN_PD3, 0);     /* CTS3 */
 }
 
-static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
 struct platform_device *atmel_default_console_device;   /* the serial console device */
 
-void __init __deprecated at91_init_serial(struct at91_uart_config *config)
-{
-        int i;
-
-        /* Fill in list of supported UARTs */
-        for (i = 0; i < config->nr_tty; i++) {
-                switch (config->tty_map[i]) {
-                        case 0:
-                                configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
-                                at91_uarts[i] = &at91sam9rl_uart0_device;
-                                at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart");
-                                break;
-                        case 1:
-                                configure_usart1_pins(0);
-                                at91_uarts[i] = &at91sam9rl_uart1_device;
-                                at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart");
-                                break;
-                        case 2:
-                                configure_usart2_pins(0);
-                                at91_uarts[i] = &at91sam9rl_uart2_device;
-                                at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart");
-                                break;
-                        case 3:
-                                configure_usart3_pins(0);
-                                at91_uarts[i] = &at91sam9rl_uart3_device;
-                                at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart");
-                                break;
-                        case 4:
-                                configure_dbgu_pins();
-                                at91_uarts[i] = &at91sam9rl_dbgu_device;
-                                at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart");
-                                break;
-                        default:
-                                continue;
-                }
-                at91_uarts[i]->id = i;          /* update ID number to mapped ID */
-        }
-
-        /* Set serial console device */
-        if (config->console_tty < ATMEL_MAX_UART)
-                atmel_default_console_device = at91_uarts[config->console_tty];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
@@ -893,8 +899,6 @@ void __init at91_set_serial_console(unsigned portnr)
 {
         if (portnr < ATMEL_MAX_UART)
                 atmel_default_console_device = at91_uarts[portnr];
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 
 void __init at91_add_device_serial(void)
@@ -905,9 +909,11 @@ void __init at91_add_device_serial(void)
                 if (at91_uarts[i])
                         platform_device_register(at91_uarts[i]);
         }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
-void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
 void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
@@ -925,6 +931,7 @@ static int __init at91_add_standard_devices(void)
         at91_add_device_rtc();
         at91_add_device_rtt();
         at91_add_device_watchdog();
+        at91_add_device_tc();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
new file mode 100644
index 000000000000..b22a1a004055
--- /dev/null
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -0,0 +1,180 @@
+/*
+ * KwikByte CAM60 (KB9260)
+ *
+ * based on board-sam9260ek.c
+ *   Copyright (C) 2005 SAN People
+ *   Copyright (C) 2006 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+
+#include "generic.h"
+
+
+static void __init cam60_map_io(void)
+{
+        /* Initialize processor: 10 MHz crystal */
+        at91sam9260_initialize(10000000);
+
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init cam60_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host
+ */
+static struct at91_usbh_data __initdata cam60_usbh_data = {
+        .ports          = 1,
+};
+
+
+/*
+ * SPI devices.
+ */
+#if defined(CONFIG_MTD_DATAFLASH)
+static struct mtd_partition __initdata cam60_spi_partitions[] = {
+        {
+                .name   = "BOOT1",
+                .offset = 0,
+                .size   = 4 * 1056,
+        },
+        {
+                .name   = "BOOT2",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 256 * 1056,
+        },
+        {
+                .name   = "kernel",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 2222 * 1056,
+        },
+        {
+                .name   = "file system",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct flash_platform_data __initdata cam60_spi_flash_platform_data = {
+        .name           = "spi_flash",
+        .parts          = cam60_spi_partitions,
+        .nr_parts       = ARRAY_SIZE(cam60_spi_partitions)
+};
+#endif
+
+static struct spi_board_info cam60_spi_devices[] = {
+#if defined(CONFIG_MTD_DATAFLASH)
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+                .platform_data  = &cam60_spi_flash_platform_data
+        },
+#endif
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct __initdata at91_eth_data cam60_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PB5,
+        .is_rmii        = 0,
+};
+
+
+/*
+ * NAND Flash
+ */
+static struct mtd_partition __initdata cam60_nand_partition[] = {
+        {
+                .name   = "nand_fs",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(cam60_nand_partition);
+        return cam60_nand_partition;
+}
+
+static struct at91_nand_data __initdata cam60_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+        // .det_pin     = ... not there
+        .rdy_pin        = AT91_PIN_PA9,
+        .enable_pin     = AT91_PIN_PA7,
+        .partition_info = nand_partitions,
+};
+
+
+static void __init cam60_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* SPI */
+        at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices));
+        /* Ethernet */
+        at91_add_device_eth(&cam60_macb_data);
+        /* USB Host */
+        /* enable USB power supply circuit */
+        at91_set_gpio_output(AT91_PIN_PB18, 1);
+        at91_add_device_usbh(&cam60_usbh_data);
+        /* NAND */
+        at91_add_device_nand(&cam60_nand_data);
+}
+
+MACHINE_START(CAM60, "KwikByte CAM60")
+        /* Maintainer: KwikByte */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = cam60_map_io,
+        .init_irq       = cam60_init_irq,
+        .init_machine   = cam60_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index 185437131541..e5512d1ff217 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -45,7 +45,7 @@
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91cap9_matrix.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 0e2a11fc5bbd..26fea4dcc3a0 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -43,17 +43,6 @@
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata csb337_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init csb337_map_io(void)
 {
         /* Initialize processor: 3.6864 MHz crystal */
@@ -62,8 +51,11 @@ static void __init csb337_map_io(void)
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&csb337_uart_config);
+        /* DBGU on ttyS0 */
+        at91_register_uart(0, 0, 0);
+
+        /* make console=ttyS0 the default */
+        at91_set_serial_console(0);
 }
 
 static void __init csb337_init_irq(void)
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index c5c721d27f42..419fd19b620b 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -40,27 +40,16 @@
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata csb637_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 1, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init csb637_map_io(void)
 {
         /* Initialize processor: 3.6864 MHz crystal */
         at91rm9200_initialize(3686400, AT91RM9200_BGA);
 
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
+        /* DBGU on ttyS0 */
+        at91_register_uart(0, 0, 0);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&csb637_uart_config);
+        /* make console=ttyS0 the default */
+        at91_set_serial_console(0);
 }
 
 static void __init csb637_init_irq(void)
@@ -118,8 +107,19 @@ static struct platform_device csb_flash = {
         .num_resources  = ARRAY_SIZE(csb_flash_resources),
 };
 
+static struct gpio_led csb_leds[] = {
+        {       /* "d1", red */
+                .name                   = "d1",
+                .gpio                   = AT91_PIN_PB2,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+};
+
 static void __init csb637_board_init(void)
 {
+        /* LED(s) */
+        at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
         /* Serial */
         at91_add_device_serial();
         /* Ethernet */
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
new file mode 100644
index 000000000000..e77fad443835
--- /dev/null
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -0,0 +1,178 @@
+/*
+ * linux/arch/arm/mach-at91rm9200/board-ecbat91.c
+ * Copyright (C) 2007 emQbit.com.
+ *
+ * We started from board-dk.c, which is Copyright (C) 2005 SAN People.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+
+#include "generic.h"
+
+
+static void __init ecb_at91map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
+
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
+
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx & Tx only) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init ecb_at91init_irq(void)
+{
+        at91rm9200_init_interrupts(NULL);
+}
+
+static struct at91_eth_data __initdata ecb_at91eth_data = {
+        .phy_irq_pin    = AT91_PIN_PC4,
+        .is_rmii        = 0,
+};
+
+static struct at91_usbh_data __initdata ecb_at91usbh_data = {
+        .ports          = 1,
+};
+
+static struct at91_mmc_data __initdata ecb_at91mmc_data = {
+        .slot_b         = 0,
+        .wire4          = 1,
+};
+
+
+#if defined(CONFIG_MTD_DATAFLASH)
+static struct mtd_partition __initdata my_flash0_partitions[] =
+{
+        {       /* 0x8400 */
+                .name   = "Darrell-loader",
+                .offset = 0,
+                .size   = 12* 1056,
+        },
+        {
+                .name   = "U-boot",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 110 * 1056,
+        },
+        {       /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
+                .name   = "UBoot-env",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 8 * 1056,
+        },
+        {       /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
+                .name   = "Kernel",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = 1534 * 1056,
+        },
+        {       /* 190200 - jffs2 root filesystem */
+                .name   = "Filesystem",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = MTDPART_SIZ_FULL,     /* 26 sectors */
+        }
+};
+
+static struct flash_platform_data __initdata my_flash0_platform = {
+        .name           = "Removable flash card",
+        .parts          = my_flash0_partitions,
+        .nr_parts       = ARRAY_SIZE(my_flash0_partitions)
+};
+
+#endif
+
+static struct spi_board_info __initdata ecb_at91spi_devices[] = {
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 10 * 1000 * 1000,
+                .bus_num        = 0,
+#if defined(CONFIG_MTD_DATAFLASH)
+                .platform_data  = &my_flash0_platform,
+#endif
+        },
+        {       /* User accessable spi - cs1 (250KHz) */
+                .modalias       = "spi-cs1",
+                .chip_select    = 1,
+                .max_speed_hz   = 250 * 1000,
+        },
+        {       /* User accessable spi - cs2 (1MHz) */
+                .modalias       = "spi-cs2",
+                .chip_select    = 2,
+                .max_speed_hz   = 1 * 1000 * 1000,
+        },
+        {       /* User accessable spi - cs3 (10MHz) */
+                .modalias       = "spi-cs3",
+                .chip_select    = 3,
+                .max_speed_hz   = 10 * 1000 * 1000,
+        },
+};
+
+static void __init ecb_at91board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+
+        /* Ethernet */
+        at91_add_device_eth(&ecb_at91eth_data);
+
+        /* USB Host */
+        at91_add_device_usbh(&ecb_at91usbh_data);
+
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+
+        /* MMC */
+        at91_add_device_mmc(0, &ecb_at91mmc_data);
+
+        /* SPI */
+        at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
+}
+
+MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
+        /* Maintainer: emQbit.com */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91rm9200_timer,
+        .map_io         = ecb_at91map_io,
+        .init_irq       = ecb_at91init_irq,
+        .init_machine   = ecb_at91board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
new file mode 100644
index 000000000000..8f76af5e219a
--- /dev/null
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -0,0 +1,199 @@
+/*
+ * linux/arch/arm/mach-at91/board-sam9-l9260.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *  Copyright (C) 2007 Olimex Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+
+#include "generic.h"
+
+
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91sam9260_initialize(18432000);
+
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
+
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init ek_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata ek_usbh_data = {
+        .ports          = 2,
+};
+
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata ek_udc_data = {
+        .vbus_pin       = AT91_PIN_PC5,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+
+/*
+ * SPI devices.
+ */
+static struct spi_board_info ek_spi_devices[] = {
+#if !defined(CONFIG_MMC_AT91)
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 1,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
+        {       /* DataFlash card */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#endif
+#endif
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PA7,
+        .is_rmii        = 0,
+};
+
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Bootloader Area",
+                .offset = 0,
+                .size   = 10 * 1024 * 1024,
+        },
+        {
+                .name   = "User Area",
+                .offset = 10 * 1024 * 1024,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+
+static struct at91_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+//      .det_pin        = ... not connected
+        .rdy_pin        = AT91_PIN_PC13,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata ek_mmc_data = {
+        .slot_b         = 1,
+        .wire4          = 1,
+        .det_pin        = AT91_PIN_PC8,
+        .wp_pin         = AT91_PIN_PC4,
+//      .vcc_pin        = ... not connected
+};
+
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&ek_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&ek_udc_data);
+        /* SPI */
+        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* NAND */
+        at91_add_device_nand(&ek_nand_data);
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* MMC */
+        at91_add_device_mmc(0, &ek_mmc_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+}
+
+MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
+        /* Maintainer: Olimex */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index b343a6c28120..4d1d9c777084 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -25,6 +25,8 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/at73c213.h>
+#include <linux/clk.h>
 
 #include <asm/hardware.h>
 #include <asm/setup.h>
@@ -37,29 +39,28 @@
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/at91sam926x_mc.h>
 
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 5 = USART0 .. USART5
- *    6      = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 3,
-        .tty_map        = { 6, 0, 1, -1, -1, -1, -1 }   /* ttyS0, ..., ttyS6 */
-};
-
 static void __init ek_map_io(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91sam9260_initialize(18432000);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&ek_uart_config);
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init ek_init_irq(void)
@@ -85,6 +86,35 @@ static struct at91_udc_data __initdata ek_udc_data = {
 
 
 /*
+ * Audio
+ */
+static struct at73c213_board_info at73c213_data = {
+        .ssc_id         = 0,
+        .shortname      = "AT91SAM9260-EK external DAC",
+};
+
+#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
+static void __init at73c213_set_clk(struct at73c213_board_info *info)
+{
+        struct clk *pck0;
+        struct clk *plla;
+
+        pck0 = clk_get(NULL, "pck0");
+        plla = clk_get(NULL, "plla");
+
+        /* AT73C213 MCK Clock */
+        at91_set_B_periph(AT91_PIN_PC1, 0);     /* PCK0 */
+
+        clk_set_parent(pck0, plla);
+        clk_put(plla);
+
+        info->dac_clk = pck0;
+}
+#else
+static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
+#endif
+
+/*
  * SPI devices.
  */
 static struct spi_board_info ek_spi_devices[] = {
@@ -110,6 +140,8 @@ static struct spi_board_info ek_spi_devices[] = {
                 .chip_select    = 0,
                 .max_speed_hz   = 10 * 1000 * 1000,
                 .bus_num        = 1,
+                .mode           = SPI_MODE_1,
+                .platform_data  = &at73c213_data,
         },
 #endif
 };
@@ -172,6 +204,24 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
 //      .vcc_pin        = ... not connected
 };
 
+
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* "bottom" led, green, userled1 to be defined */
+                .name                   = "ds5",
+                .gpio                   = AT91_PIN_PA6,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* "power" led, yellow */
+                .name                   = "ds1",
+                .gpio                   = AT91_PIN_PA9,
+                .default_trigger        = "heartbeat",
+        }
+};
+
 static void __init ek_board_init(void)
 {
         /* Serial */
@@ -190,6 +240,11 @@ static void __init ek_board_init(void)
         at91_add_device_mmc(0, &ek_mmc_data);
         /* I2C */
         at91_add_device_i2c(NULL, 0);
+        /* SSC (to AT73C213) */
+        at73c213_set_clk(&at73c213_data);
+        at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
 
 MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 0ce38dfa6ebe..08382c0df221 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -26,6 +26,8 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/spi/at73c213.h>
+#include <linux/clk.h>
 #include <linux/dm9000.h>
 #include <linux/fb.h>
 #include <linux/gpio_keys.h>
@@ -44,22 +46,11 @@
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 2 = USART0 .. USART2
- *    3      = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 1,
-        .tty_map        = { 3, -1, -1, -1 }             /* ttyS0, ..., ttyS3 */
-};
-
 static void __init ek_map_io(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
@@ -68,8 +59,11 @@ static void __init ek_map_io(void)
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&ek_uart_config);
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init ek_init_irq(void)
@@ -239,6 +233,35 @@ static void __init ek_add_device_ts(void) {}
 #endif
 
 /*
+ * Audio
+ */
+static struct at73c213_board_info at73c213_data = {
+        .ssc_id         = 1,
+        .shortname      = "AT91SAM9261-EK external DAC",
+};
+
+#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
+static void __init at73c213_set_clk(struct at73c213_board_info *info)
+{
+        struct clk *pck2;
+        struct clk *plla;
+
+        pck2 = clk_get(NULL, "pck2");
+        plla = clk_get(NULL, "plla");
+
+        /* AT73C213 MCK Clock */
+        at91_set_B_periph(AT91_PIN_PB31, 0);    /* PCK2 */
+
+        clk_set_parent(pck2, plla);
+        clk_put(plla);
+
+        info->dac_clk = pck2;
+}
+#else
+static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
+#endif
+
+/*
  * SPI devices
  */
 static struct spi_board_info ek_spi_devices[] = {
@@ -256,6 +279,7 @@ static struct spi_board_info ek_spi_devices[] = {
                 .bus_num        = 0,
                 .platform_data  = &ads_info,
                 .irq            = AT91SAM9261_ID_IRQ0,
+                .controller_data = (void *) AT91_PIN_PA28,      /* CS pin */
         },
 #endif
 #if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
@@ -271,6 +295,9 @@ static struct spi_board_info ek_spi_devices[] = {
                 .chip_select    = 3,
                 .max_speed_hz   = 10 * 1000 * 1000,
                 .bus_num        = 0,
+                .mode           = SPI_MODE_1,
+                .platform_data  = &at73c213_data,
+                .controller_data = (void*) AT91_PIN_PA29,       /* default for CS3 is PA6, but it must be PA29 */
         },
 #endif
 };
@@ -460,6 +487,29 @@ static void __init ek_add_device_buttons(void)
 static void __init ek_add_device_buttons(void) {}
 #endif
 
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* "bottom" led, green, userled1 to be defined */
+                .name                   = "ds7",
+                .gpio                   = AT91_PIN_PA14,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* "top" led, green, userled2 to be defined */
+                .name                   = "ds8",
+                .gpio                   = AT91_PIN_PA13,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* "power" led, yellow */
+                .name                   = "ds1",
+                .gpio                   = AT91_PIN_PA23,
+                .default_trigger        = "heartbeat",
+        }
+};
+
 static void __init ek_board_init(void)
 {
         /* Serial */
@@ -481,6 +531,9 @@ static void __init ek_board_init(void)
         at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
         /* Touchscreen */
         ek_add_device_ts();
+        /* SSC (to AT73C213) */
+        at73c213_set_clk(&at73c213_data);
+        at91_add_device_ssc(AT91SAM9261_ID_SSC1, ATMEL_SSC_TX);
 #else
         /* MMC */
         at91_add_device_mmc(0, &ek_mmc_data);
@@ -489,6 +542,8 @@ static void __init ek_board_init(void)
         at91_add_device_lcdc(&ek_lcdc_data);
         /* Push Buttons */
         ek_add_device_buttons();
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
 
 MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index bf103b24c937..b4cd5d0ed597 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -43,29 +43,24 @@
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 2 = USART0 .. USART2
- *    3      = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 3, 0, -1, -1, }             /* ttyS0, ..., ttyS3 */
-};
-
 static void __init ek_map_io(void)
 {
         /* Initialize processor: 16.367 MHz crystal */
         at91sam9263_initialize(16367660);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&ek_uart_config);
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init ek_init_irq(void)
@@ -341,7 +336,7 @@ static struct gpio_led ek_leds[] = {
                 .name                   = "ds3",
                 .gpio                   = AT91_PIN_PB7,
                 .default_trigger        = "heartbeat",
-        },
+        }
 };
 
 
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index bc0546d7245f..ffc0597aee8d 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -29,29 +29,24 @@
 
 #include <asm/arch/board.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/at91sam926x_mc.h>
+#include <asm/arch/at91sam9_smc.h>
 
 #include "generic.h"
 
 
-/*
- * Serial port configuration.
- *    0 .. 3 = USART0 .. USART3
- *    4      = DBGU
- */
-static struct at91_uart_config __initdata ek_uart_config = {
-        .console_tty    = 0,                            /* ttyS0 */
-        .nr_tty         = 2,
-        .tty_map        = { 4, 0, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
-};
-
 static void __init ek_map_io(void)
 {
         /* Initialize processor: 12.000 MHz crystal */
         at91sam9rl_initialize(12000000);
 
-        /* Setup the serial ports and console */
-        at91_init_serial(&ek_uart_config);
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
 }
 
 static void __init ek_init_irq(void)
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
new file mode 100755
index 000000000000..b5717108991d
--- /dev/null
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -0,0 +1,683 @@
+/*
+ * linux/arch/arm/mach-at91/board-yl-9200.c
+ *
+ * Adapted from:
+ *various board files in
+ * /arch/arm/mach-at91
+ * modifications  to convert to  YL-9200 platform
+ *  Copyright (C) 2007 S.Birtles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+/*#include <linux/can_bus/candata.h>*/
+#include <linux/spi/ads7846.h>
+#include <linux/mtd/physmap.h>
+
+/*#include <sound/gpio_sounder.h>*/
+#include <asm/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91rm9200_mc.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+
+#include "generic.h"
+#include <asm/arch/at91_pio.h>
+
+#define YL_9200_FLASH_BASE      AT91_CHIPSELECT_0
+#define YL_9200_FLASH_SIZE      0x800000
+
+/*
+ * Serial port configuration.
+ *    0 .. 3 = USART0 .. USART3
+ *    4      = DBGU
+ *atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL
+ *atmel_usart.1: ttyS1 at MMIO 0xfffc0000 (irq = 6) is a ATMEL_SERIAL
+ *atmel_usart.2: ttyS2 at MMIO 0xfffc4000 (irq = 7) is a ATMEL_SERIAL
+ *atmel_usart.3: ttyS3 at MMIO 0xfffc8000 (irq = 8) is a ATMEL_SERIAL
+ *atmel_usart.4: ttyS4 at MMIO 0xfffcc000 (irq = 9) is a ATMEL_SERIAL
+ * on the YL-9200 we are sitting at the following
+ *ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL
+ *ttyS1 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL
+ */
+
+/* extern void __init yl_9200_add_device_sounder(struct gpio_sounder *sounders, int nr);*/
+
+static struct at91_uart_config __initdata yl_9200_uart_config = {
+        .console_tty    = 0,                            /* ttyS0 */
+        .nr_tty         = 3,
+        .tty_map        = { 4, 1, 0, -1, -1 }           /* ttyS0, ..., ttyS4 */
+};
+
+static void __init yl_9200_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        /*Also initialises register clocks & gpio*/
+        at91rm9200_initialize(18432000, AT91RM9200_PQFP); /*we have a 3 bank system*/
+
+        /* Setup the serial ports and console */
+        at91_init_serial(&yl_9200_uart_config);
+
+        /* Setup the LEDs D2=PB17,D3=PB16 */
+        at91_init_leds(AT91_PIN_PB16,AT91_PIN_PB17); /*cpu-led,timer-led*/
+}
+
+static void __init yl_9200_init_irq(void)
+{
+        at91rm9200_init_interrupts(NULL);
+}
+
+static struct at91_eth_data __initdata yl_9200_eth_data = {
+        .phy_irq_pin    = AT91_PIN_PB28,
+        .is_rmii        = 1,
+};
+
+static struct at91_usbh_data __initdata yl_9200_usbh_data = {
+        .ports          = 1,  /* this should be 1 not 2 for the Yl9200*/
+};
+
+static struct at91_udc_data __initdata yl_9200_udc_data = {
+/*on sheet 7 Schemitic rev 1.0*/
+        .pullup_pin     = AT91_PIN_PC4,
+        .vbus_pin=  AT91_PIN_PC5,
+        .pullup_active_low = 1, /*ACTIVE LOW!! due to PNP transistor on page 7*/
+
+};
+/*
+static struct at91_cf_data __initdata yl_9200_cf_data = {
+TODO S.BIRTLES
+        .det_pin        = AT91_PIN_xxx,
+        .rst_pin        = AT91_PIN_xxx,
+        .irq_pin        = ... not connected
+        .vcc_pin        = ... always powered
+
+};
+*/
+static struct at91_mmc_data __initdata yl_9200_mmc_data = {
+        .det_pin        = AT91_PIN_PB9, /*THIS LOOKS CORRECT SHEET7*/
+/*      .wp_pin         = ... not connected  SHEET7*/
+        .slot_b         = 0,
+        .wire4          = 1,
+
+};
+
+/* --------------------------------------------------------------------
+ *  Touch screen
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+static int ads7843_pendown_state(void)
+{
+        return !at91_get_gpio_value(AT91_PIN_PB11);     /* Touchscreen PENIRQ */
+}
+
+static void __init at91_init_device_ts(void)
+{
+/*IMPORTANT NOTE THE SPI INTERFACE IS ALREADY CONFIGURED BY XXX_DEVICES.C
+THAT IS TO SAY THAT  MISO,MOSI,SPCK AND CS  are already configured
+we only need to enable the other datapins which are:
+PB10/RK1 BUSY
+*/
+/* Touchscreen BUSY signal ,  pin,use pullup ( TODO not currently used in the ADS7843/6.c driver)*/
+at91_set_gpio_input(AT91_PIN_PB10, 1);
+}
+
+#else
+static void __init at91_init_device_ts(void) {}
+#endif
+
+static struct ads7846_platform_data ads_info = {
+        .model                  = 7843,
+        .x_min                  = 150,
+        .x_max                  = 3830,
+        .y_min                  = 190,
+        .y_max                  = 3830,
+        .vref_delay_usecs       = 100,
+/* for a 8" touch screen*/
+        //.x_plate_ohms         = 603, //= 450, S.Birtles TODO
+        //.y_plate_ohms         = 332, //= 250, S.Birtles TODO
+/*for a 10.4" touch screen*/
+        //.x_plate_ohms         =611,
+        //.y_plate_ohms         =325,
+
+        .x_plate_ohms   = 576,
+        .y_plate_ohms   = 366,
+                //
+        .pressure_max           = 15000, /*generally nonsense on the 7843*/
+         /*number of times to send query to chip in a given run 0 equals one time (do not set to 0!! ,there is a bug in ADS 7846 code)*/
+        .debounce_max           = 1,
+        .debounce_rep           = 0,
+        .debounce_tol           = (~0),
+        .get_pendown_state      = ads7843_pendown_state,
+};
+
+/*static struct canbus_platform_data can_info = {
+        .model                  = 2510,
+};
+*/
+
+static struct spi_board_info yl_9200_spi_devices[] = {
+/*this sticks it at:
+ /sys/devices/platform/atmel_spi.0/spi0.0
+ /sys/bus/platform/devices/
+Documentation/spi IIRC*/
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+ /*(this IS correct 04-NOV-2007)*/
+        {
+                .modalias               = "ads7846", /* because the driver is called ads7846*/
+                .chip_select    = 0, /*THIS MUST BE AN INDEX INTO AN ARRAY OF  pins */
+/*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select*/
+                /*.controller_data =AT91_PIN_PA3 ,*/
+                .max_speed_hz   = 5000*26, /*(4700 * 26)-125000 * 26, (max sample rate @ 3V) * (cmd + data + overhead) */
+                .bus_num                = 0,
+                .platform_data  = &ads_info,
+                .irq                    = AT91_PIN_PB11,
+        },
+#endif
+/*we need to put our CAN driver data here!!*/
+/*THIS IS ALL DUMMY DATA*/
+/*      {
+                .modalias               = "mcp2510", //DUMMY for MCP2510 chip
+                .chip_select    = 1,*/ /*THIS MUST BE AN INDEX INTO AN ARRAY OF  pins */
+        /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select */
+        /*  .controller_data =AT91_PIN_PA4 ,
+                .max_speed_hz   = 25000 * 26,
+                .bus_num                = 0,
+                .platform_data  = &can_info,
+                .irq                    = AT91_PIN_PC0,
+        },
+        */
+        //max SPI chip needs to go here
+};
+
+static struct mtd_partition __initdata yl_9200_nand_partition[] = {
+        {
+                .name   = "AT91 NAND partition 1, boot",
+                .offset = 0,
+                .size   = 1 * SZ_256K
+        },
+        {
+                .name   = "AT91 NAND partition 2, kernel",
+                .offset = 1 * SZ_256K,
+                .size   = 2 * SZ_1M - 1 * SZ_256K
+        },
+        {
+                .name   = "AT91 NAND partition 3, filesystem",
+                .offset = 2 * SZ_1M,
+                .size   = 14 * SZ_1M
+        },
+        {
+                .name   = "AT91 NAND partition 4, storage",
+                .offset = 16 * SZ_1M,
+                .size   = 16 * SZ_1M
+        },
+        {
+                .name   = "AT91 NAND partition 5, ext-fs",
+                .offset = 32 * SZ_1M,
+                .size   = 32 * SZ_1M
+        },
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(yl_9200_nand_partition);
+        return yl_9200_nand_partition;
+}
+
+static struct at91_nand_data __initdata yl_9200_nand_data = {
+        .ale= 6,
+        .cle= 7,
+        /*.det_pin      = AT91_PIN_PCxx,*/   /*we don't have a det pin because NandFlash is fixed to board*/
+        .rdy_pin        = AT91_PIN_PC14,  /*R/!B Sheet10*/
+        .enable_pin     = AT91_PIN_PC15,  /*!CE  Sheet10 */
+        .partition_info = nand_partitions,
+};
+
+
+
+/*
+TODO S.Birtles
+potentially a problem with the size above
+physmap platform flash device: 00800000 at 10000000
+physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
+NOR chip too large to fit in mapping. Attempting to cope...
+ Intel/Sharp Extended Query Table at 0x0031
+Using buffer write method
+cfi_cmdset_0001: Erase suspend on write enabled
+Reducing visibility of 16384KiB chip to 8192KiB
+*/
+
+static struct mtd_partition yl_9200_flash_partitions[] = {
+        {
+                .name =         "Bootloader",
+                .size =         0x00040000,
+                .offset =       0,
+                .mask_flags =   MTD_WRITEABLE  /* force read-only */
+        },{
+                .name =         "Kernel",
+                .size =         0x001C0000,
+                .offset =       0x00040000,
+        },{
+                .name =         "Filesystem",
+                .size =         MTDPART_SIZ_FULL,
+                .offset =       0x00200000
+        }
+
+};
+
+static struct physmap_flash_data yl_9200_flash_data = {
+        .width  = 2,
+        .parts          = yl_9200_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(yl_9200_flash_partitions),
+};
+
+static struct resource yl_9200_flash_resources[] = {
+{
+        .start          = YL_9200_FLASH_BASE,
+        .end            = YL_9200_FLASH_BASE + YL_9200_FLASH_SIZE - 1,
+        .flags          = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device yl_9200_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                                .platform_data  = &yl_9200_flash_data,
+                        },
+        .resource       = yl_9200_flash_resources,
+        .num_resources  = ARRAY_SIZE(yl_9200_flash_resources),
+};
+
+
+static struct gpio_led yl_9200_leds[] = {
+/*D2 &D3 are passed directly in via at91_init_leds*/
+        {
+                .name                   = "led4",  /*D4*/
+                .gpio                   = AT91_PIN_PB15,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+                /*.default_trigger      = "timer",*/
+        },
+        {
+                .name                   = "led5",  /*D5*/
+                .gpio                   = AT91_PIN_PB8,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        }
+};
+
+//static struct gpio_sounder yl_9200_sounder[] = {*/
+/*This is a simple speaker attached to a gpo line*/
+
+//      {
+//              .name                   = "Speaker",  /*LS1*/
+//              .gpio                   = AT91_PIN_PA22,
+//              .active_low             = 0,
+//              .default_trigger        = "heartbeat",
+                /*.default_trigger      = "timer",*/
+//      },
+//};
+
+
+
+static struct i2c_board_info __initdata yl_9200_i2c_devices[] = {
+        {
+        /*TODO*/
+                I2C_BOARD_INFO("CS4334", 0x00),
+        }
+};
+
+
+ /*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button yl_9200_buttons[] = {
+        {
+                .gpio           = AT91_PIN_PA24,
+                .code   = BTN_2,
+                .desc           = "SW2",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = AT91_PIN_PB1,
+                .code   = BTN_3,
+                .desc           = "SW3",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = AT91_PIN_PB2,
+                .code   = BTN_4,
+                .desc           = "SW4",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = AT91_PIN_PB6,
+                .code   = BTN_5,
+                .desc           = "SW5",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+
+};
+
+static struct gpio_keys_platform_data yl_9200_button_data = {
+        .buttons        = yl_9200_buttons,
+        .nbuttons       = ARRAY_SIZE(yl_9200_buttons),
+};
+
+static struct platform_device yl_9200_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+        .platform_data  = &yl_9200_button_data,
+        }
+};
+
+static void __init yl_9200_add_device_buttons(void)
+{
+        //SW2
+        at91_set_gpio_input(AT91_PIN_PA24, 0);
+        at91_set_deglitch(AT91_PIN_PA24, 1);
+
+        //SW3
+        at91_set_gpio_input(AT91_PIN_PB1, 0);
+        at91_set_deglitch(AT91_PIN_PB1, 1);
+        //SW4
+        at91_set_gpio_input(AT91_PIN_PB2, 0);
+        at91_set_deglitch(AT91_PIN_PB2, 1);
+
+        //SW5
+        at91_set_gpio_input(AT91_PIN_PB6, 0);
+        at91_set_deglitch(AT91_PIN_PB6, 1);
+
+
+        at91_set_gpio_output(AT91_PIN_PB7, 1);  /* #TURN BUTTONS ON, SHEET 5  of schematics */
+        platform_device_register(&yl_9200_button_device);
+}
+#else
+static void __init yl_9200_add_device_buttons(void) {}
+#endif
+
+#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
+#include <video/s1d13xxxfb.h>
+
+/* EPSON S1D13806 FB (discontinued chip)*/
+/* EPSON S1D13506 FB */
+
+#define AT91_FB_REG_BASE        0x80000000L
+#define AT91_FB_REG_SIZE        0x200
+#define AT91_FB_VMEM_BASE       0x80200000L
+#define AT91_FB_VMEM_SIZE       0x200000L
+
+/*#define S1D_DISPLAY_WIDTH           640*/
+/*#define S1D_DISPLAY_HEIGHT          480*/
+
+
+static void __init yl_9200_init_video(void)
+{
+        at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
+        at91_sys_write(AT91_PIOC + PIO_BSR,0);
+        at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
+
+        at91_sys_write( AT91_SMC_CSR(2),
+        AT91_SMC_NWS_(0x4) |
+        AT91_SMC_WSEN |
+        AT91_SMC_TDF_(0x100) |
+        AT91_SMC_DBW
+        );
+
+
+
+}
+
+
+static struct s1d13xxxfb_regval yl_9200_s1dfb_initregs[] =
+{
+        {S1DREG_MISC,                           0x00},   /* Miscellaneous Register*/
+        {S1DREG_COM_DISP_MODE,          0x01},   /* Display Mode Register, LCD only*/
+        {S1DREG_GPIO_CNF0,                      0x00},   /* General IO Pins Configuration Register*/
+        {S1DREG_GPIO_CTL0,                      0x00},   /* General IO Pins Control Register*/
+        {S1DREG_CLK_CNF,                        0x11},   /* Memory Clock Configuration Register*/
+        {S1DREG_LCD_CLK_CNF,            0x10},   /* LCD Pixel Clock Configuration Register*/
+        {S1DREG_CRT_CLK_CNF,            0x12},   /* CRT/TV Pixel Clock Configuration Register*/
+        {S1DREG_MPLUG_CLK_CNF,          0x01},   /* MediaPlug Clock Configuration Register*/
+        {S1DREG_CPU2MEM_WST_SEL,        0x02},   /* CPU To Memory Wait State Select Register*/
+        {S1DREG_MEM_CNF,                        0x00},   /* Memory Configuration Register*/
+        {S1DREG_SDRAM_REF_RATE,         0x04},   /* DRAM Refresh Rate Register, MCLK source*/
+        {S1DREG_SDRAM_TC0,                      0x12},   /* DRAM Timings Control Register 0*/
+        {S1DREG_SDRAM_TC1,                      0x02},   /* DRAM Timings Control Register 1*/
+        {S1DREG_PANEL_TYPE,                     0x25},   /* Panel Type Register*/
+        {S1DREG_MOD_RATE,                       0x00},   /* MOD Rate Register*/
+        {S1DREG_LCD_DISP_HWIDTH,        0x4F},   /* LCD Horizontal Display Width Register*/
+        {S1DREG_LCD_NDISP_HPER,         0x13},   /* LCD Horizontal Non-Display Period Register*/
+        {S1DREG_TFT_FPLINE_START,       0x01},   /* TFT FPLINE Start Position Register*/
+        {S1DREG_TFT_FPLINE_PWIDTH,      0x0c},   /* TFT FPLINE Pulse Width Register*/
+        {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},   /* LCD Vertical Display Height Register 0*/
+        {S1DREG_LCD_DISP_VHEIGHT1,      0x01},   /* LCD Vertical Display Height Register 1*/
+        {S1DREG_LCD_NDISP_VPER,         0x2c},   /* LCD Vertical Non-Display Period Register*/
+        {S1DREG_TFT_FPFRAME_START,      0x0a},   /* TFT FPFRAME Start Position Register*/
+        {S1DREG_TFT_FPFRAME_PWIDTH,     0x02},   /* TFT FPFRAME Pulse Width Register*/
+        {S1DREG_LCD_DISP_MODE,          0x05},   /* LCD Display Mode Register*/
+        {S1DREG_LCD_MISC,                       0x01},   /* LCD Miscellaneous Register*/
+        {S1DREG_LCD_DISP_START0,        0x00},   /* LCD Display Start Address Register 0*/
+        {S1DREG_LCD_DISP_START1,        0x00},   /* LCD Display Start Address Register 1*/
+        {S1DREG_LCD_DISP_START2,        0x00},   /* LCD Display Start Address Register 2*/
+        {S1DREG_LCD_MEM_OFF0,           0x80},   /* LCD Memory Address Offset Register 0*/
+        {S1DREG_LCD_MEM_OFF1,           0x02},   /* LCD Memory Address Offset Register 1*/
+        {S1DREG_LCD_PIX_PAN,            0x03},   /* LCD Pixel Panning Register*/
+        {S1DREG_LCD_DISP_FIFO_HTC,      0x00},   /* LCD Display FIFO High Threshold Control Register*/
+        {S1DREG_LCD_DISP_FIFO_LTC,      0x00},   /* LCD Display FIFO Low Threshold Control Register*/
+        {S1DREG_CRT_DISP_HWIDTH,        0x4F},   /* CRT/TV Horizontal Display Width Register*/
+        {S1DREG_CRT_NDISP_HPER,         0x13},   /* CRT/TV Horizontal Non-Display Period Register*/
+        {S1DREG_CRT_HRTC_START,         0x01},   /* CRT/TV HRTC Start Position Register*/
+        {S1DREG_CRT_HRTC_PWIDTH,        0x0B},   /* CRT/TV HRTC Pulse Width Register*/
+        {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},   /* CRT/TV Vertical Display Height Register 0*/
+        {S1DREG_CRT_DISP_VHEIGHT1,      0x01},   /* CRT/TV Vertical Display Height Register 1*/
+        {S1DREG_CRT_NDISP_VPER,         0x2B},   /* CRT/TV Vertical Non-Display Period Register*/
+        {S1DREG_CRT_VRTC_START,         0x09},   /* CRT/TV VRTC Start Position Register*/
+        {S1DREG_CRT_VRTC_PWIDTH,        0x01},   /* CRT/TV VRTC Pulse Width Register*/
+        {S1DREG_TV_OUT_CTL,                     0x18},   /* TV Output Control Register */
+        {S1DREG_CRT_DISP_MODE,          0x05},   /* CRT/TV Display Mode Register, 16BPP*/
+        {S1DREG_CRT_DISP_START0,        0x00},   /* CRT/TV Display Start Address Register 0*/
+        {S1DREG_CRT_DISP_START1,        0x00},   /* CRT/TV Display Start Address Register 1*/
+        {S1DREG_CRT_DISP_START2,        0x00},   /* CRT/TV Display Start Address Register 2*/
+        {S1DREG_CRT_MEM_OFF0,           0x80},   /* CRT/TV Memory Address Offset Register 0*/
+        {S1DREG_CRT_MEM_OFF1,           0x02},   /* CRT/TV Memory Address Offset Register 1*/
+        {S1DREG_CRT_PIX_PAN,            0x00},   /* CRT/TV Pixel Panning Register*/
+        {S1DREG_CRT_DISP_FIFO_HTC,      0x00},   /* CRT/TV Display FIFO High Threshold Control Register*/
+        {S1DREG_CRT_DISP_FIFO_LTC,      0x00},   /* CRT/TV Display FIFO Low Threshold Control Register*/
+        {S1DREG_LCD_CUR_CTL,            0x00},   /* LCD Ink/Cursor Control Register*/
+        {S1DREG_LCD_CUR_START,          0x01},   /* LCD Ink/Cursor Start Address Register*/
+        {S1DREG_LCD_CUR_XPOS0,          0x00},   /* LCD Cursor X Position Register 0*/
+        {S1DREG_LCD_CUR_XPOS1,          0x00},   /* LCD Cursor X Position Register 1*/
+        {S1DREG_LCD_CUR_YPOS0,          0x00},   /* LCD Cursor Y Position Register 0*/
+        {S1DREG_LCD_CUR_YPOS1,          0x00},   /* LCD Cursor Y Position Register 1*/
+        {S1DREG_LCD_CUR_BCTL0,          0x00},   /* LCD Ink/Cursor Blue Color 0 Register*/
+        {S1DREG_LCD_CUR_GCTL0,          0x00},   /* LCD Ink/Cursor Green Color 0 Register*/
+        {S1DREG_LCD_CUR_RCTL0,          0x00},   /* LCD Ink/Cursor Red Color 0 Register*/
+        {S1DREG_LCD_CUR_BCTL1,          0x1F},   /* LCD Ink/Cursor Blue Color 1 Register*/
+        {S1DREG_LCD_CUR_GCTL1,          0x3F},   /* LCD Ink/Cursor Green Color 1 Register*/
+        {S1DREG_LCD_CUR_RCTL1,          0x1F},   /* LCD Ink/Cursor Red Color 1 Register*/
+        {S1DREG_LCD_CUR_FIFO_HTC,       0x00},   /* LCD Ink/Cursor FIFO Threshold Register*/
+        {S1DREG_CRT_CUR_CTL,            0x00},   /* CRT/TV Ink/Cursor Control Register*/
+        {S1DREG_CRT_CUR_START,          0x01},   /* CRT/TV Ink/Cursor Start Address Register*/
+        {S1DREG_CRT_CUR_XPOS0,          0x00},   /* CRT/TV Cursor X Position Register 0*/
+        {S1DREG_CRT_CUR_XPOS1,          0x00},   /* CRT/TV Cursor X Position Register 1*/
+        {S1DREG_CRT_CUR_YPOS0,          0x00},   /* CRT/TV Cursor Y Position Register 0*/
+        {S1DREG_CRT_CUR_YPOS1,          0x00},   /* CRT/TV Cursor Y Position Register 1*/
+        {S1DREG_CRT_CUR_BCTL0,          0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register*/
+        {S1DREG_CRT_CUR_GCTL0,          0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register*/
+        {S1DREG_CRT_CUR_RCTL0,          0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register*/
+        {S1DREG_CRT_CUR_BCTL1,          0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register*/
+        {S1DREG_CRT_CUR_GCTL1,          0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register*/
+        {S1DREG_CRT_CUR_RCTL1,          0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register*/
+        {S1DREG_CRT_CUR_FIFO_HTC,       0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register*/
+        {S1DREG_BBLT_CTL0,                      0x00},   /* BitBlt Control Register 0*/
+        {S1DREG_BBLT_CTL1,                      0x01},   /* BitBlt Control Register 1*/
+        {S1DREG_BBLT_CC_EXP,            0x00},   /* BitBlt ROP Code/Color Expansion Register*/
+        {S1DREG_BBLT_OP,                        0x00},   /* BitBlt Operation Register*/
+        {S1DREG_BBLT_SRC_START0,        0x00},   /* BitBlt Source Start Address Register 0*/
+        {S1DREG_BBLT_SRC_START1,        0x00},   /* BitBlt Source Start Address Register 1*/
+        {S1DREG_BBLT_SRC_START2,        0x00},   /* BitBlt Source Start Address Register 2*/
+        {S1DREG_BBLT_DST_START0,        0x00},   /* BitBlt Destination Start Address Register 0*/
+        {S1DREG_BBLT_DST_START1,        0x00},   /* BitBlt Destination Start Address Register 1*/
+        {S1DREG_BBLT_DST_START2,        0x00},   /* BitBlt Destination Start Address Register 2*/
+        {S1DREG_BBLT_MEM_OFF0,          0x00},   /* BitBlt Memory Address Offset Register 0*/
+        {S1DREG_BBLT_MEM_OFF1,          0x00},   /* BitBlt Memory Address Offset Register 1*/
+        {S1DREG_BBLT_WIDTH0,            0x00},   /* BitBlt Width Register 0*/
+        {S1DREG_BBLT_WIDTH1,            0x00},   /* BitBlt Width Register 1*/
+        {S1DREG_BBLT_HEIGHT0,           0x00},   /* BitBlt Height Register 0*/
+        {S1DREG_BBLT_HEIGHT1,           0x00},   /* BitBlt Height Register 1*/
+        {S1DREG_BBLT_BGC0,                      0x00},   /* BitBlt Background Color Register 0*/
+        {S1DREG_BBLT_BGC1,                      0x00},   /* BitBlt Background Color Register 1*/
+        {S1DREG_BBLT_FGC0,                      0x00},   /* BitBlt Foreground Color Register 0*/
+        {S1DREG_BBLT_FGC1,                      0x00},   /* BitBlt Foreground Color Register 1*/
+        {S1DREG_LKUP_MODE,                      0x00},   /* Look-Up Table Mode Register*/
+        {S1DREG_LKUP_ADDR,                      0x00},   /* Look-Up Table Address Register*/
+        {S1DREG_PS_CNF,                         0x00},   /* Power Save Configuration Register*/
+        {S1DREG_PS_STATUS,                      0x00},   /* Power Save Status Register*/
+        {S1DREG_CPU2MEM_WDOGT,          0x00},   /* CPU-to-Memory Access Watchdog Timer Register*/
+        {S1DREG_COM_DISP_MODE,          0x01},   /* Display Mode Register, LCD only*/
+};
+
+static u64 s1dfb_dmamask = 0xffffffffUL;
+
+static struct s1d13xxxfb_pdata yl_9200_s1dfb_pdata = {
+                .initregs                               = yl_9200_s1dfb_initregs,
+                .initregssize                   = ARRAY_SIZE(yl_9200_s1dfb_initregs),
+                .platform_init_video    = yl_9200_init_video,
+};
+
+static struct resource yl_9200_s1dfb_resource[] = {
+        [0] = { /* video mem */
+                .name   = "s1d13xxxfb memory",
+        /*      .name   = "s1d13806 memory",*/
+                .start  = AT91_FB_VMEM_BASE,
+                .end    = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = { /* video registers */
+                .name   = "s1d13xxxfb registers",
+        /*      .name   = "s1d13806 registers",*/
+                .start  = AT91_FB_REG_BASE,
+                .end    = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device yl_9200_s1dfb_device = {
+        /*TODO S.Birtles , really we need the chip revision in here as well*/
+                .name           = "s1d13806fb",
+        /*  .name               = "s1d13506fb",*/
+                .id                     = -1,
+                .dev            = {
+        /*TODO theres a waring here!!*/
+        /*WARNING: vmlinux.o(.data+0x2dbc): Section mismatch: reference to .init.text: (between 'yl_9200_s1dfb_pdata' and 's1dfb_dmamask')*/
+                .dma_mask               = &s1dfb_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &yl_9200_s1dfb_pdata,
+        },
+        .resource       = yl_9200_s1dfb_resource,
+        .num_resources  = ARRAY_SIZE(yl_9200_s1dfb_resource),
+};
+
+void __init yl_9200_add_device_video(void)
+{
+        platform_device_register(&yl_9200_s1dfb_device);
+}
+#else
+        void __init yl_9200_add_device_video(void) {}
+#endif
+
+/*this is not called first , yl_9200_map_io is called first*/
+static void __init yl_9200_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* Ethernet */
+        at91_add_device_eth(&yl_9200_eth_data);
+        /* USB Host */
+        at91_add_device_usbh(&yl_9200_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&yl_9200_udc_data);
+        /* pullup_pin it is  actually active low, but this is not needed, driver sets it up */
+        /*at91_set_multi_drive(yl_9200_udc_data.pullup_pin, 0);*/
+
+        /* Compact Flash */
+        /*at91_add_device_cf(&yl_9200_cf_data);*/
+
+        /* I2C */
+        at91_add_device_i2c(yl_9200_i2c_devices, ARRAY_SIZE(yl_9200_i2c_devices));
+        /* SPI */
+        /*TODO YL9200 we have 2 spi interfaces touch screen & CAN*/
+        /* AT91_PIN_PA5, AT91_PIN_PA6 , are used on the  max 485 NOT SPI*/
+
+        /*touch screen and CAN*/
+        at91_add_device_spi(yl_9200_spi_devices, ARRAY_SIZE(yl_9200_spi_devices));
+
+        /*Basically the  TS uses  PB11 & PB10 , PB11 is configured by the SPI system BP10 IS NOT USED!!*/
+        /* we need this incase the board is running without a touch screen*/
+        #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+        at91_init_device_ts(); /*init the touch screen device*/
+        #endif
+        /* DataFlash card */
+        at91_add_device_mmc(0, &yl_9200_mmc_data);
+        /* NAND */
+        at91_add_device_nand(&yl_9200_nand_data);
+        /* NOR Flash */
+        platform_device_register(&yl_9200_flash);
+        /* LEDs. Note!! this does not include the led's we passed for the processor status */
+        at91_gpio_leds(yl_9200_leds, ARRAY_SIZE(yl_9200_leds));
+        /* VGA  */
+        /*this is self registered by including the s1d13xxx chip in the kernel build*/
+        yl_9200_add_device_video();
+        /* Push Buttons */
+        yl_9200_add_device_buttons();
+        /*TODO fixup the Sounder */
+//      yl_9200_add_device_sounder(yl_9200_sounder,ARRAY_SIZE(yl_9200_sounder));
+
+}
+
+MACHINE_START(YL9200, "uCdragon YL-9200")
+        /* Maintainer: S.Birtles*/
+        .phys_io                = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer                  = &at91rm9200_timer,
+        .map_io                 = yl_9200_map_io,
+        .init_irq               = yl_9200_init_irq,
+        .init_machine   = yl_9200_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index a67defd50438..39733b6992aa 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -26,12 +26,135 @@
 #include <asm/mach-types.h>
 
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91rm9200_mc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/cpu.h>
 
 #include "generic.h"
 
+#ifdef CONFIG_ARCH_AT91RM9200
+#include <asm/arch/at91rm9200_mc.h>
+
+/*
+ * The AT91RM9200 goes into self-refresh mode with this command, and will
+ * terminate self-refresh automatically on the next SDRAM access.
+ */
+#define sdram_selfrefresh_enable()      at91_sys_write(AT91_SDRAMC_SRR, 1)
+#define sdram_selfrefresh_disable()     do {} while (0)
+
+#elif defined(CONFIG_ARCH_AT91CAP9)
+#include <asm/arch/at91cap9_ddrsdr.h>
+
+static u32 saved_lpr;
+
+static inline void sdram_selfrefresh_enable(void)
+{
+        u32 lpr;
+
+        saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
+
+        lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
+        at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
+}
+
+#define sdram_selfrefresh_disable()     at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
+
+#else
+#include <asm/arch/at91sam9_sdramc.h>
+
+static u32 saved_lpr;
+
+static inline void sdram_selfrefresh_enable(void)
+{
+        u32 lpr;
+
+        saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
+
+        lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
+        at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
+}
+
+#define sdram_selfrefresh_disable()     at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
+
+/*
+ * FIXME: The AT91SAM9263 has a second EBI controller which may have
+ *        additional SDRAM.  pm_slowclock.S will require a similar fix.
+ */
+
+#endif
+
+
+/*
+ * Show the reason for the previous system reset.
+ */
+#if defined(AT91_SHDWC)
+
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
+
+static void __init show_reset_status(void)
+{
+        static char reset[] __initdata = "reset";
+
+        static char general[] __initdata = "general";
+        static char wakeup[] __initdata = "wakeup";
+        static char watchdog[] __initdata = "watchdog";
+        static char software[] __initdata = "software";
+        static char user[] __initdata = "user";
+        static char unknown[] __initdata = "unknown";
+
+        static char signal[] __initdata = "signal";
+        static char rtc[] __initdata = "rtc";
+        static char rtt[] __initdata = "rtt";
+        static char restore[] __initdata = "power-restored";
+
+        char *reason, *r2 = reset;
+        u32 reset_type, wake_type;
+
+        reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
+        wake_type = at91_sys_read(AT91_SHDW_SR);
+
+        switch (reset_type) {
+        case AT91_RSTC_RSTTYP_GENERAL:
+                reason = general;
+                break;
+        case AT91_RSTC_RSTTYP_WAKEUP:
+                /* board-specific code enabled the wakeup sources */
+                reason = wakeup;
+
+                /* "wakeup signal" */
+                if (wake_type & AT91_SHDW_WAKEUP0)
+                        r2 = signal;
+                else {
+                        r2 = reason;
+                        if (wake_type & AT91_SHDW_RTTWK)        /* rtt wakeup */
+                                reason = rtt;
+                        else if (wake_type & AT91_SHDW_RTCWK)   /* rtc wakeup */
+                                reason = rtc;
+                        else if (wake_type == 0)        /* power-restored wakeup */
+                                reason = restore;
+                        else                            /* unknown wakeup */
+                                reason = unknown;
+                }
+                break;
+        case AT91_RSTC_RSTTYP_WATCHDOG:
+                reason = watchdog;
+                break;
+        case AT91_RSTC_RSTTYP_SOFTWARE:
+                reason = software;
+                break;
+        case AT91_RSTC_RSTTYP_USER:
+                reason = user;
+                break;
+        default:
+                reason = unknown;
+                break;
+        }
+        pr_info("AT91: Starting after %s %s\n", reason, r2);
+}
+#else
+static void __init show_reset_status(void) {}
+#endif
+
 
 static int at91_pm_valid_state(suspend_state_t state)
 {
@@ -125,6 +248,11 @@ EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
 
 static void (*slow_clock)(void);
 
+#ifdef CONFIG_AT91_SLOW_CLOCK
+extern void at91_slow_clock(void);
+extern u32 at91_slow_clock_sz;
+#endif
+
 
 static int at91_pm_enter(suspend_state_t state)
 {
@@ -158,11 +286,14 @@ static int at91_pm_enter(suspend_state_t state)
                          * turning off the main oscillator; reverse on wakeup.
                          */
                         if (slow_clock) {
+#ifdef CONFIG_AT91_SLOW_CLOCK
+                                /* copy slow_clock handler to SRAM, and call it */
+                                memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
+#endif
                                 slow_clock();
                                 break;
                         } else {
-                                /* DEVELOPMENT ONLY */
-                                pr_info("AT91: PM - no slow clock mode yet ...\n");
+                                pr_info("AT91: PM - no slow clock mode enabled ...\n");
                                 /* FALLTHROUGH leaving master clock alone */
                         }
 
@@ -175,13 +306,15 @@ static int at91_pm_enter(suspend_state_t state)
                 case PM_SUSPEND_STANDBY:
                         /*
                          * NOTE: the Wait-for-Interrupt instruction needs to be
-                         * in icache so the SDRAM stays in self-refresh mode until
-                         * the wakeup IRQ occurs.
+                         * in icache so no SDRAM accesses are needed until the
+                         * wakeup IRQ occurs and self-refresh is terminated.
                          */
                         asm("b 1f; .align 5; 1:");
                         asm("mcr p15, 0, r0, c7, c10, 4");      /* drain write buffer */
-                        at91_sys_write(AT91_SDRAMC_SRR, 1);     /* self-refresh mode */
-                        /* fall though to next state */
+                        sdram_selfrefresh_enable();
+                        asm("mcr p15, 0, r0, c7, c0, 4");       /* wait for interrupt */
+                        sdram_selfrefresh_disable();
+                        break;
 
                 case PM_SUSPEND_ON:
                         asm("mcr p15, 0, r0, c7, c0, 4");       /* wait for interrupt */
@@ -196,6 +329,7 @@ static int at91_pm_enter(suspend_state_t state)
                         at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));
 
 error:
+        sdram_selfrefresh_disable();
         target_state = PM_SUSPEND_ON;
         at91_irq_resume();
         at91_gpio_resume();
@@ -220,21 +354,20 @@ static struct platform_suspend_ops at91_pm_ops ={
 
 static int __init at91_pm_init(void)
 {
-        printk("AT91: Power Management\n");
-
-#ifdef CONFIG_AT91_PM_SLOW_CLOCK
-        /* REVISIT allocations of SRAM should be dynamically managed.
-         * FIQ handlers and other components will want SRAM/TCM too...
-         */
-        slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K));
-        memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz);
+#ifdef CONFIG_AT91_SLOW_CLOCK
+        slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
 #endif
 
-        /* Disable SDRAM low-power mode.  Cannot be used with self-refresh. */
+        pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
+
+#ifdef CONFIG_ARCH_AT91RM9200
+        /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
         at91_sys_write(AT91_SDRAMC_LPR, 0);
+#endif
 
         suspend_set_ops(&at91_pm_ops);
 
+        show_reset_status();
         return 0;
 }
 arch_initcall(at91_pm_init);
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index 0e2b641268ad..dbaae5f746a1 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -31,6 +31,8 @@ config ARCH_EDB7211
         bool "EDB7211"
         select ISA
         select ARCH_DISCONTIGMEM_ENABLE
+        select ARCH_SPARSEMEM_ENABLE
+        select ARCH_SELECT_MEMORY_MODEL
         help
           Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
           evaluation board.
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 0ecf99761feb..c1252ca9648e 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -1,7 +1,7 @@
 #
 # Makefile for the linux kernel.
 #
-obj-y                   := core.o clock.o
+obj-y                   := core.o clock.o gpio.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 91f6a07a51d5..8bc187240542 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -159,7 +159,7 @@ static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
 static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
 static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x5c };
 
-static void update_gpio_int_params(unsigned port)
+void ep93xx_gpio_update_int_params(unsigned port)
 {
         BUG_ON(port > 2);
 
@@ -175,98 +175,10 @@ static void update_gpio_int_params(unsigned port)
                 EP93XX_GPIO_REG(int_en_register_offset[port]));
 }
 
-/* Port ordering is: A B F D E C G H */
-static const u8 data_register_offset[8] = {
-        0x00, 0x04, 0x30, 0x0c, 0x20, 0x08, 0x38, 0x40,
-};
-
-static const u8 data_direction_register_offset[8] = {
-        0x10, 0x14, 0x34, 0x1c, 0x24, 0x18, 0x3c, 0x44,
-};
-
-#define GPIO_IN         0
-#define GPIO_OUT        1
-
-static void ep93xx_gpio_set_direction(unsigned line, int direction)
-{
-        unsigned int data_direction_register;
-        unsigned long flags;
-        unsigned char v;
-
-        data_direction_register =
-                EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
-
-        local_irq_save(flags);
-        if (direction == GPIO_OUT) {
-                if (line >= 0 && line <= EP93XX_GPIO_LINE_MAX_IRQ) {
-                        /* Port A/B/F */
-                        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
-                        update_gpio_int_params(line >> 3);
-                }
-
-                v = __raw_readb(data_direction_register);
-                v |= 1 << (line & 7);
-                __raw_writeb(v, data_direction_register);
-        } else if (direction == GPIO_IN) {
-                v = __raw_readb(data_direction_register);
-                v &= ~(1 << (line & 7));
-                __raw_writeb(v, data_direction_register);
-        }
-        local_irq_restore(flags);
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-        if (gpio > EP93XX_GPIO_LINE_MAX)
-                return -EINVAL;
-
-        ep93xx_gpio_set_direction(gpio, GPIO_IN);
-
-        return 0;
-}
-EXPORT_SYMBOL(gpio_direction_input);
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-        if (gpio > EP93XX_GPIO_LINE_MAX)
-                return -EINVAL;
-
-        gpio_set_value(gpio, value);
-        ep93xx_gpio_set_direction(gpio, GPIO_OUT);
-
-        return 0;
-}
-EXPORT_SYMBOL(gpio_direction_output);
-
-int gpio_get_value(unsigned gpio)
-{
-        unsigned int data_register;
-
-        data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
-
-        return !!(__raw_readb(data_register) & (1 << (gpio & 7)));
-}
-EXPORT_SYMBOL(gpio_get_value);
-
-void gpio_set_value(unsigned gpio, int value)
+void ep93xx_gpio_int_mask(unsigned line)
 {
-        unsigned int data_register;
-        unsigned long flags;
-        unsigned char v;
-
-        data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
-
-        local_irq_save(flags);
-        v = __raw_readb(data_register);
-        if (value)
-                v |= 1 << (gpio & 7);
-        else
-                v &= ~(1 << (gpio & 7));
-        __raw_writeb(v, data_register);
-        local_irq_restore(flags);
+        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
 }
-EXPORT_SYMBOL(gpio_set_value);
-
 
 /*************************************************************************
  * EP93xx IRQ handling
@@ -316,7 +228,7 @@ static void ep93xx_gpio_irq_ack(unsigned int irq)
 
         if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
-                update_gpio_int_params(port);
+                ep93xx_gpio_update_int_params(port);
         }
 
         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
@@ -332,7 +244,7 @@ static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
 
         gpio_int_unmasked[port] &= ~port_mask;
-        update_gpio_int_params(port);
+        ep93xx_gpio_update_int_params(port);
 
         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
 }
@@ -343,7 +255,7 @@ static void ep93xx_gpio_irq_mask(unsigned int irq)
         int port = line >> 3;
 
         gpio_int_unmasked[port] &= ~(1 << (line & 7));
-        update_gpio_int_params(port);
+        ep93xx_gpio_update_int_params(port);
 }
 
 static void ep93xx_gpio_irq_unmask(unsigned int irq)
@@ -352,7 +264,7 @@ static void ep93xx_gpio_irq_unmask(unsigned int irq)
         int port = line >> 3;
 
         gpio_int_unmasked[port] |= 1 << (line & 7);
-        update_gpio_int_params(port);
+        ep93xx_gpio_update_int_params(port);
 }
 
 
@@ -368,7 +280,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
         const int port = gpio >> 3;
         const int port_mask = 1 << (gpio & 7);
 
-        ep93xx_gpio_set_direction(gpio, GPIO_IN);
+        gpio_direction_output(gpio, gpio_get_value(gpio));
 
         switch (type) {
         case IRQT_RISING:
@@ -411,7 +323,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
         desc->status &= ~IRQ_TYPE_SENSE_MASK;
         desc->status |= type & IRQ_TYPE_SENSE_MASK;
 
-        update_gpio_int_params(port);
+        ep93xx_gpio_update_int_params(port);
 
         return 0;
 }
@@ -549,6 +461,7 @@ static struct platform_device ep93xx_ohci_device = {
         .resource       = ep93xx_ohci_resources,
 };
 
+extern void ep93xx_gpio_init(void);
 
 void __init ep93xx_init_devices(void)
 {
@@ -562,6 +475,8 @@ void __init ep93xx_init_devices(void)
         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
         __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
 
+        ep93xx_gpio_init();
+
         amba_device_register(&uart1_device, &iomem_resource);
         amba_device_register(&uart2_device, &iomem_resource);
         amba_device_register(&uart3_device, &iomem_resource);
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
new file mode 100644
index 000000000000..dc2e4c00d989
--- /dev/null
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -0,0 +1,158 @@
+/*
+ * linux/arch/arm/mach-ep93xx/gpio.c
+ *
+ * Generic EP93xx GPIO handling
+ *
+ * Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * Based on code originally from:
+ *  linux/arch/arm/mach-ep93xx/core.c
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/seq_file.h>
+
+#include <asm/arch/ep93xx-regs.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+struct ep93xx_gpio_chip {
+        struct gpio_chip        chip;
+
+        unsigned int            data_reg;
+        unsigned int            data_dir_reg;
+};
+
+#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
+
+/* From core.c */
+extern void ep93xx_gpio_int_mask(unsigned line);
+extern void ep93xx_gpio_update_int_params(unsigned port);
+
+static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+        unsigned long flags;
+        u8 v;
+
+        local_irq_save(flags);
+        v = __raw_readb(ep93xx_chip->data_dir_reg);
+        v &= ~(1 << offset);
+        __raw_writeb(v, ep93xx_chip->data_dir_reg);
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
+                                        unsigned offset, int val)
+{
+        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+        unsigned long flags;
+        int line;
+        u8 v;
+
+        local_irq_save(flags);
+
+        /* Set the value */
+        v = __raw_readb(ep93xx_chip->data_reg);
+        if (val)
+                v |= (1 << offset);
+        else
+                v &= ~(1 << offset);
+        __raw_writeb(v, ep93xx_chip->data_reg);
+
+        /* Drive as an output */
+        line = chip->base + offset;
+        if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
+                /* Ports A/B/F */
+                ep93xx_gpio_int_mask(line);
+                ep93xx_gpio_update_int_params(line >> 3);
+        }
+
+        v = __raw_readb(ep93xx_chip->data_dir_reg);
+        v |= (1 << offset);
+        __raw_writeb(v, ep93xx_chip->data_dir_reg);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+
+        return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
+}
+
+static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+        unsigned long flags;
+        u8 v;
+
+        local_irq_save(flags);
+        v = __raw_readb(ep93xx_chip->data_reg);
+        if (val)
+                v |= (1 << offset);
+        else
+                v &= ~(1 << offset);
+        __raw_writeb(v, ep93xx_chip->data_reg);
+        local_irq_restore(flags);
+}
+
+static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
+        u8 data_reg, data_dir_reg;
+        int i;
+
+        data_reg = __raw_readb(ep93xx_chip->data_reg);
+        data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
+
+        for (i = 0; i < chip->ngpio; i++)
+                seq_printf(s, "GPIO %s%d: %s %s\n", chip->label, i,
+                           (data_reg & (1 << i)) ? "set" : "clear",
+                           (data_dir_reg & (1 << i)) ? "out" : "in");
+}
+
+#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio)                      \
+        {                                                               \
+                .chip = {                                               \
+                        .label            = name,                       \
+                        .direction_input  = ep93xx_gpio_direction_input, \
+                        .direction_output = ep93xx_gpio_direction_output, \
+                        .get              = ep93xx_gpio_get,            \
+                        .set              = ep93xx_gpio_set,            \
+                        .dbg_show         = ep93xx_gpio_dbg_show,       \
+                        .base             = base_gpio,                  \
+                        .ngpio            = 8,                          \
+                },                                                      \
+                .data_reg       = EP93XX_GPIO_REG(dr),                  \
+                .data_dir_reg   = EP93XX_GPIO_REG(ddr),                 \
+        }
+
+static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
+        EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
+        EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
+        EP93XX_GPIO_BANK("C", 0x30, 0x34, 40),
+        EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
+        EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
+        EP93XX_GPIO_BANK("F", 0x08, 0x18, 16),
+        EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
+        EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
+};
+
+void __init ep93xx_gpio_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++)
+                gpiochip_add(&ep93xx_gpio_banks[i].chip);
+}
diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig
index dbe07c9472ed..5e8c6f7dfabb 100644
--- a/arch/arm/mach-iop32x/Kconfig
+++ b/arch/arm/mach-iop32x/Kconfig
@@ -34,14 +34,6 @@ config MACH_N2100
           Say Y here if you want to run your kernel on the Thecus n2100
           NAS appliance.
 
-config IOP3XX_ATU
-        bool "Enable the PCI Controller"
-        default y
-        help
-          Say Y here if you want the IOP to initialize its PCI Controller.
-          Say N if the IOP is an add in card, the host system owns the PCI
-          bus in this case.
-
 config MACH_EM7210
         bool "Enable support for the Lanner EM7210"
         help
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 98cfa1cd6bdb..4a89823bcebb 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -178,10 +178,9 @@ static struct hw_pci iq31244_pci __initdata = {
 
 static int __init iq31244_pci_init(void)
 {
-        if (is_ep80219()) {
-                if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
-                        pci_common_init(&ep80219_pci);
-        } else if (machine_is_iq31244()) {
+        if (is_ep80219())
+                pci_common_init(&ep80219_pci);
+        else if (machine_is_iq31244()) {
                 if (is_80219()) {
                         printk("note: iq31244 board type has been selected\n");
                         printk("note: to select ep80219 operation:\n");
@@ -190,9 +189,7 @@ static int __init iq31244_pci_init(void)
                         printk("\t2/ update boot loader to pass"
                                 " the ep80219 id: %d\n", MACH_TYPE_EP80219);
                 }
-
-                if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE)
-                        pci_common_init(&iq31244_pci);
+                pci_common_init(&iq31244_pci);
         }
 
         return 0;
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 18ad29f213b2..1da3c911edd3 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -106,7 +106,7 @@ static struct hw_pci iq80321_pci __initdata = {
         .swizzle        = pci_std_swizzle,
         .nr_controllers = 1,
         .setup          = iop3xx_pci_setup,
-        .preinit        = iop3xx_pci_preinit,
+        .preinit        = iop3xx_pci_preinit_cond,
         .scan           = iop3xx_pci_scan_bus,
         .map_irq        = iq80321_pci_map_irq,
 };
diff --git a/arch/arm/mach-iop33x/Kconfig b/arch/arm/mach-iop33x/Kconfig
index 45598e096898..9aa016bb18f9 100644
--- a/arch/arm/mach-iop33x/Kconfig
+++ b/arch/arm/mach-iop33x/Kconfig
@@ -16,14 +16,6 @@ config MACH_IQ80332
           Say Y here if you want to run your kernel on the Intel IQ80332
           evaluation kit for the IOP332 chipset.
 
-config IOP3XX_ATU
-        bool "Enable the PCI Controller"
-        default y
-        help
-          Say Y here if you want the IOP to initialize its PCI Controller.
-          Say N if the IOP is an add in card, the host system owns the PCI
-          bus in this case.
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 433188ebff2a..de39fd778579 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -89,7 +89,7 @@ static struct hw_pci iq80331_pci __initdata = {
         .swizzle        = pci_std_swizzle,
         .nr_controllers = 1,
         .setup          = iop3xx_pci_setup,
-        .preinit        = iop3xx_pci_preinit,
+        .preinit        = iop3xx_pci_preinit_cond,
         .scan           = iop3xx_pci_scan_bus,
         .map_irq        = iq80331_pci_map_irq,
 };
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 416c09564cc6..4904fd78445f 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -89,7 +89,7 @@ static struct hw_pci iq80332_pci __initdata = {
         .swizzle        = pci_std_swizzle,
         .nr_controllers = 1,
         .setup          = iop3xx_pci_setup,
-        .preinit        = iop3xx_pci_preinit,
+        .preinit        = iop3xx_pci_preinit_cond,
         .scan           = iop3xx_pci_scan_bus,
         .map_irq        = iq80332_pci_map_irq,
 };
diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile
index 730a3af12c98..ade42b73afbb 100644
--- a/arch/arm/mach-ks8695/Makefile
+++ b/arch/arm/mach-ks8695/Makefile
@@ -11,5 +11,8 @@ obj-				:=
 # PCI support is optional
 obj-$(CONFIG_PCI)               += pci.o
 
+# LEDs
+obj-$(CONFIG_LEDS)              += leds.o
+
 # Board-specific support
 obj-$(CONFIG_MACH_KS8695)       += board-micrel.o
diff --git a/arch/arm/mach-ks8695/devices.c b/arch/arm/mach-ks8695/devices.c
index 386593f8ac65..3db2ec61d06f 100644
--- a/arch/arm/mach-ks8695/devices.c
+++ b/arch/arm/mach-ks8695/devices.c
@@ -176,6 +176,27 @@ static void __init ks8695_add_device_watchdog(void) {}
 #endif
 
 
+/* --------------------------------------------------------------------
+ *  LEDs
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_LEDS)
+short ks8695_leds_cpu = -1;
+short ks8695_leds_timer = -1;
+
+void __init ks8695_init_leds(u8 cpu_led, u8 timer_led)
+{
+        /* Enable GPIO to access the LEDs */
+        gpio_direction_output(cpu_led, 1);
+        gpio_direction_output(timer_led, 1);
+
+        ks8695_leds_cpu   = cpu_led;
+        ks8695_leds_timer = timer_led;
+}
+#else
+void __init ks8695_init_leds(u8 cpu_led, u8 timer_led) {}
+#endif
+
 /* -------------------------------------------------------------------- */
 
 /*
diff --git a/arch/arm/mach-ks8695/leds.c b/arch/arm/mach-ks8695/leds.c
new file mode 100644
index 000000000000..d61762ae50d8
--- /dev/null
+++ b/arch/arm/mach-ks8695/leds.c
@@ -0,0 +1,94 @@
+/*
+ * LED driver for KS8695-based boards.
+ *
+ * Copyright (C) Andrew Victor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <asm/mach-types.h>
+#include <asm/leds.h>
+#include <asm/arch/devices.h>
+#include <asm/arch/gpio.h>
+
+
+static inline void ks8695_led_on(unsigned int led)
+{
+        gpio_set_value(led, 0);
+}
+
+static inline void ks8695_led_off(unsigned int led)
+{
+        gpio_set_value(led, 1);
+}
+
+static inline void ks8695_led_toggle(unsigned int led)
+{
+        unsigned long is_off = gpio_get_value(led);
+        if (is_off)
+                ks8695_led_on(led);
+        else
+                ks8695_led_off(led);
+}
+
+
+/*
+ * Handle LED events.
+ */
+static void ks8695_leds_event(led_event_t evt)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        switch(evt) {
+        case led_start:         /* System startup */
+                ks8695_led_on(ks8695_leds_cpu);
+                break;
+
+        case led_stop:          /* System stop / suspend */
+                ks8695_led_off(ks8695_leds_cpu);
+                break;
+
+#ifdef CONFIG_LEDS_TIMER
+        case led_timer:         /* Every 50 timer ticks */
+                ks8695_led_toggle(ks8695_leds_timer);
+                break;
+#endif
+
+#ifdef CONFIG_LEDS_CPU
+        case led_idle_start:    /* Entering idle state */
+                ks8695_led_off(ks8695_leds_cpu);
+                break;
+
+        case led_idle_end:      /* Exit idle state */
+                ks8695_led_on(ks8695_leds_cpu);
+                break;
+#endif
+
+        default:
+                break;
+        }
+
+        local_irq_restore(flags);
+}
+
+
+static int __init leds_init(void)
+{
+        if ((ks8695_leds_timer == -1) || (ks8695_leds_cpu == -1))
+                return -ENODEV;
+
+        leds_event = ks8695_leds_event;
+
+        leds_event(led_start);
+        return 0;
+}
+
+__initcall(leds_init);
diff --git a/arch/arm/mach-ns9xxx/Kconfig b/arch/arm/mach-ns9xxx/Kconfig
index 8584ed107991..dd0cd5ac4b8b 100644
--- a/arch/arm/mach-ns9xxx/Kconfig
+++ b/arch/arm/mach-ns9xxx/Kconfig
@@ -2,9 +2,26 @@ if ARCH_NS9XXX
 
 menu "NS9xxx Implementations"
 
+config NS9XXX_HAVE_SERIAL8250
+        bool
+
+config PROCESSOR_NS9360
+        bool
+
+config MODULE_CC9P9360
+        bool
+        select PROCESSOR_NS9360
+
+config BOARD_A9M9750DEV
+        select NS9XXX_HAVE_SERIAL8250
+        bool
+
+config BOARD_JSCC9P9360
+        bool
+
 config MACH_CC9P9360DEV
         bool "ConnectCore 9P 9360 on an A9M9750 Devboard"
-        select PROCESSOR_NS9360
+        select MODULE_CC9P9360
         select BOARD_A9M9750DEV
         help
           Say Y here if you are using the Digi ConnectCore 9P 9360
@@ -12,21 +29,12 @@ config MACH_CC9P9360DEV
 
 config MACH_CC9P9360JS
         bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard"
-        select PROCESSOR_NS9360
+        select MODULE_CC9P9360
         select BOARD_JSCC9P9360
         help
           Say Y here if you are using the Digi ConnectCore 9P 9360
           on an JSCC9P9360 Development Board.
 
-config PROCESSOR_NS9360
-        bool
-
-config BOARD_A9M9750DEV
-        bool
-
-config BOARD_JSCC9P9360
-        bool
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile
index 6fb82b855a55..41efaf9ad50b 100644
--- a/arch/arm/mach-ns9xxx/Makefile
+++ b/arch/arm/mach-ns9xxx/Makefile
@@ -1,7 +1,12 @@
-obj-y := irq.o time.o generic.o gpio.o
+obj-y := clock.o generic.o gpio.o irq.o
 
 obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o
 obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o
 
+obj-$(CONFIG_PROCESSOR_NS9360) += gpio-ns9360.o processor-ns9360.o time-ns9360.o
+
 obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o
 obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o
+
+# platform devices
+obj-$(CONFIG_NS9XXX_HAVE_SERIAL8250) += plat-serial8250.o
diff --git a/arch/arm/mach-ns9xxx/Makefile.boot b/arch/arm/mach-ns9xxx/Makefile.boot
index 75ed64e90fa4..54654919229b 100644
--- a/arch/arm/mach-ns9xxx/Makefile.boot
+++ b/arch/arm/mach-ns9xxx/Makefile.boot
@@ -1,2 +1,2 @@
-zreladdr-y := 0x108000
+zreladdr-y := 0x8000
 params_phys-y := 0x100
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
index 0f65177f9e5f..a494b71c0195 100644
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -8,15 +8,14 @@
  * under the terms of the GNU General Public License version 2 as published by
  * the Free Software Foundation.
  */
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
 #include <linux/irq.h>
 
 #include <asm/mach/map.h>
 #include <asm/gpio.h>
 
 #include <asm/arch-ns9xxx/board.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
 #include <asm/arch-ns9xxx/regs-mem.h>
 #include <asm/arch-ns9xxx/regs-bbu.h>
 #include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
@@ -105,9 +104,9 @@ void __init board_a9m9750dev_init_irq(void)
         int i;
 
         if (gpio_request(11, "board a9m9750dev extirq2") == 0)
-                ns9xxx_gpio_configure(11, 0, 1);
+                ns9360_gpio_configure(11, 0, 1);
         else
-                printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_EXT2\n",
+                printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n",
                                 __func__);
 
         for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
@@ -116,69 +115,16 @@ void __init board_a9m9750dev_init_irq(void)
                 set_irq_flags(i, IRQF_VALID);
         }
 
-        /* IRQ_EXT2: level sensitive + active low */
+        /* IRQ_NS9XXX_EXT2: level sensitive + active low */
         eic = __raw_readl(SYS_EIC(2));
         REGSET(eic, SYS_EIC, PLTY, AL);
         REGSET(eic, SYS_EIC, LVEDG, LEVEL);
         __raw_writel(eic, SYS_EIC(2));
 
-        set_irq_chained_handler(IRQ_EXT2,
+        set_irq_chained_handler(IRQ_NS9XXX_EXT2,
                         a9m9750dev_fpga_demux_handler);
 }
 
-static struct plat_serial8250_port board_a9m9750dev_serial8250_port[] = {
-        {
-                .iobase         = FPGA_UARTA_BASE,
-                .membase        = (unsigned char*)FPGA_UARTA_BASE,
-                .mapbase        = FPGA_UARTA_BASE,
-                .irq            = IRQ_FPGA_UARTA,
-                .iotype         = UPIO_MEM,
-                .uartclk        = 18432000,
-                .regshift       = 0,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
-        }, {
-                .iobase         = FPGA_UARTB_BASE,
-                .membase        = (unsigned char*)FPGA_UARTB_BASE,
-                .mapbase        = FPGA_UARTB_BASE,
-                .irq            = IRQ_FPGA_UARTB,
-                .iotype         = UPIO_MEM,
-                .uartclk        = 18432000,
-                .regshift       = 0,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
-        }, {
-                .iobase         = FPGA_UARTC_BASE,
-                .membase        = (unsigned char*)FPGA_UARTC_BASE,
-                .mapbase        = FPGA_UARTC_BASE,
-                .irq            = IRQ_FPGA_UARTC,
-                .iotype         = UPIO_MEM,
-                .uartclk        = 18432000,
-                .regshift       = 0,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
-        }, {
-                .iobase         = FPGA_UARTD_BASE,
-                .membase        = (unsigned char*)FPGA_UARTD_BASE,
-                .mapbase        = FPGA_UARTD_BASE,
-                .irq            = IRQ_FPGA_UARTD,
-                .iotype         = UPIO_MEM,
-                .uartclk        = 18432000,
-                .regshift       = 0,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ,
-        }, {
-                /* end marker */
-        },
-};
-
-static struct platform_device board_a9m9750dev_serial_device = {
-        .name = "serial8250",
-        .dev = {
-                .platform_data = board_a9m9750dev_serial8250_port,
-        },
-};
-
-static struct platform_device *board_a9m9750dev_devices[] __initdata = {
-        &board_a9m9750dev_serial_device,
-};
-
 void __init board_a9m9750dev_init_machine(void)
 {
         u32 reg;
@@ -210,7 +156,4 @@ void __init board_a9m9750dev_init_machine(void)
         __raw_writel(0x2, MEM_SMOED(0));
         __raw_writel(0x6, MEM_SMRD(0));
         __raw_writel(0x6, MEM_SMWD(0));
-
-        platform_add_devices(board_a9m9750dev_devices,
-                        ARRAY_SIZE(board_a9m9750dev_devices));
 }
diff --git a/arch/arm/mach-ns9xxx/clock.c b/arch/arm/mach-ns9xxx/clock.c
new file mode 100644
index 000000000000..f8639161068f
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/clock.c
@@ -0,0 +1,215 @@
+/*
+ * arch/arm/mach-ns9xxx/clock.c
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <asm/semaphore.h>
+#include "clock.h"
+
+static LIST_HEAD(clocks);
+static DEFINE_SPINLOCK(clk_lock);
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        struct clk *p, *ret = NULL, *retgen = NULL;
+        unsigned long flags;
+        int idno;
+
+        if (dev == NULL || dev->bus != &platform_bus_type)
+                idno = -1;
+        else
+                idno = to_platform_device(dev)->id;
+
+        spin_lock_irqsave(&clk_lock, flags);
+        list_for_each_entry(p, &clocks, node) {
+                if (strcmp(id, p->name) == 0) {
+                        if (p->id == idno) {
+                                if (!try_module_get(p->owner))
+                                        continue;
+                                ret = p;
+                                break;
+                        } else if (p->id == -1)
+                                /* remember match with id == -1 in case there is
+                                 * no clock for idno */
+                                retgen = p;
+                }
+        }
+
+        if (!ret && retgen && try_module_get(retgen->owner))
+                ret = retgen;
+
+        if (ret)
+                ++ret->refcount;
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return ret ? ret : ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+void clk_put(struct clk *clk)
+{
+        module_put(clk->owner);
+        --clk->refcount;
+}
+EXPORT_SYMBOL(clk_put);
+
+static int clk_enable_unlocked(struct clk *clk)
+{
+        int ret = 0;
+        if (clk->parent) {
+                ret = clk_enable_unlocked(clk->parent);
+                if (ret)
+                        return ret;
+        }
+
+        if (clk->usage++ == 0 && clk->endisable)
+                ret = clk->endisable(clk, 1);
+
+        return ret;
+}
+
+int clk_enable(struct clk *clk)
+{
+        int ret;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clk_lock, flags);
+
+        ret = clk_enable_unlocked(clk);
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+static void clk_disable_unlocked(struct clk *clk)
+{
+        if (--clk->usage == 0 && clk->endisable)
+                clk->endisable(clk, 0);
+
+        if (clk->parent)
+                clk_disable_unlocked(clk->parent);
+}
+
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clk_lock, flags);
+
+        clk_disable_unlocked(clk);
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (clk->get_rate)
+                return clk->get_rate(clk);
+
+        if (clk->rate)
+                return clk->rate;
+
+        if (clk->parent)
+                return clk_get_rate(clk->parent);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+int clk_register(struct clk *clk)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clk_lock, flags);
+
+        list_add(&clk->node, &clocks);
+
+        if (clk->parent)
+                ++clk->parent->refcount;
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return 0;
+}
+
+int clk_unregister(struct clk *clk)
+{
+        int ret = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clk_lock, flags);
+
+        if (clk->usage || clk->refcount)
+                ret = -EBUSY;
+        else
+                list_del(&clk->node);
+
+        if (clk->parent)
+                --clk->parent->refcount;
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return ret;
+}
+
+#if defined CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static int clk_debugfs_show(struct seq_file *s, void *null)
+{
+        unsigned long flags;
+        struct clk *p;
+
+        spin_lock_irqsave(&clk_lock, flags);
+
+        list_for_each_entry(p, &clocks, node)
+                seq_printf(s, "%s.%d: usage=%lu refcount=%lu rate=%lu\n",
+                                p->name, p->id, p->usage, p->refcount,
+                                p->usage ? clk_get_rate(p) : 0);
+
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return 0;
+}
+
+static int clk_debugfs_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, clk_debugfs_show, NULL);
+}
+
+static struct file_operations clk_debugfs_operations = {
+        .open = clk_debugfs_open,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+};
+
+static int __init clk_debugfs_init(void)
+{
+        struct dentry *dentry;
+
+        dentry = debugfs_create_file("clk", S_IFREG | S_IRUGO, NULL, NULL,
+                        &clk_debugfs_operations);
+        return IS_ERR(dentry) ? PTR_ERR(dentry) : 0;
+}
+subsys_initcall(clk_debugfs_init);
+
+#endif /* if defined CONFIG_DEBUG_FS */
diff --git a/arch/arm/mach-ns9xxx/clock.h b/arch/arm/mach-ns9xxx/clock.h
new file mode 100644
index 000000000000..b86c30dd79eb
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/clock.h
@@ -0,0 +1,35 @@
+/*
+ * arch/arm/mach-ns9xxx/clock.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __NS9XXX_CLOCK_H
+#define __NS9XXX_CLOCK_H
+
+#include <linux/list.h>
+
+struct clk {
+        struct module *owner;
+        const char *name;
+        int id;
+
+        struct clk *parent;
+
+        unsigned long rate;
+        int (*endisable)(struct clk *, int enable);
+        unsigned long (*get_rate)(struct clk *);
+
+        struct list_head node;
+        unsigned long refcount;
+        unsigned long usage;
+};
+
+int clk_register(struct clk *clk);
+int clk_unregister(struct clk *clk);
+
+#endif /* ifndef __NS9XXX_CLOCK_H */
diff --git a/arch/arm/mach-ns9xxx/generic.c b/arch/arm/mach-ns9xxx/generic.c
index d742c921e34d..1e0f467879cc 100644
--- a/arch/arm/mach-ns9xxx/generic.c
+++ b/arch/arm/mach-ns9xxx/generic.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-ns9xxx/generic.c
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -11,34 +11,9 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <asm/memory.h>
-#include <asm/page.h>
-#include <asm/mach-types.h>
-#include <asm/mach/map.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
-#include <asm/arch-ns9xxx/regs-mem.h>
-#include <asm/arch-ns9xxx/board.h>
 
 #include "generic.h"
 
-static struct map_desc standard_io_desc[] __initdata = {
-        { /* BBus */
-                .virtual = io_p2v(0x90000000),
-                .pfn = __phys_to_pfn(0x90000000),
-                .length = 0x00700000,
-                .type = MT_DEVICE,
-        }, { /* AHB */
-                .virtual = io_p2v(0xa0100000),
-                .pfn = __phys_to_pfn(0xa0100000),
-                .length = 0x00900000,
-                .type = MT_DEVICE,
-        },
-};
-
-void __init ns9xxx_map_io(void)
-{
-        iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
-}
-
 void __init ns9xxx_init_machine(void)
 {
 }
diff --git a/arch/arm/mach-ns9xxx/generic.h b/arch/arm/mach-ns9xxx/generic.h
index 687e291773f4..82493191aad6 100644
--- a/arch/arm/mach-ns9xxx/generic.h
+++ b/arch/arm/mach-ns9xxx/generic.h
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-ns9xxx/generic.h
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -13,7 +13,4 @@
 #include <linux/init.h>
 
 void __init ns9xxx_init_irq(void);
-void __init ns9xxx_map_io(void);
 void __init ns9xxx_init_machine(void);
-
-extern struct sys_timer ns9xxx_timer;
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.c b/arch/arm/mach-ns9xxx/gpio-ns9360.c
new file mode 100644
index 000000000000..cabfb879dda9
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/gpio-ns9360.c
@@ -0,0 +1,118 @@
+/*
+ * arch/arm/mach-ns9xxx/gpio-ns9360.c
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/bug.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/arch-ns9xxx/regs-bbu.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+
+#include "gpio-ns9360.h"
+
+static inline int ns9360_valid_gpio(unsigned gpio)
+{
+        return gpio <= 72;
+}
+
+static inline void __iomem *ns9360_gpio_get_gconfaddr(unsigned gpio)
+{
+        if (gpio < 56)
+                return BBU_GCONFb1(gpio / 8);
+        else
+                /*
+                 * this could be optimised away on
+                 * ns9750 only builds, but it isn't ...
+                 */
+                return BBU_GCONFb2((gpio - 56) / 8);
+}
+
+static inline void __iomem *ns9360_gpio_get_gctrladdr(unsigned gpio)
+{
+        if (gpio < 32)
+                return BBU_GCTRL1;
+        else if (gpio < 64)
+                return BBU_GCTRL2;
+        else
+                /* this could be optimised away on ns9750 only builds */
+                return BBU_GCTRL3;
+}
+
+static inline void __iomem *ns9360_gpio_get_gstataddr(unsigned gpio)
+{
+        if (gpio < 32)
+                return BBU_GSTAT1;
+        else if (gpio < 64)
+                return BBU_GSTAT2;
+        else
+                /* this could be optimised away on ns9750 only builds */
+                return BBU_GSTAT3;
+}
+
+/*
+ * each gpio can serve for 4 different purposes [0..3].  These are called
+ * "functions" and passed in the parameter func.  Functions 0-2 are always some
+ * special things, function 3 is GPIO.  If func == 3 dir specifies input or
+ * output, and with inv you can enable an inverter (independent of func).
+ */
+int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func)
+{
+        void __iomem *conf = ns9360_gpio_get_gconfaddr(gpio);
+        u32 confval;
+
+        confval = __raw_readl(conf);
+        REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir);
+        REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv);
+        REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func);
+        __raw_writel(confval, conf);
+
+        return 0;
+}
+
+int ns9360_gpio_configure(unsigned gpio, int inv, int func)
+{
+        if (likely(ns9360_valid_gpio(gpio))) {
+                if (func == 3) {
+                        printk(KERN_WARNING "use gpio_direction_input "
+                                        "or gpio_direction_output\n");
+                        return -EINVAL;
+                } else
+                        return __ns9360_gpio_configure(gpio, 0, inv, func);
+        } else
+                return -EINVAL;
+}
+EXPORT_SYMBOL(ns9360_gpio_configure);
+
+int ns9360_gpio_get_value(unsigned gpio)
+{
+        void __iomem *stat = ns9360_gpio_get_gstataddr(gpio);
+        int ret;
+
+        ret = 1 & (__raw_readl(stat) >> (gpio & 31));
+
+        return ret;
+}
+
+void ns9360_gpio_set_value(unsigned gpio, int value)
+{
+        void __iomem *ctrl = ns9360_gpio_get_gctrladdr(gpio);
+        u32 ctrlval;
+
+        ctrlval = __raw_readl(ctrl);
+
+        if (value)
+                ctrlval |= 1 << (gpio & 31);
+        else
+                ctrlval &= ~(1 << (gpio & 31));
+
+        __raw_writel(ctrlval, ctrl);
+}
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.h b/arch/arm/mach-ns9xxx/gpio-ns9360.h
new file mode 100644
index 000000000000..131cd1715caa
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/gpio-ns9360.h
@@ -0,0 +1,13 @@
+/*
+ * arch/arm/mach-ns9xxx/gpio-ns9360.h
+ *
+ * Copyright (C) 2006,2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func);
+int ns9360_gpio_get_value(unsigned gpio);
+void ns9360_gpio_set_value(unsigned gpio, int value);
diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c
index 5286e9fc1d30..b3c963b0c8f5 100644
--- a/arch/arm/mach-ns9xxx/gpio.c
+++ b/arch/arm/mach-ns9xxx/gpio.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-ns9xxx/gpio.c
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -15,12 +15,13 @@
 
 #include <asm/arch-ns9xxx/gpio.h>
 #include <asm/arch-ns9xxx/processor.h>
-#include <asm/arch-ns9xxx/regs-bbu.h>
-#include <asm/io.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
 #include <asm/bug.h>
 #include <asm/types.h>
 #include <asm/bitops.h>
 
+#include "gpio-ns9360.h"
+
 #if defined(CONFIG_PROCESSOR_NS9360)
 #define GPIO_MAX 72
 #elif defined(CONFIG_PROCESSOR_NS9750)
@@ -45,41 +46,10 @@ static inline int ns9xxx_valid_gpio(unsigned gpio)
                 return gpio <= 49;
         else
 #endif
+        {
                 BUG();
-}
-
-static inline void __iomem *ns9xxx_gpio_get_gconfaddr(unsigned gpio)
-{
-        if (gpio < 56)
-                return BBU_GCONFb1(gpio / 8);
-        else
-                /*
-                 * this could be optimised away on
-                 * ns9750 only builds, but it isn't ...
-                 */
-                return BBU_GCONFb2((gpio - 56) / 8);
-}
-
-static inline void __iomem *ns9xxx_gpio_get_gctrladdr(unsigned gpio)
-{
-        if (gpio < 32)
-                return BBU_GCTRL1;
-        else if (gpio < 64)
-                return BBU_GCTRL2;
-        else
-                /* this could be optimised away on ns9750 only builds */
-                return BBU_GCTRL3;
-}
-
-static inline void __iomem *ns9xxx_gpio_get_gstataddr(unsigned gpio)
-{
-        if (gpio < 32)
-                return BBU_GSTAT1;
-        else if (gpio < 64)
-                return BBU_GSTAT2;
-        else
-                /* this could be optimised away on ns9750 only builds */
-                return BBU_GSTAT3;
+                return 0;
+        }
 }
 
 int gpio_request(unsigned gpio, const char *label)
@@ -98,49 +68,24 @@ void gpio_free(unsigned gpio)
 }
 EXPORT_SYMBOL(gpio_free);
 
-/*
- * each gpio can serve for 4 different purposes [0..3].  These are called
- * "functions" and passed in the parameter func.  Functions 0-2 are always some
- * special things, function 3 is GPIO.  If func == 3 dir specifies input or
- * output, and with inv you can enable an inverter (independent of func).
- */
-static int __ns9xxx_gpio_configure(unsigned gpio, int dir, int inv, int func)
+int gpio_direction_input(unsigned gpio)
 {
-        void __iomem *conf = ns9xxx_gpio_get_gconfaddr(gpio);
-        u32 confval;
-        unsigned long flags;
-
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        confval = __raw_readl(conf);
-        REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir);
-        REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv);
-        REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func);
-        __raw_writel(confval, conf);
+        if (likely(ns9xxx_valid_gpio(gpio))) {
+                int ret = -EINVAL;
+                unsigned long flags;
 
-        spin_unlock_irqrestore(&gpio_lock, flags);
+                spin_lock_irqsave(&gpio_lock, flags);
+#if defined(CONFIG_PROCESSOR_NS9360)
+                if (processor_is_ns9360())
+                        ret = __ns9360_gpio_configure(gpio, 0, 0, 3);
+                else
+#endif
+                        BUG();
 
-        return 0;
-}
+                spin_unlock_irqrestore(&gpio_lock, flags);
 
-int ns9xxx_gpio_configure(unsigned gpio, int inv, int func)
-{
-        if (likely(ns9xxx_valid_gpio(gpio))) {
-                if (func == 3) {
-                        printk(KERN_WARNING "use gpio_direction_input "
-                                        "or gpio_direction_output\n");
-                        return -EINVAL;
-                } else
-                        return __ns9xxx_gpio_configure(gpio, 0, inv, func);
-        } else
-                return -EINVAL;
-}
-EXPORT_SYMBOL(ns9xxx_gpio_configure);
+                return ret;
 
-int gpio_direction_input(unsigned gpio)
-{
-        if (likely(ns9xxx_valid_gpio(gpio))) {
-                return __ns9xxx_gpio_configure(gpio, 0, 0, 3);
         } else
                 return -EINVAL;
 }
@@ -149,9 +94,22 @@ EXPORT_SYMBOL(gpio_direction_input);
 int gpio_direction_output(unsigned gpio, int value)
 {
         if (likely(ns9xxx_valid_gpio(gpio))) {
+                int ret = -EINVAL;
+                unsigned long flags;
+
                 gpio_set_value(gpio, value);
 
-                return __ns9xxx_gpio_configure(gpio, 1, 0, 3);
+                spin_lock_irqsave(&gpio_lock, flags);
+#if defined(CONFIG_PROCESSOR_NS9360)
+                if (processor_is_ns9360())
+                        ret = __ns9360_gpio_configure(gpio, 1, 0, 3);
+                else
+#endif
+                        BUG();
+
+                spin_unlock_irqrestore(&gpio_lock, flags);
+
+                return ret;
         } else
                 return -EINVAL;
 }
@@ -159,31 +117,28 @@ EXPORT_SYMBOL(gpio_direction_output);
 
 int gpio_get_value(unsigned gpio)
 {
-        void __iomem *stat = ns9xxx_gpio_get_gstataddr(gpio);
-        int ret;
-
-        ret = 1 & (__raw_readl(stat) >> (gpio & 31));
-
-        return ret;
+#if defined(CONFIG_PROCESSOR_NS9360)
+        if (processor_is_ns9360())
+                return ns9360_gpio_get_value(gpio);
+        else
+#endif
+        {
+                BUG();
+                return -EINVAL;
+        }
 }
 EXPORT_SYMBOL(gpio_get_value);
 
 void gpio_set_value(unsigned gpio, int value)
 {
-        void __iomem *ctrl = ns9xxx_gpio_get_gctrladdr(gpio);
-        u32 ctrlval;
         unsigned long flags;
-
         spin_lock_irqsave(&gpio_lock, flags);
-
-        ctrlval = __raw_readl(ctrl);
-
-        if (value)
-                ctrlval |= 1 << (gpio & 31);
+#if defined(CONFIG_PROCESSOR_NS9360)
+        if (processor_is_ns9360())
+                ns9360_gpio_set_value(gpio, value);
         else
-                ctrlval &= ~(1 << (gpio & 31));
-
-        __raw_writel(ctrlval, ctrl);
+#endif
+                BUG();
 
         spin_unlock_irqrestore(&gpio_lock, flags);
 }
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index 00001b874e97..36e5835e6097 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -9,21 +9,27 @@
  * the Free Software Foundation.
  */
 #include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
 #include <asm/io.h>
 #include <asm/mach/irq.h>
 #include <asm/mach-types.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/regs-sys-common.h>
 #include <asm/arch-ns9xxx/irqs.h>
 #include <asm/arch-ns9xxx/board.h>
 
 #include "generic.h"
 
+/* simple interrupt prio table: prio(x) < prio(y) <=> x < y */
+#define irq2prio(i) (i)
+#define prio2irq(p) (p)
+
 static void ns9xxx_mask_irq(unsigned int irq)
 {
         /* XXX: better use cpp symbols */
-        u32 ic = __raw_readl(SYS_IC(irq / 4));
-        ic &= ~(1 << (7 + 8 * (3 - (irq & 3))));
-        __raw_writel(ic, SYS_IC(irq / 4));
+        int prio = irq2prio(irq);
+        u32 ic = __raw_readl(SYS_IC(prio / 4));
+        ic &= ~(1 << (7 + 8 * (3 - (prio & 3))));
+        __raw_writel(ic, SYS_IC(prio / 4));
 }
 
 static void ns9xxx_ack_irq(unsigned int irq)
@@ -40,9 +46,10 @@ static void ns9xxx_maskack_irq(unsigned int irq)
 static void ns9xxx_unmask_irq(unsigned int irq)
 {
         /* XXX: better use cpp symbols */
-        u32 ic = __raw_readl(SYS_IC(irq / 4));
-        ic |= 1 << (7 + 8 * (3 - (irq & 3)));
-        __raw_writel(ic, SYS_IC(irq / 4));
+        int prio = irq2prio(irq);
+        u32 ic = __raw_readl(SYS_IC(prio / 4));
+        ic |= 1 << (7 + 8 * (3 - (prio & 3)));
+        __raw_writel(ic, SYS_IC(prio / 4));
 }
 
 static struct irq_chip ns9xxx_chip = {
@@ -52,24 +59,61 @@ static struct irq_chip ns9xxx_chip = {
         .unmask         = ns9xxx_unmask_irq,
 };
 
+#if 0
+#define handle_irq handle_level_irq
+#else
+void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned int cpu = smp_processor_id();
+        struct irqaction *action;
+        irqreturn_t action_ret;
+
+        spin_lock(&desc->lock);
+
+        if (unlikely(desc->status & IRQ_INPROGRESS))
+                goto out_unlock;
+
+        desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
+        kstat_cpu(cpu).irqs[irq]++;
+
+        action = desc->action;
+        if (unlikely(!action || (desc->status & IRQ_DISABLED)))
+                goto out_unlock;
+
+        desc->status |= IRQ_INPROGRESS;
+        spin_unlock(&desc->lock);
+
+        action_ret = handle_IRQ_event(irq, action);
+
+        spin_lock(&desc->lock);
+        desc->status &= ~IRQ_INPROGRESS;
+        if (!(desc->status & IRQ_DISABLED) && desc->chip->ack)
+                desc->chip->ack(irq);
+
+out_unlock:
+        spin_unlock(&desc->lock);
+}
+#define handle_irq handle_prio_irq
+#endif
+
 void __init ns9xxx_init_irq(void)
 {
         int i;
 
         /* disable all IRQs */
         for (i = 0; i < 8; ++i)
-                __raw_writel((4 * i) << 24 | (4 * i + 1) << 16 |
-                                (4 * i + 2) << 8 | (4 * i + 3), SYS_IC(i));
+                __raw_writel(prio2irq(4 * i) << 24 |
+                                prio2irq(4 * i + 1) << 16 |
+                                prio2irq(4 * i + 2) << 8 |
+                                prio2irq(4 * i + 3),
+                                SYS_IC(i));
 
-        /* simple interrupt prio table:
-         * prio(x) < prio(y) <=> x < y
-         */
         for (i = 0; i < 32; ++i)
-                __raw_writel(i, SYS_IVA(i));
+                __raw_writel(prio2irq(i), SYS_IVA(i));
 
-        for (i = IRQ_WATCHDOG; i <= IRQ_EXT3; ++i) {
+        for (i = 0; i <= 31; ++i) {
                 set_irq_chip(i, &ns9xxx_chip);
-                set_irq_handler(i, handle_level_irq);
+                set_irq_handler(i, handle_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 }
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
index 760c9d0db7c3..9623fff6b3bc 100644
--- a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
+++ b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -11,12 +11,14 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+
 #include "board-a9m9750dev.h"
 #include "generic.h"
 
 static void __init mach_cc9p9360dev_map_io(void)
 {
-        ns9xxx_map_io();
+        ns9360_map_io();
         board_a9m9750dev_map_io();
 }
 
@@ -36,6 +38,6 @@ MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an A9M9750 Devboard")
         .map_io = mach_cc9p9360dev_map_io,
         .init_irq = mach_cc9p9360dev_init_irq,
         .init_machine = mach_cc9p9360dev_init_machine,
-        .timer = &ns9xxx_timer,
+        .timer = &ns9360_timer,
         .boot_params = 0x100,
 MACHINE_END
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
index 85c8b41105c9..fcc815bdd291 100644
--- a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
+++ b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-ns9xxx/mach-cc9p9360js.c
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -11,6 +11,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+
 #include "board-jscc9p9360.h"
 #include "generic.h"
 
@@ -21,9 +23,9 @@ static void __init mach_cc9p9360js_init_machine(void)
 }
 
 MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard")
-        .map_io = ns9xxx_map_io,
+        .map_io = ns9360_map_io,
         .init_irq = ns9xxx_init_irq,
         .init_machine = mach_cc9p9360js_init_machine,
-        .timer = &ns9xxx_timer,
+        .timer = &ns9360_timer,
         .boot_params = 0x100,
 MACHINE_END
diff --git a/arch/arm/mach-ns9xxx/plat-serial8250.c b/arch/arm/mach-ns9xxx/plat-serial8250.c
new file mode 100644
index 000000000000..5aa5d9baf8c8
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/plat-serial8250.c
@@ -0,0 +1,69 @@
+/*
+ * arch/arm/mach-ns9xxx/plat-serial8250.c
+ *
+ * Copyright (C) 2008 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+
+#include <asm/arch-ns9xxx/regs-board-a9m9750dev.h>
+#include <asm/arch-ns9xxx/board.h>
+
+#define DRIVER_NAME "serial8250"
+
+static int __init ns9xxx_plat_serial8250_init(void)
+{
+        struct plat_serial8250_port *pdata;
+        struct platform_device *pdev;
+        int ret = -ENOMEM;
+        int i;
+
+        if (!board_is_a9m9750dev())
+                return -ENODEV;
+
+        pdev = platform_device_alloc(DRIVER_NAME, 0);
+        if (!pdev)
+                goto err;
+
+        pdata = kzalloc(5 * sizeof(*pdata), GFP_KERNEL);
+        if (!pdata)
+                goto err;
+
+        pdev->dev.platform_data = pdata;
+
+        pdata[0].iobase = FPGA_UARTA_BASE;
+        pdata[1].iobase = FPGA_UARTB_BASE;
+        pdata[2].iobase = FPGA_UARTC_BASE;
+        pdata[3].iobase = FPGA_UARTD_BASE;
+
+        for (i = 0; i < 4; ++i) {
+                pdata[i].membase = (void __iomem *)pdata[i].iobase;
+                pdata[i].mapbase = pdata[i].iobase;
+                pdata[i].iotype = UPIO_MEM;
+                pdata[i].uartclk = 18432000;
+                pdata[i].flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+        }
+
+        pdata[0].irq = IRQ_FPGA_UARTA;
+        pdata[1].irq = IRQ_FPGA_UARTB;
+        pdata[2].irq = IRQ_FPGA_UARTC;
+        pdata[3].irq = IRQ_FPGA_UARTD;
+
+        ret = platform_device_add(pdev);
+        if (ret) {
+err:
+                platform_device_put(pdev);
+
+                printk(KERN_WARNING "Could not add %s (errno=%d)\n",
+                                DRIVER_NAME, ret);
+        }
+
+        return 0;
+}
+
+arch_initcall(ns9xxx_plat_serial8250_init);
diff --git a/arch/arm/mach-ns9xxx/processor-ns9360.c b/arch/arm/mach-ns9xxx/processor-ns9360.c
new file mode 100644
index 000000000000..2bee0b7fccbb
--- /dev/null
+++ b/arch/arm/mach-ns9xxx/processor-ns9360.c
@@ -0,0 +1,54 @@
+/*
+ * arch/arm/mach-ns9xxx/processor-ns9360.c
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
+
+void ns9360_reset(char mode)
+{
+        u32 reg;
+
+        reg = __raw_readl(SYS_PLL) >> 16;
+        REGSET(reg, SYS_PLL, SWC, YES);
+        __raw_writel(reg, SYS_PLL);
+}
+
+#define CRYSTAL 29491200 /* Hz */
+unsigned long ns9360_systemclock(void)
+{
+        u32 pll = __raw_readl(SYS_PLL);
+        return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1)
+                >> REGGETIM(pll, SYS_PLL, FS);
+}
+
+static struct map_desc ns9360_io_desc[] __initdata = {
+        { /* BBus */
+                .virtual = io_p2v(0x90000000),
+                .pfn = __phys_to_pfn(0x90000000),
+                .length = 0x00700000,
+                .type = MT_DEVICE,
+        }, { /* AHB */
+                .virtual = io_p2v(0xa0100000),
+                .pfn = __phys_to_pfn(0xa0100000),
+                .length = 0x00900000,
+                .type = MT_DEVICE,
+        },
+};
+
+void __init ns9360_map_io(void)
+{
+        iotable_init(ns9360_io_desc, ARRAY_SIZE(ns9360_io_desc));
+}
diff --git a/arch/arm/mach-ns9xxx/time.c b/arch/arm/mach-ns9xxx/time-ns9360.c
index c3dd1f4acb99..4d573c9793ed 100644
--- a/arch/arm/mach-ns9xxx/time.c
+++ b/arch/arm/mach-ns9xxx/time-ns9360.c
@@ -1,7 +1,7 @@
 /*
- * arch/arm/mach-ns9xxx/time.c
+ * arch/arm/mach-ns9xxx/time-ns9360.c
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -15,8 +15,8 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 
-#include <asm/arch-ns9xxx/regs-sys.h>
-#include <asm/arch-ns9xxx/clock.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
+#include <asm/arch-ns9xxx/regs-sys-ns9360.h>
 #include <asm/arch-ns9xxx/irqs.h>
 #include <asm/arch/system.h>
 #include "generic.h"
@@ -25,26 +25,26 @@
 #define TIMER_CLOCKEVENT 1
 static u32 latch;
 
-static cycle_t ns9xxx_clocksource_read(void)
+static cycle_t ns9360_clocksource_read(void)
 {
         return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE));
 }
 
-static struct clocksource ns9xxx_clocksource = {
-        .name   = "ns9xxx-timer" __stringify(TIMER_CLOCKSOURCE),
+static struct clocksource ns9360_clocksource = {
+        .name   = "ns9360-timer" __stringify(TIMER_CLOCKSOURCE),
         .rating = 300,
-        .read   = ns9xxx_clocksource_read,
+        .read   = ns9360_clocksource_read,
         .mask   = CLOCKSOURCE_MASK(32),
         .shift  = 20,
         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static void ns9xxx_clockevent_setmode(enum clock_event_mode mode,
+static void ns9360_clockevent_setmode(enum clock_event_mode mode,
                 struct clock_event_device *clk)
 {
         u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
 
-        switch(mode) {
+        switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
                 __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT));
                 REGSET(tc, SYS_TCx, REN, EN);
@@ -69,7 +69,7 @@ static void ns9xxx_clockevent_setmode(enum clock_event_mode mode,
         __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
 }
 
-static int ns9xxx_clockevent_setnextevent(unsigned long evt,
+static int ns9360_clockevent_setnextevent(unsigned long evt,
                 struct clock_event_device *clk)
 {
         u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
@@ -88,20 +88,20 @@ static int ns9xxx_clockevent_setnextevent(unsigned long evt,
         return 0;
 }
 
-static struct clock_event_device ns9xxx_clockevent_device = {
-        .name           = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT),
+static struct clock_event_device ns9360_clockevent_device = {
+        .name           = "ns9360-timer" __stringify(TIMER_CLOCKEVENT),
         .shift          = 20,
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .set_mode       = ns9xxx_clockevent_setmode,
-        .set_next_event = ns9xxx_clockevent_setnextevent,
+        .set_mode       = ns9360_clockevent_setmode,
+        .set_next_event = ns9360_clockevent_setnextevent,
 };
 
-static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id)
+static irqreturn_t ns9360_clockevent_handler(int irq, void *dev_id)
 {
-        int timerno = irq - IRQ_TIMER0;
+        int timerno = irq - IRQ_NS9360_TIMER0;
         u32 tc;
 
-        struct clock_event_device *evt = &ns9xxx_clockevent_device;
+        struct clock_event_device *evt = &ns9360_clockevent_device;
 
         /* clear irq */
         tc = __raw_readl(SYS_TC(timerno));
@@ -119,13 +119,13 @@ static irqreturn_t ns9xxx_clockevent_handler(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static struct irqaction ns9xxx_clockevent_action = {
-        .name           = "ns9xxx-timer" __stringify(TIMER_CLOCKEVENT),
+static struct irqaction ns9360_clockevent_action = {
+        .name           = "ns9360-timer" __stringify(TIMER_CLOCKEVENT),
         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = ns9xxx_clockevent_handler,
+        .handler        = ns9360_clockevent_handler,
 };
 
-static void __init ns9xxx_timer_init(void)
+static void __init ns9360_timer_init(void)
 {
         int tc;
 
@@ -148,12 +148,12 @@ static void __init ns9xxx_timer_init(void)
 
         __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
 
-        ns9xxx_clocksource.mult = clocksource_hz2mult(ns9xxx_cpuclock(),
-                        ns9xxx_clocksource.shift);
+        ns9360_clocksource.mult = clocksource_hz2mult(ns9360_cpuclock(),
+                        ns9360_clocksource.shift);
 
-        clocksource_register(&ns9xxx_clocksource);
+        clocksource_register(&ns9360_clocksource);
 
-        latch = SH_DIV(ns9xxx_cpuclock(), HZ, 0);
+        latch = SH_DIV(ns9360_cpuclock(), HZ, 0);
 
         tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
         REGSET(tc, SYS_TCx, TEN, DIS);
@@ -166,19 +166,20 @@ static void __init ns9xxx_timer_init(void)
         REGSET(tc, SYS_TCx, REN, EN);
         __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
 
-        ns9xxx_clockevent_device.mult = div_sc(ns9xxx_cpuclock(),
-                        NSEC_PER_SEC, ns9xxx_clockevent_device.shift);
-        ns9xxx_clockevent_device.max_delta_ns =
-                clockevent_delta2ns(-1, &ns9xxx_clockevent_device);
-        ns9xxx_clockevent_device.min_delta_ns =
-                clockevent_delta2ns(1, &ns9xxx_clockevent_device);
+        ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(),
+                        NSEC_PER_SEC, ns9360_clockevent_device.shift);
+        ns9360_clockevent_device.max_delta_ns =
+                clockevent_delta2ns(-1, &ns9360_clockevent_device);
+        ns9360_clockevent_device.min_delta_ns =
+                clockevent_delta2ns(1, &ns9360_clockevent_device);
 
-        ns9xxx_clockevent_device.cpumask = cpumask_of_cpu(0);
-        clockevents_register_device(&ns9xxx_clockevent_device);
+        ns9360_clockevent_device.cpumask = cpumask_of_cpu(0);
+        clockevents_register_device(&ns9360_clockevent_device);
 
-        setup_irq(IRQ_TIMER0 + TIMER_CLOCKEVENT, &ns9xxx_clockevent_action);
+        setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT,
+                        &ns9360_clockevent_action);
 }
 
-struct sys_timer ns9xxx_timer = {
-        .init = ns9xxx_timer_init,
+struct sys_timer ns9360_timer = {
+        .init = ns9360_timer_init,
 };
diff --git a/arch/arm/mach-orion/addr-map.c b/arch/arm/mach-orion/addr-map.c
deleted file mode 100644
index 58cc3c0333b6..000000000000
--- a/arch/arm/mach-orion/addr-map.c
+++ /dev/null
@@ -1,490 +0,0 @@
-/*
- * arch/arm/mach-orion/addr-map.c
- *
- * Address map functions for Marvell Orion System On Chip
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/hardware.h>
-#include "common.h"
-
-/*
- * The Orion has fully programable address map. There's a separate address
- * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
- * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
- * address decode windows that allow it to access any of the Orion resources.
- *
- * CPU address decoding --
- * Linux assumes that it is the boot loader that already setup the access to
- * DDR and internal registers.
- * Setup access to PCI and PCI-E IO/MEM space is issued by core.c.
- * Setup access to various devices located on the device bus interface (e.g.
- * flashes, RTC, etc) should be issued by machine-setup.c according to
- * specific board population (by using orion_setup_cpu_win()).
- *
- * Non-CPU Masters address decoding --
- * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
- * banks only (the typical use case).
- * Setup access for each master to DDR is issued by common.c.
- *
- * Note: although orion_setbits() and orion_clrbits() are not atomic
- * no locking is necessary here since code in this file is only called
- * at boot time when there is no concurrency issues.
- */
-
-/*
- * Generic Address Decode Windows bit settings
- */
-#define TARGET_DDR              0
-#define TARGET_PCI              3
-#define TARGET_PCIE             4
-#define TARGET_DEV_BUS          1
-#define ATTR_DDR_CS(n)          (((n) ==0) ? 0xe :      \
-                                ((n) == 1) ? 0xd :      \
-                                ((n) == 2) ? 0xb :      \
-                                ((n) == 3) ? 0x7 : 0xf)
-#define ATTR_PCIE_MEM           0x59
-#define ATTR_PCIE_IO            0x51
-#define ATTR_PCI_MEM            0x59
-#define ATTR_PCI_IO             0x51
-#define ATTR_DEV_CS0            0x1e
-#define ATTR_DEV_CS1            0x1d
-#define ATTR_DEV_CS2            0x1b
-#define ATTR_DEV_BOOT           0xf
-#define WIN_EN                  1
-
-/*
- * Helpers to get DDR banks info
- */
-#define DDR_BASE_CS(n)          ORION_DDR_REG(0x1500 + ((n) * 8))
-#define DDR_SIZE_CS(n)          ORION_DDR_REG(0x1504 + ((n) * 8))
-#define DDR_MAX_CS              4
-#define DDR_REG_TO_SIZE(reg)    (((reg) | 0xffffff) + 1)
-#define DDR_REG_TO_BASE(reg)    ((reg) & 0xff000000)
-#define DDR_BANK_EN             1
-
-/*
- * CPU Address Decode Windows registers
- */
-#define CPU_WIN_CTRL(n)         ORION_BRIDGE_REG(0x000 | ((n) << 4))
-#define CPU_WIN_BASE(n)         ORION_BRIDGE_REG(0x004 | ((n) << 4))
-#define CPU_WIN_REMAP_LO(n)     ORION_BRIDGE_REG(0x008 | ((n) << 4))
-#define CPU_WIN_REMAP_HI(n)     ORION_BRIDGE_REG(0x00c | ((n) << 4))
-#define CPU_MAX_WIN             8
-
-/*
- * Use this CPU address decode windows allocation
- */
-#define CPU_WIN_PCIE_IO         0
-#define CPU_WIN_PCI_IO          1
-#define CPU_WIN_PCIE_MEM        2
-#define CPU_WIN_PCI_MEM         3
-#define CPU_WIN_DEV_BOOT        4
-#define CPU_WIN_DEV_CS0         5
-#define CPU_WIN_DEV_CS1         6
-#define CPU_WIN_DEV_CS2         7
-
-/*
- * PCIE Address Decode Windows registers
- */
-#define PCIE_BAR_CTRL(n)        ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
-#define PCIE_BAR_LO(n)          ORION_PCIE_REG(0x0010 + ((n) * 8))
-#define PCIE_BAR_HI(n)          ORION_PCIE_REG(0x0014 + ((n) * 8))
-#define PCIE_WIN_CTRL(n)        (((n) < 5) ? \
-                                        ORION_PCIE_REG(0x1820 + ((n) << 4)) : \
-                                        ORION_PCIE_REG(0x1880))
-#define PCIE_WIN_BASE(n)        (((n) < 5) ? \
-                                        ORION_PCIE_REG(0x1824 + ((n) << 4)) : \
-                                        ORION_PCIE_REG(0x1884))
-#define PCIE_WIN_REMAP(n)       (((n) < 5) ? \
-                                        ORION_PCIE_REG(0x182c + ((n) << 4)) : \
-                                        ORION_PCIE_REG(0x188c))
-#define PCIE_DEFWIN_CTRL        ORION_PCIE_REG(0x18b0)
-#define PCIE_EXPROM_WIN_CTRL    ORION_PCIE_REG(0x18c0)
-#define PCIE_EXPROM_WIN_REMP    ORION_PCIE_REG(0x18c4)
-#define PCIE_MAX_BARS           3
-#define PCIE_MAX_WINS           6
-
-/*
- * Use PCIE BAR '1' for all DDR banks
- */
-#define PCIE_DRAM_BAR           1
-
-/*
- * PCI Address Decode Windows registers
- */
-#define PCI_BAR_SIZE_DDR_CS(n)  (((n) == 0) ? ORION_PCI_REG(0xc08) : \
-                                ((n) == 1) ? ORION_PCI_REG(0xd08) :  \
-                                ((n) == 2) ? ORION_PCI_REG(0xc0c) :  \
-                                ((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
-#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION_PCI_REG(0xc48) : \
-                                ((n) == 1) ? ORION_PCI_REG(0xd48) :  \
-                                ((n) == 2) ? ORION_PCI_REG(0xc4c) :  \
-                                ((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
-#define PCI_BAR_ENABLE          ORION_PCI_REG(0xc3c)
-#define PCI_CTRL_BASE_LO(n)     ORION_PCI_REG(0x1e00 | ((n) << 4))
-#define PCI_CTRL_BASE_HI(n)     ORION_PCI_REG(0x1e04 | ((n) << 4))
-#define PCI_CTRL_SIZE(n)        ORION_PCI_REG(0x1e08 | ((n) << 4))
-#define PCI_ADDR_DECODE_CTRL    ORION_PCI_REG(0xd3c)
-
-/*
- * PCI configuration heleprs for BAR settings
- */
-#define PCI_CONF_FUNC_BAR_CS(n)         ((n) >> 1)
-#define PCI_CONF_REG_BAR_LO_CS(n)       (((n) & 1) ? 0x18 : 0x10)
-#define PCI_CONF_REG_BAR_HI_CS(n)       (((n) & 1) ? 0x1c : 0x14)
-
-/*
- * Gigabit Ethernet Address Decode Windows registers
- */
-#define ETH_WIN_BASE(win)       ORION_ETH_REG(0x200 + ((win) * 8))
-#define ETH_WIN_SIZE(win)       ORION_ETH_REG(0x204 + ((win) * 8))
-#define ETH_WIN_REMAP(win)      ORION_ETH_REG(0x280 + ((win) * 4))
-#define ETH_WIN_EN              ORION_ETH_REG(0x290)
-#define ETH_WIN_PROT            ORION_ETH_REG(0x294)
-#define ETH_MAX_WIN             6
-#define ETH_MAX_REMAP_WIN       4
-
-/*
- * USB Address Decode Windows registers
- */
-#define USB_WIN_CTRL(i, w)      ((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \
-                                        : ORION_USB1_REG(0x320 + ((w) << 4)))
-#define USB_WIN_BASE(i, w)      ((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \
-                                        : ORION_USB1_REG(0x324 + ((w) << 4)))
-#define USB_MAX_WIN             4
-
-/*
- * SATA Address Decode Windows registers
- */
-#define SATA_WIN_CTRL(win)      ORION_SATA_REG(0x30 + ((win) * 0x10))
-#define SATA_WIN_BASE(win)      ORION_SATA_REG(0x34 + ((win) * 0x10))
-#define SATA_MAX_WIN            4
-
-static int __init orion_cpu_win_can_remap(u32 win)
-{
-        u32 dev, rev;
-
-        orion_pcie_id(&dev, &rev);
-        if ((dev == MV88F5281_DEV_ID && win < 4)
-            || (dev == MV88F5182_DEV_ID && win < 2)
-            || (dev == MV88F5181_DEV_ID && win < 2))
-                return 1;
-
-        return 0;
-}
-
-void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap)
-{
-        u32 win, attr, ctrl;
-
-        switch (target) {
-        case ORION_PCIE_IO:
-                target = TARGET_PCIE;
-                attr = ATTR_PCIE_IO;
-                win = CPU_WIN_PCIE_IO;
-                break;
-        case ORION_PCI_IO:
-                target = TARGET_PCI;
-                attr = ATTR_PCI_IO;
-                win = CPU_WIN_PCI_IO;
-                break;
-        case ORION_PCIE_MEM:
-                target = TARGET_PCIE;
-                attr = ATTR_PCIE_MEM;
-                win = CPU_WIN_PCIE_MEM;
-                break;
-        case ORION_PCI_MEM:
-                target = TARGET_PCI;
-                attr = ATTR_PCI_MEM;
-                win = CPU_WIN_PCI_MEM;
-                break;
-        case ORION_DEV_BOOT:
-                target = TARGET_DEV_BUS;
-                attr = ATTR_DEV_BOOT;
-                win = CPU_WIN_DEV_BOOT;
-                break;
-        case ORION_DEV0:
-                target = TARGET_DEV_BUS;
-                attr = ATTR_DEV_CS0;
-                win = CPU_WIN_DEV_CS0;
-                break;
-        case ORION_DEV1:
-                target = TARGET_DEV_BUS;
-                attr = ATTR_DEV_CS1;
-                win = CPU_WIN_DEV_CS1;
-                break;
-        case ORION_DEV2:
-                target = TARGET_DEV_BUS;
-                attr = ATTR_DEV_CS2;
-                win = CPU_WIN_DEV_CS2;
-                break;
-        case ORION_DDR:
-        case ORION_REGS:
-                /*
-                 * Must be mapped by bootloader.
-                 */
-        default:
-                target = attr = win = -1;
-                BUG();
-        }
-
-        base &= 0xffff0000;
-        ctrl = (((size - 1) & 0xffff0000) | (attr << 8) |
-                (target << 4) | WIN_EN);
-
-        orion_write(CPU_WIN_BASE(win), base);
-        orion_write(CPU_WIN_CTRL(win), ctrl);
-
-        if (orion_cpu_win_can_remap(win)) {
-                if (remap >= 0) {
-                        orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
-                        orion_write(CPU_WIN_REMAP_HI(win), 0);
-                } else {
-                        orion_write(CPU_WIN_REMAP_LO(win), base);
-                        orion_write(CPU_WIN_REMAP_HI(win), 0);
-                }
-        }
-}
-
-void __init orion_setup_cpu_wins(void)
-{
-        int i;
-
-        /*
-         * First, disable and clear windows
-         */
-        for (i = 0; i < CPU_MAX_WIN; i++) {
-                orion_write(CPU_WIN_BASE(i), 0);
-                orion_write(CPU_WIN_CTRL(i), 0);
-                if (orion_cpu_win_can_remap(i)) {
-                        orion_write(CPU_WIN_REMAP_LO(i), 0);
-                        orion_write(CPU_WIN_REMAP_HI(i), 0);
-                }
-        }
-
-        /*
-         * Setup windows for PCI+PCIe IO+MEM space.
-         */
-        orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
-                                ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
-        orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
-                                ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
-        orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
-                                ORION_PCIE_MEM_SIZE, -1);
-        orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
-                                ORION_PCI_MEM_SIZE, -1);
-}
-
-/*
- * Setup PCIE BARs and Address Decode Wins:
- * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
- * WIN[0-3] -> DRAM bank[0-3]
- */
-void __init orion_setup_pcie_wins(void)
-{
-        u32 base, size, i;
-
-        /*
-         * First, disable and clear BARs and windows
-         */
-        for (i = 1; i < PCIE_MAX_BARS; i++) {
-                orion_write(PCIE_BAR_CTRL(i), 0);
-                orion_write(PCIE_BAR_LO(i), 0);
-                orion_write(PCIE_BAR_HI(i), 0);
-        }
-
-        for (i = 0; i < PCIE_MAX_WINS; i++) {
-                orion_write(PCIE_WIN_CTRL(i), 0);
-                orion_write(PCIE_WIN_BASE(i), 0);
-                orion_write(PCIE_WIN_REMAP(i), 0);
-        }
-
-        /*
-         * Setup windows for DDR banks. Count total DDR size on the fly.
-         */
-        base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0)));
-        size = 0;
-        for (i = 0; i < DDR_MAX_CS; i++) {
-                u32 bank_base, bank_size;
-                bank_size = orion_read(DDR_SIZE_CS(i));
-                bank_base = orion_read(DDR_BASE_CS(i));
-                if (bank_size & DDR_BANK_EN) {
-                        bank_size = DDR_REG_TO_SIZE(bank_size);
-                        bank_base = DDR_REG_TO_BASE(bank_base);
-                        orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000);
-                        orion_write(PCIE_WIN_REMAP(i), 0);
-                        orion_write(PCIE_WIN_CTRL(i),
-                                        ((bank_size-1) & 0xffff0000) |
-                                        (ATTR_DDR_CS(i) << 8) |
-                                        (TARGET_DDR << 4) |
-                                        (PCIE_DRAM_BAR << 1) | WIN_EN);
-                        size += bank_size;
-                }
-        }
-
-        /*
-         * Setup BAR[1] to all DRAM banks
-         */
-        orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000);
-        orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0);
-        orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR),
-                                ((size - 1) & 0xffff0000) | WIN_EN);
-}
-
-void __init orion_setup_pci_wins(void)
-{
-        u32 base, size, i;
-
-        /*
-         * First, disable windows
-         */
-        orion_write(PCI_BAR_ENABLE, 0xffffffff);
-
-        /*
-         * Setup windows for DDR banks.
-         */
-        for (i = 0; i < DDR_MAX_CS; i++) {
-                base = orion_read(DDR_BASE_CS(i));
-                size = orion_read(DDR_SIZE_CS(i));
-                if (size & DDR_BANK_EN) {
-                        u32 bus, dev, func, reg, val;
-                        size = DDR_REG_TO_SIZE(size);
-                        base = DDR_REG_TO_BASE(base);
-                        bus = orion_pci_local_bus_nr();
-                        dev = orion_pci_local_dev_nr();
-                        func = PCI_CONF_FUNC_BAR_CS(i);
-                        reg = PCI_CONF_REG_BAR_LO_CS(i);
-                        orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
-                        orion_pci_hw_wr_conf(bus, dev, func, reg, 4,
-                                        (base & 0xfffff000) | (val & 0xfff));
-                        reg = PCI_CONF_REG_BAR_HI_CS(i);
-                        orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
-                        orion_write(PCI_BAR_SIZE_DDR_CS(i),
-                                        (size - 1) & 0xfffff000);
-                        orion_write(PCI_BAR_REMAP_DDR_CS(i),
-                                        base & 0xfffff000);
-                        orion_clrbits(PCI_BAR_ENABLE, (1 << i));
-                }
-        }
-
-        /*
-         * Disable automatic update of address remaping when writing to BARs
-         */
-        orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
-}
-
-void __init orion_setup_usb_wins(void)
-{
-        int i;
-        u32 usb_if, dev, rev;
-        u32 max_usb_if = 1;
-
-        orion_pcie_id(&dev, &rev);
-        if (dev == MV88F5182_DEV_ID)
-                max_usb_if = 2;
-
-        for (usb_if = 0; usb_if < max_usb_if; usb_if++) {
-                /*
-                 * First, disable and clear windows
-                 */
-                for (i = 0; i < USB_MAX_WIN; i++) {
-                        orion_write(USB_WIN_BASE(usb_if, i), 0);
-                        orion_write(USB_WIN_CTRL(usb_if, i), 0);
-                }
-
-                /*
-                 * Setup windows for DDR banks.
-                 */
-                for (i = 0; i < DDR_MAX_CS; i++) {
-                        u32 base, size;
-                        size = orion_read(DDR_SIZE_CS(i));
-                        base = orion_read(DDR_BASE_CS(i));
-                        if (size & DDR_BANK_EN) {
-                                base = DDR_REG_TO_BASE(base);
-                                size = DDR_REG_TO_SIZE(size);
-                                orion_write(USB_WIN_CTRL(usb_if, i),
-                                                ((size-1) & 0xffff0000) |
-                                                (ATTR_DDR_CS(i) << 8) |
-                                                (TARGET_DDR << 4) | WIN_EN);
-                                orion_write(USB_WIN_BASE(usb_if, i),
-                                                base & 0xffff0000);
-                        }
-                }
-        }
-}
-
-void __init orion_setup_eth_wins(void)
-{
-        int i;
-
-        /*
-         * First, disable and clear windows
-         */
-        for (i = 0; i < ETH_MAX_WIN; i++) {
-                orion_write(ETH_WIN_BASE(i), 0);
-                orion_write(ETH_WIN_SIZE(i), 0);
-                orion_setbits(ETH_WIN_EN, 1 << i);
-                orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
-                if (i < ETH_MAX_REMAP_WIN)
-                        orion_write(ETH_WIN_REMAP(i), 0);
-        }
-
-        /*
-         * Setup windows for DDR banks.
-         */
-        for (i = 0; i < DDR_MAX_CS; i++) {
-                u32 base, size;
-                size = orion_read(DDR_SIZE_CS(i));
-                base = orion_read(DDR_BASE_CS(i));
-                if (size & DDR_BANK_EN) {
-                        base = DDR_REG_TO_BASE(base);
-                        size = DDR_REG_TO_SIZE(size);
-                        orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
-                        orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
-                                        (ATTR_DDR_CS(i) << 8) |
-                                        TARGET_DDR);
-                        orion_clrbits(ETH_WIN_EN, 1 << i);
-                        orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
-                }
-        }
-}
-
-void __init orion_setup_sata_wins(void)
-{
-        int i;
-
-        /*
-         * First, disable and clear windows
-         */
-        for (i = 0; i < SATA_MAX_WIN; i++) {
-                orion_write(SATA_WIN_BASE(i), 0);
-                orion_write(SATA_WIN_CTRL(i), 0);
-        }
-
-        /*
-         * Setup windows for DDR banks.
-         */
-        for (i = 0; i < DDR_MAX_CS; i++) {
-                u32 base, size;
-                size = orion_read(DDR_SIZE_CS(i));
-                base = orion_read(DDR_BASE_CS(i));
-                if (size & DDR_BANK_EN) {
-                        base = DDR_REG_TO_BASE(base);
-                        size = DDR_REG_TO_SIZE(size);
-                        orion_write(SATA_WIN_CTRL(i),
-                                        ((size-1) & 0xffff0000) |
-                                        (ATTR_DDR_CS(i) << 8) |
-                                        (TARGET_DDR << 4) | WIN_EN);
-                        orion_write(SATA_WIN_BASE(i),
-                                        base & 0xffff0000);
-                }
-        }
-}
diff --git a/arch/arm/mach-orion/common.h b/arch/arm/mach-orion/common.h
deleted file mode 100644
index 501497cc2c4d..000000000000
--- a/arch/arm/mach-orion/common.h
+++ /dev/null
@@ -1,92 +0,0 @@
-#ifndef __ARCH_ORION_COMMON_H__
-#define __ARCH_ORION_COMMON_H__
-
-/*
- * Basic Orion init functions used early by machine-setup.
- */
-
-void __init orion_map_io(void);
-void __init orion_init_irq(void);
-void __init orion_init(void);
-
-/*
- * Enumerations and functions for Orion windows mapping. Used by Orion core
- * functions to map its interfaces and by the machine-setup to map its on-
- * board devices. Details in /mach-orion/addr-map.c
- */
-
-enum orion_target {
-        ORION_DEV_BOOT = 0,
-        ORION_DEV0,
-        ORION_DEV1,
-        ORION_DEV2,
-        ORION_PCIE_MEM,
-        ORION_PCIE_IO,
-        ORION_PCI_MEM,
-        ORION_PCI_IO,
-        ORION_DDR,
-        ORION_REGS,
-        ORION_MAX_TARGETS
-};
-
-void orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap);
-void orion_setup_cpu_wins(void);
-void orion_setup_eth_wins(void);
-void orion_setup_usb_wins(void);
-void orion_setup_pci_wins(void);
-void orion_setup_pcie_wins(void);
-void orion_setup_sata_wins(void);
-
-/*
- * Shared code used internally by other Orion core functions.
- * (/mach-orion/pci.c)
- */
-
-struct pci_sys_data;
-struct pci_bus;
-
-void orion_pcie_id(u32 *dev, u32 *rev);
-u32 orion_pcie_local_bus_nr(void);
-u32 orion_pci_local_bus_nr(void);
-u32 orion_pci_local_dev_nr(void);
-int orion_pci_sys_setup(int nr, struct pci_sys_data *sys);
-struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
-int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val);
-int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val);
-
-/*
- * Valid GPIO pins according to MPP setup, used by machine-setup.
- * (/mach-orion/gpio.c).
- */
-
-void __init orion_gpio_set_valid_pins(u32 pins);
-void gpio_display(void);        /* debug */
-
-/*
- * Orion system timer (clocksource + clockevnt, /mach-orion/time.c)
- */
-extern struct sys_timer orion_timer;
-
-/*
- * Pull in Orion Ethernet platform_data, used by machine-setup
- */
-
-struct mv643xx_eth_platform_data;
-
-void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
-
-/*
- * Orion Sata platform_data, used by machine-setup
- */
-
-struct mv_sata_platform_data;
-
-void __init orion_sata_init(struct mv_sata_platform_data *sata_data);
-
-struct machine_desc;
-struct meminfo;
-struct tag;
-extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *,
-                                   char **, struct meminfo *);
-
-#endif /* __ARCH_ORION_COMMON_H__ */
diff --git a/arch/arm/mach-orion/pci.c b/arch/arm/mach-orion/pci.c
deleted file mode 100644
index b109bb46681e..000000000000
--- a/arch/arm/mach-orion/pci.c
+++ /dev/null
@@ -1,557 +0,0 @@
-/*
- * arch/arm/mach-orion/pci.c
- *
- * PCI and PCIE functions for Marvell Orion System On Chip
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <asm/mach/pci.h>
-#include "common.h"
-
-/*****************************************************************************
- * Orion has one PCIE controller and one PCI controller.
- *
- * Note1: The local PCIE bus number is '0'. The local PCI bus number
- * follows the scanned PCIE bridged busses, if any.
- *
- * Note2: It is possible for PCI/PCIE agents to access many subsystem's
- * space, by configuring BARs and Address Decode Windows, e.g. flashes on
- * device bus, Orion registers, etc. However this code only enable the
- * access to DDR banks.
- ****************************************************************************/
-
-
-/*****************************************************************************
- * PCIE controller
- ****************************************************************************/
-#define PCIE_CTRL               ORION_PCIE_REG(0x1a00)
-#define PCIE_STAT               ORION_PCIE_REG(0x1a04)
-#define PCIE_DEV_ID             ORION_PCIE_REG(0x0000)
-#define PCIE_CMD_STAT           ORION_PCIE_REG(0x0004)
-#define PCIE_DEV_REV            ORION_PCIE_REG(0x0008)
-#define PCIE_MASK               ORION_PCIE_REG(0x1910)
-#define PCIE_CONF_ADDR          ORION_PCIE_REG(0x18f8)
-#define PCIE_CONF_DATA          ORION_PCIE_REG(0x18fc)
-
-/*
- * PCIE_STAT bits
- */
-#define PCIE_STAT_LINK_DOWN             1
-#define PCIE_STAT_BUS_OFFS              8
-#define PCIE_STAT_BUS_MASK              (0xff << PCIE_STAT_BUS_OFFS)
-#define PCIE_STAT_DEV_OFFS              20
-#define PCIE_STAT_DEV_MASK              (0x1f << PCIE_STAT_DEV_OFFS)
-
-/*
- * PCIE_CONF_ADDR bits
- */
-#define PCIE_CONF_REG(r)                ((((r) & 0xf00) << 24) | ((r) & 0xfc))
-#define PCIE_CONF_FUNC(f)               (((f) & 0x3) << 8)
-#define PCIE_CONF_DEV(d)                (((d) & 0x1f) << 11)
-#define PCIE_CONF_BUS(b)                (((b) & 0xff) << 16)
-#define PCIE_CONF_ADDR_EN               (1 << 31)
-
-/*
- * PCIE config cycles are done by programming the PCIE_CONF_ADDR register
- * and then reading the PCIE_CONF_DATA register. Need to make sure these
- * transactions are atomic.
- */
-static DEFINE_SPINLOCK(orion_pcie_lock);
-
-void orion_pcie_id(u32 *dev, u32 *rev)
-{
-        *dev = orion_read(PCIE_DEV_ID) >> 16;
-        *rev = orion_read(PCIE_DEV_REV) & 0xff;
-}
-
-u32 orion_pcie_local_bus_nr(void)
-{
-        u32 stat = orion_read(PCIE_STAT);
-        return((stat & PCIE_STAT_BUS_MASK) >> PCIE_STAT_BUS_OFFS);
-}
-
-static u32 orion_pcie_local_dev_nr(void)
-{
-        u32 stat = orion_read(PCIE_STAT);
-        return((stat & PCIE_STAT_DEV_MASK) >> PCIE_STAT_DEV_OFFS);
-}
-
-static u32 orion_pcie_no_link(void)
-{
-        u32 stat = orion_read(PCIE_STAT);
-        return(stat & PCIE_STAT_LINK_DOWN);
-}
-
-static void orion_pcie_set_bus_nr(int nr)
-{
-        orion_clrbits(PCIE_STAT, PCIE_STAT_BUS_MASK);
-        orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS);
-}
-
-static void orion_pcie_master_slave_enable(void)
-{
-        orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER |
-                                          PCI_COMMAND_IO |
-                                          PCI_COMMAND_MEMORY);
-}
-
-static void orion_pcie_enable_interrupts(void)
-{
-        /*
-         * Enable interrupts lines
-         * INTA[24] INTB[25] INTC[26] INTD[27]
-         */
-        orion_setbits(PCIE_MASK, 0xf<<24);
-}
-
-static int orion_pcie_valid_config(u32 bus, u32 dev)
-{
-        /*
-         * Don't go out when trying to access --
-         * 1. our own device
-         * 2. where there's no device connected (no link)
-         * 3. nonexisting devices on local bus
-         */
-
-        if ((orion_pcie_local_bus_nr() == bus) &&
-           (orion_pcie_local_dev_nr() == dev))
-                return 0;
-
-        if (orion_pcie_no_link())
-                return 0;
-
-        if (bus == orion_pcie_local_bus_nr())
-                if (((orion_pcie_local_dev_nr() == 0) && (dev != 1)) ||
-                   ((orion_pcie_local_dev_nr() != 0) && (dev != 0)))
-                return 0;
-
-        return 1;
-}
-
-static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
-                                                int size, u32 *val)
-{
-        unsigned long flags;
-        unsigned int dev, rev, pcie_addr;
-
-        if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
-                *val = 0xffffffff;
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        }
-
-        spin_lock_irqsave(&orion_pcie_lock, flags);
-
-        orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
-                        PCIE_CONF_DEV(PCI_SLOT(devfn)) |
-                        PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
-                        PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
-
-        orion_pcie_id(&dev, &rev);
-        if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
-                /* extended register space */
-                pcie_addr = ORION_PCIE_WA_VIRT_BASE;
-                pcie_addr |= PCIE_CONF_BUS(bus->number) |
-                        PCIE_CONF_DEV(PCI_SLOT(devfn)) |
-                        PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
-                        PCIE_CONF_REG(where);
-                *val = orion_read(pcie_addr);
-        } else
-                *val = orion_read(PCIE_CONF_DATA);
-
-        if (size == 1)
-                *val = (*val >> (8*(where & 0x3))) & 0xff;
-        else if (size == 2)
-                *val = (*val >> (8*(where & 0x3))) & 0xffff;
-
-        spin_unlock_irqrestore(&orion_pcie_lock, flags);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-
-static int orion_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where,
-                                                int size, u32 val)
-{
-        unsigned long flags;
-        int ret;
-
-        if (orion_pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-
-        spin_lock_irqsave(&orion_pcie_lock, flags);
-
-        ret = PCIBIOS_SUCCESSFUL;
-
-        orion_write(PCIE_CONF_ADDR, PCIE_CONF_BUS(bus->number) |
-                        PCIE_CONF_DEV(PCI_SLOT(devfn)) |
-                        PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
-                        PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN);
-
-        if (size == 4) {
-                __raw_writel(val, PCIE_CONF_DATA);
-        } else if (size == 2) {
-                __raw_writew(val, PCIE_CONF_DATA + (where & 0x3));
-        } else if (size == 1) {
-                __raw_writeb(val, PCIE_CONF_DATA + (where & 0x3));
-        } else {
-                ret = PCIBIOS_BAD_REGISTER_NUMBER;
-        }
-
-        spin_unlock_irqrestore(&orion_pcie_lock, flags);
-
-        return ret;
-}
-
-struct pci_ops orion_pcie_ops = {
-        .read = orion_pcie_rd_conf,
-        .write = orion_pcie_wr_conf,
-};
-
-
-static int orion_pcie_setup(struct pci_sys_data *sys)
-{
-        struct resource *res;
-
-        /*
-         * Master + Slave enable
-         */
-        orion_pcie_master_slave_enable();
-
-        /*
-         * Enable interrupts lines A-D
-         */
-        orion_pcie_enable_interrupts();
-
-        /*
-         * Request resource
-         */
-        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-        if (!res)
-                panic("orion_pci_setup unable to alloc resources");
-
-        /*
-         * IORESOURCE_IO
-         */
-        res[0].name = "PCI-EX I/O Space";
-        res[0].flags = IORESOURCE_IO;
-        res[0].start = ORION_PCIE_IO_BUS_BASE;
-        res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
-        if (request_resource(&ioport_resource, &res[0]))
-                panic("Request PCIE IO resource failed\n");
-        sys->resource[0] = &res[0];
-
-        /*
-         * IORESOURCE_MEM
-         */
-        res[1].name = "PCI-EX Memory Space";
-        res[1].flags = IORESOURCE_MEM;
-        res[1].start = ORION_PCIE_MEM_PHYS_BASE;
-        res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
-        if (request_resource(&iomem_resource, &res[1]))
-                panic("Request PCIE Memory resource failed\n");
-        sys->resource[1] = &res[1];
-
-        sys->resource[2] = NULL;
-        sys->io_offset = 0;
-
-        return 1;
-}
-
-/*****************************************************************************
- * PCI controller
- ****************************************************************************/
-#define PCI_MODE                ORION_PCI_REG(0xd00)
-#define PCI_CMD                 ORION_PCI_REG(0xc00)
-#define PCI_P2P_CONF            ORION_PCI_REG(0x1d14)
-#define PCI_CONF_ADDR           ORION_PCI_REG(0xc78)
-#define PCI_CONF_DATA           ORION_PCI_REG(0xc7c)
-
-/*
- * PCI_MODE bits
- */
-#define PCI_MODE_64BIT                  (1 << 2)
-#define PCI_MODE_PCIX                   ((1 << 4) | (1 << 5))
-
-/*
- * PCI_CMD bits
- */
-#define PCI_CMD_HOST_REORDER            (1 << 29)
-
-/*
- * PCI_P2P_CONF bits
- */
-#define PCI_P2P_BUS_OFFS                16
-#define PCI_P2P_BUS_MASK                (0xff << PCI_P2P_BUS_OFFS)
-#define PCI_P2P_DEV_OFFS                24
-#define PCI_P2P_DEV_MASK                (0x1f << PCI_P2P_DEV_OFFS)
-
-/*
- * PCI_CONF_ADDR bits
- */
-#define PCI_CONF_REG(reg)               ((reg) & 0xfc)
-#define PCI_CONF_FUNC(func)             (((func) & 0x3) << 8)
-#define PCI_CONF_DEV(dev)               (((dev) & 0x1f) << 11)
-#define PCI_CONF_BUS(bus)               (((bus) & 0xff) << 16)
-#define PCI_CONF_ADDR_EN                (1 << 31)
-
-/*
- * Internal configuration space
- */
-#define PCI_CONF_FUNC_STAT_CMD          0
-#define PCI_CONF_REG_STAT_CMD           4
-#define PCIX_STAT                       0x64
-#define PCIX_STAT_BUS_OFFS              8
-#define PCIX_STAT_BUS_MASK              (0xff << PCIX_STAT_BUS_OFFS)
-
-/*
- * PCI config cycles are done by programming the PCI_CONF_ADDR register
- * and then reading the PCI_CONF_DATA register. Need to make sure these
- * transactions are atomic.
- */
-static DEFINE_SPINLOCK(orion_pci_lock);
-
-u32 orion_pci_local_bus_nr(void)
-{
-        u32 conf = orion_read(PCI_P2P_CONF);
-        return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
-}
-
-u32 orion_pci_local_dev_nr(void)
-{
-        u32 conf = orion_read(PCI_P2P_CONF);
-        return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS);
-}
-
-int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
-                                        u32 where, u32 size, u32 *val)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&orion_pci_lock, flags);
-
-        orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
-                        PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
-                        PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
-
-        *val = orion_read(PCI_CONF_DATA);
-
-        if (size == 1)
-                *val = (*val >> (8*(where & 0x3))) & 0xff;
-        else if (size == 2)
-                *val = (*val >> (8*(where & 0x3))) & 0xffff;
-
-        spin_unlock_irqrestore(&orion_pci_lock, flags);
-
-        return PCIBIOS_SUCCESSFUL;
-}
-
-int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
-                                        u32 where, u32 size, u32 val)
-{
-        unsigned long flags;
-        int ret = PCIBIOS_SUCCESSFUL;
-
-        spin_lock_irqsave(&orion_pci_lock, flags);
-
-        orion_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
-                        PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
-                        PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
-
-        if (size == 4) {
-                __raw_writel(val, PCI_CONF_DATA);
-        } else if (size == 2) {
-                __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
-        } else if (size == 1) {
-                __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
-        } else {
-                ret = PCIBIOS_BAD_REGISTER_NUMBER;
-        }
-
-        spin_unlock_irqrestore(&orion_pci_lock, flags);
-
-        return ret;
-}
-
-static int orion_pci_rd_conf(struct pci_bus *bus, u32 devfn,
-                                int where, int size, u32 *val)
-{
-        /*
-         * Don't go out for local device
-         */
-        if ((orion_pci_local_bus_nr() == bus->number) &&
-           (orion_pci_local_dev_nr() == PCI_SLOT(devfn))) {
-                *val = 0xffffffff;
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        }
-
-        return orion_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
-                                        PCI_FUNC(devfn), where, size, val);
-}
-
-static int orion_pci_wr_conf(struct pci_bus *bus, u32 devfn,
-                                int where, int size, u32 val)
-{
-        /*
-         * Don't go out for local device
-         */
-        if ((orion_pci_local_bus_nr() == bus->number) &&
-           (orion_pci_local_dev_nr() == PCI_SLOT(devfn)))
-                return PCIBIOS_DEVICE_NOT_FOUND;
-
-        return orion_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
-                                        PCI_FUNC(devfn), where, size, val);
-}
-
-struct pci_ops orion_pci_ops = {
-        .read = orion_pci_rd_conf,
-        .write = orion_pci_wr_conf,
-};
-
-static void orion_pci_set_bus_nr(int nr)
-{
-        u32 p2p = orion_read(PCI_P2P_CONF);
-
-        if (orion_read(PCI_MODE) & PCI_MODE_PCIX) {
-                /*
-                 * PCI-X mode
-                 */
-                u32 pcix_status, bus, dev;
-                bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
-                dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
-                orion_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
-                pcix_status &= ~PCIX_STAT_BUS_MASK;
-                pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
-                orion_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
-        } else {
-                /*
-                 * PCI Conventional mode
-                 */
-                p2p &= ~PCI_P2P_BUS_MASK;
-                p2p |= (nr << PCI_P2P_BUS_OFFS);
-                orion_write(PCI_P2P_CONF, p2p);
-        }
-}
-
-static void orion_pci_master_slave_enable(void)
-{
-        u32 bus_nr, dev_nr, func, reg, val;
-
-        bus_nr = orion_pci_local_bus_nr();
-        dev_nr = orion_pci_local_dev_nr();
-        func = PCI_CONF_FUNC_STAT_CMD;
-        reg = PCI_CONF_REG_STAT_CMD;
-        orion_pci_hw_rd_conf(bus_nr, dev_nr, func, reg, 4, &val);
-        val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-        orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7);
-}
-
-static int orion_pci_setup(struct pci_sys_data *sys)
-{
-        struct resource *res;
-
-        /*
-         * Master + Slave enable
-         */
-        orion_pci_master_slave_enable();
-
-        /*
-         * Force ordering
-         */
-        orion_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
-
-        /*
-         * Request resources
-         */
-        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-        if (!res)
-                panic("orion_pci_setup unable to alloc resources");
-
-        /*
-         * IORESOURCE_IO
-         */
-        res[0].name = "PCI I/O Space";
-        res[0].flags = IORESOURCE_IO;
-        res[0].start = ORION_PCI_IO_BUS_BASE;
-        res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
-        if (request_resource(&ioport_resource, &res[0]))
-                panic("Request PCI IO resource failed\n");
-        sys->resource[0] = &res[0];
-
-        /*
-         * IORESOURCE_MEM
-         */
-        res[1].name = "PCI Memory Space";
-        res[1].flags = IORESOURCE_MEM;
-        res[1].start = ORION_PCI_MEM_PHYS_BASE;
-        res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
-        if (request_resource(&iomem_resource, &res[1]))
-                panic("Request PCI Memory resource failed\n");
-        sys->resource[1] = &res[1];
-
-        sys->resource[2] = NULL;
-        sys->io_offset = 0;
-
-        return 1;
-}
-
-
-/*****************************************************************************
- * General PCIE + PCI
- ****************************************************************************/
-int orion_pci_sys_setup(int nr, struct pci_sys_data *sys)
-{
-        int ret = 0;
-
-        if (nr == 0) {
-                /*
-                 * PCIE setup
-                 */
-                orion_pcie_set_bus_nr(0);
-                ret = orion_pcie_setup(sys);
-        } else if (nr == 1) {
-                /*
-                 * PCI setup
-                 */
-                ret = orion_pci_setup(sys);
-        }
-
-        return ret;
-}
-
-struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
-{
-        struct pci_ops *ops;
-        struct pci_bus *bus;
-
-
-        if (nr == 0) {
-                u32 pci_bus;
-                /*
-                 * PCIE scan
-                 */
-                ops = &orion_pcie_ops;
-                bus = pci_scan_bus(sys->busnr, ops, sys);
-                /*
-                 * Set local PCI bus number to follow PCIE bridges (if any)
-                 */
-                pci_bus = bus->number + bus->subordinate - bus->secondary + 1;
-                orion_pci_set_bus_nr(pci_bus);
-        } else if (nr == 1) {
-                /*
-                 * PCI scan
-                 */
-                ops = &orion_pci_ops;
-                bus = pci_scan_bus(sys->busnr, ops, sys);
-        } else {
-                BUG();
-                bus = NULL;
-        }
-
-        return bus;
-}
diff --git a/arch/arm/mach-orion/time.c b/arch/arm/mach-orion/time.c
deleted file mode 100644
index bd4262da4f40..000000000000
--- a/arch/arm/mach-orion/time.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * arch/arm/mach-orion/time.c
- *
- * Core time functions for Marvell Orion System On Chip
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <asm/mach/time.h>
-#include <asm/arch/orion.h>
-#include "common.h"
-
-/*
- * Timer0: clock_event_device, Tick.
- * Timer1: clocksource, Free running.
- * WatchDog: Not used.
- *
- * Timers are counting down.
- */
-#define CLOCKEVENT      0
-#define CLOCKSOURCE     1
-
-/*
- * Timers bits
- */
-#define BRIDGE_INT_TIMER(x)     (1 << ((x) + 1))
-#define TIMER_EN(x)             (1 << ((x) * 2))
-#define TIMER_RELOAD_EN(x)      (1 << (((x) * 2) + 1))
-#define BRIDGE_INT_TIMER_WD     (1 << 3)
-#define TIMER_WD_EN             (1 << 4)
-#define TIMER_WD_RELOAD_EN      (1 << 5)
-
-static cycle_t orion_clksrc_read(void)
-{
-        return (0xffffffff - orion_read(TIMER_VAL(CLOCKSOURCE)));
-}
-
-static struct clocksource orion_clksrc = {
-        .name           = "orion_clocksource",
-        .shift          = 20,
-        .rating         = 300,
-        .read           = orion_clksrc_read,
-        .mask           = CLOCKSOURCE_MASK(32),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static int
-orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
-{
-        unsigned long flags;
-
-        if (delta == 0)
-                return -ETIME;
-
-        local_irq_save(flags);
-
-        /*
-         * Clear and enable timer interrupt bit
-         */
-        orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
-        orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
-
-        /*
-         * Setup new timer value
-         */
-        orion_write(TIMER_VAL(CLOCKEVENT), delta);
-
-        /*
-         * Disable auto reload and kickoff the timer
-         */
-        orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT));
-        orion_setbits(TIMER_CTRL, TIMER_EN(CLOCKEVENT));
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-static void
-orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        if (mode == CLOCK_EVT_MODE_PERIODIC) {
-                /*
-                 * Setup latch cycles in timer and enable reload interrupt.
-                 */
-                orion_write(TIMER_VAL_RELOAD(CLOCKEVENT), LATCH);
-                orion_write(TIMER_VAL(CLOCKEVENT), LATCH);
-                orion_setbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
-                orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
-                                          TIMER_EN(CLOCKEVENT));
-        } else {
-                /*
-                 * Disable timer and interrupt
-                 */
-                orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKEVENT));
-                orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
-                orion_clrbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKEVENT) |
-                                          TIMER_EN(CLOCKEVENT));
-        }
-
-        local_irq_restore(flags);
-}
-
-static struct clock_event_device orion_clkevt = {
-        .name           = "orion_tick",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .shift          = 32,
-        .rating         = 300,
-        .cpumask        = CPU_MASK_CPU0,
-        .set_next_event = orion_clkevt_next_event,
-        .set_mode       = orion_clkevt_mode,
-};
-
-static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
-{
-        /*
-         * Clear cause bit and do event
-         */
-        orion_write(BRIDGE_CAUSE, ~BRIDGE_INT_TIMER(CLOCKEVENT));
-        orion_clkevt.event_handler(&orion_clkevt);
-        return IRQ_HANDLED;
-}
-
-static struct irqaction orion_timer_irq = {
-        .name           = "orion_tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER,
-        .handler        = orion_timer_interrupt
-};
-
-static void orion_timer_init(void)
-{
-        /*
-         * Setup clocksource free running timer (no interrupt on reload)
-         */
-        orion_write(TIMER_VAL(CLOCKSOURCE), 0xffffffff);
-        orion_write(TIMER_VAL_RELOAD(CLOCKSOURCE), 0xffffffff);
-        orion_clrbits(BRIDGE_MASK, BRIDGE_INT_TIMER(CLOCKSOURCE));
-        orion_setbits(TIMER_CTRL, TIMER_RELOAD_EN(CLOCKSOURCE) |
-                                  TIMER_EN(CLOCKSOURCE));
-
-        /*
-         * Register clocksource
-         */
-        orion_clksrc.mult =
-                clocksource_hz2mult(CLOCK_TICK_RATE, orion_clksrc.shift);
-
-        clocksource_register(&orion_clksrc);
-
-        /*
-         * Connect and enable tick handler
-         */
-        setup_irq(IRQ_ORION_BRIDGE, &orion_timer_irq);
-
-        /*
-         * Register clockevent
-         */
-        orion_clkevt.mult =
-                div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, orion_clkevt.shift);
-        orion_clkevt.max_delta_ns =
-                clockevent_delta2ns(0xfffffffe, &orion_clkevt);
-        orion_clkevt.min_delta_ns =
-                clockevent_delta2ns(1, &orion_clkevt);
-
-        clockevents_register_device(&orion_clkevt);
-}
-
-struct sys_timer orion_timer = {
-        .init = orion_timer_init,
-};
diff --git a/arch/arm/mach-orion/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 1dcbb6ac5a30..93debf336155 100644
--- a/arch/arm/mach-orion/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -1,4 +1,4 @@
-if ARCH_ORION
+if ARCH_ORION5X
 
 menu "Orion Implementations"
 
@@ -36,6 +36,14 @@ config MACH_TS209
           Say 'Y' here if you want your kernel to support the
           QNAP TS-109/TS-209 platform.
 
+config MACH_LINKSTATION_PRO
+        bool "Buffalo Linkstation Pro/Live"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          Buffalo Linkstation Pro/Live platform. Both v1 and
+          v2 devices are supported.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-orion/Makefile b/arch/arm/mach-orion5x/Makefile
index f91d937a73e8..9301bf55910b 100644
--- a/arch/arm/mach-orion/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -1,6 +1,7 @@
-obj-y                           += common.o addr-map.o pci.o gpio.o irq.o time.o
+obj-y                           += common.o addr-map.o pci.o gpio.o irq.o
 obj-$(CONFIG_MACH_DB88F5281)    += db88f5281-setup.o
 obj-$(CONFIG_MACH_RD88F5182)    += rd88f5182-setup.o
 obj-$(CONFIG_MACH_KUROBOX_PRO)  += kurobox_pro-setup.o
+obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o
 obj-$(CONFIG_MACH_DNS323)       += dns323-setup.o
 obj-$(CONFIG_MACH_TS209)        += ts209-setup.o
diff --git a/arch/arm/mach-orion/Makefile.boot b/arch/arm/mach-orion5x/Makefile.boot
index 67039c3e0c48..67039c3e0c48 100644
--- a/arch/arm/mach-orion/Makefile.boot
+++ b/arch/arm/mach-orion5x/Makefile.boot
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
new file mode 100644
index 000000000000..6b179371e0a2
--- /dev/null
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -0,0 +1,240 @@
+/*
+ * arch/arm/mach-orion5x/addr-map.c
+ *
+ * Address map functions for Marvell Orion 5x SoCs
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include "common.h"
+
+/*
+ * The Orion has fully programable address map. There's a separate address
+ * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
+ * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
+ * address decode windows that allow it to access any of the Orion resources.
+ *
+ * CPU address decoding --
+ * Linux assumes that it is the boot loader that already setup the access to
+ * DDR and internal registers.
+ * Setup access to PCI and PCI-E IO/MEM space is issued by this file.
+ * Setup access to various devices located on the device bus interface (e.g.
+ * flashes, RTC, etc) should be issued by machine-setup.c according to
+ * specific board population (by using orion5x_setup_*_win()).
+ *
+ * Non-CPU Masters address decoding --
+ * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
+ * banks only (the typical use case).
+ * Setup access for each master to DDR is issued by common.c.
+ *
+ * Note: although orion_setbits() and orion_clrbits() are not atomic
+ * no locking is necessary here since code in this file is only called
+ * at boot time when there is no concurrency issues.
+ */
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define TARGET_DDR              0
+#define TARGET_DEV_BUS          1
+#define TARGET_PCI              3
+#define TARGET_PCIE             4
+#define ATTR_DDR_CS(n)          (((n) ==0) ? 0xe :      \
+                                ((n) == 1) ? 0xd :      \
+                                ((n) == 2) ? 0xb :      \
+                                ((n) == 3) ? 0x7 : 0xf)
+#define ATTR_PCIE_MEM           0x59
+#define ATTR_PCIE_IO            0x51
+#define ATTR_PCIE_WA            0x79
+#define ATTR_PCI_MEM            0x59
+#define ATTR_PCI_IO             0x51
+#define ATTR_DEV_CS0            0x1e
+#define ATTR_DEV_CS1            0x1d
+#define ATTR_DEV_CS2            0x1b
+#define ATTR_DEV_BOOT           0xf
+#define WIN_EN                  1
+
+/*
+ * Helpers to get DDR bank info
+ */
+#define DDR_BASE_CS(n)          ORION5X_DDR_REG(0x1500 + ((n) * 8))
+#define DDR_SIZE_CS(n)          ORION5X_DDR_REG(0x1504 + ((n) * 8))
+#define DDR_MAX_CS              4
+#define DDR_REG_TO_SIZE(reg)    (((reg) | 0xffffff) + 1)
+#define DDR_REG_TO_BASE(reg)    ((reg) & 0xff000000)
+#define DDR_BANK_EN             1
+
+/*
+ * CPU Address Decode Windows registers
+ */
+#define CPU_WIN_CTRL(n)         ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
+#define CPU_WIN_BASE(n)         ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
+#define CPU_WIN_REMAP_LO(n)     ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
+#define CPU_WIN_REMAP_HI(n)     ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
+
+/*
+ * Gigabit Ethernet Address Decode Windows registers
+ */
+#define ETH_WIN_BASE(win)       ORION5X_ETH_REG(0x200 + ((win) * 8))
+#define ETH_WIN_SIZE(win)       ORION5X_ETH_REG(0x204 + ((win) * 8))
+#define ETH_WIN_REMAP(win)      ORION5X_ETH_REG(0x280 + ((win) * 4))
+#define ETH_WIN_EN              ORION5X_ETH_REG(0x290)
+#define ETH_WIN_PROT            ORION5X_ETH_REG(0x294)
+#define ETH_MAX_WIN             6
+#define ETH_MAX_REMAP_WIN       4
+
+
+struct mbus_dram_target_info orion5x_mbus_dram_info;
+
+static int __init orion5x_cpu_win_can_remap(int win)
+{
+        u32 dev, rev;
+
+        orion5x_pcie_id(&dev, &rev);
+        if ((dev == MV88F5281_DEV_ID && win < 4)
+            || (dev == MV88F5182_DEV_ID && win < 2)
+            || (dev == MV88F5181_DEV_ID && win < 2))
+                return 1;
+
+        return 0;
+}
+
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+                                 u8 target, u8 attr, int remap)
+{
+        orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000);
+        orion5x_write(CPU_WIN_CTRL(win),
+                ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
+
+        if (orion5x_cpu_win_can_remap(win)) {
+                if (remap < 0)
+                        remap = base;
+
+                orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
+                orion5x_write(CPU_WIN_REMAP_HI(win), 0);
+        }
+}
+
+void __init orion5x_setup_cpu_mbus_bridge(void)
+{
+        int i;
+        int cs;
+
+        /*
+         * First, disable and clear windows.
+         */
+        for (i = 0; i < 8; i++) {
+                orion5x_write(CPU_WIN_BASE(i), 0);
+                orion5x_write(CPU_WIN_CTRL(i), 0);
+                if (orion5x_cpu_win_can_remap(i)) {
+                        orion5x_write(CPU_WIN_REMAP_LO(i), 0);
+                        orion5x_write(CPU_WIN_REMAP_HI(i), 0);
+                }
+        }
+
+        /*
+         * Setup windows for PCI+PCIe IO+MEM space.
+         */
+        setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
+                TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
+        setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
+                TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
+        setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
+                TARGET_PCIE, ATTR_PCIE_MEM, -1);
+        setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
+                TARGET_PCI, ATTR_PCI_MEM, -1);
+
+        /*
+         * Setup MBUS dram target info.
+         */
+        orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+        for (i = 0, cs = 0; i < 4; i++) {
+                u32 base = readl(DDR_BASE_CS(i));
+                u32 size = readl(DDR_SIZE_CS(i));
+
+                /*
+                 * Chip select enabled?
+                 */
+                if (size & 1) {
+                        struct mbus_dram_window *w;
+
+                        w = &orion5x_mbus_dram_info.cs[cs++];
+                        w->cs_index = i;
+                        w->mbus_attr = 0xf & ~(1 << i);
+                        w->base = base & 0xff000000;
+                        w->size = (size | 0x00ffffff) + 1;
+                }
+        }
+        orion5x_mbus_dram_info.num_cs = cs;
+}
+
+void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
+{
+        setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
+}
+
+void __init orion5x_setup_dev0_win(u32 base, u32 size)
+{
+        setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
+}
+
+void __init orion5x_setup_dev1_win(u32 base, u32 size)
+{
+        setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
+}
+
+void __init orion5x_setup_dev2_win(u32 base, u32 size)
+{
+        setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
+}
+
+void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
+{
+        setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
+}
+
+void __init orion5x_setup_eth_wins(void)
+{
+        int i;
+
+        /*
+         * First, disable and clear windows
+         */
+        for (i = 0; i < ETH_MAX_WIN; i++) {
+                orion5x_write(ETH_WIN_BASE(i), 0);
+                orion5x_write(ETH_WIN_SIZE(i), 0);
+                orion5x_setbits(ETH_WIN_EN, 1 << i);
+                orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
+                if (i < ETH_MAX_REMAP_WIN)
+                        orion5x_write(ETH_WIN_REMAP(i), 0);
+        }
+
+        /*
+         * Setup windows for DDR banks.
+         */
+        for (i = 0; i < DDR_MAX_CS; i++) {
+                u32 base, size;
+                size = orion5x_read(DDR_SIZE_CS(i));
+                base = orion5x_read(DDR_BASE_CS(i));
+                if (size & DDR_BANK_EN) {
+                        base = DDR_REG_TO_BASE(base);
+                        size = DDR_REG_TO_SIZE(size);
+                        orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
+                        orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
+                                        (ATTR_DDR_CS(i) << 8) |
+                                        TARGET_DDR);
+                        orion5x_clrbits(ETH_WIN_EN, 1 << i);
+                        orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
+                }
+        }
+}
diff --git a/arch/arm/mach-orion/common.c b/arch/arm/mach-orion5x/common.c
index bbc2b4ec932c..439c7784af02 100644
--- a/arch/arm/mach-orion/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -1,12 +1,12 @@
 /*
- * arch/arm/mach-orion/common.c
+ * arch/arm/mach-orion5x/common.c
  *
- * Core functions for Marvell Orion System On Chip
+ * Core functions for Marvell Orion 5x SoCs
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -14,64 +14,71 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/mbus.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
+#include <linux/ata_platform.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/time.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/orion5x.h>
+#include <asm/plat-orion/ehci-orion.h>
+#include <asm/plat-orion/orion_nand.h>
+#include <asm/plat-orion/time.h>
 #include "common.h"
 
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
-static struct map_desc orion_io_desc[] __initdata = {
+static struct map_desc orion5x_io_desc[] __initdata = {
         {
-                .virtual        = ORION_REGS_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ORION_REGS_PHYS_BASE),
-                .length         = ORION_REGS_SIZE,
+                .virtual        = ORION5X_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
+                .length         = ORION5X_REGS_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = ORION_PCIE_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE),
-                .length         = ORION_PCIE_IO_SIZE,
+                .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
+                .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
+                .length         = ORION5X_PCIE_IO_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = ORION_PCI_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE),
-                .length         = ORION_PCI_IO_SIZE,
+                .virtual        = ORION5X_PCI_IO_VIRT_BASE,
+                .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
+                .length         = ORION5X_PCI_IO_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = ORION_PCIE_WA_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE),
-                .length         = ORION_PCIE_WA_SIZE,
+                .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
+                .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
+                .length         = ORION5X_PCIE_WA_SIZE,
                 .type           = MT_DEVICE
         },
 };
 
-void __init orion_map_io(void)
+void __init orion5x_map_io(void)
 {
-        iotable_init(orion_io_desc, ARRAY_SIZE(orion_io_desc));
+        iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
 }
 
 /*****************************************************************************
  * UART
  ****************************************************************************/
 
-static struct resource orion_uart_resources[] = {
+static struct resource orion5x_uart_resources[] = {
         {
                 .start          = UART0_PHYS_BASE,
                 .end            = UART0_PHYS_BASE + 0xff,
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = IRQ_ORION_UART0,
-                .end            = IRQ_ORION_UART0,
+                .start          = IRQ_ORION5X_UART0,
+                .end            = IRQ_ORION5X_UART0,
                 .flags          = IORESOURCE_IRQ,
         },
         {
@@ -80,96 +87,102 @@ static struct resource orion_uart_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         {
-                .start          = IRQ_ORION_UART1,
-                .end            = IRQ_ORION_UART1,
+                .start          = IRQ_ORION5X_UART1,
+                .end            = IRQ_ORION5X_UART1,
                 .flags          = IORESOURCE_IRQ,
         },
 };
 
-static struct plat_serial8250_port orion_uart_data[] = {
+static struct plat_serial8250_port orion5x_uart_data[] = {
         {
                 .mapbase        = UART0_PHYS_BASE,
                 .membase        = (char *)UART0_VIRT_BASE,
-                .irq            = IRQ_ORION_UART0,
+                .irq            = IRQ_ORION5X_UART0,
                 .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
                 .iotype         = UPIO_MEM,
                 .regshift       = 2,
-                .uartclk        = ORION_TCLK,
+                .uartclk        = ORION5X_TCLK,
         },
         {
                 .mapbase        = UART1_PHYS_BASE,
                 .membase        = (char *)UART1_VIRT_BASE,
-                .irq            = IRQ_ORION_UART1,
+                .irq            = IRQ_ORION5X_UART1,
                 .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
                 .iotype         = UPIO_MEM,
                 .regshift       = 2,
-                .uartclk        = ORION_TCLK,
+                .uartclk        = ORION5X_TCLK,
         },
         { },
 };
 
-static struct platform_device orion_uart = {
+static struct platform_device orion5x_uart = {
         .name                   = "serial8250",
         .id                     = PLAT8250_DEV_PLATFORM,
         .dev                    = {
-                .platform_data  = orion_uart_data,
+                .platform_data  = orion5x_uart_data,
         },
-        .resource               = orion_uart_resources,
-        .num_resources          = ARRAY_SIZE(orion_uart_resources),
+        .resource               = orion5x_uart_resources,
+        .num_resources          = ARRAY_SIZE(orion5x_uart_resources),
 };
 
 /*******************************************************************************
  * USB Controller - 2 interfaces
  ******************************************************************************/
 
-static struct resource orion_ehci0_resources[] = {
+static struct resource orion5x_ehci0_resources[] = {
         {
-                .start  = ORION_USB0_PHYS_BASE,
-                .end    = ORION_USB0_PHYS_BASE + SZ_4K,
+                .start  = ORION5X_USB0_PHYS_BASE,
+                .end    = ORION5X_USB0_PHYS_BASE + SZ_4K,
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IRQ_ORION_USB0_CTRL,
-                .end    = IRQ_ORION_USB0_CTRL,
+                .start  = IRQ_ORION5X_USB0_CTRL,
+                .end    = IRQ_ORION5X_USB0_CTRL,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-static struct resource orion_ehci1_resources[] = {
+static struct resource orion5x_ehci1_resources[] = {
         {
-                .start  = ORION_USB1_PHYS_BASE,
-                .end    = ORION_USB1_PHYS_BASE + SZ_4K,
+                .start  = ORION5X_USB1_PHYS_BASE,
+                .end    = ORION5X_USB1_PHYS_BASE + SZ_4K,
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IRQ_ORION_USB1_CTRL,
-                .end    = IRQ_ORION_USB1_CTRL,
+                .start  = IRQ_ORION5X_USB1_CTRL,
+                .end    = IRQ_ORION5X_USB1_CTRL,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
+static struct orion_ehci_data orion5x_ehci_data = {
+        .dram           = &orion5x_mbus_dram_info,
+};
+
 static u64 ehci_dmamask = 0xffffffffUL;
 
-static struct platform_device orion_ehci0 = {
+static struct platform_device orion5x_ehci0 = {
         .name           = "orion-ehci",
         .id             = 0,
         .dev            = {
                 .dma_mask               = &ehci_dmamask,
                 .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &orion5x_ehci_data,
         },
-        .resource       = orion_ehci0_resources,
-        .num_resources  = ARRAY_SIZE(orion_ehci0_resources),
+        .resource       = orion5x_ehci0_resources,
+        .num_resources  = ARRAY_SIZE(orion5x_ehci0_resources),
 };
 
-static struct platform_device orion_ehci1 = {
+static struct platform_device orion5x_ehci1 = {
         .name           = "orion-ehci",
         .id             = 1,
         .dev            = {
                 .dma_mask               = &ehci_dmamask,
                 .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &orion5x_ehci_data,
         },
-        .resource       = orion_ehci1_resources,
-        .num_resources  = ARRAY_SIZE(orion_ehci1_resources),
+        .resource       = orion5x_ehci1_resources,
+        .num_resources  = ARRAY_SIZE(orion5x_ehci1_resources),
 };
 
 /*****************************************************************************
@@ -177,42 +190,42 @@ static struct platform_device orion_ehci1 = {
  * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
  ****************************************************************************/
 
-static struct resource orion_eth_shared_resources[] = {
+static struct resource orion5x_eth_shared_resources[] = {
         {
-                .start  = ORION_ETH_PHYS_BASE + 0x2000,
-                .end    = ORION_ETH_PHYS_BASE + 0x3fff,
+                .start  = ORION5X_ETH_PHYS_BASE + 0x2000,
+                .end    = ORION5X_ETH_PHYS_BASE + 0x3fff,
                 .flags  = IORESOURCE_MEM,
         },
 };
 
-static struct platform_device orion_eth_shared = {
+static struct platform_device orion5x_eth_shared = {
         .name           = MV643XX_ETH_SHARED_NAME,
         .id             = 0,
         .num_resources  = 1,
-        .resource       = orion_eth_shared_resources,
+        .resource       = orion5x_eth_shared_resources,
 };
 
-static struct resource orion_eth_resources[] = {
+static struct resource orion5x_eth_resources[] = {
         {
                 .name   = "eth irq",
-                .start  = IRQ_ORION_ETH_SUM,
-                .end    = IRQ_ORION_ETH_SUM,
+                .start  = IRQ_ORION5X_ETH_SUM,
+                .end    = IRQ_ORION5X_ETH_SUM,
                 .flags  = IORESOURCE_IRQ,
         }
 };
 
-static struct platform_device orion_eth = {
+static struct platform_device orion5x_eth = {
         .name           = MV643XX_ETH_NAME,
         .id             = 0,
         .num_resources  = 1,
-        .resource       = orion_eth_resources,
+        .resource       = orion5x_eth_resources,
 };
 
-void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data)
+void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_eth.dev.platform_data = eth_data;
-        platform_device_register(&orion_eth_shared);
-        platform_device_register(&orion_eth);
+        orion5x_eth.dev.platform_data = eth_data;
+        platform_device_register(&orion5x_eth_shared);
+        platform_device_register(&orion5x_eth);
 }
 
 /*****************************************************************************
@@ -220,13 +233,13 @@ void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data)
  * (The Orion and Discovery (MV643xx) families share the same I2C controller)
  ****************************************************************************/
 
-static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
+static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
         .freq_m         = 8, /* assumes 166 MHz TCLK */
         .freq_n         = 3,
         .timeout        = 1000, /* Default timeout of 1 second */
 };
 
-static struct resource orion_i2c_resources[] = {
+static struct resource orion5x_i2c_resources[] = {
         {
                 .name   = "i2c base",
                 .start  = I2C_PHYS_BASE,
@@ -235,66 +248,80 @@ static struct resource orion_i2c_resources[] = {
         },
         {
                 .name   = "i2c irq",
-                .start  = IRQ_ORION_I2C,
-                .end    = IRQ_ORION_I2C,
+                .start  = IRQ_ORION5X_I2C,
+                .end    = IRQ_ORION5X_I2C,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-static struct platform_device orion_i2c = {
+static struct platform_device orion5x_i2c = {
         .name           = MV64XXX_I2C_CTLR_NAME,
         .id             = 0,
-        .num_resources  = ARRAY_SIZE(orion_i2c_resources),
-        .resource       = orion_i2c_resources,
+        .num_resources  = ARRAY_SIZE(orion5x_i2c_resources),
+        .resource       = orion5x_i2c_resources,
         .dev            = {
-                .platform_data = &orion_i2c_pdata,
+                .platform_data = &orion5x_i2c_pdata,
         },
 };
 
 /*****************************************************************************
  * Sata port
  ****************************************************************************/
-static struct resource orion_sata_resources[] = {
+static struct resource orion5x_sata_resources[] = {
         {
                 .name   = "sata base",
-                .start  = ORION_SATA_PHYS_BASE,
-                .end    = ORION_SATA_PHYS_BASE + 0x5000 - 1,
+                .start  = ORION5X_SATA_PHYS_BASE,
+                .end    = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {
                 .name   = "sata irq",
-                .start  = IRQ_ORION_SATA,
-                .end    = IRQ_ORION_SATA,
+                .start  = IRQ_ORION5X_SATA,
+                .end    = IRQ_ORION5X_SATA,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-static struct platform_device orion_sata = {
+static struct platform_device orion5x_sata = {
         .name           = "sata_mv",
         .id             = 0,
         .dev            = {
                 .coherent_dma_mask      = 0xffffffff,
         },
-        .num_resources  = ARRAY_SIZE(orion_sata_resources),
-        .resource       = orion_sata_resources,
+        .num_resources  = ARRAY_SIZE(orion5x_sata_resources),
+        .resource       = orion5x_sata_resources,
 };
 
-void __init orion_sata_init(struct mv_sata_platform_data *sata_data)
+void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        orion_sata.dev.platform_data = sata_data;
-        platform_device_register(&orion_sata);
+        sata_data->dram = &orion5x_mbus_dram_info;
+        orion5x_sata.dev.platform_data = sata_data;
+        platform_device_register(&orion5x_sata);
 }
 
 /*****************************************************************************
+ * Time handling
+ ****************************************************************************/
+
+static void orion5x_timer_init(void)
+{
+        orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
+}
+
+struct sys_timer orion5x_timer = {
+        .init = orion5x_timer_init,
+};
+
+/*****************************************************************************
  * General
  ****************************************************************************/
 
 /*
  * Identify device ID and rev from PCIE configuration header space '0'.
  */
-static void orion_id(u32 *dev, u32 *rev, char **dev_name)
+static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
 {
-        orion_pcie_id(dev, rev);
+        orion5x_pcie_id(dev, rev);
 
         if (*dev == MV88F5281_DEV_ID) {
                 if (*rev == MV88F5281_REV_D2) {
@@ -321,33 +348,28 @@ static void orion_id(u32 *dev, u32 *rev, char **dev_name)
         }
 }
 
-void __init orion_init(void)
+void __init orion5x_init(void)
 {
         char *dev_name;
         u32 dev, rev;
 
-        orion_id(&dev, &rev, &dev_name);
-        printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION_TCLK);
+        orion5x_id(&dev, &rev, &dev_name);
+        printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, ORION5X_TCLK);
 
         /*
          * Setup Orion address map
          */
-        orion_setup_cpu_wins();
-        orion_setup_usb_wins();
-        orion_setup_eth_wins();
-        orion_setup_pci_wins();
-        orion_setup_pcie_wins();
-        if (dev == MV88F5182_DEV_ID)
-                orion_setup_sata_wins();
+        orion5x_setup_cpu_mbus_bridge();
+        orion5x_setup_eth_wins();
 
         /*
-         * REgister devices
+         * Register devices.
          */
-        platform_device_register(&orion_uart);
-        platform_device_register(&orion_ehci0);
+        platform_device_register(&orion5x_uart);
+        platform_device_register(&orion5x_ehci0);
         if (dev == MV88F5182_DEV_ID)
-                platform_device_register(&orion_ehci1);
-        platform_device_register(&orion_i2c);
+                platform_device_register(&orion5x_ehci1);
+        platform_device_register(&orion5x_i2c);
 }
 
 /*
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
new file mode 100644
index 000000000000..f4c4c9a72a7c
--- /dev/null
+++ b/arch/arm/mach-orion5x/common.h
@@ -0,0 +1,72 @@
+#ifndef __ARCH_ORION5X_COMMON_H
+#define __ARCH_ORION5X_COMMON_H
+
+/*
+ * Basic Orion init functions used early by machine-setup.
+ */
+
+void orion5x_map_io(void);
+void orion5x_init_irq(void);
+void orion5x_init(void);
+extern struct sys_timer orion5x_timer;
+
+/*
+ * Enumerations and functions for Orion windows mapping. Used by Orion core
+ * functions to map its interfaces and by the machine-setup to map its on-
+ * board devices. Details in /mach-orion/addr-map.c
+ */
+extern struct mbus_dram_target_info orion5x_mbus_dram_info;
+void orion5x_setup_cpu_mbus_bridge(void);
+void orion5x_setup_dev_boot_win(u32 base, u32 size);
+void orion5x_setup_dev0_win(u32 base, u32 size);
+void orion5x_setup_dev1_win(u32 base, u32 size);
+void orion5x_setup_dev2_win(u32 base, u32 size);
+void orion5x_setup_pcie_wa_win(u32 base, u32 size);
+void orion5x_setup_eth_wins(void);
+
+/*
+ * Shared code used internally by other Orion core functions.
+ * (/mach-orion/pci.c)
+ */
+
+struct pci_sys_data;
+struct pci_bus;
+
+void orion5x_pcie_id(u32 *dev, u32 *rev);
+int orion5x_pcie_local_bus_nr(void);
+int orion5x_pci_local_bus_nr(void);
+int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
+struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
+
+/*
+ * Valid GPIO pins according to MPP setup, used by machine-setup.
+ * (/mach-orion/gpio.c).
+ */
+
+void orion5x_gpio_set_valid_pins(u32 pins);
+void gpio_display(void);        /* debug */
+
+/*
+ * Pull in Orion Ethernet platform_data, used by machine-setup
+ */
+
+struct mv643xx_eth_platform_data;
+
+void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
+
+/*
+ * Orion Sata platform_data, used by machine-setup
+ */
+
+struct mv_sata_platform_data;
+
+void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
+
+struct machine_desc;
+struct meminfo;
+struct tag;
+extern void __init tag_fixup_mem32(struct machine_desc *, struct tag *,
+                                   char **, struct meminfo *);
+
+
+#endif
diff --git a/arch/arm/mach-orion/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 5ef44e1a2d36..872aed372327 100644
--- a/arch/arm/mach-orion/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -1,12 +1,12 @@
 /*
- * arch/arm/mach-orion/db88f5281-setup.c
+ * arch/arm/mach-orion5x/db88f5281-setup.c
  *
  * Marvell Orion-2 Development Board Setup
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -24,8 +24,8 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
+#include <asm/plat-orion/orion_nand.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -244,8 +244,8 @@ static int __init db88f5281_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         /*
          * PCIE IRQ is connected internally (not GPIO)
          */
-        if (dev->bus->number == orion_pcie_local_bus_nr())
-                return IRQ_ORION_PCIE0_INT;
+        if (dev->bus->number == orion5x_pcie_local_bus_nr())
+                return IRQ_ORION5X_PCIE0_INT;
 
         /*
          * PCI IRQs are connected via GPIOs
@@ -265,8 +265,8 @@ static struct hw_pci db88f5281_pci __initdata = {
         .nr_controllers = 2,
         .preinit        = db88f5281_pci_preinit,
         .swizzle        = pci_std_swizzle,
-        .setup          = orion_pci_sys_setup,
-        .scan           = orion_pci_sys_scan_bus,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
         .map_irq        = db88f5281_pci_map_irq,
 };
 
@@ -312,19 +312,16 @@ static void __init db88f5281_init(void)
         /*
          * Basic Orion setup. Need to be called early.
          */
-        orion_init();
+        orion5x_init();
 
         /*
          * Setup the CPU address decode windows for our on-board devices
          */
-        orion_setup_cpu_win(ORION_DEV_BOOT, DB88F5281_NOR_BOOT_BASE,
-                                DB88F5281_NOR_BOOT_SIZE, -1);
-        orion_setup_cpu_win(ORION_DEV0, DB88F5281_7SEG_BASE,
-                                DB88F5281_7SEG_SIZE, -1);
-        orion_setup_cpu_win(ORION_DEV1, DB88F5281_NOR_BASE,
-                                DB88F5281_NOR_SIZE, -1);
-        orion_setup_cpu_win(ORION_DEV2, DB88F5281_NAND_BASE,
-                                DB88F5281_NAND_SIZE, -1);
+        orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
+                                DB88F5281_NOR_BOOT_SIZE);
+        orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
+        orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
+        orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
 
         /*
          * Setup Multiplexing Pins:
@@ -340,25 +337,25 @@ static void __init db88f5281_init(void)
          * MPP18: UART1_CTS                     MPP19: UART1_RTS
          * MPP-DEV: DEV_D[16:31]
          */
-        orion_write(MPP_0_7_CTRL, 0x00222203);
-        orion_write(MPP_8_15_CTRL, 0x44000000);
-        orion_write(MPP_16_19_CTRL, 0);
-        orion_write(MPP_DEV_CTRL, 0);
+        orion5x_write(MPP_0_7_CTRL, 0x00222203);
+        orion5x_write(MPP_8_15_CTRL, 0x44000000);
+        orion5x_write(MPP_16_19_CTRL, 0);
+        orion5x_write(MPP_DEV_CTRL, 0);
 
-        orion_gpio_set_valid_pins(0x00003fc3);
+        orion5x_gpio_set_valid_pins(0x00003fc3);
 
         platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
         i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
-        orion_eth_init(&db88f5281_eth_data);
+        orion5x_eth_init(&db88f5281_eth_data);
 }
 
 MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
         /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
-        .phys_io        = ORION_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .init_machine   = db88f5281_init,
-        .map_io         = orion_map_io,
-        .init_irq       = orion_init_irq,
-        .timer          = &orion_timer,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 076e155ad510..d67790ef236e 100644
--- a/arch/arm/mach-orion/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-orion/dns323-setup.c
+ * arch/arm/mach-orion5x/dns323-setup.c
  *
  * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
  *
@@ -25,8 +25,7 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
 #include "common.h"
 
 #define DNS323_GPIO_LED_RIGHT_AMBER     1
@@ -45,8 +44,8 @@
 static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
         /* PCI-E */
-        if (dev->bus->number == orion_pcie_local_bus_nr())
-                return IRQ_ORION_PCIE0_INT;
+        if (dev->bus->number == orion5x_pcie_local_bus_nr())
+                return IRQ_ORION5X_PCIE0_INT;
 
         pr_err("%s: requested mapping for unknown bus\n", __func__);
 
@@ -56,8 +55,8 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 static struct hw_pci dns323_pci __initdata = {
         .nr_controllers = 1,
         .swizzle        = pci_std_swizzle,
-        .setup          = orion_pci_sys_setup,
-        .scan           = orion_pci_sys_scan_bus,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
         .map_irq        = dns323_pci_map_irq,
 };
 
@@ -247,27 +246,25 @@ static void dns323_power_off(void)
 static void __init dns323_init(void)
 {
         /* Setup basic Orion functions. Need to be called early. */
-        orion_init();
+        orion5x_init();
 
         /* setup flash mapping
          * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
          */
-        orion_setup_cpu_win(ORION_DEV_BOOT, DNS323_NOR_BOOT_BASE,
-                            DNS323_NOR_BOOT_SIZE, -1);
+        orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
 
         /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIE
          *
          * Open a special address decode windows for the PCIE WA.
          */
-        orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
-        orion_write(ORION_REGS_VIRT_BASE | 0x20070,
-                    (0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+                                ORION5X_PCIE_WA_SIZE);
 
         /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
-        orion_write(MPP_0_7_CTRL, 0);
-        orion_write(MPP_8_15_CTRL, 0);
-        orion_write(MPP_16_19_CTRL, 0);
-        orion_write(MPP_DEV_CTRL, 0);
+        orion5x_write(MPP_0_7_CTRL, 0);
+        orion5x_write(MPP_8_15_CTRL, 0);
+        orion5x_write(MPP_16_19_CTRL, 0);
+        orion5x_write(MPP_DEV_CTRL, 0);
 
         /* Define used GPIO pins
 
@@ -290,7 +287,7 @@ static void __init dns323_init(void)
           | 14 | Out | //unknown//
           | 15 | Out | //unknown//
         */
-        orion_gpio_set_valid_pins(0x07f6);
+        orion5x_gpio_set_valid_pins(0x07f6);
 
         /* register dns323 specific power-off method */
         if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0)
@@ -306,18 +303,18 @@ static void __init dns323_init(void)
         i2c_register_board_info(0, dns323_i2c_devices,
                                 ARRAY_SIZE(dns323_i2c_devices));
 
-        orion_eth_init(&dns323_eth_data);
+        orion5x_eth_init(&dns323_eth_data);
 }
 
 /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
 MACHINE_START(DNS323, "D-Link DNS-323")
         /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
-        .phys_io        = ORION_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = dns323_init,
-        .map_io         = orion_map_io,
-        .init_irq       = orion_init_irq,
-        .timer          = &orion_timer,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
 MACHINE_END
diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion5x/gpio.c
index f713818c66a3..8108c316c426 100644
--- a/arch/arm/mach-orion/gpio.c
+++ b/arch/arm/mach-orion5x/gpio.c
@@ -1,12 +1,12 @@
 /*
- * arch/arm/mach-orion/gpio.c
+ * arch/arm/mach-orion5x/gpio.c
  *
  * GPIO functions for Marvell Orion System On Chip
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -16,14 +16,15 @@
 #include <linux/spinlock.h>
 #include <linux/bitops.h>
 #include <asm/gpio.h>
-#include <asm/arch/orion.h>
+#include <asm/io.h>
+#include <asm/arch/orion5x.h>
 #include "common.h"
 
 static DEFINE_SPINLOCK(gpio_lock);
 static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
 static const char *gpio_label[GPIO_MAX];  /* non null for allocated GPIOs */
 
-void __init orion_gpio_set_valid_pins(u32 pins)
+void __init orion5x_gpio_set_valid_pins(u32 pins)
 {
         gpio_valid[0] = pins;
 }
@@ -49,7 +50,7 @@ int gpio_direction_input(unsigned pin)
         if (!gpio_label[pin])
                 gpio_label[pin] = "?";
 
-        orion_setbits(GPIO_IO_CONF, 1 << pin);
+        orion5x_setbits(GPIO_IO_CONF, 1 << pin);
 
         spin_unlock_irqrestore(&gpio_lock, flags);
         return 0;
@@ -76,12 +77,12 @@ int gpio_direction_output(unsigned pin, int value)
                 gpio_label[pin] = "?";
 
         mask = 1 << pin;
-        orion_clrbits(GPIO_BLINK_EN, mask);
+        orion5x_clrbits(GPIO_BLINK_EN, mask);
         if (value)
-                orion_setbits(GPIO_OUT, mask);
+                orion5x_setbits(GPIO_OUT, mask);
         else
-                orion_clrbits(GPIO_OUT, mask);
-        orion_clrbits(GPIO_IO_CONF, mask);
+                orion5x_clrbits(GPIO_OUT, mask);
+        orion5x_clrbits(GPIO_IO_CONF, mask);
 
         spin_unlock_irqrestore(&gpio_lock, flags);
         return 0;
@@ -92,10 +93,10 @@ int gpio_get_value(unsigned pin)
 {
         int val, mask = 1 << pin;
 
-        if (orion_read(GPIO_IO_CONF) & mask)
-                val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL);
+        if (orion5x_read(GPIO_IO_CONF) & mask)
+                val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL);
         else
-                val = orion_read(GPIO_OUT);
+                val = orion5x_read(GPIO_OUT);
 
         return val & mask;
 }
@@ -108,32 +109,32 @@ void gpio_set_value(unsigned pin, int value)
 
         spin_lock_irqsave(&gpio_lock, flags);
 
-        orion_clrbits(GPIO_BLINK_EN, mask);
+        orion5x_clrbits(GPIO_BLINK_EN, mask);
         if (value)
-                orion_setbits(GPIO_OUT, mask);
+                orion5x_setbits(GPIO_OUT, mask);
         else
-                orion_clrbits(GPIO_OUT, mask);
+                orion5x_clrbits(GPIO_OUT, mask);
 
         spin_unlock_irqrestore(&gpio_lock, flags);
 }
 EXPORT_SYMBOL(gpio_set_value);
 
-void orion_gpio_set_blink(unsigned pin, int blink)
+void orion5x_gpio_set_blink(unsigned pin, int blink)
 {
         unsigned long flags;
         int mask = 1 << pin;
 
         spin_lock_irqsave(&gpio_lock, flags);
 
-        orion_clrbits(GPIO_OUT, mask);
+        orion5x_clrbits(GPIO_OUT, mask);
         if (blink)
-                orion_setbits(GPIO_BLINK_EN, mask);
+                orion5x_setbits(GPIO_BLINK_EN, mask);
         else
-                orion_clrbits(GPIO_BLINK_EN, mask);
+                orion5x_clrbits(GPIO_BLINK_EN, mask);
 
         spin_unlock_irqrestore(&gpio_lock, flags);
 }
-EXPORT_SYMBOL(orion_gpio_set_blink);
+EXPORT_SYMBOL(orion5x_gpio_set_blink);
 
 int gpio_request(unsigned pin, const char *label)
 {
@@ -187,39 +188,39 @@ void gpio_display(void)
                         printk("GPIO, free\n");
                 } else {
                         printk("GPIO, used by %s, ", gpio_label[i]);
-                        if (orion_read(GPIO_IO_CONF) & (1 << i)) {
+                        if (orion5x_read(GPIO_IO_CONF) & (1 << i)) {
                                 printk("input, active %s, level %s, edge %s\n",
-                                ((orion_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
-                                ((orion_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
-                                ((orion_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
+                                ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
+                                ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
+                                ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
                         } else {
-                                printk("output, val=%d\n", (orion_read(GPIO_OUT) >> i) & 1);
+                                printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1);
                         }
                 }
         }
 
         printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_0_7_CTRL, orion_read(MPP_0_7_CTRL));
+                                MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL));
         printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_8_15_CTRL, orion_read(MPP_8_15_CTRL));
+                                MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL));
         printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_16_19_CTRL, orion_read(MPP_16_19_CTRL));
+                                MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL));
         printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n",
-                                MPP_DEV_CTRL, orion_read(MPP_DEV_CTRL));
+                                MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL));
         printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n",
-                                GPIO_OUT, orion_read(GPIO_OUT));
+                                GPIO_OUT, orion5x_read(GPIO_OUT));
         printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n",
-                                GPIO_IO_CONF, orion_read(GPIO_IO_CONF));
+                                GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF));
         printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n",
-                                GPIO_BLINK_EN, orion_read(GPIO_BLINK_EN));
+                                GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN));
         printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n",
-                                GPIO_IN_POL, orion_read(GPIO_IN_POL));
+                                GPIO_IN_POL, orion5x_read(GPIO_IN_POL));
         printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n",
-                                GPIO_DATA_IN, orion_read(GPIO_DATA_IN));
+                                GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN));
         printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n",
-                                GPIO_LEVEL_MASK, orion_read(GPIO_LEVEL_MASK));
+                                GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK));
         printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n",
-                                GPIO_EDGE_CAUSE, orion_read(GPIO_EDGE_CAUSE));
+                                GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE));
         printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n",
-                                GPIO_EDGE_MASK, orion_read(GPIO_EDGE_MASK));
+                                GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK));
 }
diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion5x/irq.c
index df7e12ad378b..dd21f38c5d37 100644
--- a/arch/arm/mach-orion/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -1,12 +1,12 @@
 /*
- * arch/arm/mach-orion/irq.c
+ * arch/arm/mach-orion5x/irq.c
  *
  * Core IRQ functions for Marvell Orion System On Chip
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
  *
  * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -14,7 +14,9 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <asm/gpio.h>
-#include <asm/arch/orion.h>
+#include <asm/io.h>
+#include <asm/arch/orion5x.h>
+#include <asm/plat-orion/irq.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -42,46 +44,46 @@
  *        polarity    LEVEL          mask
  *
  ****************************************************************************/
-static void orion_gpio_irq_ack(u32 irq)
+static void orion5x_gpio_irq_ack(u32 irq)
 {
         int pin = irq_to_gpio(irq);
         if (irq_desc[irq].status & IRQ_LEVEL)
                 /*
                  * Mask bit for level interrupt
                  */
-                orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
+                orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
         else
                 /*
                  * Clear casue bit for egde interrupt
                  */
-                orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
+                orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
 }
 
-static void orion_gpio_irq_mask(u32 irq)
+static void orion5x_gpio_irq_mask(u32 irq)
 {
         int pin = irq_to_gpio(irq);
         if (irq_desc[irq].status & IRQ_LEVEL)
-                orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
+                orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
         else
-                orion_clrbits(GPIO_EDGE_MASK, 1 << pin);
+                orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin);
 }
 
-static void orion_gpio_irq_unmask(u32 irq)
+static void orion5x_gpio_irq_unmask(u32 irq)
 {
         int pin = irq_to_gpio(irq);
         if (irq_desc[irq].status & IRQ_LEVEL)
-                orion_setbits(GPIO_LEVEL_MASK, 1 << pin);
+                orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin);
         else
-                orion_setbits(GPIO_EDGE_MASK, 1 << pin);
+                orion5x_setbits(GPIO_EDGE_MASK, 1 << pin);
 }
 
-static int orion_gpio_set_irq_type(u32 irq, u32 type)
+static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
 {
         int pin = irq_to_gpio(irq);
         struct irq_desc *desc;
 
-        if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
-                printk(KERN_ERR "orion_gpio_set_irq_type failed "
+        if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
+                printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
                                 "(irq %d, pin %d).\n", irq, pin);
                 return -EINVAL;
         }
@@ -92,22 +94,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type)
         case IRQT_HIGH:
                 desc->handle_irq = handle_level_irq;
                 desc->status |= IRQ_LEVEL;
-                orion_clrbits(GPIO_IN_POL, (1 << pin));
+                orion5x_clrbits(GPIO_IN_POL, (1 << pin));
                 break;
         case IRQT_LOW:
                 desc->handle_irq = handle_level_irq;
                 desc->status |= IRQ_LEVEL;
-                orion_setbits(GPIO_IN_POL, (1 << pin));
+                orion5x_setbits(GPIO_IN_POL, (1 << pin));
                 break;
         case IRQT_RISING:
                 desc->handle_irq = handle_edge_irq;
                 desc->status &= ~IRQ_LEVEL;
-                orion_clrbits(GPIO_IN_POL, (1 << pin));
+                orion5x_clrbits(GPIO_IN_POL, (1 << pin));
                 break;
         case IRQT_FALLING:
                 desc->handle_irq = handle_edge_irq;
                 desc->status &= ~IRQ_LEVEL;
-                orion_setbits(GPIO_IN_POL, (1 << pin));
+                orion5x_setbits(GPIO_IN_POL, (1 << pin));
                 break;
         case IRQT_BOTHEDGE:
                 desc->handle_irq = handle_edge_irq;
@@ -115,11 +117,11 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type)
                 /*
                  * set initial polarity based on current input level
                  */
-                if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN))
+                if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN))
                     & (1 << pin))
-                        orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
+                        orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
                 else
-                        orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
+                        orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
 
                 break;
         default:
@@ -133,22 +135,22 @@ static int orion_gpio_set_irq_type(u32 irq, u32 type)
         return 0;
 }
 
-static struct irq_chip orion_gpio_irq_chip = {
+static struct irq_chip orion5x_gpio_irq_chip = {
         .name           = "Orion-IRQ-GPIO",
-        .ack            = orion_gpio_irq_ack,
-        .mask           = orion_gpio_irq_mask,
-        .unmask         = orion_gpio_irq_unmask,
-        .set_type       = orion_gpio_set_irq_type,
+        .ack            = orion5x_gpio_irq_ack,
+        .mask           = orion5x_gpio_irq_mask,
+        .unmask         = orion5x_gpio_irq_unmask,
+        .set_type       = orion5x_gpio_set_irq_type,
 };
 
-static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
         u32 cause, offs, pin;
 
-        BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31);
-        offs = (irq - IRQ_ORION_GPIO_0_7) * 8;
-        cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) |
-                (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK));
+        BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
+        offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
+        cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) |
+                (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK));
 
         for (pin = offs; pin < offs + 8; pin++) {
                 if (cause & (1 << pin)) {
@@ -156,16 +158,16 @@ static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                         desc = irq_desc + irq;
                         if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
                                 /* Swap polarity (race with GPIO line) */
-                                u32 polarity = orion_read(GPIO_IN_POL);
+                                u32 polarity = orion5x_read(GPIO_IN_POL);
                                 polarity ^= 1 << pin;
-                                orion_write(GPIO_IN_POL, polarity);
+                                orion5x_write(GPIO_IN_POL, polarity);
                         }
                         desc_handle_irq(irq, desc);
                 }
         }
 }
 
-static void __init orion_init_gpio_irq(void)
+static void __init orion5x_init_gpio_irq(void)
 {
         int i;
         struct irq_desc *desc;
@@ -173,69 +175,37 @@ static void __init orion_init_gpio_irq(void)
         /*
          * Mask and clear GPIO IRQ interrupts
          */
-        orion_write(GPIO_LEVEL_MASK, 0x0);
-        orion_write(GPIO_EDGE_MASK, 0x0);
-        orion_write(GPIO_EDGE_CAUSE, 0x0);
+        orion5x_write(GPIO_LEVEL_MASK, 0x0);
+        orion5x_write(GPIO_EDGE_MASK, 0x0);
+        orion5x_write(GPIO_EDGE_CAUSE, 0x0);
 
         /*
          * Register chained level handlers for GPIO IRQs by default.
          * User can use set_type() if he wants to use edge types handlers.
          */
-        for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
+        for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
+                set_irq_chip(i, &orion5x_gpio_irq_chip);
                 set_irq_handler(i, handle_level_irq);
                 desc = irq_desc + i;
                 desc->status |= IRQ_LEVEL;
                 set_irq_flags(i, IRQF_VALID);
         }
-        set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler);
-        set_irq_chained_handler(IRQ_ORION_GPIO_8_15, orion_gpio_irq_handler);
-        set_irq_chained_handler(IRQ_ORION_GPIO_16_23, orion_gpio_irq_handler);
-        set_irq_chained_handler(IRQ_ORION_GPIO_24_31, orion_gpio_irq_handler);
+        set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler);
+        set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler);
+        set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler);
+        set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler);
 }
 
 /*****************************************************************************
  * Orion Main IRQ
  ****************************************************************************/
-static void orion_main_irq_mask(u32 irq)
+static void __init orion5x_init_main_irq(void)
 {
-        orion_clrbits(MAIN_IRQ_MASK, 1 << irq);
+        orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
 }
 
-static void orion_main_irq_unmask(u32 irq)
+void __init orion5x_init_irq(void)
 {
-        orion_setbits(MAIN_IRQ_MASK, 1 << irq);
-}
-
-static struct irq_chip orion_main_irq_chip = {
-        .name           = "Orion-IRQ-Main",
-        .ack            = orion_main_irq_mask,
-        .mask           = orion_main_irq_mask,
-        .unmask         = orion_main_irq_unmask,
-};
-
-static void __init orion_init_main_irq(void)
-{
-        int i;
-
-        /*
-         * Mask and clear Main IRQ interrupts
-         */
-        orion_write(MAIN_IRQ_MASK, 0x0);
-        orion_write(MAIN_IRQ_CAUSE, 0x0);
-
-        /*
-         * Register level handler for Main IRQs
-         */
-        for (i = 0; i < IRQ_ORION_GPIO_START; i++) {
-                set_irq_chip(i, &orion_main_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
-}
-
-void __init orion_init_irq(void)
-{
-        orion_init_main_irq();
-        orion_init_gpio_irq();
+        orion5x_init_main_irq();
+        orion5x_init_gpio_irq();
 }
diff --git a/arch/arm/mach-orion/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 785a07bdf1e2..91413455beba 100644
--- a/arch/arm/mach-orion/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -1,10 +1,10 @@
 /*
- * arch/arm/mach-orion/kurobox_pro-setup.c
+ * arch/arm/mach-orion5x/kurobox_pro-setup.c
  *
  * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -22,8 +22,8 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
+#include <asm/plat-orion/orion_nand.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -123,8 +123,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         /*
          * PCI isn't used on the Kuro
          */
-        if (dev->bus->number == orion_pcie_local_bus_nr())
-                return IRQ_ORION_PCIE0_INT;
+        if (dev->bus->number == orion5x_pcie_local_bus_nr())
+                return IRQ_ORION5X_PCIE0_INT;
         else
                 printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n");
 
@@ -134,8 +134,8 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 static struct hw_pci kurobox_pro_pci __initdata = {
         .nr_controllers = 1,
         .swizzle        = pci_std_swizzle,
-        .setup          = orion_pci_sys_setup,
-        .scan           = orion_pci_sys_scan_bus,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
         .map_irq        = kurobox_pro_pci_map_irq,
 };
 
@@ -178,31 +178,25 @@ static struct mv_sata_platform_data kurobox_pro_sata_data = {
  * General Setup
  ****************************************************************************/
 
-static struct platform_device *kurobox_pro_devices[] __initdata = {
-        &kurobox_pro_nor_flash,
-        &kurobox_pro_nand_flash,
-};
-
 static void __init kurobox_pro_init(void)
 {
         /*
          * Setup basic Orion functions. Need to be called early.
          */
-        orion_init();
+        orion5x_init();
 
         /*
          * Setup the CPU address decode windows for our devices
          */
-        orion_setup_cpu_win(ORION_DEV_BOOT, KUROBOX_PRO_NOR_BOOT_BASE,
-                                KUROBOX_PRO_NOR_BOOT_SIZE, -1);
-        orion_setup_cpu_win(ORION_DEV0, KUROBOX_PRO_NAND_BASE,
-                                KUROBOX_PRO_NAND_SIZE, -1);
+        orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
+                                KUROBOX_PRO_NOR_BOOT_SIZE);
+        orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE);
+
         /*
          * Open a special address decode windows for the PCIE WA.
          */
-        orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
-        orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
-                (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+                                ORION5X_PCIE_WA_SIZE);
 
         /*
          * Setup Multiplexing Pins --
@@ -219,26 +213,44 @@ static void __init kurobox_pro_init(void)
          * MPP[15] SATA 1 active indication
          * MPP[16-19] Not used
          */
-        orion_write(MPP_0_7_CTRL, 0x44220003);
-        orion_write(MPP_8_15_CTRL, 0x55550000);
-        orion_write(MPP_16_19_CTRL, 0x0);
+        orion5x_write(MPP_0_7_CTRL, 0x44220003);
+        orion5x_write(MPP_8_15_CTRL, 0x55550000);
+        orion5x_write(MPP_16_19_CTRL, 0x0);
 
-        orion_gpio_set_valid_pins(0x0000000c);
+        orion5x_gpio_set_valid_pins(0x0000000c);
 
-        platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices));
+        platform_device_register(&kurobox_pro_nor_flash);
+        if (machine_is_kurobox_pro())
+                platform_device_register(&kurobox_pro_nand_flash);
         i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
-        orion_eth_init(&kurobox_pro_eth_data);
-        orion_sata_init(&kurobox_pro_sata_data);
+        orion5x_eth_init(&kurobox_pro_eth_data);
+        orion5x_sata_init(&kurobox_pro_sata_data);
 }
 
+#ifdef CONFIG_MACH_KUROBOX_PRO
 MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
         /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
-        .phys_io        = ORION_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = kurobox_pro_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_LINKSTATION_PRO
+MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
+        /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = kurobox_pro_init,
-        .map_io         = orion_map_io,
-        .init_irq       = orion_init_irq,
-        .timer          = &orion_timer,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
 MACHINE_END
+#endif
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
new file mode 100644
index 000000000000..fdf99fca85b3
--- /dev/null
+++ b/arch/arm/mach-orion5x/pci.c
@@ -0,0 +1,559 @@
+/*
+ * arch/arm/mach-orion5x/pci.c
+ *
+ * PCI and PCIe functions for Marvell Orion System On Chip
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/plat-orion/pcie.h>
+#include "common.h"
+
+/*****************************************************************************
+ * Orion has one PCIe controller and one PCI controller.
+ *
+ * Note1: The local PCIe bus number is '0'. The local PCI bus number
+ * follows the scanned PCIe bridged busses, if any.
+ *
+ * Note2: It is possible for PCI/PCIe agents to access many subsystem's
+ * space, by configuring BARs and Address Decode Windows, e.g. flashes on
+ * device bus, Orion registers, etc. However this code only enable the
+ * access to DDR banks.
+ ****************************************************************************/
+
+
+/*****************************************************************************
+ * PCIe controller
+ ****************************************************************************/
+#define PCIE_BASE       ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
+
+void __init orion5x_pcie_id(u32 *dev, u32 *rev)
+{
+        *dev = orion_pcie_dev_id(PCIE_BASE);
+        *rev = orion_pcie_rev(PCIE_BASE);
+}
+
+int __init orion5x_pcie_local_bus_nr(void)
+{
+        return orion_pcie_get_local_bus_nr(PCIE_BASE);
+}
+
+static int pcie_valid_config(int bus, int dev)
+{
+        /*
+         * Don't go out when trying to access --
+         * 1. nonexisting device on local bus
+         * 2. where there's no device connected (no link)
+         */
+        if (bus == 0 && dev == 0)
+                return 1;
+
+        if (!orion_pcie_link_up(PCIE_BASE))
+                return 0;
+
+        if (bus == 0 && dev != 1)
+                return 0;
+
+        return 1;
+}
+
+
+/*
+ * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
+ * and then reading the PCIE_CONF_DATA register. Need to make sure these
+ * transactions are atomic.
+ */
+static DEFINE_SPINLOCK(orion5x_pcie_lock);
+
+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+                        int size, u32 *val)
+{
+        unsigned long flags;
+        int ret;
+
+        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        spin_lock_irqsave(&orion5x_pcie_lock, flags);
+        ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
+
+        return ret;
+}
+
+static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
+                           int where, int size, u32 *val)
+{
+        int ret;
+
+        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        /*
+         * We only support access to the non-extended configuration
+         * space when using the WA access method (or we would have to
+         * sacrifice 256M of CPU virtual address space.)
+         */
+        if (where >= 0x100) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
+                                    bus, devfn, where, size, val);
+
+        return ret;
+}
+
+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+                        int where, int size, u32 val)
+{
+        unsigned long flags;
+        int ret;
+
+        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        spin_lock_irqsave(&orion5x_pcie_lock, flags);
+        ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
+
+        return ret;
+}
+
+static struct pci_ops pcie_ops = {
+        .read = pcie_rd_conf,
+        .write = pcie_wr_conf,
+};
+
+
+static int __init pcie_setup(struct pci_sys_data *sys)
+{
+        struct resource *res;
+        int dev;
+
+        /*
+         * Generic PCIe unit setup.
+         */
+        orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
+
+        /*
+         * Check whether to apply Orion-1/Orion-NAS PCIe config
+         * read transaction workaround.
+         */
+        dev = orion_pcie_dev_id(PCIE_BASE);
+        if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
+                printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
+                                   "read transaction workaround\n");
+                pcie_ops.read = pcie_rd_conf_wa;
+        }
+
+        /*
+         * Request resources.
+         */
+        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+        if (!res)
+                panic("pcie_setup unable to alloc resources");
+
+        /*
+         * IORESOURCE_IO
+         */
+        res[0].name = "PCIe I/O Space";
+        res[0].flags = IORESOURCE_IO;
+        res[0].start = ORION5X_PCIE_IO_BUS_BASE;
+        res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
+        if (request_resource(&ioport_resource, &res[0]))
+                panic("Request PCIe IO resource failed\n");
+        sys->resource[0] = &res[0];
+
+        /*
+         * IORESOURCE_MEM
+         */
+        res[1].name = "PCIe Memory Space";
+        res[1].flags = IORESOURCE_MEM;
+        res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
+        res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
+        if (request_resource(&iomem_resource, &res[1]))
+                panic("Request PCIe Memory resource failed\n");
+        sys->resource[1] = &res[1];
+
+        sys->resource[2] = NULL;
+        sys->io_offset = 0;
+
+        return 1;
+}
+
+/*****************************************************************************
+ * PCI controller
+ ****************************************************************************/
+#define PCI_MODE                ORION5X_PCI_REG(0xd00)
+#define PCI_CMD                 ORION5X_PCI_REG(0xc00)
+#define PCI_P2P_CONF            ORION5X_PCI_REG(0x1d14)
+#define PCI_CONF_ADDR           ORION5X_PCI_REG(0xc78)
+#define PCI_CONF_DATA           ORION5X_PCI_REG(0xc7c)
+
+/*
+ * PCI_MODE bits
+ */
+#define PCI_MODE_64BIT                  (1 << 2)
+#define PCI_MODE_PCIX                   ((1 << 4) | (1 << 5))
+
+/*
+ * PCI_CMD bits
+ */
+#define PCI_CMD_HOST_REORDER            (1 << 29)
+
+/*
+ * PCI_P2P_CONF bits
+ */
+#define PCI_P2P_BUS_OFFS                16
+#define PCI_P2P_BUS_MASK                (0xff << PCI_P2P_BUS_OFFS)
+#define PCI_P2P_DEV_OFFS                24
+#define PCI_P2P_DEV_MASK                (0x1f << PCI_P2P_DEV_OFFS)
+
+/*
+ * PCI_CONF_ADDR bits
+ */
+#define PCI_CONF_REG(reg)               ((reg) & 0xfc)
+#define PCI_CONF_FUNC(func)             (((func) & 0x3) << 8)
+#define PCI_CONF_DEV(dev)               (((dev) & 0x1f) << 11)
+#define PCI_CONF_BUS(bus)               (((bus) & 0xff) << 16)
+#define PCI_CONF_ADDR_EN                (1 << 31)
+
+/*
+ * Internal configuration space
+ */
+#define PCI_CONF_FUNC_STAT_CMD          0
+#define PCI_CONF_REG_STAT_CMD           4
+#define PCIX_STAT                       0x64
+#define PCIX_STAT_BUS_OFFS              8
+#define PCIX_STAT_BUS_MASK              (0xff << PCIX_STAT_BUS_OFFS)
+
+/*
+ * PCI Address Decode Windows registers
+ */
+#define PCI_BAR_SIZE_DDR_CS(n)  (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
+                                ((n) == 1) ? ORION5X_PCI_REG(0xd08) :  \
+                                ((n) == 2) ? ORION5X_PCI_REG(0xc0c) :  \
+                                ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
+#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) :  \
+                                ((n) == 1) ? ORION5X_PCI_REG(0xd48) :  \
+                                ((n) == 2) ? ORION5X_PCI_REG(0xc4c) :  \
+                                ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
+#define PCI_BAR_ENABLE          ORION5X_PCI_REG(0xc3c)
+#define PCI_ADDR_DECODE_CTRL    ORION5X_PCI_REG(0xd3c)
+
+/*
+ * PCI configuration helpers for BAR settings
+ */
+#define PCI_CONF_FUNC_BAR_CS(n)         ((n) >> 1)
+#define PCI_CONF_REG_BAR_LO_CS(n)       (((n) & 1) ? 0x18 : 0x10)
+#define PCI_CONF_REG_BAR_HI_CS(n)       (((n) & 1) ? 0x1c : 0x14)
+
+/*
+ * PCI config cycles are done by programming the PCI_CONF_ADDR register
+ * and then reading the PCI_CONF_DATA register. Need to make sure these
+ * transactions are atomic.
+ */
+static DEFINE_SPINLOCK(orion5x_pci_lock);
+
+int orion5x_pci_local_bus_nr(void)
+{
+        u32 conf = orion5x_read(PCI_P2P_CONF);
+        return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
+}
+
+static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
+                                        u32 where, u32 size, u32 *val)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&orion5x_pci_lock, flags);
+
+        orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
+                        PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
+                        PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
+
+        *val = orion5x_read(PCI_CONF_DATA);
+
+        if (size == 1)
+                *val = (*val >> (8*(where & 0x3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8*(where & 0x3))) & 0xffff;
+
+        spin_unlock_irqrestore(&orion5x_pci_lock, flags);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
+                                        u32 where, u32 size, u32 val)
+{
+        unsigned long flags;
+        int ret = PCIBIOS_SUCCESSFUL;
+
+        spin_lock_irqsave(&orion5x_pci_lock, flags);
+
+        orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
+                        PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
+                        PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);
+
+        if (size == 4) {
+                __raw_writel(val, PCI_CONF_DATA);
+        } else if (size == 2) {
+                __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
+        } else if (size == 1) {
+                __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
+        } else {
+                ret = PCIBIOS_BAD_REGISTER_NUMBER;
+        }
+
+        spin_unlock_irqrestore(&orion5x_pci_lock, flags);
+
+        return ret;
+}
+
+static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
+                                int where, int size, u32 *val)
+{
+        /*
+         * Don't go out for local device
+         */
+        if (bus->number == orion5x_pci_local_bus_nr() &&
+            PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
+                                        PCI_FUNC(devfn), where, size, val);
+}
+
+static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
+                                int where, int size, u32 val)
+{
+        if (bus->number == orion5x_pci_local_bus_nr() &&
+            PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
+                                        PCI_FUNC(devfn), where, size, val);
+}
+
+static struct pci_ops pci_ops = {
+        .read = orion5x_pci_rd_conf,
+        .write = orion5x_pci_wr_conf,
+};
+
+static void __init orion5x_pci_set_bus_nr(int nr)
+{
+        u32 p2p = orion5x_read(PCI_P2P_CONF);
+
+        if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) {
+                /*
+                 * PCI-X mode
+                 */
+                u32 pcix_status, bus, dev;
+                bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
+                dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
+                orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
+                pcix_status &= ~PCIX_STAT_BUS_MASK;
+                pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
+                orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
+        } else {
+                /*
+                 * PCI Conventional mode
+                 */
+                p2p &= ~PCI_P2P_BUS_MASK;
+                p2p |= (nr << PCI_P2P_BUS_OFFS);
+                orion5x_write(PCI_P2P_CONF, p2p);
+        }
+}
+
+static void __init orion5x_pci_master_slave_enable(void)
+{
+        int bus_nr, func, reg;
+        u32 val;
+
+        bus_nr = orion5x_pci_local_bus_nr();
+        func = PCI_CONF_FUNC_STAT_CMD;
+        reg = PCI_CONF_REG_STAT_CMD;
+        orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
+        val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+        orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
+}
+
+static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
+{
+        u32 win_enable;
+        int bus;
+        int i;
+
+        /*
+         * First, disable windows.
+         */
+        win_enable = 0xffffffff;
+        orion5x_write(PCI_BAR_ENABLE, win_enable);
+
+        /*
+         * Setup windows for DDR banks.
+         */
+        bus = orion5x_pci_local_bus_nr();
+
+        for (i = 0; i < dram->num_cs; i++) {
+                struct mbus_dram_window *cs = dram->cs + i;
+                u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
+                u32 reg;
+                u32 val;
+
+                /*
+                 * Write DRAM bank base address register.
+                 */
+                reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
+                orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
+                val = (cs->base & 0xfffff000) | (val & 0xfff);
+                orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
+
+                /*
+                 * Write DRAM bank size register.
+                 */
+                reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
+                orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
+                orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
+                                (cs->size - 1) & 0xfffff000);
+                orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
+                                cs->base & 0xfffff000);
+
+                /*
+                 * Enable decode window for this chip select.
+                 */
+                win_enable &= ~(1 << cs->cs_index);
+        }
+
+        /*
+         * Re-enable decode windows.
+         */
+        orion5x_write(PCI_BAR_ENABLE, win_enable);
+
+        /*
+         * Disable automatic update of address remaping when writing to BARs.
+         */
+        orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
+}
+
+static int __init pci_setup(struct pci_sys_data *sys)
+{
+        struct resource *res;
+
+        /*
+         * Point PCI unit MBUS decode windows to DRAM space.
+         */
+        orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
+
+        /*
+         * Master + Slave enable
+         */
+        orion5x_pci_master_slave_enable();
+
+        /*
+         * Force ordering
+         */
+        orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
+
+        /*
+         * Request resources
+         */
+        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+        if (!res)
+                panic("pci_setup unable to alloc resources");
+
+        /*
+         * IORESOURCE_IO
+         */
+        res[0].name = "PCI I/O Space";
+        res[0].flags = IORESOURCE_IO;
+        res[0].start = ORION5X_PCI_IO_BUS_BASE;
+        res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
+        if (request_resource(&ioport_resource, &res[0]))
+                panic("Request PCI IO resource failed\n");
+        sys->resource[0] = &res[0];
+
+        /*
+         * IORESOURCE_MEM
+         */
+        res[1].name = "PCI Memory Space";
+        res[1].flags = IORESOURCE_MEM;
+        res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
+        res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
+        if (request_resource(&iomem_resource, &res[1]))
+                panic("Request PCI Memory resource failed\n");
+        sys->resource[1] = &res[1];
+
+        sys->resource[2] = NULL;
+        sys->io_offset = 0;
+
+        return 1;
+}
+
+
+/*****************************************************************************
+ * General PCIe + PCI
+ ****************************************************************************/
+static void __devinit rc_pci_fixup(struct pci_dev *dev)
+{
+        /*
+         * Prevent enumeration of root complex.
+         */
+        if (dev->bus->parent == NULL && dev->devfn == 0) {
+                int i;
+
+                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+                        dev->resource[i].start = 0;
+                        dev->resource[i].end   = 0;
+                        dev->resource[i].flags = 0;
+                }
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
+
+int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
+{
+        int ret = 0;
+
+        if (nr == 0) {
+                orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
+                ret = pcie_setup(sys);
+        } else if (nr == 1) {
+                orion5x_pci_set_bus_nr(sys->busnr);
+                ret = pci_setup(sys);
+        }
+
+        return ret;
+}
+
+struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        struct pci_bus *bus;
+
+        if (nr == 0) {
+                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+        } else if (nr == 1) {
+                bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
+        } else {
+                bus = NULL;
+                BUG();
+        }
+
+        return bus;
+}
diff --git a/arch/arm/mach-orion/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index e851b8ca5ac6..37e8b2dc3ed5 100644
--- a/arch/arm/mach-orion/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -1,12 +1,12 @@
 /*
- * arch/arm/mach-orion/rd88f5182-setup.c
+ * arch/arm/mach-orion5x/rd88f5182-setup.c
  *
  * Marvell Orion-NAS Reference Design Setup
  *
  * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -24,8 +24,7 @@
 #include <asm/leds.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -176,8 +175,8 @@ static int __init rd88f5182_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         /*
          * PCI-E isn't used on the RD2
          */
-        if (dev->bus->number == orion_pcie_local_bus_nr())
-                return IRQ_ORION_PCIE0_INT;
+        if (dev->bus->number == orion5x_pcie_local_bus_nr())
+                return IRQ_ORION5X_PCIE0_INT;
 
         /*
          * PCI IRQs are connected via GPIOs
@@ -197,8 +196,8 @@ static struct hw_pci rd88f5182_pci __initdata = {
         .nr_controllers = 2,
         .preinit        = rd88f5182_pci_preinit,
         .swizzle        = pci_std_swizzle,
-        .setup          = orion_pci_sys_setup,
-        .scan           = orion_pci_sys_scan_bus,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
         .map_irq        = rd88f5182_pci_map_irq,
 };
 
@@ -250,22 +249,20 @@ static void __init rd88f5182_init(void)
         /*
          * Setup basic Orion functions. Need to be called early.
          */
-        orion_init();
+        orion5x_init();
 
         /*
          * Setup the CPU address decode windows for our devices
          */
-        orion_setup_cpu_win(ORION_DEV_BOOT, RD88F5182_NOR_BOOT_BASE,
-                                RD88F5182_NOR_BOOT_SIZE, -1);
-        orion_setup_cpu_win(ORION_DEV1, RD88F5182_NOR_BASE,
-                                RD88F5182_NOR_SIZE, -1);
+        orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
+                                RD88F5182_NOR_BOOT_SIZE);
+        orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
 
         /*
          * Open a special address decode windows for the PCIE WA.
          */
-        orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
-        orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
-                (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+                                ORION5X_PCIE_WA_SIZE);
 
         /*
          * Setup Multiplexing Pins --
@@ -291,25 +288,25 @@ static void __init rd88f5182_init(void)
          * MPP[25] USB 0 over current enable
          */
 
-        orion_write(MPP_0_7_CTRL, 0x00000003);
-        orion_write(MPP_8_15_CTRL, 0x55550000);
-        orion_write(MPP_16_19_CTRL, 0x5555);
+        orion5x_write(MPP_0_7_CTRL, 0x00000003);
+        orion5x_write(MPP_8_15_CTRL, 0x55550000);
+        orion5x_write(MPP_16_19_CTRL, 0x5555);
 
-        orion_gpio_set_valid_pins(0x000000fb);
+        orion5x_gpio_set_valid_pins(0x000000fb);
 
         platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
         i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
-        orion_eth_init(&rd88f5182_eth_data);
-        orion_sata_init(&rd88f5182_sata_data);
+        orion5x_eth_init(&rd88f5182_eth_data);
+        orion5x_sata_init(&rd88f5182_sata_data);
 }
 
 MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
         /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
-        .phys_io        = ORION_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = rd88f5182_init,
-        .map_io         = orion_map_io,
-        .init_irq       = orion_init_irq,
-        .timer          = &orion_timer,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 45764dad16d0..fd43863a86f6 100644
--- a/arch/arm/mach-orion/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -26,8 +26,7 @@
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
-#include <asm/arch/orion.h>
-#include <asm/arch/platform.h>
+#include <asm/arch/orion5x.h>
 #include "common.h"
 
 #define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
@@ -145,8 +144,8 @@ static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
         /*
          * PCIE IRQ is connected internally (not GPIO)
          */
-        if (dev->bus->number == orion_pcie_local_bus_nr())
-                return IRQ_ORION_PCIE0_INT;
+        if (dev->bus->number == orion5x_pcie_local_bus_nr())
+                return IRQ_ORION5X_PCIE0_INT;
 
         /*
          * PCI IRQs are connected via GPIOs
@@ -165,8 +164,8 @@ static struct hw_pci qnap_ts209_pci __initdata = {
         .nr_controllers = 2,
         .preinit        = qnap_ts209_pci_preinit,
         .swizzle        = pci_std_swizzle,
-        .setup          = orion_pci_sys_setup,
-        .scan           = orion_pci_sys_scan_bus,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
         .map_irq        = qnap_ts209_pci_map_irq,
 };
 
@@ -189,6 +188,87 @@ static struct mv643xx_eth_platform_data qnap_ts209_eth_data = {
         .force_phy_addr = 1,
 };
 
+static int __init parse_hex_nibble(char n)
+{
+        if (n >= '0' && n <= '9')
+                return n - '0';
+
+        if (n >= 'A' && n <= 'F')
+                return n - 'A' + 10;
+
+        if (n >= 'a' && n <= 'f')
+                return n - 'a' + 10;
+
+        return -1;
+}
+
+static int __init parse_hex_byte(const char *b)
+{
+        int hi;
+        int lo;
+
+        hi = parse_hex_nibble(b[0]);
+        lo = parse_hex_nibble(b[1]);
+
+        if (hi < 0 || lo < 0)
+                return -1;
+
+        return (hi << 4) | lo;
+}
+
+static int __init check_mac_addr(const char *addr_str)
+{
+        u_int8_t addr[6];
+        int i;
+
+        for (i = 0; i < 6; i++) {
+                int byte;
+
+                /*
+                 * Enforce "xx:xx:xx:xx:xx:xx\n" format.
+                 */
+                if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
+                        return -1;
+
+                byte = parse_hex_byte(addr_str + (i * 3));
+                if (byte < 0)
+                        return -1;
+                addr[i] = byte;
+        }
+
+        printk(KERN_INFO "ts209: found ethernet mac address ");
+        for (i = 0; i < 6; i++)
+                printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
+
+        memcpy(qnap_ts209_eth_data.mac_addr, addr, 6);
+
+        return 0;
+}
+
+/*
+ * The 'NAS Config' flash partition has an ext2 filesystem which
+ * contains a file that has the ethernet MAC address in plain text
+ * (format "xx:xx:xx:xx:xx:xx\n".)
+ */
+static void __init ts209_find_mac_addr(void)
+{
+        unsigned long addr;
+
+        for (addr = 0x00700000; addr < 0x00760000; addr += 1024) {
+                char *nor_page;
+                int ret = 0;
+
+                nor_page = ioremap(QNAP_TS209_NOR_BOOT_BASE + addr, 1024);
+                if (nor_page != NULL) {
+                        ret = check_mac_addr(nor_page);
+                        iounmap(nor_page);
+                }
+
+                if (ret == 0)
+                        break;
+        }
+}
+
 /*****************************************************************************
  * RTC S35390A on I2C bus
  ****************************************************************************/
@@ -262,21 +342,21 @@ static struct platform_device *qnap_ts209_devices[] __initdata = {
 static void qnap_ts209_power_off(void)
 {
         /* 19200 baud divisor */
-        const unsigned divisor = ((ORION_TCLK + (8 * 19200)) / (16 * 19200));
+        const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
 
         pr_info("%s: triggering power-off...\n", __func__);
 
         /* hijack uart1 and reset into sane state (19200,8n1) */
-        orion_write(UART1_REG(LCR), 0x83);
-        orion_write(UART1_REG(DLL), divisor & 0xff);
-        orion_write(UART1_REG(DLM), (divisor >> 8) & 0xff);
-        orion_write(UART1_REG(LCR), 0x03);
-        orion_write(UART1_REG(IER), 0x00);
-        orion_write(UART1_REG(FCR), 0x00);
-        orion_write(UART1_REG(MCR), 0x00);
+        orion5x_write(UART1_REG(LCR), 0x83);
+        orion5x_write(UART1_REG(DLL), divisor & 0xff);
+        orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff);
+        orion5x_write(UART1_REG(LCR), 0x03);
+        orion5x_write(UART1_REG(IER), 0x00);
+        orion5x_write(UART1_REG(FCR), 0x00);
+        orion5x_write(UART1_REG(MCR), 0x00);
 
         /* send the power-off command 'A' to PIC */
-        orion_write(UART1_REG(TX), 'A');
+        orion5x_write(UART1_REG(TX), 'A');
 }
 
 static void __init qnap_ts209_init(void)
@@ -284,20 +364,19 @@ static void __init qnap_ts209_init(void)
         /*
          * Setup basic Orion functions. Need to be called early.
          */
-        orion_init();
+        orion5x_init();
 
         /*
          * Setup flash mapping
          */
-        orion_setup_cpu_win(ORION_DEV_BOOT, QNAP_TS209_NOR_BOOT_BASE,
-                            QNAP_TS209_NOR_BOOT_SIZE, -1);
+        orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
+                            QNAP_TS209_NOR_BOOT_SIZE);
 
         /*
          * Open a special address decode windows for the PCIE WA.
          */
-        orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
-        orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
-                (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
+        orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
+                                ORION5X_PCIE_WA_SIZE);
 
         /*
          * Setup Multiplexing Pins --
@@ -322,10 +401,10 @@ static void __init qnap_ts209_init(void)
          * MPP[22] USB 0 over current
          * MPP[23-25] Reserved
          */
-        orion_write(MPP_0_7_CTRL, 0x3);
-        orion_write(MPP_8_15_CTRL, 0x55550000);
-        orion_write(MPP_16_19_CTRL, 0x5500);
-        orion_gpio_set_valid_pins(0x3cc0fff);
+        orion5x_write(MPP_0_7_CTRL, 0x3);
+        orion5x_write(MPP_8_15_CTRL, 0x55550000);
+        orion5x_write(MPP_16_19_CTRL, 0x5500);
+        orion5x_gpio_set_valid_pins(0x3cc0fff);
 
         /* register ts209 specific power-off method */
         pm_power_off = qnap_ts209_power_off;
@@ -344,18 +423,20 @@ static void __init qnap_ts209_init(void)
                 pr_warning("qnap_ts209_init: failed to get RTC IRQ\n");
         i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
 
-        orion_eth_init(&qnap_ts209_eth_data);
-        orion_sata_init(&qnap_ts209_sata_data);
+        ts209_find_mac_addr();
+        orion5x_eth_init(&qnap_ts209_eth_data);
+
+        orion5x_sata_init(&qnap_ts209_sata_data);
 }
 
 MACHINE_START(TS209, "QNAP TS-109/TS-209")
         /* Maintainer:  Byron Bradley <byron.bbradley@gmail.com> */
-        .phys_io        = ORION_REGS_PHYS_BASE,
-        .io_pg_offst    = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts209_init,
-        .map_io         = orion_map_io,
-        .init_irq       = orion_init_irq,
-        .timer          = &orion_timer,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 0908bea0f609..5da7a6820492 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -23,6 +23,12 @@ endif
 choice
         prompt "Select target board"
 
+config ARCH_GUMSTIX
+        bool "Gumstix XScale boards"
+        help
+          Say Y here if you intend to run this kernel on a
+          Gumstix Full Function Minature Computer.
+
 config ARCH_LUBBOCK
         bool "Intel DBPXA250 Development Platform"
         select PXA25x
@@ -160,6 +166,20 @@ endchoice
 
 endif
 
+if ARCH_GUMSTIX
+
+choice
+        prompt "Select target Gumstix board"
+
+config MACH_GUMSTIX_F
+        bool "Basix, Connex, ws-200ax, ws-400ax systems"
+        select PXA25x
+
+endchoice
+
+endif
+
+
 if MACH_TRIZEPS4
 
 choice
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 6e0c4f5b5ae6..7cdcb459ea9d 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -5,13 +5,14 @@
 # Common support (must be linked before board specific support)
 obj-y                           += clock.o devices.o generic.o irq.o dma.o \
                                    time.o gpio.o
-obj-$(CONFIG_PXA25x)            += pxa25x.o
-obj-$(CONFIG_PXA27x)            += pxa27x.o
-obj-$(CONFIG_PXA3xx)            += pxa3xx.o mfp.o smemc.o
+obj-$(CONFIG_PXA25x)            += pxa25x.o mfp-pxa2xx.o
+obj-$(CONFIG_PXA27x)            += pxa27x.o mfp-pxa2xx.o
+obj-$(CONFIG_PXA3xx)            += pxa3xx.o mfp-pxa3xx.o smemc.o
 obj-$(CONFIG_CPU_PXA300)        += pxa300.o
 obj-$(CONFIG_CPU_PXA320)        += pxa320.o
 
 # Specific board support
+obj-$(CONFIG_ARCH_GUMSTIX)      += gumstix.o
 obj-$(CONFIG_ARCH_LUBBOCK)      += lubbock.o
 obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
 obj-$(CONFIG_MACH_MAINSTONE)    += mainstone.o
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index df5ae2710ab1..e97dc59813c8 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -13,6 +13,7 @@
 #include <linux/delay.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/hardware.h>
 
 #include "devices.h"
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c
index fcda7d5cb693..ac7f05f9f3eb 100644
--- a/arch/arm/mach-pxa/cm-x270-pci.c
+++ b/arch/arm/mach-pxa/cm-x270-pci.c
@@ -23,6 +23,7 @@
 #include <asm/mach/pci.h>
 #include <asm/arch/cm-x270.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/mach-types.h>
 
 #include <asm/hardware/it8152.h>
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index ecdbc96a4de1..6d4416a4f378 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -30,6 +30,7 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/mmc.h>
diff --git a/arch/arm/mach-pxa/colibri.c b/arch/arm/mach-pxa/colibri.c
index 6db54e31c397..43bf5a183e90 100644
--- a/arch/arm/mach-pxa/colibri.c
+++ b/arch/arm/mach-pxa/colibri.c
@@ -29,6 +29,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/flash.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/colibri.h>
 
 #include "generic.h"
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 9292576b83b3..259ca821e464 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -36,6 +36,7 @@
 #include <asm/mach/irq.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/udc.h>
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index 392c38717362..0a85f706e887 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -26,6 +26,7 @@
 #include <asm/arch/sharpsl.h>
 #include <asm/arch/corgi.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include "sharpsl.h"
 
 #define SHARPSL_CHARGE_ON_VOLT         0x99  /* 2.9V */
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c
index 31706224a04c..eccc45d21f75 100644
--- a/arch/arm/mach-pxa/corgi_ssp.c
+++ b/arch/arm/mach-pxa/corgi_ssp.c
@@ -21,6 +21,7 @@
 
 #include <asm/arch/ssp.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/regs-ssp.h>
 #include "sharpsl.h"
 
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index bfccb80ac8ef..d6c05b6eab35 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -11,6 +11,8 @@
 #include <asm/arch/irda.h>
 #include <asm/arch/i2c.h>
 #include <asm/arch/ohci.h>
+#include <asm/arch/pxa27x_keypad.h>
+#include <asm/arch/camera.h>
 
 #include "devices.h"
 
@@ -396,6 +398,31 @@ struct platform_device pxa25x_device_assp = {
 
 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 
+static struct resource pxa27x_resource_keypad[] = {
+        [0] = {
+                .start  = 0x41500000,
+                .end    = 0x4150004c,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_KEYPAD,
+                .end    = IRQ_KEYPAD,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa27x_device_keypad = {
+        .name           = "pxa27x-keypad",
+        .id             = -1,
+        .resource       = pxa27x_resource_keypad,
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_keypad),
+};
+
+void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
+{
+        pxa_register_device(&pxa27x_device_keypad, info);
+}
+
 static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
 
 static struct resource pxa27x_resource_ohci[] = {
@@ -540,6 +567,37 @@ struct platform_device pxa27x_device_ssp3 = {
         .resource       = pxa27x_resource_ssp3,
         .num_resources  = ARRAY_SIZE(pxa27x_resource_ssp3),
 };
+
+static struct resource pxa27x_resource_camera[] = {
+        [0] = {
+                .start  = 0x50000000,
+                .end    = 0x50000fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_CAMERA,
+                .end    = IRQ_CAMERA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
+
+static struct platform_device pxa27x_device_camera = {
+        .name           = "pxa27x-camera",
+        .id             = 0, /* This is used to put cameras on this interface */
+        .dev            = {
+                .dma_mask               = &pxa27x_dma_mask_camera,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_camera),
+        .resource       = pxa27x_resource_camera,
+};
+
+void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
+{
+        pxa_register_device(&pxa27x_device_camera, info);
+}
 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
 
 #ifdef CONFIG_PXA3xx
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 96c7c8909068..fcab017f27ee 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -14,6 +14,7 @@ extern struct platform_device pxa_device_rtc;
 
 extern struct platform_device pxa27x_device_i2c_power;
 extern struct platform_device pxa27x_device_ohci;
+extern struct platform_device pxa27x_device_keypad;
 
 extern struct platform_device pxa25x_device_ssp;
 extern struct platform_device pxa25x_device_nssp;
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 3bb31314429a..edc4f07a230d 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -23,6 +23,7 @@
 #include <asm/mach/arch.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/mmc.h>
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 80721c610d41..331f29b2d0cd 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -19,14 +19,8 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/ioport.h>
-#include <linux/pm.h>
-#include <linux/string.h>
-#include <linux/sysdev.h>
 
 #include <asm/hardware.h>
-#include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
@@ -134,59 +128,3 @@ void __init pxa_map_io(void)
         iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
         get_clk_frequency_khz(1);
 }
-
-#ifdef CONFIG_PM
-
-static unsigned long saved_gplr[4];
-static unsigned long saved_gpdr[4];
-static unsigned long saved_grer[4];
-static unsigned long saved_gfer[4];
-
-static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
-{
-        int i, gpio;
-
-        for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
-                saved_gplr[i] = GPLR(gpio);
-                saved_gpdr[i] = GPDR(gpio);
-                saved_grer[i] = GRER(gpio);
-                saved_gfer[i] = GFER(gpio);
-
-                /* Clear GPIO transition detect bits */
-                GEDR(gpio) = GEDR(gpio);
-        }
-        return 0;
-}
-
-static int pxa_gpio_resume(struct sys_device *dev)
-{
-        int i, gpio;
-
-        for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
-                /* restore level with set/clear */
-                GPSR(gpio) = saved_gplr[i];
-                GPCR(gpio) = ~saved_gplr[i];
-
-                GRER(gpio) = saved_grer[i];
-                GFER(gpio) = saved_gfer[i];
-                GPDR(gpio) = saved_gpdr[i];
-        }
-        return 0;
-}
-#else
-#define pxa_gpio_suspend        NULL
-#define pxa_gpio_resume         NULL
-#endif
-
-struct sysdev_class pxa_gpio_sysclass = {
-        .name           = "gpio",
-        .suspend        = pxa_gpio_suspend,
-        .resume         = pxa_gpio_resume,
-};
-
-static int __init pxa_gpio_init(void)
-{
-        return sysdev_class_register(&pxa_gpio_sysclass);
-}
-
-core_initcall(pxa_gpio_init);
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index b3d10b0e52a0..5bb7ae757831 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -9,14 +9,13 @@
  * published by the Free Software Foundation.
  */
 
+typedef int (*set_wake_t)(unsigned int, unsigned int);
+
 struct sys_timer;
 
 extern struct sys_timer pxa_timer;
-extern void __init pxa_init_irq_low(void);
-extern void __init pxa_init_irq_high(void);
-extern void __init pxa_init_irq_gpio(int gpio_nr);
-extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int));
-extern void __init pxa_init_gpio(int gpio_nr);
+extern void __init pxa_init_irq(int irq_nr, set_wake_t fn);
+extern void __init pxa_init_gpio(int gpio_nr, set_wake_t fn);
 extern void __init pxa25x_init_irq(void);
 extern void __init pxa27x_init_irq(void);
 extern void __init pxa3xx_init_irq(void);
@@ -30,6 +29,8 @@ extern int pxa_last_gpio;
         mi->bank[__nr].size = (__size), \
         mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
 
+#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+
 #ifdef CONFIG_PXA25x
 extern unsigned pxa25x_get_clk_frequency_khz(int);
 extern unsigned pxa25x_get_memclk_frequency_10khz(void);
@@ -56,3 +57,4 @@ extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
 
 extern struct sysdev_class pxa_irq_sysclass;
 extern struct sysdev_class pxa_gpio_sysclass;
+extern struct sysdev_class pxa3xx_mfp_sysclass;
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c
index 8638dd7dd076..7d3e16970be0 100644
--- a/arch/arm/mach-pxa/gpio.c
+++ b/arch/arm/mach-pxa/gpio.c
@@ -14,11 +14,14 @@
 
 #include <linux/init.h>
 #include <linux/module.h>
+#include <linux/irq.h>
+#include <linux/sysdev.h>
 
 #include <asm/gpio.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 
 #include "generic.h"
 
@@ -129,69 +132,283 @@ static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
                 __raw_writel(mask, pxa->regbase + GPCR_OFFSET);
 }
 
+#define GPIO_CHIP(_n)                                                   \
+        [_n] = {                                                        \
+                .regbase = GPIO##_n##_BASE,                             \
+                .chip = {                                               \
+                        .label            = "gpio-" #_n,                \
+                        .direction_input  = pxa_gpio_direction_input,   \
+                        .direction_output = pxa_gpio_direction_output,  \
+                        .get              = pxa_gpio_get,               \
+                        .set              = pxa_gpio_set,               \
+                        .base             = (_n) * 32,                  \
+                        .ngpio            = 32,                         \
+                },                                                      \
+        }
+
 static struct pxa_gpio_chip pxa_gpio_chip[] = {
-        [0] = {
-                .regbase = GPIO0_BASE,
-                .chip = {
-                        .label            = "gpio-0",
-                        .direction_input  = pxa_gpio_direction_input,
-                        .direction_output = pxa_gpio_direction_output,
-                        .get              = pxa_gpio_get,
-                        .set              = pxa_gpio_set,
-                        .base             = 0,
-                        .ngpio            = 32,
-                },
-        },
-        [1] = {
-                .regbase = GPIO1_BASE,
-                .chip = {
-                        .label            = "gpio-1",
-                        .direction_input  = pxa_gpio_direction_input,
-                        .direction_output = pxa_gpio_direction_output,
-                        .get              = pxa_gpio_get,
-                        .set              = pxa_gpio_set,
-                        .base             = 32,
-                        .ngpio            = 32,
-                },
-        },
-        [2] = {
-                .regbase = GPIO2_BASE,
-                .chip = {
-                        .label            = "gpio-2",
-                        .direction_input  = pxa_gpio_direction_input,
-                        .direction_output = pxa_gpio_direction_output,
-                        .get              = pxa_gpio_get,
-                        .set              = pxa_gpio_set,
-                        .base             = 64,
-                        .ngpio            = 32, /* 21 for PXA25x */
-                },
-        },
+        GPIO_CHIP(0),
+        GPIO_CHIP(1),
+        GPIO_CHIP(2),
 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-        [3] = {
-                .regbase = GPIO3_BASE,
-                .chip = {
-                        .label            = "gpio-3",
-                        .direction_input  = pxa_gpio_direction_input,
-                        .direction_output = pxa_gpio_direction_output,
-                        .get              = pxa_gpio_get,
-                        .set              = pxa_gpio_set,
-                        .base             = 96,
-                        .ngpio            = 32,
-                },
-        },
+        GPIO_CHIP(3),
 #endif
 };
 
-void __init pxa_init_gpio(int gpio_nr)
+/*
+ * PXA GPIO edge detection for IRQs:
+ * IRQs are generated on Falling-Edge, Rising-Edge, or both.
+ * Use this instead of directly setting GRER/GFER.
+ */
+
+static unsigned long GPIO_IRQ_rising_edge[4];
+static unsigned long GPIO_IRQ_falling_edge[4];
+static unsigned long GPIO_IRQ_mask[4];
+
+/*
+ * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
+ * function of a GPIO, and GPDRx cannot be altered once configured. It
+ * is attributed as "occupied" here (I know this terminology isn't
+ * accurate, you are welcome to propose a better one :-)
+ */
+static int __gpio_is_occupied(unsigned gpio)
+{
+        if (cpu_is_pxa25x() || cpu_is_pxa27x())
+                return GAFR(gpio) & (0x3 << (((gpio) & 0xf) * 2));
+        else
+                return 0;
+}
+
+static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
+{
+        int gpio, idx;
+
+        gpio = IRQ_TO_GPIO(irq);
+        idx = gpio >> 5;
+
+        if (type == IRQ_TYPE_PROBE) {
+                /* Don't mess with enabled GPIOs using preconfigured edges or
+                 * GPIOs set to alternate function or to output during probe
+                 */
+                if ((GPIO_IRQ_rising_edge[idx] |
+                     GPIO_IRQ_falling_edge[idx] |
+                     GPDR(gpio)) & GPIO_bit(gpio))
+                        return 0;
+
+                if (__gpio_is_occupied(gpio))
+                        return 0;
+
+                type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+        }
+
+        GPDR(gpio) &= ~GPIO_bit(gpio);
+
+        if (type & IRQ_TYPE_EDGE_RISING)
+                __set_bit(gpio, GPIO_IRQ_rising_edge);
+        else
+                __clear_bit(gpio, GPIO_IRQ_rising_edge);
+
+        if (type & IRQ_TYPE_EDGE_FALLING)
+                __set_bit(gpio, GPIO_IRQ_falling_edge);
+        else
+                __clear_bit(gpio, GPIO_IRQ_falling_edge);
+
+        GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
+        GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
+
+        pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio,
+                ((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
+                ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
+        return 0;
+}
+
+/*
+ * GPIO IRQs must be acknowledged.  This is for GPIO 0 and 1.
+ */
+
+static void pxa_ack_low_gpio(unsigned int irq)
+{
+        GEDR0 = (1 << (irq - IRQ_GPIO0));
+}
+
+static void pxa_mask_low_gpio(unsigned int irq)
+{
+        ICMR &= ~(1 << (irq - PXA_IRQ(0)));
+}
+
+static void pxa_unmask_low_gpio(unsigned int irq)
+{
+        ICMR |= 1 << (irq - PXA_IRQ(0));
+}
+
+static struct irq_chip pxa_low_gpio_chip = {
+        .name           = "GPIO-l",
+        .ack            = pxa_ack_low_gpio,
+        .mask           = pxa_mask_low_gpio,
+        .unmask         = pxa_unmask_low_gpio,
+        .set_type       = pxa_gpio_irq_type,
+};
+
+/*
+ * Demux handler for GPIO>=2 edge detect interrupts
+ */
+
+#define GEDR_BITS       (sizeof(gedr) * BITS_PER_BYTE)
+
+static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
+{
+        int loop, bit, n;
+        unsigned long gedr[4];
+
+        do {
+                gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3;
+                gedr[1] = GEDR1 & GPIO_IRQ_mask[1];
+                gedr[2] = GEDR2 & GPIO_IRQ_mask[2];
+                gedr[3] = GEDR3 & GPIO_IRQ_mask[3];
+
+                GEDR0 = gedr[0]; GEDR1 = gedr[1];
+                GEDR2 = gedr[2]; GEDR3 = gedr[3];
+
+                loop = 0;
+                bit = find_first_bit(gedr, GEDR_BITS);
+                while (bit < GEDR_BITS) {
+                        loop = 1;
+
+                        n = PXA_GPIO_IRQ_BASE + bit;
+                        desc_handle_irq(n, irq_desc + n);
+
+                        bit = find_next_bit(gedr, GEDR_BITS, bit + 1);
+                }
+        } while (loop);
+}
+
+static void pxa_ack_muxed_gpio(unsigned int irq)
+{
+        int gpio = irq - IRQ_GPIO(2) + 2;
+        GEDR(gpio) = GPIO_bit(gpio);
+}
+
+static void pxa_mask_muxed_gpio(unsigned int irq)
+{
+        int gpio = irq - IRQ_GPIO(2) + 2;
+        __clear_bit(gpio, GPIO_IRQ_mask);
+        GRER(gpio) &= ~GPIO_bit(gpio);
+        GFER(gpio) &= ~GPIO_bit(gpio);
+}
+
+static void pxa_unmask_muxed_gpio(unsigned int irq)
+{
+        int gpio = irq - IRQ_GPIO(2) + 2;
+        int idx = gpio >> 5;
+        __set_bit(gpio, GPIO_IRQ_mask);
+        GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
+        GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
+}
+
+static struct irq_chip pxa_muxed_gpio_chip = {
+        .name           = "GPIO",
+        .ack            = pxa_ack_muxed_gpio,
+        .mask           = pxa_mask_muxed_gpio,
+        .unmask         = pxa_unmask_muxed_gpio,
+        .set_type       = pxa_gpio_irq_type,
+};
+
+void __init pxa_init_gpio(int gpio_nr, set_wake_t fn)
 {
-        int i;
+        int irq, i, gpio;
+
+        pxa_last_gpio = gpio_nr - 1;
+
+        /* clear all GPIO edge detects */
+        for (i = 0; i < gpio_nr; i += 32) {
+                GFER(i) = 0;
+                GRER(i) = 0;
+                GEDR(i) = GEDR(i);
+        }
+
+        /* GPIO 0 and 1 must have their mask bit always set */
+        GPIO_IRQ_mask[0] = 3;
+
+        for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
+                set_irq_chip(irq, &pxa_low_gpio_chip);
+                set_irq_handler(irq, handle_edge_irq);
+                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        }
+
+        for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
+                set_irq_chip(irq, &pxa_muxed_gpio_chip);
+                set_irq_handler(irq, handle_edge_irq);
+                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        }
+
+        /* Install handler for GPIO>=2 edge detect interrupts */
+        set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
+
+        pxa_low_gpio_chip.set_wake = fn;
+        pxa_muxed_gpio_chip.set_wake = fn;
 
         /* add a GPIO chip for each register bank.
          * the last PXA25x register only contains 21 GPIOs
          */
-        for (i = 0; i < gpio_nr; i += 32) {
-                if (i+32 > gpio_nr)
-                        pxa_gpio_chip[i/32].chip.ngpio = gpio_nr - i;
-                gpiochip_add(&pxa_gpio_chip[i/32].chip);
+        for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) {
+                if (gpio + 32 > gpio_nr)
+                        pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio;
+                gpiochip_add(&pxa_gpio_chip[i].chip);
         }
 }
+
+#ifdef CONFIG_PM
+
+static unsigned long saved_gplr[4];
+static unsigned long saved_gpdr[4];
+static unsigned long saved_grer[4];
+static unsigned long saved_gfer[4];
+
+static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
+{
+        int i, gpio;
+
+        for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
+                saved_gplr[i] = GPLR(gpio);
+                saved_gpdr[i] = GPDR(gpio);
+                saved_grer[i] = GRER(gpio);
+                saved_gfer[i] = GFER(gpio);
+
+                /* Clear GPIO transition detect bits */
+                GEDR(gpio) = GEDR(gpio);
+        }
+        return 0;
+}
+
+static int pxa_gpio_resume(struct sys_device *dev)
+{
+        int i, gpio;
+
+        for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
+                /* restore level with set/clear */
+                GPSR(gpio) = saved_gplr[i];
+                GPCR(gpio) = ~saved_gplr[i];
+
+                GRER(gpio) = saved_grer[i];
+                GFER(gpio) = saved_gfer[i];
+                GPDR(gpio) = saved_gpdr[i];
+        }
+        return 0;
+}
+#else
+#define pxa_gpio_suspend        NULL
+#define pxa_gpio_resume         NULL
+#endif
+
+struct sysdev_class pxa_gpio_sysclass = {
+        .name           = "gpio",
+        .suspend        = pxa_gpio_suspend,
+        .resume         = pxa_gpio_resume,
+};
+
+static int __init pxa_gpio_init(void)
+{
+        return sysdev_class_register(&pxa_gpio_sysclass);
+}
+
+core_initcall(pxa_gpio_init);
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
new file mode 100644
index 000000000000..f01d18544133
--- /dev/null
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -0,0 +1,147 @@
+/*
+ *  linux/arch/arm/mach-pxa/gumstix.c
+ *
+ *  Support for the Gumstix motherboards.
+ *
+ *  Original Author:    Craig Hughes
+ *  Created:    Feb 14, 2008
+ *  Copyright:  Craig Hughes
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *  Implemented based on lubbock.c by Nicolas Pitre and code from Craig
+ *  Hughes
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/sizes.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/flash.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/udc.h>
+#include <asm/arch/gumstix.h>
+
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-regs.h>
+
+#include "generic.h"
+
+static struct resource flash_resource = {
+        .start  = 0x00000000,
+        .end    = SZ_64M - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct mtd_partition gumstix_partitions[] = {
+        {
+                .name =         "Bootloader",
+                .size =         0x00040000,
+                .offset =       0,
+                .mask_flags =   MTD_WRITEABLE  /* force read-only */
+        } , {
+                .name =         "rootfs",
+                .size =         MTDPART_SIZ_FULL,
+                .offset =       MTDPART_OFS_APPEND
+        }
+};
+
+static struct flash_platform_data gumstix_flash_data = {
+        .map_name       = "cfi_probe",
+        .parts          = gumstix_partitions,
+        .nr_parts       = ARRAY_SIZE(gumstix_partitions),
+        .width          = 2,
+};
+
+static struct platform_device gumstix_flash_device = {
+        .name           = "pxa2xx-flash",
+        .id             = 0,
+        .dev = {
+                .platform_data = &gumstix_flash_data,
+        },
+        .resource = &flash_resource,
+        .num_resources = 1,
+};
+
+static struct platform_device *devices[] __initdata = {
+        &gumstix_flash_device,
+};
+
+#ifdef CONFIG_MMC_PXA
+static struct pxamci_platform_data gumstix_mci_platform_data;
+
+static int gumstix_mci_init(struct device *dev, irq_handler_t detect_int,
+                                void *data)
+{
+        pxa_gpio_mode(GPIO6_MMCCLK_MD);
+        pxa_gpio_mode(GPIO53_MMCCLK_MD);
+        pxa_gpio_mode(GPIO8_MMCCS0_MD);
+
+        return 0;
+}
+
+static struct pxamci_platform_data gumstix_mci_platform_data = {
+        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
+        .init           = gumstix_mci_init,
+};
+
+static void __init gumstix_mmc_init(void)
+{
+        pxa_set_mci_info(&gumstix_mci_platform_data);
+}
+#else
+static void __init gumstix_mmc_init(void)
+{
+        printk(KERN_INFO "Gumstix mmc disabled\n");
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET_PXA2XX
+static struct pxa2xx_udc_mach_info gumstix_udc_info __initdata = {
+        .gpio_vbus              = GPIO_GUMSTIX_USB_GPIOn,
+        .gpio_pullup            = GPIO_GUMSTIX_USB_GPIOx,
+};
+
+static void __init gumstix_udc_init(void)
+{
+        pxa_set_udc_info(&gumstix_udc_info);
+}
+#else
+static void gumstix_udc_init(void)
+{
+        printk(KERN_INFO "Gumstix udc is disabled\n");
+}
+#endif
+
+static void __init gumstix_init(void)
+{
+        gumstix_udc_init();
+        gumstix_mmc_init();
+        (void) platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+MACHINE_START(GUMSTIX, "Gumstix")
+        .phys_io        = 0x40000000,
+        .boot_params    = 0xa0000100, /* match u-boot bi_boot_params */
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+        .map_io         = pxa_map_io,
+        .init_irq       = pxa25x_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = gumstix_init,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index 0a9434432c55..2637633f9166 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -32,6 +32,7 @@
 #include <asm/mach/map.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/idp.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/bitfield.h>
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 36c6a68beca2..a9a0c3fab159 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/mach-pxa/irq.c
  *
- *  Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
+ *  Generic PXA IRQ handling
  *
  *  Author:     Nicolas Pitre
  *  Created:    Jun 15, 2001
@@ -21,308 +21,58 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 
 #include "generic.h"
 
+#define IRQ_BIT(n)      (((n) - PXA_IRQ(0)) & 0x1f)
+#define _ICMR(n)        (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
+#define _ICLR(n)        (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
 
 /*
  * This is for peripheral IRQs internal to the PXA chip.
  */
 
-static void pxa_mask_low_irq(unsigned int irq)
+static int pxa_internal_irq_nr;
+
+static void pxa_mask_irq(unsigned int irq)
 {
-        ICMR &= ~(1 << irq);
+        _ICMR(irq) &= ~(1 << IRQ_BIT(irq));
 }
 
-static void pxa_unmask_low_irq(unsigned int irq)
+static void pxa_unmask_irq(unsigned int irq)
 {
-        ICMR |= (1 << irq);
+        _ICMR(irq) |= 1 << IRQ_BIT(irq);
 }
 
-static struct irq_chip pxa_internal_chip_low = {
+static struct irq_chip pxa_internal_irq_chip = {
         .name           = "SC",
-        .ack            = pxa_mask_low_irq,
-        .mask           = pxa_mask_low_irq,
-        .unmask         = pxa_unmask_low_irq,
+        .ack            = pxa_mask_irq,
+        .mask           = pxa_mask_irq,
+        .unmask         = pxa_unmask_irq,
 };
 
-void __init pxa_init_irq_low(void)
+void __init pxa_init_irq(int irq_nr, set_wake_t fn)
 {
         int irq;
 
-        /* disable all IRQs */
-        ICMR = 0;
+        pxa_internal_irq_nr = irq_nr;
 
-        /* all IRQs are IRQ, not FIQ */
-        ICLR = 0;
+        for (irq = 0; irq < irq_nr; irq += 32) {
+                _ICMR(irq) = 0; /* disable all IRQs */
+                _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
+        }
 
         /* only unmasked interrupts kick us out of idle */
         ICCR = 1;
 
-        for (irq = PXA_IRQ(0); irq <= PXA_IRQ(31); irq++) {
-                set_irq_chip(irq, &pxa_internal_chip_low);
-                set_irq_handler(irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-}
-
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-
-/*
- * This is for the second set of internal IRQs as found on the PXA27x.
- */
-
-static void pxa_mask_high_irq(unsigned int irq)
-{
-        ICMR2 &= ~(1 << (irq - 32));
-}
-
-static void pxa_unmask_high_irq(unsigned int irq)
-{
-        ICMR2 |= (1 << (irq - 32));
-}
-
-static struct irq_chip pxa_internal_chip_high = {
-        .name           = "SC-hi",
-        .ack            = pxa_mask_high_irq,
-        .mask           = pxa_mask_high_irq,
-        .unmask         = pxa_unmask_high_irq,
-};
-
-void __init pxa_init_irq_high(void)
-{
-        int irq;
-
-        ICMR2 = 0;
-        ICLR2 = 0;
-
-        for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) {
-                set_irq_chip(irq, &pxa_internal_chip_high);
+        for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
+                set_irq_chip(irq, &pxa_internal_irq_chip);
                 set_irq_handler(irq, handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
-}
-#endif
-
-/*
- * PXA GPIO edge detection for IRQs:
- * IRQs are generated on Falling-Edge, Rising-Edge, or both.
- * Use this instead of directly setting GRER/GFER.
- */
-
-static long GPIO_IRQ_rising_edge[4];
-static long GPIO_IRQ_falling_edge[4];
-static long GPIO_IRQ_mask[4];
-
-static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
-{
-        int gpio, idx;
-
-        gpio = IRQ_TO_GPIO(irq);
-        idx = gpio >> 5;
-
-        if (type == IRQT_PROBE) {
-            /* Don't mess with enabled GPIOs using preconfigured edges or
-               GPIOs set to alternate function or to output during probe */
-                if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) &
-                    GPIO_bit(gpio))
-                        return 0;
-                if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
-                        return 0;
-                type = __IRQT_RISEDGE | __IRQT_FALEDGE;
-        }
-
-        /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
-
-        pxa_gpio_mode(gpio | GPIO_IN);
-
-        if (type & __IRQT_RISEDGE) {
-                /* printk("rising "); */
-                __set_bit (gpio, GPIO_IRQ_rising_edge);
-        } else {
-                __clear_bit (gpio, GPIO_IRQ_rising_edge);
-        }
-
-        if (type & __IRQT_FALEDGE) {
-                /* printk("falling "); */
-                __set_bit (gpio, GPIO_IRQ_falling_edge);
-        } else {
-                __clear_bit (gpio, GPIO_IRQ_falling_edge);
-        }
-
-        /* printk("edges\n"); */
-
-        GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
-        GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
-        return 0;
-}
-
-/*
- * GPIO IRQs must be acknowledged.  This is for GPIO 0 and 1.
- */
-
-static void pxa_ack_low_gpio(unsigned int irq)
-{
-        GEDR0 = (1 << (irq - IRQ_GPIO0));
-}
-
-static struct irq_chip pxa_low_gpio_chip = {
-        .name           = "GPIO-l",
-        .ack            = pxa_ack_low_gpio,
-        .mask           = pxa_mask_low_irq,
-        .unmask         = pxa_unmask_low_irq,
-        .set_type       = pxa_gpio_irq_type,
-};
-
-/*
- * Demux handler for GPIO>=2 edge detect interrupts
- */
-
-static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
-{
-        unsigned int mask;
-        int loop;
-
-        do {
-                loop = 0;
-
-                mask = GEDR0 & GPIO_IRQ_mask[0] & ~3;
-                if (mask) {
-                        GEDR0 = mask;
-                        irq = IRQ_GPIO(2);
-                        desc = irq_desc + irq;
-                        mask >>= 2;
-                        do {
-                                if (mask & 1)
-                                        desc_handle_irq(irq, desc);
-                                irq++;
-                                desc++;
-                                mask >>= 1;
-                        } while (mask);
-                        loop = 1;
-                }
-
-                mask = GEDR1 & GPIO_IRQ_mask[1];
-                if (mask) {
-                        GEDR1 = mask;
-                        irq = IRQ_GPIO(32);
-                        desc = irq_desc + irq;
-                        do {
-                                if (mask & 1)
-                                        desc_handle_irq(irq, desc);
-                                irq++;
-                                desc++;
-                                mask >>= 1;
-                        } while (mask);
-                        loop = 1;
-                }
-
-                mask = GEDR2 & GPIO_IRQ_mask[2];
-                if (mask) {
-                        GEDR2 = mask;
-                        irq = IRQ_GPIO(64);
-                        desc = irq_desc + irq;
-                        do {
-                                if (mask & 1)
-                                        desc_handle_irq(irq, desc);
-                                irq++;
-                                desc++;
-                                mask >>= 1;
-                        } while (mask);
-                        loop = 1;
-                }
-
-                mask = GEDR3 & GPIO_IRQ_mask[3];
-                if (mask) {
-                        GEDR3 = mask;
-                        irq = IRQ_GPIO(96);
-                        desc = irq_desc + irq;
-                        do {
-                                if (mask & 1)
-                                        desc_handle_irq(irq, desc);
-                                irq++;
-                                desc++;
-                                mask >>= 1;
-                        } while (mask);
-                        loop = 1;
-                }
-        } while (loop);
-}
-
-static void pxa_ack_muxed_gpio(unsigned int irq)
-{
-        int gpio = irq - IRQ_GPIO(2) + 2;
-        GEDR(gpio) = GPIO_bit(gpio);
-}
-
-static void pxa_mask_muxed_gpio(unsigned int irq)
-{
-        int gpio = irq - IRQ_GPIO(2) + 2;
-        __clear_bit(gpio, GPIO_IRQ_mask);
-        GRER(gpio) &= ~GPIO_bit(gpio);
-        GFER(gpio) &= ~GPIO_bit(gpio);
-}
-
-static void pxa_unmask_muxed_gpio(unsigned int irq)
-{
-        int gpio = irq - IRQ_GPIO(2) + 2;
-        int idx = gpio >> 5;
-        __set_bit(gpio, GPIO_IRQ_mask);
-        GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
-        GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
-}
-
-static struct irq_chip pxa_muxed_gpio_chip = {
-        .name           = "GPIO",
-        .ack            = pxa_ack_muxed_gpio,
-        .mask           = pxa_mask_muxed_gpio,
-        .unmask         = pxa_unmask_muxed_gpio,
-        .set_type       = pxa_gpio_irq_type,
-};
-
-void __init pxa_init_irq_gpio(int gpio_nr)
-{
-        int irq, i;
-
-        pxa_last_gpio = gpio_nr - 1;
-
-        /* clear all GPIO edge detects */
-        for (i = 0; i < gpio_nr; i += 32) {
-                GFER(i) = 0;
-                GRER(i) = 0;
-                GEDR(i) = GEDR(i);
-        }
-
-        /* GPIO 0 and 1 must have their mask bit always set */
-        GPIO_IRQ_mask[0] = 3;
-
-        for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
-                set_irq_chip(irq, &pxa_low_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        }
 
-        for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) {
-                set_irq_chip(irq, &pxa_muxed_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        }
-
-        /* Install handler for GPIO>=2 edge detect interrupts */
-        set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
-        set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
-
-        pxa_init_gpio(gpio_nr);
-}
-
-void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
-{
-        pxa_internal_chip_low.set_wake = set_wake;
-#ifdef CONFIG_PXA27x
-        pxa_internal_chip_high.set_wake = set_wake;
-#endif
-        pxa_low_gpio_chip.set_wake = set_wake;
-        pxa_muxed_gpio_chip.set_wake = set_wake;
+        pxa_internal_irq_chip.set_wake = fn;
 }
 
 #ifdef CONFIG_PM
@@ -330,19 +80,11 @@ static unsigned long saved_icmr[2];
 
 static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
 {
-        switch (dev->id) {
-        case 0:
-                saved_icmr[0] = ICMR;
-                ICMR = 0;
-                break;
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-        case 1:
-                saved_icmr[1] = ICMR2;
-                ICMR2 = 0;
-                break;
-#endif
-        default:
-                return -EINVAL;
+        int i, irq = PXA_IRQ(0);
+
+        for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
+                saved_icmr[i] = _ICMR(irq);
+                _ICMR(irq) = 0;
         }
 
         return 0;
@@ -350,22 +92,14 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
 
 static int pxa_irq_resume(struct sys_device *dev)
 {
-        switch (dev->id) {
-        case 0:
-                ICMR = saved_icmr[0];
-                ICLR = 0;
-                ICCR = 1;
-                break;
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-        case 1:
-                ICMR2 = saved_icmr[1];
-                ICLR2 = 0;
-                break;
-#endif
-        default:
-                return -EINVAL;
+        int i, irq = PXA_IRQ(0);
+
+        for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
+                _ICMR(irq) = saved_icmr[i];
+                _ICLR(irq) = 0;
         }
 
+        ICCR = 1;
         return 0;
 }
 #else
diff --git a/arch/arm/mach-pxa/leds-trizeps4.c b/arch/arm/mach-pxa/leds-trizeps4.c
index 2271d20ffeda..21880daabafe 100644
--- a/arch/arm/mach-pxa/leds-trizeps4.c
+++ b/arch/arm/mach-pxa/leds-trizeps4.c
@@ -18,6 +18,7 @@
 #include <asm/leds.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/trizeps4.h>
 
 #include "leds.h"
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 0a4b54c21314..03396063b561 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -37,12 +37,11 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/pxafb.h>
 #include <asm/arch/ssp.h>
+#include <asm/arch/pxa27x_keypad.h>
 #include <asm/arch/littleton.h>
 
 #include "generic.h"
 
-#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
-
 /* Littleton MFP configurations */
 static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
         /* LCD */
@@ -76,6 +75,21 @@ static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
 
         /* Debug Ethernet */
         GPIO90_GPIO,
+
+        /* Keypad */
+        GPIO107_KP_DKIN_0,
+        GPIO108_KP_DKIN_1,
+        GPIO115_KP_MKIN_0,
+        GPIO116_KP_MKIN_1,
+        GPIO117_KP_MKIN_2,
+        GPIO118_KP_MKIN_3,
+        GPIO119_KP_MKIN_4,
+        GPIO120_KP_MKIN_5,
+        GPIO121_KP_MKOUT_0,
+        GPIO122_KP_MKOUT_1,
+        GPIO123_KP_MKOUT_2,
+        GPIO124_KP_MKOUT_3,
+        GPIO125_KP_MKOUT_4,
 };
 
 static struct resource smc91x_resources[] = {
@@ -300,6 +314,54 @@ static void littleton_init_lcd(void)
 static inline void littleton_init_lcd(void) {};
 #endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULES */
 
+#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
+static unsigned int littleton_matrix_key_map[] = {
+        /* KEY(row, col, key_code) */
+        KEY(1, 3, KEY_0), KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3),
+        KEY(0, 1, KEY_4), KEY(1, 1, KEY_5), KEY(2, 1, KEY_6), KEY(0, 2, KEY_7),
+        KEY(1, 2, KEY_8), KEY(2, 2, KEY_9),
+
+        KEY(0, 3, KEY_KPASTERISK),      /* * */
+        KEY(2, 3, KEY_KPDOT),           /* # */
+
+        KEY(5, 4, KEY_ENTER),
+
+        KEY(5, 0, KEY_UP),
+        KEY(5, 1, KEY_DOWN),
+        KEY(5, 2, KEY_LEFT),
+        KEY(5, 3, KEY_RIGHT),
+        KEY(3, 2, KEY_HOME),
+        KEY(4, 1, KEY_END),
+        KEY(3, 3, KEY_BACK),
+
+        KEY(4, 0, KEY_SEND),
+        KEY(4, 2, KEY_VOLUMEUP),
+        KEY(4, 3, KEY_VOLUMEDOWN),
+
+        KEY(3, 0, KEY_F22),     /* soft1 */
+        KEY(3, 1, KEY_F23),     /* soft2 */
+};
+
+static struct pxa27x_keypad_platform_data littleton_keypad_info = {
+        .matrix_key_rows        = 6,
+        .matrix_key_cols        = 5,
+        .matrix_key_map         = littleton_matrix_key_map,
+        .matrix_key_map_size    = ARRAY_SIZE(littleton_matrix_key_map),
+
+        .enable_rotary0         = 1,
+        .rotary0_up_key         = KEY_UP,
+        .rotary0_down_key       = KEY_DOWN,
+
+        .debounce_interval      = 30,
+};
+static void __init littleton_init_keypad(void)
+{
+        pxa_set_keypad_info(&littleton_keypad_info);
+}
+#else
+static inline void littleton_init_keypad(void) {}
+#endif
+
 static void __init littleton_init(void)
 {
         /* initialize MFP configurations */
@@ -312,6 +374,7 @@ static void __init littleton_init(void)
         platform_device_register(&smc91x_device);
 
         littleton_init_lcd();
+        littleton_init_keypad();
 }
 
 MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index afa62ffe3ad5..a20e4b1649d6 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -39,6 +39,7 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/lpd270.h>
 #include <asm/arch/audio.h>
 #include <asm/arch/pxafb.h>
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index e7ae4bb3e361..ca209c443f34 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -42,6 +42,7 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/mfp-pxa25x.h>
 #include <asm/arch/lubbock.h>
 #include <asm/arch/udc.h>
 #include <asm/arch/irda.h>
@@ -51,6 +52,40 @@
 #include "generic.h"
 #include "devices.h"
 
+static unsigned long lubbock_pin_config[] __initdata = {
+        GPIO15_nCS_1,   /* CS1 - Flash */
+        GPIO79_nCS_3,   /* CS3 - SMC ethernet */
+
+        /* SSP data pins */
+        GPIO23_SSP1_SCLK,
+        GPIO25_SSP1_TXD,
+        GPIO26_SSP1_RXD,
+
+        /* BTUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+
+        /* PC Card */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO52_nPCE_1,
+        GPIO53_nPCE_2,
+        GPIO54_nPSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+
+        /* MMC */
+        GPIO6_MMC_CLK,
+        GPIO8_MMC_CS0,
+
+        /* wakeup */
+        GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
+};
 
 #define LUB_MISC_WR             __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
 
@@ -186,26 +221,6 @@ static struct platform_device sa1111_device = {
         .resource       = sa1111_resources,
 };
 
-static struct resource smc91x_resources[] = {
-        [0] = {
-                .name   = "smc91x-regs",
-                .start  = 0x0c000c00,
-                .end    = 0x0c0fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = LUBBOCK_ETH_IRQ,
-                .end    = LUBBOCK_ETH_IRQ,
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
-        },
-        [2] = {
-                .name   = "smc91x-attrib",
-                .start  = 0x0e000000,
-                .end    = 0x0e0fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
 /* ADS7846 is connected through SSP ... and if your board has J5 populated,
  * you can select it to replace the ucb1400 by switching the touchscreen cable
  * (to J5) and poking board registers (as done below).  Else it's only useful
@@ -261,6 +276,26 @@ static struct spi_board_info spi_board_info[] __initdata = { {
 },
 };
 
+static struct resource smc91x_resources[] = {
+        [0] = {
+                .name   = "smc91x-regs",
+                .start  = 0x0c000c00,
+                .end    = 0x0c0fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = LUBBOCK_ETH_IRQ,
+                .end    = LUBBOCK_ETH_IRQ,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        },
+        [2] = {
+                .name   = "smc91x-attrib",
+                .start  = 0x0e000000,
+                .end    = 0x0e0fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
 static struct platform_device smc91x_device = {
         .name           = "smc91x",
         .id             = -1,
@@ -404,10 +439,6 @@ static int lubbock_mci_init(struct device *dev,
                 irq_handler_t detect_int,
                 void *data)
 {
-        /* setup GPIO for PXA25x MMC controller */
-        pxa_gpio_mode(GPIO6_MMCCLK_MD);
-        pxa_gpio_mode(GPIO8_MMCCS0_MD);
-
         /* detect card insert/eject */
         mmc_detect_int = detect_int;
         init_timer(&mmc_timer);
@@ -457,6 +488,8 @@ static void __init lubbock_init(void)
 {
         int flashboot = (LUB_CONF_SWITCHES & 1);
 
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config));
+
         pxa_set_udc_info(&udc_info);
         set_pxa_fb_info(&sharp_lm8v31);
         pxa_set_mci_info(&lubbock_mci_platform_data);
@@ -489,46 +522,6 @@ static void __init lubbock_map_io(void)
         pxa_map_io();
         iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc));
 
-        /* SSP data pins */
-        pxa_gpio_mode(GPIO23_SCLK_MD);
-        pxa_gpio_mode(GPIO25_STXD_MD);
-        pxa_gpio_mode(GPIO26_SRXD_MD);
-
-        /* This enables the BTUART */
-        pxa_gpio_mode(GPIO42_BTRXD_MD);
-        pxa_gpio_mode(GPIO43_BTTXD_MD);
-        pxa_gpio_mode(GPIO44_BTCTS_MD);
-        pxa_gpio_mode(GPIO45_BTRTS_MD);
-
-        GPSR(GPIO48_nPOE) =
-                GPIO_bit(GPIO48_nPOE) |
-                GPIO_bit(GPIO49_nPWE) |
-                GPIO_bit(GPIO50_nPIOR) |
-                GPIO_bit(GPIO51_nPIOW) |
-                GPIO_bit(GPIO52_nPCE_1) |
-                GPIO_bit(GPIO53_nPCE_2);
-
-        pxa_gpio_mode(GPIO48_nPOE_MD);
-        pxa_gpio_mode(GPIO49_nPWE_MD);
-        pxa_gpio_mode(GPIO50_nPIOR_MD);
-        pxa_gpio_mode(GPIO51_nPIOW_MD);
-        pxa_gpio_mode(GPIO52_nPCE_1_MD);
-        pxa_gpio_mode(GPIO53_nPCE_2_MD);
-        pxa_gpio_mode(GPIO54_pSKTSEL_MD);
-        pxa_gpio_mode(GPIO55_nPREG_MD);
-        pxa_gpio_mode(GPIO56_nPWAIT_MD);
-        pxa_gpio_mode(GPIO57_nIOIS16_MD);
-
-        /* This is for the SMC chip select */
-        pxa_gpio_mode(GPIO79_nCS_3_MD);
-
-        /* setup sleep mode values */
-        PWER  = 0x00000002;
-        PFER  = 0x00000000;
-        PRER  = 0x00000002;
-        PGSR0 = 0x00008000;
-        PGSR1 = 0x003F0202;
-        PGSR2 = 0x0001C000;
         PCFR |= PCFR_OPDE;
 }
 
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index d98ef7ada2f8..d70be75bd199 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -16,24 +16,106 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/delay.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/mfd/htc-egpio.h>
+#include <linux/mfd/htc-pasic3.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
+#include <linux/pda_power.h>
 
 #include <asm/gpio.h>
 #include <asm/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/arch/magician.h>
+#include <asm/arch/mfp-pxa27x.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxafb.h>
+#include <asm/arch/i2c.h>
+#include <asm/arch/mmc.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/ohci.h>
 
 #include "generic.h"
 
+static unsigned long magician_pin_config[] = {
+
+        /* SDRAM and Static Memory I/O Signals */
+        GPIO20_nSDCS_2,
+        GPIO21_nSDCS_3,
+        GPIO15_nCS_1,
+        GPIO78_nCS_2,   /* PASIC3 */
+        GPIO79_nCS_3,   /* EGPIO CPLD */
+        GPIO80_nCS_4,
+        GPIO33_nCS_5,
+
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+
+        /* PWM 0 */
+        GPIO16_PWM0_OUT,
+
+        /* I2S */
+        GPIO28_I2S_BITCLK_OUT,
+        GPIO29_I2S_SDATA_IN,
+        GPIO31_I2S_SYNC,
+        GPIO113_I2S_SYSCLK,
+
+        /* SSP 2 */
+        GPIO19_SSP2_SCLK,
+        GPIO14_SSP2_SFRM,
+        GPIO89_SSP2_TXD,
+        GPIO88_SSP2_RXD,
+
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+
+        /* LCD */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+
+        /* QCI */
+        GPIO12_CIF_DD_7,
+        GPIO17_CIF_DD_6,
+        GPIO50_CIF_DD_3,
+        GPIO51_CIF_DD_2,
+        GPIO52_CIF_DD_4,
+        GPIO53_CIF_MCLK,
+        GPIO54_CIF_PCLK,
+        GPIO55_CIF_DD_1,
+        GPIO81_CIF_DD_0,
+        GPIO82_CIF_DD_5,
+        GPIO84_CIF_FV,
+        GPIO85_CIF_LV,
+};
+
 /*
  * IRDA
  */
@@ -83,8 +165,64 @@ static struct platform_device gpio_keys = {
         .id   = -1,
 };
 
+
+/*
+ * EGPIO (Xilinx CPLD)
+ *
+ * 7 32-bit aligned 8-bit registers: 3x output, 1x irq, 3x input
+ */
+
+static struct resource egpio_resources[] = {
+        [0] = {
+                .start = PXA_CS3_PHYS,
+                .end   = PXA_CS3_PHYS + 0x20,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ),
+                .end   = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ),
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct htc_egpio_chip egpio_chips[] = {
+        [0] = {
+                .reg_start = 0,
+                .gpio_base = MAGICIAN_EGPIO(0, 0),
+                .num_gpios = 24,
+                .direction = HTC_EGPIO_OUTPUT,
+                .initial_values = 0x40, /* EGPIO_MAGICIAN_GSM_RESET */
+        },
+        [1] = {
+                .reg_start = 4,
+                .gpio_base = MAGICIAN_EGPIO(4, 0),
+                .num_gpios = 24,
+                .direction = HTC_EGPIO_INPUT,
+        },
+};
+
+static struct htc_egpio_platform_data egpio_info = {
+        .reg_width    = 8,
+        .bus_width    = 32,
+        .irq_base     = IRQ_BOARD_START,
+        .num_irqs     = 4,
+        .ack_register = 3,
+        .chip         = egpio_chips,
+        .num_chips    = ARRAY_SIZE(egpio_chips),
+};
+
+static struct platform_device egpio = {
+        .name          = "htc-egpio",
+        .id            = -1,
+        .resource      = egpio_resources,
+        .num_resources = ARRAY_SIZE(egpio_resources),
+        .dev = {
+                .platform_data = &egpio_info,
+        },
+};
+
 /*
- * LCD - Toppoly TD028STEB1
+ * LCD - Toppoly TD028STEB1 or Samsung LTP280QV
  */
 
 static struct pxafb_mode_info toppoly_modes[] = {
@@ -103,12 +241,99 @@ static struct pxafb_mode_info toppoly_modes[] = {
         },
 };
 
+static struct pxafb_mode_info samsung_modes[] = {
+        {
+                .pixclock     = 96153,
+                .bpp          = 16,
+                .xres         = 240,
+                .yres         = 320,
+                .hsync_len    = 8,
+                .vsync_len    = 4,
+                .left_margin  = 9,
+                .upper_margin = 4,
+                .right_margin = 9,
+                .lower_margin = 4,
+                .sync         = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+        },
+};
+
+static void toppoly_lcd_power(int on, struct fb_var_screeninfo *si)
+{
+        pr_debug("Toppoly LCD power\n");
+
+        if (on) {
+                pr_debug("on\n");
+                gpio_set_value(EGPIO_MAGICIAN_TOPPOLY_POWER, 1);
+                gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 1);
+                udelay(2000);
+                gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 1);
+                udelay(2000);
+                /* FIXME: enable LCDC here */
+                udelay(2000);
+                gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 1);
+                udelay(2000);
+                gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 1);
+        } else {
+                pr_debug("off\n");
+                msleep(15);
+                gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 0);
+                udelay(500);
+                gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 0);
+                udelay(1000);
+                gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 0);
+                gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 0);
+        }
+}
+
+static void samsung_lcd_power(int on, struct fb_var_screeninfo *si)
+{
+        pr_debug("Samsung LCD power\n");
+
+        if (on) {
+                pr_debug("on\n");
+                if (system_rev < 3)
+                        gpio_set_value(GPIO75_MAGICIAN_SAMSUNG_POWER, 1);
+                else
+                        gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 1);
+                mdelay(10);
+                gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 1);
+                mdelay(10);
+                gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 1);
+                mdelay(30);
+                gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 1);
+                mdelay(10);
+        } else {
+                pr_debug("off\n");
+                mdelay(10);
+                gpio_set_value(GPIO105_MAGICIAN_LCD_POWER_2, 0);
+                mdelay(30);
+                gpio_set_value(GPIO104_MAGICIAN_LCD_POWER_1, 0);
+                mdelay(10);
+                gpio_set_value(GPIO106_MAGICIAN_LCD_POWER_3, 0);
+                mdelay(10);
+                if (system_rev < 3)
+                        gpio_set_value(GPIO75_MAGICIAN_SAMSUNG_POWER, 0);
+                else
+                        gpio_set_value(EGPIO_MAGICIAN_LCD_POWER, 0);
+        }
+}
+
 static struct pxafb_mach_info toppoly_info = {
-        .modes       = toppoly_modes,
-        .num_modes   = 1,
-        .fixed_modes = 1,
-        .lccr0       = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
-        .lccr3       = LCCR3_PixRsEdg,
+        .modes           = toppoly_modes,
+        .num_modes       = 1,
+        .fixed_modes     = 1,
+        .lccr0           = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lccr3           = LCCR3_PixRsEdg,
+        .pxafb_lcd_power = toppoly_lcd_power,
+};
+
+static struct pxafb_mach_info samsung_info = {
+        .modes           = samsung_modes,
+        .num_modes       = 1,
+        .fixed_modes     = 1,
+        .lccr0           = LCCR0_LDDALT | LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
+        .lccr3           = LCCR3_PixFlEdg,
+        .pxafb_lcd_power = samsung_lcd_power,
 };
 
 /*
@@ -120,9 +345,18 @@ static void magician_set_bl_intensity(int intensity)
         if (intensity) {
                 PWM_CTRL0 = 1;
                 PWM_PERVAL0 = 0xc8;
-                PWM_PWDUTY0 = intensity;
+                if (intensity > 0xc7) {
+                        PWM_PWDUTY0 = intensity - 0x48;
+                        gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 1);
+                } else {
+                        PWM_PWDUTY0 = intensity;
+                        gpio_set_value(EGPIO_MAGICIAN_BL_POWER2, 0);
+                }
+                gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 1);
                 pxa_set_cken(CKEN_PWM0, 1);
         } else {
+                /* PWM_PWDUTY0 = intensity; */
+                gpio_set_value(EGPIO_MAGICIAN_BL_POWER, 0);
                 pxa_set_cken(CKEN_PWM0, 0);
         }
 }
@@ -130,18 +364,215 @@ static void magician_set_bl_intensity(int intensity)
 static struct generic_bl_info backlight_info = {
         .default_intensity = 0x64,
         .limit_mask        = 0x0b,
-        .max_intensity     = 0xc7,
+        .max_intensity     = 0xc7+0x48,
         .set_bl_intensity  = magician_set_bl_intensity,
 };
 
 static struct platform_device backlight = {
-        .name = "corgi-bl",
+        .name = "generic-bl",
         .dev  = {
                 .platform_data = &backlight_info,
         },
         .id   = -1,
 };
 
+/*
+ * LEDs
+ */
+
+struct gpio_led gpio_leds[] = {
+        {
+                .name = "magician::vibra",
+                .default_trigger = "none",
+                .gpio = GPIO22_MAGICIAN_VIBRA_EN,
+        },
+        {
+                .name = "magician::phone_bl",
+                .default_trigger = "none",
+                .gpio = GPIO103_MAGICIAN_LED_KP,
+        },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds = gpio_leds,
+        .num_leds = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+        .name = "leds-gpio",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &gpio_led_info,
+        },
+};
+
+static struct pasic3_led pasic3_leds[] = {
+        {
+                .led = {
+                        .name            = "magician:red",
+                        .default_trigger = "ds2760-battery.0-charging",
+                },
+                .hw_num = 0,
+                .bit2   = PASIC3_BIT2_LED0,
+                .mask   = PASIC3_MASK_LED0,
+        },
+        {
+                .led = {
+                        .name            = "magician:green",
+                        .default_trigger = "ds2760-battery.0-charging-or-full",
+                },
+                .hw_num = 1,
+                .bit2   = PASIC3_BIT2_LED1,
+                .mask   = PASIC3_MASK_LED1,
+        },
+        {
+                .led = {
+                        .name            = "magician:blue",
+                        .default_trigger = "bluetooth",
+                },
+                .hw_num = 2,
+                .bit2   = PASIC3_BIT2_LED2,
+                .mask   = PASIC3_MASK_LED2,
+        },
+};
+
+static struct platform_device pasic3;
+
+static struct pasic3_leds_machinfo __devinit pasic3_leds_info = {
+        .num_leds   = ARRAY_SIZE(pasic3_leds),
+        .power_gpio = EGPIO_MAGICIAN_LED_POWER,
+        .leds       = pasic3_leds,
+};
+
+/*
+ * PASIC3 with DS1WM
+ */
+
+static struct resource pasic3_resources[] = {
+        [0] = {
+                .start  = PXA_CS2_PHYS,
+                .end    = PXA_CS2_PHYS + 0x1b,
+                .flags  = IORESOURCE_MEM,
+        },
+        /* No IRQ handler in the PASIC3, DS1WM needs an external IRQ */
+        [1] = {
+                .start  = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ),
+                .end    = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        }
+};
+
+static struct pasic3_platform_data pasic3_platform_data = {
+        .bus_shift  = 2,
+        .led_pdata  = &pasic3_leds_info,
+        .clock_rate = 4000000,
+};
+
+static struct platform_device pasic3 = {
+        .name           = "pasic3",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pasic3_resources),
+        .resource       = pasic3_resources,
+        .dev = {
+                .platform_data = &pasic3_platform_data,
+        },
+};
+
+/*
+ * External power
+ */
+
+static int magician_is_ac_online(void)
+{
+        return gpio_get_value(EGPIO_MAGICIAN_CABLE_STATE_AC);
+}
+
+static int magician_is_usb_online(void)
+{
+        return gpio_get_value(EGPIO_MAGICIAN_CABLE_STATE_USB);
+}
+
+static void magician_set_charge(int flags)
+{
+        gpio_set_value(GPIO30_MAGICIAN_nCHARGE_EN, !flags);
+        gpio_set_value(EGPIO_MAGICIAN_CHARGE_EN, flags);
+}
+
+static char *magician_supplicants[] = {
+        "ds2760-battery.0", "backup-battery"
+};
+
+static struct pda_power_pdata power_supply_info = {
+        .is_ac_online    = magician_is_ac_online,
+        .is_usb_online   = magician_is_usb_online,
+        .set_charge      = magician_set_charge,
+        .supplied_to     = magician_supplicants,
+        .num_supplicants = ARRAY_SIZE(magician_supplicants),
+};
+
+static struct resource power_supply_resources[] = {
+        [0] = {
+                .name  = "ac",
+                .flags = IORESOURCE_IRQ,
+                .start = IRQ_MAGICIAN_AC,
+                .end   = IRQ_MAGICIAN_AC,
+        },
+        [1] = {
+                .name  = "usb",
+                .flags = IORESOURCE_IRQ,
+                .start = IRQ_MAGICIAN_AC,
+                .end   = IRQ_MAGICIAN_AC,
+        },
+};
+
+static struct platform_device power_supply = {
+        .name = "pda-power",
+        .id   = -1,
+        .dev  = {
+                .platform_data = &power_supply_info,
+        },
+        .resource      = power_supply_resources,
+        .num_resources = ARRAY_SIZE(power_supply_resources),
+};
+
+
+/*
+ * MMC/SD
+ */
+
+static int magician_mci_init(struct device *dev,
+                                irq_handler_t detect_irq, void *data)
+{
+        return request_irq(IRQ_MAGICIAN_SD, detect_irq,
+                                IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
+                                "MMC card detect", data);
+}
+
+static void magician_mci_setpower(struct device *dev, unsigned int vdd)
+{
+        struct pxamci_platform_data *pdata = dev->platform_data;
+
+        gpio_set_value(EGPIO_MAGICIAN_SD_POWER, (1 << vdd) & pdata->ocr_mask);
+}
+
+static int magician_mci_get_ro(struct device *dev)
+{
+        return (!gpio_get_value(EGPIO_MAGICIAN_nSD_READONLY));
+}
+
+static void magician_mci_exit(struct device *dev, void *data)
+{
+        free_irq(IRQ_MAGICIAN_SD, data);
+}
+
+static struct pxamci_platform_data magician_mci_info = {
+        .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
+        .init     = magician_mci_init,
+        .get_ro   = magician_mci_get_ro,
+        .setpower = magician_mci_setpower,
+        .exit     = magician_mci_exit,
+};
+
 
 /*
  * USB OHCI
@@ -166,6 +597,11 @@ static struct pxaohci_platform_data magician_ohci_info = {
  * StrataFlash
  */
 
+static void magician_set_vpp(struct map_info *map, int vpp)
+{
+        gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp);
+}
+
 #define PXA_CS_SIZE             0x04000000
 
 static struct resource strataflash_resource = {
@@ -176,13 +612,14 @@ static struct resource strataflash_resource = {
 
 static struct physmap_flash_data strataflash_data = {
         .width = 4,
+        .set_vpp = magician_set_vpp,
 };
 
 static struct platform_device strataflash = {
         .name          = "physmap-flash",
         .id            = -1,
-        .num_resources = 1,
         .resource      = &strataflash_resource,
+        .num_resources = 1,
         .dev = {
                 .platform_data = &strataflash_data,
         },
@@ -194,16 +631,43 @@ static struct platform_device strataflash = {
 
 static struct platform_device *devices[] __initdata = {
         &gpio_keys,
+        &egpio,
         &backlight,
+        &pasic3,
+        &power_supply,
         &strataflash,
+        &leds_gpio,
 };
 
 static void __init magician_init(void)
 {
+        void __iomem *cpld;
+        int lcd_select;
+
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config));
+
         platform_add_devices(devices, ARRAY_SIZE(devices));
+        pxa_set_i2c_info(NULL);
+        pxa_set_mci_info(&magician_mci_info);
         pxa_set_ohci_info(&magician_ohci_info);
         pxa_set_ficp_info(&magician_ficp_info);
-        set_pxa_fb_info(&toppoly_info);
+
+        /* Check LCD type we have */
+        cpld = ioremap_nocache(PXA_CS3_PHYS, 0x1000);
+        if (cpld) {
+                u8 board_id = __raw_readb(cpld+0x14);
+                system_rev = board_id & 0x7;
+                lcd_select = board_id & 0x8;
+                iounmap(cpld);
+                pr_info("LCD type: %s\n", lcd_select ? "Samsung" : "Toppoly");
+                if (lcd_select && (system_rev < 3))
+                        pxa_gpio_mode(GPIO75_MAGICIAN_SAMSUNG_POWER_MD);
+                pxa_gpio_mode(GPIO104_MAGICIAN_LCD_POWER_1_MD);
+                pxa_gpio_mode(GPIO105_MAGICIAN_LCD_POWER_2_MD);
+                pxa_gpio_mode(GPIO106_MAGICIAN_LCD_POWER_3_MD);
+                set_pxa_fb_info(lcd_select ? &samsung_info : &toppoly_info);
+        } else
+                pr_err("LCD detection: CPLD mapping failed\n");
 }
 
 
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 72a436fb9a29..18d47cfa2a18 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -24,6 +24,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/backlight.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -40,16 +42,94 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/mfp-pxa27x.h>
 #include <asm/arch/mainstone.h>
 #include <asm/arch/audio.h>
 #include <asm/arch/pxafb.h>
+#include <asm/arch/i2c.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/ohci.h>
+#include <asm/arch/pxa27x_keypad.h>
 
 #include "generic.h"
 #include "devices.h"
 
+static unsigned long mainstone_pin_config[] = {
+        /* Chip Select */
+        GPIO15_nCS_1,
+
+        /* LCD - 16bpp Active TFT */
+        GPIO58_LCD_LDD_0,
+        GPIO59_LCD_LDD_1,
+        GPIO60_LCD_LDD_2,
+        GPIO61_LCD_LDD_3,
+        GPIO62_LCD_LDD_4,
+        GPIO63_LCD_LDD_5,
+        GPIO64_LCD_LDD_6,
+        GPIO65_LCD_LDD_7,
+        GPIO66_LCD_LDD_8,
+        GPIO67_LCD_LDD_9,
+        GPIO68_LCD_LDD_10,
+        GPIO69_LCD_LDD_11,
+        GPIO70_LCD_LDD_12,
+        GPIO71_LCD_LDD_13,
+        GPIO72_LCD_LDD_14,
+        GPIO73_LCD_LDD_15,
+        GPIO74_LCD_FCLK,
+        GPIO75_LCD_LCLK,
+        GPIO76_LCD_PCLK,
+        GPIO77_LCD_BIAS,
+        GPIO16_PWM0_OUT,        /* Backlight */
+
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO112_MMC_CMD,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+
+        /* USB Host Port 1 */
+        GPIO88_USBH1_PWR,
+        GPIO89_USBH1_PEN,
+
+        /* PC Card */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO85_nPCE_1,
+        GPIO54_nPCE_2,
+        GPIO79_PSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+
+        /* AC97 */
+        GPIO45_AC97_SYSCLK,
+
+        /* Keypad */
+        GPIO93_KP_DKIN_0        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO94_KP_DKIN_1        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO95_KP_DKIN_2        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO100_KP_MKIN_0       | WAKEUP_ON_LEVEL_HIGH,
+        GPIO101_KP_MKIN_1       | WAKEUP_ON_LEVEL_HIGH,
+        GPIO102_KP_MKIN_2       | WAKEUP_ON_LEVEL_HIGH,
+        GPIO97_KP_MKIN_3        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO98_KP_MKIN_4        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO99_KP_MKIN_5        | WAKEUP_ON_LEVEL_HIGH,
+        GPIO103_KP_MKOUT_0,
+        GPIO104_KP_MKOUT_1,
+        GPIO105_KP_MKOUT_2,
+        GPIO106_KP_MKOUT_3,
+        GPIO107_KP_MKOUT_4,
+        GPIO108_KP_MKOUT_5,
+        GPIO96_KP_MKOUT_6,
+
+        /* GPIO */
+        GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
+};
 
 static unsigned long mainstone_irq_enabled;
 
@@ -278,13 +358,13 @@ static int mainstone_backlight_update_status(struct backlight_device *bl)
             bl->props.fb_blank != FB_BLANK_UNBLANK)
                 brightness = 0;
 
-        if (brightness != 0) {
-                pxa_gpio_mode(GPIO16_PWM0_MD);
+        if (brightness != 0)
                 pxa_set_cken(CKEN_PWM0, 1);
-        }
+
         PWM_CTRL0 = 0;
         PWM_PWDUTY0 = brightness;
         PWM_PERVAL0 = bl->props.max_brightness;
+
         if (brightness == 0)
                 pxa_set_cken(CKEN_PWM0, 0);
         return 0; /* pointless return value */
@@ -362,16 +442,6 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in
 {
         int err;
 
-        /*
-         * setup GPIO for PXA27x MMC controller
-         */
-        pxa_gpio_mode(GPIO32_MMCCLK_MD);
-        pxa_gpio_mode(GPIO112_MMCCMD_MD);
-        pxa_gpio_mode(GPIO92_MMCDAT0_MD);
-        pxa_gpio_mode(GPIO109_MMCDAT1_MD);
-        pxa_gpio_mode(GPIO110_MMCDAT2_MD);
-        pxa_gpio_mode(GPIO111_MMCDAT3_MD);
-
         /* make sure SD/Memory Stick multiplexer's signals
          * are routed to MMC controller
          */
@@ -434,19 +504,39 @@ static struct pxaficp_platform_data mainstone_ficp_platform_data = {
         .transceiver_mode = mainstone_irda_transceiver_mode,
 };
 
+static struct gpio_keys_button gpio_keys_button[] = {
+        [0] = {
+                .desc   = "wakeup",
+                .code   = KEY_SUSPEND,
+                .type   = EV_KEY,
+                .gpio   = 1,
+                .wakeup = 1,
+        },
+};
+
+static struct gpio_keys_platform_data mainstone_gpio_keys = {
+        .buttons        = gpio_keys_button,
+        .nbuttons       = 1,
+};
+
+static struct platform_device mst_gpio_keys_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &mainstone_gpio_keys,
+        },
+};
+
 static struct platform_device *platform_devices[] __initdata = {
         &smc91x_device,
         &mst_audio_device,
         &mst_flash_device[0],
         &mst_flash_device[1],
+        &mst_gpio_keys_device,
 };
 
 static int mainstone_ohci_init(struct device *dev)
 {
-        /* setup Port1 GPIO pin. */
-        pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN);  /* USBHPWR1 */
-        pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
-
         /* Set the Power Control Polarity Low and Power Sense
            Polarity Low to active low. */
         UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
@@ -460,10 +550,63 @@ static struct pxaohci_platform_data mainstone_ohci_platform_data = {
         .init           = mainstone_ohci_init,
 };
 
+#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
+static unsigned int mainstone_matrix_keys[] = {
+        KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C),
+        KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F),
+        KEY(0, 1, KEY_G), KEY(1, 1, KEY_H), KEY(2, 1, KEY_I),
+        KEY(3, 1, KEY_J), KEY(4, 1, KEY_K), KEY(5, 1, KEY_L),
+        KEY(0, 2, KEY_M), KEY(1, 2, KEY_N), KEY(2, 2, KEY_O),
+        KEY(3, 2, KEY_P), KEY(4, 2, KEY_Q), KEY(5, 2, KEY_R),
+        KEY(0, 3, KEY_S), KEY(1, 3, KEY_T), KEY(2, 3, KEY_U),
+        KEY(3, 3, KEY_V), KEY(4, 3, KEY_W), KEY(5, 3, KEY_X),
+        KEY(2, 4, KEY_Y), KEY(3, 4, KEY_Z),
+
+        KEY(0, 4, KEY_DOT),     /* . */
+        KEY(1, 4, KEY_CLOSE),   /* @ */
+        KEY(4, 4, KEY_SLASH),
+        KEY(5, 4, KEY_BACKSLASH),
+        KEY(0, 5, KEY_HOME),
+        KEY(1, 5, KEY_LEFTSHIFT),
+        KEY(2, 5, KEY_SPACE),
+        KEY(3, 5, KEY_SPACE),
+        KEY(4, 5, KEY_ENTER),
+        KEY(5, 5, KEY_BACKSPACE),
+
+        KEY(0, 6, KEY_UP),
+        KEY(1, 6, KEY_DOWN),
+        KEY(2, 6, KEY_LEFT),
+        KEY(3, 6, KEY_RIGHT),
+        KEY(4, 6, KEY_SELECT),
+};
+
+struct pxa27x_keypad_platform_data mainstone_keypad_info = {
+        .matrix_key_rows        = 6,
+        .matrix_key_cols        = 7,
+        .matrix_key_map         = mainstone_matrix_keys,
+        .matrix_key_map_size    = ARRAY_SIZE(mainstone_matrix_keys),
+
+        .enable_rotary0         = 1,
+        .rotary0_up_key         = KEY_UP,
+        .rotary0_down_key       = KEY_DOWN,
+
+        .debounce_interval      = 30,
+};
+
+static void __init mainstone_init_keypad(void)
+{
+        pxa_set_keypad_info(&mainstone_keypad_info);
+}
+#else
+static inline void mainstone_init_keypad(void) {}
+#endif
+
 static void __init mainstone_init(void)
 {
         int SW7 = 0;  /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
 
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config));
+
         mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
         mst_flash_data[1].width = 4;
 
@@ -480,31 +623,6 @@ static void __init mainstone_init(void)
          */
         ARB_CNTRL = ARB_CORE_PARK | 0x234;
 
-        /*
-         * On Mainstone, we route AC97_SYSCLK via GPIO45 to
-         * the audio daughter card
-         */
-        pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
-
-        GPSR(GPIO48_nPOE) =
-                GPIO_bit(GPIO48_nPOE) |
-                GPIO_bit(GPIO49_nPWE) |
-                GPIO_bit(GPIO50_nPIOR) |
-                GPIO_bit(GPIO51_nPIOW) |
-                GPIO_bit(GPIO85_nPCE_1) |
-                GPIO_bit(GPIO54_nPCE_2);
-
-        pxa_gpio_mode(GPIO48_nPOE_MD);
-        pxa_gpio_mode(GPIO49_nPWE_MD);
-        pxa_gpio_mode(GPIO50_nPIOR_MD);
-        pxa_gpio_mode(GPIO51_nPIOW_MD);
-        pxa_gpio_mode(GPIO85_nPCE_1_MD);
-        pxa_gpio_mode(GPIO54_nPCE_2_MD);
-        pxa_gpio_mode(GPIO79_pSKTSEL_MD);
-        pxa_gpio_mode(GPIO55_nPREG_MD);
-        pxa_gpio_mode(GPIO56_nPWAIT_MD);
-        pxa_gpio_mode(GPIO57_nIOIS16_MD);
-
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
         /* reading Mainstone's "Virtual Configuration Register"
@@ -520,6 +638,9 @@ static void __init mainstone_init(void)
         pxa_set_mci_info(&mainstone_mci_platform_data);
         pxa_set_ficp_info(&mainstone_ficp_platform_data);
         pxa_set_ohci_info(&mainstone_ohci_platform_data);
+        pxa_set_i2c_info(NULL);
+
+        mainstone_init_keypad();
 }
 
 
@@ -537,23 +658,9 @@ static void __init mainstone_map_io(void)
         pxa_map_io();
         iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
 
-        /* initialize sleep mode regs (wake-up sources, etc) */
-        PGSR0 = 0x00008800;
-        PGSR1 = 0x00000002;
-        PGSR2 = 0x0001FC00;
-        PGSR3 = 0x00001F81;
-        PWER  = 0xC0000002;
-        PRER  = 0x00000002;
-        PFER  = 0x00000002;
         /*      for use I SRAM as framebuffer.  */
         PSLR |= 0xF04;
         PCFR = 0x66;
-        /*      For Keypad wakeup.      */
-        KPC &=~KPC_ASACT;
-        KPC |=KPC_AS;
-        PKWR  = 0x000FD000;
-        /*      Need read PKWR back after set it.       */
-        PKWR;
 }
 
 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
new file mode 100644
index 000000000000..22097a1707cc
--- /dev/null
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -0,0 +1,245 @@
+/*
+ *  linux/arch/arm/mach-pxa/mfp-pxa2xx.c
+ *
+ *  PXA2xx pin mux configuration support
+ *
+ *  The GPIOs on PXA2xx can be configured as one of many alternate
+ *  functions, this is by concept samilar to the MFP configuration
+ *  on PXA3xx,  what's more important, the low power pin state and
+ *  wakeup detection are also supported by the same framework.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/mfp-pxa2xx.h>
+
+#include "generic.h"
+
+#define PGSR(x)         __REG2(0x40F00020, ((x) & 0x60) >> 3)
+
+#define PWER_WE35       (1 << 24)
+
+struct gpio_desc {
+        unsigned        valid           : 1;
+        unsigned        can_wakeup      : 1;
+        unsigned        keypad_gpio     : 1;
+        unsigned int    mask; /* bit mask in PWER or PKWR */
+        unsigned long   config;
+};
+
+static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];
+
+static int __mfp_config_gpio(unsigned gpio, unsigned long c)
+{
+        unsigned long gafr, mask = GPIO_bit(gpio);
+        int fn;
+
+        fn = MFP_AF(c);
+        if (fn > 3)
+                return -EINVAL;
+
+        /* alternate function and direction */
+        gafr = GAFR(gpio) & ~(0x3 << ((gpio & 0xf) * 2));
+        GAFR(gpio) = gafr |  (fn  << ((gpio & 0xf) * 2));
+
+        if (c & MFP_DIR_OUT)
+                GPDR(gpio) |= mask;
+        else
+                GPDR(gpio) &= ~mask;
+
+        /* low power state */
+        switch (c & MFP_LPM_STATE_MASK) {
+        case MFP_LPM_DRIVE_HIGH:
+                PGSR(gpio) |= mask;
+                break;
+        case MFP_LPM_DRIVE_LOW:
+                PGSR(gpio) &= ~mask;
+                break;
+        case MFP_LPM_INPUT:
+                break;
+        default:
+                pr_warning("%s: invalid low power state for GPIO%d\n",
+                                __func__, gpio);
+                return -EINVAL;
+        }
+
+        /* give early warning if MFP_LPM_CAN_WAKEUP is set on the
+         * configurations of those pins not able to wakeup
+         */
+        if ((c & MFP_LPM_CAN_WAKEUP) && !gpio_desc[gpio].can_wakeup) {
+                pr_warning("%s: GPIO%d unable to wakeup\n",
+                                __func__, gpio);
+                return -EINVAL;
+        }
+
+        if ((c & MFP_LPM_CAN_WAKEUP) && (c & MFP_DIR_OUT)) {
+                pr_warning("%s: output GPIO%d unable to wakeup\n",
+                                __func__, gpio);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
+{
+        unsigned long flags;
+        unsigned long *c;
+        int i, gpio;
+
+        for (i = 0, c = mfp_cfgs; i < num; i++, c++) {
+
+                gpio = mfp_to_gpio(MFP_PIN(*c));
+
+                if (!gpio_desc[gpio].valid) {
+                        pr_warning("%s: GPIO%d is invalid pin\n",
+                                __func__, gpio);
+                        continue;
+                }
+
+                local_irq_save(flags);
+
+                gpio_desc[gpio].config = *c;
+                __mfp_config_gpio(gpio, *c);
+
+                local_irq_restore(flags);
+        }
+}
+
+int gpio_set_wake(unsigned int gpio, unsigned int on)
+{
+        struct gpio_desc *d;
+        unsigned long c;
+
+        if (gpio > mfp_to_gpio(MFP_PIN_GPIO127))
+                return -EINVAL;
+
+        d = &gpio_desc[gpio];
+        c = d->config;
+
+        if (!d->valid)
+                return -EINVAL;
+
+        if (d->keypad_gpio)
+                return -EINVAL;
+
+        if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) {
+                if (on) {
+                        PWER |= d->mask;
+
+                        if (c & MFP_LPM_EDGE_RISE)
+                                PRER |= d->mask;
+                        else
+                                PRER &= ~d->mask;
+
+                        if (c & MFP_LPM_EDGE_FALL)
+                                PFER |= d->mask;
+                        else
+                                PFER &= ~d->mask;
+                } else {
+                        PWER &= ~d->mask;
+                        PRER &= ~d->mask;
+                        PFER &= ~d->mask;
+                }
+        }
+        return 0;
+}
+
+#ifdef CONFIG_PXA25x
+static int __init pxa25x_mfp_init(void)
+{
+        int i;
+
+        if (cpu_is_pxa25x()) {
+                for (i = 0; i <= 84; i++)
+                        gpio_desc[i].valid = 1;
+
+                for (i = 0; i <= 15; i++) {
+                        gpio_desc[i].can_wakeup = 1;
+                        gpio_desc[i].mask = GPIO_bit(i);
+                }
+        }
+
+        return 0;
+}
+postcore_initcall(pxa25x_mfp_init);
+#endif /* CONFIG_PXA25x */
+
+#ifdef CONFIG_PXA27x
+static int pxa27x_pkwr_gpio[] = {
+        13, 16, 17, 34, 36, 37, 38, 39, 90, 91, 93, 94,
+        95, 96, 97, 98, 99, 100, 101, 102
+};
+
+int keypad_set_wake(unsigned int on)
+{
+        unsigned int i, gpio, mask = 0;
+
+        if (!on) {
+                PKWR = 0;
+                return 0;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
+
+                gpio = pxa27x_pkwr_gpio[i];
+
+                if (gpio_desc[gpio].config & MFP_LPM_CAN_WAKEUP)
+                        mask |= gpio_desc[gpio].mask;
+        }
+
+        PKWR = mask;
+        return 0;
+}
+
+static int __init pxa27x_mfp_init(void)
+{
+        int i, gpio;
+
+        if (cpu_is_pxa27x()) {
+                for (i = 0; i <= 120; i++) {
+                        /* skip GPIO2, 5, 6, 7, 8, they are not
+                         * valid pins allow configuration
+                         */
+                        if (i == 2 || i == 5 || i == 6 ||
+                            i == 7 || i == 8)
+                                continue;
+
+                        gpio_desc[i].valid = 1;
+                }
+
+                /* Keypad GPIOs */
+                for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
+                        gpio = pxa27x_pkwr_gpio[i];
+                        gpio_desc[gpio].can_wakeup = 1;
+                        gpio_desc[gpio].keypad_gpio = 1;
+                        gpio_desc[gpio].mask = 1 << i;
+                }
+
+                /* Overwrite GPIO13 as a PWER wakeup source */
+                for (i = 0; i <= 15; i++) {
+                        /* skip GPIO2, 5, 6, 7, 8 */
+                        if (GPIO_bit(i) & 0x1e4)
+                                continue;
+
+                        gpio_desc[i].can_wakeup = 1;
+                        gpio_desc[i].mask = GPIO_bit(i);
+                }
+
+                gpio_desc[35].can_wakeup = 1;
+                gpio_desc[35].mask = PWER_WE35;
+        }
+
+        return 0;
+}
+postcore_initcall(pxa27x_mfp_init);
+#endif /* CONFIG_PXA27x */
diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp-pxa3xx.c
index f5809adce298..b84c3ba7a8d6 100644
--- a/arch/arm/mach-pxa/mfp.c
+++ b/arch/arm/mach-pxa/mfp-pxa3xx.c
@@ -234,22 +234,22 @@ static int pxa3xx_mfp_resume(struct sys_device *d)
 
         return 0;
 }
+#else
+#define pxa3xx_mfp_suspend      NULL
+#define pxa3xx_mfp_resume       NULL
+#endif
 
-static struct sysdev_class mfp_sysclass = {
+struct sysdev_class pxa3xx_mfp_sysclass = {
         .name           = "mfp",
         .suspend        = pxa3xx_mfp_suspend,
         .resume         = pxa3xx_mfp_resume,
 };
 
-static struct sys_device mfp_device = {
-        .id             = 0,
-        .cls            = &mfp_sysclass,
-};
-
 static int __init mfp_init_devicefs(void)
 {
-        sysdev_class_register(&mfp_sysclass);
-        return sysdev_register(&mfp_device);
+        if (cpu_is_pxa3xx())
+                return sysdev_class_register(&pxa3xx_mfp_sysclass);
+
+        return 0;
 }
-device_initcall(mfp_init_devicefs);
-#endif
+postcore_initcall(mfp_init_devicefs);
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index c14696b9979d..3b945eb0aee3 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -29,6 +29,7 @@
 #include <asm/mach/arch.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/pxa2xx-regs.h>
 #include <asm/arch/pxa2xx_spi.h>
 #include <asm/arch/pcm027.h>
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 3dda16a20049..e6be9d0aeccf 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -23,8 +23,16 @@
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/ide.h>
+#include <linux/i2c.h>
+
+#include <media/soc_camera.h>
+
+#include <asm/gpio.h>
+#include <asm/arch/i2c.h>
+#include <asm/arch/camera.h>
 #include <asm/mach/map.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/pcm990_baseboard.h>
@@ -258,6 +266,76 @@ static struct pxaohci_platform_data pcm990_ohci_platform_data = {
 };
 
 /*
+ * PXA27x Camera specific stuff
+ */
+#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
+static int pcm990_pxacamera_init(struct device *dev)
+{
+        pxa_gpio_mode(GPIO98_CIF_DD_0_MD);
+        pxa_gpio_mode(GPIO105_CIF_DD_1_MD);
+        pxa_gpio_mode(GPIO104_CIF_DD_2_MD);
+        pxa_gpio_mode(GPIO103_CIF_DD_3_MD);
+        pxa_gpio_mode(GPIO95_CIF_DD_4_MD);
+        pxa_gpio_mode(GPIO94_CIF_DD_5_MD);
+        pxa_gpio_mode(GPIO93_CIF_DD_6_MD);
+        pxa_gpio_mode(GPIO108_CIF_DD_7_MD);
+        pxa_gpio_mode(GPIO107_CIF_DD_8_MD);
+        pxa_gpio_mode(GPIO106_CIF_DD_9_MD);
+        pxa_gpio_mode(GPIO42_CIF_MCLK_MD);
+        pxa_gpio_mode(GPIO45_CIF_PCLK_MD);
+        pxa_gpio_mode(GPIO43_CIF_FV_MD);
+        pxa_gpio_mode(GPIO44_CIF_LV_MD);
+
+        return 0;
+}
+
+/*
+ * CICR4: PCLK_EN:      Pixel clock is supplied by the sensor
+ *      MCLK_EN:        Master clock is generated by PXA
+ *      PCP:            Data sampled on the falling edge of pixel clock
+ */
+struct pxacamera_platform_data pcm990_pxacamera_platform_data = {
+        .init   = pcm990_pxacamera_init,
+        .flags  = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | PXA_CAMERA_DATAWIDTH_10 |
+                PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN/* | PXA_CAMERA_PCP*/,
+        .mclk_10khz = 1000,
+};
+
+#include <linux/i2c/pca953x.h>
+
+static struct pca953x_platform_data pca9536_data = {
+        .gpio_base      = NR_BUILTIN_GPIO + 1,
+};
+
+static struct soc_camera_link iclink[] = {
+        {
+                .bus_id = 0, /* Must match with the camera ID above */
+                .gpio   = NR_BUILTIN_GPIO + 1,
+        }, {
+                .bus_id = 0, /* Must match with the camera ID above */
+        }
+};
+
+/* Board I2C devices. */
+static struct i2c_board_info __initdata pcm990_i2c_devices[] = {
+        {
+                /* Must initialize before the camera(s) */
+                I2C_BOARD_INFO("pca953x", 0x41),
+                .type = "pca9536",
+                .platform_data = &pca9536_data,
+        }, {
+                I2C_BOARD_INFO("mt9v022", 0x48),
+                .type = "mt9v022",
+                .platform_data = &iclink[0], /* With extender */
+        }, {
+                I2C_BOARD_INFO("mt9m001", 0x5d),
+                .type = "mt9m001",
+                .platform_data = &iclink[0], /* With extender */
+        },
+};
+#endif /* CONFIG_VIDEO_PXA27x ||CONFIG_VIDEO_PXA27x_MODULE */
+
+/*
  * AC97 support
  * Note: The connected AC97 mixer also reports interrupts at PCM990_AC97_IRQ
  */
@@ -326,5 +404,14 @@ void __init pcm990_baseboard_init(void)
         /* USB host */
         pxa_set_ohci_info(&pcm990_ohci_platform_data);
 
+        pxa_set_i2c_info(NULL);
+
+#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
+        pxa_set_camera_info(&pcm990_pxacamera_platform_data);
+
+        i2c_register_board_info(0, pcm990_i2c_devices,
+                ARRAY_SIZE(pcm990_i2c_devices));
+#endif
+
         printk(KERN_INFO"PCM-990 Evaluation baseboard initialized\n");
 }
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 209eabf0ed3e..ca5ac196b47b 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -32,6 +32,7 @@
 #include <asm/mach/irq.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/udc.h>
 #include <asm/arch/irda.h>
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 599e53fcc2c5..d9b5450aee5b 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -26,6 +26,7 @@
 #include <asm/hardware.h>
 #include <asm/arch/irqs.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/mfp-pxa25x.h>
 #include <asm/arch/pm.h>
 #include <asm/arch/dma.h>
 
@@ -129,6 +130,8 @@ static struct clk pxa25x_clks[] = {
         INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
         INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
 
+        INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),
+
         /*
         INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
         INIT_CKEN("PWMCLK",  PWM0, 3686400,  0, NULL),
@@ -228,24 +231,10 @@ static inline void pxa25x_init_pm(void) {}
 static int pxa25x_set_wake(unsigned int irq, unsigned int on)
 {
         int gpio = IRQ_TO_GPIO(irq);
-        uint32_t gpio_bit, mask = 0;
-
-        if (gpio >= 0 && gpio <= 15) {
-                gpio_bit = GPIO_bit(gpio);
-                mask = gpio_bit;
-                if (on) {
-                        if (GRER(gpio) | gpio_bit)
-                                PRER |= gpio_bit;
-                        else
-                                PRER &= ~gpio_bit;
-
-                        if (GFER(gpio) | gpio_bit)
-                                PFER |= gpio_bit;
-                        else
-                                PFER &= ~gpio_bit;
-                }
-                goto set_pwer;
-        }
+        uint32_t mask = 0;
+
+        if (gpio >= 0 && gpio < 85)
+                return gpio_set_wake(gpio, on);
 
         if (irq == IRQ_RTCAlrm) {
                 mask = PWER_RTC;
@@ -265,9 +254,8 @@ set_pwer:
 
 void __init pxa25x_init_irq(void)
 {
-        pxa_init_irq_low();
-        pxa_init_irq_gpio(85);
-        pxa_init_irq_set_wake(pxa25x_set_wake);
+        pxa_init_irq(32, pxa25x_set_wake);
+        pxa_init_gpio(85, pxa25x_set_wake);
 }
 
 static struct platform_device *pxa25x_devices[] __initdata = {
@@ -325,4 +313,4 @@ static int __init pxa25x_init(void)
         return ret;
 }
 
-subsys_initcall(pxa25x_init);
+postcore_initcall(pxa25x_init);
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 46a951c3e5a0..7a2449dd0fd4 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -23,6 +23,7 @@
 #include <asm/arch/irqs.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/mfp-pxa27x.h>
 #include <asm/arch/ohci.h>
 #include <asm/arch/pm.h>
 #include <asm/arch/dma.h>
@@ -151,12 +152,15 @@ static struct clk pxa27x_clks[] = {
 
         INIT_CKEN("USBCLK", USBHOST, 48000000, 0, &pxa27x_device_ohci.dev),
         INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
-        INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
+        INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev),
 
         INIT_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
         INIT_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
         INIT_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
 
+        INIT_CKEN("AC97CLK",     AC97,     24576000, 0, NULL),
+        INIT_CKEN("AC97CONFCLK", AC97CONF, 24576000, 0, NULL),
+
         /*
         INIT_CKEN("PWMCLK",  PWM0, 13000000, 0, NULL),
         INIT_CKEN("MSLCLK",  MSL,  48000000, 0, NULL),
@@ -283,37 +287,16 @@ static inline void pxa27x_init_pm(void) {}
 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
  * handles the simple cases, not the WEMUX2 and WEMUX3 options
  */
-#define PXA27x_GPIO_NOWAKE_MASK \
-        ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
-#define WAKEMASK(gpio) \
-        (((gpio) <= 15) \
-                 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
-                 : ((gpio == 35) ? (1 << 24) : 0))
-
 static int pxa27x_set_wake(unsigned int irq, unsigned int on)
 {
         int gpio = IRQ_TO_GPIO(irq);
         uint32_t mask;
 
-        if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) {
-                if (WAKEMASK(gpio) == 0)
-                        return -EINVAL;
-
-                mask = WAKEMASK(gpio);
-
-                if (on) {
-                        if (GRER(gpio) | GPIO_bit(gpio))
-                                PRER |= mask;
-                        else
-                                PRER &= ~mask;
+        if (gpio >= 0 && gpio < 128)
+                return gpio_set_wake(gpio, on);
 
-                        if (GFER(gpio) | GPIO_bit(gpio))
-                                PFER |= mask;
-                        else
-                                PFER &= ~mask;
-                }
-                goto set_pwer;
-        }
+        if (irq == IRQ_KEYPAD)
+                return keypad_set_wake(on);
 
         switch (irq) {
         case IRQ_RTCAlrm:
@@ -326,7 +309,6 @@ static int pxa27x_set_wake(unsigned int irq, unsigned int on)
                 return -EINVAL;
         }
 
-set_pwer:
         if (on)
                 PWER |= mask;
         else
@@ -337,10 +319,8 @@ set_pwer:
 
 void __init pxa27x_init_irq(void)
 {
-        pxa_init_irq_low();
-        pxa_init_irq_high();
-        pxa_init_irq_gpio(128);
-        pxa_init_irq_set_wake(pxa27x_set_wake);
+        pxa_init_irq(34, pxa27x_set_wake);
+        pxa_init_gpio(128, pxa27x_set_wake);
 }
 
 /*
@@ -386,10 +366,6 @@ static struct platform_device *devices[] __initdata = {
 
 static struct sys_device pxa27x_sysdev[] = {
         {
-                .id     = 0,
-                .cls    = &pxa_irq_sysclass,
-        }, {
-                .id     = 1,
                 .cls    = &pxa_irq_sysclass,
         }, {
                 .cls    = &pxa_gpio_sysclass,
@@ -420,4 +396,4 @@ static int __init pxa27x_init(void)
         return ret;
 }
 
-subsys_initcall(pxa27x_init);
+postcore_initcall(pxa27x_init);
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 35f25fdaeba3..dde355e88fa1 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -110,6 +110,25 @@ unsigned int pxa3xx_get_memclk_frequency_10khz(void)
 }
 
 /*
+ * Return the current AC97 clock frequency.
+ */
+static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
+{
+        unsigned long rate = 312000000;
+        unsigned long ac97_div;
+
+        ac97_div = AC97_DIV;
+
+        /* This may loose precision for some rates but won't for the
+         * standard 24.576MHz.
+         */
+        rate /= (ac97_div >> 12) & 0x7fff;
+        rate *= (ac97_div & 0xfff);
+
+        return rate;
+}
+
+/*
  * Return the current HSIO bus clock frequency
  */
 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
@@ -156,6 +175,27 @@ static const struct clkops clk_pxa3xx_hsio_ops = {
         .getrate        = clk_pxa3xx_hsio_getrate,
 };
 
+static const struct clkops clk_pxa3xx_ac97_ops = {
+        .enable         = clk_pxa3xx_cken_enable,
+        .disable        = clk_pxa3xx_cken_disable,
+        .getrate        = clk_pxa3xx_ac97_getrate,
+};
+
+static void clk_pout_enable(struct clk *clk)
+{
+        OSCC |= OSCC_PEN;
+}
+
+static void clk_pout_disable(struct clk *clk)
+{
+        OSCC &= ~OSCC_PEN;
+}
+
+static const struct clkops clk_pout_ops = {
+        .enable         = clk_pout_enable,
+        .disable        = clk_pout_disable,
+};
+
 #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev)  \
         {                                               \
                 .name   = _name,                        \
@@ -175,8 +215,16 @@ static const struct clkops clk_pxa3xx_hsio_ops = {
         }
 
 static struct clk pxa3xx_clks[] = {
-        PXA3xx_CK("LCDCLK", LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
-        PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
+        {
+                .name           = "CLK_POUT",
+                .ops            = &clk_pout_ops,
+                .rate           = 13000000,
+                .delay          = 70,
+        },
+
+        PXA3xx_CK("LCDCLK",  LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
+        PXA3xx_CK("CAMCLK",  CAMERA, &clk_pxa3xx_hsio_ops, NULL),
+        PXA3xx_CK("AC97CLK", AC97,   &clk_pxa3xx_ac97_ops, NULL),
 
         PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
         PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
@@ -185,6 +233,7 @@ static struct clk pxa3xx_clks[] = {
         PXA3xx_CKEN("I2CCLK", I2C,  32842000, 0, &pxa_device_i2c.dev),
         PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa_device_udc.dev),
         PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
+        PXA3xx_CKEN("KBDCLK", KEYPAD,  32768, 0, &pxa27x_device_keypad.dev),
 
         PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
         PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
@@ -305,8 +354,10 @@ static void pxa3xx_cpu_pm_enter(suspend_state_t state)
         /*
          * Don't sleep if no wakeup sources are defined
          */
-        if (wakeup_src == 0)
+        if (wakeup_src == 0) {
+                printk(KERN_ERR "Not suspending: no wakeup sources\n");
                 return;
+        }
 
         switch (state) {
         case PM_SUSPEND_STANDBY:
@@ -446,15 +497,9 @@ static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
 
         return 0;
 }
-
-static void pxa3xx_init_irq_pm(void)
-{
-        pxa_init_irq_set_wake(pxa3xx_set_wake);
-}
-
 #else
 static inline void pxa3xx_init_pm(void) {}
-static inline void pxa3xx_init_irq_pm(void) {}
+#define pxa3xx_set_wake NULL
 #endif
 
 void __init pxa3xx_init_irq(void)
@@ -465,10 +510,8 @@ void __init pxa3xx_init_irq(void)
         value |= (1 << 6);
         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 
-        pxa_init_irq_low();
-        pxa_init_irq_high();
-        pxa_init_irq_gpio(128);
-        pxa3xx_init_irq_pm();
+        pxa_init_irq(56, pxa3xx_set_wake);
+        pxa_init_gpio(128, NULL);
 }
 
 /*
@@ -490,11 +533,9 @@ static struct platform_device *devices[] __initdata = {
 
 static struct sys_device pxa3xx_sysdev[] = {
         {
-                .id     = 0,
                 .cls    = &pxa_irq_sysclass,
         }, {
-                .id     = 1,
-                .cls    = &pxa_irq_sysclass,
+                .cls    = &pxa3xx_mfp_sysclass,
         }, {
                 .cls    = &pxa_gpio_sysclass,
         },
@@ -532,4 +573,4 @@ static int __init pxa3xx_init(void)
         return ret;
 }
 
-subsys_initcall(pxa3xx_init);
+postcore_initcall(pxa3xx_init);
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index f9d1b61e1185..34cd585075b0 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -26,6 +26,7 @@
 #include <asm/mach-types.h>
 #include <asm/arch/pm.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/sharpsl.h>
 #include "sharpsl.h"
 
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 9e7773fca01c..62a02c3927c5 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -37,6 +37,7 @@
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/ohci.h>
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 745a4dc7acdd..7a7f5f947cc5 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -26,6 +26,7 @@
 #include <asm/arch/sharpsl.h>
 #include <asm/arch/spitz.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include "sharpsl.h"
 
 #define SHARPSL_CHARGE_ON_VOLT         0x99  /* 2.9V */
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index f99112d50b41..6458f6d371d9 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -23,6 +23,7 @@
 #include <linux/delay.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/gpio.h>
 
 #include <asm/setup.h>
 #include <asm/memory.h>
@@ -32,7 +33,9 @@
 #include <asm/system.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/arch/pxa2xx-regs.h>
+#include <asm/arch/mfp-pxa25x.h>
 #include <asm/arch/irda.h>
+#include <asm/arch/i2c.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/udc.h>
 
@@ -47,6 +50,110 @@
 #include "generic.h"
 #include "devices.h"
 
+static unsigned long tosa_pin_config[] = {
+        GPIO78_nCS_2, /* Scoop */
+        GPIO80_nCS_4, /* tg6393xb */
+        GPIO33_nCS_5, /* Scoop */
+
+        // GPIO76 CARD_VCC_ON1
+
+        GPIO19_GPIO, /* Reset out */
+        GPIO1_RST | WAKEUP_ON_EDGE_FALL,
+
+        GPIO0_GPIO | WAKEUP_ON_EDGE_FALL, /* WAKE_UP */
+        GPIO2_GPIO | WAKEUP_ON_EDGE_BOTH, /* AC_IN */
+        GPIO3_GPIO | WAKEUP_ON_EDGE_FALL, /* RECORD */
+        GPIO4_GPIO | WAKEUP_ON_EDGE_FALL, /* SYNC */
+        GPIO20_GPIO, /* EAR_IN */
+        GPIO22_GPIO, /* On */
+
+        GPIO5_GPIO, /* USB_IN */
+        GPIO32_GPIO, /* Pen IRQ */
+
+        GPIO7_GPIO, /* Jacket Detect */
+        GPIO14_GPIO, /* BAT0_CRG */
+        GPIO12_GPIO, /* BAT1_CRG */
+        GPIO17_GPIO, /* BAT0_LOW */
+        GPIO84_GPIO, /* BAT1_LOW */
+        GPIO38_GPIO, /* BAT_LOCK */
+
+        GPIO11_3_6MHz,
+        GPIO15_GPIO, /* TC6393XB IRQ */
+        GPIO18_RDY,
+        GPIO27_GPIO, /* LCD Sync */
+
+        /* MMC */
+        GPIO6_MMC_CLK,
+        GPIO8_MMC_CS0,
+        GPIO9_GPIO, /* Detect */
+        // GPIO10 nSD_INT
+
+        /* CF */
+        GPIO13_GPIO, /* CD_IRQ */
+        GPIO21_GPIO, /* Main Slot IRQ */
+        GPIO36_GPIO, /* Jacket Slot IRQ */
+        GPIO48_nPOE,
+        GPIO49_nPWE,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO52_nPCE_1,
+        GPIO53_nPCE_2,
+        GPIO54_nPSKTSEL,
+        GPIO55_nPREG,
+        GPIO56_nPWAIT,
+        GPIO57_nIOIS16,
+
+        /* AC97 */
+        GPIO31_AC97_SYNC,
+        GPIO30_AC97_SDATA_OUT,
+        GPIO28_AC97_BITCLK,
+        GPIO29_AC97_SDATA_IN_0,
+        // GPIO79 nAUD_IRQ
+
+        /* FFUART */
+        GPIO34_FFUART_RXD,
+        GPIO35_FFUART_CTS,
+        GPIO37_FFUART_DSR,
+        GPIO39_FFUART_TXD,
+        GPIO40_FFUART_DTR,
+        GPIO41_FFUART_RTS,
+
+        /* BTUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO44_BTUART_CTS,
+        GPIO45_BTUART_RTS,
+
+        /* IrDA */
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+
+        /* Keybd */
+        GPIO58_GPIO,
+        GPIO59_GPIO,
+        GPIO60_GPIO,
+        GPIO61_GPIO,
+        GPIO62_GPIO,
+        GPIO63_GPIO,
+        GPIO64_GPIO,
+        GPIO65_GPIO,
+        GPIO66_GPIO,
+        GPIO67_GPIO,
+        GPIO68_GPIO,
+        GPIO69_GPIO,
+        GPIO70_GPIO,
+        GPIO71_GPIO,
+        GPIO72_GPIO,
+        GPIO73_GPIO,
+        GPIO74_GPIO,
+        GPIO75_GPIO,
+
+        /* SPI */
+        GPIO81_SSP2_CLK_OUT,
+        GPIO82_SSP2_FRM_OUT,
+        GPIO83_SSP2_TXD,
+};
+
 /*
  * SCOOP Device
  */
@@ -60,11 +167,10 @@ static struct resource tosa_scoop_resources[] = {
 
 static struct scoop_config tosa_scoop_setup = {
         .io_dir         = TOSA_SCOOP_IO_DIR,
-        .io_out         = TOSA_SCOOP_IO_OUT,
-
+        .gpio_base      = TOSA_SCOOP_GPIO_BASE,
 };
 
-struct platform_device tosascoop_device = {
+static struct platform_device tosascoop_device = {
         .name           = "sharp-scoop",
         .id             = 0,
         .dev            = {
@@ -88,10 +194,10 @@ static struct resource tosa_scoop_jc_resources[] = {
 
 static struct scoop_config tosa_scoop_jc_setup = {
         .io_dir         = TOSA_SCOOP_JC_IO_DIR,
-        .io_out         = TOSA_SCOOP_JC_IO_OUT,
+        .gpio_base      = TOSA_SCOOP_JC_GPIO_BASE,
 };
 
-struct platform_device tosascoop_jc_device = {
+static struct platform_device tosascoop_jc_device = {
         .name           = "sharp-scoop",
         .id             = 1,
         .dev            = {
@@ -118,50 +224,16 @@ static struct scoop_pcmcia_dev tosa_pcmcia_scoop[] = {
 },
 };
 
-static void tosa_pcmcia_init(void)
-{
-        /* Setup default state of GPIO outputs
-           before we enable them as outputs. */
-        GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
-                GPIO_bit(GPIO49_nPWE) | GPIO_bit(GPIO50_nPIOR) |
-                GPIO_bit(GPIO51_nPIOW) | GPIO_bit(GPIO52_nPCE_1) |
-                GPIO_bit(GPIO53_nPCE_2);
-
-        pxa_gpio_mode(GPIO48_nPOE_MD);
-        pxa_gpio_mode(GPIO49_nPWE_MD);
-        pxa_gpio_mode(GPIO50_nPIOR_MD);
-        pxa_gpio_mode(GPIO51_nPIOW_MD);
-        pxa_gpio_mode(GPIO55_nPREG_MD);
-        pxa_gpio_mode(GPIO56_nPWAIT_MD);
-        pxa_gpio_mode(GPIO57_nIOIS16_MD);
-        pxa_gpio_mode(GPIO52_nPCE_1_MD);
-        pxa_gpio_mode(GPIO53_nPCE_2_MD);
-        pxa_gpio_mode(GPIO54_pSKTSEL_MD);
-}
-
 static struct scoop_pcmcia_config tosa_pcmcia_config = {
         .devs         = &tosa_pcmcia_scoop[0],
         .num_devs     = 2,
-        .pcmcia_init  = tosa_pcmcia_init,
 };
 
 /*
  * USB Device Controller
  */
-static void tosa_udc_command(int cmd)
-{
-        switch(cmd)     {
-                case PXA2XX_UDC_CMD_CONNECT:
-                        set_scoop_gpio(&tosascoop_jc_device.dev,TOSA_SCOOP_JC_USB_PULLUP);
-                        break;
-                case PXA2XX_UDC_CMD_DISCONNECT:
-                        reset_scoop_gpio(&tosascoop_jc_device.dev,TOSA_SCOOP_JC_USB_PULLUP);
-                        break;
-        }
-}
-
 static struct pxa2xx_udc_mach_info udc_info __initdata = {
-        .udc_command            = tosa_udc_command,
+        .gpio_pullup            = TOSA_GPIO_USB_PULLUP,
         .gpio_vbus              = TOSA_GPIO_USB_IN,
         .gpio_vbus_inverted     = 1,
 };
@@ -175,19 +247,44 @@ static int tosa_mci_init(struct device *dev, irq_handler_t tosa_detect_int, void
 {
         int err;
 
-        /* setup GPIO for PXA25x MMC controller */
-        pxa_gpio_mode(GPIO6_MMCCLK_MD);
-        pxa_gpio_mode(GPIO8_MMCCS0_MD);
-        pxa_gpio_mode(TOSA_GPIO_nSD_DETECT | GPIO_IN);
-
         tosa_mci_platform_data.detect_delay = msecs_to_jiffies(250);
 
         err = request_irq(TOSA_IRQ_GPIO_nSD_DETECT, tosa_detect_int,
                           IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                                 "MMC/SD card detect", data);
-        if (err)
+        if (err) {
                 printk(KERN_ERR "tosa_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
+                goto err_irq;
+        }
 
+        err = gpio_request(TOSA_GPIO_SD_WP, "sd_wp");
+        if (err) {
+                printk(KERN_ERR "tosa_mci_init: can't request SD_WP gpio\n");
+                goto err_gpio_wp;
+        }
+        err = gpio_direction_input(TOSA_GPIO_SD_WP);
+        if (err)
+                goto err_gpio_wp_dir;
+
+        err = gpio_request(TOSA_GPIO_PWR_ON, "sd_pwr");
+        if (err) {
+                printk(KERN_ERR "tosa_mci_init: can't request SD_PWR gpio\n");
+                goto err_gpio_pwr;
+        }
+        err = gpio_direction_output(TOSA_GPIO_PWR_ON, 0);
+        if (err)
+                goto err_gpio_pwr_dir;
+
+        return 0;
+
+err_gpio_pwr_dir:
+        gpio_free(TOSA_GPIO_PWR_ON);
+err_gpio_pwr:
+err_gpio_wp_dir:
+        gpio_free(TOSA_GPIO_SD_WP);
+err_gpio_wp:
+        free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data);
+err_irq:
         return err;
 }
 
@@ -196,19 +293,21 @@ static void tosa_mci_setpower(struct device *dev, unsigned int vdd)
         struct pxamci_platform_data* p_d = dev->platform_data;
 
         if (( 1 << vdd) & p_d->ocr_mask) {
-                set_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_PWR_ON);
+                gpio_set_value(TOSA_GPIO_PWR_ON, 1);
         } else {
-                reset_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_PWR_ON);
+                gpio_set_value(TOSA_GPIO_PWR_ON, 0);
         }
 }
 
 static int tosa_mci_get_ro(struct device *dev)
 {
-        return (read_scoop_reg(&tosascoop_device.dev, SCOOP_GPWR)&TOSA_SCOOP_SD_WP);
+        return gpio_get_value(TOSA_GPIO_SD_WP);
 }
 
 static void tosa_mci_exit(struct device *dev, void *data)
 {
+        gpio_free(TOSA_GPIO_PWR_ON);
+        gpio_free(TOSA_GPIO_SD_WP);
         free_irq(TOSA_IRQ_GPIO_nSD_DETECT, data);
 }
 
@@ -223,21 +322,36 @@ static struct pxamci_platform_data tosa_mci_platform_data = {
 /*
  * Irda
  */
-static void tosa_irda_transceiver_mode(struct device *dev, int mode)
+static int tosa_irda_startup(struct device *dev)
 {
-        if (mode & IR_OFF) {
-                reset_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_IR_POWERDWN);
-                pxa_gpio_mode(GPIO47_STTXD|GPIO_DFLT_LOW);
-                pxa_gpio_mode(GPIO47_STTXD|GPIO_OUT);
-        } else {
-                pxa_gpio_mode(GPIO47_STTXD_MD);
-                set_scoop_gpio(&tosascoop_device.dev,TOSA_SCOOP_IR_POWERDWN);
+        int ret;
+
+        ret = gpio_request(TOSA_GPIO_IR_POWERDWN, "IrDA powerdown");
+        if (ret)
+                return ret;
+
+        ret = gpio_direction_output(TOSA_GPIO_IR_POWERDWN, 0);
+        if (ret)
+                gpio_free(TOSA_GPIO_IR_POWERDWN);
+
+        return ret;
         }
+
+static void tosa_irda_shutdown(struct device *dev)
+{
+        gpio_free(TOSA_GPIO_IR_POWERDWN);
+}
+
+static void tosa_irda_transceiver_mode(struct device *dev, int mode)
+{
+        gpio_set_value(TOSA_GPIO_IR_POWERDWN, !(mode & IR_OFF));
 }
 
 static struct pxaficp_platform_data tosa_ficp_platform_data = {
         .transceiver_cap  = IR_SIRMODE | IR_OFF,
         .transceiver_mode = tosa_irda_transceiver_mode,
+        .startup = tosa_irda_startup,
+        .shutdown = tosa_irda_shutdown,
 };
 
 /*
@@ -249,12 +363,28 @@ static struct platform_device tosakbd_device = {
 };
 
 static struct gpio_keys_button tosa_gpio_keys[] = {
+        /*
+         * Two following keys are directly tied to "ON" button of tosa. Why?
+         * The first one can be used as a wakeup source, the second can't;
+         * also the first one is OR of ac_powered and on_button.
+         */
+        {
+                .type   = EV_PWR,
+                .code   = KEY_RESERVED,
+                .gpio   = TOSA_GPIO_POWERON,
+                .desc   = "Poweron",
+                .wakeup = 1,
+                .active_low = 1,
+        },
         {
                 .type   = EV_PWR,
                 .code   = KEY_SUSPEND,
                 .gpio   = TOSA_GPIO_ON_KEY,
                 .desc   = "On key",
-                .wakeup = 1,
+                /*
+                 * can't be used as wakeup
+                 * .wakeup      = 1,
+                 */
                 .active_low = 1,
         },
         {
@@ -291,9 +421,40 @@ static struct platform_device tosa_gpio_keys_device = {
 /*
  * Tosa LEDs
  */
+static struct gpio_led tosa_gpio_leds[] = {
+        {
+                .name                   = "tosa:amber:charge",
+                .default_trigger        = "main-battery-charging",
+                .gpio                   = TOSA_GPIO_CHRG_ERR_LED,
+        },
+        {
+                .name                   = "tosa:green:mail",
+                .default_trigger        = "nand-disk",
+                .gpio                   = TOSA_GPIO_NOTE_LED,
+        },
+        {
+                .name                   = "tosa:dual:wlan",
+                .default_trigger        = "none",
+                .gpio                   = TOSA_GPIO_WLAN_LED,
+        },
+        {
+                .name                   = "tosa:blue:bluetooth",
+                .default_trigger        = "none",
+                .gpio                   = TOSA_GPIO_BT_LED,
+        },
+};
+
+static struct gpio_led_platform_data tosa_gpio_leds_platform_data = {
+        .leds           = tosa_gpio_leds,
+        .num_leds       = ARRAY_SIZE(tosa_gpio_leds),
+};
+
 static struct platform_device tosaled_device = {
-    .name   = "tosa-led",
-    .id     = -1,
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &tosa_gpio_leds_platform_data,
+        },
 };
 
 static struct platform_device *devices[] __initdata = {
@@ -326,20 +487,13 @@ static void tosa_restart(char mode)
 
 static void __init tosa_init(void)
 {
+        pxa2xx_mfp_config(ARRAY_AND_SIZE(tosa_pin_config));
+        gpio_set_wake(MFP_PIN_GPIO1, 1);
+        /* We can't pass to gpio-keys since it will drop the Reset altfunc */
+
         pm_power_off = tosa_poweroff;
         arm_pm_restart = tosa_restart;
 
-        pxa_gpio_mode(TOSA_GPIO_ON_RESET | GPIO_IN);
-        pxa_gpio_mode(TOSA_GPIO_TC6393_INT | GPIO_IN);
-        pxa_gpio_mode(TOSA_GPIO_USB_IN | GPIO_IN);
-
-        /* setup sleep mode values */
-        PWER  = 0x00000002;
-        PFER  = 0x00000000;
-        PRER  = 0x00000002;
-        PGSR0 = 0x00000000;
-        PGSR1 = 0x00FF0002;
-        PGSR2 = 0x00014000;
         PCFR |= PCFR_OPDE;
 
         /* enable batt_fault */
@@ -348,6 +502,7 @@ static void __init tosa_init(void)
         pxa_set_mci_info(&tosa_mci_platform_data);
         pxa_set_udc_info(&udc_info);
         pxa_set_ficp_info(&tosa_ficp_platform_data);
+        pxa_set_i2c_info(NULL);
         platform_scoop_config = &tosa_pcmcia_config;
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index f207fcd30cd7..931885d86b91 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -41,6 +41,7 @@
 #include <asm/mach/flash.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/trizeps4.h>
 #include <asm/arch/audio.h>
 #include <asm/arch/pxafb.h>
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index afd2cbfca0d9..dbb546216be1 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -26,6 +26,7 @@
 #include <asm/arch/pxafb.h>
 #include <asm/arch/zylonite.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/pxa27x_keypad.h>
 
 #include "generic.h"
 
@@ -35,6 +36,8 @@ struct platform_mmc_slot zylonite_mmc_slot[MAX_SLOTS];
 int gpio_backlight;
 int gpio_eth_irq;
 
+int wm9713_irq;
+
 int lcd_id;
 int lcd_orientation;
 
@@ -249,6 +252,71 @@ static void __init zylonite_init_mmc(void)
 static inline void zylonite_init_mmc(void) {}
 #endif
 
+#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULES)
+static unsigned int zylonite_matrix_key_map[] = {
+        /* KEY(row, col, key_code) */
+        KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_C), KEY(0, 5, KEY_D),
+        KEY(1, 0, KEY_E), KEY(1, 1, KEY_F), KEY(1, 2, KEY_G), KEY(1, 5, KEY_H),
+        KEY(2, 0, KEY_I), KEY(2, 1, KEY_J), KEY(2, 2, KEY_K), KEY(2, 5, KEY_L),
+        KEY(3, 0, KEY_M), KEY(3, 1, KEY_N), KEY(3, 2, KEY_O), KEY(3, 5, KEY_P),
+        KEY(5, 0, KEY_Q), KEY(5, 1, KEY_R), KEY(5, 2, KEY_S), KEY(5, 5, KEY_T),
+        KEY(6, 0, KEY_U), KEY(6, 1, KEY_V), KEY(6, 2, KEY_W), KEY(6, 5, KEY_X),
+        KEY(7, 1, KEY_Y), KEY(7, 2, KEY_Z),
+
+        KEY(4, 4, KEY_0), KEY(1, 3, KEY_1), KEY(4, 1, KEY_2), KEY(1, 4, KEY_3),
+        KEY(2, 3, KEY_4), KEY(4, 2, KEY_5), KEY(2, 4, KEY_6), KEY(3, 3, KEY_7),
+        KEY(4, 3, KEY_8), KEY(3, 4, KEY_9),
+
+        KEY(4, 5, KEY_SPACE),
+        KEY(5, 3, KEY_KPASTERISK),      /* * */
+        KEY(5, 4, KEY_KPDOT),           /* #" */
+
+        KEY(0, 7, KEY_UP),
+        KEY(1, 7, KEY_DOWN),
+        KEY(2, 7, KEY_LEFT),
+        KEY(3, 7, KEY_RIGHT),
+        KEY(2, 6, KEY_HOME),
+        KEY(3, 6, KEY_END),
+        KEY(6, 4, KEY_DELETE),
+        KEY(6, 6, KEY_BACK),
+        KEY(6, 3, KEY_CAPSLOCK),        /* KEY_LEFTSHIFT), */
+
+        KEY(4, 6, KEY_ENTER),           /* scroll push */
+        KEY(5, 7, KEY_ENTER),           /* keypad action */
+
+        KEY(0, 4, KEY_EMAIL),
+        KEY(5, 6, KEY_SEND),
+        KEY(4, 0, KEY_CALENDAR),
+        KEY(7, 6, KEY_RECORD),
+        KEY(6, 7, KEY_VOLUMEUP),
+        KEY(7, 7, KEY_VOLUMEDOWN),
+
+        KEY(0, 6, KEY_F22),     /* soft1 */
+        KEY(1, 6, KEY_F23),     /* soft2 */
+        KEY(0, 3, KEY_AUX),     /* contact */
+};
+
+static struct pxa27x_keypad_platform_data zylonite_keypad_info = {
+        .matrix_key_rows        = 8,
+        .matrix_key_cols        = 8,
+        .matrix_key_map         = zylonite_matrix_key_map,
+        .matrix_key_map_size    = ARRAY_SIZE(zylonite_matrix_key_map),
+
+        .enable_rotary0         = 1,
+        .rotary0_up_key         = KEY_UP,
+        .rotary0_down_key       = KEY_DOWN,
+
+        .debounce_interval      = 30,
+};
+
+static void __init zylonite_init_keypad(void)
+{
+        pxa_set_keypad_info(&zylonite_keypad_info);
+}
+#else
+static inline void zylonite_init_keypad(void) {}
+#endif
+
 static void __init zylonite_init(void)
 {
         /* board-processor specific initialization */
@@ -265,6 +333,7 @@ static void __init zylonite_init(void)
 
         zylonite_init_lcd();
         zylonite_init_mmc();
+        zylonite_init_keypad();
 }
 
 MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 6ac04c09b0e9..324fb9daae28 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -21,7 +21,7 @@
 #include <asm/arch/mfp-pxa300.h>
 #include <asm/arch/zylonite.h>
 
-#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+#include "generic.h"
 
 /* PXA300/PXA310 common configurations */
 static mfp_cfg_t common_mfp_cfg[] __initdata = {
@@ -69,6 +69,9 @@ static mfp_cfg_t common_mfp_cfg[] __initdata = {
         GPIO27_AC97_SDATA_OUT,
         GPIO28_AC97_SYNC,
 
+        /* WM9713 IRQ */
+        GPIO26_GPIO,
+
         /* Keypad */
         GPIO107_KP_DKIN_0 | MFP_LPM_EDGE_BOTH,
         GPIO108_KP_DKIN_1 | MFP_LPM_EDGE_BOTH,
@@ -203,6 +206,9 @@ void __init zylonite_pxa300_init(void)
                 /* MMC card detect & write protect for controller 0 */
                 zylonite_mmc_slot[0].gpio_cd  = EXT_GPIO(0);
                 zylonite_mmc_slot[0].gpio_wp  = EXT_GPIO(2);
+
+                /* WM9713 IRQ */
+                wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO26);
         }
 
         if (cpu_is_pxa300()) {
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
index dfa79992b8ab..193d07903b06 100644
--- a/arch/arm/mach-pxa/zylonite_pxa320.c
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -21,7 +21,7 @@
 #include <asm/arch/mfp-pxa320.h>
 #include <asm/arch/zylonite.h>
 
-#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+#include "generic.h"
 
 static mfp_cfg_t mfp_cfg[] __initdata = {
         /* LCD */
@@ -68,6 +68,9 @@ static mfp_cfg_t mfp_cfg[] __initdata = {
         GPIO39_AC97_BITCLK,
         GPIO40_AC97_nACRESET,
 
+        /* WM9713 IRQ */
+        GPIO15_GPIO,
+
         /* I2C */
         GPIO32_I2C_SCL,
         GPIO33_I2C_SDA,
@@ -190,5 +193,8 @@ void __init zylonite_pxa320_init(void)
                 /* MMC card detect & write protect for controller 0 */
                 zylonite_mmc_slot[0].gpio_cd  = mfp_to_gpio(MFP_PIN_GPIO1);
                 zylonite_mmc_slot[0].gpio_wp  = mfp_to_gpio(MFP_PIN_GPIO5);
+
+                /* WM9713 IRQ */
+                wm9713_irq = mfp_to_gpio(MFP_PIN_GPIO15);
         }
 }
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 39b3bb7f1020..5ccde7cf39e8 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -10,7 +10,6 @@ config MACH_REALVIEW_EB
 config REALVIEW_EB_ARM11MP
         bool "Support ARM11MPCore tile"
         depends on MACH_REALVIEW_EB
-        select CACHE_L2X0
         help
           Enable support for the ARM11MPCore tile on the Realview platform.
 
@@ -24,4 +23,18 @@ config REALVIEW_EB_ARM11MP_REVB
           kernel built with this option enabled is not compatible with
           other revisions of the ARM11MPCore tile.
 
+config MACH_REALVIEW_PB11MP
+        bool "Support RealView/PB11MPCore platform"
+        select ARM_GIC
+        help
+          Include support for the ARM(R) RealView MPCore Platform Baseboard.
+          PB11MPCore is a platform with an on-board ARM11MPCore and has
+          support for PCI-E and Compact Flash.
+
+config MACH_REALVIEW_PB1176
+        bool "Support RealView/PB1176 platform"
+        select ARM_GIC
+        help
+          Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
+
 endmenu
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index ca1e390c3c28..d2ae077431dd 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -4,5 +4,7 @@
 
 obj-y                                   := core.o clock.o
 obj-$(CONFIG_MACH_REALVIEW_EB)          += realview_eb.o
+obj-$(CONFIG_MACH_REALVIEW_PB11MP)      += realview_pb11mp.o
+obj-$(CONFIG_MACH_REALVIEW_PB1176)      += realview_pb1176.o
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o localtimer.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 98aefc9f4df3..131990d196f5 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -109,22 +109,21 @@ static struct flash_platform_data realview_flash_data = {
         .set_vpp                = realview_flash_set_vpp,
 };
 
-static struct resource realview_flash_resource = {
-        .start                  = REALVIEW_FLASH_BASE,
-        .end                    = REALVIEW_FLASH_BASE + REALVIEW_FLASH_SIZE,
-        .flags                  = IORESOURCE_MEM,
-};
-
 struct platform_device realview_flash_device = {
         .name                   = "armflash",
         .id                     = 0,
         .dev                    = {
                 .platform_data  = &realview_flash_data,
         },
-        .num_resources          = 1,
-        .resource               = &realview_flash_resource,
 };
 
+int realview_flash_register(struct resource *res, u32 num)
+{
+        realview_flash_device.resource = res;
+        realview_flash_device.num_resources = num;
+        return platform_device_register(&realview_flash_device);
+}
+
 static struct resource realview_i2c_resource = {
         .start          = REALVIEW_I2C_BASE,
         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
@@ -445,10 +444,10 @@ void realview_leds_event(led_event_t ledevt)
 /*
  * Where is the timer (VA)?
  */
-#define TIMER0_VA_BASE           __io_address(REALVIEW_TIMER0_1_BASE)
-#define TIMER1_VA_BASE          (__io_address(REALVIEW_TIMER0_1_BASE) + 0x20)
-#define TIMER2_VA_BASE           __io_address(REALVIEW_TIMER2_3_BASE)
-#define TIMER3_VA_BASE          (__io_address(REALVIEW_TIMER2_3_BASE) + 0x20)
+void __iomem *timer0_va_base;
+void __iomem *timer1_va_base;
+void __iomem *timer2_va_base;
+void __iomem *timer3_va_base;
 
 /*
  * How long is the timer interval?
@@ -475,7 +474,7 @@ static void timer_set_mode(enum clock_event_mode mode,
 
         switch(mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
+                writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
 
                 ctrl = TIMER_CTRL_PERIODIC;
                 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
@@ -491,16 +490,16 @@ static void timer_set_mode(enum clock_event_mode mode,
                 ctrl = 0;
         }
 
-        writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
+        writel(ctrl, timer0_va_base + TIMER_CTRL);
 }
 
 static int timer_set_next_event(unsigned long evt,
                                 struct clock_event_device *unused)
 {
-        unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
+        unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
 
-        writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
-        writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
+        writel(evt, timer0_va_base + TIMER_LOAD);
+        writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
 
         return 0;
 }
@@ -536,7 +535,7 @@ static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
         struct clock_event_device *evt = &timer0_clockevent;
 
         /* clear the interrupt */
-        writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
+        writel(1, timer0_va_base + TIMER_INTCLR);
 
         evt->event_handler(evt);
 
@@ -551,7 +550,7 @@ static struct irqaction realview_timer_irq = {
 
 static cycle_t realview_get_cycles(void)
 {
-        return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
+        return ~readl(timer3_va_base + TIMER_VALUE);
 }
 
 static struct clocksource clocksource_realview = {
@@ -566,11 +565,11 @@ static struct clocksource clocksource_realview = {
 static void __init realview_clocksource_init(void)
 {
         /* setup timer 0 as free-running clocksource */
-        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
-        writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
-        writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
+        writel(0, timer3_va_base + TIMER_CTRL);
+        writel(0xffffffff, timer3_va_base + TIMER_LOAD);
+        writel(0xffffffff, timer3_va_base + TIMER_VALUE);
         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
-                TIMER3_VA_BASE + TIMER_CTRL);
+                timer3_va_base + TIMER_CTRL);
 
         clocksource_realview.mult =
                 clocksource_khz2mult(1000, clocksource_realview.shift);
@@ -607,10 +606,10 @@ void __init realview_timer_init(unsigned int timer_irq)
         /*
          * Initialise to a known state (all timers off)
          */
-        writel(0, TIMER0_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
-        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
+        writel(0, timer0_va_base + TIMER_CTRL);
+        writel(0, timer1_va_base + TIMER_CTRL);
+        writel(0, timer2_va_base + TIMER_CTRL);
+        writel(0, timer3_va_base + TIMER_CTRL);
 
         /* 
          * Make irqs happen for the system timer
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 492a14c0d604..33dbbb41a663 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -55,8 +55,13 @@ extern void __iomem *gic_cpu_base_addr;
 extern void __iomem *twd_base_addr;
 extern unsigned int twd_size;
 #endif
+extern void __iomem *timer0_va_base;
+extern void __iomem *timer1_va_base;
+extern void __iomem *timer2_va_base;
+extern void __iomem *timer3_va_base;
 
 extern void realview_leds_event(led_event_t ledevt);
 extern void realview_timer_init(unsigned int timer_irq);
+extern int realview_flash_register(struct resource *res, u32 num);
 
 #endif
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index de2b7159557d..3e57428affee 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -15,11 +15,14 @@
 #include <linux/smp.h>
 
 #include <asm/cacheflush.h>
-#include <asm/hardware/arm_scu.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 
+#include <asm/arch/board-eb.h>
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/scu.h>
+
 extern void realview_secondary_startup(void);
 
 /*
@@ -31,9 +34,15 @@ volatile int __cpuinitdata pen_release = -1;
 static unsigned int __init get_core_count(void)
 {
         unsigned int ncores;
+        void __iomem *scu_base = 0;
+
+        if (machine_is_realview_eb() && core_tile_eb11mp())
+                scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
+        else if (machine_is_realview_pb11mp())
+                scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
 
-        if (machine_is_realview_eb() && core_tile_eb11mp()) {
-                ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG);
+        if (scu_base) {
+                ncores = __raw_readl(scu_base + SCU_CONFIG);
                 ncores = (ncores & 0x03) + 1;
         } else
                 ncores = 1;
@@ -41,6 +50,26 @@ static unsigned int __init get_core_count(void)
         return ncores;
 }
 
+/*
+ * Setup the SCU
+ */
+static void scu_enable(void)
+{
+        u32 scu_ctrl;
+        void __iomem *scu_base;
+
+        if (machine_is_realview_eb() && core_tile_eb11mp())
+                scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
+        else if (machine_is_realview_pb11mp())
+                scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
+        else
+                BUG();
+
+        scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
+        scu_ctrl |= 1;
+        __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
+}
+
 static DEFINE_SPINLOCK(boot_lock);
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
@@ -57,7 +86,10 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
          */
-        gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
+        if (machine_is_realview_eb() && core_tile_eb11mp())
+                gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
+        else if (machine_is_realview_pb11mp())
+                gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
 
         /*
          * let the primary processor know we're out of the
@@ -198,7 +230,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
          * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
          * realview_timer_init
          */
-        if (machine_is_realview_eb() && core_tile_eb11mp())
+        if ((machine_is_realview_eb() && core_tile_eb11mp()) ||
+            machine_is_realview_pb11mp())
                 local_timer_setup(cpu);
 #endif
 
@@ -210,11 +243,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                 cpu_set(i, cpu_present_map);
 
         /*
-         * Do we need any more CPUs? If so, then let them know where
-         * to start. Note that, on modern versions of MILO, the "poke"
-         * doesn't actually do anything until each individual core is
-         * sent a soft interrupt to get it out of WFI
+         * Initialise the SCU if there are more than one CPU and let
+         * them know where to start. Note that, on modern versions of
+         * MILO, the "poke" doesn't actually do anything until each
+         * individual core is sent a soft interrupt to get it out of
+         * WFI
          */
-        if (max_cpus > 1)
+        if (max_cpus > 1) {
+                scu_enable();
                 poke_milo();
+        }
 }
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 60d9eb810246..5782d83fd886 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -51,13 +51,13 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(REALVIEW_GIC_CPU_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_GIC_CPU_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_EB_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_EB_GIC_CPU_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(REALVIEW_GIC_DIST_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_GIC_DIST_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_EB_GIC_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_EB_GIC_DIST_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
@@ -66,20 +66,20 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(REALVIEW_TIMER0_1_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_TIMER0_1_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_EB_TIMER0_1_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_EB_TIMER0_1_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(REALVIEW_TIMER2_3_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_TIMER2_3_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_EB_TIMER2_3_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_EB_TIMER2_3_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         },
 #ifdef CONFIG_DEBUG_LL
         {
-                .virtual        = IO_ADDRESS(REALVIEW_UART0_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_UART0_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_EB_UART0_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_EB_UART0_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }
@@ -136,12 +136,12 @@ static void __init realview_eb_map_io(void)
 /*
  * These devices are connected directly to the multi-layer AHB switch
  */
-#define SMC_IRQ         { NO_IRQ, NO_IRQ }
-#define SMC_DMA         { 0, 0 }
+#define EB_SMC_IRQ      { NO_IRQ, NO_IRQ }
+#define EB_SMC_DMA      { 0, 0 }
 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 #define MPMC_DMA        { 0, 0 }
-#define CLCD_IRQ        { IRQ_EB_CLCD, NO_IRQ }
-#define CLCD_DMA        { 0, 0 }
+#define EB_CLCD_IRQ     { IRQ_EB_CLCD, NO_IRQ }
+#define EB_CLCD_DMA     { 0, 0 }
 #define DMAC_IRQ        { IRQ_EB_DMA, NO_IRQ }
 #define DMAC_DMA        { 0, 0 }
 
@@ -150,53 +150,53 @@ static void __init realview_eb_map_io(void)
  */
 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 #define SCTL_DMA        { 0, 0 }
-#define WATCHDOG_IRQ    { IRQ_EB_WDOG, NO_IRQ }
-#define WATCHDOG_DMA    { 0, 0 }
-#define GPIO0_IRQ       { IRQ_EB_GPIO0, NO_IRQ }
-#define GPIO0_DMA       { 0, 0 }
+#define EB_WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
+#define EB_WATCHDOG_DMA { 0, 0 }
+#define EB_GPIO0_IRQ    { IRQ_EB_GPIO0, NO_IRQ }
+#define EB_GPIO0_DMA    { 0, 0 }
 #define GPIO1_IRQ       { IRQ_EB_GPIO1, NO_IRQ }
 #define GPIO1_DMA       { 0, 0 }
-#define RTC_IRQ         { IRQ_EB_RTC, NO_IRQ }
-#define RTC_DMA         { 0, 0 }
+#define EB_RTC_IRQ      { IRQ_EB_RTC, NO_IRQ }
+#define EB_RTC_DMA      { 0, 0 }
 
 /*
  * These devices are connected via the DMA APB bridge
  */
 #define SCI_IRQ         { IRQ_EB_SCI, NO_IRQ }
 #define SCI_DMA         { 7, 6 }
-#define UART0_IRQ       { IRQ_EB_UART0, NO_IRQ }
-#define UART0_DMA       { 15, 14 }
-#define UART1_IRQ       { IRQ_EB_UART1, NO_IRQ }
-#define UART1_DMA       { 13, 12 }
-#define UART2_IRQ       { IRQ_EB_UART2, NO_IRQ }
-#define UART2_DMA       { 11, 10 }
-#define UART3_IRQ       { IRQ_EB_UART3, NO_IRQ }
-#define UART3_DMA       { 0x86, 0x87 }
-#define SSP_IRQ         { IRQ_EB_SSP, NO_IRQ }
-#define SSP_DMA         { 9, 8 }
+#define EB_UART0_IRQ    { IRQ_EB_UART0, NO_IRQ }
+#define EB_UART0_DMA    { 15, 14 }
+#define EB_UART1_IRQ    { IRQ_EB_UART1, NO_IRQ }
+#define EB_UART1_DMA    { 13, 12 }
+#define EB_UART2_IRQ    { IRQ_EB_UART2, NO_IRQ }
+#define EB_UART2_DMA    { 11, 10 }
+#define EB_UART3_IRQ    { IRQ_EB_UART3, NO_IRQ }
+#define EB_UART3_DMA    { 0x86, 0x87 }
+#define EB_SSP_IRQ      { IRQ_EB_SSP, NO_IRQ }
+#define EB_SSP_DMA      { 9, 8 }
 
 /* FPGA Primecells */
 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &realview_mmc0_plat_data);
 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
-AMBA_DEVICE(uart3, "fpga:09", UART3,    NULL);
+AMBA_DEVICE(uart3, "fpga:09", EB_UART3, NULL);
 
 /* DevChip Primecells */
-AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
-AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
+AMBA_DEVICE(smc,   "dev:00",  EB_SMC,   NULL);
+AMBA_DEVICE(clcd,  "dev:20",  EB_CLCD,  &clcd_plat_data);
 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
-AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
-AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
+AMBA_DEVICE(wdog,  "dev:e1",  EB_WATCHDOG, NULL);
+AMBA_DEVICE(gpio0, "dev:e4",  EB_GPIO0, NULL);
 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
 AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    NULL);
-AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
+AMBA_DEVICE(rtc,   "dev:e8",  EB_RTC,   NULL);
 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
-AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
-AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
-AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
-AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
+AMBA_DEVICE(uart0, "dev:f1",  EB_UART0, NULL);
+AMBA_DEVICE(uart1, "dev:f2",  EB_UART1, NULL);
+AMBA_DEVICE(uart2, "dev:f3",  EB_UART2, NULL);
+AMBA_DEVICE(ssp0,  "dev:f4",  EB_SSP,   NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &dmac_device,
@@ -223,11 +223,16 @@ static struct amba_device *amba_devs[] __initdata = {
 /*
  * RealView EB platform devices
  */
+static struct resource realview_eb_flash_resource = {
+        .start                  = REALVIEW_EB_FLASH_BASE,
+        .end                    = REALVIEW_EB_FLASH_BASE + REALVIEW_EB_FLASH_SIZE - 1,
+        .flags                  = IORESOURCE_MEM,
+};
 
-static struct resource realview_eb_smc91x_resources[] = {
+static struct resource realview_eb_eth_resources[] = {
         [0] = {
-                .start          = REALVIEW_ETH_BASE,
-                .end            = REALVIEW_ETH_BASE + SZ_64K - 1,
+                .start          = REALVIEW_EB_ETH_BASE,
+                .end            = REALVIEW_EB_ETH_BASE + SZ_64K - 1,
                 .flags          = IORESOURCE_MEM,
         },
         [1] = {
@@ -237,13 +242,36 @@ static struct resource realview_eb_smc91x_resources[] = {
         },
 };
 
-static struct platform_device realview_eb_smc91x_device = {
-        .name           = "smc91x",
+static struct platform_device realview_eb_eth_device = {
         .id             = 0,
-        .num_resources  = ARRAY_SIZE(realview_eb_smc91x_resources),
-        .resource       = realview_eb_smc91x_resources,
+        .num_resources  = ARRAY_SIZE(realview_eb_eth_resources),
+        .resource       = realview_eb_eth_resources,
 };
 
+/*
+ * Detect and register the correct Ethernet device. RealView/EB rev D
+ * platforms use the newer SMSC LAN9118 Ethernet chip
+ */
+static int eth_device_register(void)
+{
+        void __iomem *eth_addr = ioremap(REALVIEW_EB_ETH_BASE, SZ_4K);
+        u32 idrev;
+
+        if (!eth_addr)
+                return -ENOMEM;
+
+        idrev = readl(eth_addr + 0x50);
+        if ((idrev & 0xFFFF0000) == 0x01180000)
+                /* SMSC LAN9118 chip present */
+                realview_eb_eth_device.name = "smc911x";
+        else
+                /* SMSC 91C111 chip present */
+                realview_eb_eth_device.name = "smc91x";
+
+        iounmap(eth_addr);
+        return platform_device_register(&realview_eb_eth_device);
+}
+
 static void __init gic_init_irq(void)
 {
         if (core_tile_eb11mp()) {
@@ -263,14 +291,14 @@ static void __init gic_init_irq(void)
 
 #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
                 /* board GIC, secondary */
-                gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64);
-                gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE));
+                gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
+                gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
                 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
 #endif
         } else {
                 /* board GIC, primary */
-                gic_cpu_base_addr = __io_address(REALVIEW_GIC_CPU_BASE);
-                gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
+                gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
+                gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
                 gic_cpu_init(0, gic_cpu_base_addr);
         }
 }
@@ -301,14 +329,19 @@ static void realview_eb11mp_fixup(void)
         kmi1_device.irq[0]      = IRQ_EB11MP_KMI1;
 
         /* platform devices */
-        realview_eb_smc91x_resources[1].start   = IRQ_EB11MP_ETH;
-        realview_eb_smc91x_resources[1].end     = IRQ_EB11MP_ETH;
+        realview_eb_eth_resources[1].start      = IRQ_EB11MP_ETH;
+        realview_eb_eth_resources[1].end        = IRQ_EB11MP_ETH;
 }
 
 static void __init realview_eb_timer_init(void)
 {
         unsigned int timer_irq;
 
+        timer0_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE);
+        timer1_va_base = __io_address(REALVIEW_EB_TIMER0_1_BASE) + 0x20;
+        timer2_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE);
+        timer3_va_base = __io_address(REALVIEW_EB_TIMER2_3_BASE) + 0x20;
+
         if (core_tile_eb11mp()) {
 #ifdef CONFIG_LOCAL_TIMERS
                 twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE);
@@ -332,16 +365,18 @@ static void __init realview_eb_init(void)
         if (core_tile_eb11mp()) {
                 realview_eb11mp_fixup();
 
+#ifdef CONFIG_CACHE_L2X0
                 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
                  * Bits:  .... ...0 0111 1001 0000 .... .... .... */
                 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
+#endif
         }
 
         clk_register(&realview_clcd_clk);
 
-        platform_device_register(&realview_flash_device);
-        platform_device_register(&realview_eb_smc91x_device);
+        realview_flash_register(&realview_eb_flash_resource, 1);
         platform_device_register(&realview_i2c_device);
+        eth_device_register();
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
@@ -355,8 +390,8 @@ static void __init realview_eb_init(void)
 
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .phys_io        = REALVIEW_UART0_BASE,
-        .io_pg_offst    = (IO_ADDRESS(REALVIEW_UART0_BASE) >> 18) & 0xfffc,
+        .phys_io        = REALVIEW_EB_UART0_BASE,
+        .io_pg_offst    = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
         .boot_params    = 0x00000100,
         .map_io         = realview_eb_map_io,
         .init_irq       = gic_init_irq,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
new file mode 100644
index 000000000000..cf7f576a5860
--- /dev/null
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -0,0 +1,292 @@
+/*
+ *  linux/arch/arm/mach-realview/realview_pb1176.c
+ *
+ *  Copyright (C) 2008 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/icst307.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+#include <asm/mach/mmc.h>
+#include <asm/mach/time.h>
+
+#include <asm/arch/board-pb1176.h>
+#include <asm/arch/irqs.h>
+
+#include "core.h"
+#include "clock.h"
+
+static struct map_desc realview_pb1176_io_desc[] __initdata = {
+        {
+                .virtual        = IO_ADDRESS(REALVIEW_SYS_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_SYS_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB1176_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB1176_GIC_CPU_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB1176_GIC_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB1176_GIC_DIST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_DC1176_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_DC1176_GIC_CPU_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_DC1176_GIC_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_DC1176_GIC_DIST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_SCTL_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_SCTL_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB1176_TIMER0_1_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB1176_TIMER0_1_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB1176_TIMER2_3_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB1176_TIMER2_3_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB1176_L220_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB1176_L220_BASE),
+                .length         = SZ_8K,
+                .type           = MT_DEVICE,
+        },
+#ifdef CONFIG_DEBUG_LL
+        {
+                .virtual        = IO_ADDRESS(REALVIEW_PB1176_UART0_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB1176_UART0_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+#endif
+};
+
+static void __init realview_pb1176_map_io(void)
+{
+        iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc));
+}
+
+/*
+ * RealView PB1176 AMBA devices
+ */
+#define GPIO2_IRQ       { IRQ_PB1176_GPIO2, NO_IRQ }
+#define GPIO2_DMA       { 0, 0 }
+#define GPIO3_IRQ       { IRQ_PB1176_GPIO3, NO_IRQ }
+#define GPIO3_DMA       { 0, 0 }
+#define AACI_IRQ        { IRQ_PB1176_AACI, NO_IRQ }
+#define AACI_DMA        { 0x80, 0x81 }
+#define MMCI0_IRQ       { IRQ_PB1176_MMCI0A, IRQ_PB1176_MMCI0B }
+#define MMCI0_DMA       { 0x84, 0 }
+#define KMI0_IRQ        { IRQ_PB1176_KMI0, NO_IRQ }
+#define KMI0_DMA        { 0, 0 }
+#define KMI1_IRQ        { IRQ_PB1176_KMI1, NO_IRQ }
+#define KMI1_DMA        { 0, 0 }
+#define PB1176_SMC_IRQ  { NO_IRQ, NO_IRQ }
+#define PB1176_SMC_DMA  { 0, 0 }
+#define MPMC_IRQ        { NO_IRQ, NO_IRQ }
+#define MPMC_DMA        { 0, 0 }
+#define PB1176_CLCD_IRQ { IRQ_DC1176_CLCD, NO_IRQ }
+#define PB1176_CLCD_DMA { 0, 0 }
+#define DMAC_IRQ        { IRQ_PB1176_DMAC, NO_IRQ }
+#define DMAC_DMA        { 0, 0 }
+#define SCTL_IRQ        { NO_IRQ, NO_IRQ }
+#define SCTL_DMA        { 0, 0 }
+#define PB1176_WATCHDOG_IRQ     { IRQ_DC1176_WATCHDOG, NO_IRQ }
+#define PB1176_WATCHDOG_DMA     { 0, 0 }
+#define PB1176_GPIO0_IRQ        { IRQ_PB1176_GPIO0, NO_IRQ }
+#define PB1176_GPIO0_DMA        { 0, 0 }
+#define GPIO1_IRQ       { IRQ_PB1176_GPIO1, NO_IRQ }
+#define GPIO1_DMA       { 0, 0 }
+#define PB1176_RTC_IRQ  { IRQ_DC1176_RTC, NO_IRQ }
+#define PB1176_RTC_DMA  { 0, 0 }
+#define SCI_IRQ         { IRQ_PB1176_SCI, NO_IRQ }
+#define SCI_DMA         { 7, 6 }
+#define PB1176_UART0_IRQ        { IRQ_DC1176_UART0, NO_IRQ }
+#define PB1176_UART0_DMA        { 15, 14 }
+#define PB1176_UART1_IRQ        { IRQ_DC1176_UART1, NO_IRQ }
+#define PB1176_UART1_DMA        { 13, 12 }
+#define PB1176_UART2_IRQ        { IRQ_DC1176_UART2, NO_IRQ }
+#define PB1176_UART2_DMA        { 11, 10 }
+#define PB1176_UART3_IRQ        { IRQ_DC1176_UART3, NO_IRQ }
+#define PB1176_UART3_DMA        { 0x86, 0x87 }
+#define PB1176_SSP_IRQ          { IRQ_PB1176_SSP, NO_IRQ }
+#define PB1176_SSP_DMA          { 9, 8 }
+
+/* FPGA Primecells */
+AMBA_DEVICE(aaci,       "fpga:04",      AACI,           NULL);
+AMBA_DEVICE(mmc0,       "fpga:05",      MMCI0,          &realview_mmc0_plat_data);
+AMBA_DEVICE(kmi0,       "fpga:06",      KMI0,           NULL);
+AMBA_DEVICE(kmi1,       "fpga:07",      KMI1,           NULL);
+AMBA_DEVICE(uart3,      "fpga:09",      PB1176_UART3,   NULL);
+
+/* DevChip Primecells */
+AMBA_DEVICE(smc,        "dev:00",       PB1176_SMC,     NULL);
+AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
+AMBA_DEVICE(wdog,       "dev:e1",       PB1176_WATCHDOG,        NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PB1176_GPIO0,   NULL);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(rtc,        "dev:e8",       PB1176_RTC,     NULL);
+AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
+AMBA_DEVICE(uart0,      "dev:f1",       PB1176_UART0,   NULL);
+AMBA_DEVICE(uart1,      "dev:f2",       PB1176_UART1,   NULL);
+AMBA_DEVICE(uart2,      "dev:f3",       PB1176_UART2,   NULL);
+AMBA_DEVICE(ssp0,       "dev:f4",       PB1176_SSP,     NULL);
+
+/* Primecells on the NEC ISSP chip */
+AMBA_DEVICE(clcd,       "issp:20",      PB1176_CLCD,    &clcd_plat_data);
+//AMBA_DEVICE(dmac,     "issp:30",      PB1176_DMAC,    NULL);
+
+static struct amba_device *amba_devs[] __initdata = {
+//      &dmac_device,
+        &uart0_device,
+        &uart1_device,
+        &uart2_device,
+        &uart3_device,
+        &smc_device,
+        &clcd_device,
+        &sctl_device,
+        &wdog_device,
+        &gpio0_device,
+        &gpio1_device,
+        &gpio2_device,
+        &rtc_device,
+        &sci0_device,
+        &ssp0_device,
+        &aaci_device,
+        &mmc0_device,
+        &kmi0_device,
+        &kmi1_device,
+};
+
+/*
+ * RealView PB1176 platform devices
+ */
+static struct resource realview_pb1176_flash_resource = {
+        .start                  = REALVIEW_PB1176_FLASH_BASE,
+        .end                    = REALVIEW_PB1176_FLASH_BASE + REALVIEW_PB1176_FLASH_SIZE - 1,
+        .flags                  = IORESOURCE_MEM,
+};
+
+static struct resource realview_pb1176_smsc911x_resources[] = {
+        [0] = {
+                .start          = REALVIEW_PB1176_ETH_BASE,
+                .end            = REALVIEW_PB1176_ETH_BASE + SZ_64K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = IRQ_PB1176_ETH,
+                .end            = IRQ_PB1176_ETH,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device realview_pb1176_smsc911x_device = {
+        .name           = "smc911x",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(realview_pb1176_smsc911x_resources),
+        .resource       = realview_pb1176_smsc911x_resources,
+};
+
+static void __init gic_init_irq(void)
+{
+        /* ARM1176 DevChip GIC, primary */
+        gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE);
+        gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START);
+        gic_cpu_init(0, gic_cpu_base_addr);
+
+        /* board GIC, secondary */
+        gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START);
+        gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
+        gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
+}
+
+static void __init realview_pb1176_timer_init(void)
+{
+        timer0_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE);
+        timer1_va_base = __io_address(REALVIEW_PB1176_TIMER0_1_BASE) + 0x20;
+        timer2_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE);
+        timer3_va_base = __io_address(REALVIEW_PB1176_TIMER2_3_BASE) + 0x20;
+
+        realview_timer_init(IRQ_DC1176_TIMER0);
+}
+
+static struct sys_timer realview_pb1176_timer = {
+        .init           = realview_pb1176_timer_init,
+};
+
+static void __init realview_pb1176_init(void)
+{
+        int i;
+
+#ifdef CONFIG_CACHE_L2X0
+        /* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */
+        l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
+#endif
+
+        clk_register(&realview_clcd_clk);
+
+        realview_flash_register(&realview_pb1176_flash_resource, 1);
+        platform_device_register(&realview_pb1176_smsc911x_device);
+
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+
+#ifdef CONFIG_LEDS
+        leds_event = realview_leds_event;
+#endif
+}
+
+MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
+        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
+        .phys_io        = REALVIEW_PB1176_UART0_BASE,
+        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .map_io         = realview_pb1176_map_io,
+        .init_irq       = gic_init_irq,
+        .timer          = &realview_pb1176_timer,
+        .init_machine   = realview_pb1176_init,
+MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
new file mode 100644
index 000000000000..f7ce1c5a178a
--- /dev/null
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -0,0 +1,342 @@
+/*
+ *  linux/arch/arm/mach-realview/realview_pb11mp.c
+ *
+ *  Copyright (C) 2008 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/icst307.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+#include <asm/mach/mmc.h>
+#include <asm/mach/time.h>
+
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/irqs.h>
+
+#include "core.h"
+#include "clock.h"
+
+static struct map_desc realview_pb11mp_io_desc[] __initdata = {
+        {
+                .virtual        = IO_ADDRESS(REALVIEW_SYS_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_SYS_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_SCTL_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_SCTL_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE),
+                .length         = SZ_8K,
+                .type           = MT_DEVICE,
+        },
+#ifdef CONFIG_DEBUG_LL
+        {
+                .virtual        = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+#endif
+};
+
+static void __init realview_pb11mp_map_io(void)
+{
+        iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
+}
+
+/*
+ * RealView PB11MPCore AMBA devices
+ */
+
+#define GPIO2_IRQ               { IRQ_PB11MP_GPIO2, NO_IRQ }
+#define GPIO2_DMA               { 0, 0 }
+#define GPIO3_IRQ               { IRQ_PB11MP_GPIO3, NO_IRQ }
+#define GPIO3_DMA               { 0, 0 }
+#define AACI_IRQ                { IRQ_TC11MP_AACI, NO_IRQ }
+#define AACI_DMA                { 0x80, 0x81 }
+#define MMCI0_IRQ               { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
+#define MMCI0_DMA               { 0x84, 0 }
+#define KMI0_IRQ                { IRQ_TC11MP_KMI0, NO_IRQ }
+#define KMI0_DMA                { 0, 0 }
+#define KMI1_IRQ                { IRQ_TC11MP_KMI1, NO_IRQ }
+#define KMI1_DMA                { 0, 0 }
+#define PB11MP_SMC_IRQ          { NO_IRQ, NO_IRQ }
+#define PB11MP_SMC_DMA          { 0, 0 }
+#define MPMC_IRQ                { NO_IRQ, NO_IRQ }
+#define MPMC_DMA                { 0, 0 }
+#define PB11MP_CLCD_IRQ         { IRQ_PB11MP_CLCD, NO_IRQ }
+#define PB11MP_CLCD_DMA         { 0, 0 }
+#define DMAC_IRQ                { IRQ_PB11MP_DMAC, NO_IRQ }
+#define DMAC_DMA                { 0, 0 }
+#define SCTL_IRQ                { NO_IRQ, NO_IRQ }
+#define SCTL_DMA                { 0, 0 }
+#define PB11MP_WATCHDOG_IRQ     { IRQ_PB11MP_WATCHDOG, NO_IRQ }
+#define PB11MP_WATCHDOG_DMA     { 0, 0 }
+#define PB11MP_GPIO0_IRQ        { IRQ_PB11MP_GPIO0, NO_IRQ }
+#define PB11MP_GPIO0_DMA        { 0, 0 }
+#define GPIO1_IRQ               { IRQ_PB11MP_GPIO1, NO_IRQ }
+#define GPIO1_DMA               { 0, 0 }
+#define PB11MP_RTC_IRQ          { IRQ_TC11MP_RTC, NO_IRQ }
+#define PB11MP_RTC_DMA          { 0, 0 }
+#define SCI_IRQ                 { IRQ_PB11MP_SCI, NO_IRQ }
+#define SCI_DMA                 { 7, 6 }
+#define PB11MP_UART0_IRQ        { IRQ_TC11MP_UART0, NO_IRQ }
+#define PB11MP_UART0_DMA        { 15, 14 }
+#define PB11MP_UART1_IRQ        { IRQ_TC11MP_UART1, NO_IRQ }
+#define PB11MP_UART1_DMA        { 13, 12 }
+#define PB11MP_UART2_IRQ        { IRQ_PB11MP_UART2, NO_IRQ }
+#define PB11MP_UART2_DMA        { 11, 10 }
+#define PB11MP_UART3_IRQ        { IRQ_PB11MP_UART3, NO_IRQ }
+#define PB11MP_UART3_DMA        { 0x86, 0x87 }
+#define PB11MP_SSP_IRQ          { IRQ_PB11MP_SSP, NO_IRQ }
+#define PB11MP_SSP_DMA          { 9, 8 }
+
+/* FPGA Primecells */
+AMBA_DEVICE(aaci,       "fpga:04",      AACI,           NULL);
+AMBA_DEVICE(mmc0,       "fpga:05",      MMCI0,          &realview_mmc0_plat_data);
+AMBA_DEVICE(kmi0,       "fpga:06",      KMI0,           NULL);
+AMBA_DEVICE(kmi1,       "fpga:07",      KMI1,           NULL);
+AMBA_DEVICE(uart3,      "fpga:09",      PB11MP_UART3,   NULL);
+
+/* DevChip Primecells */
+AMBA_DEVICE(smc,        "dev:00",       PB11MP_SMC,     NULL);
+AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
+AMBA_DEVICE(wdog,       "dev:e1",       PB11MP_WATCHDOG, NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PB11MP_GPIO0,   NULL);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(rtc,        "dev:e8",       PB11MP_RTC,     NULL);
+AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
+AMBA_DEVICE(uart0,      "dev:f1",       PB11MP_UART0,   NULL);
+AMBA_DEVICE(uart1,      "dev:f2",       PB11MP_UART1,   NULL);
+AMBA_DEVICE(uart2,      "dev:f3",       PB11MP_UART2,   NULL);
+AMBA_DEVICE(ssp0,       "dev:f4",       PB11MP_SSP,     NULL);
+
+/* Primecells on the NEC ISSP chip */
+AMBA_DEVICE(clcd,       "issp:20",      PB11MP_CLCD,    &clcd_plat_data);
+AMBA_DEVICE(dmac,       "issp:30",      DMAC,           NULL);
+
+static struct amba_device *amba_devs[] __initdata = {
+        &dmac_device,
+        &uart0_device,
+        &uart1_device,
+        &uart2_device,
+        &uart3_device,
+        &smc_device,
+        &clcd_device,
+        &sctl_device,
+        &wdog_device,
+        &gpio0_device,
+        &gpio1_device,
+        &gpio2_device,
+        &rtc_device,
+        &sci0_device,
+        &ssp0_device,
+        &aaci_device,
+        &mmc0_device,
+        &kmi0_device,
+        &kmi1_device,
+};
+
+/*
+ * RealView PB11MPCore platform devices
+ */
+static struct resource realview_pb11mp_flash_resource[] = {
+        [0] = {
+                .start          = REALVIEW_PB11MP_FLASH0_BASE,
+                .end            = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = REALVIEW_PB11MP_FLASH1_BASE,
+                .end            = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct resource realview_pb11mp_smsc911x_resources[] = {
+        [0] = {
+                .start          = REALVIEW_PB11MP_ETH_BASE,
+                .end            = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = IRQ_TC11MP_ETH,
+                .end            = IRQ_TC11MP_ETH,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device realview_pb11mp_smsc911x_device = {
+        .name           = "smc911x",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(realview_pb11mp_smsc911x_resources),
+        .resource       = realview_pb11mp_smsc911x_resources,
+};
+
+struct resource realview_pb11mp_cf_resources[] = {
+        [0] = {
+                .start          = REALVIEW_PB11MP_CF_BASE,
+                .end            = REALVIEW_PB11MP_CF_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = REALVIEW_PB11MP_CF_MEM_BASE,
+                .end            = REALVIEW_PB11MP_CF_MEM_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start          = -1,           /* FIXME: Find correct irq */
+                .end            = -1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device realview_pb11mp_cf_device = {
+        .name           = "compactflash",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(realview_pb11mp_cf_resources),
+        .resource       = realview_pb11mp_cf_resources,
+};
+
+static void __init gic_init_irq(void)
+{
+        unsigned int pldctrl;
+
+        /* new irq mode with no DCC */
+        writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
+        pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
+        pldctrl |= 2 << 22;
+        writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
+        writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
+
+        /* ARM11MPCore test chip GIC, primary */
+        gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE);
+        gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29);
+        gic_cpu_init(0, gic_cpu_base_addr);
+
+        /* board GIC, secondary */
+        gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START);
+        gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
+        gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
+}
+
+static void __init realview_pb11mp_timer_init(void)
+{
+        timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
+        timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20;
+        timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
+        timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
+
+#ifdef CONFIG_LOCAL_TIMERS
+        twd_base_addr = __io_address(REALVIEW_TC11MP_TWD_BASE);
+        twd_size = REALVIEW_TC11MP_TWD_SIZE;
+#endif
+        realview_timer_init(IRQ_TC11MP_TIMER0_1);
+}
+
+static struct sys_timer realview_pb11mp_timer = {
+        .init           = realview_pb11mp_timer_init,
+};
+
+static void __init realview_pb11mp_init(void)
+{
+        int i;
+
+#ifdef CONFIG_CACHE_L2X0
+        /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
+         * Bits:  .... ...0 0111 1001 0000 .... .... .... */
+        l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
+#endif
+
+        clk_register(&realview_clcd_clk);
+
+        realview_flash_register(realview_pb11mp_flash_resource,
+                                ARRAY_SIZE(realview_pb11mp_flash_resource));
+        platform_device_register(&realview_pb11mp_smsc911x_device);
+        platform_device_register(&realview_i2c_device);
+        platform_device_register(&realview_pb11mp_cf_device);
+
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+
+#ifdef CONFIG_LEDS
+        leds_event = realview_leds_event;
+#endif
+}
+
+MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
+        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
+        .phys_io        = REALVIEW_PB11MP_UART0_BASE,
+        .io_pg_offst    = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .map_io         = realview_pb11mp_map_io,
+        .init_irq       = gic_init_irq,
+        .timer          = &realview_pb11mp_timer,
+        .init_machine   = realview_pb11mp_init,
+MACHINE_END
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index 7a61e8d33ab7..8e0244631d65 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := clock.o generic.o irq.o dma.o time.o #nmi-oopser.o
+obj-y := clock.o generic.o gpio.o irq.o dma.o time.o #nmi-oopser.o
 obj-m :=
 obj-n :=
 obj-  :=
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 5c84c604ed86..0c2fa1c4fb4c 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -139,37 +139,6 @@ unsigned long long sched_clock(void)
         return v;
 }
 
-int gpio_direction_input(unsigned gpio)
-{
-        unsigned long flags;
-
-        if (gpio > GPIO_MAX)
-                return -EINVAL;
-
-        local_irq_save(flags);
-        GPDR &= ~GPIO_GPIO(gpio);
-        local_irq_restore(flags);
-        return 0;
-}
-
-EXPORT_SYMBOL(gpio_direction_input);
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-        unsigned long flags;
-
-        if (gpio > GPIO_MAX)
-                return -EINVAL;
-
-        local_irq_save(flags);
-        gpio_set_value(gpio, value);
-        GPDR |= GPIO_GPIO(gpio);
-        local_irq_restore(flags);
-        return 0;
-}
-
-EXPORT_SYMBOL(gpio_direction_output);
-
 /*
  * Default power-off for SA1100
  */
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index f085d68e568e..793c2e6c991f 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -9,6 +9,7 @@ struct sys_timer;
 extern struct sys_timer sa1100_timer;
 extern void __init sa1100_map_io(void);
 extern void __init sa1100_init_irq(void);
+extern void __init sa1100_init_gpio(void);
 
 #define SET_BANK(__nr,__start,__size) \
         mi->bank[__nr].start = (__start), \
diff --git a/arch/arm/mach-sa1100/gpio.c b/arch/arm/mach-sa1100/gpio.c
new file mode 100644
index 000000000000..372f1f4f54a1
--- /dev/null
+++ b/arch/arm/mach-sa1100/gpio.c
@@ -0,0 +1,65 @@
+/*
+ * linux/arch/arm/mach-sa1100/gpio.c
+ *
+ * Generic SA-1100 GPIO handling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <asm/gpio.h>
+#include <asm/hardware.h>
+#include "generic.h"
+
+static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        return GPLR & GPIO_GPIO(offset);
+}
+
+static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        if (value)
+                GPSR = GPIO_GPIO(offset);
+        else
+                GPCR = GPIO_GPIO(offset);
+}
+
+static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        GPDR &= ~GPIO_GPIO(offset);
+        local_irq_restore(flags);
+        return 0;
+}
+
+static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        sa1100_gpio_set(chip, offset, value);
+        GPDR |= GPIO_GPIO(offset);
+        local_irq_restore(flags);
+        return 0;
+}
+
+static struct gpio_chip sa1100_gpio_chip = {
+        .label                  = "gpio",
+        .direction_input        = sa1100_direction_input,
+        .direction_output       = sa1100_direction_output,
+        .set                    = sa1100_gpio_set,
+        .get                    = sa1100_gpio_get,
+        .base                   = 0,
+        .ngpio                  = GPIO_MAX + 1,
+};
+
+void __init sa1100_init_gpio(void)
+{
+        gpiochip_add(&sa1100_gpio_chip);
+}
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 3dc17d7bf38e..fa0403af7eec 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -347,4 +347,6 @@ void __init sa1100_init_irq(void)
          */
         set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
         set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
+
+        sa1100_init_gpio();
 }
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index c2677368d6af..a9799cb35b74 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -13,67 +13,69 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/timex.h>
-#include <linux/signal.h>
-#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
 #include <asm/hardware.h>
 
-#define RTC_DEF_DIVIDER         (32768 - 1)
-#define RTC_DEF_TRIM            0
+#define MIN_OSCR_DELTA 2
 
-static int sa1100_set_rtc(void)
+static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
 {
-        unsigned long current_time = xtime.tv_sec;
+        struct clock_event_device *c = dev_id;
 
-        if (RTSR & RTSR_ALE) {
-                /* make sure not to forward the clock over an alarm */
-                unsigned long alarm = RTAR;
-                if (current_time >= alarm && alarm >= RCNR)
-                        return -ERESTARTSYS;
-        }
-        RCNR = current_time;
-        return 0;
-}
+        /* Disarm the compare/match, signal the event. */
+        OIER &= ~OIER_E0;
+        OSSR = OSSR_M0;
+        c->event_handler(c);
 
-#ifdef CONFIG_NO_IDLE_HZ
-static unsigned long initial_match;
-static int match_posponed;
-#endif
+        return IRQ_HANDLED;
+}
 
-static irqreturn_t
-sa1100_timer_interrupt(int irq, void *dev_id)
+static int
+sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
 {
-        unsigned int next_match;
+        unsigned long flags, next, oscr;
 
-#ifdef CONFIG_NO_IDLE_HZ
-        if (match_posponed) {
-                match_posponed = 0;
-                OSMR0 = initial_match;
-        }
-#endif
+        raw_local_irq_save(flags);
+        OIER |= OIER_E0;
+        next = OSCR + delta;
+        OSMR0 = next;
+        oscr = OSCR;
+        raw_local_irq_restore(flags);
 
-        /*
-         * Loop until we get ahead of the free running timer.
-         * This ensures an exact clock tick count and time accuracy.
-         * Since IRQs are disabled at this point, coherence between
-         * lost_ticks(updated in do_timer()) and the match reg value is
-         * ensured, hence we can use do_gettimeofday() from interrupt
-         * handlers.
-         */
-        do {
-                timer_tick();
-                OSSR = OSSR_M0;  /* Clear match on timer 0 */
-                next_match = (OSMR0 += LATCH);
-        } while ((signed long)(next_match - OSCR) <= 0);
+        return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
+}
 
-        return IRQ_HANDLED;
+static void
+sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
+{
+        unsigned long flags;
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                raw_local_irq_save(flags);
+                OIER &= ~OIER_E0;
+                OSSR = OSSR_M0;
+                raw_local_irq_restore(flags);
+                break;
+
+        case CLOCK_EVT_MODE_RESUME:
+        case CLOCK_EVT_MODE_PERIODIC:
+                break;
+        }
 }
 
-static struct irqaction sa1100_timer_irq = {
-        .name           = "SA11xx Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = sa1100_timer_interrupt,
+static struct clock_event_device ckevt_sa1100_osmr0 = {
+        .name           = "osmr0",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .rating         = 200,
+        .cpumask        = CPU_MASK_CPU0,
+        .set_next_event = sa1100_osmr0_set_next_event,
+        .set_mode       = sa1100_osmr0_set_mode,
 };
 
 static cycle_t sa1100_read_oscr(void)
@@ -90,62 +92,34 @@ static struct clocksource cksrc_sa1100_oscr = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static struct irqaction sa1100_timer_irq = {
+        .name           = "ost0",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = sa1100_ost0_interrupt,
+        .dev_id         = &ckevt_sa1100_osmr0,
+};
+
 static void __init sa1100_timer_init(void)
 {
-        unsigned long flags;
-
-        set_rtc = sa1100_set_rtc;
-
         OIER = 0;               /* disable any timer interrupts */
         OSSR = 0xf;             /* clear status on all timers */
-        setup_irq(IRQ_OST0, &sa1100_timer_irq);
-        local_irq_save(flags);
-        OIER = OIER_E0;         /* enable match on timer 0 to cause interrupts */
-        OSMR0 = OSCR + LATCH;   /* set initial match */
-        local_irq_restore(flags);
+
+        ckevt_sa1100_osmr0.mult =
+                div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift);
+        ckevt_sa1100_osmr0.max_delta_ns =
+                clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
+        ckevt_sa1100_osmr0.min_delta_ns =
+                clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1;
 
         cksrc_sa1100_oscr.mult =
                 clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift);
 
-        clocksource_register(&cksrc_sa1100_oscr);
-}
-
-#ifdef CONFIG_NO_IDLE_HZ
-static int sa1100_dyn_tick_enable_disable(void)
-{
-        /* nothing to do */
-        return 0;
-}
-
-static void sa1100_dyn_tick_reprogram(unsigned long ticks)
-{
-        if (ticks > 1) {
-                initial_match = OSMR0;
-                OSMR0 = initial_match + ticks * LATCH;
-                match_posponed = 1;
-        }
-}
+        setup_irq(IRQ_OST0, &sa1100_timer_irq);
 
-static irqreturn_t
-sa1100_dyn_tick_handler(int irq, void *dev_id)
-{
-        if (match_posponed) {
-                match_posponed = 0;
-                OSMR0 = initial_match;
-                if ((signed long)(initial_match - OSCR) <= 0)
-                        return sa1100_timer_interrupt(irq, dev_id);
-        }
-        return IRQ_NONE;
+        clocksource_register(&cksrc_sa1100_oscr);
+        clockevents_register_device(&ckevt_sa1100_osmr0);
 }
 
-static struct dyn_tick_timer sa1100_dyn_tick = {
-        .enable         = sa1100_dyn_tick_enable_disable,
-        .disable        = sa1100_dyn_tick_enable_disable,
-        .reprogram      = sa1100_dyn_tick_reprogram,
-        .handler        = sa1100_dyn_tick_handler,
-};
-#endif
-
 #ifdef CONFIG_PM
 unsigned long osmr[4], oier;
 
@@ -181,7 +155,4 @@ struct sys_timer sa1100_timer = {
         .init           = sa1100_timer_init,
         .suspend        = sa1100_timer_suspend,
         .resume         = sa1100_timer_resume,
-#ifdef CONFIG_NO_IDLE_HZ
-        .dyn_tick       = &sa1100_dyn_tick,
-#endif
 };
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 76348f060f27..746cbb7c8e95 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -18,6 +18,7 @@ config CPU_ARM610
         select CPU_CP15_MMU
         select CPU_COPY_V3 if MMU
         select CPU_TLB_V3 if MMU
+        select CPU_PABRT_NOIFAR
         help
           The ARM610 is the successor to the ARM3 processor
           and was produced by VLSI Technology Inc.
@@ -49,6 +50,7 @@ config CPU_ARM710
         select CPU_CP15_MMU
         select CPU_COPY_V3 if MMU
         select CPU_TLB_V3 if MMU
+        select CPU_PABRT_NOIFAR
         help
           A 32-bit RISC microprocessor based on the ARM7 processor core
           designed by Advanced RISC Machines Ltd. The ARM710 is the
@@ -64,6 +66,7 @@ config CPU_ARM720T
         default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
         select CPU_32v4T
         select CPU_ABRT_LV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -113,6 +116,7 @@ config CPU_ARM920T
         default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
         select CPU_32v4T
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -135,6 +139,7 @@ config CPU_ARM922T
         default y if ARCH_LH7A40X || ARCH_KS8695
         select CPU_32v4T
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -155,6 +160,7 @@ config CPU_ARM925T
         default y if ARCH_OMAP15XX
         select CPU_32v4T
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -175,6 +181,7 @@ config CPU_ARM926T
         default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
         select CPU_32v5
         select CPU_ABRT_EV5TJ
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_V4WB if MMU
@@ -226,6 +233,7 @@ config CPU_ARM1020
         depends on ARCH_INTEGRATOR
         select CPU_32v5
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -244,6 +252,7 @@ config CPU_ARM1020E
         depends on ARCH_INTEGRATOR
         select CPU_32v5
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WT
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -257,6 +266,7 @@ config CPU_ARM1022
         depends on ARCH_INTEGRATOR
         select CPU_32v5
         select CPU_ABRT_EV4T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_V4WB if MMU # can probably do better
@@ -275,6 +285,7 @@ config CPU_ARM1026
         depends on ARCH_INTEGRATOR
         select CPU_32v5
         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_V4WB if MMU # can probably do better
@@ -293,6 +304,7 @@ config CPU_SA110
         select CPU_32v3 if ARCH_RPC
         select CPU_32v4 if !ARCH_RPC
         select CPU_ABRT_EV4
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WB
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -314,6 +326,7 @@ config CPU_SA1100
         default y
         select CPU_32v4
         select CPU_ABRT_EV4
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V4WB
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
@@ -326,6 +339,7 @@ config CPU_XSCALE
         default y
         select CPU_32v5
         select CPU_ABRT_EV5T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_TLB_V4WBI if MMU
@@ -345,10 +359,11 @@ config CPU_XSC3
 # Feroceon
 config CPU_FEROCEON
         bool
-        depends on ARCH_ORION
+        depends on ARCH_ORION5X
         default y
         select CPU_32v5
         select CPU_ABRT_EV5T
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_VIVT
         select CPU_CP15_MMU
         select CPU_COPY_V4WB if MMU
@@ -366,11 +381,12 @@ config CPU_FEROCEON_OLD_ID
 # ARMv6
 config CPU_V6
         bool "Support ARM V6 processor"
-        depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A
+        depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
         default y if ARCH_MX3
         default y if ARCH_MSM7X00A
         select CPU_32v6
         select CPU_ABRT_EV6
+        select CPU_PABRT_NOIFAR
         select CPU_CACHE_V6
         select CPU_CACHE_VIPT
         select CPU_CP15_MMU
@@ -393,10 +409,11 @@ config CPU_32v6K
 # ARMv7
 config CPU_V7
         bool "Support ARM V7 processor"
-        depends on ARCH_INTEGRATOR
+        depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
         select CPU_32v6K
         select CPU_32v7
         select CPU_ABRT_EV7
+        select CPU_PABRT_IFAR
         select CPU_CACHE_V7
         select CPU_CACHE_VIPT
         select CPU_CP15_MMU
@@ -458,6 +475,12 @@ config CPU_ABRT_EV6
 config CPU_ABRT_EV7
         bool
 
+config CPU_PABRT_IFAR
+        bool
+
+config CPU_PABRT_NOIFAR
+        bool
+
 # The cache model
 config CPU_CACHE_V3
         bool
@@ -572,6 +595,13 @@ config ARM_THUMB
 
           If you don't know what this all is, saying Y is a safe choice.
 
+config ARM_THUMBEE
+        bool "Enable ThumbEE CPU extension"
+        depends on CPU_V7
+        help
+          Say Y here if you have a CPU with the ThumbEE extension and code to
+          make use of it. Say N for code that can run on CPUs without ThumbEE.
+
 config CPU_BIG_ENDIAN
         bool "Build big-endian kernel"
         depends on ARCH_SUPPORTS_BIG_ENDIAN
@@ -671,5 +701,9 @@ config OUTER_CACHE
         default n
 
 config CACHE_L2X0
-        bool
+        bool "Enable the L2x0 outer cache controller"
+        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
+        default y
         select OUTER_CACHE
+        help
+          This option enables the L2x0 PrimeCell.
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index ec00f26bffa4..b657f1719af0 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -48,8 +48,6 @@ void show_mem(void)
 
         printk("Mem-info:\n");
         show_free_areas();
-        printk("Free swap:       %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
-
         for_each_online_node(node) {
                 pg_data_t *n = NODE_DATA(node);
                 struct page *map = n->node_mem_map - n->node_start_pfn;
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 700c04d6996e..32fd7ea533f2 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -478,6 +478,7 @@ arm1020_processor_functions:
         .word   cpu_arm1020_dcache_clean_area
         .word   cpu_arm1020_switch_mm
         .word   cpu_arm1020_set_pte_ext
+        .word   pabort_noifar
         .size   arm1020_processor_functions, . - arm1020_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 1cc206ab5eae..fe2b0ae70274 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -459,6 +459,7 @@ arm1020e_processor_functions:
         .word   cpu_arm1020e_dcache_clean_area
         .word   cpu_arm1020e_switch_mm
         .word   cpu_arm1020e_set_pte_ext
+        .word   pabort_noifar
         .size   arm1020e_processor_functions, . - arm1020e_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index aff0ea08e2f8..06dde678e19d 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -442,6 +442,7 @@ arm1022_processor_functions:
         .word   cpu_arm1022_dcache_clean_area
         .word   cpu_arm1022_switch_mm
         .word   cpu_arm1022_set_pte_ext
+        .word   pabort_noifar
         .size   arm1022_processor_functions, . - arm1022_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 65e43a109085..f5506e6e681e 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -437,6 +437,7 @@ arm1026_processor_functions:
         .word   cpu_arm1026_dcache_clean_area
         .word   cpu_arm1026_switch_mm
         .word   cpu_arm1026_set_pte_ext
+        .word   pabort_noifar
         .size   arm1026_processor_functions, . - arm1026_processor_functions
 
         .section .rodata
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 123a7dc7a433..14b6a95c8d45 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -300,6 +300,7 @@ ENTRY(arm6_processor_functions)
                 .word   cpu_arm6_dcache_clean_area
                 .word   cpu_arm6_switch_mm
                 .word   cpu_arm6_set_pte_ext
+                .word   pabort_noifar
                 .size   arm6_processor_functions, . - arm6_processor_functions
 
 /*
@@ -316,6 +317,7 @@ ENTRY(arm7_processor_functions)
                 .word   cpu_arm7_dcache_clean_area
                 .word   cpu_arm7_switch_mm
                 .word   cpu_arm7_set_pte_ext
+                .word   pabort_noifar
                 .size   arm7_processor_functions, . - arm7_processor_functions
 
                 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index dc763be43362..ca5e7aac2da7 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -205,6 +205,7 @@ ENTRY(arm720_processor_functions)
                 .word   cpu_arm720_dcache_clean_area
                 .word   cpu_arm720_switch_mm
                 .word   cpu_arm720_set_pte_ext
+                .word   pabort_noifar
                 .size   arm720_processor_functions, . - arm720_processor_functions
 
                 .section ".rodata"
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 75c945ed6c4d..0170d4f466ea 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -424,6 +424,7 @@ arm920_processor_functions:
         .word   cpu_arm920_dcache_clean_area
         .word   cpu_arm920_switch_mm
         .word   cpu_arm920_set_pte_ext
+        .word   pabort_noifar
         .size   arm920_processor_functions, . - arm920_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index ffb751b877ff..b7952493d404 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -428,6 +428,7 @@ arm922_processor_functions:
         .word   cpu_arm922_dcache_clean_area
         .word   cpu_arm922_switch_mm
         .word   cpu_arm922_set_pte_ext
+        .word   pabort_noifar
         .size   arm922_processor_functions, . - arm922_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 44c2c997819f..e2988eba4cf6 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -491,6 +491,7 @@ arm925_processor_functions:
         .word   cpu_arm925_dcache_clean_area
         .word   cpu_arm925_switch_mm
         .word   cpu_arm925_set_pte_ext
+        .word   pabort_noifar
         .size   arm925_processor_functions, . - arm925_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 194ef48968e6..62f7d1dfe016 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -444,6 +444,7 @@ arm926_processor_functions:
         .word   cpu_arm926_dcache_clean_area
         .word   cpu_arm926_switch_mm
         .word   cpu_arm926_set_pte_ext
+        .word   pabort_noifar
         .size   arm926_processor_functions, . - arm926_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index fa0dc7e6f0ea..2f169b28e938 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -430,6 +430,7 @@ feroceon_processor_functions:
         .word   cpu_feroceon_dcache_clean_area
         .word   cpu_feroceon_switch_mm
         .word   cpu_feroceon_set_pte_ext
+        .word   pabort_noifar
         .size   feroceon_processor_functions, . - feroceon_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 6e226e12989f..4db3d6299a2b 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -223,6 +223,7 @@ ENTRY(sa110_processor_functions)
         .word   cpu_sa110_dcache_clean_area
         .word   cpu_sa110_switch_mm
         .word   cpu_sa110_set_pte_ext
+        .word   pabort_noifar
         .size   sa110_processor_functions, . - sa110_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 9afb11d089fe..3cdef043760f 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -238,6 +238,7 @@ ENTRY(sa1100_processor_functions)
         .word   cpu_sa1100_dcache_clean_area
         .word   cpu_sa1100_switch_mm
         .word   cpu_sa1100_set_pte_ext
+        .word   pabort_noifar
         .size   sa1100_processor_functions, . - sa1100_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index eb42e5b94863..bf760ea2f789 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -17,10 +17,6 @@
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
-#ifdef CONFIG_SMP
-#include <asm/hardware/arm_scu.h>
-#endif
-
 #include "proc-macros.S"
 
 #define D_CACHE_LINE_SIZE       32
@@ -187,20 +183,10 @@ cpu_v6_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-        /* Set up the SCU on core 0 only */
-        mrc     p15, 0, r0, c0, c0, 5           @ CPU core number
-        ands    r0, r0, #15
-        ldreq   r0, =SCU_BASE
-        ldreq   r5, [r0, #SCU_CTRL]
-        orreq   r5, r5, #1
-        streq   r5, [r0, #SCU_CTRL]
-
-#ifndef CONFIG_CPU_DCACHE_DISABLE
         mrc     p15, 0, r0, c1, c0, 1           @ Enable SMP/nAMP mode
         orr     r0, r0, #0x20
         mcr     p15, 0, r0, c1, c0, 1
 #endif
-#endif
 
         mov     r0, #0
         mcr     p15, 0, r0, c7, c14, 0          @ clean+invalidate D cache
@@ -240,6 +226,7 @@ ENTRY(v6_processor_functions)
         .word   cpu_v6_dcache_clean_area
         .word   cpu_v6_switch_mm
         .word   cpu_v6_set_pte_ext
+        .word   pabort_noifar
         .size   v6_processor_functions, . - v6_processor_functions
 
         .type   cpu_arch_name, #object
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index e0acc5ae6f6f..a1d7331cd64c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -212,6 +212,7 @@ ENTRY(v7_processor_functions)
         .word   cpu_v7_dcache_clean_area
         .word   cpu_v7_switch_mm
         .word   cpu_v7_set_pte_ext
+        .word   pabort_ifar
         .size   v7_processor_functions, . - v7_processor_functions
 
         .type   cpu_arch_name, #object
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 016690b9d564..1a6d89823dff 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -534,6 +534,7 @@ ENTRY(xscale_processor_functions)
         .word   cpu_xscale_dcache_clean_area
         .word   cpu_xscale_switch_mm
         .word   cpu_xscale_set_pte_ext
+        .word   pabort_noifar
         .size   xscale_processor_functions, . - xscale_processor_functions
 
         .section ".rodata"
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index 98d01517b563..d9bc15a69e5d 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -24,6 +24,7 @@
 #include <asm/hardware.h>
 #include <asm/mach/pci.h>
 #include <asm/hardware/iop3xx.h>
+#include <asm/mach-types.h>
 
 // #define DEBUG
 
@@ -209,8 +210,11 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
         res[1].flags = IORESOURCE_MEM;
         request_resource(&iomem_resource, &res[1]);
 
-        sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA;
-        sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - IOP3XX_PCI_LOWER_IO_BA;
+        /*
+         * Use whatever translation is already setup.
+         */
+        sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
+        sys->io_offset  = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR;
 
         sys->resource[0] = &res[0];
         sys->resource[1] = &res[1];
@@ -250,11 +254,11 @@ void __init iop3xx_atu_setup(void)
         *IOP3XX_IATVR2 = PHYS_OFFSET;
 
         /* Outbound window 0 */
-        *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_PA;
+        *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA;
         *IOP3XX_OUMWTVR0 = 0;
 
         /* Outbound window 1 */
-        *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE;
+        *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + IOP3XX_PCI_MEM_WINDOW_SIZE;
         *IOP3XX_OUMWTVR1 = 0;
 
         /* BAR 3 ( Disabled ) */
@@ -265,7 +269,7 @@ void __init iop3xx_atu_setup(void)
 
         /* Setup the I/O Bar
          */
-        *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_PA;;
+        *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA;
 
         /* Enable inbound and outbound cycles
          */
@@ -322,34 +326,59 @@ void __init iop3xx_atu_disable(void)
 /* Flag to determine whether the ATU is initialized and the PCI bus scanned */
 int init_atu;
 
-void __init iop3xx_pci_preinit(void)
+int iop3xx_get_init_atu(void) {
+        /* check if default has been overridden */
+        if (init_atu != IOP3XX_INIT_ATU_DEFAULT)
+                return init_atu;
+        else
+                return IOP3XX_INIT_ATU_DISABLE;
+}
+
+static void __init iop3xx_atu_debug(void)
 {
-        if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
-                iop3xx_atu_disable();
-                iop3xx_atu_setup();
-        }
+        DBG("PCI: Intel IOP3xx PCI init.\n");
+        DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n",
+                *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0);
+        DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n",
+                *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1);
+        DBG("PCI: Outbound IO window: PCI 0x%08x\n",
+                *IOP3XX_OIOWTVR);
+
+        DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
+                *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
+        DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n",
+                *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1);
+        DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
+                *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
+        DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
+                *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
+
+        DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
+                0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
 
-        DBG("PCI:  Intel 803xx PCI init code.\n");
         DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
-        DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
-                        *IOP3XX_OMWTVR0,
-                        *IOP3XX_OIOWTVR);
         DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
-        DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",
-                        *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
-        DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0);
-        DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",
-                        *IOP3XX_IABAR1, *IOP3XX_IALR1);
-        DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",
-                        *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
-        DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",
-                        *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
-        DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",
-                        *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
 
         hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
 }
 
+/* for platforms that might be host-bus-adapters */
+void __init iop3xx_pci_preinit_cond(void)
+{
+        if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
+                iop3xx_atu_disable();
+                iop3xx_atu_setup();
+                iop3xx_atu_debug();
+        }
+}
+
+void __init iop3xx_pci_preinit(void)
+{
+        iop3xx_atu_disable();
+        iop3xx_atu_setup();
+        iop3xx_atu_debug();
+}
+
 /* allow init_atu to be user overridden */
 static int __init iop3xx_init_atu_setup(char *str)
 {
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 03a65c0dfb60..bb6e12738fb3 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -4,7 +4,7 @@ menu "Freescale MXC Implementations"
 
 choice
         prompt "MXC/iMX System Type"
-        default 0
+        default ARCH_MX3
 
 config ARCH_MX3
         bool "MX3-based"
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 66ad9c2b6d64..f96dc0362068 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -4,7 +4,3 @@
 
 # Common support
 obj-y := irq.o
-
-obj-m :=
-obj-n :=
-obj-  :=
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 87d253bc3d3c..2ad5a6917b3f 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -19,21 +19,13 @@
 #include <asm/mach/irq.h>
 #include <asm/arch/common.h>
 
-/*!
- * Disable interrupt number "irq" in the AVIC
- *
- * @param  irq          interrupt source number
- */
+/* Disable interrupt number "irq" in the AVIC */
 static void mxc_mask_irq(unsigned int irq)
 {
         __raw_writel(irq, AVIC_INTDISNUM);
 }
 
-/*!
- * Enable interrupt number "irq" in the AVIC
- *
- * @param  irq          interrupt source number
- */
+/* Enable interrupt number "irq" in the AVIC */
 static void mxc_unmask_irq(unsigned int irq)
 {
         __raw_writel(irq, AVIC_INTENNUM);
@@ -45,7 +37,7 @@ static struct irq_chip mxc_avic_chip = {
         .unmask = mxc_unmask_irq,
 };
 
-/*!
+/*
  * This function initializes the AVIC hardware and disables all the
  * interrupts. It registers the interrupt enable and disable functions
  * to the kernel for each interrupt source.
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
new file mode 100644
index 000000000000..198f3dde2be3
--- /dev/null
+++ b/arch/arm/plat-orion/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y   := irq.o pcie.o time.o
+obj-m   :=
+obj-n   :=
+obj-    :=
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
new file mode 100644
index 000000000000..c5b669d234bc
--- /dev/null
+++ b/arch/arm/plat-orion/irq.c
@@ -0,0 +1,64 @@
+/*
+ * arch/arm/plat-orion/irq.c
+ *
+ * Marvell Orion SoC IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/plat-orion/irq.h>
+
+static void orion_irq_mask(u32 irq)
+{
+        void __iomem *maskaddr = get_irq_chip_data(irq);
+        u32 mask;
+
+        mask = readl(maskaddr);
+        mask &= ~(1 << (irq & 31));
+        writel(mask, maskaddr);
+}
+
+static void orion_irq_unmask(u32 irq)
+{
+        void __iomem *maskaddr = get_irq_chip_data(irq);
+        u32 mask;
+
+        mask = readl(maskaddr);
+        mask |= 1 << (irq & 31);
+        writel(mask, maskaddr);
+}
+
+static struct irq_chip orion_irq_chip = {
+        .name           = "orion_irq",
+        .ack            = orion_irq_mask,
+        .mask           = orion_irq_mask,
+        .unmask         = orion_irq_unmask,
+};
+
+void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
+{
+        unsigned int i;
+
+        /*
+         * Mask all interrupts initially.
+         */
+        writel(0, maskaddr);
+
+        /*
+         * Register IRQ sources.
+         */
+        for (i = 0; i < 32; i++) {
+                unsigned int irq = irq_start + i;
+
+                set_irq_chip(irq, &orion_irq_chip);
+                set_irq_chip_data(irq, maskaddr);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+}
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
new file mode 100644
index 000000000000..abfda53f1800
--- /dev/null
+++ b/arch/arm/plat-orion/pcie.c
@@ -0,0 +1,245 @@
+/*
+ * arch/arm/plat-orion/pcie.c
+ *
+ * Marvell Orion SoC PCIe handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/plat-orion/pcie.h>
+
+/*
+ * PCIe unit register offsets.
+ */
+#define PCIE_DEV_ID_OFF         0x0000
+#define PCIE_CMD_OFF            0x0004
+#define PCIE_DEV_REV_OFF        0x0008
+#define PCIE_BAR_LO_OFF(n)      (0x0010 + ((n) << 3))
+#define PCIE_BAR_HI_OFF(n)      (0x0014 + ((n) << 3))
+#define PCIE_HEADER_LOG_4_OFF   0x0128
+#define PCIE_BAR_CTRL_OFF(n)    (0x1804 + ((n - 1) * 4))
+#define PCIE_WIN04_CTRL_OFF(n)  (0x1820 + ((n) << 4))
+#define PCIE_WIN04_BASE_OFF(n)  (0x1824 + ((n) << 4))
+#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
+#define PCIE_WIN5_CTRL_OFF      0x1880
+#define PCIE_WIN5_BASE_OFF      0x1884
+#define PCIE_WIN5_REMAP_OFF     0x188c
+#define PCIE_CONF_ADDR_OFF      0x18f8
+#define  PCIE_CONF_ADDR_EN              0x80000000
+#define  PCIE_CONF_REG(r)               ((((r) & 0xf00) << 16) | ((r) & 0xfc))
+#define  PCIE_CONF_BUS(b)               (((b) & 0xff) << 16)
+#define  PCIE_CONF_DEV(d)               (((d) & 0x1f) << 11)
+#define  PCIE_CONF_FUNC(f)              (((f) & 0x3) << 8)
+#define PCIE_CONF_DATA_OFF      0x18fc
+#define PCIE_MASK_OFF           0x1910
+#define PCIE_CTRL_OFF           0x1a00
+#define PCIE_STAT_OFF           0x1a04
+#define  PCIE_STAT_DEV_OFFS             20
+#define  PCIE_STAT_DEV_MASK             0x1f
+#define  PCIE_STAT_BUS_OFFS             8
+#define  PCIE_STAT_BUS_MASK             0xff
+#define  PCIE_STAT_LINK_DOWN            1
+
+
+u32 __init orion_pcie_dev_id(void __iomem *base)
+{
+        return readl(base + PCIE_DEV_ID_OFF) >> 16;
+}
+
+u32 __init orion_pcie_rev(void __iomem *base)
+{
+        return readl(base + PCIE_DEV_REV_OFF) & 0xff;
+}
+
+int orion_pcie_link_up(void __iomem *base)
+{
+        return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
+}
+
+int orion_pcie_get_local_bus_nr(void __iomem *base)
+{
+        u32 stat = readl(base + PCIE_STAT_OFF);
+
+        return (stat >> PCIE_STAT_BUS_OFFS) & PCIE_STAT_BUS_MASK;
+}
+
+void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
+{
+        u32 stat;
+
+        stat = readl(base + PCIE_STAT_OFF);
+        stat &= ~(PCIE_STAT_BUS_MASK << PCIE_STAT_BUS_OFFS);
+        stat |= nr << PCIE_STAT_BUS_OFFS;
+        writel(stat, base + PCIE_STAT_OFF);
+}
+
+/*
+ * Setup PCIE BARs and Address Decode Wins:
+ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
+ * WIN[0-3] -> DRAM bank[0-3]
+ */
+static void __init orion_pcie_setup_wins(void __iomem *base,
+                                         struct mbus_dram_target_info *dram)
+{
+        u32 size;
+        int i;
+
+        /*
+         * First, disable and clear BARs and windows.
+         */
+        for (i = 1; i <= 2; i++) {
+                writel(0, base + PCIE_BAR_CTRL_OFF(i));
+                writel(0, base + PCIE_BAR_LO_OFF(i));
+                writel(0, base + PCIE_BAR_HI_OFF(i));
+        }
+
+        for (i = 0; i < 5; i++) {
+                writel(0, base + PCIE_WIN04_CTRL_OFF(i));
+                writel(0, base + PCIE_WIN04_BASE_OFF(i));
+                writel(0, base + PCIE_WIN04_REMAP_OFF(i));
+        }
+
+        writel(0, base + PCIE_WIN5_CTRL_OFF);
+        writel(0, base + PCIE_WIN5_BASE_OFF);
+        writel(0, base + PCIE_WIN5_REMAP_OFF);
+
+        /*
+         * Setup windows for DDR banks.  Count total DDR size on the fly.
+         */
+        size = 0;
+        for (i = 0; i < dram->num_cs; i++) {
+                struct mbus_dram_window *cs = dram->cs + i;
+
+                writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
+                writel(0, base + PCIE_WIN04_REMAP_OFF(i));
+                writel(((cs->size - 1) & 0xffff0000) |
+                        (cs->mbus_attr << 8) |
+                        (dram->mbus_dram_target_id << 4) | 1,
+                                base + PCIE_WIN04_CTRL_OFF(i));
+
+                size += cs->size;
+        }
+
+        /*
+         * Setup BAR[1] to all DRAM banks.
+         */
+        writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1));
+        writel(0, base + PCIE_BAR_HI_OFF(1));
+        writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1));
+}
+
+void __init orion_pcie_setup(void __iomem *base,
+                             struct mbus_dram_target_info *dram)
+{
+        u16 cmd;
+        u32 mask;
+
+        /*
+         * Point PCIe unit MBUS decode windows to DRAM space.
+         */
+        orion_pcie_setup_wins(base, dram);
+
+        /*
+         * Master + slave enable.
+         */
+        cmd = readw(base + PCIE_CMD_OFF);
+        cmd |= PCI_COMMAND_IO;
+        cmd |= PCI_COMMAND_MEMORY;
+        cmd |= PCI_COMMAND_MASTER;
+        writew(cmd, base + PCIE_CMD_OFF);
+
+        /*
+         * Enable interrupt lines A-D.
+         */
+        mask = readl(base + PCIE_MASK_OFF);
+        mask |= 0x0f000000;
+        writel(mask, base + PCIE_MASK_OFF);
+}
+
+int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
+                       u32 devfn, int where, int size, u32 *val)
+{
+        writel(PCIE_CONF_BUS(bus->number) |
+                PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+                PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+                PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
+                        base + PCIE_CONF_ADDR_OFF);
+
+        *val = readl(base + PCIE_CONF_DATA_OFF);
+
+        if (size == 1)
+                *val = (*val >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
+                           u32 devfn, int where, int size, u32 *val)
+{
+        writel(PCIE_CONF_BUS(bus->number) |
+                PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+                PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+                PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
+                        base + PCIE_CONF_ADDR_OFF);
+
+        *val = readl(base + PCIE_CONF_DATA_OFF);
+
+        if (bus->number != orion_pcie_get_local_bus_nr(base) ||
+            PCI_FUNC(devfn) != 0)
+                *val = readl(base + PCIE_HEADER_LOG_4_OFF);
+
+        if (size == 1)
+                *val = (*val >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
+                          u32 devfn, int where, int size, u32 *val)
+{
+        *val = readl(wa_base + (PCIE_CONF_BUS(bus->number) |
+                                PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+                                PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+                                PCIE_CONF_REG(where)));
+
+        if (size == 1)
+                *val = (*val >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
+                       u32 devfn, int where, int size, u32 val)
+{
+        int ret = PCIBIOS_SUCCESSFUL;
+
+        writel(PCIE_CONF_BUS(bus->number) |
+                PCIE_CONF_DEV(PCI_SLOT(devfn)) |
+                PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
+                PCIE_CONF_REG(where) | PCIE_CONF_ADDR_EN,
+                        base + PCIE_CONF_ADDR_OFF);
+
+        if (size == 4) {
+                writel(val, base + PCIE_CONF_DATA_OFF);
+        } else if (size == 2) {
+                writew(val, base + PCIE_CONF_DATA_OFF + (where & 3));
+        } else if (size == 1) {
+                writeb(val, base + PCIE_CONF_DATA_OFF + (where & 3));
+        } else {
+                ret = PCIBIOS_BAD_REGISTER_NUMBER;
+        }
+
+        return ret;
+}
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
new file mode 100644
index 000000000000..28b5285446e8
--- /dev/null
+++ b/arch/arm/plat-orion/time.c
@@ -0,0 +1,203 @@
+/*
+ * arch/arm/plat-orion/time.c
+ *
+ * Marvell Orion SoC timer handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Timer 0 is used as free-running clocksource, while timer 1 is
+ * used as clock_event_device.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/mach/time.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * Number of timer ticks per jiffy.
+ */
+static u32 ticks_per_jiffy;
+
+
+/*
+ * Timer block registers.
+ */
+#define TIMER_CTRL              (TIMER_VIRT_BASE + 0x0000)
+#define  TIMER0_EN              0x0001
+#define  TIMER0_RELOAD_EN       0x0002
+#define  TIMER1_EN              0x0004
+#define  TIMER1_RELOAD_EN       0x0008
+#define TIMER0_RELOAD           (TIMER_VIRT_BASE + 0x0010)
+#define TIMER0_VAL              (TIMER_VIRT_BASE + 0x0014)
+#define TIMER1_RELOAD           (TIMER_VIRT_BASE + 0x0018)
+#define TIMER1_VAL              (TIMER_VIRT_BASE + 0x001c)
+
+
+/*
+ * Clocksource handling.
+ */
+static cycle_t orion_clksrc_read(void)
+{
+        return 0xffffffff - readl(TIMER0_VAL);
+}
+
+static struct clocksource orion_clksrc = {
+        .name           = "orion_clocksource",
+        .shift          = 20,
+        .rating         = 300,
+        .read           = orion_clksrc_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+
+
+/*
+ * Clockevent handling.
+ */
+static int
+orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
+{
+        unsigned long flags;
+        u32 u;
+
+        if (delta == 0)
+                return -ETIME;
+
+        local_irq_save(flags);
+
+        /*
+         * Clear and enable clockevent timer interrupt.
+         */
+        writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+
+        u = readl(BRIDGE_MASK);
+        u |= BRIDGE_INT_TIMER1;
+        writel(u, BRIDGE_MASK);
+
+        /*
+         * Setup new clockevent timer value.
+         */
+        writel(delta, TIMER1_VAL);
+
+        /*
+         * Enable the timer.
+         */
+        u = readl(TIMER_CTRL);
+        u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
+        writel(u, TIMER_CTRL);
+
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static void
+orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
+{
+        unsigned long flags;
+        u32 u;
+
+        local_irq_save(flags);
+        if (mode == CLOCK_EVT_MODE_PERIODIC) {
+                /*
+                 * Setup timer to fire at 1/HZ intervals.
+                 */
+                writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
+                writel(ticks_per_jiffy - 1, TIMER1_VAL);
+
+                /*
+                 * Enable timer interrupt.
+                 */
+                u = readl(BRIDGE_MASK);
+                writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);
+
+                /*
+                 * Enable timer.
+                 */
+                u = readl(TIMER_CTRL);
+                writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
+        } else {
+                /*
+                 * Disable timer.
+                 */
+                u = readl(TIMER_CTRL);
+                writel(u & ~TIMER1_EN, TIMER_CTRL);
+
+                /*
+                 * Disable timer interrupt.
+                 */
+                u = readl(BRIDGE_MASK);
+                writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
+
+                /*
+                 * ACK pending timer interrupt.
+                 */
+                writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+
+        }
+        local_irq_restore(flags);
+}
+
+static struct clock_event_device orion_clkevt = {
+        .name           = "orion_tick",
+        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+        .shift          = 32,
+        .rating         = 300,
+        .cpumask        = CPU_MASK_CPU0,
+        .set_next_event = orion_clkevt_next_event,
+        .set_mode       = orion_clkevt_mode,
+};
+
+static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
+{
+        /*
+         * ACK timer interrupt and call event handler.
+         */
+        writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
+        orion_clkevt.event_handler(&orion_clkevt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction orion_timer_irq = {
+        .name           = "orion_tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .handler        = orion_timer_interrupt
+};
+
+void __init orion_time_init(unsigned int irq, unsigned int tclk)
+{
+        u32 u;
+
+        ticks_per_jiffy = (tclk + HZ/2) / HZ;
+
+
+        /*
+         * Setup free-running clocksource timer (interrupts
+         * disabled.)
+         */
+        writel(0xffffffff, TIMER0_VAL);
+        writel(0xffffffff, TIMER0_RELOAD);
+        u = readl(BRIDGE_MASK);
+        writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
+        u = readl(TIMER_CTRL);
+        writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
+        orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
+        clocksource_register(&orion_clksrc);
+
+
+        /*
+         * Setup clockevent timer (interrupt-driven.)
+         */
+        setup_irq(irq, &orion_timer_irq);
+        orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
+        orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
+        orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
+        clockevents_register_device(&orion_clkevt);
+}
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 7ed58c0c24c2..207a8b5a0c4a 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Sat Jan 26 14:45:34 2008
+# Last update: Sat Apr 19 11:23:38 2008
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -381,13 +381,13 @@ ks8695p			ARCH_KS8695P		KS8695P			363
 se4000                  ARCH_SE4000             SE4000                  364
 quadriceps              ARCH_QUADRICEPS         QUADRICEPS              365
 bronco                  ARCH_BRONCO             BRONCO                  366
-esl_wireless_tab        ARCH_ESL_WIRELESS_TABLETESL_WIRELESS_TABLET     367
+esl_wireless_tab        ARCH_ESL_WIRELESS_TAB   ESL_WIRELESS_TAB        367
 esl_sofcomp             ARCH_ESL_SOFCOMP        ESL_SOFCOMP             368
 s5c7375                 ARCH_S5C7375            S5C7375                 369
 spearhead               ARCH_SPEARHEAD          SPEARHEAD               370
 pantera                 ARCH_PANTERA            PANTERA                 371
 prayoglite              ARCH_PRAYOGLITE         PRAYOGLITE              372
-gumstix                 ARCH_GUMSTIK            GUMSTIK                 373
+gumstix                 ARCH_GUMSTIX            GUMSTIX                 373
 rcube                   ARCH_RCUBE              RCUBE                   374
 rea_olv                 ARCH_REA_OLV            REA_OLV                 375
 pxa_iphone              ARCH_PXA_IPHONE         PXA_IPHONE              376
@@ -1463,7 +1463,7 @@ artemis			MACH_ARTEMIS		ARTEMIS			1462
 htctitan                MACH_HTCTITAN           HTCTITAN                1463
 qranium                 MACH_QRANIUM            QRANIUM                 1464
 adx_wsc2                MACH_ADX_WSC2           ADX_WSC2                1465
-adx_medinet             MACH_ADX_MEDINET        ADX_MEDINET             1466
+adx_medcom              MACH_ADX_MEDINET        ADX_MEDINET             1466
 bboard                  MACH_BBOARD             BBOARD                  1467
 cambria                 MACH_CAMBRIA            CAMBRIA                 1468
 mt7xxx                  MACH_MT7XXX             MT7XXX                  1469
@@ -1611,3 +1611,112 @@ kb9263			MACH_KB9263		KB9263			1612
 mt7108                  MACH_MT7108             MT7108                  1613
 smtr2440                MACH_SMTR2440           SMTR2440                1614
 manao                   MACH_MANAO              MANAO                   1615
+cm_x300                 MACH_CM_X300            CM_X300                 1616
+gulfstream_kp           MACH_GULFSTREAM_KP      GULFSTREAM_KP           1617
+lanreadyfn522           MACH_LANREADYFN522      LANREADYFN522           1618
+arma37                  MACH_ARMA37             ARMA37                  1619
+mendel                  MACH_MENDEL             MENDEL                  1620
+pelco_iliad             MACH_PELCO_ILIAD        PELCO_ILIAD             1621
+unit2p                  MACH_UNIT2P             UNIT2P                  1622
+inc20otter              MACH_INC20OTTER         INC20OTTER              1623
+at91sam9g20ek           MACH_AT91SAM9G20EK      AT91SAM9G20EK           1624
+sc_ge2                  MACH_STORCENTER         STORCENTER              1625
+smdk6410                MACH_SMDK6410           SMDK6410                1626
+u300                    MACH_U300               U300                    1627
+u500                    MACH_U500               U500                    1628
+ds9260                  MACH_DS9260             DS9260                  1629
+riverrock               MACH_RIVERROCK          RIVERROCK               1630
+scibath                 MACH_SCIBATH            SCIBATH                 1631
+at91sam7se              MACH_AT91SAM7SE512EK    AT91SAM7SE512EK         1632
+wrt350n_v2              MACH_WRT350N_V2         WRT350N_V2              1633
+multimedia              MACH_MULTIMEDIA         MULTIMEDIA              1634
+marvin                  MACH_MARVIN             MARVIN                  1635
+x500                    MACH_X500               X500                    1636
+awlug4lcu               MACH_AWLUG4LCU          AWLUG4LCU               1637
+palermoc                MACH_PALERMOC           PALERMOC                1638
+omap_ldp                MACH_OMAP_LDP           OMAP_LDP                1639
+ip500                   MACH_IP500              IP500                   1640
+mx35ads                 MACH_MACH_MX35ADS       MACH_MX35ADS            1641
+ase2                    MACH_ASE2               ASE2                    1642
+mx35evb                 MACH_MX35EVB            MX35EVB                 1643
+aml_m8050               MACH_AML_M8050          AML_M8050               1644
+mx35_3ds                MACH_MX35_3DS           MX35_3DS                1645
+mars                    MACH_MARS               MARS                    1646
+ntosd_644xa             MACH_NTOSD_644XA        NTOSD_644XA             1647
+badger                  MACH_BADGER             BADGER                  1648
+trizeps4wl              MACH_TRIZEPS4WL         TRIZEPS4WL              1649
+trizeps5                MACH_TRIZEPS5           TRIZEPS5                1650
+marlin                  MACH_MARLIN             MARLIN                  1651
+ts7800                  MACH_TS7800             TS7800                  1652
+hpipaq214               MACH_HPIPAQ214          HPIPAQ214               1653
+at572d940dcm            MACH_AT572D940DCM       AT572D940DCM            1654
+ne1board                MACH_NE1BOARD           NE1BOARD                1655
+zante                   MACH_ZANTE              ZANTE                   1656
+sffsdr                  MACH_SFFSDR             SFFSDR                  1657
+tw2662                  MACH_TW2662             TW2662                  1658
+vf10xx                  MACH_VF10XX             VF10XX                  1659
+zoran43xx               MACH_ZORAN43XX          ZORAN43XX               1660
+sonix926                MACH_SONIX926           SONIX926                1661
+celestialsemi           MACH_CELESTIALSEMI      CELESTIALSEMI           1662
+cc9m2443                MACH_CC9M2443           CC9M2443                1663
+tw5334                  MACH_TW5334             TW5334                  1664
+omap_htcartemis         MACH_HTCARTEMIS         HTCARTEMIS              1665
+nal_hlite               MACH_NAL_HLITE          NAL_HLITE               1666
+htcvogue                MACH_HTCVOGUE           HTCVOGUE                1667
+smartweb                MACH_SMARTWEB           SMARTWEB                1668
+mv86xx                  MACH_MV86XX             MV86XX                  1669
+mv87xx                  MACH_MV87XX             MV87XX                  1670
+songyoungho             MACH_SONGYOUNGHO        SONGYOUNGHO             1671
+younghotema             MACH_YOUNGHOTEMA        YOUNGHOTEMA             1672
+pcm037                  MACH_PCM037             PCM037                  1673
+mmvp                    MACH_MMVP               MMVP                    1674
+mmap                    MACH_MMAP               MMAP                    1675
+ptid2410                MACH_PTID2410           PTID2410                1676
+james_926               MACH_JAMES_926          JAMES_926               1677
+fm6000                  MACH_FM6000             FM6000                  1678
+db88f6281_bp            MACH_DB88F6281_BP       DB88F6281_BP            1680
+rd88f6192_nas           MACH_RD88F6192_NAS      RD88F6192_NAS           1681
+rd88f6281               MACH_RD88F6281          RD88F6281               1682
+db78x00_bp              MACH_DB78X00_BP         DB78X00_BP              1683
+smdk2416                MACH_SMDK2416           SMDK2416                1685
+oce_spider_si           MACH_OCE_SPIDER_SI      OCE_SPIDER_SI           1686
+oce_spider_sk           MACH_OCE_SPIDER_SK      OCE_SPIDER_SK           1687
+rovern6                 MACH_ROVERN6            ROVERN6                 1688
+pelco_evolution         MACH_PELCO_EVOLUTION    PELCO_EVOLUTION         1689
+wbd111                  MACH_WBD111             WBD111                  1690
+elaracpe                MACH_ELARACPE           ELARACPE                1691
+mabv3                   MACH_MABV3              MABV3                   1692
+mv2120                  MACH_MV2120             MV2120                  1693
+csb737                  MACH_CSB737             CSB737                  1695
+mx51_3ds                MACH_MX51_3DS           MX51_3DS                1696
+g900                    MACH_G900               G900                    1697
+apf27                   MACH_APF27              APF27                   1698
+ggus2000                MACH_GGUS2000           GGUS2000                1699
+omap_2430_mimic         MACH_OMAP_2430_MIMIC    OMAP_2430_MIMIC         1700
+imx27lite               MACH_IMX27LITE          IMX27LITE               1701
+almex                   MACH_ALMEX              ALMEX                   1702
+control                 MACH_CONTROL            CONTROL                 1703
+mba2410                 MACH_MBA2410            MBA2410                 1704
+volcano                 MACH_VOLCANO            VOLCANO                 1705
+zenith                  MACH_ZENITH             ZENITH                  1706
+muchip                  MACH_MUCHIP             MUCHIP                  1707
+magellan                MACH_MAGELLAN           MAGELLAN                1708
+usb_a9260               MACH_USB_A9260          USB_A9260               1709
+usb_a9263               MACH_USB_A9263          USB_A9263               1710
+qil_a9260               MACH_QIL_A9260          QIL_A9260               1711
+cme9210                 MACH_CME9210            CME9210                 1712
+hczh4                   MACH_HCZH4              HCZH4                   1713
+spearbasic              MACH_SPEARBASIC         SPEARBASIC              1714
+dep2440                 MACH_DEP2440            DEP2440                 1715
+hdl_gxr                 MACH_HDL_GXR            HDL_GXR                 1716
+hdl_gt                  MACH_HDL_GT             HDL_GT                  1717
+hdl_4g                  MACH_HDL_4G             HDL_4G                  1718
+s3c6000                 MACH_S3C6000            S3C6000                 1719
+mmsp2_mdk               MACH_MMSP2_MDK          MMSP2_MDK               1720
+mpx220                  MACH_MPX220             MPX220                  1721
+kzm_arm11_01            MACH_KZM_ARM11_01       KZM_ARM11_01            1722
+htc_polaris             MACH_HTC_POLARIS        HTC_POLARIS             1723
+htc_kaiser              MACH_HTC_KAISER         HTC_KAISER              1724
+lg_ks20                 MACH_LG_KS20            LG_KS20                 1725
+hhgps                   MACH_HHGPS              HHGPS                   1726
+nokia_n810_wimax        MACH_NOKIA_N810_WIMAX   NOKIA_N810_WIMAX        1727
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 6ebebde8454a..83584b6e1ba5 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -74,6 +74,7 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
+#include <linux/mbus.h>
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_cmnd.h>
 #include <scsi/scsi_device.h>
@@ -352,6 +353,9 @@ enum {
 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
 #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
 
+#define WINDOW_CTRL(i)          (0x20030 + ((i) << 4))
+#define WINDOW_BASE(i)          (0x20034 + ((i) << 4))
+
 enum {
         /* DMA boundary 0xffff is required by the s/g splitting
          * we need on /length/ in mv_fill-sg().
@@ -2897,6 +2901,27 @@ static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
         return 0;
 }
 
+static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
+                                 struct mbus_dram_target_info *dram)
+{
+        int i;
+
+        for (i = 0; i < 4; i++) {
+                writel(0, hpriv->base + WINDOW_CTRL(i));
+                writel(0, hpriv->base + WINDOW_BASE(i));
+        }
+
+        for (i = 0; i < dram->num_cs; i++) {
+                struct mbus_dram_window *cs = dram->cs + i;
+
+                writel(((cs->size - 1) & 0xffff0000) |
+                        (cs->mbus_attr << 8) |
+                        (dram->mbus_dram_target_id << 4) | 1,
+                        hpriv->base + WINDOW_CTRL(i));
+                writel(cs->base, hpriv->base + WINDOW_BASE(i));
+        }
+}
+
 /**
  *      mv_platform_probe - handle a positive probe of an soc Marvell
  *      host
@@ -2951,6 +2976,12 @@ static int mv_platform_probe(struct platform_device *pdev)
                                    res->end - res->start + 1);
         hpriv->base -= MV_SATAHC0_REG_BASE;
 
+        /*
+         * (Re-)program MBUS remapping windows if we are asked to.
+         */
+        if (mv_platform_data->dram != NULL)
+                mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
+
         rc = mv_create_dma_pools(hpriv, &pdev->dev);
         if (rc)
                 return rc;
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 5fa9c3c67e0c..b04c99580d0d 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -645,7 +645,7 @@ config I2C_PCA_ISA
 
 config I2C_MV64XXX
         tristate "Marvell mv64xxx I2C Controller"
-        depends on (MV64X60 || ARCH_ORION) && EXPERIMENTAL
+        depends on (MV64X60 || PLAT_ORION) && EXPERIMENTAL
         help
           If you say yes to this option, support will be included for the
           built-in I2C interface on the Marvell 64xxx line of host bridges.
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 2d2087ad708f..6fd2d6a84eff 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -39,6 +39,7 @@
 #include <asm/io.h>
 #include <asm/arch/i2c.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 
 struct pxa_i2c {
         spinlock_t              lock;
diff --git a/drivers/input/keyboard/corgikbd.c b/drivers/input/keyboard/corgikbd.c
index 790fed368aae..5d6cc7f1dc94 100644
--- a/drivers/input/keyboard/corgikbd.c
+++ b/drivers/input/keyboard/corgikbd.c
@@ -23,6 +23,7 @@
 #include <asm/arch/corgi.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/hardware/scoop.h>
 
 #define KB_ROWS                         8
diff --git a/drivers/input/keyboard/spitzkbd.c b/drivers/input/keyboard/spitzkbd.c
index 1d59a2dc3c17..0be74bfc58fe 100644
--- a/drivers/input/keyboard/spitzkbd.c
+++ b/drivers/input/keyboard/spitzkbd.c
@@ -23,6 +23,7 @@
 #include <asm/arch/spitz.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 
 #define KB_ROWS                 7
 #define KB_COLS                 11
diff --git a/drivers/input/touchscreen/corgi_ts.c b/drivers/input/touchscreen/corgi_ts.c
index 99d92f5c93d6..a22576779acd 100644
--- a/drivers/input/touchscreen/corgi_ts.c
+++ b/drivers/input/touchscreen/corgi_ts.c
@@ -22,6 +22,7 @@
 #include <asm/arch/sharpsl.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 
 
 #define PWR_MODE_ACTIVE         0
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 859814f62cb0..a3a6199639f9 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -46,13 +46,6 @@ config LEDS_SPITZ
           This option enables support for the LEDs on Sharp Zaurus
           SL-Cxx00 series (C1000, C3000, C3100).
 
-config LEDS_TOSA
-        tristate "LED Support for the Sharp SL-6000 series"
-        depends on LEDS_CLASS && PXA_SHARPSL
-        help
-          This option enables support for the LEDs on Sharp Zaurus
-          SL-6000 series.
-
 config LEDS_S3C24XX
         tristate "LED Support for Samsung S3C24XX GPIO LEDs"
         depends on LEDS_CLASS && ARCH_S3C2410
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 84ced3b1a13d..e54f42da21a2 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -9,7 +9,6 @@ obj-$(CONFIG_LEDS_ATMEL_PWM)		+= leds-atmel-pwm.o
 obj-$(CONFIG_LEDS_CORGI)                += leds-corgi.o
 obj-$(CONFIG_LEDS_LOCOMO)               += leds-locomo.o
 obj-$(CONFIG_LEDS_SPITZ)                += leds-spitz.o
-obj-$(CONFIG_LEDS_TOSA)                 += leds-tosa.o
 obj-$(CONFIG_LEDS_S3C24XX)              += leds-s3c24xx.o
 obj-$(CONFIG_LEDS_AMS_DELTA)            += leds-ams-delta.o
 obj-$(CONFIG_LEDS_NET48XX)              += leds-net48xx.o
diff --git a/drivers/leds/leds-tosa.c b/drivers/leds/leds-tosa.c
deleted file mode 100644
index 9e0a188fbb0a..000000000000
--- a/drivers/leds/leds-tosa.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * LED Triggers Core
- *
- * Copyright 2005 Dirk Opfer
- *
- * Author: Dirk Opfer <Dirk@Opfer-Online.de>
- *      based on spitz.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/leds.h>
-#include <asm/hardware/scoop.h>
-#include <asm/mach-types.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pxa-regs.h>
-#include <asm/arch/tosa.h>
-
-static void tosaled_amber_set(struct led_classdev *led_cdev,
-                                enum led_brightness value)
-{
-        if (value)
-                set_scoop_gpio(&tosascoop_jc_device.dev,
-                                TOSA_SCOOP_JC_CHRG_ERR_LED);
-        else
-                reset_scoop_gpio(&tosascoop_jc_device.dev,
-                                TOSA_SCOOP_JC_CHRG_ERR_LED);
-}
-
-static void tosaled_green_set(struct led_classdev *led_cdev,
-                                enum led_brightness value)
-{
-        if (value)
-                set_scoop_gpio(&tosascoop_jc_device.dev,
-                                TOSA_SCOOP_JC_NOTE_LED);
-        else
-                reset_scoop_gpio(&tosascoop_jc_device.dev,
-                                TOSA_SCOOP_JC_NOTE_LED);
-}
-
-static struct led_classdev tosa_amber_led = {
-        .name                   = "tosa:amber:charge",
-        .default_trigger        = "sharpsl-charge",
-        .brightness_set         = tosaled_amber_set,
-};
-
-static struct led_classdev tosa_green_led = {
-        .name                   = "tosa:green:mail",
-        .default_trigger        = "nand-disk",
-        .brightness_set         = tosaled_green_set,
-};
-
-#ifdef CONFIG_PM
-static int tosaled_suspend(struct platform_device *dev, pm_message_t state)
-{
-#ifdef CONFIG_LEDS_TRIGGERS
-        if (tosa_amber_led.trigger && strcmp(tosa_amber_led.trigger->name,
-                                                "sharpsl-charge"))
-#endif
-                led_classdev_suspend(&tosa_amber_led);
-        led_classdev_suspend(&tosa_green_led);
-        return 0;
-}
-
-static int tosaled_resume(struct platform_device *dev)
-{
-        led_classdev_resume(&tosa_amber_led);
-        led_classdev_resume(&tosa_green_led);
-        return 0;
-}
-#else
-#define tosaled_suspend NULL
-#define tosaled_resume NULL
-#endif
-
-static int tosaled_probe(struct platform_device *pdev)
-{
-        int ret;
-
-        ret = led_classdev_register(&pdev->dev, &tosa_amber_led);
-        if (ret < 0)
-                return ret;
-
-        ret = led_classdev_register(&pdev->dev, &tosa_green_led);
-        if (ret < 0)
-                led_classdev_unregister(&tosa_amber_led);
-
-        return ret;
-}
-
-static int tosaled_remove(struct platform_device *pdev)
-{
-        led_classdev_unregister(&tosa_amber_led);
-        led_classdev_unregister(&tosa_green_led);
-
-        return 0;
-}
-
-static struct platform_driver tosaled_driver = {
-        .probe          = tosaled_probe,
-        .remove         = tosaled_remove,
-        .suspend        = tosaled_suspend,
-        .resume         = tosaled_resume,
-        .driver         = {
-                .name           = "tosa-led",
-        },
-};
-
-static int __init tosaled_init(void)
-{
-        return platform_driver_register(&tosaled_driver);
-}
-
-static void __exit tosaled_exit(void)
-{
-        platform_driver_unregister(&tosaled_driver);
-}
-
-module_init(tosaled_init);
-module_exit(tosaled_exit);
-
-MODULE_AUTHOR("Dirk Opfer <Dirk@Opfer-Online.de>");
-MODULE_DESCRIPTION("Tosa LED driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 0c886c882385..2566479937c9 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -22,6 +22,22 @@ config MFD_ASIC3
           This driver supports the ASIC3 multifunction chip found on many
           PDAs (mainly iPAQ and HTC based ones)
 
+config HTC_EGPIO
+        bool "HTC EGPIO support"
+        depends on GENERIC_HARDIRQS && HAVE_GPIO_LIB
+        help
+            This driver supports the CPLD egpio chip present on
+            several HTC phones.  It provides basic support for input
+            pins, output pins, and irqs.
+
+config HTC_PASIC3
+        tristate "HTC PASIC3 LED/DS1WM chip support"
+        help
+          This core driver provides register access for the LED/DS1WM
+          chips labeled "AIC2" and "AIC3", found on HTC Blueangel and
+          HTC Magician devices, respectively. Actual functionality is
+          handled by the leds-pasic3 and ds1wm drivers.
+
 endmenu
 
 menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 521cd5cb68af..eef4e26807df 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -5,6 +5,9 @@
 obj-$(CONFIG_MFD_SM501)         += sm501.o
 obj-$(CONFIG_MFD_ASIC3)         += asic3.o
 
+obj-$(CONFIG_HTC_EGPIO)         += htc-egpio.o
+obj-$(CONFIG_HTC_PASIC3)        += htc-pasic3.o
+
 obj-$(CONFIG_MCP)               += mcp-core.o
 obj-$(CONFIG_MCP_SA11X0)        += mcp-sa11x0.o
 obj-$(CONFIG_MCP_UCB1200)       += ucb1x00-core.o
diff --git a/drivers/mfd/htc-egpio.c b/drivers/mfd/htc-egpio.c
new file mode 100644
index 000000000000..8872cc077519
--- /dev/null
+++ b/drivers/mfd/htc-egpio.c
@@ -0,0 +1,440 @@
+/*
+ * Support for the GPIO/IRQ expander chips present on several HTC phones.
+ * These are implemented in CPLD chips present on the board.
+ *
+ * Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
+ * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This file may be distributed under the terms of the GNU GPL license.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/mfd/htc-egpio.h>
+
+struct egpio_chip {
+        int              reg_start;
+        int              cached_values;
+        unsigned long    is_out;
+        struct device    *dev;
+        struct gpio_chip chip;
+};
+
+struct egpio_info {
+        spinlock_t        lock;
+
+        /* iomem info */
+        void __iomem      *base_addr;
+        int               bus_shift;    /* byte shift */
+        int               reg_shift;    /* bit shift */
+        int               reg_mask;
+
+        /* irq info */
+        int               ack_register;
+        int               ack_write;
+        u16               irqs_enabled;
+        uint              irq_start;
+        int               nirqs;
+        uint              chained_irq;
+
+        /* egpio info */
+        struct egpio_chip *chip;
+        int               nchips;
+};
+
+static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
+{
+        writew(value, ei->base_addr + (reg << ei->bus_shift));
+}
+
+static inline u16 egpio_readw(struct egpio_info *ei, int reg)
+{
+        return readw(ei->base_addr + (reg << ei->bus_shift));
+}
+
+/*
+ * IRQs
+ */
+
+static inline void ack_irqs(struct egpio_info *ei)
+{
+        egpio_writew(ei->ack_write, ei, ei->ack_register);
+        pr_debug("EGPIO ack - write %x to base+%x\n",
+                        ei->ack_write, ei->ack_register << ei->bus_shift);
+}
+
+static void egpio_ack(unsigned int irq)
+{
+}
+
+/* There does not appear to be a way to proactively mask interrupts
+ * on the egpio chip itself.  So, we simply ignore interrupts that
+ * aren't desired. */
+static void egpio_mask(unsigned int irq)
+{
+        struct egpio_info *ei = get_irq_chip_data(irq);
+        ei->irqs_enabled &= ~(1 << (irq - ei->irq_start));
+        pr_debug("EGPIO mask %d %04x\n", irq, ei->irqs_enabled);
+}
+static void egpio_unmask(unsigned int irq)
+{
+        struct egpio_info *ei = get_irq_chip_data(irq);
+        ei->irqs_enabled |= 1 << (irq - ei->irq_start);
+        pr_debug("EGPIO unmask %d %04x\n", irq, ei->irqs_enabled);
+}
+
+static struct irq_chip egpio_muxed_chip = {
+        .name   = "htc-egpio",
+        .ack    = egpio_ack,
+        .mask   = egpio_mask,
+        .unmask = egpio_unmask,
+};
+
+static void egpio_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct egpio_info *ei = get_irq_data(irq);
+        int irqpin;
+
+        /* Read current pins. */
+        unsigned long readval = egpio_readw(ei, ei->ack_register);
+        pr_debug("IRQ reg: %x\n", (unsigned int)readval);
+        /* Ack/unmask interrupts. */
+        ack_irqs(ei);
+        /* Process all set pins. */
+        readval &= ei->irqs_enabled;
+        for_each_bit(irqpin, &readval, ei->nirqs) {
+                /* Run irq handler */
+                pr_debug("got IRQ %d\n", irqpin);
+                irq = ei->irq_start + irqpin;
+                desc = &irq_desc[irq];
+                desc->handle_irq(irq, desc);
+        }
+}
+
+int htc_egpio_get_wakeup_irq(struct device *dev)
+{
+        struct egpio_info *ei = dev_get_drvdata(dev);
+
+        /* Read current pins. */
+        u16 readval = egpio_readw(ei, ei->ack_register);
+        /* Ack/unmask interrupts. */
+        ack_irqs(ei);
+        /* Return first set pin. */
+        readval &= ei->irqs_enabled;
+        return ei->irq_start + ffs(readval) - 1;
+}
+EXPORT_SYMBOL(htc_egpio_get_wakeup_irq);
+
+static inline int egpio_pos(struct egpio_info *ei, int bit)
+{
+        return bit >> ei->reg_shift;
+}
+
+static inline int egpio_bit(struct egpio_info *ei, int bit)
+{
+        return 1 << (bit & ((1 << ei->reg_shift)-1));
+}
+
+/*
+ * Input pins
+ */
+
+static int egpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct egpio_chip *egpio;
+        struct egpio_info *ei;
+        unsigned           bit;
+        int                reg;
+        int                value;
+
+        pr_debug("egpio_get_value(%d)\n", chip->base + offset);
+
+        egpio = container_of(chip, struct egpio_chip, chip);
+        ei    = dev_get_drvdata(egpio->dev);
+        bit   = egpio_bit(ei, offset);
+        reg   = egpio->reg_start + egpio_pos(ei, offset);
+
+        value = egpio_readw(ei, reg);
+        pr_debug("readw(%p + %x) = %x\n",
+                        ei->base_addr, reg << ei->bus_shift, value);
+        return value & bit;
+}
+
+static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct egpio_chip *egpio;
+
+        egpio = container_of(chip, struct egpio_chip, chip);
+        return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
+}
+
+
+/*
+ * Output pins
+ */
+
+static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        unsigned long     flag;
+        struct egpio_chip *egpio;
+        struct egpio_info *ei;
+        unsigned          bit;
+        int               pos;
+        int               reg;
+        int               shift;
+
+        pr_debug("egpio_set(%s, %d(%d), %d)\n",
+                        chip->label, offset, offset+chip->base, value);
+
+        egpio = container_of(chip, struct egpio_chip, chip);
+        ei    = dev_get_drvdata(egpio->dev);
+        bit   = egpio_bit(ei, offset);
+        pos   = egpio_pos(ei, offset);
+        reg   = egpio->reg_start + pos;
+        shift = pos << ei->reg_shift;
+
+        pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
+                        reg, (egpio->cached_values >> shift) & ei->reg_mask);
+
+        spin_lock_irqsave(&ei->lock, flag);
+        if (value)
+                egpio->cached_values |= (1 << offset);
+        else
+                egpio->cached_values &= ~(1 << offset);
+        egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
+        spin_unlock_irqrestore(&ei->lock, flag);
+}
+
+static int egpio_direction_output(struct gpio_chip *chip,
+                                        unsigned offset, int value)
+{
+        struct egpio_chip *egpio;
+
+        egpio = container_of(chip, struct egpio_chip, chip);
+        if (test_bit(offset, &egpio->is_out)) {
+                egpio_set(chip, offset, value);
+                return 0;
+        } else {
+                return -EINVAL;
+        }
+}
+
+static void egpio_write_cache(struct egpio_info *ei)
+{
+        int               i;
+        struct egpio_chip *egpio;
+        int               shift;
+
+        for (i = 0; i < ei->nchips; i++) {
+                egpio = &(ei->chip[i]);
+                if (!egpio->is_out)
+                        continue;
+
+                for (shift = 0; shift < egpio->chip.ngpio;
+                                shift += (1<<ei->reg_shift)) {
+
+                        int reg = egpio->reg_start + egpio_pos(ei, shift);
+
+                        if (!((egpio->is_out >> shift) & ei->reg_mask))
+                                continue;
+
+                        pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
+                                (egpio->cached_values >> shift) & ei->reg_mask,
+                                egpio_readw(ei, reg));
+
+                        egpio_writew((egpio->cached_values >> shift)
+                                        & ei->reg_mask, ei, reg);
+                }
+        }
+}
+
+
+/*
+ * Setup
+ */
+
+static int __init egpio_probe(struct platform_device *pdev)
+{
+        struct htc_egpio_platform_data *pdata = pdev->dev.platform_data;
+        struct resource   *res;
+        struct egpio_info *ei;
+        struct gpio_chip  *chip;
+        unsigned int      irq, irq_end;
+        int               i;
+        int               ret;
+
+        /* Initialize ei data structure. */
+        ei = kzalloc(sizeof(*ei), GFP_KERNEL);
+        if (!ei)
+                return -ENOMEM;
+
+        spin_lock_init(&ei->lock);
+
+        /* Find chained irq */
+        ret = -EINVAL;
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (res)
+                ei->chained_irq = res->start;
+
+        /* Map egpio chip into virtual address space. */
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                goto fail;
+        ei->base_addr = ioremap_nocache(res->start, res->end - res->start);
+        if (!ei->base_addr)
+                goto fail;
+        pr_debug("EGPIO phys=%08x virt=%p\n", res->start, ei->base_addr);
+
+        if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
+                goto fail;
+        ei->bus_shift = fls(pdata->bus_width - 1) - 3;
+        pr_debug("bus_shift = %d\n", ei->bus_shift);
+
+        if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
+                goto fail;
+        ei->reg_shift = fls(pdata->reg_width - 1);
+        pr_debug("reg_shift = %d\n", ei->reg_shift);
+
+        ei->reg_mask = (1 << pdata->reg_width) - 1;
+
+        platform_set_drvdata(pdev, ei);
+
+        ei->nchips = pdata->num_chips;
+        ei->chip = kzalloc(sizeof(struct egpio_chip) * ei->nchips, GFP_KERNEL);
+        if (!ei) {
+                ret = -ENOMEM;
+                goto fail;
+        }
+        for (i = 0; i < ei->nchips; i++) {
+                ei->chip[i].reg_start = pdata->chip[i].reg_start;
+                ei->chip[i].cached_values = pdata->chip[i].initial_values;
+                ei->chip[i].is_out = pdata->chip[i].direction;
+                ei->chip[i].dev = &(pdev->dev);
+                chip = &(ei->chip[i].chip);
+                chip->label           = "htc-egpio";
+                chip->get             = egpio_get;
+                chip->set             = egpio_set;
+                chip->direction_input = egpio_direction_input;
+                chip->direction_output = egpio_direction_output;
+                chip->base            = pdata->chip[i].gpio_base;
+                chip->ngpio           = pdata->chip[i].num_gpios;
+
+                gpiochip_add(chip);
+        }
+
+        /* Set initial pin values */
+        egpio_write_cache(ei);
+
+        ei->irq_start = pdata->irq_base;
+        ei->nirqs = pdata->num_irqs;
+        ei->ack_register = pdata->ack_register;
+
+        if (ei->chained_irq) {
+                /* Setup irq handlers */
+                ei->ack_write = 0xFFFF;
+                if (pdata->invert_acks)
+                        ei->ack_write = 0;
+                irq_end = ei->irq_start + ei->nirqs;
+                for (irq = ei->irq_start; irq < irq_end; irq++) {
+                        set_irq_chip(irq, &egpio_muxed_chip);
+                        set_irq_chip_data(irq, ei);
+                        set_irq_handler(irq, handle_simple_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                }
+                set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
+                set_irq_data(ei->chained_irq, ei);
+                set_irq_chained_handler(ei->chained_irq, egpio_handler);
+                ack_irqs(ei);
+
+                device_init_wakeup(&pdev->dev, 1);
+        }
+
+        return 0;
+
+fail:
+        printk(KERN_ERR "EGPIO failed to setup\n");
+        kfree(ei);
+        return ret;
+}
+
+static int __exit egpio_remove(struct platform_device *pdev)
+{
+        struct egpio_info *ei = platform_get_drvdata(pdev);
+        unsigned int      irq, irq_end;
+
+        if (ei->chained_irq) {
+                irq_end = ei->irq_start + ei->nirqs;
+                for (irq = ei->irq_start; irq < irq_end; irq++) {
+                        set_irq_chip(irq, NULL);
+                        set_irq_handler(irq, NULL);
+                        set_irq_flags(irq, 0);
+                }
+                set_irq_chained_handler(ei->chained_irq, NULL);
+                device_init_wakeup(&pdev->dev, 0);
+        }
+        iounmap(ei->base_addr);
+        kfree(ei->chip);
+        kfree(ei);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
+{
+        struct egpio_info *ei = platform_get_drvdata(pdev);
+
+        if (ei->chained_irq && device_may_wakeup(&pdev->dev))
+                enable_irq_wake(ei->chained_irq);
+        return 0;
+}
+
+static int egpio_resume(struct platform_device *pdev)
+{
+        struct egpio_info *ei = platform_get_drvdata(pdev);
+
+        if (ei->chained_irq && device_may_wakeup(&pdev->dev))
+                disable_irq_wake(ei->chained_irq);
+
+        /* Update registers from the cache, in case
+           the CPLD was powered off during suspend */
+        egpio_write_cache(ei);
+        return 0;
+}
+#else
+#define egpio_suspend NULL
+#define egpio_resume NULL
+#endif
+
+
+static struct platform_driver egpio_driver = {
+        .driver = {
+                .name = "htc-egpio",
+        },
+        .remove       = __exit_p(egpio_remove),
+        .suspend      = egpio_suspend,
+        .resume       = egpio_resume,
+};
+
+static int __init egpio_init(void)
+{
+        return platform_driver_probe(&egpio_driver, egpio_probe);
+}
+
+static void __exit egpio_exit(void)
+{
+        platform_driver_unregister(&egpio_driver);
+}
+
+/* start early for dependencies */
+subsys_initcall(egpio_init);
+module_exit(egpio_exit)
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kevin O'Connor <kevin@koconnor.net>");
diff --git a/drivers/mfd/htc-pasic3.c b/drivers/mfd/htc-pasic3.c
new file mode 100644
index 000000000000..af66f4f28300
--- /dev/null
+++ b/drivers/mfd/htc-pasic3.c
@@ -0,0 +1,265 @@
+/*
+ * Core driver for HTC PASIC3 LED/DS1WM chip.
+ *
+ * Copyright (C) 2006 Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <linux/ds1wm.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/htc-pasic3.h>
+
+#include <asm/arch/pxa-regs.h>
+
+struct pasic3_data {
+        void __iomem *mapping;
+        unsigned int bus_shift;
+        struct platform_device *ds1wm_pdev;
+        struct platform_device *led_pdev;
+};
+
+#define REG_ADDR  5
+#define REG_DATA  6
+#define NUM_REGS  7
+
+#define READ_MODE 0x80
+
+/*
+ * write to a secondary register on the PASIC3
+ */
+void pasic3_write_register(struct device *dev, u32 reg, u8 val)
+{
+        struct pasic3_data *asic = dev->driver_data;
+        int bus_shift = asic->bus_shift;
+        void __iomem *addr = asic->mapping + (REG_ADDR << bus_shift);
+        void __iomem *data = asic->mapping + (REG_DATA << bus_shift);
+
+        __raw_writeb(~READ_MODE & reg, addr);
+        __raw_writeb(val, data);
+}
+EXPORT_SYMBOL(pasic3_write_register); /* for leds-pasic3 */
+
+/*
+ * read from a secondary register on the PASIC3
+ */
+u8 pasic3_read_register(struct device *dev, u32 reg)
+{
+        struct pasic3_data *asic = dev->driver_data;
+        int bus_shift = asic->bus_shift;
+        void __iomem *addr = asic->mapping + (REG_ADDR << bus_shift);
+        void __iomem *data = asic->mapping + (REG_DATA << bus_shift);
+
+        __raw_writeb(READ_MODE | reg, addr);
+        return __raw_readb(data);
+}
+EXPORT_SYMBOL(pasic3_read_register); /* for leds-pasic3 */
+
+/*
+ * LEDs
+ */
+
+static int led_device_add(struct device *pasic3_dev,
+                                const struct pasic3_leds_machinfo *pdata)
+{
+        struct pasic3_data *asic = pasic3_dev->driver_data;
+        struct platform_device *pdev;
+        int ret;
+
+        pdev = platform_device_alloc("pasic3-led", -1);
+        if (!pdev) {
+                dev_dbg(pasic3_dev, "failed to allocate LED platform device\n");
+                return -ENOMEM;
+        }
+
+        ret = platform_device_add_data(pdev, pdata,
+                                        sizeof(struct pasic3_leds_machinfo));
+        if (ret < 0) {
+                dev_dbg(pasic3_dev, "failed to add LED platform data\n");
+                goto exit_pdev_put;
+        }
+
+        pdev->dev.parent = pasic3_dev;
+        ret = platform_device_add(pdev);
+        if (ret < 0) {
+                dev_dbg(pasic3_dev, "failed to add LED platform device\n");
+                goto exit_pdev_put;
+        }
+
+        asic->led_pdev = pdev;
+        return 0;
+
+exit_pdev_put:
+        platform_device_put(pdev);
+        return ret;
+}
+
+/*
+ * DS1WM
+ */
+
+static void ds1wm_enable(struct platform_device *pdev)
+{
+        struct device *dev = pdev->dev.parent;
+        int c;
+
+        c = pasic3_read_register(dev, 0x28);
+        pasic3_write_register(dev, 0x28, c & 0x7f);
+
+        dev_dbg(dev, "DS1WM OWM_EN low (active) %02x\n", c & 0x7f);
+}
+
+static void ds1wm_disable(struct platform_device *pdev)
+{
+        struct device *dev = pdev->dev.parent;
+        int c;
+
+        c = pasic3_read_register(dev, 0x28);
+        pasic3_write_register(dev, 0x28, c | 0x80);
+
+        dev_dbg(dev, "DS1WM OWM_EN high (inactive) %02x\n", c | 0x80);
+}
+
+static struct ds1wm_platform_data ds1wm_pdata = {
+        .bus_shift = 2,
+        .enable    = ds1wm_enable,
+        .disable   = ds1wm_disable,
+};
+
+static int ds1wm_device_add(struct device *pasic3_dev, int bus_shift)
+{
+        struct pasic3_data *asic = pasic3_dev->driver_data;
+        struct platform_device *pdev;
+        int ret;
+
+        pdev = platform_device_alloc("ds1wm", -1);
+        if (!pdev) {
+                dev_dbg(pasic3_dev, "failed to allocate DS1WM platform device\n");
+                return -ENOMEM;
+        }
+
+        ret = platform_device_add_resources(pdev, pdev->resource,
+                                                pdev->num_resources);
+        if (ret < 0) {
+                dev_dbg(pasic3_dev, "failed to add DS1WM resources\n");
+                goto exit_pdev_put;
+        }
+
+        ds1wm_pdata.bus_shift = asic->bus_shift;
+        ret = platform_device_add_data(pdev, &ds1wm_pdata,
+                                        sizeof(struct ds1wm_platform_data));
+        if (ret < 0) {
+                dev_dbg(pasic3_dev, "failed to add DS1WM platform data\n");
+                goto exit_pdev_put;
+        }
+
+        pdev->dev.parent = pasic3_dev;
+        ret = platform_device_add(pdev);
+        if (ret < 0) {
+                dev_dbg(pasic3_dev, "failed to add DS1WM platform device\n");
+                goto exit_pdev_put;
+        }
+
+        asic->ds1wm_pdev = pdev;
+        return 0;
+
+exit_pdev_put:
+        platform_device_put(pdev);
+        return ret;
+}
+
+static int __init pasic3_probe(struct platform_device *pdev)
+{
+        struct pasic3_platform_data *pdata = pdev->dev.platform_data;
+        struct device *dev = &pdev->dev;
+        struct pasic3_data *asic;
+        struct resource *r;
+        int ret;
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!r)
+                return -ENXIO;
+
+        if (!request_mem_region(r->start, r->end - r->start + 1, "pasic3"))
+                return -EBUSY;
+
+        asic = kzalloc(sizeof(struct pasic3_data), GFP_KERNEL);
+        if (!asic)
+                return -ENOMEM;
+
+        platform_set_drvdata(pdev, asic);
+
+        if (pdata && pdata->bus_shift)
+                asic->bus_shift = pdata->bus_shift;
+        else
+                asic->bus_shift = 2;
+
+        asic->mapping = ioremap(r->start, r->end - r->start + 1);
+        if (!asic->mapping) {
+                dev_err(dev, "couldn't ioremap PASIC3\n");
+                kfree(asic);
+                return -ENOMEM;
+        }
+
+        ret = ds1wm_device_add(dev, asic->bus_shift);
+        if (ret < 0)
+                dev_warn(dev, "failed to register DS1WM\n");
+
+        if (pdata->led_pdata) {
+                ret = led_device_add(dev, pdata->led_pdata);
+                if (ret < 0)
+                        dev_warn(dev, "failed to register LED device\n");
+        }
+
+        return 0;
+}
+
+static int pasic3_remove(struct platform_device *pdev)
+{
+        struct pasic3_data *asic = platform_get_drvdata(pdev);
+        struct resource *r;
+
+        if (asic->led_pdev)
+                platform_device_unregister(asic->led_pdev);
+        if (asic->ds1wm_pdev)
+                platform_device_unregister(asic->ds1wm_pdev);
+
+        iounmap(asic->mapping);
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(r->start, r->end - r->start + 1);
+        kfree(asic);
+        return 0;
+}
+
+static struct platform_driver pasic3_driver = {
+        .driver         = {
+                .name   = "pasic3",
+        },
+        .remove         = pasic3_remove,
+};
+
+static int __init pasic3_base_init(void)
+{
+        return platform_driver_probe(&pasic3_driver, pasic3_probe);
+}
+
+static void __exit pasic3_base_exit(void)
+{
+        platform_driver_unregister(&pasic3_driver);
+}
+
+module_init(pasic3_base_init);
+module_exit(pasic3_base_exit);
+
+MODULE_AUTHOR("Philipp Zabel <philipp.zabel@gmail.com>");
+MODULE_DESCRIPTION("Core driver for HTC PASIC3");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 4a3c6759492b..959fb86cda01 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -314,7 +314,7 @@ config MTD_ALAUDA
 
 config MTD_NAND_ORION
         tristate "NAND Flash support for Marvell Orion SoC"
-        depends on ARCH_ORION && MTD_NAND
+        depends on PLAT_ORION && MTD_NAND
         help
           This enables the NAND flash controller on Orion machines.
 
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c
index 9162cca0182b..ec5ad28b237e 100644
--- a/drivers/mtd/nand/orion_nand.c
+++ b/drivers/mtd/nand/orion_nand.c
@@ -18,8 +18,8 @@
 #include <linux/mtd/partitions.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
-#include <asm/arch/platform.h>
 #include <asm/arch/hardware.h>
+#include <asm/plat-orion/orion_nand.h>
 
 #ifdef CONFIG_MTD_CMDLINE_PARTS
 static const char *part_probes[] = { "cmdlinepart", NULL };
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index fe7b5ec09708..124d29f5fa0c 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2415,7 +2415,7 @@ config UGETH_TX_ON_DEMAND
 
 config MV643XX_ETH
         tristate "Marvell Discovery (643XX) and Orion ethernet support"
-        depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32) || ARCH_ORION
+        depends on MV64360 || MV64X60 || (PPC_MULTIPLATFORM && PPC32) || PLAT_ORION
         select MII
         help
           This driver supports the gigabit ethernet MACs in the
diff --git a/drivers/net/arm/at91_ether.c b/drivers/net/arm/at91_ether.c
index 0ae0d83e5d22..978e20a1791b 100644
--- a/drivers/net/arm/at91_ether.c
+++ b/drivers/net/arm/at91_ether.c
@@ -1043,7 +1043,9 @@ static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_add
         } else if (machine_is_csb337()) {
                 /* mix link activity status into LED2 link state */
                 write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22);
-        }
+        } else if (machine_is_ecbat91())
+                write_phy(phy_address, MII_LEDCTRL_REG, 0x156A);
+
         disable_mdi();
         spin_unlock_irq(&lp->lock);
 
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index 8c09344f58dc..8db71ab20456 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -36,6 +36,7 @@
 #include <asm/hardware.h>
 #include <asm/arch/irda.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 
 #ifdef CONFIG_MACH_MAINSTONE
 #include <asm/arch/mainstone.h>
@@ -831,6 +832,11 @@ static int pxa_irda_probe(struct platform_device *pdev)
         if (err)
                 goto err_mem_5;
 
+        if (si->pdata->startup)
+                err = si->pdata->startup(si->dev);
+        if (err)
+                goto err_startup;
+
         dev->hard_start_xmit    = pxa_irda_hard_xmit;
         dev->open               = pxa_irda_start;
         dev->stop               = pxa_irda_stop;
@@ -856,6 +862,9 @@ static int pxa_irda_probe(struct platform_device *pdev)
                 dev_set_drvdata(&pdev->dev, dev);
 
         if (err) {
+                if (si->pdata->shutdown)
+                        si->pdata->shutdown(si->dev);
+err_startup:
                 kfree(si->tx_buff.head);
 err_mem_5:
                 kfree(si->rx_buff.head);
@@ -881,6 +890,8 @@ static int pxa_irda_remove(struct platform_device *_dev)
         if (dev) {
                 struct pxa_irda *si = netdev_priv(dev);
                 unregister_netdev(dev);
+                if (si->pdata->shutdown)
+                        si->pdata->shutdown(si->dev);
                 kfree(si->tx_buff.head);
                 kfree(si->rx_buff.head);
                 clk_put(si->fir_clk);
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 125e7b7f34ff..f7cb8e0758b4 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -486,12 +486,7 @@ void __ref pci_bus_size_bridges(struct pci_bus *bus)
                 break;
 
         case PCI_CLASS_BRIDGE_PCI:
-                /* don't size subtractive decoding (transparent)
-                 * PCI-to-PCI bridges */
-                if (bus->self->transparent)
-                        break;
                 pci_bridge_check_ranges(bus);
-                /* fall through */
         default:
                 pbus_size_io(bus);
                 /* If the bridge supports prefetchable range, size it
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index 8b22281b087f..ed8c06904807 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -200,6 +200,7 @@ config PCMCIA_AU1X00
 config PCMCIA_SA1100
         tristate "SA1100 support"
         depends on ARM && ARCH_SA1100 && PCMCIA
+        depends on ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL || MACH_ARMCORE
         help
           Say Y here to include support for SA11x0-based PCMCIA or CF
           sockets, found on HP iPAQs, Yopy, and other StrongARM(R)/
diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c
index fbf2f3a6984c..e7ab060ff118 100644
--- a/drivers/pcmcia/pxa2xx_cm_x270.c
+++ b/drivers/pcmcia/pxa2xx_cm_x270.c
@@ -20,6 +20,7 @@
 #include <asm/hardware.h>
 
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/cm-x270.h>
 
 #include "soc_common.h"
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index 56af1f566a4c..cf29a2d0ba4c 100644
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -166,15 +166,6 @@
 #define SERIAL_IMX_MAJOR        204
 #define MINOR_START             41
 
-#define NR_PORTS                2
-
-#define IMX_ISR_PASS_LIMIT      256
-
-/*
- * This is the size of our serial port register set.
- */
-#define UART_PORT_SIZE  0x100
-
 /*
  * This determines how often we check the modem status signals
  * for any change.  They generally aren't connected to an IRQ
@@ -358,66 +349,60 @@ static irqreturn_t imx_rxint(int irq, void *dev_id)
         struct tty_struct *tty = sport->port.info->tty;
         unsigned long flags, temp;
 
-        rx = readl(sport->port.membase + URXD0);
         spin_lock_irqsave(&sport->port.lock,flags);
 
-        do {
+        while (readl(sport->port.membase + USR2) & USR2_RDR) {
                 flg = TTY_NORMAL;
                 sport->port.icount.rx++;
 
+                rx = readl(sport->port.membase + URXD0);
+
                 temp = readl(sport->port.membase + USR2);
-                if( temp & USR2_BRCD ) {
+                if (temp & USR2_BRCD) {
                         writel(temp | USR2_BRCD, sport->port.membase + USR2);
-                        if(uart_handle_break(&sport->port))
-                                goto ignore_char;
+                        if (uart_handle_break(&sport->port))
+                                continue;
                 }
 
                 if (uart_handle_sysrq_char
                             (&sport->port, (unsigned char)rx))
-                        goto ignore_char;
+                        continue;
+
+                if (rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) ) {
+                        if (rx & URXD_PRERR)
+                                sport->port.icount.parity++;
+                        else if (rx & URXD_FRMERR)
+                                sport->port.icount.frame++;
+                        if (rx & URXD_OVRRUN)
+                                sport->port.icount.overrun++;
+
+                        if (rx & sport->port.ignore_status_mask) {
+                                if (++ignored > 100)
+                                        goto out;
+                                continue;
+                        }
+
+                        rx &= sport->port.read_status_mask;
+
+                        if (rx & URXD_PRERR)
+                                flg = TTY_PARITY;
+                        else if (rx & URXD_FRMERR)
+                                flg = TTY_FRAME;
+                        if (rx & URXD_OVRRUN)
+                                flg = TTY_OVERRUN;
 
-                if( rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) )
-                        goto handle_error;
+#ifdef SUPPORT_SYSRQ
+                        sport->port.sysrq = 0;
+#endif
+                }
 
-        error_return:
                 tty_insert_flip_char(tty, rx, flg);
-
-        ignore_char:
-                rx = readl(sport->port.membase + URXD0);
-        } while(rx & URXD_CHARRDY);
+        }
 
 out:
         spin_unlock_irqrestore(&sport->port.lock,flags);
         tty_flip_buffer_push(tty);
         return IRQ_HANDLED;
-
-handle_error:
-        if (rx & URXD_PRERR)
-                sport->port.icount.parity++;
-        else if (rx & URXD_FRMERR)
-                sport->port.icount.frame++;
-        if (rx & URXD_OVRRUN)
-                sport->port.icount.overrun++;
-
-        if (rx & sport->port.ignore_status_mask) {
-                if (++ignored > 100)
-                        goto out;
-                goto ignore_char;
-        }
-
-        rx &= sport->port.read_status_mask;
-
-        if (rx & URXD_PRERR)
-                flg = TTY_PARITY;
-        else if (rx & URXD_FRMERR)
-                flg = TTY_FRAME;
-        if (rx & URXD_OVRRUN)
-                flg = TTY_OVERRUN;
-
-#ifdef SUPPORT_SYSRQ
-        sport->port.sysrq = 0;
-#endif
-        goto error_return;
 }
 
 /*
@@ -546,7 +531,7 @@ static int imx_startup(struct uart_port *port)
         writel(USR1_RTSD, sport->port.membase + USR1);
 
         temp = readl(sport->port.membase + UCR1);
-        temp |= (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
+        temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
         writel(temp, sport->port.membase + UCR1);
 
         temp = readl(sport->port.membase + UCR2);
@@ -731,9 +716,11 @@ static const char *imx_type(struct uart_port *port)
  */
 static void imx_release_port(struct uart_port *port)
 {
-        struct imx_port *sport = (struct imx_port *)port;
+        struct platform_device *pdev = to_platform_device(port->dev);
+        struct resource *mmres;
 
-        release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
+        mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(mmres->start, mmres->end - mmres->start + 1);
 }
 
 /*
@@ -741,10 +728,18 @@ static void imx_release_port(struct uart_port *port)
  */
 static int imx_request_port(struct uart_port *port)
 {
-        struct imx_port *sport = (struct imx_port *)port;
+        struct platform_device *pdev = to_platform_device(port->dev);
+        struct resource *mmres;
+        void *ret;
+
+        mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!mmres)
+                return -ENODEV;
+
+        ret = request_mem_region(mmres->start, mmres->end - mmres->start + 1,
+                        "imx-uart");
 
-        return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
-                        "imx-uart") != NULL ? 0 : -EBUSY;
+        return  ret ? 0 : -EBUSY;
 }
 
 /*
@@ -815,7 +810,7 @@ static struct imx_port imx_ports[] = {
                 .type           = PORT_IMX,
                 .iotype         = UPIO_MEM,
                 .membase        = (void *)IMX_UART1_BASE,
-                .mapbase        = IMX_UART1_BASE, /* FIXME */
+                .mapbase        = 0x00206000,
                 .irq            = UART1_MINT_RX,
                 .uartclk        = 16000000,
                 .fifosize       = 32,
@@ -831,7 +826,7 @@ static struct imx_port imx_ports[] = {
                 .type           = PORT_IMX,
                 .iotype         = UPIO_MEM,
                 .membase        = (void *)IMX_UART2_BASE,
-                .mapbase        = IMX_UART2_BASE, /* FIXME */
+                .mapbase        = 0x00207000,
                 .irq            = UART2_MINT_RX,
                 .uartclk        = 16000000,
                 .fifosize       = 32,
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 46ee7f4c0912..85074cb36f38 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1033,7 +1033,7 @@ MODULE_LICENSE ("GPL");
 #define OF_PLATFORM_DRIVER      ehci_hcd_ppc_of_driver
 #endif
 
-#ifdef CONFIG_ARCH_ORION
+#ifdef CONFIG_PLAT_ORION
 #include "ehci-orion.c"
 #define PLATFORM_DRIVER         ehci_orion_driver
 #endif
diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
index e129981f139f..d187d0313742 100644
--- a/drivers/usb/host/ehci-orion.c
+++ b/drivers/usb/host/ehci-orion.c
@@ -11,15 +11,18 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
-#include <asm/arch/orion.h>
+#include <linux/mbus.h>
+#include <asm/plat-orion/ehci-orion.h>
 
 #define rdl(off)        __raw_readl(hcd->regs + (off))
 #define wrl(off, val)   __raw_writel((val), hcd->regs + (off))
 
-#define USB_CAUSE               0x310
-#define USB_MASK                0x314
 #define USB_CMD                 0x140
 #define USB_MODE                0x1a8
+#define USB_CAUSE               0x310
+#define USB_MASK                0x314
+#define USB_WINDOW_CTRL(i)      (0x320 + ((i) << 4))
+#define USB_WINDOW_BASE(i)      (0x324 + ((i) << 4))
 #define USB_IPG                 0x360
 #define USB_PHY_PWR_CTRL        0x400
 #define USB_PHY_TX_CTRL         0x420
@@ -162,8 +165,30 @@ static const struct hc_driver ehci_orion_hc_driver = {
         .bus_resume = ehci_bus_resume,
 };
 
+static void __init
+ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
+                                struct mbus_dram_target_info *dram)
+{
+        int i;
+
+        for (i = 0; i < 4; i++) {
+                wrl(USB_WINDOW_CTRL(i), 0);
+                wrl(USB_WINDOW_BASE(i), 0);
+        }
+
+        for (i = 0; i < dram->num_cs; i++) {
+                struct mbus_dram_window *cs = dram->cs + i;
+
+                wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) |
+                                        (cs->mbus_attr << 8) |
+                                        (dram->mbus_dram_target_id << 4) | 1);
+                wrl(USB_WINDOW_BASE(i), cs->base);
+        }
+}
+
 static int __init ehci_orion_drv_probe(struct platform_device *pdev)
 {
+        struct orion_ehci_data *pd = pdev->dev.platform_data;
         struct resource *res;
         struct usb_hcd *hcd;
         struct ehci_hcd *ehci;
@@ -227,6 +252,12 @@ static int __init ehci_orion_drv_probe(struct platform_device *pdev)
         ehci->sbrn = 0x20;
 
         /*
+         * (Re-)program MBUS remapping windows if we are asked to.
+         */
+        if (pd != NULL && pd->dram != NULL)
+                ehci_orion_conf_mbus_windows(hcd, pd->dram);
+
+        /*
          * setup Orion USB controller
          */
         orion_usb_setup(hcd);
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index 97facb121c73..757651954e6c 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -45,6 +45,7 @@
 #include <asm/irq.h>
 #include <asm/div64.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/bitfield.h>
 #include <asm/arch/pxafb.h>
 
diff --git a/include/asm-arm/arch-at91/at91_ecc.h b/include/asm-arm/arch-at91/at91_ecc.h
index ff93df516d6d..1e5a8caca2d1 100644
--- a/include/asm-arm/arch-at91/at91_ecc.h
+++ b/include/asm-arm/arch-at91/at91_ecc.h
@@ -13,26 +13,26 @@
 #ifndef AT91_ECC_H
 #define AT91_ECC_H
 
-#define AT91_ECC_CR             (AT91_ECC + 0x00)       /* Control register */
+#define AT91_ECC_CR             0x00                    /* Control register */
 #define         AT91_ECC_RST            (1 << 0)                /* Reset parity */
 
-#define AT91_ECC_MR             (AT91_ECC + 0x04)       /* Mode register */
+#define AT91_ECC_MR             0x04                    /* Mode register */
 #define         AT91_ECC_PAGESIZE       (3 << 0)                /* Page Size */
 #define                 AT91_ECC_PAGESIZE_528           (0)
 #define                 AT91_ECC_PAGESIZE_1056          (1)
 #define                 AT91_ECC_PAGESIZE_2112          (2)
 #define                 AT91_ECC_PAGESIZE_4224          (3)
 
-#define AT91_ECC_SR             (AT91_ECC + 0x08)       /* Status register */
+#define AT91_ECC_SR             0x08                    /* Status register */
 #define         AT91_ECC_RECERR         (1 << 0)                /* Recoverable Error */
 #define         AT91_ECC_ECCERR         (1 << 1)                /* ECC Single Bit Error */
 #define         AT91_ECC_MULERR         (1 << 2)                /* Multiple Errors */
 
-#define AT91_ECC_PR             (AT91_ECC + 0x0c)       /* Parity register */
+#define AT91_ECC_PR             0x0c                    /* Parity register */
 #define         AT91_ECC_BITADDR        (0xf << 0)              /* Bit Error Address */
 #define         AT91_ECC_WORDADDR       (0xfff << 4)            /* Word Error Address */
 
-#define AT91_ECC_NPR            (AT91_ECC + 0x10)       /* NParity register */
+#define AT91_ECC_NPR            0x10                    /* NParity register */
 #define         AT91_ECC_NPARITY        (0xffff << 0)           /* NParity */
 
 #endif
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index 52cd8e5dabc9..c2b13c280155 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -76,10 +76,17 @@
 #define                 AT91_PMC_PRES_32                (5 << 2)
 #define                 AT91_PMC_PRES_64                (6 << 2)
 #define         AT91_PMC_MDIV           (3 <<  8)               /* Master Clock Division */
-#define                 AT91_PMC_MDIV_1                 (0 << 8)
-#define                 AT91_PMC_MDIV_2                 (1 << 8)
-#define                 AT91_PMC_MDIV_3                 (2 << 8)
-#define                 AT91_PMC_MDIV_4                 (3 << 8)
+#define                 AT91RM9200_PMC_MDIV_1           (0 << 8)        /* [AT91RM9200 only] */
+#define                 AT91RM9200_PMC_MDIV_2           (1 << 8)
+#define                 AT91RM9200_PMC_MDIV_3           (2 << 8)
+#define                 AT91RM9200_PMC_MDIV_4           (3 << 8)
+#define                 AT91SAM9_PMC_MDIV_1             (0 << 8)        /* [SAM9,CAP9 only] */
+#define                 AT91SAM9_PMC_MDIV_2             (1 << 8)
+#define                 AT91SAM9_PMC_MDIV_4             (2 << 8)
+#define                 AT91SAM9_PMC_MDIV_6             (3 << 8)
+#define         AT91_PMC_PDIV           (1 << 12)               /* Processor Clock Division [some SAM9 only] */
+#define                 AT91_PMC_PDIV_1                 (0 << 12)
+#define                 AT91_PMC_PDIV_2                 (1 << 12)
 
 #define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-3 Registers */
 
diff --git a/include/asm-arm/arch-at91/at91_shdwc.h b/include/asm-arm/arch-at91/at91_shdwc.h
index 01b433de2272..581fa41d90e8 100644
--- a/include/asm-arm/arch-at91/at91_shdwc.h
+++ b/include/asm-arm/arch-at91/at91_shdwc.h
@@ -24,10 +24,12 @@
 #define                 AT91_SHDW_WKMODE0_LOW           2
 #define                 AT91_SHDW_WKMODE0_ANYLEVEL      3
 #define         AT91_SHDW_CPTWK0        (0xf << 4)              /* Counter On Wake Up 0 */
+#define                 AT91_SHDW_CPTWK0_(x)    ((x) << 4)
 #define         AT91_SHDW_RTTWKEN       (1   << 16)             /* Real Time Timer Wake-up Enable */
 
 #define AT91_SHDW_SR            (AT91_SHDWC + 0x08)     /* Shut Down Status Register */
 #define         AT91_SHDW_WAKEUP0       (1 <<  0)               /* Wake-up 0 Status */
 #define         AT91_SHDW_RTTWK         (1 << 16)               /* Real-time Timer Wake-up */
+#define         AT91_SHDW_RTCWK         (1 << 17)               /* Real-time Clock Wake-up [SAM9RL] */
 
 #endif
diff --git a/include/asm-arm/arch-at91/at91cap9_ddrsdr.h b/include/asm-arm/arch-at91/at91cap9_ddrsdr.h
new file mode 100644
index 000000000000..efdb23af1ee4
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91cap9_ddrsdr.h
@@ -0,0 +1,100 @@
+/*
+ * include/asm-arm/arch-at91/at91cap9_ddrsdr.h
+ *
+ * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
+ * Based on AT91CAP9 datasheet revision B.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91CAP9_DDRSDR_H
+#define AT91CAP9_DDRSDR_H
+
+#define AT91_DDRSDRC_MR         (AT91_DDRSDRC + 0x00)   /* Mode Register */
+#define         AT91_DDRSDRC_MODE       (0xf << 0)              /* Command Mode */
+#define                 AT91_DDRSDRC_MODE_NORMAL                0
+#define                 AT91_DDRSDRC_MODE_NOP           1
+#define                 AT91_DDRSDRC_MODE_PRECHARGE     2
+#define                 AT91_DDRSDRC_MODE_LMR           3
+#define                 AT91_DDRSDRC_MODE_REFRESH       4
+#define                 AT91_DDRSDRC_MODE_EXT_LMR       5
+#define                 AT91_DDRSDRC_MODE_DEEP          6
+
+#define AT91_DDRSDRC_RTR        (AT91_DDRSDRC + 0x04)   /* Refresh Timer Register */
+#define         AT91_DDRSDRC_COUNT      (0xfff << 0)            /* Refresh Timer Counter */
+
+#define AT91_DDRSDRC_CR         (AT91_DDRSDRC + 0x08)   /* Configuration Register */
+#define         AT91_DDRSDRC_NC         (3 << 0)                /* Number of Column Bits */
+#define                 AT91_DDRSDRC_NC_SDR8    (0 << 0)
+#define                 AT91_DDRSDRC_NC_SDR9    (1 << 0)
+#define                 AT91_DDRSDRC_NC_SDR10   (2 << 0)
+#define                 AT91_DDRSDRC_NC_SDR11   (3 << 0)
+#define                 AT91_DDRSDRC_NC_DDR9    (0 << 0)
+#define                 AT91_DDRSDRC_NC_DDR10   (1 << 0)
+#define                 AT91_DDRSDRC_NC_DDR11   (2 << 0)
+#define                 AT91_DDRSDRC_NC_DDR12   (3 << 0)
+#define         AT91_DDRSDRC_NR         (3 << 2)                /* Number of Row Bits */
+#define                 AT91_DDRSDRC_NR_11      (0 << 2)
+#define                 AT91_DDRSDRC_NR_12      (1 << 2)
+#define                 AT91_DDRSDRC_NR_13      (2 << 2)
+#define         AT91_DDRSDRC_CAS        (7 << 4)                /* CAS Latency */
+#define                 AT91_DDRSDRC_CAS_2      (2 << 4)
+#define                 AT91_DDRSDRC_CAS_3      (3 << 4)
+#define                 AT91_DDRSDRC_CAS_25     (6 << 4)
+#define         AT91_DDRSDRC_DLL        (1 << 7)                /* Reset DLL */
+#define         AT91_DDRSDRC_DICDS      (1 << 8)                /* Output impedance control */
+
+#define AT91_DDRSDRC_T0PR       (AT91_DDRSDRC + 0x0C)   /* Timing 0 Register */
+#define         AT91_DDRSDRC_TRAS       (0xf <<  0)             /* Active to Precharge delay */
+#define         AT91_DDRSDRC_TRCD       (0xf <<  4)             /* Row to Column delay */
+#define         AT91_DDRSDRC_TWR        (0xf <<  8)             /* Write recovery delay */
+#define         AT91_DDRSDRC_TRC        (0xf << 12)             /* Row cycle delay */
+#define         AT91_DDRSDRC_TRP        (0xf << 16)             /* Row precharge delay */
+#define         AT91_DDRSDRC_TRRD       (0xf << 20)             /* Active BankA to BankB */
+#define         AT91_DDRSDRC_TWTR       (1   << 24)             /* Internal Write to Read delay */
+#define         AT91_DDRSDRC_TMRD       (0xf << 28)             /* Load mode to active/refresh delay */
+
+#define AT91_DDRSDRC_T1PR       (AT91_DDRSDRC + 0x10)   /* Timing 1 Register */
+#define         AT91_DDRSDRC_TRFC       (0x1f << 0)             /* Row Cycle Delay */
+#define         AT91_DDRSDRC_TXSNR      (0xff << 8)             /* Exit self-refresh to non-read */
+#define         AT91_DDRSDRC_TXSRD      (0xff << 16)            /* Exit self-refresh to read */
+#define         AT91_DDRSDRC_TXP        (0xf  << 24)            /* Exit power-down delay */
+
+#define AT91_DDRSDRC_LPR        (AT91_DDRSDRC + 0x18)   /* Low Power Register */
+#define         AT91_DDRSDRC_LPCB               (3 << 0)        /* Low-power Configurations */
+#define                 AT91_DDRSDRC_LPCB_DISABLE               0
+#define                 AT91_DDRSDRC_LPCB_SELF_REFRESH          1
+#define                 AT91_DDRSDRC_LPCB_POWER_DOWN            2
+#define                 AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN       3
+#define         AT91_DDRSDRC_CLKFR              (1 << 2)        /* Clock Frozen */
+#define         AT91_DDRSDRC_PASR               (7 << 4)        /* Partial Array Self Refresh */
+#define         AT91_DDRSDRC_TCSR               (3 << 8)        /* Temperature Compensated Self Refresh */
+#define         AT91_DDRSDRC_DS                 (3 << 10)       /* Drive Strength */
+#define         AT91_DDRSDRC_TIMEOUT            (3 << 12)       /* Time to define when Low Power Mode is enabled */
+#define                 AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES       (0 << 12)
+#define                 AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES      (1 << 12)
+#define                 AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES     (2 << 12)
+
+#define AT91_DDRSDRC_MDR        (AT91_DDRSDRC + 0x1C)   /* Memory Device Register */
+#define         AT91_DDRSDRC_MD         (3 << 0)                /* Memory Device Type */
+#define                 AT91_DDRSDRC_MD_SDR             0
+#define                 AT91_DDRSDRC_MD_LOW_POWER_SDR   1
+#define                 AT91_DDRSDRC_MD_DDR             2
+#define                 AT91_DDRSDRC_MD_LOW_POWER_DDR   3
+
+#define AT91_DDRSDRC_DLLR       (AT91_DDRSDRC + 0x20)   /* DLL Information Register */
+#define         AT91_DDRSDRC_MDINC      (1 << 0)                /* Master Delay increment */
+#define         AT91_DDRSDRC_MDDEC      (1 << 1)                /* Master Delay decrement */
+#define         AT91_DDRSDRC_MDOVF      (1 << 2)                /* Master Delay Overflow */
+#define         AT91_DDRSDRC_SDCOVF     (1 << 3)                /* Slave Delay Correction Overflow */
+#define         AT91_DDRSDRC_SDCUDF     (1 << 4)                /* Slave Delay Correction Underflow */
+#define         AT91_DDRSDRC_SDERF      (1 << 5)                /* Slave Delay Correction error */
+#define         AT91_DDRSDRC_MDVAL      (0xff <<  8)            /* Master Delay value */
+#define         AT91_DDRSDRC_SDVAL      (0xff << 16)            /* Slave Delay value */
+#define         AT91_DDRSDRC_SDCVAL     (0xff << 24)            /* Slave Delay Correction value */
+
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91sam926x_mc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h
index d82631c251f1..d3b8b3da6b4d 100644
--- a/include/asm-arm/arch-at91/at91sam926x_mc.h
+++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h
@@ -1,7 +1,7 @@
 /*
- * include/asm-arm/arch-at91/at91sam926x_mc.h
+ * include/asm-arm/arch-at91/at91sam9_sdramc.h
  *
- * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
+ * SDRAM Controllers (SDRAMC) - System peripherals registers.
  * Based on AT91SAM9261 datasheet revision D.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -10,8 +10,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91SAM926x_MC_H
-#define AT91SAM926x_MC_H
+#ifndef AT91SAM9_SDRAMC_H
+#define AT91SAM9_SDRAMC_H
 
 /* SDRAM Controller (SDRAMC) registers */
 #define AT91_SDRAMC_MR          (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
@@ -62,7 +62,7 @@
 #define                 AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
 #define         AT91_SDRAMC_PASR                (7 << 4)        /* Partial Array Self Refresh */
 #define         AT91_SDRAMC_TCSR                (3 << 8)        /* Temperature Compensated Self Refresh */
-#define         AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strenght */
+#define         AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strength */
 #define         AT91_SDRAMC_TIMEOUT             (3 << 12)       /* Time to define when Low Power Mode is enabled */
 #define                 AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        (0 << 12)
 #define                 AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
@@ -80,62 +80,4 @@
 #define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
 
 
-/* Static Memory Controller (SMC) registers */
-#define AT91_SMC_SETUP(n)       (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
-#define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
-#define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
-#define         AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
-#define                 AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
-#define         AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
-#define                 AT91_SMC_NRDSETUP_(x)   ((x) << 16)
-#define         AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
-#define                 AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
-
-#define AT91_SMC_PULSE(n)       (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
-#define         AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
-#define                 AT91_SMC_NWEPULSE_(x)   ((x) << 0)
-#define         AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
-#define                 AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
-#define         AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
-#define                 AT91_SMC_NRDPULSE_(x)   ((x) << 16)
-#define         AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
-#define                 AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-
-#define AT91_SMC_CYCLE(n)       (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
-#define         AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
-#define                 AT91_SMC_NWECYCLE_(x)   ((x) << 0)
-#define         AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
-#define                 AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
-
-#define AT91_SMC_MODE(n)        (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
-#define         AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
-#define         AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
-#define         AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
-#define                 AT91_SMC_EXNWMODE_DISABLE       (0 << 4)
-#define                 AT91_SMC_EXNWMODE_FROZEN        (2 << 4)
-#define                 AT91_SMC_EXNWMODE_READY         (3 << 4)
-#define         AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
-#define                 AT91_SMC_BAT_SELECT             (0 << 8)
-#define                 AT91_SMC_BAT_WRITE              (1 << 8)
-#define         AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
-#define                 AT91_SMC_DBW_8                  (0 << 12)
-#define                 AT91_SMC_DBW_16                 (1 << 12)
-#define                 AT91_SMC_DBW_32                 (2 << 12)
-#define         AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
-#define                 AT91_SMC_TDF_(x)                ((x) << 16)
-#define         AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
-#define         AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
-#define         AT91_SMC_PS             (3 << 28)                       /* Page Size */
-#define                 AT91_SMC_PS_4                   (0 << 28)
-#define                 AT91_SMC_PS_8                   (1 << 28)
-#define                 AT91_SMC_PS_16                  (2 << 28)
-#define                 AT91_SMC_PS_32                  (3 << 28)
-
-#if defined(AT91_SMC1)          /* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n)      (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n)      (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n)      (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n)       (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
-#endif
-
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9_smc.h b/include/asm-arm/arch-at91/at91sam9_smc.h
new file mode 100644
index 000000000000..9e49eed31e50
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91sam9_smc.h
@@ -0,0 +1,73 @@
+/*
+ * include/asm-arm/arch-at91/at91sam9_smc.h
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on AT91SAM9261 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91SAM9_SMC_H
+#define AT91SAM9_SMC_H
+
+#define AT91_SMC_SETUP(n)       (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
+#define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
+#define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
+#define         AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
+#define                 AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
+#define         AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
+#define                 AT91_SMC_NRDSETUP_(x)   ((x) << 16)
+#define         AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
+#define                 AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
+
+#define AT91_SMC_PULSE(n)       (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
+#define         AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
+#define                 AT91_SMC_NWEPULSE_(x)   ((x) << 0)
+#define         AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
+#define                 AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
+#define         AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
+#define                 AT91_SMC_NRDPULSE_(x)   ((x) << 16)
+#define         AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
+#define                 AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
+
+#define AT91_SMC_CYCLE(n)       (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
+#define         AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
+#define                 AT91_SMC_NWECYCLE_(x)   ((x) << 0)
+#define         AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
+#define                 AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
+
+#define AT91_SMC_MODE(n)        (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
+#define         AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
+#define         AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
+#define         AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
+#define                 AT91_SMC_EXNWMODE_DISABLE       (0 << 4)
+#define                 AT91_SMC_EXNWMODE_FROZEN        (2 << 4)
+#define                 AT91_SMC_EXNWMODE_READY         (3 << 4)
+#define         AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
+#define                 AT91_SMC_BAT_SELECT             (0 << 8)
+#define                 AT91_SMC_BAT_WRITE              (1 << 8)
+#define         AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
+#define                 AT91_SMC_DBW_8                  (0 << 12)
+#define                 AT91_SMC_DBW_16                 (1 << 12)
+#define                 AT91_SMC_DBW_32                 (2 << 12)
+#define         AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
+#define                 AT91_SMC_TDF_(x)                ((x) << 16)
+#define         AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
+#define         AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
+#define         AT91_SMC_PS             (3 << 28)                       /* Page Size */
+#define                 AT91_SMC_PS_4                   (0 << 28)
+#define                 AT91_SMC_PS_8                   (1 << 28)
+#define                 AT91_SMC_PS_16                  (2 << 28)
+#define                 AT91_SMC_PS_32                  (3 << 28)
+
+#if defined(AT91_SMC1)          /* The AT91SAM9263 has 2 Static Memory contollers */
+#define AT91_SMC1_SETUP(n)      (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
+#define AT91_SMC1_PULSE(n)      (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
+#define AT91_SMC1_CYCLE(n)      (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
+#define AT91_SMC1_MODE(n)       (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-ep93xx/gpio.h b/include/asm-arm/arch-ep93xx/gpio.h
index 9b1864bbd9a8..186e7c715f8a 100644
--- a/include/asm-arm/arch-ep93xx/gpio.h
+++ b/include/asm-arm/arch-ep93xx/gpio.h
@@ -101,30 +101,17 @@
 
 /* new generic GPIO API - see Documentation/gpio.txt */
 
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        if (gpio > EP93XX_GPIO_LINE_MAX)
-                return -EINVAL;
-        return 0;
-}
+#include <asm-generic/gpio.h>
 
-static inline void gpio_free(unsigned gpio)
-{
-}
-
-int gpio_direction_input(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
-int gpio_get_value(unsigned gpio);
-void gpio_set_value(unsigned gpio, int value);
-
-#include <asm-generic/gpio.h> /* cansleep wrappers */
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
 
 /*
  * Map GPIO A0..A7  (0..7)  to irq 64..71,
  *          B0..B7  (7..15) to irq 72..79, and
  *          F0..F7 (16..24) to irq 80..87.
  */
-
 static inline int gpio_to_irq(unsigned gpio)
 {
         if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ)
diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h
index b0364dce463f..7ad2c656e162 100644
--- a/include/asm-arm/arch-ks8695/devices.h
+++ b/include/asm-arm/arch-ks8695/devices.h
@@ -18,6 +18,11 @@ extern void __init ks8695_add_device_wan(void);
 extern void __init ks8695_add_device_lan(void);
 extern void __init ks8695_add_device_hpna(void);
 
+ /* LEDs */
+extern short ks8695_leds_cpu;
+extern short ks8695_leds_timer;
+extern void __init ks8695_init_leds(u8 cpu_led, u8 timer_led);
+
  /* PCI */
 #define KS8695_MODE_PCI         0
 #define KS8695_MODE_MINIPCI     1
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
index be29b83ad4ae..8590127760a8 100644
--- a/include/asm-arm/arch-mxc/board-mx31ads.h
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -11,107 +11,77 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
 #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
 
-/*!
- * @name PBC Controller parameters
- */
-/*! @{ */
-/*!
- * Base address of PBC controller
- */
+/* Base address of PBC controller */
 #define PBC_BASE_ADDRESS        IO_ADDRESS(CS4_BASE_ADDR)
 /* Offsets for the PBC Controller register */
-/*!
- * PBC Board status register offset
- */
+
+/* PBC Board status register offset */
 #define PBC_BSTAT               0x000002
-/*!
- * PBC Board control register 1 set address.
- */
+
+/* PBC Board control register 1 set address */
 #define PBC_BCTRL1_SET          0x000004
-/*!
- * PBC Board control register 1 clear address.
- */
+
+/* PBC Board control register 1 clear address */
 #define PBC_BCTRL1_CLEAR        0x000006
-/*!
- * PBC Board control register 2 set address.
- */
+
+/* PBC Board control register 2 set address */
 #define PBC_BCTRL2_SET          0x000008
-/*!
- * PBC Board control register 2 clear address.
- */
+
+/* PBC Board control register 2 clear address */
 #define PBC_BCTRL2_CLEAR        0x00000A
-/*!
- * PBC Board control register 3 set address.
- */
+
+/* PBC Board control register 3 set address */
 #define PBC_BCTRL3_SET          0x00000C
-/*!
- * PBC Board control register 3 clear address.
- */
+
+/* PBC Board control register 3 clear address */
 #define PBC_BCTRL3_CLEAR        0x00000E
-/*!
- * PBC Board control register 4 set address.
- */
+
+/* PBC Board control register 4 set address */
 #define PBC_BCTRL4_SET          0x000010
-/*!
- * PBC Board control register 4 clear address.
- */
+
+/* PBC Board control register 4 clear address */
 #define PBC_BCTRL4_CLEAR        0x000012
-/*!
- * PBC Board status register 1.
- */
+
+/* PBC Board status register 1 */
 #define PBC_BSTAT1              0x000014
-/*!
- * PBC Board interrupt status register.
- */
+
+/* PBC Board interrupt status register */
 #define PBC_INTSTATUS           0x000016
-/*!
- * PBC Board interrupt current status register.
- */
+
+/* PBC Board interrupt current status register */
 #define PBC_INTCURR_STATUS      0x000018
-/*!
- * PBC Interrupt mask register set address.
- */
+
+/* PBC Interrupt mask register set address */
 #define PBC_INTMASK_SET         0x00001A
-/*!
- * PBC Interrupt mask register clear address.
- */
+
+/* PBC Interrupt mask register clear address */
 #define PBC_INTMASK_CLEAR       0x00001C
 
-/*!
- * External UART A.
- */
+/* External UART A */
 #define PBC_SC16C652_UARTA      0x010000
-/*!
- * External UART B.
- */
+
+/* External UART B */
 #define PBC_SC16C652_UARTB      0x010010
-/*!
- * Ethernet Controller IO base address.
- */
+
+/* Ethernet Controller IO base address */
 #define PBC_CS8900A_IOBASE      0x020000
-/*!
- * Ethernet Controller Memory base address.
- */
+
+/* Ethernet Controller Memory base address */
 #define PBC_CS8900A_MEMBASE     0x021000
-/*!
- * Ethernet Controller DMA base address.
- */
+
+/* Ethernet Controller DMA base address */
 #define PBC_CS8900A_DMABASE     0x022000
-/*!
- * External chip select 0.
- */
+
+/* External chip select 0 */
 #define PBC_XCS0                0x040000
-/*!
- * LCD Display enable.
- */
+
+/* LCD Display enable */
 #define PBC_LCD_EN_B            0x060000
-/*!
- * Code test debug enable.
- */
+
+/* Code test debug enable */
 #define PBC_CODE_B              0x070000
-/*!
- * PSRAM memory select.
- */
+
+/* PSRAM memory select */
 #define PBC_PSRAM_B             0x5000000
 
 #define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
@@ -139,4 +109,4 @@
 
 #define MXC_MAX_EXP_IO_LINES    16
 
-#endif                          /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
+#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h
index 65e639d51d2b..c822d569a05e 100644
--- a/include/asm-arm/arch-mxc/dma.h
+++ b/include/asm-arm/arch-mxc/dma.h
@@ -11,11 +11,4 @@
 #ifndef __ASM_ARCH_MXC_DMA_H__
 #define __ASM_ARCH_MXC_DMA_H__
 
-/*!
- * @file dma.h
- * @brief This file contains Unified DMA API for all MXC platforms.
- * The API is platform independent.
- *
- * @ingroup SDMA
- */
 #endif
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
index 3c09b92fef0d..e87ff0679d5e 100644
--- a/include/asm-arm/arch-mxc/hardware.h
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -8,45 +8,24 @@
  * published by the Free Software Foundation.
  */
 
-/*!
- * @file hardware.h
- * @brief This file contains the hardware definitions of the board.
- *
- * @ingroup System
- */
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
 #define __ASM_ARCH_MXC_HARDWARE_H__
 
 #include <asm/sizes.h>
 
-#include <asm/arch/mx31.h>
+#ifdef CONFIG_ARCH_MX3
+# include <asm/arch/mx31.h>
+#endif
 
 #include <asm/arch/mxc.h>
 
-#define MXC_MAX_GPIO_LINES      (GPIO_NUM_PIN * GPIO_PORT_NUM)
-
 /*
  * ---------------------------------------------------------------------------
  * Board specific defines
  * ---------------------------------------------------------------------------
  */
-#define MXC_EXP_IO_BASE         (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES)
-
-#include <asm/arch/board-mx31ads.h>
-
-#ifndef MXC_MAX_EXP_IO_LINES
-#define MXC_MAX_EXP_IO_LINES 0
+#ifdef CONFIG_MACH_MX31ADS
+# include <asm/arch/board-mx31ads.h>
 #endif
 
-#define MXC_MAX_VIRTUAL_INTS    16
-#define MXC_VIRTUAL_INTS_BASE   (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
-#define MXC_SDIO1_CARD_IRQ      MXC_VIRTUAL_INTS_BASE
-#define MXC_SDIO2_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 1)
-#define MXC_SDIO3_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 2)
-
-#define MXC_MAX_INTS            (MXC_MAX_INT_LINES + \
-                                MXC_MAX_GPIO_LINES + \
-                                MXC_MAX_EXP_IO_LINES + \
-                                MXC_MAX_VIRTUAL_INTS)
-
-#endif                          /* __ASM_ARCH_MXC_HARDWARE_H__ */
+#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h
index cf6c83a4b9f7..65b6810124c1 100644
--- a/include/asm-arm/arch-mxc/io.h
+++ b/include/asm-arm/arch-mxc/io.h
@@ -8,24 +8,13 @@
  * published by the Free Software Foundation.
  */
 
-/*!
- * @file io.h
- * @brief This file contains some memory mapping macros.
- * @note There is no real ISA or PCI buses. But have to define these macros
- * for some drivers to compile.
- *
- * @ingroup System
- */
-
 #ifndef __ASM_ARCH_MXC_IO_H__
 #define __ASM_ARCH_MXC_IO_H__
 
-/*! Allow IO space to be anywhere in the memory */
+/* Allow IO space to be anywhere in the memory */
 #define IO_SPACE_LIMIT 0xffffffff
 
-/*!
- * io address mapping macro
- */
+/* io address mapping macro */
 #define __io(a)                 ((void __iomem *)(a))
 
 #define __mem_pci(a)            (a)
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
index e4686c6bc4bf..b2c5205e1962 100644
--- a/include/asm-arm/arch-mxc/irqs.h
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -13,26 +13,17 @@
 
 #include <asm/hardware.h>
 
-/*!
- * @file irqs.h
- * @brief This file defines the number of normal interrupts and fast interrupts
- *
- * @ingroup Interrupt
- */
-
 #define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
 
 #define MXC_IRQ_TO_GPIO(irq)    ((irq) - MXC_GPIO_INT_BASE)
 #define MXC_GPIO_TO_IRQ(x)      (MXC_GPIO_INT_BASE + x)
 
-/*!
- * Number of normal interrupts
- */
-#define NR_IRQS         MXC_MAX_INTS
+/* Number of normal interrupts */
+#define NR_IRQS         (MXC_MAX_INT_LINES + \
+                        MXC_MAX_GPIO_LINES + \
+                        MXC_MAX_VIRTUAL_INTS)
 
-/*!
- * Number of fast interrupts
- */
+/* Number of fast interrupts */
 #define NR_FIQS         MXC_MAX_INTS
 
-#endif                          /* __ASM_ARCH_MXC_IRQS_H__ */
+#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h
index c89aac83a407..059f83023a10 100644
--- a/include/asm-arm/arch-mxc/memory.h
+++ b/include/asm-arm/arch-mxc/memory.h
@@ -13,24 +13,17 @@
 
 #include <asm/hardware.h>
 
-/*!
- * @file memory.h
- * @brief This file contains macros needed by the Linux kernel and drivers.
- *
- * @ingroup Memory
- */
-
-/*!
+/*
  * Virtual view <-> DMA view memory address translations
  * This macro is used to translate the virtual address to an address
  * suitable to be passed to set_dma_addr()
  */
 #define __virt_to_bus(a)        __virt_to_phys(a)
 
-/*!
+/*
  * Used to convert an address for DMA operations to an address that the
  * kernel can use.
  */
 #define __bus_to_virt(a)        __phys_to_virt(a)
 
-#endif                          /* __ASM_ARCH_MXC_MEMORY_H__ */
+#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
index 85c49c9e5d15..36a1af495bb3 100644
--- a/include/asm-arm/arch-mxc/mx31.h
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -317,6 +317,8 @@
 #define MXC_MAX_INT_LINES       64
 
 #define MXC_GPIO_INT_BASE       MXC_MAX_INT_LINES
+#define MXC_MAX_GPIO_LINES      (GPIO_NUM_PIN * GPIO_PORT_NUM)
+#define MXC_MAX_VIRTUAL_INTS    16
 
 /*!
  * Number of GPIO port as defined in the IC Spec
@@ -329,7 +331,33 @@
 
 #define PROD_SIGNATURE          0x1     /* For MX31 */
 
+/* silicon revisions specific to i.MX31 */
+#define CHIP_REV_1_0            0x10
+#define CHIP_REV_1_1            0x11
+#define CHIP_REV_1_2            0x12
+#define CHIP_REV_1_3            0x13
+#define CHIP_REV_2_0            0x20
+#define CHIP_REV_2_1            0x21
+#define CHIP_REV_2_2            0x22
+#define CHIP_REV_2_3            0x23
+#define CHIP_REV_3_0            0x30
+#define CHIP_REV_3_1            0x31
+#define CHIP_REV_3_2            0x32
+
 #define SYSTEM_REV_MIN          CHIP_REV_1_0
 #define SYSTEM_REV_NUM          3
 
-#endif                  /*  __ASM_ARCH_MXC_MX31_H__ */
+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
+
+/* this is a i.MX31 CPU */
+#define cpu_is_mx31()           (1)
+
+extern unsigned int system_rev;
+
+static inline int mx31_revision(void)
+{
+        return system_rev;
+}
+#endif
+
+#endif /*  __ASM_ARCH_MXC_MX31_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 0837f1f9ca31..146d3f60951a 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -15,6 +15,11 @@
 #error "Do not include directly."
 #endif
 
+/* clean up all things that are not used */
+#ifndef CONFIG_ARCH_MX3
+# define cpu_is_mx31() (0)
+#endif
+
 /*
  *****************************************
  * GPT  Register definitions             *
@@ -31,9 +36,7 @@
 #define MXC_GPT_GPTICR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
 #define MXC_GPT_GPTCNT          IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
 
-/*!
- * GPT Control register bit definitions
- */
+/* GPT Control register bit definitions */
 #define GPTCR_FO3                       (1 << 31)
 #define GPTCR_FO2                       (1 << 30)
 #define GPTCR_FO1                       (1 << 29)
@@ -146,4 +149,4 @@
 #define IIM_PROD_REV_SH         3
 #define IIM_PROD_REV_LEN        5
 
-#endif                          /*  __ASM_ARCH_MXC_H__ */
+#endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h
index 109956b41aca..bbfc37465fc5 100644
--- a/include/asm-arm/arch-mxc/system.h
+++ b/include/asm-arm/arch-mxc/system.h
@@ -21,30 +21,14 @@
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
 #define __ASM_ARCH_MXC_SYSTEM_H__
 
-/*!
- * @file system.h
- * @brief This file contains idle and reset functions.
- *
- * @ingroup System
- */
-
-/*!
- * This function puts the CPU into idle mode. It is called by default_idle()
- * in process.c file.
- */
 static inline void arch_idle(void)
 {
         cpu_do_idle();
 }
 
-/*
- * This function resets the system. It is called by machine_restart().
- *
- * @param  mode         indicates different kinds of resets
- */
 static inline void arch_reset(char mode)
 {
         cpu_reset(0);
 }
 
-#endif                          /* __ASM_ARCH_MXC_SYSTEM_H__ */
+#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h
index 83a73da895eb..62d97623412f 100644
--- a/include/asm-arm/arch-mxc/vmalloc.h
+++ b/include/asm-arm/arch-mxc/vmalloc.h
@@ -20,17 +20,7 @@
 #ifndef __ASM_ARCH_MXC_VMALLOC_H__
 #define __ASM_ARCH_MXC_VMALLOC_H__
 
-/*!
- * @file vmalloc.h
- *
- * @brief This file contains platform specific macros for vmalloc.
- *
- * @ingroup System
- */
-
-/*!
- * vmalloc ending address
- */
+/* vmalloc ending address */
 #define VMALLOC_END       0xF4000000
 
-#endif                          /* __ASM_ARCH_MXC_VMALLOC_H__ */
+#endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
diff --git a/include/asm-arm/arch-ns9xxx/board.h b/include/asm-arm/arch-ns9xxx/board.h
index 716f34fdb716..e57443bdbbd9 100644
--- a/include/asm-arm/arch-ns9xxx/board.h
+++ b/include/asm-arm/arch-ns9xxx/board.h
@@ -1,7 +1,7 @@
 /*
  * include/asm-arm/arch-ns9xxx/board.h
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -13,8 +13,30 @@
 
 #include <asm/mach-types.h>
 
-#define board_is_a9m9750dev()   (machine_is_cc9p9360dev())
+#define board_is_a9m9750dev()   (0                      \
+                || machine_is_cc9p9360dev()             \
+                || machine_is_cc9p9750dev()             \
+                )
 
-#define board_is_jscc9p9360()   (machine_is_cc9p9360js())
+#define board_is_a9mvali()      (0                      \
+                || machine_is_cc9p9360val()             \
+                || machine_is_cc9p9750val()             \
+                )
+
+#define board_is_jscc9p9210()   (0                      \
+                || machine_is_cc9p9210js()              \
+                )
+
+#define board_is_jscc9p9215()   (0                      \
+                || machine_is_cc9p9215js()              \
+                )
+
+#define board_is_jscc9p9360()   (0                      \
+                || machine_is_cc9p9360js()              \
+                )
+
+#define board_is_uncbas()       (0                      \
+                || machine_is_cc7ucamry()               \
+                )
 
 #endif /* ifndef __ASM_ARCH_BOARD_H */
diff --git a/include/asm-arm/arch-ns9xxx/clock.h b/include/asm-arm/arch-ns9xxx/clock.h
deleted file mode 100644
index b943d3a92a1d..000000000000
--- a/include/asm-arm/arch-ns9xxx/clock.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * include/asm-arm/arch-ns9xxx/clock.h
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#include <asm/arch-ns9xxx/regs-sys.h>
-
-#define CRYSTAL 29491200 /* Hz */
-
-/* The HRM calls this value f_vco */
-static inline u32 ns9xxx_systemclock(void) __attribute__((const));
-static inline u32 ns9xxx_systemclock(void)
-{
-        u32 pll = __raw_readl(SYS_PLL);
-
-        /*
-         * The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in
-         * time.c).
-         *
-         * The following values are given:
-         *   - TIMERCLOCKSELECT == 2^i for an i in {0 .. 6}
-         *   - CRYSTAL == 29491200 == 2^17 * 3^2 * 5^2
-         *   - ND in {0 .. 31}
-         *   - FS in {0 .. 3}
-         *
-         * Assuming the worst, we consider:
-         *   - TIMERCLOCKSELECT == 64
-         *   - ND == 0
-         *   - FS == 3
-         *
-         * So HZ should be a divisor of:
-         *      (CRYSTAL * (ND + 1) >> FS) / TIMERCLOCKSELECT
-         *   == (2^17 * 3^2 * 5^2 * 1 >> 3) / 64
-         *   == 2^8 * 3^2 * 5^2
-         *   == 57600
-         *
-         * Currently HZ is defined to be 100 for this platform.
-         *
-         * Fine.
-         */
-        return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1)
-                >> REGGETIM(pll, SYS_PLL, FS);
-}
-
-static inline u32 ns9xxx_cpuclock(void) __attribute__((const));
-static inline u32 ns9xxx_cpuclock(void)
-{
-        return ns9xxx_systemclock() / 2;
-}
-
-static inline u32 ns9xxx_ahbclock(void) __attribute__((const));
-static inline u32 ns9xxx_ahbclock(void)
-{
-        return ns9xxx_systemclock() / 4;
-}
-
-static inline u32 ns9xxx_bbusclock(void) __attribute__((const));
-static inline u32 ns9xxx_bbusclock(void)
-{
-        return ns9xxx_systemclock() / 8;
-}
-
-#endif /* ifndef __ASM_ARCH_CLOCK_H */
diff --git a/include/asm-arm/arch-ns9xxx/entry-macro.S b/include/asm-arm/arch-ns9xxx/entry-macro.S
index 86aec87303e4..89a21c530468 100644
--- a/include/asm-arm/arch-ns9xxx/entry-macro.S
+++ b/include/asm-arm/arch-ns9xxx/entry-macro.S
@@ -1,7 +1,7 @@
 /*
  * include/asm-arm/arch-ns9xxx/entry-macro.S
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -9,16 +9,16 @@
  * the Free Software Foundation.
  */
 #include <asm/hardware.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
+#include <asm/arch-ns9xxx/regs-sys-common.h>
 
                 .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =SYS_ISRADDR
                 .endm
 
                 .macro  arch_ret_to_user, tmp1, tmp2
                 .endm
 
                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =SYS_ISRADDR
                 ldr     \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)]
                 cmp     \irqstat, #0
                 ldrne   \irqnr, [\base]
diff --git a/include/asm-arm/arch-ns9xxx/irqs.h b/include/asm-arm/arch-ns9xxx/irqs.h
index 25d8d28b27f3..e83d48ec42c9 100644
--- a/include/asm-arm/arch-ns9xxx/irqs.h
+++ b/include/asm-arm/arch-ns9xxx/irqs.h
@@ -1,7 +1,7 @@
 /*
  * include/asm-arm/arch-ns9xxx/irqs.h
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -11,38 +11,39 @@
 #ifndef __ASM_ARCH_IRQS_H
 #define __ASM_ARCH_IRQS_H
 
-#define IRQ_WATCHDOG    0
-#define IRQ_AHBBUSERR   1
-#define IRQ_BBUSAGG     2
+/* NetSilicon 9360 */
+#define IRQ_NS9XXX_WATCHDOG     0
+#define IRQ_NS9XXX_AHBBUSERR    1
+#define IRQ_NS9360_BBUSAGG      2
 /* irq 3 is reserved for NS9360 */
-#define IRQ_ETHRX       4
-#define IRQ_ETHTX       5
-#define IRQ_ETHPHY      6
-#define IRQ_LCD         7
-#define IRQ_SERBRX      8
-#define IRQ_SERBTX      9
-#define IRQ_SERARX      10
-#define IRQ_SERATX      11
-#define IRQ_SERCRX      12
-#define IRQ_SERCTX      13
-#define IRQ_I2C         14
-#define IRQ_BBUSDMA     15
-#define IRQ_TIMER0      16
-#define IRQ_TIMER1      17
-#define IRQ_TIMER2      18
-#define IRQ_TIMER3      19
-#define IRQ_TIMER4      20
-#define IRQ_TIMER5      21
-#define IRQ_TIMER6      22
-#define IRQ_TIMER7      23
-#define IRQ_RTC         24
-#define IRQ_USBHOST     25
-#define IRQ_USBDEVICE   26
-#define IRQ_IEEE1284    27
-#define IRQ_EXT0        28
-#define IRQ_EXT1        29
-#define IRQ_EXT2        30
-#define IRQ_EXT3        31
+#define IRQ_NS9XXX_ETHRX        4
+#define IRQ_NS9XXX_ETHTX        5
+#define IRQ_NS9XXX_ETHPHY       6
+#define IRQ_NS9360_LCD          7
+#define IRQ_NS9360_SERBRX       8
+#define IRQ_NS9360_SERBTX       9
+#define IRQ_NS9360_SERARX       10
+#define IRQ_NS9360_SERATX       11
+#define IRQ_NS9360_SERCRX       12
+#define IRQ_NS9360_SERCTX       13
+#define IRQ_NS9360_I2C          14
+#define IRQ_NS9360_BBUSDMA      15
+#define IRQ_NS9360_TIMER0       16
+#define IRQ_NS9360_TIMER1       17
+#define IRQ_NS9360_TIMER2       18
+#define IRQ_NS9360_TIMER3       19
+#define IRQ_NS9360_TIMER4       20
+#define IRQ_NS9360_TIMER5       21
+#define IRQ_NS9360_TIMER6       22
+#define IRQ_NS9360_TIMER7       23
+#define IRQ_NS9360_RTC          24
+#define IRQ_NS9360_USBHOST      25
+#define IRQ_NS9360_USBDEVICE    26
+#define IRQ_NS9360_IEEE1284     27
+#define IRQ_NS9XXX_EXT0         28
+#define IRQ_NS9XXX_EXT1         29
+#define IRQ_NS9XXX_EXT2         30
+#define IRQ_NS9XXX_EXT3         31
 
 #define BBUS_IRQ(irq)   (32 + irq)
 
@@ -67,7 +68,7 @@
 /*
  * these Interrupts are specific for the a9m9750dev board.
  * They are generated by an FPGA that interrupts the CPU on
- * IRQ_EXT2
+ * IRQ_NS9360_EXT2
  */
 #define FPGA_IRQ(irq)   (64 + irq)
 
diff --git a/include/asm-arm/arch-ns9xxx/module.h b/include/asm-arm/arch-ns9xxx/module.h
new file mode 100644
index 000000000000..ac08a31111e4
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/module.h
@@ -0,0 +1,60 @@
+/*
+ * include/asm-arm/arch-ns9xxx/module.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MODULE_H
+#define __ASM_ARCH_MODULE_H
+
+#include <asm/mach-types.h>
+
+#define module_is_cc7ucamry()   (0                      \
+                || machine_is_cc7ucamry()               \
+                )
+
+#define module_is_cc9c()        (0                      \
+                || machine_is_cc9c()                    \
+                )
+
+#define module_is_cc9p9210()    (0                      \
+                || machine_is_cc9p9210()                \
+                || machine_is_cc9p9210js()              \
+                )
+
+#define module_is_cc9p9215()    (0                      \
+                || machine_is_cc9p9215()                \
+                || machine_is_cc9p9215js()              \
+                )
+
+#define module_is_cc9p9360()    (0                      \
+                || machine_is_a9m9360()                 \
+                || machine_is_cc9p9360dev()             \
+                || machine_is_cc9p9360js()              \
+                || machine_is_cc9p9360val()             \
+                )
+
+#define module_is_cc9p9750()    (0                      \
+                || machine_is_a9m9750()                 \
+                || machine_is_cc9p9750dev()             \
+                || machine_is_cc9p9750js()              \
+                || machine_is_cc9p9750val()             \
+                )
+
+#define module_is_ccw9c()       (0                      \
+                || machine_is_ccw9c()                   \
+                )
+
+#define module_is_inc20otter()  (0                      \
+                || machine_is_inc20otter()              \
+                )
+
+#define module_is_otter()       (0                      \
+                || machine_is_otter()                   \
+                )
+
+#endif /* ifndef __ASM_ARCH_MODULE_H */
diff --git a/include/asm-arm/arch-ns9xxx/processor-ns9360.h b/include/asm-arm/arch-ns9xxx/processor-ns9360.h
new file mode 100644
index 000000000000..f3aa6c50dbe5
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/processor-ns9360.h
@@ -0,0 +1,32 @@
+/*
+ * include/asm-arm/arch-ns9xxx/processor-ns9360.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_PROCESSORNS9360_H
+#define __ASM_ARCH_PROCESSORNS9360_H
+
+#include <linux/init.h>
+
+void ns9360_reset(char mode);
+
+unsigned long ns9360_systemclock(void) __attribute__((const));
+
+static inline unsigned long ns9360_cpuclock(void) __attribute__((const));
+static inline unsigned long ns9360_cpuclock(void)
+{
+        return ns9360_systemclock() / 2;
+}
+
+void __init ns9360_map_io(void);
+
+extern struct sys_timer ns9360_timer;
+
+int ns9360_gpio_configure(unsigned gpio, int inv, int func);
+
+#endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */
diff --git a/include/asm-arm/arch-ns9xxx/processor.h b/include/asm-arm/arch-ns9xxx/processor.h
index 223e51b8e104..f7b53b65de81 100644
--- a/include/asm-arm/arch-ns9xxx/processor.h
+++ b/include/asm-arm/arch-ns9xxx/processor.h
@@ -1,7 +1,7 @@
 /*
  * include/asm-arm/arch-ns9xxx/processor.h
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -11,9 +11,32 @@
 #ifndef __ASM_ARCH_PROCESSOR_H
 #define __ASM_ARCH_PROCESSOR_H
 
-#include <asm/mach-types.h>
+#include <asm/arch-ns9xxx/module.h>
 
-#define processor_is_ns9360()   (machine_is_cc9p9360dev()               \
-                || machine_is_cc9p9360js())
+#define processor_is_ns9210()   (0                      \
+                || module_is_cc7ucamry()                \
+                || module_is_cc9p9210()                 \
+                || module_is_inc20otter()               \
+                || module_is_otter()                    \
+                )
+
+#define processor_is_ns9215()   (0                      \
+                || module_is_cc9p9215()                 \
+                )
+
+#define processor_is_ns9360()   (0                      \
+                || module_is_cc9p9360()                 \
+                || module_is_cc9c()                     \
+                || module_is_ccw9c()                    \
+                )
+
+#define processor_is_ns9750()   (0                      \
+                || module_is_cc9p9750()                 \
+                )
+
+#define processor_is_ns921x()   (0                      \
+                || processor_is_ns9210()                \
+                || processor_is_ns9215()                \
+                )
 
 #endif /* ifndef __ASM_ARCH_PROCESSOR_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys-common.h b/include/asm-arm/arch-ns9xxx/regs-sys-common.h
new file mode 100644
index 000000000000..956c57cb781f
--- /dev/null
+++ b/include/asm-arm/arch-ns9xxx/regs-sys-common.h
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/arch-ns9xxx/regs-sys-common.h
+ *
+ * Copyright (C) 2007 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_REGSSYSCOMMON_H
+#define __ASM_ARCH_REGSSYSCOMMON_H
+#include <asm/hardware.h>
+
+/* Interrupt Vector Address Register Level x */
+#define SYS_IVA(x)      __REG2(0xa09000c4, (x))
+
+/* Interrupt Configuration registers */
+#define SYS_IC(x)       __REG2(0xa0900144, (x))
+
+/* ISRADDR */
+#define SYS_ISRADDR     __REG(0xa0900164)
+
+/* Interrupt Status Active */
+#define SYS_ISA         __REG(0xa0900168)
+
+/* Interrupt Status Raw */
+#define SYS_ISR         __REG(0xa090016c)
+
+#endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys.h b/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h
index 749262f86204..318b6945afb6 100644
--- a/include/asm-arm/arch-ns9xxx/regs-sys.h
+++ b/include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h
@@ -1,15 +1,15 @@
 /*
- * include/asm-arm/arch-ns9xxx/regs-sys.h
+ * include/asm-arm/arch-ns9xxx/regs-sys-ns9360.h
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License version 2 as published by
  * the Free Software Foundation.
  */
-#ifndef __ASM_ARCH_REGSSYS_H
-#define __ASM_ARCH_REGSSYS_H
+#ifndef __ASM_ARCH_REGSSYSNS9360_H
+#define __ASM_ARCH_REGSSYSNS9360_H
 
 #include <asm/hardware.h>
 
@@ -27,21 +27,6 @@
 /* Timer x Read register */
 #define SYS_TR(x)       __REG2(0xa0900084, (x))
 
-/* Interrupt Vector Address Register Level x */
-#define SYS_IVA(x)      __REG2(0xa09000c4, (x))
-
-/* Interrupt Configuration registers */
-#define SYS_IC(x)       __REG2(0xa0900144, (x))
-
-/* ISRADDR */
-#define SYS_ISRADDR     __REG(0xa0900164)
-
-/* Interrupt Status Active */
-#define SYS_ISA         __REG(0xa0900168)
-
-/* Interrupt Status Raw */
-#define SYS_ISR         __REG(0xa090016c)
-
 /* Timer Interrupt Status register */
 #define SYS_TIS         __REG(0xa0900170)
 
@@ -160,4 +145,4 @@
 #define SYS_EIC_LVEDG_LEVEL             __REGVAL(SYS_EIC_LVEDG, 0)
 #define SYS_EIC_LVEDG_EDGE              __REGVAL(SYS_EIC_LVEDG, 1)
 
-#endif /* ifndef __ASM_ARCH_REGSSYS_H */
+#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */
diff --git a/include/asm-arm/arch-ns9xxx/system.h b/include/asm-arm/arch-ns9xxx/system.h
index c1082bd8977c..1348073afe48 100644
--- a/include/asm-arm/arch-ns9xxx/system.h
+++ b/include/asm-arm/arch-ns9xxx/system.h
@@ -1,7 +1,7 @@
 /*
  * include/asm-arm/arch-ns9xxx/system.h
  *
- * Copyright (C) 2006 by Digi International Inc.
+ * Copyright (C) 2006,2007 by Digi International Inc.
  * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
@@ -12,8 +12,8 @@
 #define __ASM_ARCH_SYSTEM_H
 
 #include <asm/proc-fns.h>
-#include <asm/arch-ns9xxx/regs-sys.h>
-#include <asm/mach-types.h>
+#include <asm/arch-ns9xxx/processor.h>
+#include <asm/arch-ns9xxx/processor-ns9360.h>
 
 static inline void arch_idle(void)
 {
@@ -22,11 +22,12 @@ static inline void arch_idle(void)
 
 static inline void arch_reset(char mode)
 {
-        u32 reg;
-
-        reg = __raw_readl(SYS_PLL) >> 16;
-        REGSET(reg, SYS_PLL, SWC, YES);
-        __raw_writel(reg, SYS_PLL);
+#ifdef CONFIG_PROCESSOR_NS9360
+        if (processor_is_ns9360())
+                ns9360_reset(mode);
+        else
+#endif
+                BUG();
 
         BUG();
 }
diff --git a/include/asm-arm/arch-ns9xxx/uncompress.h b/include/asm-arm/arch-ns9xxx/uncompress.h
index 961ca7dc9954..71066baceab7 100644
--- a/include/asm-arm/arch-ns9xxx/uncompress.h
+++ b/include/asm-arm/arch-ns9xxx/uncompress.h
@@ -11,20 +11,149 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H
 
-static void putc(char c)
+#include <asm/io.h>
+
+#define __REG(x)        ((void __iomem __force *)(x))
+
+static void putc_dummy(char c, void __iomem *base)
 {
-        volatile u8 *base = (volatile u8 *)0x40000000;
-        int t = 0x10000;
+        /* nothing */
+}
 
+static void putc_ns9360(char c, void __iomem *base)
+{
+        static int t = 0x10000;
+        do {
+                if (t)
+                        --t;
+
+                if (__raw_readl(base + 8) & (1 << 3)) {
+                        __raw_writeb(c, base + 16);
+                        t = 0x10000;
+                        break;
+                }
+        } while (t);
+}
+
+static void putc_a9m9750dev(char c, void __iomem *base)
+{
+        static int t = 0x10000;
+        do {
+                if (t)
+                        --t;
+
+                if (__raw_readb(base + 5) & (1 << 5)) {
+                        __raw_writeb(c, base);
+                        t = 0x10000;
+                        break;
+                }
+        } while (t);
+
+}
+
+static void putc_ns921x(char c, void __iomem *base)
+{
+        static int t = 0x10000;
         do {
-                if (base[5] & 0x20) {
-                        base[0] = c;
+                if (t)
+                        --t;
+
+                if (!(__raw_readl(base) & (1 << 11))) {
+                        __raw_writeb(c, base + 0x0028);
+                        t = 0x10000;
                         break;
                 }
-        } while (--t);
+        } while (t);
 }
 
-#define arch_decomp_setup()
+#define MSCS __REG(0xA0900184)
+
+#define NS9360_UARTA    __REG(0x90200040)
+#define NS9360_UARTB    __REG(0x90200000)
+#define NS9360_UARTC    __REG(0x90300000)
+#define NS9360_UARTD    __REG(0x90300040)
+
+#define NS9360_UART_ENABLED(base)                                       \
+                (__raw_readl(NS9360_UARTA) & (1 << 31))
+
+#define A9M9750DEV_UARTA        __REG(0x40000000)
+
+#define NS921XSYS_CLOCK __REG(0xa090017c)
+#define NS921X_UARTA    __REG(0x90010000)
+#define NS921X_UARTB    __REG(0x90018000)
+#define NS921X_UARTC    __REG(0x90020000)
+#define NS921X_UARTD    __REG(0x90028000)
+
+#define NS921X_UART_ENABLED(base)                                       \
+                (__raw_readl((base) + 0x1000) & (1 << 29))
+
+static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base)
+{
+        if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) {
+                /* ns9360 or ns9750 */
+                if (NS9360_UART_ENABLED(NS9360_UARTA)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTA;
+                        return;
+                } else if (NS9360_UART_ENABLED(NS9360_UARTB)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTB;
+                        return;
+                } else if (NS9360_UART_ENABLED(NS9360_UARTC)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTC;
+                        return;
+                } else if (NS9360_UART_ENABLED(NS9360_UARTD)) {
+                        *putc = putc_ns9360;
+                        *base = NS9360_UARTD;
+                        return;
+                } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) {
+                        *putc = putc_a9m9750dev;
+                        *base = A9M9750DEV_UARTA;
+                        return;
+                }
+        } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) {
+                /* ns921x */
+                u32 clock = __raw_readl(NS921XSYS_CLOCK);
+
+                if ((clock & (1 << 1)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTA)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTA;
+                        return;
+                } else if ((clock & (1 << 2)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTB)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTB;
+                        return;
+                } else if ((clock & (1 << 3)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTC)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTC;
+                        return;
+                } else if ((clock & (1 << 4)) &&
+                                NS921X_UART_ENABLED(NS921X_UARTD)) {
+                        *putc = putc_ns921x;
+                        *base = NS921X_UARTD;
+                        return;
+                }
+        }
+
+        *putc = putc_dummy;
+}
+
+void (*myputc)(char, void __iomem *);
+void __iomem *base;
+
+static void putc(char c)
+{
+        myputc(c, base);
+}
+
+static void arch_decomp_setup(void)
+{
+        autodetect(&myputc, &base);
+}
 #define arch_decomp_wdog()
 
 static void flush(void)
diff --git a/include/asm-arm/arch-orion/io.h b/include/asm-arm/arch-orion/io.h
deleted file mode 100644
index e0b8c39b9167..000000000000
--- a/include/asm-arm/arch-orion/io.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * include/asm-arm/arch-orion/io.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#include "orion.h"
-
-#define IO_SPACE_LIMIT          0xffffffff
-#define IO_SPACE_REMAP          ORION_PCI_SYS_IO_BASE
-
-static inline void __iomem *__io(unsigned long addr)
-{
-        return (void __iomem *)addr;
-}
-
-#define __io(a)                 __io(a)
-#define __mem_pci(a)            (a)
-
-#endif
diff --git a/include/asm-arm/arch-orion/irqs.h b/include/asm-arm/arch-orion/irqs.h
deleted file mode 100644
index eea65ca6076a..000000000000
--- a/include/asm-arm/arch-orion/irqs.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * include/asm-arm/arch-orion/irqs.h
- *
- * IRQ definitions for Orion SoC
- *
- *  Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- *  This file is licensed under the terms of the GNU General Public
- *  License version 2. This program is licensed "as is" without any
- *  warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IRQS_H__
-#define __ASM_ARCH_IRQS_H__
-
-#include "orion.h"      /* need GPIO_MAX */
-
-/*
- * Orion Main Interrupt Controller
- */
-#define IRQ_ORION_BRIDGE        0
-#define IRQ_ORION_DOORBELL_H2C  1
-#define IRQ_ORION_DOORBELL_C2H  2
-#define IRQ_ORION_UART0         3
-#define IRQ_ORION_UART1         4
-#define IRQ_ORION_I2C           5
-#define IRQ_ORION_GPIO_0_7      6
-#define IRQ_ORION_GPIO_8_15     7
-#define IRQ_ORION_GPIO_16_23    8
-#define IRQ_ORION_GPIO_24_31    9
-#define IRQ_ORION_PCIE0_ERR     10
-#define IRQ_ORION_PCIE0_INT     11
-#define IRQ_ORION_USB1_CTRL     12
-#define IRQ_ORION_DEV_BUS_ERR   14
-#define IRQ_ORION_PCI_ERR       15
-#define IRQ_ORION_USB_BR_ERR    16
-#define IRQ_ORION_USB0_CTRL     17
-#define IRQ_ORION_ETH_RX        18
-#define IRQ_ORION_ETH_TX        19
-#define IRQ_ORION_ETH_MISC      20
-#define IRQ_ORION_ETH_SUM       21
-#define IRQ_ORION_ETH_ERR       22
-#define IRQ_ORION_IDMA_ERR      23
-#define IRQ_ORION_IDMA_0        24
-#define IRQ_ORION_IDMA_1        25
-#define IRQ_ORION_IDMA_2        26
-#define IRQ_ORION_IDMA_3        27
-#define IRQ_ORION_CESA          28
-#define IRQ_ORION_SATA          29
-#define IRQ_ORION_XOR0          30
-#define IRQ_ORION_XOR1          31
-
-/*
- * Orion General Purpose Pins
- */
-#define IRQ_ORION_GPIO_START    32
-#define NR_GPIO_IRQS            GPIO_MAX
-
-#define NR_IRQS                 (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
-
-#endif /* __ASM_ARCH_IRQS_H__ */
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
deleted file mode 100644
index 673a418a7419..000000000000
--- a/include/asm-arm/arch-orion/orion.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * include/asm-arm/arch-orion/orion.h
- *
- * Generic definitions of Orion SoC flavors:
- *  Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
- *
- * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_ORION_H__
-#define __ASM_ARCH_ORION_H__
-
-/*****************************************************************************
- * Orion Address Map
- *
- * virt         phys            size
- * fdd00000     f1000000        1M      on-chip peripheral registers
- * fde00000     f2000000        1M      PCIe I/O space
- * fdf00000     f2100000        1M      PCI I/O space
- * fe000000     f0000000        16M     PCIe WA space (Orion-NAS only)
- ****************************************************************************/
-#define ORION_REGS_PHYS_BASE    0xf1000000
-#define ORION_REGS_VIRT_BASE    0xfdd00000
-#define ORION_REGS_SIZE         SZ_1M
-
-#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
-#define ORION_PCIE_IO_VIRT_BASE 0xfde00000
-#define ORION_PCIE_IO_BUS_BASE  0x00000000
-#define ORION_PCIE_IO_SIZE      SZ_1M
-
-#define ORION_PCI_IO_PHYS_BASE  0xf2100000
-#define ORION_PCI_IO_VIRT_BASE  0xfdf00000
-#define ORION_PCI_IO_BUS_BASE   0x00100000
-#define ORION_PCI_IO_SIZE       SZ_1M
-
-/* Relevant only for Orion-NAS */
-#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
-#define ORION_PCIE_WA_VIRT_BASE 0xfe000000
-#define ORION_PCIE_WA_SIZE      SZ_16M
-
-#define ORION_PCIE_MEM_PHYS_BASE        0xe0000000
-#define ORION_PCIE_MEM_SIZE             SZ_128M
-
-#define ORION_PCI_MEM_PHYS_BASE         0xe8000000
-#define ORION_PCI_MEM_SIZE              SZ_128M
-
-/*******************************************************************************
- * Supported Devices & Revisions
- ******************************************************************************/
-/* Orion-1 (88F5181) */
-#define MV88F5181_DEV_ID        0x5181
-#define MV88F5181_REV_B1        3
-/* Orion-NAS (88F5182) */
-#define MV88F5182_DEV_ID        0x5182
-#define MV88F5182_REV_A2        2
-/* Orion-2 (88F5281) */
-#define MV88F5281_DEV_ID        0x5281
-#define MV88F5281_REV_D1        5
-#define MV88F5281_REV_D2        6
-
-/*******************************************************************************
- * Orion Registers Map
- ******************************************************************************/
-#define ORION_DDR_VIRT_BASE             (ORION_REGS_VIRT_BASE | 0x00000)
-#define ORION_DDR_REG(x)                (ORION_DDR_VIRT_BASE | (x))
-
-#define ORION_DEV_BUS_PHYS_BASE         (ORION_REGS_PHYS_BASE | 0x10000)
-#define ORION_DEV_BUS_VIRT_BASE         (ORION_REGS_VIRT_BASE | 0x10000)
-#define ORION_DEV_BUS_REG(x)            (ORION_DEV_BUS_VIRT_BASE | (x))
-#define  I2C_PHYS_BASE                  (ORION_DEV_BUS_PHYS_BASE | 0x1000)
-#define  UART0_PHYS_BASE                (ORION_DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE                (ORION_DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE                (ORION_DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE                (ORION_DEV_BUS_VIRT_BASE | 0x2100)
-
-#define ORION_BRIDGE_VIRT_BASE          (ORION_REGS_VIRT_BASE | 0x20000)
-#define ORION_BRIDGE_REG(x)             (ORION_BRIDGE_VIRT_BASE | (x))
-
-#define ORION_PCI_VIRT_BASE             (ORION_REGS_VIRT_BASE | 0x30000)
-#define ORION_PCI_REG(x)                (ORION_PCI_VIRT_BASE | (x))
-
-#define ORION_PCIE_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0x40000)
-#define ORION_PCIE_REG(x)               (ORION_PCIE_VIRT_BASE | (x))
-
-#define ORION_USB0_PHYS_BASE            (ORION_REGS_PHYS_BASE | 0x50000)
-#define ORION_USB0_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0x50000)
-#define ORION_USB0_REG(x)               (ORION_USB0_VIRT_BASE | (x))
-
-#define ORION_ETH_PHYS_BASE             (ORION_REGS_PHYS_BASE | 0x70000)
-#define ORION_ETH_VIRT_BASE             (ORION_REGS_VIRT_BASE | 0x70000)
-#define ORION_ETH_REG(x)                (ORION_ETH_VIRT_BASE | (x))
-
-#define ORION_SATA_PHYS_BASE            (ORION_REGS_PHYS_BASE | 0x80000)
-#define ORION_SATA_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0x80000)
-#define ORION_SATA_REG(x)               (ORION_SATA_VIRT_BASE | (x))
-
-#define ORION_USB1_PHYS_BASE            (ORION_REGS_PHYS_BASE | 0xa0000)
-#define ORION_USB1_VIRT_BASE            (ORION_REGS_VIRT_BASE | 0xa0000)
-#define ORION_USB1_REG(x)               (ORION_USB1_VIRT_BASE | (x))
-
-/*******************************************************************************
- * Device Bus Registers
- ******************************************************************************/
-#define MPP_0_7_CTRL            ORION_DEV_BUS_REG(0x000)
-#define MPP_8_15_CTRL           ORION_DEV_BUS_REG(0x004)
-#define MPP_16_19_CTRL          ORION_DEV_BUS_REG(0x050)
-#define MPP_DEV_CTRL            ORION_DEV_BUS_REG(0x008)
-#define MPP_RESET_SAMPLE        ORION_DEV_BUS_REG(0x010)
-#define GPIO_OUT                ORION_DEV_BUS_REG(0x100)
-#define GPIO_IO_CONF            ORION_DEV_BUS_REG(0x104)
-#define GPIO_BLINK_EN           ORION_DEV_BUS_REG(0x108)
-#define GPIO_IN_POL             ORION_DEV_BUS_REG(0x10c)
-#define GPIO_DATA_IN            ORION_DEV_BUS_REG(0x110)
-#define GPIO_EDGE_CAUSE         ORION_DEV_BUS_REG(0x114)
-#define GPIO_EDGE_MASK          ORION_DEV_BUS_REG(0x118)
-#define GPIO_LEVEL_MASK         ORION_DEV_BUS_REG(0x11c)
-#define DEV_BANK_0_PARAM        ORION_DEV_BUS_REG(0x45c)
-#define DEV_BANK_1_PARAM        ORION_DEV_BUS_REG(0x460)
-#define DEV_BANK_2_PARAM        ORION_DEV_BUS_REG(0x464)
-#define DEV_BANK_BOOT_PARAM     ORION_DEV_BUS_REG(0x46c)
-#define DEV_BUS_CTRL            ORION_DEV_BUS_REG(0x4c0)
-#define DEV_BUS_INT_CAUSE       ORION_DEV_BUS_REG(0x4d0)
-#define DEV_BUS_INT_MASK        ORION_DEV_BUS_REG(0x4d4)
-#define GPIO_MAX                32
-
-/***************************************************************************
- * Orion CPU Bridge Registers
- **************************************************************************/
-#define CPU_CONF                ORION_BRIDGE_REG(0x100)
-#define CPU_CTRL                ORION_BRIDGE_REG(0x104)
-#define CPU_RESET_MASK          ORION_BRIDGE_REG(0x108)
-#define CPU_SOFT_RESET          ORION_BRIDGE_REG(0x10c)
-#define POWER_MNG_CTRL_REG      ORION_BRIDGE_REG(0x11C)
-#define BRIDGE_CAUSE            ORION_BRIDGE_REG(0x110)
-#define BRIDGE_MASK             ORION_BRIDGE_REG(0x114)
-#define MAIN_IRQ_CAUSE          ORION_BRIDGE_REG(0x200)
-#define MAIN_IRQ_MASK           ORION_BRIDGE_REG(0x204)
-#define TIMER_CTRL              ORION_BRIDGE_REG(0x300)
-#define TIMER_VAL(x)            ORION_BRIDGE_REG(0x314 + ((x) * 8))
-#define TIMER_VAL_RELOAD(x)     ORION_BRIDGE_REG(0x310 + ((x) * 8))
-
-#ifndef __ASSEMBLY__
-
-/*******************************************************************************
- * Helpers to access Orion registers
- ******************************************************************************/
-#include <asm/types.h>
-#include <asm/io.h>
-
-#define orion_read(r)           __raw_readl(r)
-#define orion_write(r, val)     __raw_writel(val, r)
-
-/*
- * These are not preempt safe. Locks, if needed, must be taken care by caller.
- */
-#define orion_setbits(r, mask)  orion_write((r), orion_read(r) | (mask))
-#define orion_clrbits(r, mask)  orion_write((r), orion_read(r) & ~(mask))
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_ARCH_ORION_H__ */
diff --git a/include/asm-arm/arch-orion/timex.h b/include/asm-arm/arch-orion/timex.h
deleted file mode 100644
index 26c2c91eecf0..000000000000
--- a/include/asm-arm/arch-orion/timex.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * include/asm-arm/arch-orion/timex.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#define ORION_TCLK              166666667
-#define CLOCK_TICK_RATE         ORION_TCLK
diff --git a/include/asm-arm/arch-orion/debug-macro.S b/include/asm-arm/arch-orion5x/debug-macro.S
index 2746220f5d85..4f98f3ba2929 100644
--- a/include/asm-arm/arch-orion/debug-macro.S
+++ b/include/asm-arm/arch-orion5x/debug-macro.S
@@ -1,5 +1,5 @@
 /*
- * linux/include/asm-arm/arch-orion/debug-macro.S
+ * include/asm-arm/arch-orion5x/debug-macro.S
  *
  * Debugging macro include header
  *
@@ -8,13 +8,13 @@
  * published by the Free Software Foundation.
 */
 
-#include <asm/arch/orion.h>
+#include <asm/arch/orion5x.h>
 
         .macro  addruart,rx
         mrc     p15, 0, \rx, c1, c0
         tst     \rx, #1                                 @ MMU enabled?
-        ldreq   \rx, =ORION_REGS_PHYS_BASE
-        ldrne   \rx, =ORION_REGS_VIRT_BASE
+        ldreq   \rx, =ORION5X_REGS_PHYS_BASE
+        ldrne   \rx, =ORION5X_REGS_VIRT_BASE
         orr     \rx, \rx, #0x00012000
         .endm
 
diff --git a/include/asm-arm/arch-orion/dma.h b/include/asm-arm/arch-orion5x/dma.h
index 40a8c178f10d..40a8c178f10d 100644
--- a/include/asm-arm/arch-orion/dma.h
+++ b/include/asm-arm/arch-orion5x/dma.h
diff --git a/include/asm-arm/arch-orion/entry-macro.S b/include/asm-arm/arch-orion5x/entry-macro.S
index cda096b2acfd..d8ef54c0ee9a 100644
--- a/include/asm-arm/arch-orion/entry-macro.S
+++ b/include/asm-arm/arch-orion5x/entry-macro.S
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-orion/entry-macro.S
+ * include/asm-arm/arch-orion5x/entry-macro.S
  *
  * Low-level IRQ helper macros for Orion platforms
  *
@@ -8,7 +8,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include <asm/arch/orion.h>
+#include <asm/arch/orion5x.h>
 
         .macro  disable_fiq
         .endm
diff --git a/include/asm-arm/arch-orion/gpio.h b/include/asm-arm/arch-orion5x/gpio.h
index d66284f9a14c..c85e498388b6 100644
--- a/include/asm-arm/arch-orion/gpio.h
+++ b/include/asm-arm/arch-orion5x/gpio.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-orion/gpio.h
+ * include/asm-arm/arch-orion5x/gpio.h
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2. This program is licensed "as is" without any
@@ -12,17 +12,17 @@ extern int gpio_direction_input(unsigned pin);
 extern int gpio_direction_output(unsigned pin, int value);
 extern int gpio_get_value(unsigned pin);
 extern void gpio_set_value(unsigned pin, int value);
-extern void orion_gpio_set_blink(unsigned pin, int blink);
+extern void orion5x_gpio_set_blink(unsigned pin, int blink);
 extern void gpio_display(void);         /* debug */
 
 static inline int gpio_to_irq(int pin)
 {
-        return pin + IRQ_ORION_GPIO_START;
+        return pin + IRQ_ORION5X_GPIO_START;
 }
 
 static inline int irq_to_gpio(int irq)
 {
-        return irq - IRQ_ORION_GPIO_START;
+        return irq - IRQ_ORION5X_GPIO_START;
 }
 
 #include <asm-generic/gpio.h>           /* cansleep wrappers */
diff --git a/include/asm-arm/arch-orion/hardware.h b/include/asm-arm/arch-orion5x/hardware.h
index 65da374de735..5d2d8e0b5630 100644
--- a/include/asm-arm/arch-orion/hardware.h
+++ b/include/asm-arm/arch-orion5x/hardware.h
@@ -1,21 +1,21 @@
 /*
- * include/asm-arm/arch-orion/hardware.h
+ * include/asm-arm/arch-orion5x/hardware.h
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-#ifndef __ASM_ARCH_HARDWARE_H__
-#define __ASM_ARCH_HARDWARE_H__
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
 
-#include "orion.h"
+#include "orion5x.h"
 
 #define pcibios_assign_all_busses()     1
 
 #define PCIBIOS_MIN_IO          0x00001000
 #define PCIBIOS_MIN_MEM         0x01000000
-#define PCIMEM_BASE             ORION_PCIE_MEM_PHYS_BASE
+#define PCIMEM_BASE             ORION5X_PCIE_MEM_PHYS_BASE
 
 
 #endif
diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h
new file mode 100644
index 000000000000..5148ab7ad1f8
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/io.h
@@ -0,0 +1,68 @@
+/*
+ * include/asm-arm/arch-orion5x/io.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "orion5x.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+#define IO_SPACE_REMAP          ORION5X_PCI_SYS_IO_BASE
+
+static inline void __iomem *
+__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
+{
+        void __iomem *retval;
+
+        if (mtype == MT_DEVICE && size && paddr >= ORION5X_REGS_PHYS_BASE &&
+            paddr + size <= ORION5X_REGS_PHYS_BASE + ORION5X_REGS_SIZE) {
+                retval = (void __iomem *)ORION5X_REGS_VIRT_BASE +
+                                (paddr - ORION5X_REGS_PHYS_BASE);
+        } else {
+                retval = __arm_ioremap(paddr, size, mtype);
+        }
+
+        return retval;
+}
+
+static inline void
+__arch_iounmap(void __iomem *addr)
+{
+        if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE ||
+            addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE))
+                __iounmap(addr);
+}
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+
+#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
+#define __arch_iounmap(a)       __arch_iounmap(a)
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+
+/*****************************************************************************
+ * Helpers to access Orion registers
+ ****************************************************************************/
+#define orion5x_read(r)         __raw_readl(r)
+#define orion5x_write(r, val)   __raw_writel(val, r)
+
+/*
+ * These are not preempt-safe.  Locks, if needed, must be taken
+ * care of by the caller.
+ */
+#define orion5x_setbits(r, mask)        orion5x_write((r), orion5x_read(r) | (mask))
+#define orion5x_clrbits(r, mask)        orion5x_write((r), orion5x_read(r) & ~(mask))
+
+
+#endif
diff --git a/include/asm-arm/arch-orion5x/irqs.h b/include/asm-arm/arch-orion5x/irqs.h
new file mode 100644
index 000000000000..abdd61a4833a
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/irqs.h
@@ -0,0 +1,62 @@
+/*
+ * include/asm-arm/arch-orion5x/irqs.h
+ *
+ * IRQ definitions for Orion SoC
+ *
+ *  Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ *  This file is licensed under the terms of the GNU General Public
+ *  License version 2. This program is licensed "as is" without any
+ *  warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "orion5x.h"    /* need GPIO_MAX */
+
+/*
+ * Orion Main Interrupt Controller
+ */
+#define IRQ_ORION5X_BRIDGE              0
+#define IRQ_ORION5X_DOORBELL_H2C        1
+#define IRQ_ORION5X_DOORBELL_C2H        2
+#define IRQ_ORION5X_UART0               3
+#define IRQ_ORION5X_UART1               4
+#define IRQ_ORION5X_I2C                 5
+#define IRQ_ORION5X_GPIO_0_7            6
+#define IRQ_ORION5X_GPIO_8_15           7
+#define IRQ_ORION5X_GPIO_16_23          8
+#define IRQ_ORION5X_GPIO_24_31          9
+#define IRQ_ORION5X_PCIE0_ERR           10
+#define IRQ_ORION5X_PCIE0_INT           11
+#define IRQ_ORION5X_USB1_CTRL           12
+#define IRQ_ORION5X_DEV_BUS_ERR         14
+#define IRQ_ORION5X_PCI_ERR             15
+#define IRQ_ORION5X_USB_BR_ERR          16
+#define IRQ_ORION5X_USB0_CTRL           17
+#define IRQ_ORION5X_ETH_RX              18
+#define IRQ_ORION5X_ETH_TX              19
+#define IRQ_ORION5X_ETH_MISC            20
+#define IRQ_ORION5X_ETH_SUM             21
+#define IRQ_ORION5X_ETH_ERR             22
+#define IRQ_ORION5X_IDMA_ERR            23
+#define IRQ_ORION5X_IDMA_0              24
+#define IRQ_ORION5X_IDMA_1              25
+#define IRQ_ORION5X_IDMA_2              26
+#define IRQ_ORION5X_IDMA_3              27
+#define IRQ_ORION5X_CESA                28
+#define IRQ_ORION5X_SATA                29
+#define IRQ_ORION5X_XOR0                30
+#define IRQ_ORION5X_XOR1                31
+
+/*
+ * Orion General Purpose Pins
+ */
+#define IRQ_ORION5X_GPIO_START  32
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
diff --git a/include/asm-arm/arch-orion/memory.h b/include/asm-arm/arch-orion5x/memory.h
index d954dba87ced..80053a7afc7a 100644
--- a/include/asm-arm/arch-orion/memory.h
+++ b/include/asm-arm/arch-orion5x/memory.h
@@ -1,15 +1,16 @@
 /*
- * include/asm-arm/arch-orion/memory.h
+ * include/asm-arm/arch-orion5x/memory.h
  *
  * Marvell Orion memory definitions
  */
 
-#ifndef __ASM_ARCH_MMU_H
-#define __ASM_ARCH_MMU_H
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
 
 #define PHYS_OFFSET     UL(0x00000000)
 
 #define __virt_to_bus(x)        __virt_to_phys(x)
 #define __bus_to_virt(x)        __phys_to_virt(x)
 
+
 #endif
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
new file mode 100644
index 000000000000..206ddd71e193
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/orion5x.h
@@ -0,0 +1,159 @@
+/*
+ * include/asm-arm/arch-orion5x/orion5x.h
+ *
+ * Generic definitions of Orion SoC flavors:
+ *  Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_ORION5X_H
+#define __ASM_ARCH_ORION5X_H
+
+/*****************************************************************************
+ * Orion Address Maps
+ *
+ * phys
+ * e0000000     PCIe MEM space
+ * e8000000     PCI MEM space
+ * f0000000     PCIe WA space (Orion-1/Orion-NAS only)
+ * f1000000     on-chip peripheral registers
+ * f2000000     PCIe I/O space
+ * f2100000     PCI I/O space
+ * f4000000     device bus mappings (boot)
+ * fa000000     device bus mappings (cs0)
+ * fa800000     device bus mappings (cs2)
+ * fc000000     device bus mappings (cs0/cs1)
+ *
+ * virt         phys            size
+ * fdd00000     f1000000        1M      on-chip peripheral registers
+ * fde00000     f2000000        1M      PCIe I/O space
+ * fdf00000     f2100000        1M      PCI I/O space
+ * fe000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
+ ****************************************************************************/
+#define ORION5X_REGS_PHYS_BASE          0xf1000000
+#define ORION5X_REGS_VIRT_BASE          0xfdd00000
+#define ORION5X_REGS_SIZE               SZ_1M
+
+#define ORION5X_PCIE_IO_PHYS_BASE       0xf2000000
+#define ORION5X_PCIE_IO_VIRT_BASE       0xfde00000
+#define ORION5X_PCIE_IO_BUS_BASE        0x00000000
+#define ORION5X_PCIE_IO_SIZE            SZ_1M
+
+#define ORION5X_PCI_IO_PHYS_BASE        0xf2100000
+#define ORION5X_PCI_IO_VIRT_BASE        0xfdf00000
+#define ORION5X_PCI_IO_BUS_BASE         0x00100000
+#define ORION5X_PCI_IO_SIZE             SZ_1M
+
+/* Relevant only for Orion-1/Orion-NAS */
+#define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
+#define ORION5X_PCIE_WA_VIRT_BASE       0xfe000000
+#define ORION5X_PCIE_WA_SIZE            SZ_16M
+
+#define ORION5X_PCIE_MEM_PHYS_BASE      0xe0000000
+#define ORION5X_PCIE_MEM_SIZE           SZ_128M
+
+#define ORION5X_PCI_MEM_PHYS_BASE       0xe8000000
+#define ORION5X_PCI_MEM_SIZE            SZ_128M
+
+/*******************************************************************************
+ * Supported Devices & Revisions
+ ******************************************************************************/
+/* Orion-1 (88F5181) */
+#define MV88F5181_DEV_ID        0x5181
+#define MV88F5181_REV_B1        3
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID        0x5182
+#define MV88F5182_REV_A2        2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID        0x5281
+#define MV88F5281_REV_D1        5
+#define MV88F5281_REV_D2        6
+
+/*******************************************************************************
+ * Orion Registers Map
+ ******************************************************************************/
+#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
+#define ORION5X_DDR_REG(x)              (ORION5X_DDR_VIRT_BASE | (x))
+
+#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
+#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
+#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
+#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
+
+#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE | 0x20000)
+#define ORION5X_BRIDGE_REG(x)           (ORION5X_BRIDGE_VIRT_BASE | (x))
+#define  TIMER_VIRT_BASE                (ORION5X_BRIDGE_VIRT_BASE | 0x300)
+
+#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x30000)
+#define ORION5X_PCI_REG(x)              (ORION5X_PCI_VIRT_BASE | (x))
+
+#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x40000)
+#define ORION5X_PCIE_REG(x)             (ORION5X_PCIE_VIRT_BASE | (x))
+
+#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x50000)
+#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x50000)
+#define ORION5X_USB0_REG(x)             (ORION5X_USB0_VIRT_BASE | (x))
+
+#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x70000)
+#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x70000)
+#define ORION5X_ETH_REG(x)              (ORION5X_ETH_VIRT_BASE | (x))
+
+#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
+#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
+#define ORION5X_SATA_REG(x)             (ORION5X_SATA_VIRT_BASE | (x))
+
+#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
+#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
+#define ORION5X_USB1_REG(x)             (ORION5X_USB1_VIRT_BASE | (x))
+
+/*******************************************************************************
+ * Device Bus Registers
+ ******************************************************************************/
+#define MPP_0_7_CTRL            ORION5X_DEV_BUS_REG(0x000)
+#define MPP_8_15_CTRL           ORION5X_DEV_BUS_REG(0x004)
+#define MPP_16_19_CTRL          ORION5X_DEV_BUS_REG(0x050)
+#define MPP_DEV_CTRL            ORION5X_DEV_BUS_REG(0x008)
+#define MPP_RESET_SAMPLE        ORION5X_DEV_BUS_REG(0x010)
+#define GPIO_OUT                ORION5X_DEV_BUS_REG(0x100)
+#define GPIO_IO_CONF            ORION5X_DEV_BUS_REG(0x104)
+#define GPIO_BLINK_EN           ORION5X_DEV_BUS_REG(0x108)
+#define GPIO_IN_POL             ORION5X_DEV_BUS_REG(0x10c)
+#define GPIO_DATA_IN            ORION5X_DEV_BUS_REG(0x110)
+#define GPIO_EDGE_CAUSE         ORION5X_DEV_BUS_REG(0x114)
+#define GPIO_EDGE_MASK          ORION5X_DEV_BUS_REG(0x118)
+#define GPIO_LEVEL_MASK         ORION5X_DEV_BUS_REG(0x11c)
+#define DEV_BANK_0_PARAM        ORION5X_DEV_BUS_REG(0x45c)
+#define DEV_BANK_1_PARAM        ORION5X_DEV_BUS_REG(0x460)
+#define DEV_BANK_2_PARAM        ORION5X_DEV_BUS_REG(0x464)
+#define DEV_BANK_BOOT_PARAM     ORION5X_DEV_BUS_REG(0x46c)
+#define DEV_BUS_CTRL            ORION5X_DEV_BUS_REG(0x4c0)
+#define DEV_BUS_INT_CAUSE       ORION5X_DEV_BUS_REG(0x4d0)
+#define DEV_BUS_INT_MASK        ORION5X_DEV_BUS_REG(0x4d4)
+#define GPIO_MAX                32
+
+/***************************************************************************
+ * Orion CPU Bridge Registers
+ **************************************************************************/
+#define CPU_CONF                ORION5X_BRIDGE_REG(0x100)
+#define CPU_CTRL                ORION5X_BRIDGE_REG(0x104)
+#define CPU_RESET_MASK          ORION5X_BRIDGE_REG(0x108)
+#define CPU_SOFT_RESET          ORION5X_BRIDGE_REG(0x10c)
+#define POWER_MNG_CTRL_REG      ORION5X_BRIDGE_REG(0x11C)
+#define BRIDGE_CAUSE            ORION5X_BRIDGE_REG(0x110)
+#define BRIDGE_MASK             ORION5X_BRIDGE_REG(0x114)
+#define  BRIDGE_INT_TIMER0      0x0002
+#define  BRIDGE_INT_TIMER1      0x0004
+#define MAIN_IRQ_CAUSE          ORION5X_BRIDGE_REG(0x200)
+#define MAIN_IRQ_MASK           ORION5X_BRIDGE_REG(0x204)
+
+
+#endif
diff --git a/include/asm-arm/arch-orion/system.h b/include/asm-arm/arch-orion5x/system.h
index 17704c68f90e..3f1d1e2d38f8 100644
--- a/include/asm-arm/arch-orion/system.h
+++ b/include/asm-arm/arch-orion5x/system.h
@@ -1,10 +1,10 @@
 /*
- * include/asm-arm/arch-orion/system.h
+ * include/asm-arm/arch-orion5x/system.h
  *
  * Tzachi Perelstein <tzachi@marvell.com>
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
@@ -12,7 +12,7 @@
 #define __ASM_ARCH_SYSTEM_H
 
 #include <asm/arch/hardware.h>
-#include <asm/arch/orion.h>
+#include <asm/arch/orion5x.h>
 
 static inline void arch_idle(void)
 {
@@ -24,8 +24,9 @@ static inline void arch_reset(char mode)
         /*
          * Enable and issue soft reset
          */
-        orion_setbits(CPU_RESET_MASK, (1 << 2));
-        orion_setbits(CPU_SOFT_RESET, 1);
+        orion5x_setbits(CPU_RESET_MASK, (1 << 2));
+        orion5x_setbits(CPU_SOFT_RESET, 1);
 }
 
+
 #endif
diff --git a/include/asm-arm/arch-orion5x/timex.h b/include/asm-arm/arch-orion5x/timex.h
new file mode 100644
index 000000000000..31c568e28cc3
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/timex.h
@@ -0,0 +1,13 @@
+/*
+ * include/asm-arm/arch-orion5x/timex.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
+
+#define ORION5X_TCLK            166666667
diff --git a/include/asm-arm/arch-orion/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h
index 59f44039909a..5c13d4fafb4e 100644
--- a/include/asm-arm/arch-orion/uncompress.h
+++ b/include/asm-arm/arch-orion5x/uncompress.h
@@ -1,14 +1,14 @@
 /*
- * include/asm-arm/arch-orion/uncompress.h
+ * include/asm-arm/arch-orion5x/uncompress.h
  *
  * Tzachi Perelstein <tzachi@marvell.com>
  *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#include <asm/arch/orion.h>
+#include <asm/arch/orion5x.h>
 
 #define MV_UART_THR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
 #define MV_UART_LSR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
diff --git a/include/asm-arm/arch-orion/vmalloc.h b/include/asm-arm/arch-orion5x/vmalloc.h
index 9d580278d2bc..2b3061e90dc1 100644
--- a/include/asm-arm/arch-orion/vmalloc.h
+++ b/include/asm-arm/arch-orion5x/vmalloc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-arm/arch-orion/vmalloc.h
+ * include/asm-arm/arch-orion5x/vmalloc.h
  */
 
 #define VMALLOC_END       0xfd800000
diff --git a/include/asm-arm/arch-pxa/camera.h b/include/asm-arm/arch-pxa/camera.h
new file mode 100644
index 000000000000..39516ced8b1f
--- /dev/null
+++ b/include/asm-arm/arch-pxa/camera.h
@@ -0,0 +1,48 @@
+/*
+    camera.h - PXA camera driver header file
+
+    Copyright (C) 2003, Intel Corporation
+    Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef __ASM_ARCH_CAMERA_H_
+#define __ASM_ARCH_CAMERA_H_
+
+#define PXA_CAMERA_MASTER       1
+#define PXA_CAMERA_DATAWIDTH_4  2
+#define PXA_CAMERA_DATAWIDTH_5  4
+#define PXA_CAMERA_DATAWIDTH_8  8
+#define PXA_CAMERA_DATAWIDTH_9  0x10
+#define PXA_CAMERA_DATAWIDTH_10 0x20
+#define PXA_CAMERA_PCLK_EN      0x40
+#define PXA_CAMERA_MCLK_EN      0x80
+#define PXA_CAMERA_PCP          0x100
+#define PXA_CAMERA_HSP          0x200
+#define PXA_CAMERA_VSP          0x400
+
+struct pxacamera_platform_data {
+        int (*init)(struct device *);
+        int (*power)(struct device *, int);
+        int (*reset)(struct device *, int);
+
+        unsigned long flags;
+        unsigned long mclk_10khz;
+};
+
+extern void pxa_set_camera_info(struct pxacamera_platform_data *);
+
+#endif /* __ASM_ARCH_CAMERA_H_ */
diff --git a/include/asm-arm/arch-pxa/gumstix.h b/include/asm-arm/arch-pxa/gumstix.h
new file mode 100644
index 000000000000..6fa85c4f94f8
--- /dev/null
+++ b/include/asm-arm/arch-pxa/gumstix.h
@@ -0,0 +1,96 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/gumstix.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+/* BTRESET - Reset line to Bluetooth module, active low signal. */
+#define GPIO_GUMSTIX_BTRESET          7
+#define GPIO_GUMSTIX_BTRESET_MD         (GPIO_GUMSTIX_BTRESET | GPIO_OUT)
+
+
+/*
+GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean
+interrupt signal for determining cable presence. On the original gumstix,
+this is GPIO81, and GPIO83 needs to be defined as well. On the gumstix F,
+this moves to GPIO17 and GPIO37. */
+
+/* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn
+has detected a cable insertion; driven low otherwise. */
+
+#ifdef CONFIG_ARCH_GUMSTIX_ORIG
+
+#define GPIO_GUMSTIX_USB_GPIOn          81
+#define GPIO_GUMSTIX_USB_GPIOx          83
+
+#else
+
+#define GPIO_GUMSTIX_USB_GPIOn          35
+#define GPIO_GUMSTIX_USB_GPIOx          41
+
+#endif
+
+/* usb state change */
+#define GUMSTIX_USB_INTR_IRQ            IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn)
+
+#define GPIO_GUMSTIX_USB_GPIOn_MD       (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)
+#define GPIO_GUMSTIX_USB_GPIOx_CON_MD   (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)
+#define GPIO_GUMSTIX_USB_GPIOx_DIS_MD   (GPIO_GUMSTIX_USB_GPIOx | GPIO_IN)
+
+/*
+ * SD/MMC definitions
+ */
+#define GUMSTIX_GPIO_nSD_WP             22 /* SD Write Protect */
+#define GUMSTIX_GPIO_nSD_DETECT         11 /* MMC/SD Card Detect */
+#define GUMSTIX_IRQ_GPIO_nSD_DETECT     IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT)
+
+/*
+ * SMC Ethernet definitions
+ * ETH_RST provides a hardware reset line to the ethernet chip
+ * ETH is the IRQ line in from the ethernet chip to the PXA
+ */
+#define GPIO_GUMSTIX_ETH0_RST           80
+#define GPIO_GUMSTIX_ETH0_RST_MD        (GPIO_GUMSTIX_ETH0_RST | GPIO_OUT)
+#define GPIO_GUMSTIX_ETH1_RST           52
+#define GPIO_GUMSTIX_ETH1_RST_MD        (GPIO_GUMSTIX_ETH1_RST | GPIO_OUT)
+
+#define GPIO_GUMSTIX_ETH0               36
+#define GPIO_GUMSTIX_ETH0_MD            (GPIO_GUMSTIX_ETH0 | GPIO_IN)
+#define GUMSTIX_ETH0_IRQ                IRQ_GPIO(GPIO_GUMSTIX_ETH0)
+#define GPIO_GUMSTIX_ETH1               27
+#define GPIO_GUMSTIX_ETH1_MD            (GPIO_GUMSTIX_ETH1 | GPIO_IN)
+#define GUMSTIX_ETH1_IRQ                IRQ_GPIO(GPIO_GUMSTIX_ETH1)
+
+
+/* CF reset line */
+#define GPIO8_RESET                     8
+
+/* CF slot 0 */
+#define GPIO4_nBVD1                     4
+#define GPIO4_nSTSCHG                   GPIO4_nBVD1
+#define GPIO11_nCD                      11
+#define GPIO26_PRDY_nBSY                26
+#define GUMSTIX_S0_nSTSCHG_IRQ          IRQ_GPIO(GPIO4_nSTSCHG)
+#define GUMSTIX_S0_nCD_IRQ              IRQ_GPIO(GPIO11_nCD)
+#define GUMSTIX_S0_PRDY_nBSY_IRQ        IRQ_GPIO(GPIO26_PRDY_nBSY)
+
+/* CF slot 1 */
+#define GPIO18_nBVD1                    18
+#define GPIO18_nSTSCHG                  GPIO18_nBVD1
+#define GPIO36_nCD                      36
+#define GPIO27_PRDY_nBSY                27
+#define GUMSTIX_S1_nSTSCHG_IRQ          IRQ_GPIO(GPIO18_nSTSCHG)
+#define GUMSTIX_S1_nCD_IRQ              IRQ_GPIO(GPIO36_nCD)
+#define GUMSTIX_S1_PRDY_nBSY_IRQ        IRQ_GPIO(GPIO27_PRDY_nBSY)
+
+/* CF GPIO line modes */
+#define GPIO4_nSTSCHG_MD                (GPIO4_nSTSCHG | GPIO_IN)
+#define GPIO8_RESET_MD                  (GPIO8_RESET | GPIO_OUT)
+#define GPIO11_nCD_MD                   (GPIO11_nCD | GPIO_IN)
+#define GPIO18_nSTSCHG_MD               (GPIO18_nSTSCHG | GPIO_IN)
+#define GPIO26_PRDY_nBSY_MD             (GPIO26_PRDY_nBSY | GPIO_IN)
+#define GPIO27_PRDY_nBSY_MD             (GPIO27_PRDY_nBSY | GPIO_IN)
+#define GPIO36_nCD_MD                   (GPIO36_nCD | GPIO_IN)
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h
index 748406f384c2..99f4f423a8e1 100644
--- a/include/asm-arm/arch-pxa/irda.h
+++ b/include/asm-arm/arch-pxa/irda.h
@@ -10,6 +10,8 @@
 struct pxaficp_platform_data {
         int transceiver_cap;
         void (*transceiver_mode)(struct device *dev, int mode);
+        int (*startup)(struct device *dev);
+        void (*shutdown)(struct device *dev);
 };
 
 extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index c562b972a4a6..50c77eacbd5e 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -181,7 +181,8 @@
 #elif defined(CONFIG_ARCH_LUBBOCK) || \
       defined(CONFIG_MACH_LOGICPD_PXA270) || \
       defined(CONFIG_MACH_MAINSTONE) || \
-      defined(CONFIG_MACH_PCM027)
+      defined(CONFIG_MACH_PCM027) || \
+      defined(CONFIG_MACH_MAGICIAN)
 #define NR_IRQS                 (IRQ_BOARD_END)
 #else
 #define NR_IRQS                 (IRQ_BOARD_START)
diff --git a/include/asm-arm/arch-pxa/magician.h b/include/asm-arm/arch-pxa/magician.h
index 337f51f06b3a..b34fd5683e2d 100644
--- a/include/asm-arm/arch-pxa/magician.h
+++ b/include/asm-arm/arch-pxa/magician.h
@@ -12,7 +12,8 @@
 #ifndef _MAGICIAN_H_
 #define _MAGICIAN_H_
 
-#include <asm/arch/pxa-regs.h>
+#include <asm/arch/irqs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 
 /*
  * PXA GPIOs
@@ -34,6 +35,7 @@
 #define GPIO48_MAGICIAN_UNKNOWN                 48
 #define GPIO56_MAGICIAN_UNKNOWN                 56
 #define GPIO57_MAGICIAN_CAM_RESET               57
+#define GPIO75_MAGICIAN_SAMSUNG_POWER           75
 #define GPIO83_MAGICIAN_nIR_EN                  83
 #define GPIO86_MAGICIAN_GSM_RESET               86
 #define GPIO87_MAGICIAN_GSM_SELECT              87
@@ -81,6 +83,7 @@
 #define GPIO48_MAGICIAN_UNKNOWN_MD              (48 | GPIO_OUT)
 #define GPIO56_MAGICIAN_UNKNOWN_MD              (56 | GPIO_OUT)
 #define GPIO57_MAGICIAN_CAM_RESET_MD            (57 | GPIO_OUT)
+#define GPIO75_MAGICIAN_SAMSUNG_POWER_MD        (75 | GPIO_OUT)
 #define GPIO83_MAGICIAN_nIR_EN_MD               (83 | GPIO_OUT)
 #define GPIO86_MAGICIAN_GSM_RESET_MD            (86 | GPIO_OUT)
 #define GPIO87_MAGICIAN_GSM_SELECT_MD           (87 | GPIO_OUT)
@@ -108,4 +111,56 @@
 #define GPIO119_MAGICIAN_UNKNOWN_MD             (119 | GPIO_OUT)
 #define GPIO120_MAGICIAN_UNKNOWN_MD             (120 | GPIO_OUT)
 
+/*
+ * CPLD IRQs
+ */
+
+#define IRQ_MAGICIAN_SD         (IRQ_BOARD_START + 0)
+#define IRQ_MAGICIAN_EP         (IRQ_BOARD_START + 1)
+#define IRQ_MAGICIAN_BT         (IRQ_BOARD_START + 2)
+#define IRQ_MAGICIAN_AC         (IRQ_BOARD_START + 3)
+
+/*
+ * CPLD EGPIOs
+ */
+
+#define MAGICIAN_EGPIO_BASE                     0x80 /* GPIO_BOARD_START */
+#define MAGICIAN_EGPIO(reg,bit) \
+        (MAGICIAN_EGPIO_BASE + 8*reg + bit)
+
+/* output */
+
+#define EGPIO_MAGICIAN_TOPPOLY_POWER            MAGICIAN_EGPIO(0, 2)
+#define EGPIO_MAGICIAN_LED_POWER                MAGICIAN_EGPIO(0, 5)
+#define EGPIO_MAGICIAN_GSM_RESET                MAGICIAN_EGPIO(0, 6)
+#define EGPIO_MAGICIAN_LCD_POWER                MAGICIAN_EGPIO(0, 7)
+#define EGPIO_MAGICIAN_SPK_POWER                MAGICIAN_EGPIO(1, 0)
+#define EGPIO_MAGICIAN_EP_POWER                 MAGICIAN_EGPIO(1, 1)
+#define EGPIO_MAGICIAN_IN_SEL0                  MAGICIAN_EGPIO(1, 2)
+#define EGPIO_MAGICIAN_IN_SEL1                  MAGICIAN_EGPIO(1, 3)
+#define EGPIO_MAGICIAN_MIC_POWER                MAGICIAN_EGPIO(1, 4)
+#define EGPIO_MAGICIAN_CODEC_RESET              MAGICIAN_EGPIO(1, 5)
+#define EGPIO_MAGICIAN_CODEC_POWER              MAGICIAN_EGPIO(1, 6)
+#define EGPIO_MAGICIAN_BL_POWER                 MAGICIAN_EGPIO(1, 7)
+#define EGPIO_MAGICIAN_SD_POWER                 MAGICIAN_EGPIO(2, 0)
+#define EGPIO_MAGICIAN_CARKIT_MIC               MAGICIAN_EGPIO(2, 1)
+#define EGPIO_MAGICIAN_UNKNOWN_WAVEDEV_DLL      MAGICIAN_EGPIO(2, 2)
+#define EGPIO_MAGICIAN_FLASH_VPP                MAGICIAN_EGPIO(2, 3)
+#define EGPIO_MAGICIAN_BL_POWER2                MAGICIAN_EGPIO(2, 4)
+#define EGPIO_MAGICIAN_CHARGE_EN                MAGICIAN_EGPIO(2, 5)
+#define EGPIO_MAGICIAN_GSM_POWER                MAGICIAN_EGPIO(2, 7)
+
+/* input */
+
+#define EGPIO_MAGICIAN_CABLE_STATE_AC           MAGICIAN_EGPIO(4, 0)
+#define EGPIO_MAGICIAN_CABLE_STATE_USB          MAGICIAN_EGPIO(4, 1)
+
+#define EGPIO_MAGICIAN_BOARD_ID0                MAGICIAN_EGPIO(5, 0)
+#define EGPIO_MAGICIAN_BOARD_ID1                MAGICIAN_EGPIO(5, 1)
+#define EGPIO_MAGICIAN_BOARD_ID2                MAGICIAN_EGPIO(5, 2)
+#define EGPIO_MAGICIAN_LCD_SELECT               MAGICIAN_EGPIO(5, 3)
+#define EGPIO_MAGICIAN_nSD_READONLY             MAGICIAN_EGPIO(5, 4)
+
+#define EGPIO_MAGICIAN_EP_INSERT                MAGICIAN_EGPIO(6, 1)
+
 #endif /* _MAGICIAN_H_ */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa25x.h b/include/asm-arm/arch-pxa/mfp-pxa25x.h
new file mode 100644
index 000000000000..0499323010ba
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa25x.h
@@ -0,0 +1,161 @@
+#ifndef __ASM_ARCH_MFP_PXA25X_H
+#define __ASM_ARCH_MFP_PXA25X_H
+
+#include <asm/arch/mfp.h>
+#include <asm/arch/mfp-pxa2xx.h>
+
+/* GPIO */
+#define GPIO2_GPIO              MFP_CFG_IN(GPIO2, AF0)
+#define GPIO3_GPIO              MFP_CFG_IN(GPIO3, AF0)
+#define GPIO4_GPIO              MFP_CFG_IN(GPIO4, AF0)
+#define GPIO5_GPIO              MFP_CFG_IN(GPIO5, AF0)
+#define GPIO6_GPIO              MFP_CFG_IN(GPIO6, AF0)
+#define GPIO7_GPIO              MFP_CFG_IN(GPIO7, AF0)
+#define GPIO8_GPIO              MFP_CFG_IN(GPIO8, AF0)
+
+#define GPIO1_RST               MFP_CFG_IN(GPIO1, AF1)
+
+/* Crystal and Clock Signals */
+#define GPIO10_RTCCLK           MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
+#define GPIO70_RTC_CLK          MFP_CFG_OUT(GPIO70, AF1, DRIVE_LOW)
+#define GPIO7_48MHz             MFP_CFG_OUT(GPIO7,  AF1, DRIVE_LOW)
+#define GPIO11_3_6MHz           MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
+#define GPIO71_3_6MHz           MFP_CFG_OUT(GPIO71, AF1, DRIVE_LOW)
+#define GPIO12_32KHz            MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
+#define GPIO72_32kHz            MFP_CFG_OUT(GPIO72, AF1, DRIVE_LOW)
+
+/* SDRAM and Static Memory I/O Signals */
+#define GPIO15_nCS_1            MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
+#define GPIO78_nCS_2            MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
+#define GPIO79_nCS_3            MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
+#define GPIO80_nCS_4            MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
+#define GPIO33_nCS_5            MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
+
+/* Miscellaneous I/O and DMA Signals */
+#define GPIO18_RDY              MFP_CFG_IN(GPIO18, AF1)
+#define GPIO20_DREQ_0           MFP_CFG_IN(GPIO20, AF1)
+#define GPIO19_DREQ_1           MFP_CFG_IN(GPIO19, AF1)
+
+/* Alternate Bus Master Mode I/O Signals */
+#define GPIO13_MBGNT            MFP_CFG_OUT(GPIO13, AF2, DRIVE_LOW)
+#define GPIO73_MBGNT            MFP_CFG_OUT(GPIO73, AF1, DRIVE_LOW)
+#define GPIO14_MBREQ            MFP_CFG_IN(GPIO14, AF1)
+#define GPIO66_MBREQ            MFP_CFG_IN(GPIO66, AF1)
+
+/* PC CARD */
+#define GPIO52_nPCE_1           MFP_CFG_OUT(GPIO52, AF2, DRIVE_HIGH)
+#define GPIO53_nPCE_2           MFP_CFG_OUT(GPIO53, AF2, DRIVE_HIGH)
+#define GPIO55_nPREG            MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
+#define GPIO50_nPIOR            MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
+#define GPIO51_nPIOW            MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
+#define GPIO49_nPWE             MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
+#define GPIO48_nPOE             MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
+#define GPIO57_nIOIS16          MFP_CFG_IN(GPIO57, AF1)
+#define GPIO56_nPWAIT           MFP_CFG_IN(GPIO56, AF1)
+#define GPIO54_nPSKTSEL         MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
+
+/* FFUART */
+#define GPIO34_FFUART_RXD       MFP_CFG_IN(GPIO34, AF1)
+#define GPIO35_FFUART_CTS       MFP_CFG_IN(GPIO35, AF1)
+#define GPIO36_FFUART_DCD       MFP_CFG_IN(GPIO36, AF1)
+#define GPIO37_FFUART_DSR       MFP_CFG_IN(GPIO37, AF1)
+#define GPIO38_FFUART_RI        MFP_CFG_IN(GPIO38, AF1)
+#define GPIO39_FFUART_TXD       MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
+#define GPIO40_FFUART_DTR       MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
+#define GPIO41_FFUART_RTS       MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
+
+/* BTUART */
+#define GPIO42_BTUART_RXD       MFP_CFG_IN(GPIO42, AF1)
+#define GPIO43_BTUART_TXD       MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
+#define GPIO44_BTUART_CTS       MFP_CFG_IN(GPIO44, AF1)
+#define GPIO45_BTUART_RTS       MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
+
+/* STUART */
+#define GPIO46_STUART_RXD       MFP_CFG_IN(GPIO46, AF2)
+#define GPIO47_STUART_TXD       MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
+
+/* HWUART */
+#define GPIO42_HWUART_RXD       MFP_CFG_IN(GPIO42, AF3)
+#define GPIO43_HWUART_TXD       MFP_CFG_OUT(GPIO43, AF3, DRIVE_HIGH)
+#define GPIO44_HWUART_CTS       MFP_CFG_IN(GPIO44, AF3)
+#define GPIO45_HWUART_RTS       MFP_CFG_OUT(GPIO45, AF3, DRIVE_HIGH)
+#define GPIO48_HWUART_TXD       MFP_CFG_OUT(GPIO48, AF1, DRIVE_HIGH)
+#define GPIO49_HWUART_RXD       MFP_CFG_IN(GPIO49, AF1)
+#define GPIO50_HWUART_CTS       MFP_CFG_IN(GPIO50, AF1)
+#define GPIO51_HWUART_RTS       MFP_CFG_OUT(GPIO51, AF1, DRIVE_HIGH)
+
+/* FICP */
+#define GPIO46_FICP_RXD         MFP_CFG_IN(GPIO46, AF1)
+#define GPIO47_FICP_TXD         MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
+
+/* PWM 0/1 */
+#define GPIO16_PWM0_OUT         MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
+#define GPIO17_PWM1_OUT         MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
+
+/* AC97 */
+#define GPIO28_AC97_BITCLK      MFP_CFG_IN(GPIO28, AF1)
+#define GPIO29_AC97_SDATA_IN_0  MFP_CFG_IN(GPIO29, AF1)
+#define GPIO30_AC97_SDATA_OUT   MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
+#define GPIO31_AC97_SYNC        MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
+#define GPIO32_AC97_SDATA_IN_1  MFP_CFG_IN(GPIO32, AF1)
+
+/* I2S */
+#define GPIO28_I2S_BITCLK_IN    MFP_CFG_IN(GPIO28, AF2)
+#define GPIO28_I2S_BITCLK_OUT   MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
+#define GPIO29_I2S_SDATA_IN     MFP_CFG_IN(GPIO29, AF2)
+#define GPIO30_I2S_SDATA_OUT    MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
+#define GPIO31_I2S_SYNC         MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
+#define GPIO32_I2S_SYSCLK       MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
+
+/* SSP 1 */
+#define GPIO23_SSP1_SCLK        MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
+#define GPIO24_SSP1_SFRM        MFP_CFG_OUT(GPIO24, AF2, DRIVE_LOW)
+#define GPIO25_SSP1_TXD         MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
+#define GPIO26_SSP1_RXD         MFP_CFG_IN(GPIO26, AF1)
+#define GPIO27_SSP1_EXTCLK      MFP_CFG_IN(GPIO27, AF1)
+
+/* SSP 2 - NSSP */
+#define GPIO81_SSP2_CLK_OUT     MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
+#define GPIO81_SSP2_CLK_IN      MFP_CFG_IN(GPIO81, AF1)
+#define GPIO82_SSP2_FRM_OUT     MFP_CFG_OUT(GPIO82, AF1, DRIVE_LOW)
+#define GPIO82_SSP2_FRM_IN      MFP_CFG_IN(GPIO82, AF1)
+#define GPIO83_SSP2_TXD         MFP_CFG_OUT(GPIO83, AF1, DRIVE_LOW)
+#define GPIO83_SSP2_RXD         MFP_CFG_IN(GPIO83, AF2)
+#define GPIO84_SSP2_TXD         MFP_CFG_OUT(GPIO84, AF1, DRIVE_LOW)
+#define GPIO84_SSP2_RXD         MFP_CFG_IN(GPIO84, AF2)
+
+/* MMC */
+#define GPIO6_MMC_CLK           MFP_CFG_OUT(GPIO6, AF1, DRIVE_LOW)
+#define GPIO8_MMC_CS0           MFP_CFG_OUT(GPIO8, AF1, DRIVE_LOW)
+#define GPIO9_MMC_CS1           MFP_CFG_OUT(GPIO9, AF1, DRIVE_LOW)
+#define GPIO34_MMC_CS0          MFP_CFG_OUT(GPIO34, AF2, DRIVE_LOW)
+#define GPIO39_MMC_CS1          MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
+#define GPIO53_MMC_CLK          MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
+#define GPIO54_MMC_CLK          MFP_CFG_OUT(GPIO54, AF1, DRIVE_LOW)
+#define GPIO69_MMC_CLK          MFP_CFG_OUT(GPIO69, AF1, DRIVE_LOW)
+#define GPIO67_MMC_CS0          MFP_CFG_OUT(GPIO67, AF1, DRIVE_LOW)
+#define GPIO68_MMC_CS1          MFP_CFG_OUT(GPIO68, AF1, DRIVE_LOW)
+
+/* LCD */
+#define GPIO58_LCD_LDD_0        MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
+#define GPIO59_LCD_LDD_1        MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
+#define GPIO60_LCD_LDD_2        MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
+#define GPIO61_LCD_LDD_3        MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
+#define GPIO62_LCD_LDD_4        MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
+#define GPIO63_LCD_LDD_5        MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
+#define GPIO64_LCD_LDD_6        MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
+#define GPIO65_LCD_LDD_7        MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
+#define GPIO66_LCD_LDD_8        MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
+#define GPIO67_LCD_LDD_9        MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
+#define GPIO68_LCD_LDD_10       MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
+#define GPIO69_LCD_LDD_11       MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
+#define GPIO70_LCD_LDD_12       MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
+#define GPIO71_LCD_LDD_13       MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
+#define GPIO72_LCD_LDD_14       MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
+#define GPIO73_LCD_LDD_15       MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
+#define GPIO74_LCD_FCLK         MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
+#define GPIO75_LCD_LCLK         MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
+#define GPIO76_LCD_PCLK         MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
+#define GPIO77_LCD_ACBIAS       MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
+
+#endif /* __ASM_ARCH_MFP_PXA25X_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa27x.h b/include/asm-arm/arch-pxa/mfp-pxa27x.h
new file mode 100644
index 000000000000..eb6eaa174f8d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa27x.h
@@ -0,0 +1,432 @@
+#ifndef __ASM_ARCH_MFP_PXA27X_H
+#define __ASM_ARCH_MFP_PXA27X_H
+
+/*
+ * NOTE:  for those special-function bidirectional GPIOs, as described
+ * in the "PXA27x Developer's Manual" Section 24.4.2.1, only its input
+ * alternative is preserved, the direction is actually selected by the
+ * specific controller, and this should work in most cases.
+ */
+
+#include <asm/arch/mfp.h>
+#include <asm/arch/mfp-pxa2xx.h>
+
+/* GPIO */
+#define GPIO85_GPIO             MFP_CFG_IN(GPIO85, AF0)
+#define GPIO86_GPIO             MFP_CFG_IN(GPIO86, AF0)
+#define GPIO87_GPIO             MFP_CFG_IN(GPIO87, AF0)
+#define GPIO88_GPIO             MFP_CFG_IN(GPIO88, AF0)
+#define GPIO89_GPIO             MFP_CFG_IN(GPIO89, AF0)
+#define GPIO90_GPIO             MFP_CFG_IN(GPIO90, AF0)
+#define GPIO91_GPIO             MFP_CFG_IN(GPIO91, AF0)
+#define GPIO92_GPIO             MFP_CFG_IN(GPIO92, AF0)
+#define GPIO93_GPIO             MFP_CFG_IN(GPIO93, AF0)
+#define GPIO94_GPIO             MFP_CFG_IN(GPIO94, AF0)
+#define GPIO95_GPIO             MFP_CFG_IN(GPIO95, AF0)
+#define GPIO96_GPIO             MFP_CFG_IN(GPIO96, AF0)
+#define GPIO97_GPIO             MFP_CFG_IN(GPIO97, AF0)
+#define GPIO98_GPIO             MFP_CFG_IN(GPIO98, AF0)
+#define GPIO99_GPIO             MFP_CFG_IN(GPIO99, AF0)
+#define GPIO100_GPIO            MFP_CFG_IN(GPIO100, AF0)
+#define GPIO101_GPIO            MFP_CFG_IN(GPIO101, AF0)
+#define GPIO102_GPIO            MFP_CFG_IN(GPIO102, AF0)
+#define GPIO103_GPIO            MFP_CFG_IN(GPIO103, AF0)
+#define GPIO104_GPIO            MFP_CFG_IN(GPIO104, AF0)
+#define GPIO105_GPIO            MFP_CFG_IN(GPIO105, AF0)
+#define GPIO106_GPIO            MFP_CFG_IN(GPIO106, AF0)
+#define GPIO107_GPIO            MFP_CFG_IN(GPIO107, AF0)
+#define GPIO108_GPIO            MFP_CFG_IN(GPIO108, AF0)
+#define GPIO109_GPIO            MFP_CFG_IN(GPIO109, AF0)
+#define GPIO110_GPIO            MFP_CFG_IN(GPIO110, AF0)
+#define GPIO111_GPIO            MFP_CFG_IN(GPIO111, AF0)
+#define GPIO112_GPIO            MFP_CFG_IN(GPIO112, AF0)
+#define GPIO113_GPIO            MFP_CFG_IN(GPIO113, AF0)
+#define GPIO114_GPIO            MFP_CFG_IN(GPIO114, AF0)
+#define GPIO115_GPIO            MFP_CFG_IN(GPIO115, AF0)
+#define GPIO116_GPIO            MFP_CFG_IN(GPIO116, AF0)
+#define GPIO117_GPIO            MFP_CFG_IN(GPIO117, AF0)
+#define GPIO118_GPIO            MFP_CFG_IN(GPIO118, AF0)
+#define GPIO119_GPIO            MFP_CFG_IN(GPIO119, AF0)
+#define GPIO120_GPIO            MFP_CFG_IN(GPIO120, AF0)
+
+/* Crystal and Clock Signals */
+#define GPIO9_HZ_CLK            MFP_CFG_OUT(GPIO9,  AF1, DRIVE_LOW)
+#define GPIO10_HZ_CLK           MFP_CFG_OUT(GPIO10, AF1, DRIVE_LOW)
+#define GPIO11_48_MHz           MFP_CFG_OUT(GPIO11, AF3, DRIVE_LOW)
+#define GPIO12_48_MHz           MFP_CFG_OUT(GPIO12, AF3, DRIVE_LOW)
+#define GPIO13_CLK_EXT          MFP_CFG_IN(GPIO13, AF1)
+
+/* OS Timer Signals */
+#define GPIO11_EXT_SYNC_0       MFP_CFG_IN(GPIO11, AF1)
+#define GPIO12_EXT_SYNC_1       MFP_CFG_IN(GPIO12, AF1)
+#define GPIO9_CHOUT_0           MFP_CFG_OUT(GPIO9,  AF3, DRIVE_LOW)
+#define GPIO10_CHOUT_1          MFP_CFG_OUT(GPIO10, AF3, DRIVE_LOW)
+#define GPIO11_CHOUT_0          MFP_CFG_OUT(GPIO11, AF1, DRIVE_LOW)
+#define GPIO12_CHOUT_1          MFP_CFG_OUT(GPIO12, AF1, DRIVE_LOW)
+
+/* SDRAM and Static Memory I/O Signals */
+#define GPIO20_nSDCS_2          MFP_CFG_OUT(GPIO20, AF1, DRIVE_HIGH)
+#define GPIO21_nSDCS_3          MFP_CFG_OUT(GPIO21, AF1, DRIVE_HIGH)
+#define GPIO15_nCS_1            MFP_CFG_OUT(GPIO15, AF2, DRIVE_HIGH)
+#define GPIO78_nCS_2            MFP_CFG_OUT(GPIO78, AF2, DRIVE_HIGH)
+#define GPIO79_nCS_3            MFP_CFG_OUT(GPIO79, AF2, DRIVE_HIGH)
+#define GPIO80_nCS_4            MFP_CFG_OUT(GPIO80, AF2, DRIVE_HIGH)
+#define GPIO33_nCS_5            MFP_CFG_OUT(GPIO33, AF2, DRIVE_HIGH)
+
+/* Miscellaneous I/O and DMA Signals */
+#define GPIO21_DVAL_0           MFP_CFG_OUT(GPIO21, AF2, DRIVE_HIGH)
+#define GPIO116_DVAL_0          MFP_CFG_OUT(GPIO116, AF1, DRIVE_HIGH)
+#define GPIO33_DVAL_1           MFP_CFG_OUT(GPIO33, AF1, DRIVE_HIGH)
+#define GPIO96_DVAL_1           MFP_CFG_OUT(GPIO96, AF2, DRIVE_HIGH)
+#define GPIO18_RDY              MFP_CFG_IN(GPIO18, AF1)
+#define GPIO20_DREQ_0           MFP_CFG_IN(GPIO20, AF1)
+#define GPIO115_DREQ_0          MFP_CFG_IN(GPIO115, AF1)
+#define GPIO80_DREQ_1           MFP_CFG_IN(GPIO80, AF1)
+#define GPIO97_DREQ_1           MFP_CFG_IN(GPIO97, AF2)
+#define GPIO85_DREQ_2           MFP_CFG_IN(GPIO85, AF2)
+#define GPIO100_DREQ_2          MFP_CFG_IN(GPIO100, AF2)
+
+/* Alternate Bus Master Mode I/O Signals */
+#define GPIO20_MBREQ            MFP_CFG_IN(GPIO20, AF2)
+#define GPIO80_MBREQ            MFP_CFG_IN(GPIO80, AF2)
+#define GPIO96_MBREQ            MFP_CFG_IN(GPIO96, AF2)
+#define GPIO115_MBREQ           MFP_CFG_IN(GPIO115, AF3)
+#define GPIO21_MBGNT            MFP_CFG_OUT(GPIO21, AF3, DRIVE_LOW)
+#define GPIO33_MBGNT            MFP_CFG_OUT(GPIO33, AF3, DRIVE_LOW)
+#define GPIO97_MBGNT            MFP_CFG_OUT(GPIO97, AF2, DRIVE_LOW)
+#define GPIO116_MBGNT           MFP_CFG_OUT(GPIO116, AF3, DRIVE_LOW)
+
+/* PC CARD */
+#define GPIO15_nPCE_1           MFP_CFG_OUT(GPIO15, AF1, DRIVE_HIGH)
+#define GPIO85_nPCE_1           MFP_CFG_OUT(GPIO85, AF1, DRIVE_HIGH)
+#define GPIO86_nPCE_1           MFP_CFG_OUT(GPIO86, AF1, DRIVE_HIGH)
+#define GPIO102_nPCE_1          MFP_CFG_OUT(GPIO102, AF1, DRIVE_HIGH)
+#define GPIO54_nPCE_2           MFP_CFG_OUT(GPIO54, AF2, DRIVE_HIGH)
+#define GPIO78_nPCE_2           MFP_CFG_OUT(GPIO78, AF1, DRIVE_HIGH)
+#define GPIO87_nPCE_2           MFP_CFG_IN(GPIO87, AF1)
+#define GPIO55_nPREG            MFP_CFG_OUT(GPIO55, AF2, DRIVE_HIGH)
+#define GPIO50_nPIOR            MFP_CFG_OUT(GPIO50, AF2, DRIVE_HIGH)
+#define GPIO51_nPIOW            MFP_CFG_OUT(GPIO51, AF2, DRIVE_HIGH)
+#define GPIO49_nPWE             MFP_CFG_OUT(GPIO49, AF2, DRIVE_HIGH)
+#define GPIO48_nPOE             MFP_CFG_OUT(GPIO48, AF2, DRIVE_HIGH)
+#define GPIO57_nIOIS16          MFP_CFG_IN(GPIO57, AF1)
+#define GPIO56_nPWAIT           MFP_CFG_IN(GPIO56, AF1)
+#define GPIO79_PSKTSEL          MFP_CFG_OUT(GPIO79, AF1, DRIVE_HIGH)
+
+/* I2C */
+#define GPIO117_I2C_SCL         MFP_CFG_IN(GPIO117, AF1)
+#define GPIO118_I2C_SDA         MFP_CFG_IN(GPIO118, AF1)
+
+/* FFUART */
+#define GPIO9_FFUART_CTS        MFP_CFG_IN(GPIO9, AF3)
+#define GPIO26_FFUART_CTS       MFP_CFG_IN(GPIO26, AF3)
+#define GPIO35_FFUART_CTS       MFP_CFG_IN(GPIO35, AF1)
+#define GPIO100_FFUART_CTS      MFP_CFG_IN(GPIO100, AF3)
+#define GPIO10_FFUART_DCD       MFP_CFG_IN(GPIO10, AF1)
+#define GPIO36_FFUART_DCD       MFP_CFG_IN(GPIO36, AF1)
+#define GPIO33_FFUART_DSR       MFP_CFG_IN(GPIO33, AF2)
+#define GPIO37_FFUART_DSR       MFP_CFG_IN(GPIO37, AF1)
+#define GPIO38_FFUART_RI        MFP_CFG_IN(GPIO38, AF1)
+#define GPIO89_FFUART_RI        MFP_CFG_IN(GPIO89, AF3)
+#define GPIO19_FFUART_RXD       MFP_CFG_IN(GPIO19, AF3)
+#define GPIO33_FFUART_RXD       MFP_CFG_IN(GPIO33, AF1)
+#define GPIO34_FFUART_RXD       MFP_CFG_IN(GPIO34, AF1)
+#define GPIO41_FFUART_RXD       MFP_CFG_IN(GPIO41, AF1)
+#define GPIO53_FFUART_RXD       MFP_CFG_IN(GPIO53, AF1)
+#define GPIO85_FFUART_RXD       MFP_CFG_IN(GPIO85, AF1)
+#define GPIO96_FFUART_RXD       MFP_CFG_IN(GPIO96, AF3)
+#define GPIO102_FFUART_RXD      MFP_CFG_IN(GPIO102, AF3)
+#define GPIO16_FFUART_TXD       MFP_CFG_OUT(GPIO16, AF3, DRIVE_HIGH)
+#define GPIO37_FFUART_TXD       MFP_CFG_OUT(GPIO37, AF3, DRIVE_HIGH)
+#define GPIO39_FFUART_TXD       MFP_CFG_OUT(GPIO39, AF2, DRIVE_HIGH)
+#define GPIO83_FFUART_TXD       MFP_CFG_OUT(GPIO83, AF2, DRIVE_HIGH)
+#define GPIO99_FFUART_TXD       MFP_CFG_OUT(GPIO99, AF3, DRIVE_HIGH)
+#define GPIO27_FFUART_RTS       MFP_CFG_OUT(GPIO27, AF3, DRIVE_HIGH)
+#define GPIO41_FFUART_RTS       MFP_CFG_OUT(GPIO41, AF2, DRIVE_HIGH)
+#define GPIO83_FFUART_RTS       MFP_CFG_OUT(GPIO83, AF3, DRIVE_HIGH)
+#define GPIO98_FFUART_RTS       MFP_CFG_OUT(GPIO98, AF3, DRIVE_HIGH)
+#define GPIO40_FFUART_DTR       MFP_CFG_OUT(GPIO40, AF2, DRIVE_HIGH)
+#define GPIO82_FFUART_DTR       MFP_CFG_OUT(GPIO82, AF3, DRIVE_HIGH)
+
+/* BTUART */
+#define GPIO44_BTUART_CTS       MFP_CFG_IN(GPIO44, AF1)
+#define GPIO42_BTUART_RXD       MFP_CFG_IN(GPIO42, AF1)
+#define GPIO45_BTUART_RTS       MFP_CFG_OUT(GPIO45, AF2, DRIVE_HIGH)
+#define GPIO43_BTUART_TXD       MFP_CFG_OUT(GPIO43, AF2, DRIVE_HIGH)
+
+/* STUART */
+#define GPIO46_STUART_RXD       MFP_CFG_IN(GPIO46, AF2)
+#define GPIO47_STUART_TXD       MFP_CFG_OUT(GPIO47, AF1, DRIVE_HIGH)
+
+/* FICP */
+#define GPIO42_FICP_RXD         MFP_CFG_IN(GPIO42, AF2)
+#define GPIO46_FICP_RXD         MFP_CFG_IN(GPIO46, AF1)
+#define GPIO43_FICP_TXD         MFP_CFG_OUT(GPIO43, AF1, DRIVE_HIGH)
+#define GPIO47_FICP_TXD         MFP_CFG_OUT(GPIO47, AF2, DRIVE_HIGH)
+
+/* PWM 0/1/2/3 */
+#define GPIO11_PWM2_OUT         MFP_CFG_OUT(GPIO11, AF2, DRIVE_LOW)
+#define GPIO12_PWM3_OUT         MFP_CFG_OUT(GPIO12, AF2, DRIVE_LOW)
+#define GPIO16_PWM0_OUT         MFP_CFG_OUT(GPIO16, AF2, DRIVE_LOW)
+#define GPIO17_PWM1_OUT         MFP_CFG_OUT(GPIO17, AF2, DRIVE_LOW)
+#define GPIO38_PWM1_OUT         MFP_CFG_OUT(GPIO38, AF3, DRIVE_LOW)
+#define GPIO46_PWM2_OUT         MFP_CFG_OUT(GPIO46, AF2, DRIVE_LOW)
+#define GPIO47_PWM3_OUT         MFP_CFG_OUT(GPIO47, AF3, DRIVE_LOW)
+#define GPIO79_PWM2_OUT         MFP_CFG_OUT(GPIO79, AF3, DRIVE_LOW)
+#define GPIO80_PWM3_OUT         MFP_CFG_OUT(GPIO80, AF3, DRIVE_LOW)
+#define GPIO115_PWM1_OUT        MFP_CFG_OUT(GPIO115, AF3, DRIVE_LOW)
+
+/* AC97 */
+#define GPIO31_AC97_SYNC        MFP_CFG_OUT(GPIO31, AF2, DRIVE_LOW)
+#define GPIO94_AC97_SYNC        MFP_CFG_OUT(GPIO94, AF1, DRIVE_LOW)
+#define GPIO30_AC97_SDATA_OUT   MFP_CFG_OUT(GPIO30, AF2, DRIVE_LOW)
+#define GPIO93_AC97_SDATA_OUT   MFP_CFG_OUT(GPIO93, AF1, DRIVE_LOW)
+#define GPIO45_AC97_SYSCLK      MFP_CFG_OUT(GPIO45, AF1, DRIVE_LOW)
+#define GPIO89_AC97_SYSCLK      MFP_CFG_OUT(GPIO89, AF1, DRIVE_LOW)
+#define GPIO98_AC97_SYSCLK      MFP_CFG_OUT(GPIO98, AF1, DRIVE_LOW)
+#define GPIO95_AC97_nRESET      MFP_CFG_OUT(GPIO95, AF1, DRIVE_LOW)
+#define GPIO113_AC97_nRESET     MFP_CFG_OUT(GPIO113, AF2, DRIVE_LOW)
+#define GPIO28_AC97_BITCLK      MFP_CFG_IN(GPIO28, AF1)
+#define GPIO29_AC97_SDATA_IN_0  MFP_CFG_IN(GPIO29, AF1)
+#define GPIO116_AC97_SDATA_IN_0 MFP_CFG_IN(GPIO116, AF2)
+#define GPIO99_AC97_SDATA_IN_1  MFP_CFG_IN(GPIO99, AF2)
+
+/* I2S */
+#define GPIO28_I2S_BITCLK_IN    MFP_CFG_IN(GPIO28, AF2)
+#define GPIO28_I2S_BITCLK_OUT   MFP_CFG_OUT(GPIO28, AF1, DRIVE_LOW)
+#define GPIO29_I2S_SDATA_IN     MFP_CFG_IN(GPIO29, AF2)
+#define GPIO30_I2S_SDATA_OUT    MFP_CFG_OUT(GPIO30, AF1, DRIVE_LOW)
+#define GPIO31_I2S_SYNC         MFP_CFG_OUT(GPIO31, AF1, DRIVE_LOW)
+#define GPIO113_I2S_SYSCLK      MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW)
+
+/* SSP 1 */
+#define GPIO23_SSP1_SCLK        MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
+#define GPIO29_SSP1_SCLK        MFP_CFG_IN(GPIO29, AF3)
+#define GPIO27_SSP1_SYSCLK      MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW)
+#define GPIO53_SSP1_SYSCLK      MFP_CFG_OUT(GPIO53, AF3, DRIVE_LOW)
+#define GPIO24_SSP1_SFRM        MFP_CFG_IN(GPIO24, AF2)
+#define GPIO28_SSP1_SFRM        MFP_CFG_IN(GPIO28, AF3)
+#define GPIO25_SSP1_TXD         MFP_CFG_OUT(GPIO25, AF2, DRIVE_LOW)
+#define GPIO57_SSP1_TXD         MFP_CFG_OUT(GPIO57, AF3, DRIVE_LOW)
+#define GPIO26_SSP1_RXD         MFP_CFG_IN(GPIO26, AF1)
+#define GPIO27_SSP1_SCLKEN      MFP_CFG_IN(GPIO27, AF2)
+
+/* SSP 2 */
+#define GPIO19_SSP2_SCLK        MFP_CFG_IN(GPIO19, AF1)
+#define GPIO22_SSP2_SCLK        MFP_CFG_IN(GPIO22, AF3)
+#define GPIO29_SSP2_SCLK        MFP_CFG_OUT(GPIO29, AF3, DRIVE_LOW)
+#define GPIO36_SSP2_SCLK        MFP_CFG_IN(GPIO36, AF2)
+#define GPIO50_SSP2_SCLK        MFP_CFG_IN(GPIO50, AF3)
+#define GPIO22_SSP2_SYSCLK      MFP_CFG_OUT(GPIO22, AF2, DRIVE_LOW)
+#define GPIO14_SSP2_SFRM        MFP_CFG_IN(GPIO14, AF2)
+#define GPIO37_SSP2_SFRM        MFP_CFG_IN(GPIO37, AF2)
+#define GPIO87_SSP2_SFRM        MFP_CFG_OUT(GPIO87, AF3, DRIVE_LOW)
+#define GPIO88_SSP2_SFRM        MFP_CFG_IN(GPIO88, AF3)
+#define GPIO13_SSP2_TXD         MFP_CFG_OUT(GPIO13, AF1, DRIVE_LOW)
+#define GPIO38_SSP2_TXD         MFP_CFG_OUT(GPIO38, AF2, DRIVE_LOW)
+#define GPIO87_SSP2_TXD         MFP_CFG_OUT(GPIO87, AF1, DRIVE_LOW)
+#define GPIO89_SSP2_TXD         MFP_CFG_OUT(GPIO89, AF3, DRIVE_LOW)
+#define GPIO11_SSP2_RXD         MFP_CFG_IN(GPIO11, AF2)
+#define GPIO29_SSP2_RXD         MFP_CFG_OUT(GPIO29, AF1, DRIVE_LOW)
+#define GPIO40_SSP2_RXD         MFP_CFG_IN(GPIO40, AF1)
+#define GPIO86_SSP2_RXD         MFP_CFG_IN(GPIO86, AF1)
+#define GPIO88_SSP2_RXD         MFP_CFG_IN(GPIO88, AF2)
+#define GPIO22_SSP2_EXTCLK      MFP_CFG_IN(GPIO22, AF1)
+#define GPIO27_SSP2_EXTCLK      MFP_CFG_IN(GPIO27, AF1)
+#define GPIO22_SSP2_SCLKEN      MFP_CFG_IN(GPIO22, AF2)
+#define GPIO23_SSP2_SCLKEN      MFP_CFG_IN(GPIO23, AF2)
+
+/* SSP 3 */
+#define GPIO34_SSP3_SCLK        MFP_CFG_IN(GPIO34, AF3)
+#define GPIO40_SSP3_SCLK        MFP_CFG_OUT(GPIO40, AF3, DRIVE_LOW)
+#define GPIO52_SSP3_SCLK        MFP_CFG_IN(GPIO52, AF2)
+#define GPIO84_SSP3_SCLK        MFP_CFG_IN(GPIO84, AF1)
+#define GPIO45_SSP3_SYSCLK      MFP_CFG_OUT(GPIO45, AF3, DRIVE_LOW)
+#define GPIO35_SSP3_SFRM        MFP_CFG_IN(GPIO35, AF3)
+#define GPIO39_SSP3_SFRM        MFP_CFG_IN(GPIO39, AF3)
+#define GPIO83_SSP3_SFRM        MFP_CFG_IN(GPIO83, AF1)
+#define GPIO35_SSP3_TXD         MFP_CFG_OUT(GPIO35, AF3, DRIVE_LOW)
+#define GPIO38_SSP3_TXD         MFP_CFG_OUT(GPIO38, AF1, DRIVE_LOW)
+#define GPIO81_SSP3_TXD         MFP_CFG_OUT(GPIO81, AF1, DRIVE_LOW)
+#define GPIO41_SSP3_RXD         MFP_CFG_IN(GPIO41, AF3)
+#define GPIO82_SSP3_RXD         MFP_CFG_IN(GPIO82, AF1)
+#define GPIO89_SSP3_RXD         MFP_CFG_IN(GPIO89, AF1)
+
+/* MMC */
+#define GPIO32_MMC_CLK          MFP_CFG_OUT(GPIO32, AF2, DRIVE_LOW)
+#define GPIO92_MMC_DAT_0        MFP_CFG_IN(GPIO92, AF1)
+#define GPIO109_MMC_DAT_1       MFP_CFG_IN(GPIO109, AF1)
+#define GPIO110_MMC_DAT_2       MFP_CFG_IN(GPIO110, AF1)
+#define GPIO111_MMC_DAT_3       MFP_CFG_IN(GPIO111, AF1)
+#define GPIO112_MMC_CMD         MFP_CFG_IN(GPIO112, AF1)
+
+/* LCD */
+#define GPIO58_LCD_LDD_0        MFP_CFG_OUT(GPIO58, AF2, DRIVE_LOW)
+#define GPIO59_LCD_LDD_1        MFP_CFG_OUT(GPIO59, AF2, DRIVE_LOW)
+#define GPIO60_LCD_LDD_2        MFP_CFG_OUT(GPIO60, AF2, DRIVE_LOW)
+#define GPIO61_LCD_LDD_3        MFP_CFG_OUT(GPIO61, AF2, DRIVE_LOW)
+#define GPIO62_LCD_LDD_4        MFP_CFG_OUT(GPIO62, AF2, DRIVE_LOW)
+#define GPIO63_LCD_LDD_5        MFP_CFG_OUT(GPIO63, AF2, DRIVE_LOW)
+#define GPIO64_LCD_LDD_6        MFP_CFG_OUT(GPIO64, AF2, DRIVE_LOW)
+#define GPIO65_LCD_LDD_7        MFP_CFG_OUT(GPIO65, AF2, DRIVE_LOW)
+#define GPIO66_LCD_LDD_8        MFP_CFG_OUT(GPIO66, AF2, DRIVE_LOW)
+#define GPIO67_LCD_LDD_9        MFP_CFG_OUT(GPIO67, AF2, DRIVE_LOW)
+#define GPIO68_LCD_LDD_10       MFP_CFG_OUT(GPIO68, AF2, DRIVE_LOW)
+#define GPIO69_LCD_LDD_11       MFP_CFG_OUT(GPIO69, AF2, DRIVE_LOW)
+#define GPIO70_LCD_LDD_12       MFP_CFG_OUT(GPIO70, AF2, DRIVE_LOW)
+#define GPIO71_LCD_LDD_13       MFP_CFG_OUT(GPIO71, AF2, DRIVE_LOW)
+#define GPIO72_LCD_LDD_14       MFP_CFG_OUT(GPIO72, AF2, DRIVE_LOW)
+#define GPIO73_LCD_LDD_15       MFP_CFG_OUT(GPIO73, AF2, DRIVE_LOW)
+#define GPIO86_LCD_LDD_16       MFP_CFG_OUT(GPIO86, AF2, DRIVE_LOW)
+#define GPIO87_LCD_LDD_17       MFP_CFG_OUT(GPIO87, AF2, DRIVE_LOW)
+#define GPIO74_LCD_FCLK         MFP_CFG_OUT(GPIO74, AF2, DRIVE_LOW)
+#define GPIO75_LCD_LCLK         MFP_CFG_OUT(GPIO75, AF2, DRIVE_LOW)
+#define GPIO76_LCD_PCLK         MFP_CFG_OUT(GPIO76, AF2, DRIVE_LOW)
+#define GPIO77_LCD_BIAS         MFP_CFG_OUT(GPIO77, AF2, DRIVE_LOW)
+#define GPIO14_LCD_VSYNC        MFP_CFG_IN(GPIO14, AF1)
+#define GPIO19_LCD_CS           MFP_CFG_OUT(GPIO19, AF2, DRIVE_LOW)
+
+/* Keypad */
+#define GPIO93_KP_DKIN_0        MFP_CFG_IN(GPIO93, AF1)
+#define GPIO94_KP_DKIN_1        MFP_CFG_IN(GPIO94, AF1)
+#define GPIO95_KP_DKIN_2        MFP_CFG_IN(GPIO95, AF1)
+#define GPIO96_KP_DKIN_3        MFP_CFG_IN(GPIO96, AF1)
+#define GPIO97_KP_DKIN_4        MFP_CFG_IN(GPIO97, AF1)
+#define GPIO98_KP_DKIN_5        MFP_CFG_IN(GPIO98, AF1)
+#define GPIO99_KP_DKIN_6        MFP_CFG_IN(GPIO99, AF1)
+#define GPIO13_KP_KDIN_7        MFP_CFG_IN(GPIO13, AF2)
+#define GPIO100_KP_MKIN_0       MFP_CFG_IN(GPIO100, AF1)
+#define GPIO101_KP_MKIN_1       MFP_CFG_IN(GPIO101, AF1)
+#define GPIO102_KP_MKIN_2       MFP_CFG_IN(GPIO102, AF1)
+#define GPIO34_KP_MKIN_3        MFP_CFG_IN(GPIO34, AF2)
+#define GPIO37_KP_MKIN_3        MFP_CFG_IN(GPIO37, AF3)
+#define GPIO97_KP_MKIN_3        MFP_CFG_IN(GPIO97, AF3)
+#define GPIO98_KP_MKIN_4        MFP_CFG_IN(GPIO98, AF3)
+#define GPIO38_KP_MKIN_4        MFP_CFG_IN(GPIO38, AF2)
+#define GPIO39_KP_MKIN_4        MFP_CFG_IN(GPIO39, AF1)
+#define GPIO16_KP_MKIN_5        MFP_CFG_IN(GPIO16, AF1)
+#define GPIO90_KP_MKIN_5        MFP_CFG_IN(GPIO90, AF1)
+#define GPIO99_KP_MKIN_5        MFP_CFG_IN(GPIO99, AF3)
+#define GPIO17_KP_MKIN_6        MFP_CFG_IN(GPIO17, AF1)
+#define GPIO91_KP_MKIN_6        MFP_CFG_IN(GPIO91, AF1)
+#define GPIO95_KP_MKIN_6        MFP_CFG_IN(GPIO95, AF3)
+#define GPIO13_KP_MKIN_7        MFP_CFG_IN(GPIO13, AF3)
+#define GPIO36_KP_MKIN_7        MFP_CFG_IN(GPIO36, AF3)
+#define GPIO103_KP_MKOUT_0      MFP_CFG_OUT(GPIO103, AF2, DRIVE_HIGH)
+#define GPIO104_KP_MKOUT_1      MFP_CFG_OUT(GPIO104, AF2, DRIVE_HIGH)
+#define GPIO105_KP_MKOUT_2      MFP_CFG_OUT(GPIO105, AF2, DRIVE_HIGH)
+#define GPIO106_KP_MKOUT_3      MFP_CFG_OUT(GPIO106, AF2, DRIVE_HIGH)
+#define GPIO107_KP_MKOUT_4      MFP_CFG_OUT(GPIO107, AF2, DRIVE_HIGH)
+#define GPIO108_KP_MKOUT_5      MFP_CFG_OUT(GPIO108, AF2, DRIVE_HIGH)
+#define GPIO35_KP_MKOUT_6       MFP_CFG_OUT(GPIO35, AF2, DRIVE_HIGH)
+#define GPIO22_KP_MKOUT_7       MFP_CFG_OUT(GPIO22, AF1, DRIVE_HIGH)
+#define GPIO40_KP_MKOUT_6       MFP_CFG_OUT(GPIO40, AF1, DRIVE_HIGH)
+#define GPIO41_KP_MKOUT_7       MFP_CFG_OUT(GPIO41, AF1, DRIVE_HIGH)
+#define GPIO96_KP_MKOUT_6       MFP_CFG_OUT(GPIO96, AF3, DRIVE_HIGH)
+
+/* USB P3 */
+#define GPIO10_USB_P3_5         MFP_CFG_IN(GPIO10, AF3)
+#define GPIO11_USB_P3_1         MFP_CFG_IN(GPIO11, AF3)
+#define GPIO30_USB_P3_2         MFP_CFG_OUT(GPIO30, AF3, DRIVE_LOW)
+#define GPIO31_USB_P3_6         MFP_CFG_OUT(GPIO31, AF3, DRIVE_LOW)
+#define GPIO56_USB_P3_4         MFP_CFG_OUT(GPIO56, AF1, DRIVE_LOW)
+#define GPIO86_USB_P3_5         MFP_CFG_IN(GPIO86, AF3)
+#define GPIO87_USB_P3_1         MFP_CFG_IN(GPIO87, AF3)
+#define GPIO90_USB_P3_5         MFP_CFG_IN(GPIO90, AF2)
+#define GPIO91_USB_P3_1         MFP_CFG_IN(GPIO91, AF2)
+#define GPIO113_USB_P3_3        MFP_CFG_IN(GPIO113, AF3)
+
+/* USB P2 */
+#define GPIO34_USB_P2_2         MFP_CFG_OUT(GPIO34, AF1, DRIVE_LOW)
+#define GPIO35_USB_P2_1         MFP_CFG_IN(GPIO35, AF2)
+#define GPIO36_USB_P2_4         MFP_CFG_OUT(GPIO36, AF1, DRIVE_LOW)
+#define GPIO37_USB_P2_8         MFP_CFG_OUT(GPIO37, AF1, DRIVE_LOW)
+#define GPIO38_USB_P2_3         MFP_CFG_IN(GPIO38, AF3)
+#define GPIO39_USB_P2_6         MFP_CFG_OUT(GPIO39, AF1, DRIVE_LOW)
+#define GPIO40_USB_P2_5         MFP_CFG_IN(GPIO40, AF3)
+#define GPIO41_USB_P2_7         MFP_CFG_IN(GPIO41, AF2)
+#define GPIO53_USB_P2_3         MFP_CFG_IN(GPIO53, AF2)
+
+/* USB Host Port 1/2 */
+#define GPIO88_USBH1_PWR        MFP_CFG_IN(GPIO88, AF1)
+#define GPIO89_USBH1_PEN        MFP_CFG_OUT(GPIO89, AF2, DRIVE_LOW)
+#define GPIO119_USBH2_PWR       MFP_CFG_IN(GPIO119, AF1)
+#define GPIO120_USBH2_PEN       MFP_CFG_OUT(GPIO120, AF2, DRIVE_LOW)
+
+/* QCI - default to Master Mode: CIF_FV/CIF_LV Direction In */
+#define GPIO115_CIF_DD_3        MFP_CFG_IN(GPIO115, AF2)
+#define GPIO116_CIF_DD_2        MFP_CFG_IN(GPIO116, AF1)
+#define GPIO12_CIF_DD_7         MFP_CFG_IN(GPIO12, AF2)
+#define GPIO17_CIF_DD_6         MFP_CFG_IN(GPIO17, AF2)
+#define GPIO23_CIF_MCLK         MFP_CFG_OUT(GPIO23, AF1, DRIVE_LOW)
+#define GPIO24_CIF_FV           MFP_CFG_IN(GPIO24, AF1)
+#define GPIO25_CIF_LV           MFP_CFG_IN(GPIO25, AF1)
+#define GPIO26_CIF_PCLK         MFP_CFG_IN(GPIO26, AF2)
+#define GPIO27_CIF_DD_0         MFP_CFG_IN(GPIO27, AF3)
+#define GPIO42_CIF_MCLK         MFP_CFG_OUT(GPIO42, AF3, DRIVE_LOW)
+#define GPIO43_CIF_FV           MFP_CFG_IN(GPIO43, AF3)
+#define GPIO44_CIF_LV           MFP_CFG_IN(GPIO44, AF3)
+#define GPIO45_CIF_PCLK         MFP_CFG_IN(GPIO45, AF3)
+#define GPIO47_CIF_DD_0         MFP_CFG_IN(GPIO47, AF1)
+#define GPIO48_CIF_DD_5         MFP_CFG_IN(GPIO48, AF1)
+#define GPIO50_CIF_DD_3         MFP_CFG_IN(GPIO50, AF1)
+#define GPIO51_CIF_DD_2         MFP_CFG_IN(GPIO51, AF1)
+#define GPIO52_CIF_DD_4         MFP_CFG_IN(GPIO52, AF1)
+#define GPIO53_CIF_MCLK         MFP_CFG_OUT(GPIO53, AF2, DRIVE_LOW)
+#define GPIO54_CIF_PCLK         MFP_CFG_IN(GPIO54, AF3)
+#define GPIO55_CIF_DD_1         MFP_CFG_IN(GPIO55, AF1)
+#define GPIO81_CIF_DD_0         MFP_CFG_IN(GPIO81, AF2)
+#define GPIO82_CIF_DD_5         MFP_CFG_IN(GPIO82, AF3)
+#define GPIO83_CIF_DD_4         MFP_CFG_IN(GPIO83, AF3)
+#define GPIO84_CIF_FV           MFP_CFG_IN(GPIO84, AF3)
+#define GPIO85_CIF_LV           MFP_CFG_IN(GPIO85, AF3)
+#define GPIO90_CIF_DD_4         MFP_CFG_IN(GPIO90, AF3)
+#define GPIO91_CIF_DD_5         MFP_CFG_IN(GPIO91, AF3)
+#define GPIO93_CIF_DD_6         MFP_CFG_IN(GPIO93, AF2)
+#define GPIO94_CIF_DD_5         MFP_CFG_IN(GPIO94, AF2)
+#define GPIO95_CIF_DD_4         MFP_CFG_IN(GPIO95, AF2)
+#define GPIO98_CIF_DD_0         MFP_CFG_IN(GPIO98, AF2)
+#define GPIO103_CIF_DD_3        MFP_CFG_IN(GPIO103, AF1)
+#define GPIO104_CIF_DD_2        MFP_CFG_IN(GPIO104, AF1)
+#define GPIO105_CIF_DD_1        MFP_CFG_IN(GPIO105, AF1)
+#define GPIO106_CIF_DD_9        MFP_CFG_IN(GPIO106, AF1)
+#define GPIO107_CIF_DD_8        MFP_CFG_IN(GPIO107, AF1)
+#define GPIO108_CIF_DD_7        MFP_CFG_IN(GPIO108, AF1)
+#define GPIO114_CIF_DD_1        MFP_CFG_IN(GPIO114, AF1)
+
+/* Universal Subscriber ID Interface */
+#define GPIO114_UVS0            MFP_CFG_OUT(GPIO114, AF2, DRIVE_LOW)
+#define GPIO115_nUVS1           MFP_CFG_OUT(GPIO115, AF2, DRIVE_LOW)
+#define GPIO116_nUVS2           MFP_CFG_OUT(GPIO116, AF2, DRIVE_LOW)
+#define GPIO14_UCLK             MFP_CFG_OUT(GPIO14, AF3, DRIVE_LOW)
+#define GPIO91_UCLK             MFP_CFG_OUT(GPIO91, AF2, DRIVE_LOW)
+#define GPIO19_nURST            MFP_CFG_OUT(GPIO19, AF3, DRIVE_LOW)
+#define GPIO90_nURST            MFP_CFG_OUT(GPIO90, AF2, DRIVE_LOW)
+#define GPIO116_UDET            MFP_CFG_IN(GPIO116, AF3)
+#define GPIO114_UEN             MFP_CFG_OUT(GPIO114, AF1, DRIVE_LOW)
+#define GPIO115_UEN             MFP_CFG_OUT(GPIO115, AF1, DRIVE_LOW)
+
+/* Mobile Scalable Link (MSL) Interface */
+#define GPIO81_BB_OB_DAT_0      MFP_CFG_OUT(GPIO81, AF2, DRIVE_LOW)
+#define GPIO48_BB_OB_DAT_1      MFP_CFG_OUT(GPIO48, AF1, DRIVE_LOW)
+#define GPIO50_BB_OB_DAT_2      MFP_CFG_OUT(GPIO50, AF1, DRIVE_LOW)
+#define GPIO51_BB_OB_DAT_3      MFP_CFG_OUT(GPIO51, AF1, DRIVE_LOW)
+#define GPIO52_BB_OB_CLK        MFP_CFG_OUT(GPIO52, AF1, DRIVE_LOW)
+#define GPIO53_BB_OB_STB        MFP_CFG_OUT(GPIO53, AF1, DRIVE_LOW)
+#define GPIO54_BB_OB_WAIT       MFP_CFG_IN(GPIO54, AF2)
+#define GPIO82_BB_IB_DAT_0      MFP_CFG_IN(GPIO82, AF2)
+#define GPIO55_BB_IB_DAT_1      MFP_CFG_IN(GPIO55, AF2)
+#define GPIO56_BB_IB_DAT_2      MFP_CFG_IN(GPIO56, AF2)
+#define GPIO57_BB_IB_DAT_3      MFP_CFG_IN(GPIO57, AF2)
+#define GPIO83_BB_IB_CLK        MFP_CFG_IN(GPIO83, AF2)
+#define GPIO84_BB_IB_STB        MFP_CFG_IN(GPIO84, AF2)
+#define GPIO85_BB_IB_WAIT       MFP_CFG_OUT(GPIO85, AF2, DRIVE_LOW)
+
+/* Memory Stick Host Controller */
+#define GPIO92_MSBS             MFP_CFG_OUT(GPIO92, AF2, DRIVE_LOW)
+#define GPIO109_MSSDIO          MFP_CFG_IN(GPIO109, AF2)
+#define GPIO112_nMSINS          MFP_CFG_IN(GPIO112, AF2)
+#define GPIO32_MSSCLK           MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW)
+
+extern int keypad_set_wake(unsigned int on);
+#endif /* __ASM_ARCH_MFP_PXA27X_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa2xx.h b/include/asm-arm/arch-pxa/mfp-pxa2xx.h
new file mode 100644
index 000000000000..db8d890d237c
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa2xx.h
@@ -0,0 +1,132 @@
+#ifndef __ASM_ARCH_MFP_PXA2XX_H
+#define __ASM_ARCH_MFP_PXA2XX_H
+
+#include <asm/arch/mfp.h>
+
+/*
+ * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
+ *
+ *  MFP_PIN(x)
+ *  MFP_AFx
+ *  MFP_LPM_DRIVE_{LOW, HIGH}
+ *  MFP_LPM_EDGE_x
+ *
+ * other MFP_x bit definitions will be ignored
+ *
+ * and adds the below two bits specifically for pxa2xx:
+ *
+ * bit     23 - Input/Output (PXA2xx specific)
+ * bit     24 - Wakeup Enable(PXA2xx specific)
+ */
+
+#define MFP_DIR_IN              (0x0 << 23)
+#define MFP_DIR_OUT             (0x1 << 23)
+#define MFP_DIR_MASK            (0x1 << 23)
+#define MFP_DIR(x)              (((x) >> 23) & 0x1)
+
+#define MFP_LPM_CAN_WAKEUP      (0x1 << 24)
+#define WAKEUP_ON_EDGE_RISE     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
+#define WAKEUP_ON_EDGE_FALL     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL)
+#define WAKEUP_ON_EDGE_BOTH     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_BOTH)
+
+/* specifically for enabling wakeup on keypad GPIOs */
+#define WAKEUP_ON_LEVEL_HIGH    (MFP_LPM_CAN_WAKEUP)
+
+#define MFP_CFG_IN(pin, af)             \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_IN))
+
+/* NOTE:  pins configured as output _must_ provide a low power state,
+ * and this state should help to minimize the power dissipation.
+ */
+#define MFP_CFG_OUT(pin, af, state)     \
+        ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\
+         (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state))
+
+/* Common configurations for pxa25x and pxa27x
+ *
+ * Note: pins configured as GPIO are always initialized to input
+ * so not to cause any side effect
+ */
+#define GPIO0_GPIO      MFP_CFG_IN(GPIO0, AF0)
+#define GPIO1_GPIO      MFP_CFG_IN(GPIO1, AF0)
+#define GPIO9_GPIO      MFP_CFG_IN(GPIO9, AF0)
+#define GPIO10_GPIO     MFP_CFG_IN(GPIO10, AF0)
+#define GPIO11_GPIO     MFP_CFG_IN(GPIO11, AF0)
+#define GPIO12_GPIO     MFP_CFG_IN(GPIO12, AF0)
+#define GPIO13_GPIO     MFP_CFG_IN(GPIO13, AF0)
+#define GPIO14_GPIO     MFP_CFG_IN(GPIO14, AF0)
+#define GPIO15_GPIO     MFP_CFG_IN(GPIO15, AF0)
+#define GPIO16_GPIO     MFP_CFG_IN(GPIO16, AF0)
+#define GPIO17_GPIO     MFP_CFG_IN(GPIO17, AF0)
+#define GPIO18_GPIO     MFP_CFG_IN(GPIO18, AF0)
+#define GPIO19_GPIO     MFP_CFG_IN(GPIO19, AF0)
+#define GPIO20_GPIO     MFP_CFG_IN(GPIO20, AF0)
+#define GPIO21_GPIO     MFP_CFG_IN(GPIO21, AF0)
+#define GPIO22_GPIO     MFP_CFG_IN(GPIO22, AF0)
+#define GPIO23_GPIO     MFP_CFG_IN(GPIO23, AF0)
+#define GPIO24_GPIO     MFP_CFG_IN(GPIO24, AF0)
+#define GPIO25_GPIO     MFP_CFG_IN(GPIO25, AF0)
+#define GPIO26_GPIO     MFP_CFG_IN(GPIO26, AF0)
+#define GPIO27_GPIO     MFP_CFG_IN(GPIO27, AF0)
+#define GPIO28_GPIO     MFP_CFG_IN(GPIO28, AF0)
+#define GPIO29_GPIO     MFP_CFG_IN(GPIO29, AF0)
+#define GPIO30_GPIO     MFP_CFG_IN(GPIO30, AF0)
+#define GPIO31_GPIO     MFP_CFG_IN(GPIO31, AF0)
+#define GPIO32_GPIO     MFP_CFG_IN(GPIO32, AF0)
+#define GPIO33_GPIO     MFP_CFG_IN(GPIO33, AF0)
+#define GPIO34_GPIO     MFP_CFG_IN(GPIO34, AF0)
+#define GPIO35_GPIO     MFP_CFG_IN(GPIO35, AF0)
+#define GPIO36_GPIO     MFP_CFG_IN(GPIO36, AF0)
+#define GPIO37_GPIO     MFP_CFG_IN(GPIO37, AF0)
+#define GPIO38_GPIO     MFP_CFG_IN(GPIO38, AF0)
+#define GPIO39_GPIO     MFP_CFG_IN(GPIO39, AF0)
+#define GPIO40_GPIO     MFP_CFG_IN(GPIO40, AF0)
+#define GPIO41_GPIO     MFP_CFG_IN(GPIO41, AF0)
+#define GPIO42_GPIO     MFP_CFG_IN(GPIO42, AF0)
+#define GPIO43_GPIO     MFP_CFG_IN(GPIO43, AF0)
+#define GPIO44_GPIO     MFP_CFG_IN(GPIO44, AF0)
+#define GPIO45_GPIO     MFP_CFG_IN(GPIO45, AF0)
+#define GPIO46_GPIO     MFP_CFG_IN(GPIO46, AF0)
+#define GPIO47_GPIO     MFP_CFG_IN(GPIO47, AF0)
+#define GPIO48_GPIO     MFP_CFG_IN(GPIO48, AF0)
+#define GPIO49_GPIO     MFP_CFG_IN(GPIO49, AF0)
+#define GPIO50_GPIO     MFP_CFG_IN(GPIO50, AF0)
+#define GPIO51_GPIO     MFP_CFG_IN(GPIO51, AF0)
+#define GPIO52_GPIO     MFP_CFG_IN(GPIO52, AF0)
+#define GPIO53_GPIO     MFP_CFG_IN(GPIO53, AF0)
+#define GPIO54_GPIO     MFP_CFG_IN(GPIO54, AF0)
+#define GPIO55_GPIO     MFP_CFG_IN(GPIO55, AF0)
+#define GPIO56_GPIO     MFP_CFG_IN(GPIO56, AF0)
+#define GPIO57_GPIO     MFP_CFG_IN(GPIO57, AF0)
+#define GPIO58_GPIO     MFP_CFG_IN(GPIO58, AF0)
+#define GPIO59_GPIO     MFP_CFG_IN(GPIO59, AF0)
+#define GPIO60_GPIO     MFP_CFG_IN(GPIO60, AF0)
+#define GPIO61_GPIO     MFP_CFG_IN(GPIO61, AF0)
+#define GPIO62_GPIO     MFP_CFG_IN(GPIO62, AF0)
+#define GPIO63_GPIO     MFP_CFG_IN(GPIO63, AF0)
+#define GPIO64_GPIO     MFP_CFG_IN(GPIO64, AF0)
+#define GPIO65_GPIO     MFP_CFG_IN(GPIO65, AF0)
+#define GPIO66_GPIO     MFP_CFG_IN(GPIO66, AF0)
+#define GPIO67_GPIO     MFP_CFG_IN(GPIO67, AF0)
+#define GPIO68_GPIO     MFP_CFG_IN(GPIO68, AF0)
+#define GPIO69_GPIO     MFP_CFG_IN(GPIO69, AF0)
+#define GPIO70_GPIO     MFP_CFG_IN(GPIO70, AF0)
+#define GPIO71_GPIO     MFP_CFG_IN(GPIO71, AF0)
+#define GPIO72_GPIO     MFP_CFG_IN(GPIO72, AF0)
+#define GPIO73_GPIO     MFP_CFG_IN(GPIO73, AF0)
+#define GPIO74_GPIO     MFP_CFG_IN(GPIO74, AF0)
+#define GPIO75_GPIO     MFP_CFG_IN(GPIO75, AF0)
+#define GPIO76_GPIO     MFP_CFG_IN(GPIO76, AF0)
+#define GPIO77_GPIO     MFP_CFG_IN(GPIO77, AF0)
+#define GPIO78_GPIO     MFP_CFG_IN(GPIO78, AF0)
+#define GPIO79_GPIO     MFP_CFG_IN(GPIO79, AF0)
+#define GPIO80_GPIO     MFP_CFG_IN(GPIO80, AF0)
+#define GPIO81_GPIO     MFP_CFG_IN(GPIO81, AF0)
+#define GPIO82_GPIO     MFP_CFG_IN(GPIO82, AF0)
+#define GPIO83_GPIO     MFP_CFG_IN(GPIO83, AF0)
+#define GPIO84_GPIO     MFP_CFG_IN(GPIO84, AF0)
+
+extern void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num);
+extern int gpio_set_wake(unsigned int gpio, unsigned int on);
+#endif /* __ASM_ARCH_MFP_PXA2XX_H */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 2357a73340d4..a322012f16ac 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1129,6 +1129,11 @@
 #define ICPR            __REG(0x40D00010)  /* Interrupt Controller Pending Register */
 #define ICCR            __REG(0x40D00014)  /* Interrupt Controller Control Register */
 
+#define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
+#define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
+#define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
 
 /*
  * General Purpose I/O
@@ -1200,12 +1205,6 @@
 
 /* Interrupt Controller */
 
-#define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
-#define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
-#define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
-
 #define _GPLR(x)        __REG2(0x40E00000, ((x) & 0x60) >> 3)
 #define _GPDR(x)        __REG2(0x40E0000C, ((x) & 0x60) >> 3)
 #define _GPSR(x)        __REG2(0x40E00018, ((x) & 0x60) >> 3)
@@ -1237,267 +1236,6 @@
 
 #endif
 
-
-/* GPIO alternate function assignments */
-
-#define GPIO1_RST               1       /* reset */
-#define GPIO6_MMCCLK            6       /* MMC Clock */
-#define GPIO7_48MHz             7       /* 48 MHz clock output */
-#define GPIO8_MMCCS0            8       /* MMC Chip Select 0 */
-#define GPIO9_MMCCS1            9       /* MMC Chip Select 1 */
-#define GPIO10_RTCCLK           10      /* real time clock (1 Hz) */
-#define GPIO11_3_6MHz           11      /* 3.6 MHz oscillator out */
-#define GPIO12_32KHz            12      /* 32 kHz out */
-#define GPIO13_MBGNT            13      /* memory controller grant */
-#define GPIO14_MBREQ            14      /* alternate bus master request */
-#define GPIO15_nCS_1            15      /* chip select 1 */
-#define GPIO16_PWM0             16      /* PWM0 output */
-#define GPIO17_PWM1             17      /* PWM1 output */
-#define GPIO18_RDY              18      /* Ext. Bus Ready */
-#define GPIO19_DREQ1            19      /* External DMA Request */
-#define GPIO20_DREQ0            20      /* External DMA Request */
-#define GPIO23_SCLK             23      /* SSP clock */
-#define GPIO24_SFRM             24      /* SSP Frame */
-#define GPIO25_STXD             25      /* SSP transmit */
-#define GPIO26_SRXD             26      /* SSP receive */
-#define GPIO27_SEXTCLK          27      /* SSP ext_clk */
-#define GPIO28_BITCLK           28      /* AC97/I2S bit_clk */
-#define GPIO29_SDATA_IN         29      /* AC97 Sdata_in0 / I2S Sdata_in */
-#define GPIO30_SDATA_OUT        30      /* AC97/I2S Sdata_out */
-#define GPIO31_SYNC             31      /* AC97/I2S sync */
-#define GPIO32_SDATA_IN1        32      /* AC97 Sdata_in1 */
-#define GPIO32_SYSCLK           32      /* I2S System Clock */
-#define GPIO32_MMCCLK           32      /* MMC Clock (PXA270) */
-#define GPIO33_nCS_5            33      /* chip select 5 */
-#define GPIO34_FFRXD            34      /* FFUART receive */
-#define GPIO34_MMCCS0           34      /* MMC Chip Select 0 */
-#define GPIO35_FFCTS            35      /* FFUART Clear to send */
-#define GPIO36_FFDCD            36      /* FFUART Data carrier detect */
-#define GPIO37_FFDSR            37      /* FFUART data set ready */
-#define GPIO38_FFRI             38      /* FFUART Ring Indicator */
-#define GPIO39_MMCCS1           39      /* MMC Chip Select 1 */
-#define GPIO39_FFTXD            39      /* FFUART transmit data */
-#define GPIO40_FFDTR            40      /* FFUART data terminal Ready */
-#define GPIO41_FFRTS            41      /* FFUART request to send */
-#define GPIO42_BTRXD            42      /* BTUART receive data */
-#define GPIO42_HWRXD            42      /* HWUART receive data */
-#define GPIO43_BTTXD            43      /* BTUART transmit data */
-#define GPIO43_HWTXD            43      /* HWUART transmit data */
-#define GPIO44_BTCTS            44      /* BTUART clear to send */
-#define GPIO44_HWCTS            44      /* HWUART clear to send */
-#define GPIO45_BTRTS            45      /* BTUART request to send */
-#define GPIO45_HWRTS            45      /* HWUART request to send */
-#define GPIO45_AC97_SYSCLK      45      /* AC97 System Clock */
-#define GPIO46_ICPRXD           46      /* ICP receive data */
-#define GPIO46_STRXD            46      /* STD_UART receive data */
-#define GPIO47_ICPTXD           47      /* ICP transmit data */
-#define GPIO47_STTXD            47      /* STD_UART transmit data */
-#define GPIO48_nPOE             48      /* Output Enable for Card Space */
-#define GPIO49_nPWE             49      /* Write Enable for Card Space */
-#define GPIO50_nPIOR            50      /* I/O Read for Card Space */
-#define GPIO51_nPIOW            51      /* I/O Write for Card Space */
-#define GPIO52_nPCE_1           52      /* Card Enable for Card Space */
-#define GPIO53_nPCE_2           53      /* Card Enable for Card Space */
-#define GPIO53_MMCCLK           53      /* MMC Clock */
-#define GPIO54_MMCCLK           54      /* MMC Clock */
-#define GPIO54_pSKTSEL          54      /* Socket Select for Card Space */
-#define GPIO54_nPCE_2           54      /* Card Enable for Card Space (PXA27x) */
-#define GPIO55_nPREG            55      /* Card Address bit 26 */
-#define GPIO56_nPWAIT           56      /* Wait signal for Card Space */
-#define GPIO57_nIOIS16          57      /* Bus Width select for I/O Card Space */
-#define GPIO58_LDD_0            58      /* LCD data pin 0 */
-#define GPIO59_LDD_1            59      /* LCD data pin 1 */
-#define GPIO60_LDD_2            60      /* LCD data pin 2 */
-#define GPIO61_LDD_3            61      /* LCD data pin 3 */
-#define GPIO62_LDD_4            62      /* LCD data pin 4 */
-#define GPIO63_LDD_5            63      /* LCD data pin 5 */
-#define GPIO64_LDD_6            64      /* LCD data pin 6 */
-#define GPIO65_LDD_7            65      /* LCD data pin 7 */
-#define GPIO66_LDD_8            66      /* LCD data pin 8 */
-#define GPIO66_MBREQ            66      /* alternate bus master req */
-#define GPIO67_LDD_9            67      /* LCD data pin 9 */
-#define GPIO67_MMCCS0           67      /* MMC Chip Select 0 */
-#define GPIO68_LDD_10           68      /* LCD data pin 10 */
-#define GPIO68_MMCCS1           68      /* MMC Chip Select 1 */
-#define GPIO69_LDD_11           69      /* LCD data pin 11 */
-#define GPIO69_MMCCLK           69      /* MMC_CLK */
-#define GPIO70_LDD_12           70      /* LCD data pin 12 */
-#define GPIO70_RTCCLK           70      /* Real Time clock (1 Hz) */
-#define GPIO71_LDD_13           71      /* LCD data pin 13 */
-#define GPIO71_3_6MHz           71      /* 3.6 MHz Oscillator clock */
-#define GPIO72_LDD_14           72      /* LCD data pin 14 */
-#define GPIO72_32kHz            72      /* 32 kHz clock */
-#define GPIO73_LDD_15           73      /* LCD data pin 15 */
-#define GPIO73_MBGNT            73      /* Memory controller grant */
-#define GPIO74_LCD_FCLK         74      /* LCD Frame clock */
-#define GPIO75_LCD_LCLK         75      /* LCD line clock */
-#define GPIO76_LCD_PCLK         76      /* LCD Pixel clock */
-#define GPIO77_LCD_ACBIAS       77      /* LCD AC Bias */
-#define GPIO78_nCS_2            78      /* chip select 2 */
-#define GPIO79_nCS_3            79      /* chip select 3 */
-#define GPIO80_nCS_4            80      /* chip select 4 */
-#define GPIO81_NSCLK            81      /* NSSP clock */
-#define GPIO82_NSFRM            82      /* NSSP Frame */
-#define GPIO83_NSTXD            83      /* NSSP transmit */
-#define GPIO84_NSRXD            84      /* NSSP receive */
-#define GPIO85_nPCE_1           85      /* Card Enable for Card Space (PXA27x) */
-#define GPIO92_MMCDAT0          92      /* MMC DAT0 (PXA27x) */
-#define GPIO102_nPCE_1          102     /* PCMCIA (PXA27x) */
-#define GPIO109_MMCDAT1         109     /* MMC DAT1 (PXA27x) */
-#define GPIO110_MMCDAT2         110     /* MMC DAT2 (PXA27x) */
-#define GPIO110_MMCCS0          110     /* MMC Chip Select 0 (PXA27x) */
-#define GPIO111_MMCDAT3         111     /* MMC DAT3 (PXA27x) */
-#define GPIO111_MMCCS1          111     /* MMC Chip Select 1 (PXA27x) */
-#define GPIO112_MMCCMD          112     /* MMC CMD (PXA27x) */
-#define GPIO113_I2S_SYSCLK      113     /* I2S System Clock (PXA27x) */
-#define GPIO113_AC97_RESET_N    113     /* AC97 NRESET on (PXA27x) */
-
-/* GPIO alternate function mode & direction */
-
-#define GPIO_IN                 0x000
-#define GPIO_OUT                0x080
-#define GPIO_ALT_FN_1_IN        0x100
-#define GPIO_ALT_FN_1_OUT       0x180
-#define GPIO_ALT_FN_2_IN        0x200
-#define GPIO_ALT_FN_2_OUT       0x280
-#define GPIO_ALT_FN_3_IN        0x300
-#define GPIO_ALT_FN_3_OUT       0x380
-#define GPIO_MD_MASK_NR         0x07f
-#define GPIO_MD_MASK_DIR        0x080
-#define GPIO_MD_MASK_FN         0x300
-#define GPIO_DFLT_LOW           0x400
-#define GPIO_DFLT_HIGH          0x800
-
-#define GPIO1_RTS_MD            ( 1 | GPIO_ALT_FN_1_IN)
-#define GPIO6_MMCCLK_MD         ( 6 | GPIO_ALT_FN_1_OUT)
-#define GPIO7_48MHz_MD          ( 7 | GPIO_ALT_FN_1_OUT)
-#define GPIO8_MMCCS0_MD         ( 8 | GPIO_ALT_FN_1_OUT)
-#define GPIO9_MMCCS1_MD         ( 9 | GPIO_ALT_FN_1_OUT)
-#define GPIO10_RTCCLK_MD        (10 | GPIO_ALT_FN_1_OUT)
-#define GPIO11_3_6MHz_MD        (11 | GPIO_ALT_FN_1_OUT)
-#define GPIO12_32KHz_MD         (12 | GPIO_ALT_FN_1_OUT)
-#define GPIO13_MBGNT_MD         (13 | GPIO_ALT_FN_2_OUT)
-#define GPIO14_MBREQ_MD         (14 | GPIO_ALT_FN_1_IN)
-#define GPIO15_nCS_1_MD         (15 | GPIO_ALT_FN_2_OUT)
-#define GPIO16_PWM0_MD          (16 | GPIO_ALT_FN_2_OUT)
-#define GPIO17_PWM1_MD          (17 | GPIO_ALT_FN_2_OUT)
-#define GPIO18_RDY_MD           (18 | GPIO_ALT_FN_1_IN)
-#define GPIO19_DREQ1_MD         (19 | GPIO_ALT_FN_1_IN)
-#define GPIO20_DREQ0_MD         (20 | GPIO_ALT_FN_1_IN)
-#define GPIO23_SCLK_MD          (23 | GPIO_ALT_FN_2_OUT)
-#define GPIO24_SFRM_MD          (24 | GPIO_ALT_FN_2_OUT)
-#define GPIO25_STXD_MD          (25 | GPIO_ALT_FN_2_OUT)
-#define GPIO26_SRXD_MD          (26 | GPIO_ALT_FN_1_IN)
-#define GPIO27_SEXTCLK_MD       (27 | GPIO_ALT_FN_1_IN)
-#define GPIO28_BITCLK_AC97_MD   (28 | GPIO_ALT_FN_1_IN)
-#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
-#define GPIO28_BITCLK_OUT_I2S_MD        (28 | GPIO_ALT_FN_1_OUT)
-#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
-#define GPIO29_SDATA_IN_I2S_MD  (29 | GPIO_ALT_FN_2_IN)
-#define GPIO30_SDATA_OUT_AC97_MD        (30 | GPIO_ALT_FN_2_OUT)
-#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
-#define GPIO31_SYNC_I2S_MD      (31 | GPIO_ALT_FN_1_OUT)
-#define GPIO31_SYNC_AC97_MD     (31 | GPIO_ALT_FN_2_OUT)
-#define GPIO32_SDATA_IN1_AC97_MD        (32 | GPIO_ALT_FN_1_IN)
-#define GPIO32_SYSCLK_I2S_MD    (32 | GPIO_ALT_FN_1_OUT)
-#define GPIO32_MMCCLK_MD                ( 32 | GPIO_ALT_FN_2_OUT)
-#define GPIO33_nCS_5_MD         (33 | GPIO_ALT_FN_2_OUT)
-#define GPIO34_FFRXD_MD         (34 | GPIO_ALT_FN_1_IN)
-#define GPIO34_MMCCS0_MD        (34 | GPIO_ALT_FN_2_OUT)
-#define GPIO35_FFCTS_MD         (35 | GPIO_ALT_FN_1_IN)
-#define GPIO36_FFDCD_MD         (36 | GPIO_ALT_FN_1_IN)
-#define GPIO37_FFDSR_MD         (37 | GPIO_ALT_FN_1_IN)
-#define GPIO38_FFRI_MD          (38 | GPIO_ALT_FN_1_IN)
-#define GPIO39_MMCCS1_MD        (39 | GPIO_ALT_FN_1_OUT)
-#define GPIO39_FFTXD_MD         (39 | GPIO_ALT_FN_2_OUT)
-#define GPIO40_FFDTR_MD         (40 | GPIO_ALT_FN_2_OUT)
-#define GPIO41_FFRTS_MD         (41 | GPIO_ALT_FN_2_OUT)
-#define GPIO42_BTRXD_MD         (42 | GPIO_ALT_FN_1_IN)
-#define GPIO42_HWRXD_MD         (42 | GPIO_ALT_FN_3_IN)
-#define GPIO43_BTTXD_MD         (43 | GPIO_ALT_FN_2_OUT)
-#define GPIO43_HWTXD_MD         (43 | GPIO_ALT_FN_3_OUT)
-#define GPIO44_BTCTS_MD         (44 | GPIO_ALT_FN_1_IN)
-#define GPIO44_HWCTS_MD         (44 | GPIO_ALT_FN_3_IN)
-#define GPIO45_BTRTS_MD         (45 | GPIO_ALT_FN_2_OUT)
-#define GPIO45_HWRTS_MD         (45 | GPIO_ALT_FN_3_OUT)
-#define GPIO45_SYSCLK_AC97_MD           (45 | GPIO_ALT_FN_1_OUT)
-#define GPIO46_ICPRXD_MD        (46 | GPIO_ALT_FN_1_IN)
-#define GPIO46_STRXD_MD         (46 | GPIO_ALT_FN_2_IN)
-#define GPIO47_ICPTXD_MD        (47 | GPIO_ALT_FN_2_OUT)
-#define GPIO47_STTXD_MD         (47 | GPIO_ALT_FN_1_OUT)
-#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
-#define GPIO48_HWTXD_MD         (48 | GPIO_ALT_FN_1_OUT)
-#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
-#define GPIO49_HWRXD_MD         (49 | GPIO_ALT_FN_1_IN)
-#define GPIO49_nPWE_MD          (49 | GPIO_ALT_FN_2_OUT)
-#define GPIO50_nPIOR_MD         (50 | GPIO_ALT_FN_2_OUT)
-#define GPIO50_HWCTS_MD         (50 | GPIO_ALT_FN_1_IN)
-#define GPIO51_HWRTS_MD         (51 | GPIO_ALT_FN_1_OUT)
-#define GPIO51_nPIOW_MD         (51 | GPIO_ALT_FN_2_OUT)
-#define GPIO52_nPCE_1_MD        (52 | GPIO_ALT_FN_2_OUT)
-#define GPIO53_nPCE_2_MD        (53 | GPIO_ALT_FN_2_OUT)
-#define GPIO53_MMCCLK_MD        (53 | GPIO_ALT_FN_1_OUT)
-#define GPIO54_MMCCLK_MD        (54 | GPIO_ALT_FN_1_OUT)
-#define GPIO54_nPCE_2_MD        (54 | GPIO_ALT_FN_2_OUT)
-#define GPIO54_pSKTSEL_MD       (54 | GPIO_ALT_FN_2_OUT)
-#define GPIO55_nPREG_MD         (55 | GPIO_ALT_FN_2_OUT)
-#define GPIO56_nPWAIT_MD        (56 | GPIO_ALT_FN_1_IN)
-#define GPIO57_nIOIS16_MD       (57 | GPIO_ALT_FN_1_IN)
-#define GPIO58_LDD_0_MD         (58 | GPIO_ALT_FN_2_OUT)
-#define GPIO59_LDD_1_MD         (59 | GPIO_ALT_FN_2_OUT)
-#define GPIO60_LDD_2_MD         (60 | GPIO_ALT_FN_2_OUT)
-#define GPIO61_LDD_3_MD         (61 | GPIO_ALT_FN_2_OUT)
-#define GPIO62_LDD_4_MD         (62 | GPIO_ALT_FN_2_OUT)
-#define GPIO63_LDD_5_MD         (63 | GPIO_ALT_FN_2_OUT)
-#define GPIO64_LDD_6_MD         (64 | GPIO_ALT_FN_2_OUT)
-#define GPIO65_LDD_7_MD         (65 | GPIO_ALT_FN_2_OUT)
-#define GPIO66_LDD_8_MD         (66 | GPIO_ALT_FN_2_OUT)
-#define GPIO66_MBREQ_MD         (66 | GPIO_ALT_FN_1_IN)
-#define GPIO67_LDD_9_MD         (67 | GPIO_ALT_FN_2_OUT)
-#define GPIO67_MMCCS0_MD        (67 | GPIO_ALT_FN_1_OUT)
-#define GPIO68_LDD_10_MD        (68 | GPIO_ALT_FN_2_OUT)
-#define GPIO68_MMCCS1_MD        (68 | GPIO_ALT_FN_1_OUT)
-#define GPIO69_LDD_11_MD        (69 | GPIO_ALT_FN_2_OUT)
-#define GPIO69_MMCCLK_MD        (69 | GPIO_ALT_FN_1_OUT)
-#define GPIO70_LDD_12_MD        (70 | GPIO_ALT_FN_2_OUT)
-#define GPIO70_RTCCLK_MD        (70 | GPIO_ALT_FN_1_OUT)
-#define GPIO71_LDD_13_MD        (71 | GPIO_ALT_FN_2_OUT)
-#define GPIO71_3_6MHz_MD        (71 | GPIO_ALT_FN_1_OUT)
-#define GPIO72_LDD_14_MD        (72 | GPIO_ALT_FN_2_OUT)
-#define GPIO72_32kHz_MD         (72 | GPIO_ALT_FN_1_OUT)
-#define GPIO73_LDD_15_MD        (73 | GPIO_ALT_FN_2_OUT)
-#define GPIO73_MBGNT_MD         (73 | GPIO_ALT_FN_1_OUT)
-#define GPIO74_LCD_FCLK_MD      (74 | GPIO_ALT_FN_2_OUT)
-#define GPIO75_LCD_LCLK_MD      (75 | GPIO_ALT_FN_2_OUT)
-#define GPIO76_LCD_PCLK_MD      (76 | GPIO_ALT_FN_2_OUT)
-#define GPIO77_LCD_ACBIAS_MD    (77 | GPIO_ALT_FN_2_OUT)
-#define GPIO78_nCS_2_MD         (78 | GPIO_ALT_FN_2_OUT)
-#define GPIO79_nCS_3_MD         (79 | GPIO_ALT_FN_2_OUT)
-#define GPIO79_pSKTSEL_MD       (79 | GPIO_ALT_FN_1_OUT)
-#define GPIO80_nCS_4_MD         (80 | GPIO_ALT_FN_2_OUT)
-#define GPIO81_NSSP_CLK_OUT     (81 | GPIO_ALT_FN_1_OUT)
-#define GPIO81_NSSP_CLK_IN      (81 | GPIO_ALT_FN_1_IN)
-#define GPIO82_NSSP_FRM_OUT     (82 | GPIO_ALT_FN_1_OUT)
-#define GPIO82_NSSP_FRM_IN      (82 | GPIO_ALT_FN_1_IN)
-#define GPIO83_NSSP_TX          (83 | GPIO_ALT_FN_1_OUT)
-#define GPIO83_NSSP_RX          (83 | GPIO_ALT_FN_2_IN)
-#define GPIO84_NSSP_TX          (84 | GPIO_ALT_FN_1_OUT)
-#define GPIO84_NSSP_RX          (84 | GPIO_ALT_FN_2_IN)
-#define GPIO85_nPCE_1_MD        (85 | GPIO_ALT_FN_1_OUT)
-#define GPIO92_MMCDAT0_MD       (92 | GPIO_ALT_FN_1_OUT)
-#define GPIO102_nPCE_1_MD       (102 | GPIO_ALT_FN_1_OUT)
-#define GPIO104_pSKTSEL_MD      (104 | GPIO_ALT_FN_1_OUT)
-#define GPIO109_MMCDAT1_MD      (109 | GPIO_ALT_FN_1_OUT)
-#define GPIO110_MMCDAT2_MD      (110 | GPIO_ALT_FN_1_OUT)
-#define GPIO110_MMCCS0_MD       (110 | GPIO_ALT_FN_1_OUT)
-#define GPIO111_MMCDAT3_MD      (111 | GPIO_ALT_FN_1_OUT)
-#define GPIO110_MMCCS1_MD       (111 | GPIO_ALT_FN_1_OUT)
-#define GPIO112_MMCCMD_MD       (112 | GPIO_ALT_FN_1_OUT)
-#define GPIO113_I2S_SYSCLK_MD   (113 | GPIO_ALT_FN_1_OUT)
-#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
-#define GPIO117_I2CSCL_MD       (117 | GPIO_ALT_FN_1_IN)
-#define GPIO118_I2CSDA_MD       (118 | GPIO_ALT_FN_1_IN)
-
 /*
  * Power Manager
  */
@@ -1866,62 +1604,6 @@
 
 #ifdef CONFIG_PXA27x
 
-/*
- * Keypad
- */
-#define KPC             __REG(0x41500000) /* Keypad Interface Control register */
-#define KPDK            __REG(0x41500008) /* Keypad Interface Direct Key register */
-#define KPREC           __REG(0x41500010) /* Keypad Interface Rotary Encoder register */
-#define KPMK            __REG(0x41500018) /* Keypad Interface Matrix Key register */
-#define KPAS            __REG(0x41500020) /* Keypad Interface Automatic Scan register */
-#define KPASMKP0        __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
-#define KPASMKP1        __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
-#define KPASMKP2        __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
-#define KPASMKP3        __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
-#define KPKDI           __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
-
-#define KPC_AS          (0x1 << 30)  /* Automatic Scan bit */
-#define KPC_ASACT       (0x1 << 29)  /* Automatic Scan on Activity */
-#define KPC_MI          (0x1 << 22)  /* Matrix interrupt bit */
-#define KPC_IMKP        (0x1 << 21)  /* Ignore Multiple Key Press */
-#define KPC_MS7         (0x1 << 20)  /* Matrix scan line 7 */
-#define KPC_MS6         (0x1 << 19)  /* Matrix scan line 6 */
-#define KPC_MS5         (0x1 << 18)  /* Matrix scan line 5 */
-#define KPC_MS4         (0x1 << 17)  /* Matrix scan line 4 */
-#define KPC_MS3         (0x1 << 16)  /* Matrix scan line 3 */
-#define KPC_MS2         (0x1 << 15)  /* Matrix scan line 2 */
-#define KPC_MS1         (0x1 << 14)  /* Matrix scan line 1 */
-#define KPC_MS0         (0x1 << 13)  /* Matrix scan line 0 */
-#define KPC_MS_ALL      (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7)
-#define KPC_ME          (0x1 << 12)  /* Matrix Keypad Enable */
-#define KPC_MIE         (0x1 << 11)  /* Matrix Interrupt Enable */
-#define KPC_DK_DEB_SEL  (0x1 <<  9)  /* Direct Keypad Debounce Select */
-#define KPC_DI          (0x1 <<  5)  /* Direct key interrupt bit */
-#define KPC_RE_ZERO_DEB (0x1 <<  4)  /* Rotary Encoder Zero Debounce */
-#define KPC_REE1        (0x1 <<  3)  /* Rotary Encoder1 Enable */
-#define KPC_REE0        (0x1 <<  2)  /* Rotary Encoder0 Enable */
-#define KPC_DE          (0x1 <<  1)  /* Direct Keypad Enable */
-#define KPC_DIE         (0x1 <<  0)  /* Direct Keypad interrupt Enable */
-
-#define KPDK_DKP        (0x1 << 31)
-#define KPDK_DK7        (0x1 <<  7)
-#define KPDK_DK6        (0x1 <<  6)
-#define KPDK_DK5        (0x1 <<  5)
-#define KPDK_DK4        (0x1 <<  4)
-#define KPDK_DK3        (0x1 <<  3)
-#define KPDK_DK2        (0x1 <<  2)
-#define KPDK_DK1        (0x1 <<  1)
-#define KPDK_DK0        (0x1 <<  0)
-
-#define KPREC_OF1       (0x1 << 31)
-#define kPREC_UF1       (0x1 << 30)
-#define KPREC_OF0       (0x1 << 15)
-#define KPREC_UF0       (0x1 << 14)
-
-#define KPMK_MKP        (0x1 << 31)
-#define KPAS_SO         (0x1 << 31)
-#define KPASMKPx_SO     (0x1 << 31)
-
 /* Camera Interface */
 #define CICR0           __REG(0x50000000)
 #define CICR1           __REG(0x50000004)
@@ -1953,7 +1635,7 @@
 #define CICR0_FOM       (1 << 0)        /* FIFO-overrun mask */
 
 #define CICR1_TBIT      (1 << 31)       /* Transparency bit */
-#define CICR1_RGBT_CONV (0x3 << 30)     /* RGBT conversion mask */
+#define CICR1_RGBT_CONV (0x3 << 29)     /* RGBT conversion mask */
 #define CICR1_PPL       (0x7ff << 15)   /* Pixels per line mask */
 #define CICR1_RGB_CONV  (0x7 << 12)     /* RGB conversion mask */
 #define CICR1_RGB_F     (1 << 11)       /* RGB format */
diff --git a/include/asm-arm/arch-pxa/pxa27x_keypad.h b/include/asm-arm/arch-pxa/pxa27x_keypad.h
index 644f7609b523..d5a48a96dea7 100644
--- a/include/asm-arm/arch-pxa/pxa27x_keypad.h
+++ b/include/asm-arm/arch-pxa/pxa27x_keypad.h
@@ -53,4 +53,6 @@ struct pxa27x_keypad_platform_data {
 
 #define KEY(row, col, val)      (((row) << 28) | ((col) << 24) | (val))
 
+extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
+
 #endif /* __ASM_ARCH_PXA27x_KEYPAD_H */
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
new file mode 100644
index 000000000000..763313c5e6be
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
@@ -0,0 +1,357 @@
+#ifndef __ASM_ARCH_PXA2XX_GPIO_H
+#define __ASM_ARCH_PXA2XX_GPIO_H
+
+/* GPIO alternate function assignments */
+
+#define GPIO1_RST               1       /* reset */
+#define GPIO6_MMCCLK            6       /* MMC Clock */
+#define GPIO7_48MHz             7       /* 48 MHz clock output */
+#define GPIO8_MMCCS0            8       /* MMC Chip Select 0 */
+#define GPIO9_MMCCS1            9       /* MMC Chip Select 1 */
+#define GPIO10_RTCCLK           10      /* real time clock (1 Hz) */
+#define GPIO11_3_6MHz           11      /* 3.6 MHz oscillator out */
+#define GPIO12_32KHz            12      /* 32 kHz out */
+#define GPIO12_CIF_DD_7         12      /* Camera data pin 7 */
+#define GPIO13_MBGNT            13      /* memory controller grant */
+#define GPIO14_MBREQ            14      /* alternate bus master request */
+#define GPIO15_nCS_1            15      /* chip select 1 */
+#define GPIO16_PWM0             16      /* PWM0 output */
+#define GPIO17_PWM1             17      /* PWM1 output */
+#define GPIO17_CIF_DD_6         17      /* Camera data pin 6 */
+#define GPIO18_RDY              18      /* Ext. Bus Ready */
+#define GPIO19_DREQ1            19      /* External DMA Request */
+#define GPIO20_DREQ0            20      /* External DMA Request */
+#define GPIO23_SCLK             23      /* SSP clock */
+#define GPIO23_CIF_MCLK         23      /* Camera Master Clock */
+#define GPIO24_SFRM             24      /* SSP Frame */
+#define GPIO24_CIF_FV           24      /* Camera frame start signal */
+#define GPIO25_STXD             25      /* SSP transmit */
+#define GPIO25_CIF_LV           25      /* Camera line start signal */
+#define GPIO26_SRXD             26      /* SSP receive */
+#define GPIO26_CIF_PCLK         26      /* Camera Pixel Clock */
+#define GPIO27_SEXTCLK          27      /* SSP ext_clk */
+#define GPIO27_CIF_DD_0         27      /* Camera data pin 0 */
+#define GPIO28_BITCLK           28      /* AC97/I2S bit_clk */
+#define GPIO29_SDATA_IN         29      /* AC97 Sdata_in0 / I2S Sdata_in */
+#define GPIO30_SDATA_OUT        30      /* AC97/I2S Sdata_out */
+#define GPIO31_SYNC             31      /* AC97/I2S sync */
+#define GPIO32_SDATA_IN1        32      /* AC97 Sdata_in1 */
+#define GPIO32_SYSCLK           32      /* I2S System Clock */
+#define GPIO32_MMCCLK           32      /* MMC Clock (PXA270) */
+#define GPIO33_nCS_5            33      /* chip select 5 */
+#define GPIO34_FFRXD            34      /* FFUART receive */
+#define GPIO34_MMCCS0           34      /* MMC Chip Select 0 */
+#define GPIO35_FFCTS            35      /* FFUART Clear to send */
+#define GPIO36_FFDCD            36      /* FFUART Data carrier detect */
+#define GPIO37_FFDSR            37      /* FFUART data set ready */
+#define GPIO38_FFRI             38      /* FFUART Ring Indicator */
+#define GPIO39_MMCCS1           39      /* MMC Chip Select 1 */
+#define GPIO39_FFTXD            39      /* FFUART transmit data */
+#define GPIO40_FFDTR            40      /* FFUART data terminal Ready */
+#define GPIO41_FFRTS            41      /* FFUART request to send */
+#define GPIO42_BTRXD            42      /* BTUART receive data */
+#define GPIO42_HWRXD            42      /* HWUART receive data */
+#define GPIO42_CIF_MCLK         42      /* Camera Master Clock */
+#define GPIO43_BTTXD            43      /* BTUART transmit data */
+#define GPIO43_HWTXD            43      /* HWUART transmit data */
+#define GPIO43_CIF_FV           43      /* Camera frame start signal */
+#define GPIO44_BTCTS            44      /* BTUART clear to send */
+#define GPIO44_HWCTS            44      /* HWUART clear to send */
+#define GPIO44_CIF_LV           44      /* Camera line start signal */
+#define GPIO45_BTRTS            45      /* BTUART request to send */
+#define GPIO45_HWRTS            45      /* HWUART request to send */
+#define GPIO45_AC97_SYSCLK      45      /* AC97 System Clock */
+#define GPIO45_CIF_PCLK         45      /* Camera Pixel Clock */
+#define GPIO46_ICPRXD           46      /* ICP receive data */
+#define GPIO46_STRXD            46      /* STD_UART receive data */
+#define GPIO47_ICPTXD           47      /* ICP transmit data */
+#define GPIO47_STTXD            47      /* STD_UART transmit data */
+#define GPIO47_CIF_DD_0         47      /* Camera data pin 0 */
+#define GPIO48_nPOE             48      /* Output Enable for Card Space */
+#define GPIO48_CIF_DD_5         48      /* Camera data pin 5 */
+#define GPIO49_nPWE             49      /* Write Enable for Card Space */
+#define GPIO50_nPIOR            50      /* I/O Read for Card Space */
+#define GPIO50_CIF_DD_3         50      /* Camera data pin 3 */
+#define GPIO51_nPIOW            51      /* I/O Write for Card Space */
+#define GPIO51_CIF_DD_2         51      /* Camera data pin 2 */
+#define GPIO52_nPCE_1           52      /* Card Enable for Card Space */
+#define GPIO52_CIF_DD_4         52      /* Camera data pin 4 */
+#define GPIO53_nPCE_2           53      /* Card Enable for Card Space */
+#define GPIO53_MMCCLK           53      /* MMC Clock */
+#define GPIO53_CIF_MCLK         53      /* Camera Master Clock */
+#define GPIO54_MMCCLK           54      /* MMC Clock */
+#define GPIO54_pSKTSEL          54      /* Socket Select for Card Space */
+#define GPIO54_nPCE_2           54      /* Card Enable for Card Space (PXA27x) */
+#define GPIO54_CIF_PCLK         54      /* Camera Pixel Clock */
+#define GPIO55_nPREG            55      /* Card Address bit 26 */
+#define GPIO55_CIF_DD_1         55      /* Camera data pin 1 */
+#define GPIO56_nPWAIT           56      /* Wait signal for Card Space */
+#define GPIO57_nIOIS16          57      /* Bus Width select for I/O Card Space */
+#define GPIO58_LDD_0            58      /* LCD data pin 0 */
+#define GPIO59_LDD_1            59      /* LCD data pin 1 */
+#define GPIO60_LDD_2            60      /* LCD data pin 2 */
+#define GPIO61_LDD_3            61      /* LCD data pin 3 */
+#define GPIO62_LDD_4            62      /* LCD data pin 4 */
+#define GPIO63_LDD_5            63      /* LCD data pin 5 */
+#define GPIO64_LDD_6            64      /* LCD data pin 6 */
+#define GPIO65_LDD_7            65      /* LCD data pin 7 */
+#define GPIO66_LDD_8            66      /* LCD data pin 8 */
+#define GPIO66_MBREQ            66      /* alternate bus master req */
+#define GPIO67_LDD_9            67      /* LCD data pin 9 */
+#define GPIO67_MMCCS0           67      /* MMC Chip Select 0 */
+#define GPIO68_LDD_10           68      /* LCD data pin 10 */
+#define GPIO68_MMCCS1           68      /* MMC Chip Select 1 */
+#define GPIO69_LDD_11           69      /* LCD data pin 11 */
+#define GPIO69_MMCCLK           69      /* MMC_CLK */
+#define GPIO70_LDD_12           70      /* LCD data pin 12 */
+#define GPIO70_RTCCLK           70      /* Real Time clock (1 Hz) */
+#define GPIO71_LDD_13           71      /* LCD data pin 13 */
+#define GPIO71_3_6MHz           71      /* 3.6 MHz Oscillator clock */
+#define GPIO72_LDD_14           72      /* LCD data pin 14 */
+#define GPIO72_32kHz            72      /* 32 kHz clock */
+#define GPIO73_LDD_15           73      /* LCD data pin 15 */
+#define GPIO73_MBGNT            73      /* Memory controller grant */
+#define GPIO74_LCD_FCLK         74      /* LCD Frame clock */
+#define GPIO75_LCD_LCLK         75      /* LCD line clock */
+#define GPIO76_LCD_PCLK         76      /* LCD Pixel clock */
+#define GPIO77_LCD_ACBIAS       77      /* LCD AC Bias */
+#define GPIO78_nCS_2            78      /* chip select 2 */
+#define GPIO79_nCS_3            79      /* chip select 3 */
+#define GPIO80_nCS_4            80      /* chip select 4 */
+#define GPIO81_NSCLK            81      /* NSSP clock */
+#define GPIO81_CIF_DD_0         81      /* Camera data pin 0 */
+#define GPIO82_NSFRM            82      /* NSSP Frame */
+#define GPIO82_CIF_DD_5         82      /* Camera data pin 5 */
+#define GPIO83_NSTXD            83      /* NSSP transmit */
+#define GPIO83_CIF_DD_4         83      /* Camera data pin 4 */
+#define GPIO84_NSRXD            84      /* NSSP receive */
+#define GPIO84_CIF_FV           84      /* Camera frame start signal */
+#define GPIO85_nPCE_1           85      /* Card Enable for Card Space (PXA27x) */
+#define GPIO85_CIF_LV           85      /* Camera line start signal */
+#define GPIO90_CIF_DD_4         90      /* Camera data pin 4 */
+#define GPIO91_CIF_DD_5         91      /* Camera data pin 5 */
+#define GPIO92_MMCDAT0          92      /* MMC DAT0 (PXA27x) */
+#define GPIO93_CIF_DD_6         93      /* Camera data pin 6 */
+#define GPIO94_CIF_DD_5         94      /* Camera data pin 5 */
+#define GPIO95_CIF_DD_4         95      /* Camera data pin 4 */
+#define GPIO98_CIF_DD_0         98      /* Camera data pin 0 */
+#define GPIO102_nPCE_1          102     /* PCMCIA (PXA27x) */
+#define GPIO103_CIF_DD_3        103     /* Camera data pin 3 */
+#define GPIO104_CIF_DD_2        104     /* Camera data pin 2 */
+#define GPIO105_CIF_DD_1        105     /* Camera data pin 1 */
+#define GPIO106_CIF_DD_9        106     /* Camera data pin 9 */
+#define GPIO107_CIF_DD_8        107     /* Camera data pin 8 */
+#define GPIO108_CIF_DD_7        108     /* Camera data pin 7 */
+#define GPIO109_MMCDAT1         109     /* MMC DAT1 (PXA27x) */
+#define GPIO110_MMCDAT2         110     /* MMC DAT2 (PXA27x) */
+#define GPIO110_MMCCS0          110     /* MMC Chip Select 0 (PXA27x) */
+#define GPIO111_MMCDAT3         111     /* MMC DAT3 (PXA27x) */
+#define GPIO111_MMCCS1          111     /* MMC Chip Select 1 (PXA27x) */
+#define GPIO112_MMCCMD          112     /* MMC CMD (PXA27x) */
+#define GPIO113_I2S_SYSCLK      113     /* I2S System Clock (PXA27x) */
+#define GPIO113_AC97_RESET_N    113     /* AC97 NRESET on (PXA27x) */
+#define GPIO114_CIF_DD_1        114     /* Camera data pin 1 */
+#define GPIO115_CIF_DD_3        115     /* Camera data pin 3 */
+#define GPIO116_CIF_DD_2        116     /* Camera data pin 2 */
+
+/* GPIO alternate function mode & direction */
+
+#define GPIO_IN                 0x000
+#define GPIO_OUT                0x080
+#define GPIO_ALT_FN_1_IN        0x100
+#define GPIO_ALT_FN_1_OUT       0x180
+#define GPIO_ALT_FN_2_IN        0x200
+#define GPIO_ALT_FN_2_OUT       0x280
+#define GPIO_ALT_FN_3_IN        0x300
+#define GPIO_ALT_FN_3_OUT       0x380
+#define GPIO_MD_MASK_NR         0x07f
+#define GPIO_MD_MASK_DIR        0x080
+#define GPIO_MD_MASK_FN         0x300
+#define GPIO_DFLT_LOW           0x400
+#define GPIO_DFLT_HIGH          0x800
+
+#define GPIO1_RTS_MD            ( 1 | GPIO_ALT_FN_1_IN)
+#define GPIO6_MMCCLK_MD         ( 6 | GPIO_ALT_FN_1_OUT)
+#define GPIO7_48MHz_MD          ( 7 | GPIO_ALT_FN_1_OUT)
+#define GPIO8_MMCCS0_MD         ( 8 | GPIO_ALT_FN_1_OUT)
+#define GPIO9_MMCCS1_MD         ( 9 | GPIO_ALT_FN_1_OUT)
+#define GPIO10_RTCCLK_MD        (10 | GPIO_ALT_FN_1_OUT)
+#define GPIO11_3_6MHz_MD        (11 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_32KHz_MD         (12 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_CIF_DD_7_MD      (12 | GPIO_ALT_FN_2_IN)
+#define GPIO13_MBGNT_MD         (13 | GPIO_ALT_FN_2_OUT)
+#define GPIO14_MBREQ_MD         (14 | GPIO_ALT_FN_1_IN)
+#define GPIO15_nCS_1_MD         (15 | GPIO_ALT_FN_2_OUT)
+#define GPIO16_PWM0_MD          (16 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_PWM1_MD          (17 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_CIF_DD_6_MD      (17 | GPIO_ALT_FN_2_IN)
+#define GPIO18_RDY_MD           (18 | GPIO_ALT_FN_1_IN)
+#define GPIO19_DREQ1_MD         (19 | GPIO_ALT_FN_1_IN)
+#define GPIO20_DREQ0_MD         (20 | GPIO_ALT_FN_1_IN)
+#define GPIO23_CIF_MCLK_MD      (23 | GPIO_ALT_FN_1_OUT)
+#define GPIO23_SCLK_MD          (23 | GPIO_ALT_FN_2_OUT)
+#define GPIO24_CIF_FV_MD        (24 | GPIO_ALT_FN_1_OUT)
+#define GPIO24_SFRM_MD          (24 | GPIO_ALT_FN_2_OUT)
+#define GPIO25_CIF_LV_MD        (25 | GPIO_ALT_FN_1_OUT)
+#define GPIO25_STXD_MD          (25 | GPIO_ALT_FN_2_OUT)
+#define GPIO26_SRXD_MD          (26 | GPIO_ALT_FN_1_IN)
+#define GPIO26_CIF_PCLK_MD      (26 | GPIO_ALT_FN_2_IN)
+#define GPIO27_SEXTCLK_MD       (27 | GPIO_ALT_FN_1_IN)
+#define GPIO27_CIF_DD_0_MD      (27 | GPIO_ALT_FN_3_IN)
+#define GPIO28_BITCLK_AC97_MD   (28 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
+#define GPIO28_BITCLK_OUT_I2S_MD        (28 | GPIO_ALT_FN_1_OUT)
+#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
+#define GPIO29_SDATA_IN_I2S_MD  (29 | GPIO_ALT_FN_2_IN)
+#define GPIO30_SDATA_OUT_AC97_MD        (30 | GPIO_ALT_FN_2_OUT)
+#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_I2S_MD      (31 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_AC97_MD     (31 | GPIO_ALT_FN_2_OUT)
+#define GPIO32_SDATA_IN1_AC97_MD        (32 | GPIO_ALT_FN_1_IN)
+#define GPIO32_SYSCLK_I2S_MD    (32 | GPIO_ALT_FN_1_OUT)
+#define GPIO32_MMCCLK_MD        (32 | GPIO_ALT_FN_2_OUT)
+#define GPIO33_nCS_5_MD         (33 | GPIO_ALT_FN_2_OUT)
+#define GPIO34_FFRXD_MD         (34 | GPIO_ALT_FN_1_IN)
+#define GPIO34_MMCCS0_MD        (34 | GPIO_ALT_FN_2_OUT)
+#define GPIO35_FFCTS_MD         (35 | GPIO_ALT_FN_1_IN)
+#define GPIO35_KP_MKOUT6_MD     (35 | GPIO_ALT_FN_2_OUT)
+#define GPIO36_FFDCD_MD         (36 | GPIO_ALT_FN_1_IN)
+#define GPIO37_FFDSR_MD         (37 | GPIO_ALT_FN_1_IN)
+#define GPIO38_FFRI_MD          (38 | GPIO_ALT_FN_1_IN)
+#define GPIO39_MMCCS1_MD        (39 | GPIO_ALT_FN_1_OUT)
+#define GPIO39_FFTXD_MD         (39 | GPIO_ALT_FN_2_OUT)
+#define GPIO40_FFDTR_MD         (40 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_FFRTS_MD         (41 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_KP_MKOUT7_MD     (41 | GPIO_ALT_FN_1_OUT)
+#define GPIO42_BTRXD_MD         (42 | GPIO_ALT_FN_1_IN)
+#define GPIO42_HWRXD_MD         (42 | GPIO_ALT_FN_3_IN)
+#define GPIO42_CIF_MCLK_MD      (42 | GPIO_ALT_FN_3_OUT)
+#define GPIO43_BTTXD_MD         (43 | GPIO_ALT_FN_2_OUT)
+#define GPIO43_HWTXD_MD         (43 | GPIO_ALT_FN_3_OUT)
+#define GPIO43_CIF_FV_MD        (43 | GPIO_ALT_FN_3_OUT)
+#define GPIO44_BTCTS_MD         (44 | GPIO_ALT_FN_1_IN)
+#define GPIO44_HWCTS_MD         (44 | GPIO_ALT_FN_3_IN)
+#define GPIO44_CIF_LV_MD        (44 | GPIO_ALT_FN_3_OUT)
+#define GPIO45_CIF_PCLK_MD      (45 | GPIO_ALT_FN_3_IN)
+#define GPIO45_BTRTS_MD         (45 | GPIO_ALT_FN_2_OUT)
+#define GPIO45_HWRTS_MD         (45 | GPIO_ALT_FN_3_OUT)
+#define GPIO45_SYSCLK_AC97_MD   (45 | GPIO_ALT_FN_1_OUT)
+#define GPIO46_ICPRXD_MD        (46 | GPIO_ALT_FN_1_IN)
+#define GPIO46_STRXD_MD         (46 | GPIO_ALT_FN_2_IN)
+#define GPIO47_CIF_DD_0_MD      (47 | GPIO_ALT_FN_1_IN)
+#define GPIO47_ICPTXD_MD        (47 | GPIO_ALT_FN_2_OUT)
+#define GPIO47_STTXD_MD         (47 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_CIF_DD_5_MD      (48 | GPIO_ALT_FN_1_IN)
+#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO48_HWTXD_MD         (48 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO49_HWRXD_MD         (49 | GPIO_ALT_FN_1_IN)
+#define GPIO49_nPWE_MD          (49 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_CIF_DD_3_MD      (50 | GPIO_ALT_FN_1_IN)
+#define GPIO50_nPIOR_MD         (50 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_HWCTS_MD         (50 | GPIO_ALT_FN_1_IN)
+#define GPIO50_CIF_DD_3_MD      (50 | GPIO_ALT_FN_1_IN)
+#define GPIO51_CIF_DD_2_MD      (51 | GPIO_ALT_FN_1_IN)
+#define GPIO51_nPIOW_MD         (51 | GPIO_ALT_FN_2_OUT)
+#define GPIO51_HWRTS_MD         (51 | GPIO_ALT_FN_1_OUT)
+#define GPIO51_CIF_DD_2_MD      (51 | GPIO_ALT_FN_1_IN)
+#define GPIO52_nPCE_1_MD        (52 | GPIO_ALT_FN_2_OUT)
+#define GPIO52_CIF_DD_4_MD      (52 | GPIO_ALT_FN_1_IN)
+#define GPIO53_nPCE_2_MD        (53 | GPIO_ALT_FN_2_OUT)
+#define GPIO53_MMCCLK_MD        (53 | GPIO_ALT_FN_1_OUT)
+#define GPIO53_CIF_MCLK_MD      (53 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_MMCCLK_MD        (54 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_nPCE_2_MD        (54 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_pSKTSEL_MD       (54 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_CIF_PCLK_MD      (54 | GPIO_ALT_FN_3_IN)
+#define GPIO55_nPREG_MD         (55 | GPIO_ALT_FN_2_OUT)
+#define GPIO55_CIF_DD_1_MD      (55 | GPIO_ALT_FN_1_IN)
+#define GPIO56_nPWAIT_MD        (56 | GPIO_ALT_FN_1_IN)
+#define GPIO57_nIOIS16_MD       (57 | GPIO_ALT_FN_1_IN)
+#define GPIO58_LDD_0_MD         (58 | GPIO_ALT_FN_2_OUT)
+#define GPIO59_LDD_1_MD         (59 | GPIO_ALT_FN_2_OUT)
+#define GPIO60_LDD_2_MD         (60 | GPIO_ALT_FN_2_OUT)
+#define GPIO61_LDD_3_MD         (61 | GPIO_ALT_FN_2_OUT)
+#define GPIO62_LDD_4_MD         (62 | GPIO_ALT_FN_2_OUT)
+#define GPIO63_LDD_5_MD         (63 | GPIO_ALT_FN_2_OUT)
+#define GPIO64_LDD_6_MD         (64 | GPIO_ALT_FN_2_OUT)
+#define GPIO65_LDD_7_MD         (65 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_LDD_8_MD         (66 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_MBREQ_MD         (66 | GPIO_ALT_FN_1_IN)
+#define GPIO67_LDD_9_MD         (67 | GPIO_ALT_FN_2_OUT)
+#define GPIO67_MMCCS0_MD        (67 | GPIO_ALT_FN_1_OUT)
+#define GPIO68_LDD_10_MD        (68 | GPIO_ALT_FN_2_OUT)
+#define GPIO68_MMCCS1_MD        (68 | GPIO_ALT_FN_1_OUT)
+#define GPIO69_LDD_11_MD        (69 | GPIO_ALT_FN_2_OUT)
+#define GPIO69_MMCCLK_MD        (69 | GPIO_ALT_FN_1_OUT)
+#define GPIO70_LDD_12_MD        (70 | GPIO_ALT_FN_2_OUT)
+#define GPIO70_RTCCLK_MD        (70 | GPIO_ALT_FN_1_OUT)
+#define GPIO71_LDD_13_MD        (71 | GPIO_ALT_FN_2_OUT)
+#define GPIO71_3_6MHz_MD        (71 | GPIO_ALT_FN_1_OUT)
+#define GPIO72_LDD_14_MD        (72 | GPIO_ALT_FN_2_OUT)
+#define GPIO72_32kHz_MD         (72 | GPIO_ALT_FN_1_OUT)
+#define GPIO73_LDD_15_MD        (73 | GPIO_ALT_FN_2_OUT)
+#define GPIO73_MBGNT_MD         (73 | GPIO_ALT_FN_1_OUT)
+#define GPIO74_LCD_FCLK_MD      (74 | GPIO_ALT_FN_2_OUT)
+#define GPIO75_LCD_LCLK_MD      (75 | GPIO_ALT_FN_2_OUT)
+#define GPIO76_LCD_PCLK_MD      (76 | GPIO_ALT_FN_2_OUT)
+#define GPIO77_LCD_ACBIAS_MD    (77 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nCS_2_MD         (78 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nPCE_2_MD        (78 | GPIO_ALT_FN_1_OUT)
+#define GPIO79_nCS_3_MD         (79 | GPIO_ALT_FN_2_OUT)
+#define GPIO79_pSKTSEL_MD       (79 | GPIO_ALT_FN_1_OUT)
+#define GPIO80_nCS_4_MD         (80 | GPIO_ALT_FN_2_OUT)
+#define GPIO81_NSSP_CLK_OUT     (81 | GPIO_ALT_FN_1_OUT)
+#define GPIO81_NSSP_CLK_IN      (81 | GPIO_ALT_FN_1_IN)
+#define GPIO81_CIF_DD_0_MD      (81 | GPIO_ALT_FN_2_IN)
+#define GPIO82_NSSP_FRM_OUT     (82 | GPIO_ALT_FN_1_OUT)
+#define GPIO82_NSSP_FRM_IN      (82 | GPIO_ALT_FN_1_IN)
+#define GPIO82_CIF_DD_5_MD      (82 | GPIO_ALT_FN_3_IN)
+#define GPIO83_NSSP_TX          (83 | GPIO_ALT_FN_1_OUT)
+#define GPIO83_NSSP_RX          (83 | GPIO_ALT_FN_2_IN)
+#define GPIO83_CIF_DD_4_MD      (83 | GPIO_ALT_FN_3_IN)
+#define GPIO84_NSSP_TX          (84 | GPIO_ALT_FN_1_OUT)
+#define GPIO84_NSSP_RX          (84 | GPIO_ALT_FN_2_IN)
+#define GPIO84_CIF_FV_MD        (84 | GPIO_ALT_FN_3_IN)
+#define GPIO85_nPCE_1_MD        (85 | GPIO_ALT_FN_1_OUT)
+#define GPIO85_CIF_LV_MD        (85 | GPIO_ALT_FN_3_IN)
+#define GPIO86_nPCE_1_MD        (86 | GPIO_ALT_FN_1_OUT)
+#define GPIO90_CIF_DD_4_MD      (90 | GPIO_ALT_FN_3_IN)
+#define GPIO91_CIF_DD_5_MD      (91 | GPIO_ALT_FN_3_IN)
+#define GPIO92_MMCDAT0_MD       (92 | GPIO_ALT_FN_1_OUT)
+#define GPIO93_CIF_DD_6_MD      (93 | GPIO_ALT_FN_2_IN)
+#define GPIO94_CIF_DD_5_MD      (94 | GPIO_ALT_FN_2_IN)
+#define GPIO95_CIF_DD_4_MD      (95 | GPIO_ALT_FN_2_IN)
+#define GPIO95_KP_MKIN6_MD      (95 | GPIO_ALT_FN_3_IN)
+#define GPIO96_KP_DKIN3_MD      (96 | GPIO_ALT_FN_1_IN)
+#define GPIO97_KP_MKIN3_MD      (97 | GPIO_ALT_FN_3_IN)
+#define GPIO98_CIF_DD_0_MD      (98 | GPIO_ALT_FN_2_IN)
+#define GPIO100_KP_MKIN0_MD     (100 | GPIO_ALT_FN_1_IN)
+#define GPIO101_KP_MKIN1_MD     (101 | GPIO_ALT_FN_1_IN)
+#define GPIO102_nPCE_1_MD       (102 | GPIO_ALT_FN_1_OUT)
+#define GPIO102_KP_MKIN2_MD     (102 | GPIO_ALT_FN_1_IN)
+#define GPIO103_CIF_DD_3_MD     (103 | GPIO_ALT_FN_1_IN)
+#define GPIO103_KP_MKOUT0_MD    (103 | GPIO_ALT_FN_2_OUT)
+#define GPIO104_CIF_DD_2_MD     (104 | GPIO_ALT_FN_1_IN)
+#define GPIO104_pSKTSEL_MD      (104 | GPIO_ALT_FN_1_OUT)
+#define GPIO104_KP_MKOUT1_MD    (104 | GPIO_ALT_FN_2_OUT)
+#define GPIO105_CIF_DD_1_MD     (105 | GPIO_ALT_FN_1_IN)
+#define GPIO105_KP_MKOUT2_MD    (105 | GPIO_ALT_FN_2_OUT)
+#define GPIO106_CIF_DD_9_MD     (106 | GPIO_ALT_FN_1_IN)
+#define GPIO106_KP_MKOUT3_MD    (106 | GPIO_ALT_FN_2_OUT)
+#define GPIO107_CIF_DD_8_MD     (107 | GPIO_ALT_FN_1_IN)
+#define GPIO107_KP_MKOUT4_MD    (107 | GPIO_ALT_FN_2_OUT)
+#define GPIO108_CIF_DD_7_MD     (108 | GPIO_ALT_FN_1_IN)
+#define GPIO108_KP_MKOUT5_MD    (108 | GPIO_ALT_FN_2_OUT)
+#define GPIO109_MMCDAT1_MD      (109 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCDAT2_MD      (110 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCCS0_MD       (110 | GPIO_ALT_FN_1_OUT)
+#define GPIO111_MMCDAT3_MD      (111 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCCS1_MD       (111 | GPIO_ALT_FN_1_OUT)
+#define GPIO112_MMCCMD_MD       (112 | GPIO_ALT_FN_1_OUT)
+#define GPIO113_I2S_SYSCLK_MD   (113 | GPIO_ALT_FN_1_OUT)
+#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
+#define GPIO117_I2CSCL_MD       (117 | GPIO_ALT_FN_1_IN)
+#define GPIO118_I2CSDA_MD       (118 | GPIO_ALT_FN_1_IN)
+
+#endif /* __ASM_ARCH_PXA2XX_GPIO_H */
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
index 8e1b3ead827f..fe9364c83a28 100644
--- a/include/asm-arm/arch-pxa/pxa3xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -12,6 +12,15 @@
 
 #ifndef __ASM_ARCH_PXA3XX_REGS_H
 #define __ASM_ARCH_PXA3XX_REGS_H
+
+/*
+ * Oscillator Configuration Register (OSCC)
+ */
+#define OSCC           __REG(0x41350000)  /* Oscillator Configuration Register */
+
+#define OSCC_PEN       (1 << 11)       /* 13MHz POUT */
+
+
 /*
  * Service Power Management Unit (MPMU)
  */
diff --git a/include/asm-arm/arch-pxa/tosa.h b/include/asm-arm/arch-pxa/tosa.h
index c05e4faf85a6..c5b6fde6907c 100644
--- a/include/asm-arm/arch-pxa/tosa.h
+++ b/include/asm-arm/arch-pxa/tosa.h
@@ -23,11 +23,12 @@
 /*
  * SCOOP2 internal GPIOs
  */
+#define TOSA_SCOOP_GPIO_BASE            NR_BUILTIN_GPIO
 #define TOSA_SCOOP_PXA_VCORE1           SCOOP_GPCR_PA11
 #define TOSA_SCOOP_TC6393_REST_IN       SCOOP_GPCR_PA12
-#define TOSA_SCOOP_IR_POWERDWN          SCOOP_GPCR_PA13
-#define TOSA_SCOOP_SD_WP                SCOOP_GPCR_PA14
-#define TOSA_SCOOP_PWR_ON               SCOOP_GPCR_PA15
+#define TOSA_GPIO_IR_POWERDWN           (TOSA_SCOOP_GPIO_BASE + 2)
+#define TOSA_GPIO_SD_WP                 (TOSA_SCOOP_GPIO_BASE + 3)
+#define TOSA_GPIO_PWR_ON                (TOSA_SCOOP_GPIO_BASE + 4)
 #define TOSA_SCOOP_AUD_PWR_ON           SCOOP_GPCR_PA16
 #define TOSA_SCOOP_BT_RESET             SCOOP_GPCR_PA17
 #define TOSA_SCOOP_BT_PWR_EN            SCOOP_GPCR_PA18
@@ -35,7 +36,7 @@
 
 /* GPIO Direction   1 : output mode / 0:input mode */
 #define TOSA_SCOOP_IO_DIR     ( TOSA_SCOOP_PXA_VCORE1 | TOSA_SCOOP_TC6393_REST_IN | \
-                TOSA_SCOOP_IR_POWERDWN | TOSA_SCOOP_PWR_ON | TOSA_SCOOP_AUD_PWR_ON |\
+                TOSA_SCOOP_AUD_PWR_ON |\
                 TOSA_SCOOP_BT_RESET | TOSA_SCOOP_BT_PWR_EN )
 /* GPIO out put level when init   1: Hi */
 #define TOSA_SCOOP_IO_OUT     ( TOSA_SCOOP_TC6393_REST_IN )
@@ -43,23 +44,21 @@
 /*
  * SCOOP2 jacket GPIOs
  */
-#define TOSA_SCOOP_JC_BT_LED            SCOOP_GPCR_PA11
-#define TOSA_SCOOP_JC_NOTE_LED          SCOOP_GPCR_PA12
-#define TOSA_SCOOP_JC_CHRG_ERR_LED      SCOOP_GPCR_PA13
-#define TOSA_SCOOP_JC_USB_PULLUP        SCOOP_GPCR_PA14
+#define TOSA_SCOOP_JC_GPIO_BASE         (NR_BUILTIN_GPIO + 12)
+#define TOSA_GPIO_BT_LED                (TOSA_SCOOP_JC_GPIO_BASE + 0)
+#define TOSA_GPIO_NOTE_LED              (TOSA_SCOOP_JC_GPIO_BASE + 1)
+#define TOSA_GPIO_CHRG_ERR_LED          (TOSA_SCOOP_JC_GPIO_BASE + 2)
+#define TOSA_GPIO_USB_PULLUP            (TOSA_SCOOP_JC_GPIO_BASE + 3)
 #define TOSA_SCOOP_JC_TC6393_SUSPEND    SCOOP_GPCR_PA15
 #define TOSA_SCOOP_JC_TC3693_L3V_ON     SCOOP_GPCR_PA16
 #define TOSA_SCOOP_JC_WLAN_DETECT       SCOOP_GPCR_PA17
-#define TOSA_SCOOP_JC_WLAN_LED          SCOOP_GPCR_PA18
+#define TOSA_GPIO_WLAN_LED              (TOSA_SCOOP_JC_GPIO_BASE + 7)
 #define TOSA_SCOOP_JC_CARD_LIMIT_SEL    SCOOP_GPCR_PA19
 
 /* GPIO Direction   1 : output mode / 0:input mode */
-#define TOSA_SCOOP_JC_IO_DIR ( TOSA_SCOOP_JC_BT_LED | TOSA_SCOOP_JC_NOTE_LED | \
-                TOSA_SCOOP_JC_CHRG_ERR_LED | TOSA_SCOOP_JC_USB_PULLUP | \
+#define TOSA_SCOOP_JC_IO_DIR ( \
                 TOSA_SCOOP_JC_TC6393_SUSPEND | TOSA_SCOOP_JC_TC3693_L3V_ON | \
-                TOSA_SCOOP_JC_WLAN_LED | TOSA_SCOOP_JC_CARD_LIMIT_SEL )
-/* GPIO out put level when init   1: Hi */
-#define TOSA_SCOOP_JC_IO_OUT ( 0 )
+                TOSA_SCOOP_JC_CARD_LIMIT_SEL )
 
 /*
  * Timing Generator
@@ -74,15 +73,6 @@
 #define TG_HPOSCTL                      0x07
 
 /*
- * LED
- */
-#define TOSA_SCOOP_LED_BLUE             TOSA_SCOOP_GPCR_PA11
-#define TOSA_SCOOP_LED_GREEN            TOSA_SCOOP_GPCR_PA12
-#define TOSA_SCOOP_LED_ORANGE           TOSA_SCOOP_GPCR_PA13
-#define TOSA_SCOOP_LED_WLAN             TOSA_SCOOP_GPCR_PA18
-
-
-/*
  * PXA GPIOs
  */
 #define TOSA_GPIO_POWERON               (0)
@@ -161,12 +151,8 @@
 
 #define TOSA_IRQ_GPIO_MAIN_BAT_LOW      IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW)
 
-extern struct platform_device tosascoop_jc_device;
-extern struct platform_device tosascoop_device;
-
 #define TOSA_KEY_SYNC           KEY_102ND /* ??? */
 
-
 #ifndef CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES
 #define TOSA_KEY_RECORD         KEY_YEN
 #define TOSA_KEY_ADDRESSBOOK    KEY_KATAKANA
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index 5f717d64ea7d..4881b80f0f90 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -18,6 +18,8 @@ extern struct platform_mmc_slot zylonite_mmc_slot[];
 extern int gpio_backlight;
 extern int gpio_eth_irq;
 
+extern int wm9713_irq;
+
 extern int lcd_id;
 extern int lcd_orientation;
 
diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h
index 3e437b7f425a..206f7a752882 100644
--- a/include/asm-arm/arch-realview/board-eb.h
+++ b/include/asm-arm/arch-realview/board-eb.h
@@ -26,6 +26,26 @@
 /*
  * RealView EB + ARM11MPCore peripheral addresses
  */
+#define REALVIEW_EB_UART0_BASE          0x10009000      /* UART 0 */
+#define REALVIEW_EB_UART1_BASE          0x1000A000      /* UART 1 */
+#define REALVIEW_EB_UART2_BASE          0x1000B000      /* UART 2 */
+#define REALVIEW_EB_UART3_BASE          0x1000C000      /* UART 3 */
+#define REALVIEW_EB_SSP_BASE            0x1000D000      /* Synchronous Serial Port */
+#define REALVIEW_EB_WATCHDOG_BASE       0x10010000      /* watchdog interface */
+#define REALVIEW_EB_TIMER0_1_BASE       0x10011000      /* Timer 0 and 1 */
+#define REALVIEW_EB_TIMER2_3_BASE       0x10012000      /* Timer 2 and 3 */
+#define REALVIEW_EB_GPIO0_BASE          0x10013000      /* GPIO port 0 */
+#define REALVIEW_EB_RTC_BASE            0x10017000      /* Real Time Clock */
+#define REALVIEW_EB_CLCD_BASE           0x10020000      /* CLCD */
+#define REALVIEW_EB_GIC_CPU_BASE        0x10040000      /* Generic interrupt controller CPU interface */
+#define REALVIEW_EB_GIC_DIST_BASE       0x10041000      /* Generic interrupt controller distributor */
+#define REALVIEW_EB_SMC_BASE            0x10080000      /* Static memory controller */
+
+#define REALVIEW_EB_FLASH_BASE          0x40000000
+#define REALVIEW_EB_FLASH_SIZE          SZ_64M
+#define REALVIEW_EB_ETH_BASE            0x4E000000      /* Ethernet */
+#define REALVIEW_EB_USB_BASE            0x4F000000      /* USB */
+
 #ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
 #define REALVIEW_EB11MP_SCU_BASE        0x10100000      /* SCU registers */
 #define REALVIEW_EB11MP_GIC_CPU_BASE    0x10100100      /* Generic interrupt controller CPU interface */
diff --git a/include/asm-arm/arch-realview/board-pb1176.h b/include/asm-arm/arch-realview/board-pb1176.h
new file mode 100644
index 000000000000..48ce9c833705
--- /dev/null
+++ b/include/asm-arm/arch-realview/board-pb1176.h
@@ -0,0 +1,152 @@
+/*
+ * include/asm-arm/arch-realview/board-pb1176.h
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_BOARD_PB1176_H
+#define __ASM_ARCH_BOARD_PB1176_H
+
+#include <asm/arch/platform.h>
+
+/*
+ * Peripheral addresses
+ */
+#define REALVIEW_PB1176_SCTL_BASE               0x10100000 /* System controller */
+#define REALVIEW_PB1176_SMC_BASE                0x10111000 /* SMC */
+#define REALVIEW_PB1176_DMC_BASE                0x10109000 /* DMC configuration */
+#define REALVIEW_PB1176_SDRAM67_BASE            0x70000000 /* SDRAM banks 6 and 7 */
+#define REALVIEW_PB1176_FLASH_BASE              0x30000000
+#define REALVIEW_PB1176_FLASH_SIZE              SZ_64M
+
+#define REALVIEW_PB1176_TIMER0_1_BASE           0x10104000 /* Timer 0 and 1 */
+#define REALVIEW_PB1176_TIMER2_3_BASE           0x10105000 /* Timer 2 and 3 */
+#define REALVIEW_PB1176_TIMER4_5_BASE           0x10106000 /* Timer 4 and 5 */
+#define REALVIEW_PB1176_WATCHDOG_BASE           0x10107000 /* watchdog interface */
+#define REALVIEW_PB1176_RTC_BASE                0x10108000 /* Real Time Clock */
+#define REALVIEW_PB1176_GPIO0_BASE              0x1010A000 /* GPIO port 0 */
+#define REALVIEW_PB1176_SSP_BASE                0x1010B000 /* Synchronous Serial Port */
+#define REALVIEW_PB1176_UART0_BASE              0x1010C000 /* UART 0 */
+#define REALVIEW_PB1176_UART1_BASE              0x1010D000 /* UART 1 */
+#define REALVIEW_PB1176_UART2_BASE              0x1010E000 /* UART 2 */
+#define REALVIEW_PB1176_UART3_BASE              0x1010F000 /* UART 3 */
+#define REALVIEW_PB1176_CLCD_BASE               0x10112000 /* CLCD */
+#define REALVIEW_PB1176_ETH_BASE                0x3A000000 /* Ethernet */
+#define REALVIEW_PB1176_USB_BASE                0x3B000000 /* USB */
+
+/*
+ * PCI regions
+ */
+#define REALVIEW_PB1176_PCI_BASE                0x60000000 /* PCI self config */
+#define REALVIEW_PB1176_PCI_CFG_BASE            0x61000000 /* PCI config */
+#define REALVIEW_PB1176_PCI_IO_BASE0            0x62000000 /* PCI IO region */
+#define REALVIEW_PB1176_PCI_MEM_BASE0           0x63000000 /* Memory region 1 */
+#define REALVIEW_PB1176_PCI_MEM_BASE1           0x64000000 /* Memory region 2 */
+#define REALVIEW_PB1176_PCI_MEM_BASE2           0x68000000 /* Memory region 3 */
+
+#define REALVIEW_PB1176_PCI_BASE_SIZE           0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_CFG_BASE_SIZE       0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_IO_BASE0_SIZE       0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_MEM_BASE0_SIZE      0x01000000 /* 16MB */
+#define REALVIEW_PB1176_PCI_MEM_BASE1_SIZE      0x04000000 /* 64MB */
+#define REALVIEW_PB1176_PCI_MEM_BASE2_SIZE      0x08000000 /* 128MB */
+
+#define REALVIEW_DC1176_GIC_CPU_BASE            0x10120000 /* GIC CPU interface, on devchip */
+#define REALVIEW_DC1176_GIC_DIST_BASE           0x10121000 /* GIC distributor, on devchip */
+#define REALVIEW_PB1176_GIC_CPU_BASE            0x10040000 /* GIC CPU interface, on FPGA */
+#define REALVIEW_PB1176_GIC_DIST_BASE           0x10041000 /* GIC distributor, on FPGA */
+#define REALVIEW_PB1176_L220_BASE               0x10110000 /* L220 registers */
+
+/*
+ * Irqs
+ */
+#define IRQ_DC1176_GIC_START                    32
+#define IRQ_PB1176_GIC_START                    64
+
+/*
+ * ARM1176 DevChip interrupt sources (primary GIC)
+ */
+#define IRQ_DC1176_WATCHDOG     (IRQ_DC1176_GIC_START + 0)      /* Watchdog timer */
+#define IRQ_DC1176_SOFTINT      (IRQ_DC1176_GIC_START + 1)      /* Software interrupt */
+#define IRQ_DC1176_COMMRx       (IRQ_DC1176_GIC_START + 2)      /* Debug Comm Rx interrupt */
+#define IRQ_DC1176_COMMTx       (IRQ_DC1176_GIC_START + 3)      /* Debug Comm Tx interrupt */
+#define IRQ_DC1176_TIMER0       (IRQ_DC1176_GIC_START + 8)      /* Timer 0 */
+#define IRQ_DC1176_TIMER1       (IRQ_DC1176_GIC_START + 9)      /* Timer 1 */
+#define IRQ_DC1176_TIMER2       (IRQ_DC1176_GIC_START + 10)     /* Timer 2 */
+#define IRQ_DC1176_APC          (IRQ_DC1176_GIC_START + 11)
+#define IRQ_DC1176_IEC          (IRQ_DC1176_GIC_START + 12)
+#define IRQ_DC1176_L2CC         (IRQ_DC1176_GIC_START + 13)
+#define IRQ_DC1176_RTC          (IRQ_DC1176_GIC_START + 14)
+#define IRQ_DC1176_CLCD         (IRQ_DC1176_GIC_START + 15)     /* CLCD controller */
+#define IRQ_DC1176_UART0        (IRQ_DC1176_GIC_START + 18)     /* UART 0 on development chip */
+#define IRQ_DC1176_UART1        (IRQ_DC1176_GIC_START + 19)     /* UART 1 on development chip */
+#define IRQ_DC1176_UART2        (IRQ_DC1176_GIC_START + 20)     /* UART 2 on development chip */
+#define IRQ_DC1176_UART3        (IRQ_DC1176_GIC_START + 21)     /* UART 3 on development chip */
+
+#define IRQ_DC1176_PB_IRQ2      (IRQ_DC1176_GIC_START + 30)     /* tile GIC */
+#define IRQ_DC1176_PB_IRQ1      (IRQ_DC1176_GIC_START + 31)     /* main GIC */
+
+/*
+ * RealView PB1176 interrupt sources (secondary GIC)
+ */
+#define IRQ_PB1176_MMCI0A       (IRQ_PB1176_GIC_START + 1)      /* Multimedia Card 0A */
+#define IRQ_PB1176_MMCI0B       (IRQ_PB1176_GIC_START + 2)      /* Multimedia Card 0A */
+#define IRQ_PB1176_KMI0         (IRQ_PB1176_GIC_START + 3)      /* Keyboard/Mouse port 0 */
+#define IRQ_PB1176_KMI1         (IRQ_PB1176_GIC_START + 4)      /* Keyboard/Mouse port 1 */
+#define IRQ_PB1176_SCI          (IRQ_PB1176_GIC_START + 5)
+#define IRQ_PB1176_UART4        (IRQ_PB1176_GIC_START + 6)      /* UART 4 on baseboard */
+#define IRQ_PB1176_CHARLCD      (IRQ_PB1176_GIC_START + 7)      /* Character LCD */
+#define IRQ_PB1176_GPIO1        (IRQ_PB1176_GIC_START + 8)
+#define IRQ_PB1176_GPIO2        (IRQ_PB1176_GIC_START + 9)
+#define IRQ_PB1176_ETH          (IRQ_PB1176_GIC_START + 10)     /* Ethernet controller */
+#define IRQ_PB1176_USB          (IRQ_PB1176_GIC_START + 11)     /* USB controller */
+
+#define IRQ_PB1176_PISMO        (IRQ_PB1176_GIC_START + 16)
+
+#define IRQ_PB1176_AACI         (IRQ_PB1176_GIC_START + 19)     /* Audio Codec */
+
+#define IRQ_PB1176_TIMER0_1     (IRQ_PB1176_GIC_START + 22)
+#define IRQ_PB1176_TIMER2_3     (IRQ_PB1176_GIC_START + 23)
+#define IRQ_PB1176_DMAC         (IRQ_PB1176_GIC_START + 24)     /* DMA controller */
+#define IRQ_PB1176_RTC          (IRQ_PB1176_GIC_START + 25)     /* Real Time Clock */
+
+#define IRQ_PB1176_GPIO0        -1
+#define IRQ_PB1176_SSP          -1
+#define IRQ_PB1176_SCTL         -1
+
+#define NR_GIC_PB1176           2
+
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PB1176
+ */
+#define NR_IRQS_PB1176          (IRQ_DC1176_GIC_START + 96)
+
+#if defined(CONFIG_MACH_REALVIEW_PB1176)
+
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB1176)
+#undef NR_IRQS
+#define NR_IRQS                 NR_IRQS_PB1176
+#endif
+
+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB1176)
+#undef MAX_GIC_NR
+#define MAX_GIC_NR              NR_GIC_PB1176
+#endif
+
+#endif  /* CONFIG_MACH_REALVIEW_PB1176 */
+
+#endif  /* __ASM_ARCH_BOARD_PB1176_H */
diff --git a/include/asm-arm/arch-realview/board-pb11mp.h b/include/asm-arm/arch-realview/board-pb11mp.h
new file mode 100644
index 000000000000..a1294d915fa8
--- /dev/null
+++ b/include/asm-arm/arch-realview/board-pb11mp.h
@@ -0,0 +1,186 @@
+/*
+ * include/asm-arm/arch-realview/board-pb11mp.h
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_BOARD_PB11MP_H
+#define __ASM_ARCH_BOARD_PB11MP_H
+
+#include <asm/arch/platform.h>
+
+/*
+ * Peripheral addresses
+ */
+#define REALVIEW_PB11MP_UART0_BASE              0x10009000      /* UART 0 */
+#define REALVIEW_PB11MP_UART1_BASE              0x1000A000      /* UART 1 */
+#define REALVIEW_PB11MP_UART2_BASE              0x1000B000      /* UART 2 */
+#define REALVIEW_PB11MP_UART3_BASE              0x1000C000      /* UART 3 */
+#define REALVIEW_PB11MP_SSP_BASE                0x1000D000      /* Synchronous Serial Port */
+#define REALVIEW_PB11MP_WATCHDOG0_BASE          0x1000F000      /* Watchdog 0 */
+#define REALVIEW_PB11MP_WATCHDOG_BASE           0x10010000      /* watchdog interface */
+#define REALVIEW_PB11MP_TIMER0_1_BASE           0x10011000      /* Timer 0 and 1 */
+#define REALVIEW_PB11MP_TIMER2_3_BASE           0x10012000      /* Timer 2 and 3 */
+#define REALVIEW_PB11MP_GPIO0_BASE              0x10013000      /* GPIO port 0 */
+#define REALVIEW_PB11MP_RTC_BASE                0x10017000      /* Real Time Clock */
+#define REALVIEW_PB11MP_TIMER4_5_BASE           0x10018000      /* Timer 4/5 */
+#define REALVIEW_PB11MP_TIMER6_7_BASE           0x10019000      /* Timer 6/7 */
+#define REALVIEW_PB11MP_SCTL_BASE               0x1001A000      /* System Controller */
+#define REALVIEW_PB11MP_CLCD_BASE               0x10020000      /* CLCD */
+#define REALVIEW_PB11MP_ONB_SRAM_BASE           0x10060000      /* On-board SRAM */
+#define REALVIEW_PB11MP_DMC_BASE                0x100E0000      /* DMC configuration */
+#define REALVIEW_PB11MP_SMC_BASE                0x100E1000      /* SMC configuration */
+#define REALVIEW_PB11MP_CAN_BASE                0x100E2000      /* CAN bus */
+#define REALVIEW_PB11MP_CF_BASE                 0x18000000      /* Compact flash */
+#define REALVIEW_PB11MP_CF_MEM_BASE             0x18003000      /* SMC for Compact flash */
+#define REALVIEW_PB11MP_GIC_CPU_BASE            0x1E000000      /* Generic interrupt controller CPU interface */
+#define REALVIEW_PB11MP_FLASH0_BASE             0x40000000
+#define REALVIEW_PB11MP_FLASH0_SIZE             SZ_64M
+#define REALVIEW_PB11MP_FLASH1_BASE             0x44000000
+#define REALVIEW_PB11MP_FLASH1_SIZE             SZ_64M
+#define REALVIEW_PB11MP_ETH_BASE                0x4E000000      /* Ethernet */
+#define REALVIEW_PB11MP_USB_BASE                0x4F000000      /* USB */
+#define REALVIEW_PB11MP_GIC_DIST_BASE           0x1E001000      /* Generic interrupt controller distributor */
+#define REALVIEW_PB11MP_LT_BASE                 0xC0000000      /* Logic Tile expansion */
+#define REALVIEW_PB11MP_SDRAM6_BASE             0x70000000      /* SDRAM bank 6 256MB */
+#define REALVIEW_PB11MP_SDRAM7_BASE             0x80000000      /* SDRAM bank 7 256MB */
+
+#define REALVIEW_PB11MP_SYS_PLD_CTRL1           0x74
+
+/*
+ * PB11MPCore PCI regions
+ */
+#define REALVIEW_PB11MP_PCI_BASE                0x90040000      /* PCI-X Unit base */
+#define REALVIEW_PB11MP_PCI_IO_BASE             0x90050000      /* IO Region on AHB */
+#define REALVIEW_PB11MP_PCI_MEM_BASE            0xA0000000      /* MEM Region on AHB */
+
+#define REALVIEW_PB11MP_PCI_BASE_SIZE           0x10000         /* 16 Kb */
+#define REALVIEW_PB11MP_PCI_IO_SIZE             0x1000          /* 4 Kb */
+#define REALVIEW_PB11MP_PCI_MEM_SIZE            0x20000000      /* 512 MB */
+
+/*
+ * Testchip peripheral and fpga gic regions
+ */
+#define REALVIEW_TC11MP_SCU_BASE                0x1F000000      /* IRQ, Test chip */
+#define REALVIEW_TC11MP_GIC_CPU_BASE            0x1F000100      /* Test chip interrupt controller CPU interface */
+#define REALVIEW_TC11MP_TWD_BASE                0x1F000700
+#define REALVIEW_TC11MP_TWD_SIZE                0x00000100
+#define REALVIEW_TC11MP_GIC_DIST_BASE           0x1F001000      /* Test chip interrupt controller distributor */
+#define REALVIEW_TC11MP_L220_BASE               0x1F002000      /* L220 registers */
+
+/*
+ * Irqs
+ */
+#define IRQ_TC11MP_GIC_START                    32
+#define IRQ_PB11MP_GIC_START                    64
+
+/*
+ * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
+ */
+#define IRQ_TC11MP_AACI         (IRQ_TC11MP_GIC_START + 0)
+#define IRQ_TC11MP_TIMER0_1     (IRQ_TC11MP_GIC_START + 1)
+#define IRQ_TC11MP_TIMER2_3     (IRQ_TC11MP_GIC_START + 2)
+#define IRQ_TC11MP_USB          (IRQ_TC11MP_GIC_START + 3)
+#define IRQ_TC11MP_UART0        (IRQ_TC11MP_GIC_START + 4)
+#define IRQ_TC11MP_UART1        (IRQ_TC11MP_GIC_START + 5)
+#define IRQ_TC11MP_RTC          (IRQ_TC11MP_GIC_START + 6)
+#define IRQ_TC11MP_KMI0         (IRQ_TC11MP_GIC_START + 7)
+#define IRQ_TC11MP_KMI1         (IRQ_TC11MP_GIC_START + 8)
+#define IRQ_TC11MP_ETH          (IRQ_TC11MP_GIC_START + 9)
+#define IRQ_TC11MP_PB_IRQ1      (IRQ_TC11MP_GIC_START + 10)             /* main GIC */
+#define IRQ_TC11MP_PB_IRQ2      (IRQ_TC11MP_GIC_START + 11)             /* tile GIC */
+#define IRQ_TC11MP_PB_FIQ1      (IRQ_TC11MP_GIC_START + 12)             /* main GIC */
+#define IRQ_TC11MP_PB_FIQ2      (IRQ_TC11MP_GIC_START + 13)             /* tile GIC */
+#define IRQ_TC11MP_MMCI0A       (IRQ_TC11MP_GIC_START + 14)
+#define IRQ_TC11MP_MMCI0B       (IRQ_TC11MP_GIC_START + 15)
+
+#define IRQ_TC11MP_PMU_CPU0     (IRQ_TC11MP_GIC_START + 17)
+#define IRQ_TC11MP_PMU_CPU1     (IRQ_TC11MP_GIC_START + 18)
+#define IRQ_TC11MP_PMU_CPU2     (IRQ_TC11MP_GIC_START + 19)
+#define IRQ_TC11MP_PMU_CPU3     (IRQ_TC11MP_GIC_START + 20)
+#define IRQ_TC11MP_PMU_SCU0     (IRQ_TC11MP_GIC_START + 21)
+#define IRQ_TC11MP_PMU_SCU1     (IRQ_TC11MP_GIC_START + 22)
+#define IRQ_TC11MP_PMU_SCU2     (IRQ_TC11MP_GIC_START + 23)
+#define IRQ_TC11MP_PMU_SCU3     (IRQ_TC11MP_GIC_START + 24)
+#define IRQ_TC11MP_PMU_SCU4     (IRQ_TC11MP_GIC_START + 25)
+#define IRQ_TC11MP_PMU_SCU5     (IRQ_TC11MP_GIC_START + 26)
+#define IRQ_TC11MP_PMU_SCU6     (IRQ_TC11MP_GIC_START + 27)
+#define IRQ_TC11MP_PMU_SCU7     (IRQ_TC11MP_GIC_START + 28)
+
+#define IRQ_TC11MP_L220_EVENT   (IRQ_TC11MP_GIC_START + 29)
+#define IRQ_TC11MP_L220_SLAVE   (IRQ_TC11MP_GIC_START + 30)
+#define IRQ_TC11MP_L220_DECODE  (IRQ_TC11MP_GIC_START + 31)
+
+/*
+ * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
+ */
+#define IRQ_PB11MP_WATCHDOG     (IRQ_PB11MP_GIC_START + 0)      /* Watchdog timer */
+#define IRQ_PB11MP_SOFT         (IRQ_PB11MP_GIC_START + 1)      /* Software interrupt */
+#define IRQ_PB11MP_COMMRx       (IRQ_PB11MP_GIC_START + 2)      /* Debug Comm Rx interrupt */
+#define IRQ_PB11MP_COMMTx       (IRQ_PB11MP_GIC_START + 3)      /* Debug Comm Tx interrupt */
+#define IRQ_PB11MP_GPIO0        (IRQ_PB11MP_GIC_START + 6)      /* GPIO 0 */
+#define IRQ_PB11MP_GPIO1        (IRQ_PB11MP_GIC_START + 7)      /* GPIO 1 */
+#define IRQ_PB11MP_GPIO2        (IRQ_PB11MP_GIC_START + 8)      /* GPIO 2 */
+                                                                /* 9 reserved */
+#define IRQ_PB11MP_RTC_GIC1     (IRQ_PB11MP_GIC_START + 10)     /* Real Time Clock */
+#define IRQ_PB11MP_SSP          (IRQ_PB11MP_GIC_START + 11)     /* Synchronous Serial Port */
+#define IRQ_PB11MP_UART0_GIC1   (IRQ_PB11MP_GIC_START + 12)     /* UART 0 on development chip */
+#define IRQ_PB11MP_UART1_GIC1   (IRQ_PB11MP_GIC_START + 13)     /* UART 1 on development chip */
+#define IRQ_PB11MP_UART2        (IRQ_PB11MP_GIC_START + 14)     /* UART 2 on development chip */
+#define IRQ_PB11MP_UART3        (IRQ_PB11MP_GIC_START + 15)     /* UART 3 on development chip */
+#define IRQ_PB11MP_SCI          (IRQ_PB11MP_GIC_START + 16)     /* Smart Card Interface */
+#define IRQ_PB11MP_MMCI0A_GIC1  (IRQ_PB11MP_GIC_START + 17)     /* Multimedia Card 0A */
+#define IRQ_PB11MP_MMCI0B_GIC1  (IRQ_PB11MP_GIC_START + 18)     /* Multimedia Card 0B */
+#define IRQ_PB11MP_AACI_GIC1    (IRQ_PB11MP_GIC_START + 19)     /* Audio Codec */
+#define IRQ_PB11MP_KMI0_GIC1    (IRQ_PB11MP_GIC_START + 20)     /* Keyboard/Mouse port 0 */
+#define IRQ_PB11MP_KMI1_GIC1    (IRQ_PB11MP_GIC_START + 21)     /* Keyboard/Mouse port 1 */
+#define IRQ_PB11MP_CHARLCD      (IRQ_PB11MP_GIC_START + 22)     /* Character LCD */
+#define IRQ_PB11MP_CLCD         (IRQ_PB11MP_GIC_START + 23)     /* CLCD controller */
+#define IRQ_PB11MP_DMAC         (IRQ_PB11MP_GIC_START + 24)     /* DMA controller */
+#define IRQ_PB11MP_PWRFAIL      (IRQ_PB11MP_GIC_START + 25)     /* Power failure */
+#define IRQ_PB11MP_PISMO        (IRQ_PB11MP_GIC_START + 26)     /* PISMO interface */
+#define IRQ_PB11MP_DoC          (IRQ_PB11MP_GIC_START + 27)     /* Disk on Chip memory controller */
+#define IRQ_PB11MP_ETH_GIC1     (IRQ_PB11MP_GIC_START + 28)     /* Ethernet controller */
+#define IRQ_PB11MP_USB_GIC1     (IRQ_PB11MP_GIC_START + 29)     /* USB controller */
+#define IRQ_PB11MP_TSPEN        (IRQ_PB11MP_GIC_START + 30)     /* Touchscreen pen */
+#define IRQ_PB11MP_TSKPAD       (IRQ_PB11MP_GIC_START + 31)     /* Touchscreen keypad */
+
+#define IRQ_PB11MP_SMC          -1
+#define IRQ_PB11MP_SCTL         -1
+
+#define NR_GIC_PB11MP           2
+
+/*
+ * Only define NR_IRQS if less than NR_IRQS_PB11MP
+ */
+#define NR_IRQS_PB11MP          (IRQ_TC11MP_GIC_START + 96)
+
+#if defined(CONFIG_MACH_REALVIEW_PB11MP)
+
+#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP)
+#undef NR_IRQS
+#define NR_IRQS                 NR_IRQS_PB11MP
+#endif
+
+#if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP)
+#undef MAX_GIC_NR
+#define MAX_GIC_NR              NR_GIC_PB11MP
+#endif
+
+#endif  /* CONFIG_MACH_REALVIEW_PB11MP */
+
+#endif  /* __ASM_ARCH_BOARD_PB11MP_H */
diff --git a/include/asm-arm/arch-realview/debug-macro.S b/include/asm-arm/arch-realview/debug-macro.S
index f17efc65518a..c8c860c3c26e 100644
--- a/include/asm-arm/arch-realview/debug-macro.S
+++ b/include/asm-arm/arch-realview/debug-macro.S
@@ -15,7 +15,7 @@
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx,      #0x10000000
-                movne   \rx,      #0xf1000000   @ virtual base
+                movne   \rx,      #0xf0000000   @ virtual base
                 orr     \rx, \rx, #0x00009000
                 .endm
 
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h
index bad8d7ce9bfe..1ee8313ceb6a 100644
--- a/include/asm-arm/arch-realview/hardware.h
+++ b/include/asm-arm/arch-realview/hardware.h
@@ -25,7 +25,7 @@
 #include <asm/sizes.h>
 
 /* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x)           ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
+#define IO_ADDRESS(x)           (((x) & 0x0fffffff) + 0xf0000000)
 #define __io_address(n)         __io(IO_ADDRESS(n))
 
 #endif
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
index ad0c911002fc..ccbac59235c6 100644
--- a/include/asm-arm/arch-realview/irqs.h
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -23,6 +23,8 @@
 #define __ASM_ARCH_IRQS_H
 
 #include <asm/arch/board-eb.h>
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/board-pb1176.h>
 
 #define IRQ_LOCALTIMER          29
 #define IRQ_LOCALWDOG           30
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index 4fd351b5e4a2..424c0aaf46a0 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -32,9 +32,6 @@
 #define REALVIEW_SSRAM_BASE           /* REALVIEW_SSMC_BASE ? */
 #define REALVIEW_SSRAM_SIZE           SZ_2M
 
-#define REALVIEW_FLASH_BASE           0x40000000
-#define REALVIEW_FLASH_SIZE           SZ_64M
-
 /* 
  *  SDRAM
  */
@@ -175,42 +172,20 @@
 #define REALVIEW_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */
 
 /*
- * REALVIEW peripheral addresses
+ * RealView common peripheral addresses
  */
 #define REALVIEW_SCTL_BASE            0x10001000        /* System controller */
 #define REALVIEW_I2C_BASE             0x10002000        /* I2C control */
-        /* Reserved 0x10003000 */
 #define REALVIEW_AACI_BASE            0x10004000        /* Audio */
 #define REALVIEW_MMCI0_BASE           0x10005000        /* MMC interface */
 #define REALVIEW_KMI0_BASE            0x10006000        /* KMI interface */
 #define REALVIEW_KMI1_BASE            0x10007000        /* KMI 2nd interface */
 #define REALVIEW_CHAR_LCD_BASE        0x10008000        /* Character LCD */
-#define REALVIEW_UART0_BASE           0x10009000        /* UART 0 */
-#define REALVIEW_UART1_BASE           0x1000A000        /* UART 1 */
-#define REALVIEW_UART2_BASE           0x1000B000        /* UART 2 */
-#define REALVIEW_UART3_BASE           0x1000C000        /* UART 3 */
-#define REALVIEW_SSP_BASE             0x1000D000        /* Synchronous Serial Port */
 #define REALVIEW_SCI_BASE             0x1000E000        /* Smart card controller */
-        /* Reserved 0x1000F000 */
-#define REALVIEW_WATCHDOG_BASE        0x10010000        /* watchdog interface */
-#define REALVIEW_TIMER0_1_BASE        0x10011000        /* Timer 0 and 1 */
-#define REALVIEW_TIMER2_3_BASE        0x10012000        /* Timer 2 and 3 */
-#define REALVIEW_GPIO0_BASE           0x10013000        /* GPIO port 0 */
 #define REALVIEW_GPIO1_BASE           0x10014000        /* GPIO port 1 */
 #define REALVIEW_GPIO2_BASE           0x10015000        /* GPIO port 2 */
-        /* Reserved 0x10016000 */
-#define REALVIEW_RTC_BASE             0x10017000        /* Real Time Clock */
 #define REALVIEW_DMC_BASE             0x10018000        /* DMC configuration */
-#define REALVIEW_PCI_CORE_BASE        0x10019000        /* PCI configuration */
-        /* Reserved 0x1001A000 - 0x1001FFFF */
-#define REALVIEW_CLCD_BASE            0x10020000        /* CLCD */
 #define REALVIEW_DMAC_BASE            0x10030000        /* DMA controller */
-#define REALVIEW_GIC_CPU_BASE         0x10040000        /* Generic interrupt controller CPU interface */
-#define REALVIEW_GIC_DIST_BASE        0x10041000        /* Generic interrupt controller distributor */
-#define REALVIEW_SMC_BASE             0x10080000        /* SMC */
-        /* Reserved 0x10090000 - 0x100EFFFF */
-
-#define REALVIEW_ETH_BASE             0x4E000000        /* Ethernet */
 
 /* PCI space */
 #define REALVIEW_PCI_BASE             0x41000000        /* PCI Interface */
diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h
index 08b3db883c36..d55802d645af 100644
--- a/include/asm-arm/arch-realview/scu.h
+++ b/include/asm-arm/arch-realview/scu.h
@@ -1,8 +1,13 @@
 #ifndef __ASMARM_ARCH_SCU_H
 #define __ASMARM_ARCH_SCU_H
 
-#include <asm/arch/board-eb.h>
-
-#define SCU_BASE        REALVIEW_EB11MP_SCU_BASE
+/*
+ * SCU registers
+ */
+#define SCU_CTRL                0x00
+#define SCU_CONFIG              0x04
+#define SCU_CPU_STATUS          0x08
+#define SCU_INVALIDATE          0x0c
+#define SCU_FPGA_REVISION       0x10
 
 #endif
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
index 3d5c2db07a26..4c905d7a13a1 100644
--- a/include/asm-arm/arch-realview/uncompress.h
+++ b/include/asm-arm/arch-realview/uncompress.h
@@ -18,28 +18,50 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #include <asm/hardware.h>
+#include <asm/mach-types.h>
 
-#include <asm/arch/platform.h>
+#include <asm/arch/board-eb.h>
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/board-pb1176.h>
 
-#define AMBA_UART_DR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
-#define AMBA_UART_LCRH  (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
-#define AMBA_UART_CR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
-#define AMBA_UART_FR    (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x18))
+#define AMBA_UART_DR(base)      (*(volatile unsigned char *)((base) + 0x00))
+#define AMBA_UART_LCRH(base)    (*(volatile unsigned char *)((base) + 0x2c))
+#define AMBA_UART_CR(base)      (*(volatile unsigned char *)((base) + 0x30))
+#define AMBA_UART_FR(base)      (*(volatile unsigned char *)((base) + 0x18))
+
+/*
+ * Return the UART base address
+ */
+static inline unsigned long get_uart_base(void)
+{
+        if (machine_is_realview_eb())
+                return REALVIEW_EB_UART0_BASE;
+        else if (machine_is_realview_pb11mp())
+                return REALVIEW_PB11MP_UART0_BASE;
+        else if (machine_is_realview_pb1176())
+                return REALVIEW_PB1176_UART0_BASE;
+        else
+                return 0;
+}
 
 /*
  * This does not append a newline
  */
 static inline void putc(int c)
 {
-        while (AMBA_UART_FR & (1 << 5))
+        unsigned long base = get_uart_base();
+
+        while (AMBA_UART_FR(base) & (1 << 5))
                 barrier();
 
-        AMBA_UART_DR = c;
+        AMBA_UART_DR(base) = c;
 }
 
 static inline void flush(void)
 {
-        while (AMBA_UART_FR & (1 << 3))
+        unsigned long base = get_uart_base();
+
+        while (AMBA_UART_FR(base) & (1 << 3))
                 barrier();
 }
 
diff --git a/include/asm-arm/arch-sa1100/gpio.h b/include/asm-arm/arch-sa1100/gpio.h
index e7a9d26e22a8..93d3395b102d 100644
--- a/include/asm-arm/arch-sa1100/gpio.h
+++ b/include/asm-arm/arch-sa1100/gpio.h
@@ -26,35 +26,28 @@
 
 #include <asm/hardware.h>
 #include <asm/irq.h>
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-        return;
-}
-
-extern int gpio_direction_input(unsigned gpio);
-extern int gpio_direction_output(unsigned gpio, int value);
-
+#include <asm-generic/gpio.h>
 
 static inline int gpio_get_value(unsigned gpio)
 {
-        return GPLR & GPIO_GPIO(gpio);
+        if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
+                return GPLR & GPIO_GPIO(gpio);
+        else
+                return __gpio_get_value(gpio);
 }
 
 static inline void gpio_set_value(unsigned gpio, int value)
 {
-        if (value)
-                GPSR = GPIO_GPIO(gpio);
+        if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
+                if (value)
+                        GPSR = GPIO_GPIO(gpio);
+                else
+                        GPCR = GPIO_GPIO(gpio);
         else
-                GPCR = GPIO_GPIO(gpio);
+                __gpio_set_value(gpio, value);
 }
 
-#include <asm-generic/gpio.h>                   /* cansleep wrappers */
+#define gpio_cansleep   __gpio_cansleep
 
 static inline unsigned gpio_to_irq(unsigned gpio)
 {
diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h
index 715e18a4add1..3479de9266e5 100644
--- a/include/asm-arm/cpu-multi32.h
+++ b/include/asm-arm/cpu-multi32.h
@@ -21,6 +21,10 @@ extern struct processor {
          */
         void (*_data_abort)(unsigned long pc);
         /*
+         * Retrieve prefetch fault address
+         */
+        unsigned long (*_prefetch_abort)(unsigned long lr);
+        /*
          * Set up any processor specifics
          */
         void (*_proc_init)(void);
diff --git a/include/asm-arm/glue.h b/include/asm-arm/glue.h
index 22274ce81375..a97a182ba287 100644
--- a/include/asm-arm/glue.h
+++ b/include/asm-arm/glue.h
@@ -40,83 +40,110 @@
  *        v6_early      - ARMv6 generic early abort handler
  *        v7_early      - ARMv7 generic early abort handler
  */
-#undef CPU_ABORT_HANDLER
-#undef MULTI_ABORT
+#undef CPU_DABORT_HANDLER
+#undef MULTI_DABORT
 
 #if defined(CONFIG_CPU_ARM610)
-# ifdef CPU_ABORT_HANDLER
-#  define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER cpu_arm6_data_abort
+#  define CPU_DABORT_HANDLER cpu_arm6_data_abort
 # endif
 #endif
 
 #if defined(CONFIG_CPU_ARM710)
-# ifdef CPU_ABORT_HANDLER
-#  define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER cpu_arm7_data_abort
+#  define CPU_DABORT_HANDLER cpu_arm7_data_abort
 # endif
 #endif
 
 #ifdef CONFIG_CPU_ABRT_LV4T
-# ifdef CPU_ABORT_HANDLER
-#  define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v4t_late_abort
+#  define CPU_DABORT_HANDLER v4t_late_abort
 # endif
 #endif
 
 #ifdef CONFIG_CPU_ABRT_EV4
-# ifdef CPU_ABORT_HANDLER
-#  define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v4_early_abort
+#  define CPU_DABORT_HANDLER v4_early_abort
 # endif
 #endif
 
 #ifdef CONFIG_CPU_ABRT_EV4T
-# ifdef CPU_ABORT_HANDLER
-#  define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v4t_early_abort
+#  define CPU_DABORT_HANDLER v4t_early_abort
 # endif
 #endif
 
 #ifdef CONFIG_CPU_ABRT_EV5TJ
-# ifdef CPU_ABORT_HANDLER
-#  define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v5tj_early_abort
+#  define CPU_DABORT_HANDLER v5tj_early_abort
 # endif
 #endif
 
 #ifdef CONFIG_CPU_ABRT_EV5T
-# ifdef CPU_ABORT_HANDLER
-#  define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v5t_early_abort
+#  define CPU_DABORT_HANDLER v5t_early_abort
 # endif
 #endif
 
 #ifdef CONFIG_CPU_ABRT_EV6
-# ifdef CPU_ABORT_HANDLER
-#  define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v6_early_abort
+#  define CPU_DABORT_HANDLER v6_early_abort
 # endif
 #endif
 
 #ifdef CONFIG_CPU_ABRT_EV7
-# ifdef CPU_ABORT_HANDLER
-#  define MULTI_ABORT 1
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
 # else
-#  define CPU_ABORT_HANDLER v7_early_abort
+#  define CPU_DABORT_HANDLER v7_early_abort
 # endif
 #endif
 
-#ifndef CPU_ABORT_HANDLER
+#ifndef CPU_DABORT_HANDLER
 #error Unknown data abort handler type
 #endif
 
+/*
+ * Prefetch abort handler.  If the CPU has an IFAR use that, otherwise
+ * use the address of the aborted instruction
+ */
+#undef CPU_PABORT_HANDLER
+#undef MULTI_PABORT
+
+#ifdef CONFIG_CPU_PABRT_IFAR
+# ifdef CPU_PABORT_HANDLER
+#  define MULTI_PABORT 1
+# else
+#  define CPU_PABORT_HANDLER(reg, insn) mrc p15, 0, reg, cr6, cr0, 2
+# endif
+#endif
+
+#ifdef CONFIG_CPU_PABRT_NOIFAR
+# ifdef CPU_PABORT_HANDLER
+#  define MULTI_PABORT 1
+# else
+#  define CPU_PABORT_HANDLER(reg, insn) mov reg, insn
+# endif
+#endif
+
+#ifndef CPU_PABORT_HANDLER
+#error Unknown prefetch abort handler type
+#endif
+
 #endif
diff --git a/include/asm-arm/hardware/arm_scu.h b/include/asm-arm/hardware/arm_scu.h
deleted file mode 100644
index 7d28eb5a1758..000000000000
--- a/include/asm-arm/hardware/arm_scu.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef ASMARM_HARDWARE_ARM_SCU_H
-#define ASMARM_HARDWARE_ARM_SCU_H
-
-#include <asm/arch/scu.h>
-
-/*
- * SCU registers
- */
-#define SCU_CTRL                0x00
-#define SCU_CONFIG              0x04
-#define SCU_CPU_STATUS          0x08
-#define SCU_INVALIDATE          0x0c
-#define SCU_FPGA_REVISION       0x10
-
-#endif
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
index ede377ec9147..18f6937f5010 100644
--- a/include/asm-arm/hardware/iop3xx.h
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -29,6 +29,7 @@ extern void gpio_line_config(int line, int direction);
 extern int  gpio_line_get(int line);
 extern void gpio_line_set(int line, int value);
 extern int init_atu;
+extern int iop3xx_get_init_atu(void);
 #endif
 
 
@@ -112,14 +113,6 @@ extern int init_atu;
 #define IOP3XX_INIT_ATU_DISABLE -1
 #define IOP3XX_INIT_ATU_ENABLE   1
 
-#ifdef CONFIG_IOP3XX_ATU
-#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
-                                IOP3XX_INIT_ATU_ENABLE : init_atu)
-#else
-#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
-                                IOP3XX_INIT_ATU_DISABLE : init_atu)
-#endif
-
 /* Messaging Unit  */
 #define IOP3XX_IMR0             (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
 #define IOP3XX_IMR1             (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
diff --git a/include/asm-arm/hardware/scoop.h b/include/asm-arm/hardware/scoop.h
index d37bf7443264..dfb8330599f9 100644
--- a/include/asm-arm/hardware/scoop.h
+++ b/include/asm-arm/hardware/scoop.h
@@ -40,6 +40,7 @@ struct scoop_config {
         unsigned short io_dir;
         unsigned short suspend_clr;
         unsigned short suspend_set;
+        int gpio_base;
 };
 
 /* Structure for linking scoop devices to PCMCIA sockets */
@@ -62,7 +63,7 @@ struct scoop_pcmcia_config {
 extern struct scoop_pcmcia_config *platform_scoop_config;
 
 void reset_scoop(struct device *dev);
-unsigned short set_scoop_gpio(struct device *dev, unsigned short bit);
-unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit);
+unsigned short __deprecated set_scoop_gpio(struct device *dev, unsigned short bit);
+unsigned short __deprecated reset_scoop_gpio(struct device *dev, unsigned short bit);
 unsigned short read_scoop_reg(struct device *dev, unsigned short reg);
 void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data);
diff --git a/include/asm-arm/hwcap.h b/include/asm-arm/hwcap.h
index 01a1391d3014..81f4c899a555 100644
--- a/include/asm-arm/hwcap.h
+++ b/include/asm-arm/hwcap.h
@@ -15,6 +15,7 @@
 #define HWCAP_JAVA      256
 #define HWCAP_IWMMXT    512
 #define HWCAP_CRUNCH    1024
+#define HWCAP_THUMBEE   2048
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 /*
diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h
index 24621c49a0c7..9d4f6b5ea419 100644
--- a/include/asm-arm/mach/pci.h
+++ b/include/asm-arm/mach/pci.h
@@ -55,6 +55,7 @@ void pci_common_init(struct hw_pci *);
 extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
 extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
 extern void iop3xx_pci_preinit(void);
+extern void iop3xx_pci_preinit_cond(void);
 
 extern int dc21285_setup(int nr, struct pci_sys_data *);
 extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index d9bfb39adabf..9ba4d7136e6b 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -217,7 +217,10 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 #ifndef CONFIG_DISCONTIGMEM
 
 #define ARCH_PFN_OFFSET         PHYS_PFN_OFFSET
+
+#ifndef CONFIG_SPARSEMEM
 #define pfn_valid(pfn)          ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
+#endif
 
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define virt_addr_valid(kaddr)  ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
diff --git a/include/asm-arm/plat-orion/ehci-orion.h b/include/asm-arm/plat-orion/ehci-orion.h
new file mode 100644
index 000000000000..785705651e24
--- /dev/null
+++ b/include/asm-arm/plat-orion/ehci-orion.h
@@ -0,0 +1,19 @@
+/*
+ * include/asm-arm/plat-orion/ehci-orion.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_PLAT_ORION_EHCI_ORION_H
+#define __ASM_PLAT_ORION_EHCI_ORION_H
+
+#include <linux/mbus.h>
+
+struct orion_ehci_data {
+        struct mbus_dram_target_info    *dram;
+};
+
+
+#endif
diff --git a/include/asm-arm/plat-orion/irq.h b/include/asm-arm/plat-orion/irq.h
new file mode 100644
index 000000000000..94aeed919d5b
--- /dev/null
+++ b/include/asm-arm/plat-orion/irq.h
@@ -0,0 +1,17 @@
+/*
+ * include/asm-arm/plat-orion/irq.h
+ *
+ * Marvell Orion SoC IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_PLAT_ORION_IRQ_H
+#define __ASM_PLAT_ORION_IRQ_H
+
+void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr);
+
+
+#endif
diff --git a/include/asm-arm/arch-orion/platform.h b/include/asm-arm/plat-orion/orion_nand.h
index 143c38e2fa0b..ffd3852a0dd7 100644
--- a/include/asm-arm/arch-orion/platform.h
+++ b/include/asm-arm/plat-orion/orion_nand.h
@@ -1,15 +1,13 @@
 /*
- * asm-arm/arch-orion/platform.h
- *
- * Tzachi Perelstein <tzachi@marvell.com>
+ * include/asm-arm/plat-orion/orion_nand.h
  *
  * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_ARCH_PLATFORM_H__
-#define __ASM_ARCH_PLATFORM_H__
+#ifndef __ASM_PLAT_ORION_ORION_NAND_H
+#define __ASM_PLAT_ORION_ORION_NAND_H
 
 /*
  * Device bus NAND private data
@@ -22,4 +20,5 @@ struct orion_nand_data {
         u8 width;       /* buswidth */
 };
 
+
 #endif
diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h
new file mode 100644
index 000000000000..6434ac685d21
--- /dev/null
+++ b/include/asm-arm/plat-orion/pcie.h
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/plat-orion/pcie.h
+ *
+ * Marvell Orion SoC PCIe handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_PLAT_ORION_PCIE_H
+#define __ASM_PLAT_ORION_PCIE_H
+
+u32 orion_pcie_dev_id(void __iomem *base);
+u32 orion_pcie_rev(void __iomem *base);
+int orion_pcie_link_up(void __iomem *base);
+int orion_pcie_get_local_bus_nr(void __iomem *base);
+void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
+void orion_pcie_setup(void __iomem *base,
+                      struct mbus_dram_target_info *dram);
+int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
+                       u32 devfn, int where, int size, u32 *val);
+int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
+                           u32 devfn, int where, int size, u32 *val);
+int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
+                          u32 devfn, int where, int size, u32 *val);
+int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
+                       u32 devfn, int where, int size, u32 val);
+
+
+#endif
diff --git a/include/asm-arm/plat-orion/time.h b/include/asm-arm/plat-orion/time.h
new file mode 100644
index 000000000000..0e85cc8f44d9
--- /dev/null
+++ b/include/asm-arm/plat-orion/time.h
@@ -0,0 +1,17 @@
+/*
+ * include/asm-arm/plat-orion/time.h
+ *
+ * Marvell Orion SoC time handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_PLAT_ORION_TIME_H
+#define __ASM_PLAT_ORION_TIME_H
+
+void orion_time_init(unsigned int irq, unsigned int tclk);
+
+
+#endif
diff --git a/include/asm-arm/sparsemem.h b/include/asm-arm/sparsemem.h
new file mode 100644
index 000000000000..277158191a0d
--- /dev/null
+++ b/include/asm-arm/sparsemem.h
@@ -0,0 +1,10 @@
+#ifndef ASMARM_SPARSEMEM_H
+#define ASMARM_SPARSEMEM_H
+
+#include <asm/memory.h>
+
+#define MAX_PHYSADDR_BITS       32
+#define MAX_PHYSMEM_BITS        32
+#define SECTION_SIZE_BITS       NODE_MEM_SIZE_BITS
+
+#endif
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index 41784357a204..f5a664786311 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -62,6 +62,9 @@ struct thread_info {
         struct crunch_state     crunchstate;
         union fp_state          fpstate __attribute__((aligned(8)));
         union vfp_state         vfpstate;
+#ifdef CONFIG_ARM_THUMBEE
+        unsigned long           thumbee_state;  /* ThumbEE Handler Base register */
+#endif
         struct restart_block    restart_block;
 };
 
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index 88e868b7aae0..7c570082b1e0 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -376,9 +376,11 @@
 #define __NR_kexec_load                 (__NR_SYSCALL_BASE+347)
 #define __NR_utimensat                  (__NR_SYSCALL_BASE+348)
 #define __NR_signalfd                   (__NR_SYSCALL_BASE+349)
-#define __NR_timerfd                    (__NR_SYSCALL_BASE+350)
+#define __NR_timerfd_create             (__NR_SYSCALL_BASE+350)
 #define __NR_eventfd                    (__NR_SYSCALL_BASE+351)
 #define __NR_fallocate                  (__NR_SYSCALL_BASE+352)
+#define __NR_timerfd_settime            (__NR_SYSCALL_BASE+353)
+#define __NR_timerfd_gettime            (__NR_SYSCALL_BASE+354)
 
 /*
  * The following SWIs are ARM private.
diff --git a/include/linux/ata_platform.h b/include/linux/ata_platform.h
index b856a2a590d9..9a26c83a2c9e 100644
--- a/include/linux/ata_platform.h
+++ b/include/linux/ata_platform.h
@@ -27,7 +27,10 @@ extern int __devexit __pata_platform_remove(struct device *dev);
 /*
  * Marvell SATA private data
  */
+struct mbus_dram_target_info;
+
 struct mv_sata_platform_data {
+        struct mbus_dram_target_info    *dram;
         int     n_ports; /* number of sata ports */
 };
 
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
new file mode 100644
index 000000000000..c11ff2932549
--- /dev/null
+++ b/include/linux/mbus.h
@@ -0,0 +1,36 @@
+/*
+ * Marvell MBUS common definitions.
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __LINUX_MBUS_H
+#define __LINUX_MBUS_H
+
+struct mbus_dram_target_info
+{
+        /*
+         * The 4-bit MBUS target ID of the DRAM controller.
+         */
+        u8              mbus_dram_target_id;
+
+        /*
+         * The base address, size, and MBUS attribute ID for each
+         * of the possible DRAM chip selects.  Peripherals are
+         * required to support at least 4 decode windows.
+         */
+        int             num_cs;
+        struct mbus_dram_window {
+                u8      cs_index;
+                u8      mbus_attr;
+                u32     base;
+                u32     size;
+        } cs[4];
+};
+
+
+#endif
diff --git a/include/linux/mfd/htc-egpio.h b/include/linux/mfd/htc-egpio.h
new file mode 100644
index 000000000000..b4201c971367
--- /dev/null
+++ b/include/linux/mfd/htc-egpio.h
@@ -0,0 +1,57 @@
+/*
+ * HTC simple EGPIO irq and gpio extender
+ */
+
+#ifndef __HTC_EGPIO_H__
+#define __HTC_EGPIO_H__
+
+#include <linux/gpio.h>
+
+/* Descriptive values for all-in or all-out htc_egpio_chip descriptors. */
+#define HTC_EGPIO_OUTPUT (~0)
+#define HTC_EGPIO_INPUT  0
+
+/**
+ * struct htc_egpio_chip - descriptor to create gpio_chip for register range
+ * @reg_start: index of first register
+ * @gpio_base: gpio number of first pin in this register range
+ * @num_gpios: number of gpios in this register range, max BITS_PER_LONG
+ *    (number of registers = DIV_ROUND_UP(num_gpios, reg_width))
+ * @direction: bitfield, '0' = input, '1' = output,
+ */
+struct htc_egpio_chip {
+        int           reg_start;
+        int           gpio_base;
+        int           num_gpios;
+        unsigned long direction;
+        unsigned long initial_values;
+};
+
+/**
+ * struct htc_egpio_platform_data - description provided by the arch
+ * @irq_base: beginning of available IRQs (eg, IRQ_BOARD_START)
+ * @num_irqs: number of irqs
+ * @reg_width: number of bits per register, either 8 or 16 bit
+ * @bus_width: alignment of the registers, either 16 or 32 bit
+ * @invert_acks: set if chip requires writing '0' to ack an irq, instead of '1'
+ * @ack_register: location of the irq/ack register
+ * @chip: pointer to array of htc_egpio_chip descriptors
+ * @num_chips: number of egpio chip descriptors
+ */
+struct htc_egpio_platform_data {
+        int                   bus_width;
+        int                   reg_width;
+
+        int                   irq_base;
+        int                   num_irqs;
+        int                   invert_acks;
+        int                   ack_register;
+
+        struct htc_egpio_chip *chip;
+        int                   num_chips;
+};
+
+/* Determine the wakeup irq, to be called during early resume */
+extern int htc_egpio_get_wakeup_irq(struct device *dev);
+
+#endif
diff --git a/include/linux/mfd/htc-pasic3.h b/include/linux/mfd/htc-pasic3.h
new file mode 100644
index 000000000000..b4294f12c4f8
--- /dev/null
+++ b/include/linux/mfd/htc-pasic3.h
@@ -0,0 +1,55 @@
+/*
+ * HTC PASIC3 driver - LEDs and DS1WM
+ *
+ * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive for
+ * more details.
+ *
+ */
+
+#ifndef __PASIC3_H
+#define __PASIC3_H
+
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+
+extern void pasic3_write_register(struct device *dev, u32 reg, u8 val);
+extern u8 pasic3_read_register(struct device *dev, u32 reg);
+
+/*
+ * mask for registers 0x20,0x21,0x22
+ */
+#define PASIC3_MASK_LED0 0x04
+#define PASIC3_MASK_LED1 0x08
+#define PASIC3_MASK_LED2 0x40
+
+/*
+ * bits in register 0x06
+ */
+#define PASIC3_BIT2_LED0 0x08
+#define PASIC3_BIT2_LED1 0x10
+#define PASIC3_BIT2_LED2 0x20
+
+struct pasic3_led {
+        struct led_classdev         led;
+        unsigned int                hw_num;
+        unsigned int                bit2;
+        unsigned int                mask;
+        struct pasic3_leds_machinfo *pdata;
+};
+
+struct pasic3_leds_machinfo {
+        unsigned int      num_leds;
+        unsigned int      power_gpio;
+        struct pasic3_led *leds;
+};
+
+struct pasic3_platform_data {
+        struct pasic3_leds_machinfo *led_pdata;
+        unsigned int                 bus_shift;
+        unsigned int                 clock_rate;
+};
+
+#endif
diff --git a/include/linux/sched.h b/include/linux/sched.h
index fed07d03364e..6a1e7afb099b 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -1541,6 +1541,12 @@ static inline void idle_task_exit(void) {}
 
 extern void sched_idle_next(void);
 
+#if defined(CONFIG_NO_HZ) && defined(CONFIG_SMP)
+extern void wake_up_idle_cpu(int cpu);
+#else
+static inline void wake_up_idle_cpu(int cpu) { }
+#endif
+
 #ifdef CONFIG_SCHED_DEBUG
 extern unsigned int sysctl_sched_latency;
 extern unsigned int sysctl_sched_min_granularity;
diff --git a/kernel/relay.c b/kernel/relay.c
index 4c035a8a248c..d6204a485818 100644
--- a/kernel/relay.c
+++ b/kernel/relay.c
@@ -736,7 +736,7 @@ static int relay_file_open(struct inode *inode, struct file *filp)
         kref_get(&buf->kref);
         filp->private_data = buf;
 
-        return 0;
+        return nonseekable_open(inode, filp);
 }
 
 /**
@@ -1056,6 +1056,10 @@ static struct pipe_buf_operations relay_pipe_buf_ops = {
         .get = generic_pipe_buf_get,
 };
 
+static void relay_page_release(struct splice_pipe_desc *spd, unsigned int i)
+{
+}
+
 /*
  *      subbuf_splice_actor - splice up to one subbuf's worth of data
  */
@@ -1083,6 +1087,7 @@ static int subbuf_splice_actor(struct file *in,
                 .partial = partial,
                 .flags = flags,
                 .ops = &relay_pipe_buf_ops,
+                .spd_release = relay_page_release,
         };
 
         if (rbuf->subbufs_produced == rbuf->subbufs_consumed)
diff --git a/kernel/sched.c b/kernel/sched.c
index 28c73f07efb2..8dcdec6fe0fe 100644
--- a/kernel/sched.c
+++ b/kernel/sched.c
@@ -1052,6 +1052,49 @@ static void resched_cpu(int cpu)
         resched_task(cpu_curr(cpu));
         spin_unlock_irqrestore(&rq->lock, flags);
 }
+
+#ifdef CONFIG_NO_HZ
+/*
+ * When add_timer_on() enqueues a timer into the timer wheel of an
+ * idle CPU then this timer might expire before the next timer event
+ * which is scheduled to wake up that CPU. In case of a completely
+ * idle system the next event might even be infinite time into the
+ * future. wake_up_idle_cpu() ensures that the CPU is woken up and
+ * leaves the inner idle loop so the newly added timer is taken into
+ * account when the CPU goes back to idle and evaluates the timer
+ * wheel for the next timer event.
+ */
+void wake_up_idle_cpu(int cpu)
+{
+        struct rq *rq = cpu_rq(cpu);
+
+        if (cpu == smp_processor_id())
+                return;
+
+        /*
+         * This is safe, as this function is called with the timer
+         * wheel base lock of (cpu) held. When the CPU is on the way
+         * to idle and has not yet set rq->curr to idle then it will
+         * be serialized on the timer wheel base lock and take the new
+         * timer into account automatically.
+         */
+        if (rq->curr != rq->idle)
+                return;
+
+        /*
+         * We can set TIF_RESCHED on the idle task of the other CPU
+         * lockless. The worst case is that the other CPU runs the
+         * idle task through an additional NOOP schedule()
+         */
+        set_tsk_thread_flag(rq->idle, TIF_NEED_RESCHED);
+
+        /* NEED_RESCHED must be visible before we test polling */
+        smp_mb();
+        if (!tsk_is_polling(rq->idle))
+                smp_send_reschedule(cpu);
+}
+#endif
+
 #else
 static void __resched_task(struct task_struct *p, int tif_bit)
 {
diff --git a/kernel/time/clocksource.c b/kernel/time/clocksource.c
index 278534bbca95..7f60097d443a 100644
--- a/kernel/time/clocksource.c
+++ b/kernel/time/clocksource.c
@@ -174,7 +174,7 @@ static void clocksource_check_watchdog(struct clocksource *cs)
                         if (watchdog)
                                 del_timer(&watchdog_timer);
                         watchdog = cs;
-                        init_timer_deferrable(&watchdog_timer);
+                        init_timer(&watchdog_timer);
                         watchdog_timer.function = clocksource_watchdog;
 
                         /* Reset watchdog cycles */
diff --git a/kernel/timer.c b/kernel/timer.c
index 99b00a25f88b..b024106daa70 100644
--- a/kernel/timer.c
+++ b/kernel/timer.c
@@ -451,10 +451,18 @@ void add_timer_on(struct timer_list *timer, int cpu)
         spin_lock_irqsave(&base->lock, flags);
         timer_set_base(timer, base);
         internal_add_timer(base, timer);
+        /*
+         * Check whether the other CPU is idle and needs to be
+         * triggered to reevaluate the timer wheel when nohz is
+         * active. We are protected against the other CPU fiddling
+         * with the timer by holding the timer base lock. This also
+         * makes sure that a CPU on the way to idle can not evaluate
+         * the timer wheel.
+         */
+        wake_up_idle_cpu(cpu);
         spin_unlock_irqrestore(&base->lock, flags);
 }
 
-
 /**
  * mod_timer - modify a timer's timeout
  * @timer: the timer to be modified
diff --git a/mm/slab.c b/mm/slab.c
index bb4070e1079f..04b308c3bc54 100644
--- a/mm/slab.c
+++ b/mm/slab.c
@@ -1481,7 +1481,7 @@ void __init kmem_cache_init(void)
         list_add(&cache_cache.next, &cache_chain);
         cache_cache.colour_off = cache_line_size();
         cache_cache.array[smp_processor_id()] = &initarray_cache.cache;
-        cache_cache.nodelists[node] = &initkmem_list3[CACHE_CACHE];
+        cache_cache.nodelists[node] = &initkmem_list3[CACHE_CACHE + node];
 
         /*
          * struct kmem_cache size depends on nr_node_ids, which
@@ -1602,7 +1602,7 @@ void __init kmem_cache_init(void)
                 int nid;
 
                 for_each_online_node(nid) {
-                        init_list(&cache_cache, &initkmem_list3[CACHE_CACHE], nid);
+                        init_list(&cache_cache, &initkmem_list3[CACHE_CACHE + nid], nid);
 
                         init_list(malloc_sizes[INDEX_AC].cs_cachep,
                                   &initkmem_list3[SIZE_AC + nid], nid);
diff --git a/mm/slub.c b/mm/slub.c
index ca71d5b81e4a..b72bc98e2dc1 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -2685,6 +2685,7 @@ void kfree(const void *x)
 }
 EXPORT_SYMBOL(kfree);
 
+#if defined(SLUB_DEBUG) || defined(CONFIG_SLABINFO)
 static unsigned long count_partial(struct kmem_cache_node *n)
 {
         unsigned long flags;
@@ -2697,6 +2698,7 @@ static unsigned long count_partial(struct kmem_cache_node *n)
         spin_unlock_irqrestore(&n->list_lock, flags);
         return x;
 }
+#endif
 
 /*
  * kmem_cache_shrink removes empty slabs from the partial lists and sorts
diff --git a/net/sunrpc/xprtrdma/svc_rdma_recvfrom.c b/net/sunrpc/xprtrdma/svc_rdma_recvfrom.c
index 971271602dd0..c22d6b6f2db4 100644
--- a/net/sunrpc/xprtrdma/svc_rdma_recvfrom.c
+++ b/net/sunrpc/xprtrdma/svc_rdma_recvfrom.c
@@ -322,15 +322,6 @@ next_sge:
                 ctxt->direction = DMA_FROM_DEVICE;
                 clear_bit(RDMACTXT_F_READ_DONE, &ctxt->flags);
                 clear_bit(RDMACTXT_F_LAST_CTXT, &ctxt->flags);
-                if ((ch+1)->rc_discrim == 0) {
-                        /*
-                         * Checked in sq_cq_reap to see if we need to
-                         * be enqueued
-                         */
-                        set_bit(RDMACTXT_F_LAST_CTXT, &ctxt->flags);
-                        ctxt->next = hdr_ctxt;
-                        hdr_ctxt->next = head;
-                }
 
                 /* Prepare READ WR */
                 memset(&read_wr, 0, sizeof read_wr);
@@ -348,7 +339,17 @@ next_sge:
                 rdma_set_ctxt_sge(ctxt, &sge[ch_sge_ary[ch_no].start],
                                   &sgl_offset,
                                   read_wr.num_sge);
-
+                if (((ch+1)->rc_discrim == 0) &&
+                    (read_wr.num_sge == ch_sge_ary[ch_no].count)) {
+                        /*
+                         * Mark the last RDMA_READ with a bit to
+                         * indicate all RPC data has been fetched from
+                         * the client and the RPC needs to be enqueued.
+                         */
+                        set_bit(RDMACTXT_F_LAST_CTXT, &ctxt->flags);
+                        ctxt->next = hdr_ctxt;
+                        hdr_ctxt->next = head;
+                }
                 /* Post the read */
                 err = svc_rdma_send(xprt, &read_wr);
                 if (err) {
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c
index 5d86e6809752..8704e2825b10 100644
--- a/sound/arm/pxa2xx-ac97.c
+++ b/sound/arm/pxa2xx-ac97.c
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/wait.h>
+#include <linux/clk.h>
 #include <linux/delay.h>
 
 #include <sound/core.h>
@@ -27,6 +28,7 @@
 #include <linux/mutex.h>
 #include <asm/hardware.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/audio.h>
 
 #include "pxa2xx-pcm.h"
@@ -35,6 +37,10 @@
 static DEFINE_MUTEX(car_mutex);
 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
 static volatile long gsr_bits;
+static struct clk *ac97_clk;
+#ifdef CONFIG_PXA27x
+static struct clk *ac97conf_clk;
+#endif
 
 /*
  * Beware PXA27x bugs:
@@ -112,9 +118,9 @@ static void pxa2xx_ac97_reset(struct snd_ac97 *ac97)
         gsr_bits = 0;
 #ifdef CONFIG_PXA27x
         /* PXA27x Developers Manual section 13.5.2.2.1 */
-        pxa_set_cken(CKEN_AC97CONF, 1);
+        clk_enable(ac97conf_clk);
         udelay(5);
-        pxa_set_cken(CKEN_AC97CONF, 0);
+        clk_disable(ac97conf_clk);
         GCR = GCR_COLD_RST;
         udelay(50);
 #else
@@ -259,7 +265,7 @@ static int pxa2xx_ac97_do_suspend(struct snd_card *card, pm_message_t state)
         if (platform_ops && platform_ops->suspend)
                 platform_ops->suspend(platform_ops->priv);
         GCR |= GCR_ACLINK_OFF;
-        pxa_set_cken(CKEN_AC97, 0);
+        clk_disable(ac97_clk);
 
         return 0;
 }
@@ -268,7 +274,7 @@ static int pxa2xx_ac97_do_resume(struct snd_card *card)
 {
         pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
 
-        pxa_set_cken(CKEN_AC97, 1);
+        clk_enable(ac97_clk);
         if (platform_ops && platform_ops->resume)
                 platform_ops->resume(platform_ops->priv);
         snd_ac97_resume(pxa2xx_ac97_ac97);
@@ -335,8 +341,21 @@ static int __devinit pxa2xx_ac97_probe(struct platform_device *dev)
 #ifdef CONFIG_PXA27x
         /* Use GPIO 113 as AC97 Reset on Bulverde */
         pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
+        ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
+        if (IS_ERR(ac97conf_clk)) {
+                ret = PTR_ERR(ac97conf_clk);
+                ac97conf_clk = NULL;
+                goto err;
+        }
 #endif
-        pxa_set_cken(CKEN_AC97, 1);
+
+        ac97_clk = clk_get(&dev->dev, "AC97CLK");
+        if (IS_ERR(ac97_clk)) {
+                ret = PTR_ERR(ac97_clk);
+                ac97_clk = NULL;
+                goto err;
+        }
+        clk_enable(ac97_clk);
 
         ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus);
         if (ret)
@@ -361,11 +380,19 @@ static int __devinit pxa2xx_ac97_probe(struct platform_device *dev)
  err:
         if (card)
                 snd_card_free(card);
-        if (CKEN & (1 << CKEN_AC97)) {
+        if (ac97_clk) {
                 GCR |= GCR_ACLINK_OFF;
                 free_irq(IRQ_AC97, NULL);
-                pxa_set_cken(CKEN_AC97, 0);
+                clk_disable(ac97_clk);
+                clk_put(ac97_clk);
+                ac97_clk = NULL;
+        }
+#ifdef CONFIG_PXA27x
+        if (ac97conf_clk) {
+                clk_put(ac97conf_clk);
+                ac97conf_clk = NULL;
         }
+#endif
         return ret;
 }
 
@@ -378,7 +405,13 @@ static int __devexit pxa2xx_ac97_remove(struct platform_device *dev)
                 platform_set_drvdata(dev, NULL);
                 GCR |= GCR_ACLINK_OFF;
                 free_irq(IRQ_AC97, NULL);
-                pxa_set_cken(CKEN_AC97, 0);
+                clk_disable(ac97_clk);
+                clk_put(ac97_clk);
+                ac97_clk = NULL;
+#ifdef CONFIG_PXA27x
+                clk_put(ac97conf_clk);
+                ac97conf_clk = NULL;
+#endif
         }
 
         return 0;
diff --git a/sound/soc/at91/eti_b1_wm8731.c b/sound/soc/at91/eti_b1_wm8731.c
index ad3ad9d662f8..1347dcf3f80b 100644
--- a/sound/soc/at91/eti_b1_wm8731.c
+++ b/sound/soc/at91/eti_b1_wm8731.c
@@ -33,8 +33,7 @@
 #include <sound/soc.h>
 #include <sound/soc-dapm.h>
 
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pio.h>
+#include <asm/hardware.h>
 #include <asm/arch/gpio.h>
 
 #include "../codecs/wm8731.h"
@@ -47,13 +46,6 @@
 #define DBG(x...)
 #endif
 
-#define AT91_PIO_TF1    (1 << (AT91_PIN_PB6 - PIN_BASE) % 32)
-#define AT91_PIO_TK1    (1 << (AT91_PIN_PB7 - PIN_BASE) % 32)
-#define AT91_PIO_TD1    (1 << (AT91_PIN_PB8 - PIN_BASE) % 32)
-#define AT91_PIO_RD1    (1 << (AT91_PIN_PB9 - PIN_BASE) % 32)
-#define AT91_PIO_RK1    (1 << (AT91_PIN_PB10 - PIN_BASE) % 32)
-#define AT91_PIO_RF1    (1 << (AT91_PIN_PB11 - PIN_BASE) % 32)
-
 static struct clk *pck1_clk;
 static struct clk *pllb_clk;
 
@@ -276,7 +268,6 @@ static struct platform_device *eti_b1_snd_device;
 static int __init eti_b1_init(void)
 {
         int ret;
-        u32 ssc_pio_lines;
         struct at91_ssc_periph *ssc = eti_b1_dai.cpu_dai->private_data;
 
         if (!request_mem_region(AT91RM9200_BASE_SSC1, SZ_16K, "soc-audio")) {
@@ -310,19 +301,12 @@ static int __init eti_b1_init(void)
                 goto fail_io_unmap;
         }
 
-        ssc_pio_lines = AT91_PIO_TF1 | AT91_PIO_TK1 | AT91_PIO_TD1
-                        | AT91_PIO_RD1 /* | AT91_PIO_RK1 */ | AT91_PIO_RF1;
-
-        /* Reset all PIO registers and assign lines to peripheral A */
-        at91_sys_write(AT91_PIOB + PIO_PDR,  ssc_pio_lines);
-        at91_sys_write(AT91_PIOB + PIO_ODR,  ssc_pio_lines);
-        at91_sys_write(AT91_PIOB + PIO_IFDR, ssc_pio_lines);
-        at91_sys_write(AT91_PIOB + PIO_CODR, ssc_pio_lines);
-        at91_sys_write(AT91_PIOB + PIO_IDR,  ssc_pio_lines);
-        at91_sys_write(AT91_PIOB + PIO_MDDR, ssc_pio_lines);
-        at91_sys_write(AT91_PIOB + PIO_PUDR, ssc_pio_lines);
-        at91_sys_write(AT91_PIOB + PIO_ASR,  ssc_pio_lines);
-        at91_sys_write(AT91_PIOB + PIO_OWDR, ssc_pio_lines);
+        at91_set_A_periph(AT91_PIN_PB6, 0);     /* TF1 */
+        at91_set_A_periph(AT91_PIN_PB7, 0);     /* TK1 */
+        at91_set_A_periph(AT91_PIN_PB8, 0);     /* TD1 */
+        at91_set_A_periph(AT91_PIN_PB9, 0);     /* RD1 */
+/*      at91_set_A_periph(AT91_PIN_PB10, 0);*/  /* RK1 */
+        at91_set_A_periph(AT91_PIN_PB11, 0);    /* RF1 */
 
         /*
          * Set PCK1 parent to PLLB and its rate to 12 Mhz.
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
index 815c15336255..e17379998802 100644
--- a/sound/soc/pxa/pxa2xx-ac97.c
+++ b/sound/soc/pxa/pxa2xx-ac97.c
@@ -15,6 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/wait.h>
+#include <linux/clk.h>
 #include <linux/delay.h>
 
 #include <sound/core.h>
@@ -27,6 +28,7 @@
 #include <linux/mutex.h>
 #include <asm/hardware.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/audio.h>
 
 #include "pxa2xx-pcm.h"
@@ -35,6 +37,10 @@
 static DEFINE_MUTEX(car_mutex);
 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
 static volatile long gsr_bits;
+static struct clk *ac97_clk;
+#ifdef CONFIG_PXA27x
+static struct clk *ac97conf_clk;
+#endif
 
 /*
  * Beware PXA27x bugs:
@@ -159,9 +165,9 @@ static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97)
         gsr_bits = 0;
 #ifdef CONFIG_PXA27x
         /* PXA27x Developers Manual section 13.5.2.2.1 */
-        pxa_set_cken(CKEN_AC97CONF, 1);
+        clk_enable(ac97conf_clk);
         udelay(5);
-        pxa_set_cken(CKEN_AC97CONF, 0);
+        clk_disable(ac97conf_clk);
         GCR = GCR_COLD_RST;
         udelay(50);
 #else
@@ -255,7 +261,7 @@ static int pxa2xx_ac97_suspend(struct platform_device *pdev,
         struct snd_soc_cpu_dai *dai)
 {
         GCR |= GCR_ACLINK_OFF;
-        pxa_set_cken(CKEN_AC97, 0);
+        clk_disable(ac97_clk);
         return 0;
 }
 
@@ -270,7 +276,7 @@ static int pxa2xx_ac97_resume(struct platform_device *pdev,
         /* Use GPIO 113 as AC97 Reset on Bulverde */
         pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
 #endif
-        pxa_set_cken(CKEN_AC97, 1);
+        clk_enable(ac97_clk);
         return 0;
 }
 
@@ -294,16 +300,33 @@ static int pxa2xx_ac97_probe(struct platform_device *pdev)
 #ifdef CONFIG_PXA27x
         /* Use GPIO 113 as AC97 Reset on Bulverde */
         pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
+
+        ac97conf_clk = clk_get(&pdev->dev, "AC97CONFCLK");
+        if (IS_ERR(ac97conf_clk)) {
+                ret = PTR_ERR(ac97conf_clk);
+                ac97conf_clk = NULL;
+                goto err_irq;
+        }
 #endif
-        pxa_set_cken(CKEN_AC97, 1);
+        ac97_clk = clk_get(&pdev->dev, "AC97CLK");
+        if (IS_ERR(ac97_clk)) {
+                ret = PTR_ERR(ac97_clk);
+                ac97_clk = NULL;
+                goto err_irq;
+        }
+        clk_enable(ac97_clk);
         return 0;
 
- err:
-        if (CKEN & (1 << CKEN_AC97)) {
-                GCR |= GCR_ACLINK_OFF;
-                free_irq(IRQ_AC97, NULL);
-                pxa_set_cken(CKEN_AC97, 0);
+ err_irq:
+        GCR |= GCR_ACLINK_OFF;
+#ifdef CONFIG_PXA27x
+        if (ac97conf_clk) {
+                clk_put(ac97conf_clk);
+                ac97conf_clk = NULL;
         }
+#endif
+        free_irq(IRQ_AC97, NULL);
+ err:
         return ret;
 }
 
@@ -311,7 +334,13 @@ static void pxa2xx_ac97_remove(struct platform_device *pdev)
 {
         GCR |= GCR_ACLINK_OFF;
         free_irq(IRQ_AC97, NULL);
-        pxa_set_cken(CKEN_AC97, 0);
+#ifdef CONFIG_PXA27x
+        clk_put(ac97conf_clk);
+        ac97conf_clk = NULL;
+#endif
+        clk_disable(ac97_clk);
+        clk_put(ac97_clk);
+        ac97_clk = NULL;
 }
 
 static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream,
diff --git a/sound/soc/pxa/pxa2xx-i2s.c b/sound/soc/pxa/pxa2xx-i2s.c
index 692b90002489..425071030970 100644
--- a/sound/soc/pxa/pxa2xx-i2s.c
+++ b/sound/soc/pxa/pxa2xx-i2s.c
@@ -25,6 +25,7 @@
 
 #include <asm/hardware.h>
 #include <asm/arch/pxa-regs.h>
+#include <asm/arch/pxa2xx-gpio.h>
 #include <asm/arch/audio.h>
 
 #include "pxa2xx-pcm.h"