diff options
-rw-r--r-- | arch/mips/kernel/traps.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 200de027f354..3f58b6ac1358 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
@@ -927,12 +927,6 @@ asmlinkage void do_reserved(struct pt_regs *regs) | |||
927 | (regs->cp0_cause & 0x7f) >> 2); | 927 | (regs->cp0_cause & 0x7f) >> 2); |
928 | } | 928 | } |
929 | 929 | ||
930 | static asmlinkage void do_default_vi(void) | ||
931 | { | ||
932 | show_regs(get_irq_regs()); | ||
933 | panic("Caught unexpected vectored interrupt."); | ||
934 | } | ||
935 | |||
936 | /* | 930 | /* |
937 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | 931 | * Some MIPS CPUs can enable/disable for cache parity detection, but do |
938 | * it different ways. | 932 | * it different ways. |
@@ -1128,6 +1122,12 @@ void mips_srs_free(int set) | |||
1128 | clear_bit(set, &sr->sr_allocated); | 1122 | clear_bit(set, &sr->sr_allocated); |
1129 | } | 1123 | } |
1130 | 1124 | ||
1125 | static asmlinkage void do_default_vi(void) | ||
1126 | { | ||
1127 | show_regs(get_irq_regs()); | ||
1128 | panic("Caught unexpected vectored interrupt."); | ||
1129 | } | ||
1130 | |||
1131 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) | 1131 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
1132 | { | 1132 | { |
1133 | unsigned long handler; | 1133 | unsigned long handler; |