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-rw-r--r--arch/arm/Kconfig18
-rw-r--r--arch/arm/common/time-acorn.c2
-rw-r--r--arch/arm/kernel/Makefile1
-rw-r--r--arch/arm/kernel/atags.c86
-rw-r--r--arch/arm/kernel/atags.h5
-rw-r--r--arch/arm/kernel/machine_kexec.c2
-rw-r--r--arch/arm/kernel/relocate_kernel.S30
-rw-r--r--arch/arm/kernel/setup.c32
-rw-r--r--arch/arm/kernel/smp.c39
-rw-r--r--arch/arm/mach-at91/Kconfig30
-rw-r--r--arch/arm/mach-at91/at91sam926x_time.c3
-rw-r--r--arch/arm/mach-at91/generic.h3
-rw-r--r--arch/arm/mach-at91/gpio.c89
-rw-r--r--arch/arm/mach-pxa/Makefile2
-rw-r--r--arch/arm/mach-pxa/cm-x270.c1
-rw-r--r--arch/arm/mach-pxa/devices.c1
-rw-r--r--arch/arm/mach-pxa/generic.c57
-rw-r--r--arch/arm/mach-pxa/generic.h3
-rw-r--r--arch/arm/mach-pxa/irq.c62
-rw-r--r--arch/arm/mach-pxa/mfp.c11
-rw-r--r--arch/arm/mach-pxa/pcm027.c1
-rw-r--r--arch/arm/mach-pxa/poodle.c8
-rw-r--r--arch/arm/mach-pxa/pxa25x.c43
-rw-r--r--arch/arm/mach-pxa/pxa27x.c49
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c99
-rw-r--r--arch/arm/mach-pxa/sleep.S102
-rw-r--r--arch/arm/mach-pxa/smemc.c88
-rw-r--r--arch/arm/mach-pxa/spitz.c1
-rw-r--r--arch/arm/mach-pxa/tosa.c1
-rw-r--r--arch/arm/mach-realview/Kconfig21
-rw-r--r--arch/arm/mach-realview/Makefile3
-rw-r--r--arch/arm/mach-realview/core.c179
-rw-r--r--arch/arm/mach-realview/core.h71
-rw-r--r--arch/arm/mach-realview/localtimer.c144
-rw-r--r--arch/arm/mach-realview/platsmp.c20
-rw-r--r--arch/arm/mach-realview/realview_eb.c234
-rw-r--r--arch/arm/mach-sa1100/generic.c2
-rw-r--r--arch/arm/plat-iop/time.c4
-rw-r--r--arch/arm/plat-s3c24xx/time.c2
-rw-r--r--drivers/pcmcia/sa1100_jornada720.c2
-rw-r--r--drivers/serial/21285.c8
-rw-r--r--drivers/serial/atmel_serial.c3
-rw-r--r--include/asm-arm/arch-at91/at91_mci.h2
-rw-r--r--include/asm-arm/arch-at91/at91rm9200.h5
-rw-r--r--include/asm-arm/arch-at91/at91sam9260.h7
-rw-r--r--include/asm-arm/arch-at91/at91sam9261.h4
-rw-r--r--include/asm-arm/arch-at91/at91sam9263.h4
-rw-r--r--include/asm-arm/arch-at91/at91sam9rl.h5
-rw-r--r--include/asm-arm/arch-at91/uncompress.h32
-rw-r--r--include/asm-arm/arch-pxa/pxa3xx-regs.h13
-rw-r--r--include/asm-arm/arch-realview/board-eb.h171
-rw-r--r--include/asm-arm/arch-realview/entry-macro.S3
-rw-r--r--include/asm-arm/arch-realview/hardware.h1
-rw-r--r--include/asm-arm/arch-realview/irqs.h105
-rw-r--r--include/asm-arm/arch-realview/platform.h170
-rw-r--r--include/asm-arm/arch-realview/scu.h4
-rw-r--r--include/asm-arm/arch-realview/uncompress.h2
-rw-r--r--include/asm-arm/hardware/arm_twd.h7
-rw-r--r--include/asm-arm/kexec.h3
-rw-r--r--include/asm-arm/smp.h21
-rw-r--r--include/linux/atmel_serial.h (renamed from drivers/serial/atmel_serial.h)2
61 files changed, 1431 insertions, 692 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4b1a8e3d292c..9d8b7f9bca1d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -33,6 +33,11 @@ config GENERIC_CLOCKEVENTS
33 bool 33 bool
34 default n 34 default n
35 35
36config GENERIC_CLOCKEVENTS_BROADCAST
37 bool
38 depends on GENERIC_CLOCKEVENTS
39 default y if SMP && !LOCAL_TIMERS
40
36config MMU 41config MMU
37 bool 42 bool
38 default y 43 default y
@@ -168,6 +173,8 @@ config ARCH_REALVIEW
168 bool "ARM Ltd. RealView family" 173 bool "ARM Ltd. RealView family"
169 select ARM_AMBA 174 select ARM_AMBA
170 select ICST307 175 select ICST307
176 select GENERIC_TIME
177 select GENERIC_CLOCKEVENTS
171 help 178 help
172 This enables support for ARM Ltd RealView boards. 179 This enables support for ARM Ltd RealView boards.
173 180
@@ -604,7 +611,7 @@ source "kernel/time/Kconfig"
604 611
605config SMP 612config SMP
606 bool "Symmetric Multi-Processing (EXPERIMENTAL)" 613 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
607 depends on EXPERIMENTAL && REALVIEW_MPCORE 614 depends on EXPERIMENTAL && REALVIEW_EB_ARM11MP
608 help 615 help
609 This enables support for systems with more than one CPU. If you have 616 This enables support for systems with more than one CPU. If you have
610 a system with only one CPU, like most personal computers, say N. If 617 a system with only one CPU, like most personal computers, say N. If
@@ -638,7 +645,7 @@ config HOTPLUG_CPU
638 645
639config LOCAL_TIMERS 646config LOCAL_TIMERS
640 bool "Use local timer interrupts" 647 bool "Use local timer interrupts"
641 depends on SMP && REALVIEW_MPCORE 648 depends on SMP && REALVIEW_EB_ARM11MP
642 default y 649 default y
643 help 650 help
644 Enable support for local timers on SMP platforms, rather then the 651 Enable support for local timers on SMP platforms, rather then the
@@ -894,6 +901,13 @@ config KEXEC
894 initially work for you. It may help to enable device hotplugging 901 initially work for you. It may help to enable device hotplugging
895 support. 902 support.
896 903
904config ATAGS_PROC
905 bool "Export atags in procfs"
906 default n
907 help
908 Should the atags used to boot the kernel be exported in an "atags"
909 file in procfs. Useful with kexec.
910
897endmenu 911endmenu
898 912
899if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA) 913if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
diff --git a/arch/arm/common/time-acorn.c b/arch/arm/common/time-acorn.c
index 34038eccbba9..d544da414731 100644
--- a/arch/arm/common/time-acorn.c
+++ b/arch/arm/common/time-acorn.c
@@ -69,9 +69,7 @@ void __init ioctime_init(void)
69static irqreturn_t 69static irqreturn_t
70ioc_timer_interrupt(int irq, void *dev_id) 70ioc_timer_interrupt(int irq, void *dev_id)
71{ 71{
72 write_seqlock(&xtime_lock);
73 timer_tick(); 72 timer_tick();
74 write_sequnlock(&xtime_lock);
75 return IRQ_HANDLED; 73 return IRQ_HANDLED;
76} 74}
77 75
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index faa761921153..00d44c6fbfe9 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PCI) += bios32.o isa.o
20obj-$(CONFIG_SMP) += smp.o 20obj-$(CONFIG_SMP) += smp.o
21obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o 21obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
22obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o 22obj-$(CONFIG_KPROBES) += kprobes.o kprobes-decode.o
23obj-$(CONFIG_ATAGS_PROC) += atags.o
23obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o 24obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o
24 25
25obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o 26obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
diff --git a/arch/arm/kernel/atags.c b/arch/arm/kernel/atags.c
new file mode 100644
index 000000000000..e2e934c38080
--- /dev/null
+++ b/arch/arm/kernel/atags.c
@@ -0,0 +1,86 @@
1#include <linux/slab.h>
2#include <linux/kexec.h>
3#include <linux/proc_fs.h>
4#include <asm/setup.h>
5#include <asm/types.h>
6#include <asm/page.h>
7
8struct buffer {
9 size_t size;
10 char *data;
11};
12static struct buffer tags_buffer;
13
14static int
15read_buffer(char* page, char** start, off_t off, int count,
16 int* eof, void* data)
17{
18 struct buffer *buffer = (struct buffer *)data;
19
20 if (off >= buffer->size) {
21 *eof = 1;
22 return 0;
23 }
24
25 count = min((int) (buffer->size - off), count);
26
27 memcpy(page, &buffer->data[off], count);
28
29 return count;
30}
31
32
33static int
34create_proc_entries(void)
35{
36 struct proc_dir_entry* tags_entry;
37
38 tags_entry = create_proc_read_entry("atags", 0400, &proc_root, read_buffer, &tags_buffer);
39 if (!tags_entry)
40 return -ENOMEM;
41
42 return 0;
43}
44
45
46static char __initdata atags_copy_buf[KEXEC_BOOT_PARAMS_SIZE];
47static char __initdata *atags_copy;
48
49void __init save_atags(const struct tag *tags)
50{
51 atags_copy = atags_copy_buf;
52 memcpy(atags_copy, tags, KEXEC_BOOT_PARAMS_SIZE);
53}
54
55
56static int __init init_atags_procfs(void)
57{
58 struct tag *tag;
59 int error;
60
61 if (!atags_copy) {
62 printk(KERN_WARNING "Exporting ATAGs: No saved tags found\n");
63 return -EIO;
64 }
65
66 for (tag = (struct tag *) atags_copy; tag->hdr.size; tag = tag_next(tag))
67 ;
68
69 tags_buffer.size = ((char *) tag - atags_copy) + sizeof(tag->hdr);
70 tags_buffer.data = kmalloc(tags_buffer.size, GFP_KERNEL);
71 if (tags_buffer.data == NULL)
72 return -ENOMEM;
73 memcpy(tags_buffer.data, atags_copy, tags_buffer.size);
74
75 error = create_proc_entries();
76 if (error) {
77 printk(KERN_ERR "Exporting ATAGs: not enough memory\n");
78 kfree(tags_buffer.data);
79 tags_buffer.size = 0;
80 tags_buffer.data = NULL;
81 }
82
83 return error;
84}
85
86arch_initcall(init_atags_procfs);
diff --git a/arch/arm/kernel/atags.h b/arch/arm/kernel/atags.h
new file mode 100644
index 000000000000..e5f028d214a1
--- /dev/null
+++ b/arch/arm/kernel/atags.h
@@ -0,0 +1,5 @@
1#ifdef CONFIG_ATAGS_PROC
2extern void save_atags(struct tag *tags);
3#else
4static inline void save_atags(struct tag *tags) { }
5#endif
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 863c66454f2b..db8f54a3451f 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -21,6 +21,7 @@ extern void setup_mm_for_reboot(char mode);
21extern unsigned long kexec_start_address; 21extern unsigned long kexec_start_address;
22extern unsigned long kexec_indirection_page; 22extern unsigned long kexec_indirection_page;
23extern unsigned long kexec_mach_type; 23extern unsigned long kexec_mach_type;
24extern unsigned long kexec_boot_atags;
24 25
25/* 26/*
26 * Provide a dummy crash_notes definition while crash dump arrives to arm. 27 * Provide a dummy crash_notes definition while crash dump arrives to arm.
@@ -62,6 +63,7 @@ void machine_kexec(struct kimage *image)
62 kexec_start_address = image->start; 63 kexec_start_address = image->start;
63 kexec_indirection_page = page_list; 64 kexec_indirection_page = page_list;
64 kexec_mach_type = machine_arch_type; 65 kexec_mach_type = machine_arch_type;
66 kexec_boot_atags = image->start - KEXEC_ARM_ZIMAGE_OFFSET + KEXEC_ARM_ATAGS_OFFSET;
65 67
66 /* copy our kernel relocation code to the control code page */ 68 /* copy our kernel relocation code to the control code page */
67 memcpy(reboot_code_buffer, 69 memcpy(reboot_code_buffer,
diff --git a/arch/arm/kernel/relocate_kernel.S b/arch/arm/kernel/relocate_kernel.S
index 062c111c572f..61930eb09029 100644
--- a/arch/arm/kernel/relocate_kernel.S
+++ b/arch/arm/kernel/relocate_kernel.S
@@ -7,23 +7,6 @@
7 .globl relocate_new_kernel 7 .globl relocate_new_kernel
8relocate_new_kernel: 8relocate_new_kernel:
9 9
10 /* Move boot params back to where the kernel expects them */
11
12 ldr r0,kexec_boot_params_address
13 teq r0,#0
14 beq 8f
15
16 ldr r1,kexec_boot_params_copy
17 mov r6,#KEXEC_BOOT_PARAMS_SIZE/4
187:
19 ldr r5,[r1],#4
20 str r5,[r0],#4
21 subs r6,r6,#1
22 bne 7b
23
248:
25 /* Boot params moved, now go on with the kernel */
26
27 ldr r0,kexec_indirection_page 10 ldr r0,kexec_indirection_page
28 ldr r1,kexec_start_address 11 ldr r1,kexec_start_address
29 12
@@ -67,7 +50,7 @@ relocate_new_kernel:
67 mov lr,r1 50 mov lr,r1
68 mov r0,#0 51 mov r0,#0
69 ldr r1,kexec_mach_type 52 ldr r1,kexec_mach_type
70 ldr r2,kexec_boot_params_address 53 ldr r2,kexec_boot_atags
71 mov pc,lr 54 mov pc,lr
72 55
73 .globl kexec_start_address 56 .globl kexec_start_address
@@ -82,14 +65,9 @@ kexec_indirection_page:
82kexec_mach_type: 65kexec_mach_type:
83 .long 0x0 66 .long 0x0
84 67
85 /* phy addr where new kernel will expect to find boot params */ 68 /* phy addr of the atags for the new kernel */
86 .globl kexec_boot_params_address 69 .globl kexec_boot_atags
87kexec_boot_params_address: 70kexec_boot_atags:
88 .long 0x0
89
90 /* phy addr where old kernel put a copy of orig boot params */
91 .globl kexec_boot_params_copy
92kexec_boot_params_copy:
93 .long 0x0 71 .long 0x0
94 72
95relocate_new_kernel_end: 73relocate_new_kernel_end:
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index dd37901f786a..d3941a7b0455 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -24,7 +24,6 @@
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/smp.h> 25#include <linux/smp.h>
26#include <linux/fs.h> 26#include <linux/fs.h>
27#include <linux/kexec.h>
28 27
29#include <asm/cpu.h> 28#include <asm/cpu.h>
30#include <asm/elf.h> 29#include <asm/elf.h>
@@ -39,6 +38,7 @@
39#include <asm/mach/time.h> 38#include <asm/mach/time.h>
40 39
41#include "compat.h" 40#include "compat.h"
41#include "atags.h"
42 42
43#ifndef MEM_SIZE 43#ifndef MEM_SIZE
44#define MEM_SIZE (16*1024*1024) 44#define MEM_SIZE (16*1024*1024)
@@ -785,23 +785,6 @@ static int __init customize_machine(void)
785} 785}
786arch_initcall(customize_machine); 786arch_initcall(customize_machine);
787 787
788#ifdef CONFIG_KEXEC
789
790/* Physical addr of where the boot params should be for this machine */
791extern unsigned long kexec_boot_params_address;
792
793/* Physical addr of the buffer into which the boot params are copied */
794extern unsigned long kexec_boot_params_copy;
795
796/* Pointer to the boot params buffer, for manipulation and display */
797unsigned long kexec_boot_params;
798EXPORT_SYMBOL(kexec_boot_params);
799
800/* The buffer itself - make sure it is sized correctly */
801static unsigned long kexec_boot_params_buf[(KEXEC_BOOT_PARAMS_SIZE + 3) / 4];
802
803#endif
804
805void __init setup_arch(char **cmdline_p) 788void __init setup_arch(char **cmdline_p)
806{ 789{
807 struct tag *tags = (struct tag *)&init_tags; 790 struct tag *tags = (struct tag *)&init_tags;
@@ -820,18 +803,6 @@ void __init setup_arch(char **cmdline_p)
820 else if (mdesc->boot_params) 803 else if (mdesc->boot_params)
821 tags = phys_to_virt(mdesc->boot_params); 804 tags = phys_to_virt(mdesc->boot_params);
822 805
823#ifdef CONFIG_KEXEC
824 kexec_boot_params_copy = virt_to_phys(kexec_boot_params_buf);
825 kexec_boot_params = (unsigned long)kexec_boot_params_buf;
826 if (__atags_pointer) {
827 kexec_boot_params_address = __atags_pointer;
828 memcpy((void *)kexec_boot_params, tags, KEXEC_BOOT_PARAMS_SIZE);
829 } else if (mdesc->boot_params) {
830 kexec_boot_params_address = mdesc->boot_params;
831 memcpy((void *)kexec_boot_params, tags, KEXEC_BOOT_PARAMS_SIZE);
832 }
833#endif
834
835 /* 806 /*
836 * If we have the old style parameters, convert them to 807 * If we have the old style parameters, convert them to
837 * a tag list. 808 * a tag list.
@@ -847,6 +818,7 @@ void __init setup_arch(char **cmdline_p)
847 if (tags->hdr.tag == ATAG_CORE) { 818 if (tags->hdr.tag == ATAG_CORE) {
848 if (meminfo.nr_banks != 0) 819 if (meminfo.nr_banks != 0)
849 squash_mem_tags(tags); 820 squash_mem_tags(tags);
821 save_atags(tags);
850 parse_tags(tags); 822 parse_tags(tags);
851 } 823 }
852 824
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index eafbb2b05eb8..e9dfbab46cb6 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -290,6 +290,11 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
290 local_irq_enable(); 290 local_irq_enable();
291 local_fiq_enable(); 291 local_fiq_enable();
292 292
293 /*
294 * Setup local timer for this CPU.
295 */
296 local_timer_setup(cpu);
297
293 calibrate_delay(); 298 calibrate_delay();
294 299
295 smp_store_cpu_info(cpu); 300 smp_store_cpu_info(cpu);
@@ -300,11 +305,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
300 cpu_set(cpu, cpu_online_map); 305 cpu_set(cpu, cpu_online_map);
301 306
302 /* 307 /*
303 * Setup local timer for this CPU.
304 */
305 local_timer_setup(cpu);
306
307 /*
308 * OK, it's off to the idle thread for us 308 * OK, it's off to the idle thread for us
309 */ 309 */
310 cpu_idle(); 310 cpu_idle();
@@ -454,6 +454,27 @@ int smp_call_function(void (*func)(void *info), void *info, int retry,
454} 454}
455EXPORT_SYMBOL_GPL(smp_call_function); 455EXPORT_SYMBOL_GPL(smp_call_function);
456 456
457int smp_call_function_single(int cpu, void (*func)(void *info), void *info,
458 int retry, int wait)
459{
460 /* prevent preemption and reschedule on another processor */
461 int current_cpu = get_cpu();
462 int ret = 0;
463
464 if (cpu == current_cpu) {
465 local_irq_disable();
466 func(info);
467 local_irq_enable();
468 } else
469 ret = smp_call_function_on_cpu(func, info, retry, wait,
470 cpumask_of_cpu(cpu));
471
472 put_cpu();
473
474 return ret;
475}
476EXPORT_SYMBOL_GPL(smp_call_function_single);
477
457void show_ipi_list(struct seq_file *p) 478void show_ipi_list(struct seq_file *p)
458{ 479{
459 unsigned int cpu; 480 unsigned int cpu;
@@ -481,8 +502,7 @@ void show_local_irqs(struct seq_file *p)
481static void ipi_timer(void) 502static void ipi_timer(void)
482{ 503{
483 irq_enter(); 504 irq_enter();
484 profile_tick(CPU_PROFILING); 505 local_timer_interrupt();
485 update_process_times(user_mode(get_irq_regs()));
486 irq_exit(); 506 irq_exit();
487} 507}
488 508
@@ -621,6 +641,11 @@ void smp_send_timer(void)
621 send_ipi_message(mask, IPI_TIMER); 641 send_ipi_message(mask, IPI_TIMER);
622} 642}
623 643
644void smp_timer_broadcast(cpumask_t mask)
645{
646 send_ipi_message(mask, IPI_TIMER);
647}
648
624void smp_send_stop(void) 649void smp_send_stop(void)
625{ 650{
626 cpumask_t mask = cpu_online_map; 651 cpumask_t mask = cpu_online_map;
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 5b0422cdde76..074dcd5d9a7e 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -253,6 +253,36 @@ config AT91_TIMER_HZ
253 system clock (of at least several MHz), rounding is less of a 253 system clock (of at least several MHz), rounding is less of a
254 problem so it can be safer to use a decimal values like 100. 254 problem so it can be safer to use a decimal values like 100.
255 255
256choice
257 prompt "Select a UART for early kernel messages"
258
259config AT91_EARLY_DBGU
260 bool "DBGU"
261
262config AT91_EARLY_USART0
263 bool "USART0"
264
265config AT91_EARLY_USART1
266 bool "USART1"
267
268config AT91_EARLY_USART2
269 bool "USART2"
270 depends on ! ARCH_AT91X40
271
272config AT91_EARLY_USART3
273 bool "USART3"
274 depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260)
275
276config AT91_EARLY_USART4
277 bool "USART4"
278 depends on ARCH_AT91SAM9260
279
280config AT91_EARLY_USART5
281 bool "USART5"
282 depends on ARCH_AT91SAM9260
283
284endchoice
285
256endmenu 286endmenu
257 287
258endif 288endif
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 5c090c9442f5..e38d23770992 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -49,8 +49,6 @@ static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
49 volatile long nr_ticks; 49 volatile long nr_ticks;
50 50
51 if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */ 51 if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) { /* This is a shared interrupt */
52 write_seqlock(&xtime_lock);
53
54 /* Get number to ticks performed before interrupt and clear PIT interrupt */ 52 /* Get number to ticks performed before interrupt and clear PIT interrupt */
55 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); 53 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
56 do { 54 do {
@@ -58,7 +56,6 @@ static irqreturn_t at91sam926x_timer_interrupt(int irq, void *dev_id)
58 nr_ticks--; 56 nr_ticks--;
59 } while (nr_ticks); 57 } while (nr_ticks);
60 58
61 write_sequnlock(&xtime_lock);
62 return IRQ_HANDLED; 59 return IRQ_HANDLED;
63 } else 60 } else
64 return IRQ_NONE; /* not handled */ 61 return IRQ_NONE; /* not handled */
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index b5daf7f5e011..7b9ce7a336b0 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -47,6 +47,9 @@ extern void at91_irq_resume(void);
47#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ 47#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
48 48
49struct at91_gpio_bank { 49struct at91_gpio_bank {
50 unsigned chipbase; /* bank's first GPIO number */
51 void __iomem *regbase; /* base of register bank */
52 struct at91_gpio_bank *next; /* bank sharing same IRQ/clock/... */
50 unsigned short id; /* peripheral ID */ 53 unsigned short id; /* peripheral ID */
51 unsigned long offset; /* offset from system peripheral base */ 54 unsigned long offset; /* offset from system peripheral base */
52 struct clk *clock; /* associated clock */ 55 struct clk *clock; /* associated clock */
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 6aeddd68d8af..f629c2b5f0c5 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -33,12 +33,10 @@ static int gpio_banks;
33 33
34static inline void __iomem *pin_to_controller(unsigned pin) 34static inline void __iomem *pin_to_controller(unsigned pin)
35{ 35{
36 void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
37
38 pin -= PIN_BASE; 36 pin -= PIN_BASE;
39 pin /= 32; 37 pin /= 32;
40 if (likely(pin < gpio_banks)) 38 if (likely(pin < gpio_banks))
41 return sys_base + gpio[pin].offset; 39 return gpio[pin].regbase;
42 40
43 return NULL; 41 return NULL;
44} 42}
@@ -294,11 +292,11 @@ void at91_gpio_suspend(void)
294 int i; 292 int i;
295 293
296 for (i = 0; i < gpio_banks; i++) { 294 for (i = 0; i < gpio_banks; i++) {
297 u32 pio = gpio[i].offset; 295 void __iomem *pio = gpio[i].regbase;
298 296
299 backups[i] = at91_sys_read(pio + PIO_IMR); 297 backups[i] = __raw_readl(pio + PIO_IMR);
300 at91_sys_write(pio + PIO_IDR, backups[i]); 298 __raw_writel(backups[i], pio + PIO_IDR);
301 at91_sys_write(pio + PIO_IER, wakeups[i]); 299 __raw_writel(wakeups[i], pio + PIO_IER);
302 300
303 if (!wakeups[i]) 301 if (!wakeups[i])
304 clk_disable(gpio[i].clock); 302 clk_disable(gpio[i].clock);
@@ -315,13 +313,13 @@ void at91_gpio_resume(void)
315 int i; 313 int i;
316 314
317 for (i = 0; i < gpio_banks; i++) { 315 for (i = 0; i < gpio_banks; i++) {
318 u32 pio = gpio[i].offset; 316 void __iomem *pio = gpio[i].regbase;
319 317
320 if (!wakeups[i]) 318 if (!wakeups[i])
321 clk_enable(gpio[i].clock); 319 clk_enable(gpio[i].clock);
322 320
323 at91_sys_write(pio + PIO_IDR, wakeups[i]); 321 __raw_writel(wakeups[i], pio + PIO_IDR);
324 at91_sys_write(pio + PIO_IER, backups[i]); 322 __raw_writel(backups[i], pio + PIO_IER);
325 } 323 }
326} 324}
327 325
@@ -361,7 +359,13 @@ static void gpio_irq_unmask(unsigned pin)
361 359
362static int gpio_irq_type(unsigned pin, unsigned type) 360static int gpio_irq_type(unsigned pin, unsigned type)
363{ 361{
364 return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL; 362 switch (type) {
363 case IRQ_TYPE_NONE:
364 case IRQ_TYPE_EDGE_BOTH:
365 return 0;
366 default:
367 return -EINVAL;
368 }
365} 369}
366 370
367static struct irq_chip gpio_irqchip = { 371static struct irq_chip gpio_irqchip = {
@@ -376,20 +380,30 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
376{ 380{
377 unsigned pin; 381 unsigned pin;
378 struct irq_desc *gpio; 382 struct irq_desc *gpio;
383 struct at91_gpio_bank *bank;
379 void __iomem *pio; 384 void __iomem *pio;
380 u32 isr; 385 u32 isr;
381 386
382 pio = get_irq_chip_data(irq); 387 bank = get_irq_chip_data(irq);
388 pio = bank->regbase;
383 389
384 /* temporarily mask (level sensitive) parent IRQ */ 390 /* temporarily mask (level sensitive) parent IRQ */
385 desc->chip->ack(irq); 391 desc->chip->ack(irq);
386 for (;;) { 392 for (;;) {
387 /* reading ISR acks the pending (edge triggered) GPIO interrupt */ 393 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
394 * When there none are pending, we're finished unless we need
395 * to process multiple banks (like ID_PIOCDE on sam9263).
396 */
388 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); 397 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
389 if (!isr) 398 if (!isr) {
390 break; 399 if (!bank->next)
400 break;
401 bank = bank->next;
402 pio = bank->regbase;
403 continue;
404 }
391 405
392 pin = (unsigned) get_irq_data(irq); 406 pin = bank->chipbase;
393 gpio = &irq_desc[pin]; 407 gpio = &irq_desc[pin];
394 408
395 while (isr) { 409 while (isr) {
@@ -481,24 +495,21 @@ postcore_initcall(at91_gpio_debugfs_init);
481 */ 495 */
482void __init at91_gpio_irq_setup(void) 496void __init at91_gpio_irq_setup(void)
483{ 497{
484 unsigned pioc, pin; 498 unsigned pioc, pin;
499 struct at91_gpio_bank *this, *prev;
485 500
486 for (pioc = 0, pin = PIN_BASE; 501 for (pioc = 0, pin = PIN_BASE, this = gpio, prev = NULL;
487 pioc < gpio_banks; 502 pioc++ < gpio_banks;
488 pioc++) { 503 prev = this, this++) {
489 void __iomem *controller; 504 unsigned id = this->id;
490 unsigned id = gpio[pioc].id;
491 unsigned i; 505 unsigned i;
492 506
493 clk_enable(gpio[pioc].clock); /* enable PIO controller's clock */ 507 /* enable PIO controller's clock */
494 508 clk_enable(this->clock);
495 controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset;
496 __raw_writel(~0, controller + PIO_IDR);
497 509
498 set_irq_data(id, (void *) pin); 510 __raw_writel(~0, this->regbase + PIO_IDR);
499 set_irq_chip_data(id, controller);
500 511
501 for (i = 0; i < 32; i++, pin++) { 512 for (i = 0, pin = this->chipbase; i < 32; i++, pin++) {
502 /* 513 /*
503 * Can use the "simple" and not "edge" handler since it's 514 * Can use the "simple" and not "edge" handler since it's
504 * shorter, and the AIC handles interrupts sanely. 515 * shorter, and the AIC handles interrupts sanely.
@@ -508,6 +519,14 @@ void __init at91_gpio_irq_setup(void)
508 set_irq_flags(pin, IRQF_VALID); 519 set_irq_flags(pin, IRQF_VALID);
509 } 520 }
510 521
522 /* The toplevel handler handles one bank of GPIOs, except
523 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
524 * the list, so we only set up that handler.
525 */
526 if (prev && prev->next == this)
527 continue;
528
529 set_irq_chip_data(id, this);
511 set_irq_chained_handler(id, gpio_irq_handler); 530 set_irq_chained_handler(id, gpio_irq_handler);
512 } 531 }
513 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); 532 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
@@ -518,8 +537,20 @@ void __init at91_gpio_irq_setup(void)
518 */ 537 */
519void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) 538void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
520{ 539{
540 unsigned i;
541 struct at91_gpio_bank *last;
542
521 BUG_ON(nr_banks > MAX_GPIO_BANKS); 543 BUG_ON(nr_banks > MAX_GPIO_BANKS);
522 544
523 gpio = data; 545 gpio = data;
524 gpio_banks = nr_banks; 546 gpio_banks = nr_banks;
547
548 for (i = 0, last = NULL; i < nr_banks; i++, last = data, data++) {
549 data->chipbase = PIN_BASE + i * 32;
550 data->regbase = data->offset + (void __iomem *)AT91_VA_BASE_SYS;
551
552 /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
553 if (last && last->id == data->id)
554 last->next = data;
555 }
525} 556}
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index b5c916c0747d..8604938bd948 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -6,7 +6,7 @@
6obj-y += clock.o devices.o generic.o irq.o dma.o time.o 6obj-y += clock.o devices.o generic.o irq.o dma.o time.o
7obj-$(CONFIG_PXA25x) += pxa25x.o 7obj-$(CONFIG_PXA25x) += pxa25x.o
8obj-$(CONFIG_PXA27x) += pxa27x.o 8obj-$(CONFIG_PXA27x) += pxa27x.o
9obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o 9obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o smemc.o
10obj-$(CONFIG_CPU_PXA300) += pxa300.o 10obj-$(CONFIG_CPU_PXA300) += pxa300.o
11obj-$(CONFIG_CPU_PXA320) += pxa320.o 11obj-$(CONFIG_CPU_PXA320) += pxa320.o
12 12
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index 28cfd71c032d..6012177a29a3 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -29,6 +29,7 @@
29#include <asm/mach/map.h> 29#include <asm/mach/map.h>
30 30
31#include <asm/arch/pxa-regs.h> 31#include <asm/arch/pxa-regs.h>
32#include <asm/arch/pxa2xx-regs.h>
32#include <asm/arch/pxafb.h> 33#include <asm/arch/pxafb.h>
33#include <asm/arch/ohci.h> 34#include <asm/arch/ohci.h>
34#include <asm/arch/mmc.h> 35#include <asm/arch/mmc.h>
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 50ff453ad370..bfccb80ac8ef 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -10,6 +10,7 @@
10#include <asm/arch/mmc.h> 10#include <asm/arch/mmc.h>
11#include <asm/arch/irda.h> 11#include <asm/arch/irda.h>
12#include <asm/arch/i2c.h> 12#include <asm/arch/i2c.h>
13#include <asm/arch/ohci.h>
13 14
14#include "devices.h" 15#include "devices.h"
15 16
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 698aeec52961..76970598f550 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -23,6 +23,7 @@
23#include <linux/ioport.h> 23#include <linux/ioport.h>
24#include <linux/pm.h> 24#include <linux/pm.h>
25#include <linux/string.h> 25#include <linux/string.h>
26#include <linux/sysdev.h>
26 27
27#include <asm/hardware.h> 28#include <asm/hardware.h>
28#include <asm/irq.h> 29#include <asm/irq.h>
@@ -226,3 +227,59 @@ void __init pxa_map_io(void)
226 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 227 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
227 get_clk_frequency_khz(1); 228 get_clk_frequency_khz(1);
228} 229}
230
231#ifdef CONFIG_PM
232
233static unsigned long saved_gplr[4];
234static unsigned long saved_gpdr[4];
235static unsigned long saved_grer[4];
236static unsigned long saved_gfer[4];
237
238static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state)
239{
240 int i, gpio;
241
242 for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
243 saved_gplr[i] = GPLR(gpio);
244 saved_gpdr[i] = GPDR(gpio);
245 saved_grer[i] = GRER(gpio);
246 saved_gfer[i] = GFER(gpio);
247
248 /* Clear GPIO transition detect bits */
249 GEDR(gpio) = GEDR(gpio);
250 }
251 return 0;
252}
253
254static int pxa_gpio_resume(struct sys_device *dev)
255{
256 int i, gpio;
257
258 for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) {
259 /* restore level with set/clear */
260 GPSR(gpio) = saved_gplr[i];
261 GPCR(gpio) = ~saved_gplr[i];
262
263 GRER(gpio) = saved_grer[i];
264 GFER(gpio) = saved_gfer[i];
265 GPDR(gpio) = saved_gpdr[i];
266 }
267 return 0;
268}
269#else
270#define pxa_gpio_suspend NULL
271#define pxa_gpio_resume NULL
272#endif
273
274struct sysdev_class pxa_gpio_sysclass = {
275 .name = "gpio",
276 .suspend = pxa_gpio_suspend,
277 .resume = pxa_gpio_resume,
278};
279
280static int __init pxa_gpio_init(void)
281{
282 return sysdev_class_register(&pxa_gpio_sysclass);
283}
284
285core_initcall(pxa_gpio_init);
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index b30f240a16c7..1a16ad3ecee6 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -52,3 +52,6 @@ extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
52#define pxa3xx_get_clk_frequency_khz(x) (0) 52#define pxa3xx_get_clk_frequency_khz(x) (0)
53#define pxa3xx_get_memclk_frequency_10khz() (0) 53#define pxa3xx_get_memclk_frequency_10khz() (0)
54#endif 54#endif
55
56extern struct sysdev_class pxa_irq_sysclass;
57extern struct sysdev_class pxa_gpio_sysclass;
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 07acb45b16ea..5a1d5eef10a4 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/sysdev.h>
18 19
19#include <asm/hardware.h> 20#include <asm/hardware.h>
20#include <asm/irq.h> 21#include <asm/irq.h>
@@ -321,3 +322,64 @@ void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
321 pxa_low_gpio_chip.set_wake = set_wake; 322 pxa_low_gpio_chip.set_wake = set_wake;
322 pxa_muxed_gpio_chip.set_wake = set_wake; 323 pxa_muxed_gpio_chip.set_wake = set_wake;
323} 324}
325
326#ifdef CONFIG_PM
327static unsigned long saved_icmr[2];
328
329static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
330{
331 switch (dev->id) {
332 case 0:
333 saved_icmr[0] = ICMR;
334 ICMR = 0;
335 break;
336#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
337 case 1:
338 saved_icmr[1] = ICMR2;
339 ICMR2 = 0;
340 break;
341#endif
342 default:
343 return -EINVAL;
344 }
345
346 return 0;
347}
348
349static int pxa_irq_resume(struct sys_device *dev)
350{
351 switch (dev->id) {
352 case 0:
353 ICMR = saved_icmr[0];
354 ICLR = 0;
355 ICCR = 1;
356 break;
357#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
358 case 1:
359 ICMR2 = saved_icmr[1];
360 ICLR2 = 0;
361 break;
362#endif
363 default:
364 return -EINVAL;
365 }
366
367 return 0;
368}
369#else
370#define pxa_irq_suspend NULL
371#define pxa_irq_resume NULL
372#endif
373
374struct sysdev_class pxa_irq_sysclass = {
375 .name = "irq",
376 .suspend = pxa_irq_suspend,
377 .resume = pxa_irq_resume,
378};
379
380static int __init pxa_irq_init(void)
381{
382 return sysdev_class_register(&pxa_irq_sysclass);
383}
384
385core_initcall(pxa_irq_init);
diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp.c
index ec1b2d8f61c4..f5809adce298 100644
--- a/arch/arm/mach-pxa/mfp.c
+++ b/arch/arm/mach-pxa/mfp.c
@@ -22,6 +22,7 @@
22#include <asm/hardware.h> 22#include <asm/hardware.h>
23#include <asm/arch/mfp.h> 23#include <asm/arch/mfp.h>
24#include <asm/arch/mfp-pxa3xx.h> 24#include <asm/arch/mfp-pxa3xx.h>
25#include <asm/arch/pxa3xx-regs.h>
25 26
26/* mfp_spin_lock is used to ensure that MFP register configuration 27/* mfp_spin_lock is used to ensure that MFP register configuration
27 * (most likely a read-modify-write operation) is atomic, and that 28 * (most likely a read-modify-write operation) is atomic, and that
@@ -223,11 +224,19 @@ static int pxa3xx_mfp_resume(struct sys_device *d)
223 struct pxa3xx_mfp_pin *p = &mfp_table[pin]; 224 struct pxa3xx_mfp_pin *p = &mfp_table[pin];
224 __mfp_config_run(p); 225 __mfp_config_run(p);
225 } 226 }
227
228 /* clear RDH bit when MFP settings are restored
229 *
230 * NOTE: the last 3 bits DxS are write-1-to-clear so carefully
231 * preserve them here in case they will be referenced later
232 */
233 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
234
226 return 0; 235 return 0;
227} 236}
228 237
229static struct sysdev_class mfp_sysclass = { 238static struct sysdev_class mfp_sysclass = {
230 set_kset_name("mfp"), 239 .name = "mfp",
231 .suspend = pxa3xx_mfp_suspend, 240 .suspend = pxa3xx_mfp_suspend,
232 .resume = pxa3xx_mfp_resume, 241 .resume = pxa3xx_mfp_resume,
233}; 242};
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 540c3bba5f9a..c14696b9979d 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -29,6 +29,7 @@
29#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
30#include <asm/arch/hardware.h> 30#include <asm/arch/hardware.h>
31#include <asm/arch/pxa-regs.h> 31#include <asm/arch/pxa-regs.h>
32#include <asm/arch/pxa2xx-regs.h>
32#include <asm/arch/pxa2xx_spi.h> 33#include <asm/arch/pxa2xx_spi.h>
33#include <asm/arch/pcm027.h> 34#include <asm/arch/pcm027.h>
34#include "generic.h" 35#include "generic.h"
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index dd54496083cb..209eabf0ed3e 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -164,7 +164,7 @@ static struct resource poodlets_resources[] = {
164 }, 164 },
165}; 165};
166 166
167static unsigned long poodle_get_hsync_len(void) 167static unsigned long poodle_get_hsync_invperiod(void)
168{ 168{
169 return 0; 169 return 0;
170} 170}
@@ -174,9 +174,9 @@ static void poodle_null_hsync(void)
174} 174}
175 175
176static struct corgits_machinfo poodle_ts_machinfo = { 176static struct corgits_machinfo poodle_ts_machinfo = {
177 .get_hsync_len = poodle_get_hsync_len, 177 .get_hsync_invperiod = poodle_get_hsync_invperiod,
178 .put_hsync = poodle_null_hsync, 178 .put_hsync = poodle_null_hsync,
179 .wait_hsync = poodle_null_hsync, 179 .wait_hsync = poodle_null_hsync,
180}; 180};
181 181
182static struct platform_device poodle_ts_device = { 182static struct platform_device poodle_ts_device = {
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index ddd05bf78e02..599e53fcc2c5 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/suspend.h> 23#include <linux/suspend.h>
24#include <linux/sysdev.h>
24 25
25#include <asm/hardware.h> 26#include <asm/hardware.h>
26#include <asm/arch/irqs.h> 27#include <asm/arch/irqs.h>
@@ -141,11 +142,6 @@ static struct clk pxa25x_clks[] = {
141#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 142#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
142#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 143#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
143 144
144#define RESTORE_GPLEVEL(n) do { \
145 GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
146 GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
147} while (0)
148
149/* 145/*
150 * List of global PXA peripheral registers to preserve. 146 * List of global PXA peripheral registers to preserve.
151 * More ones like CP and general purpose register values are preserved 147 * More ones like CP and general purpose register values are preserved
@@ -153,10 +149,6 @@ static struct clk pxa25x_clks[] = {
153 */ 149 */
154enum { SLEEP_SAVE_START = 0, 150enum { SLEEP_SAVE_START = 0,
155 151
156 SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2,
157 SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2,
158 SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2,
159 SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2,
160 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, 152 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
161 153
162 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 154 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
@@ -165,7 +157,6 @@ enum { SLEEP_SAVE_START = 0,
165 157
166 SLEEP_SAVE_PSTR, 158 SLEEP_SAVE_PSTR,
167 159
168 SLEEP_SAVE_ICMR,
169 SLEEP_SAVE_CKEN, 160 SLEEP_SAVE_CKEN,
170 161
171 SLEEP_SAVE_SIZE 162 SLEEP_SAVE_SIZE
@@ -174,17 +165,12 @@ enum { SLEEP_SAVE_START = 0,
174 165
175static void pxa25x_cpu_pm_save(unsigned long *sleep_save) 166static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
176{ 167{
177 SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2);
178 SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2);
179 SAVE(GRER0); SAVE(GRER1); SAVE(GRER2);
180 SAVE(GFER0); SAVE(GFER1); SAVE(GFER2);
181 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); 168 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
182 169
183 SAVE(GAFR0_L); SAVE(GAFR0_U); 170 SAVE(GAFR0_L); SAVE(GAFR0_U);
184 SAVE(GAFR1_L); SAVE(GAFR1_U); 171 SAVE(GAFR1_L); SAVE(GAFR1_U);
185 SAVE(GAFR2_L); SAVE(GAFR2_U); 172 SAVE(GAFR2_L); SAVE(GAFR2_U);
186 173
187 SAVE(ICMR); ICMR = 0;
188 SAVE(CKEN); 174 SAVE(CKEN);
189 SAVE(PSTR); 175 SAVE(PSTR);
190 176
@@ -198,22 +184,14 @@ static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
198 PSPR = 0; 184 PSPR = 0;
199 185
200 /* restore registers */ 186 /* restore registers */
201 RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1); RESTORE_GPLEVEL(2);
202 RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2);
203 RESTORE(GAFR0_L); RESTORE(GAFR0_U); 187 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
204 RESTORE(GAFR1_L); RESTORE(GAFR1_U); 188 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
205 RESTORE(GAFR2_L); RESTORE(GAFR2_U); 189 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
206 RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2);
207 RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2);
208 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); 190 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
209 191
210 PSSR = PSSR_RDH | PSSR_PH; 192 PSSR = PSSR_RDH | PSSR_PH;
211 193
212 RESTORE(CKEN); 194 RESTORE(CKEN);
213
214 ICLR = 0;
215 ICCR = 1;
216 RESTORE(ICMR);
217 RESTORE(PSTR); 195 RESTORE(PSTR);
218} 196}
219 197
@@ -304,9 +282,17 @@ static struct platform_device *pxa25x_devices[] __initdata = {
304 &pxa25x_device_assp, 282 &pxa25x_device_assp,
305}; 283};
306 284
285static struct sys_device pxa25x_sysdev[] = {
286 {
287 .cls = &pxa_irq_sysclass,
288 }, {
289 .cls = &pxa_gpio_sysclass,
290 },
291};
292
307static int __init pxa25x_init(void) 293static int __init pxa25x_init(void)
308{ 294{
309 int ret = 0; 295 int i, ret = 0;
310 296
311 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ 297 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
312 if (cpu_is_pxa25x()) 298 if (cpu_is_pxa25x())
@@ -320,9 +306,18 @@ static int __init pxa25x_init(void)
320 306
321 pxa25x_init_pm(); 307 pxa25x_init_pm();
322 308
309 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
310 ret = sysdev_register(&pxa25x_sysdev[i]);
311 if (ret)
312 pr_err("failed to register sysdev[%d]\n", i);
313 }
314
323 ret = platform_add_devices(pxa25x_devices, 315 ret = platform_add_devices(pxa25x_devices,
324 ARRAY_SIZE(pxa25x_devices)); 316 ARRAY_SIZE(pxa25x_devices));
317 if (ret)
318 return ret;
325 } 319 }
320
326 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ 321 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
327 if (cpu_is_pxa25x()) 322 if (cpu_is_pxa25x())
328 ret = platform_device_register(&pxa_device_hwuart); 323 ret = platform_device_register(&pxa_device_hwuart);
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 96cf274ec7cb..46a951c3e5a0 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -16,6 +16,7 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/suspend.h> 17#include <linux/suspend.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/sysdev.h>
19 20
20#include <asm/hardware.h> 21#include <asm/hardware.h>
21#include <asm/irq.h> 22#include <asm/irq.h>
@@ -171,11 +172,6 @@ static struct clk pxa27x_clks[] = {
171#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 172#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
172#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 173#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
173 174
174#define RESTORE_GPLEVEL(n) do { \
175 GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
176 GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
177} while (0)
178
179/* 175/*
180 * List of global PXA peripheral registers to preserve. 176 * List of global PXA peripheral registers to preserve.
181 * More ones like CP and general purpose register values are preserved 177 * More ones like CP and general purpose register values are preserved
@@ -183,10 +179,6 @@ static struct clk pxa27x_clks[] = {
183 */ 179 */
184enum { SLEEP_SAVE_START = 0, 180enum { SLEEP_SAVE_START = 0,
185 181
186 SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
187 SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
188 SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
189 SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
190 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3, 182 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
191 183
192 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 184 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
@@ -196,7 +188,6 @@ enum { SLEEP_SAVE_START = 0,
196 188
197 SLEEP_SAVE_PSTR, 189 SLEEP_SAVE_PSTR,
198 190
199 SLEEP_SAVE_ICMR,
200 SLEEP_SAVE_CKEN, 191 SLEEP_SAVE_CKEN,
201 192
202 SLEEP_SAVE_MDREFR, 193 SLEEP_SAVE_MDREFR,
@@ -208,10 +199,6 @@ enum { SLEEP_SAVE_START = 0,
208 199
209void pxa27x_cpu_pm_save(unsigned long *sleep_save) 200void pxa27x_cpu_pm_save(unsigned long *sleep_save)
210{ 201{
211 SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3);
212 SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3);
213 SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3);
214 SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3);
215 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3); 202 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
216 203
217 SAVE(GAFR0_L); SAVE(GAFR0_U); 204 SAVE(GAFR0_L); SAVE(GAFR0_U);
@@ -223,12 +210,8 @@ void pxa27x_cpu_pm_save(unsigned long *sleep_save)
223 SAVE(PWER); SAVE(PCFR); SAVE(PRER); 210 SAVE(PWER); SAVE(PCFR); SAVE(PRER);
224 SAVE(PFER); SAVE(PKWR); 211 SAVE(PFER); SAVE(PKWR);
225 212
226 SAVE(ICMR); ICMR = 0;
227 SAVE(CKEN); 213 SAVE(CKEN);
228 SAVE(PSTR); 214 SAVE(PSTR);
229
230 /* Clear GPIO transition detect bits */
231 GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3;
232} 215}
233 216
234void pxa27x_cpu_pm_restore(unsigned long *sleep_save) 217void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
@@ -237,15 +220,10 @@ void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
237 PSPR = 0; 220 PSPR = 0;
238 221
239 /* restore registers */ 222 /* restore registers */
240 RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1);
241 RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3);
242 RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3);
243 RESTORE(GAFR0_L); RESTORE(GAFR0_U); 223 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
244 RESTORE(GAFR1_L); RESTORE(GAFR1_U); 224 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
245 RESTORE(GAFR2_L); RESTORE(GAFR2_U); 225 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
246 RESTORE(GAFR3_L); RESTORE(GAFR3_U); 226 RESTORE(GAFR3_L); RESTORE(GAFR3_U);
247 RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3);
248 RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3);
249 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3); 227 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
250 228
251 RESTORE(MDREFR); 229 RESTORE(MDREFR);
@@ -256,9 +234,6 @@ void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
256 234
257 RESTORE(CKEN); 235 RESTORE(CKEN);
258 236
259 ICLR = 0;
260 ICCR = 1;
261 RESTORE(ICMR);
262 RESTORE(PSTR); 237 RESTORE(PSTR);
263} 238}
264 239
@@ -409,9 +384,22 @@ static struct platform_device *devices[] __initdata = {
409 &pxa27x_device_ssp3, 384 &pxa27x_device_ssp3,
410}; 385};
411 386
387static struct sys_device pxa27x_sysdev[] = {
388 {
389 .id = 0,
390 .cls = &pxa_irq_sysclass,
391 }, {
392 .id = 1,
393 .cls = &pxa_irq_sysclass,
394 }, {
395 .cls = &pxa_gpio_sysclass,
396 },
397};
398
412static int __init pxa27x_init(void) 399static int __init pxa27x_init(void)
413{ 400{
414 int ret = 0; 401 int i, ret = 0;
402
415 if (cpu_is_pxa27x()) { 403 if (cpu_is_pxa27x()) {
416 clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks)); 404 clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
417 405
@@ -420,8 +408,15 @@ static int __init pxa27x_init(void)
420 408
421 pxa27x_init_pm(); 409 pxa27x_init_pm();
422 410
411 for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
412 ret = sysdev_register(&pxa27x_sysdev[i]);
413 if (ret)
414 pr_err("failed to register sysdev[%d]\n", i);
415 }
416
423 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 417 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
424 } 418 }
419
425 return ret; 420 return ret;
426} 421}
427 422
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 5cbf057a1b32..e47e67c11afe 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -20,6 +20,7 @@
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/sysdev.h>
23 24
24#include <asm/hardware.h> 25#include <asm/hardware.h>
25#include <asm/arch/pxa3xx-regs.h> 26#include <asm/arch/pxa3xx-regs.h>
@@ -39,6 +40,7 @@
39#define RO_CLK 60000000 40#define RO_CLK 60000000
40 41
41#define ACCR_D0CS (1 << 26) 42#define ACCR_D0CS (1 << 26)
43#define ACCR_PCCE (1 << 11)
42 44
43/* crystal frequency to static memory controller multiplier (SMCFS) */ 45/* crystal frequency to static memory controller multiplier (SMCFS) */
44static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; 46static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
@@ -203,7 +205,6 @@ static struct clk pxa3xx_clks[] = {
203}; 205};
204 206
205#ifdef CONFIG_PM 207#ifdef CONFIG_PM
206#define SLEEP_SAVE_SIZE 4
207 208
208#define ISRAM_START 0x5c000000 209#define ISRAM_START 0x5c000000
209#define ISRAM_SIZE SZ_256K 210#define ISRAM_SIZE SZ_256K
@@ -211,25 +212,29 @@ static struct clk pxa3xx_clks[] = {
211static void __iomem *sram; 212static void __iomem *sram;
212static unsigned long wakeup_src; 213static unsigned long wakeup_src;
213 214
214static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 215#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
215{ 216#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
216 pr_debug("PM: CKENA=%08x CKENB=%08x\n", CKENA, CKENB);
217 217
218 if (CKENA & (1 << CKEN_USBH)) { 218enum { SLEEP_SAVE_START = 0,
219 printk(KERN_ERR "PM: USB host clock not stopped?\n"); 219 SLEEP_SAVE_CKENA,
220 CKENA &= ~(1 << CKEN_USBH); 220 SLEEP_SAVE_CKENB,
221 } 221 SLEEP_SAVE_ACCR,
222// CKENA |= 1 << (CKEN_ISC & 31);
223 222
224 /* 223 SLEEP_SAVE_SIZE,
225 * Low power modes require the HSIO2 clock to be enabled. 224};
226 */ 225
227 CKENB |= 1 << (CKEN_HSIO2 & 31); 226static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
227{
228 SAVE(CKENA);
229 SAVE(CKENB);
230 SAVE(ACCR);
228} 231}
229 232
230static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) 233static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
231{ 234{
232 CKENB &= ~(1 << (CKEN_HSIO2 & 31)); 235 RESTORE(ACCR);
236 RESTORE(CKENA);
237 RESTORE(CKENB);
233} 238}
234 239
235/* 240/*
@@ -265,6 +270,46 @@ static void pxa3xx_cpu_standby(unsigned int pwrmode)
265 printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR); 270 printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
266} 271}
267 272
273/*
274 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
275 * PXA3xx development kits assumes that the resuming process continues
276 * with the address stored within the first 4 bytes of SDRAM. The PSPR
277 * register is used privately by BootROM and OBM, and _must_ be set to
278 * 0x5c014000 for the moment.
279 */
280static void pxa3xx_cpu_pm_suspend(void)
281{
282 volatile unsigned long *p = (volatile void *)0xc0000000;
283 unsigned long saved_data = *p;
284
285 extern void pxa3xx_cpu_suspend(void);
286 extern void pxa3xx_cpu_resume(void);
287
288 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
289 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
290 CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
291
292 /* clear and setup wakeup source */
293 AD3SR = ~0;
294 AD3ER = wakeup_src;
295 ASCR = ASCR;
296 ARSR = ARSR;
297
298 PCFR |= (1u << 13); /* L1_DIS */
299 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
300
301 PSPR = 0x5c014000;
302
303 /* overwrite with the resume address */
304 *p = virt_to_phys(pxa3xx_cpu_resume);
305
306 pxa3xx_cpu_suspend();
307
308 *p = saved_data;
309
310 AD3ER = 0;
311}
312
268static void pxa3xx_cpu_pm_enter(suspend_state_t state) 313static void pxa3xx_cpu_pm_enter(suspend_state_t state)
269{ 314{
270 /* 315 /*
@@ -279,6 +324,7 @@ static void pxa3xx_cpu_pm_enter(suspend_state_t state)
279 break; 324 break;
280 325
281 case PM_SUSPEND_MEM: 326 case PM_SUSPEND_MEM:
327 pxa3xx_cpu_pm_suspend();
282 break; 328 break;
283 } 329 }
284} 330}
@@ -452,9 +498,21 @@ static struct platform_device *devices[] __initdata = {
452 &pxa3xx_device_ssp4, 498 &pxa3xx_device_ssp4,
453}; 499};
454 500
501static struct sys_device pxa3xx_sysdev[] = {
502 {
503 .id = 0,
504 .cls = &pxa_irq_sysclass,
505 }, {
506 .id = 1,
507 .cls = &pxa_irq_sysclass,
508 }, {
509 .cls = &pxa_gpio_sysclass,
510 },
511};
512
455static int __init pxa3xx_init(void) 513static int __init pxa3xx_init(void)
456{ 514{
457 int ret = 0; 515 int i, ret = 0;
458 516
459 if (cpu_is_pxa3xx()) { 517 if (cpu_is_pxa3xx()) {
460 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); 518 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
@@ -464,9 +522,16 @@ static int __init pxa3xx_init(void)
464 522
465 pxa3xx_init_pm(); 523 pxa3xx_init_pm();
466 524
467 return platform_add_devices(devices, ARRAY_SIZE(devices)); 525 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
526 ret = sysdev_register(&pxa3xx_sysdev[i]);
527 if (ret)
528 pr_err("failed to register sysdev[%d]\n", i);
529 }
530
531 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
468 } 532 }
469 return 0; 533
534 return ret;
470} 535}
471 536
472subsys_initcall(pxa3xx_init); 537subsys_initcall(pxa3xx_init);
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 14bb4a93ea52..784716eb7fc5 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -50,6 +50,108 @@ pxa_cpu_save_sp:
50 str r0, [r1] 50 str r0, [r1]
51 ldr pc, [sp], #4 51 ldr pc, [sp], #4
52 52
53#ifdef CONFIG_PXA3xx
54/*
55 * pxa3xx_cpu_suspend() - forces CPU into sleep state (S2D3C4)
56 *
57 * NOTE: unfortunately, pxa_cpu_save_cp can not be reused here since
58 * the auxiliary control register address is different between pxa3xx
59 * and pxa{25x,27x}
60 */
61
62ENTRY(pxa3xx_cpu_suspend)
63
64#ifndef CONFIG_IWMMXT
65 mra r2, r3, acc0
66#endif
67 stmfd sp!, {r2 - r12, lr} @ save registers on stack
68
69 mrc p14, 0, r3, c6, c0, 0 @ clock configuration, for turbo mode
70 mrc p15, 0, r4, c15, c1, 0 @ CP access reg
71 mrc p15, 0, r5, c13, c0, 0 @ PID
72 mrc p15, 0, r6, c3, c0, 0 @ domain ID
73 mrc p15, 0, r7, c2, c0, 0 @ translation table base addr
74 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
75 mrc p15, 0, r9, c1, c0, 0 @ control reg
76
77 bic r3, r3, #2 @ clear frequency change bit
78
79 @ store them plus current virtual stack ptr on stack
80 mov r10, sp
81 stmfd sp!, {r3 - r10}
82
83 @ store physical address of stack pointer
84 mov r0, sp
85 bl sleep_phys_sp
86 ldr r1, =sleep_save_sp
87 str r0, [r1]
88
89 @ clean data cache
90 bl xsc3_flush_kern_cache_all
91
92 mov r0, #0x06 @ S2D3C4 mode
93 mcr p14, 0, r0, c7, c0, 0 @ enter sleep
94
9520: b 20b @ waiting for sleep
96
97 .data
98 .align 5
99/*
100 * pxa3xx_cpu_resume
101 */
102
103ENTRY(pxa3xx_cpu_resume)
104
105 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
106 msr cpsr_c, r0
107
108 ldr r0, sleep_save_sp @ stack phys addr
109 ldmfd r0, {r3 - r9, sp} @ CP regs + virt stack ptr
110
111 mov r1, #0
112 mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
113 mcr p15, 0, r1, c7, c10, 4 @ drain write (&fill) buffer
114 mcr p15, 0, r1, c7, c5, 4 @ flush prefetch buffer
115 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
116
117 mcr p14, 0, r3, c6, c0, 0 @ clock configuration, turbo mode.
118 mcr p15, 0, r4, c15, c1, 0 @ CP access reg
119 mcr p15, 0, r5, c13, c0, 0 @ PID
120 mcr p15, 0, r6, c3, c0, 0 @ domain ID
121 mcr p15, 0, r7, c2, c0, 0 @ translation table base addr
122 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
123
124 @ temporarily map resume_turn_on_mmu into the page table,
125 @ otherwise prefetch abort occurs after MMU is turned on
126 mov r1, r7
127 bic r1, r1, #0x00ff
128 bic r1, r1, #0x3f00
129 ldr r2, =0x542e
130
131 adr r3, resume_turn_on_mmu
132 mov r3, r3, lsr #20
133 orr r4, r2, r3, lsl #20
134 ldr r5, [r1, r3, lsl #2]
135 str r4, [r1, r3, lsl #2]
136
137 @ Mapping page table address in the page table
138 mov r6, r1, lsr #20
139 orr r7, r2, r6, lsl #20
140 ldr r8, [r1, r6, lsl #2]
141 str r7, [r1, r6, lsl #2]
142
143 ldr r2, =pxa3xx_resume_after_mmu @ absolute virtual address
144 b resume_turn_on_mmu @ cache align execution
145
146 .text
147pxa3xx_resume_after_mmu:
148 /* restore the temporary mapping */
149 str r5, [r1, r3, lsl #2]
150 str r8, [r1, r6, lsl #2]
151 b resume_after_mmu
152
153#endif /* CONFIG_PXA3xx */
154
53#ifdef CONFIG_PXA27x 155#ifdef CONFIG_PXA27x
54/* 156/*
55 * pxa27x_cpu_suspend() 157 * pxa27x_cpu_suspend()
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c
new file mode 100644
index 000000000000..ad346addc028
--- /dev/null
+++ b/arch/arm/mach-pxa/smemc.c
@@ -0,0 +1,88 @@
1/*
2 * Static Memory Controller
3 */
4
5#include <linux/module.h>
6#include <linux/kernel.h>
7#include <linux/init.h>
8#include <linux/io.h>
9#include <linux/sysdev.h>
10
11#define SMEMC_PHYS_BASE (0x4A000000)
12#define SMEMC_PHYS_SIZE (0x90)
13
14#define MSC0 (0x08) /* Static Memory Controller Register 0 */
15#define MSC1 (0x0C) /* Static Memory Controller Register 1 */
16#define SXCNFG (0x1C) /* Synchronous Static Memory Control Register */
17#define MEMCLKCFG (0x68) /* Clock Configuration */
18#define CSADRCFG0 (0x80) /* Address Configuration Register for CS0 */
19#define CSADRCFG1 (0x84) /* Address Configuration Register for CS1 */
20#define CSADRCFG2 (0x88) /* Address Configuration Register for CS2 */
21#define CSADRCFG3 (0x8C) /* Address Configuration Register for CS3 */
22
23#ifdef CONFIG_PM
24static void __iomem *smemc_mmio_base;
25
26static unsigned long msc[2];
27static unsigned long sxcnfg, memclkcfg;
28static unsigned long csadrcfg[4];
29
30static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state)
31{
32 msc[0] = __raw_readl(smemc_mmio_base + MSC0);
33 msc[1] = __raw_readl(smemc_mmio_base + MSC1);
34 sxcnfg = __raw_readl(smemc_mmio_base + SXCNFG);
35 memclkcfg = __raw_readl(smemc_mmio_base + MEMCLKCFG);
36 csadrcfg[0] = __raw_readl(smemc_mmio_base + CSADRCFG0);
37 csadrcfg[1] = __raw_readl(smemc_mmio_base + CSADRCFG1);
38 csadrcfg[2] = __raw_readl(smemc_mmio_base + CSADRCFG2);
39 csadrcfg[3] = __raw_readl(smemc_mmio_base + CSADRCFG3);
40
41 return 0;
42}
43
44static int pxa3xx_smemc_resume(struct sys_device *dev)
45{
46 __raw_writel(msc[0], smemc_mmio_base + MSC0);
47 __raw_writel(msc[1], smemc_mmio_base + MSC1);
48 __raw_writel(sxcnfg, smemc_mmio_base + SXCNFG);
49 __raw_writel(memclkcfg, smemc_mmio_base + MEMCLKCFG);
50 __raw_writel(csadrcfg[0], smemc_mmio_base + CSADRCFG0);
51 __raw_writel(csadrcfg[1], smemc_mmio_base + CSADRCFG1);
52 __raw_writel(csadrcfg[2], smemc_mmio_base + CSADRCFG2);
53 __raw_writel(csadrcfg[3], smemc_mmio_base + CSADRCFG3);
54
55 return 0;
56}
57
58static struct sysdev_class smemc_sysclass = {
59 .name = "smemc",
60 .suspend = pxa3xx_smemc_suspend,
61 .resume = pxa3xx_smemc_resume,
62};
63
64static struct sys_device smemc_sysdev = {
65 .id = 0,
66 .cls = &smemc_sysclass,
67};
68
69static int __init smemc_init(void)
70{
71 int ret = 0;
72
73 if (cpu_is_pxa3xx()) {
74 smemc_mmio_base = ioremap(SMEMC_PHYS_BASE, SMEMC_PHYS_SIZE);
75 if (smemc_mmio_base == NULL)
76 return -ENODEV;
77
78 ret = sysdev_class_register(&smemc_sysclass);
79 if (ret)
80 return ret;
81
82 ret = sysdev_register(&smemc_sysdev);
83 }
84
85 return ret;
86}
87subsys_initcall(smemc_init);
88#endif
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 5078edeadf96..9e7773fca01c 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -36,6 +36,7 @@
36#include <asm/mach/irq.h> 36#include <asm/mach/irq.h>
37 37
38#include <asm/arch/pxa-regs.h> 38#include <asm/arch/pxa-regs.h>
39#include <asm/arch/pxa2xx-regs.h>
39#include <asm/arch/irda.h> 40#include <asm/arch/irda.h>
40#include <asm/arch/mmc.h> 41#include <asm/arch/mmc.h>
41#include <asm/arch/ohci.h> 42#include <asm/arch/ohci.h>
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 1a9c844ac7eb..9b26fa5edad6 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -29,6 +29,7 @@
29#include <asm/irq.h> 29#include <asm/irq.h>
30#include <asm/system.h> 30#include <asm/system.h>
31#include <asm/arch/pxa-regs.h> 31#include <asm/arch/pxa-regs.h>
32#include <asm/arch/pxa2xx-regs.h>
32#include <asm/arch/irda.h> 33#include <asm/arch/irda.h>
33#include <asm/arch/mmc.h> 34#include <asm/arch/mmc.h>
34#include <asm/arch/udc.h> 35#include <asm/arch/udc.h>
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index 35156ca39df7..39b3bb7f1020 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -7,24 +7,21 @@ config MACH_REALVIEW_EB
7 help 7 help
8 Include support for the ARM(R) RealView Emulation Baseboard platform. 8 Include support for the ARM(R) RealView Emulation Baseboard platform.
9 9
10config REALVIEW_MPCORE 10config REALVIEW_EB_ARM11MP
11 bool "Support MPcore tile" 11 bool "Support ARM11MPCore tile"
12 depends on MACH_REALVIEW_EB 12 depends on MACH_REALVIEW_EB
13 select CACHE_L2X0 13 select CACHE_L2X0
14 help 14 help
15 Enable support for the MPCore tile on the Realview platform. 15 Enable support for the ARM11MPCore tile on the Realview platform.
16 Since there are device address and interrupt differences, a
17 kernel built with this option enabled is not compatible with
18 other tiles.
19 16
20config REALVIEW_MPCORE_REVB 17config REALVIEW_EB_ARM11MP_REVB
21 bool "Support MPcore RevB tile" 18 bool "Support ARM11MPCore RevB tile"
22 depends on REALVIEW_MPCORE 19 depends on REALVIEW_EB_ARM11MP
23 default n 20 default n
24 help 21 help
25 Enable support for the MPCore RevB tile on the Realview platform. 22 Enable support for the ARM11MPCore RevB tile on the Realview
26 Since there are device address differences, a 23 platform. Since there are device address differences, a
27 kernel built with this option enabled is not compatible with 24 kernel built with this option enabled is not compatible with
28 other tiles. 25 other revisions of the ARM11MPCore tile.
29 26
30endmenu 27endmenu
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index 36e76ba937fc..ca1e390c3c28 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -4,6 +4,5 @@
4 4
5obj-y := core.o clock.o 5obj-y := core.o clock.o
6obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o 6obj-$(CONFIG_MACH_REALVIEW_EB) += realview_eb.o
7obj-$(CONFIG_SMP) += platsmp.o headsmp.o 7obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o
8obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 8obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
9obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 61d70218f1e8..98aefc9f4df3 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -25,6 +25,8 @@
25#include <linux/interrupt.h> 25#include <linux/interrupt.h>
26#include <linux/amba/bus.h> 26#include <linux/amba/bus.h>
27#include <linux/amba/clcd.h> 27#include <linux/amba/clcd.h>
28#include <linux/clocksource.h>
29#include <linux/clockchips.h>
28 30
29#include <asm/system.h> 31#include <asm/system.h>
30#include <asm/hardware.h> 32#include <asm/hardware.h>
@@ -37,7 +39,6 @@
37#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
38#include <asm/mach/flash.h> 40#include <asm/mach/flash.h>
39#include <asm/mach/irq.h> 41#include <asm/mach/irq.h>
40#include <asm/mach/time.h>
41#include <asm/mach/map.h> 42#include <asm/mach/map.h>
42#include <asm/mach/mmc.h> 43#include <asm/mach/mmc.h>
43 44
@@ -48,6 +49,9 @@
48 49
49#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET) 50#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
50 51
52/* used by entry-macro.S */
53void __iomem *gic_cpu_base_addr;
54
51/* 55/*
52 * This is the RealView sched_clock implementation. This has 56 * This is the RealView sched_clock implementation. This has
53 * a resolution of 41.7ns, and a maximum value of about 179s. 57 * a resolution of 41.7ns, and a maximum value of about 179s.
@@ -121,26 +125,6 @@ struct platform_device realview_flash_device = {
121 .resource = &realview_flash_resource, 125 .resource = &realview_flash_resource,
122}; 126};
123 127
124static struct resource realview_smc91x_resources[] = {
125 [0] = {
126 .start = REALVIEW_ETH_BASE,
127 .end = REALVIEW_ETH_BASE + SZ_64K - 1,
128 .flags = IORESOURCE_MEM,
129 },
130 [1] = {
131 .start = IRQ_ETH,
132 .end = IRQ_ETH,
133 .flags = IORESOURCE_IRQ,
134 },
135};
136
137struct platform_device realview_smc91x_device = {
138 .name = "smc91x",
139 .id = 0,
140 .num_resources = ARRAY_SIZE(realview_smc91x_resources),
141 .resource = realview_smc91x_resources,
142};
143
144static struct resource realview_i2c_resource = { 128static struct resource realview_i2c_resource = {
145 .start = REALVIEW_I2C_BASE, 129 .start = REALVIEW_I2C_BASE,
146 .end = REALVIEW_I2C_BASE + SZ_4K - 1, 130 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
@@ -484,45 +468,64 @@ void realview_leds_event(led_event_t ledevt)
484#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) 468#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
485#endif 469#endif
486 470
487/* 471static void timer_set_mode(enum clock_event_mode mode,
488 * Returns number of ms since last clock interrupt. Note that interrupts 472 struct clock_event_device *clk)
489 * will have been disabled by do_gettimeoffset()
490 */
491static unsigned long realview_gettimeoffset(void)
492{ 473{
493 unsigned long ticks1, ticks2, status; 474 unsigned long ctrl;
494 475
495 /* 476 switch(mode) {
496 * Get the current number of ticks. Note that there is a race 477 case CLOCK_EVT_MODE_PERIODIC:
497 * condition between us reading the timer and checking for 478 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
498 * an interrupt. We get around this by ensuring that the
499 * counter has not reloaded between our two reads.
500 */
501 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
502 do {
503 ticks1 = ticks2;
504 status = __raw_readl(__io_address(REALVIEW_GIC_DIST_BASE + GIC_DIST_PENDING_SET)
505 + ((IRQ_TIMERINT0_1 >> 5) << 2));
506 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
507 } while (ticks2 > ticks1);
508 479
509 /* 480 ctrl = TIMER_CTRL_PERIODIC;
510 * Number of ticks since last interrupt. 481 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
511 */ 482 break;
512 ticks1 = TIMER_RELOAD - ticks2; 483 case CLOCK_EVT_MODE_ONESHOT:
484 /* period set, and timer enabled in 'next_event' hook */
485 ctrl = TIMER_CTRL_ONESHOT;
486 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
487 break;
488 case CLOCK_EVT_MODE_UNUSED:
489 case CLOCK_EVT_MODE_SHUTDOWN:
490 default:
491 ctrl = 0;
492 }
513 493
514 /* 494 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
515 * Interrupt pending? If so, we've reloaded once already. 495}
516 *
517 * FIXME: Need to check this is effectively timer 0 that expires
518 */
519 if (status & IRQMASK_TIMERINT0_1)
520 ticks1 += TIMER_RELOAD;
521 496
522 /* 497static int timer_set_next_event(unsigned long evt,
523 * Convert the ticks to usecs 498 struct clock_event_device *unused)
524 */ 499{
525 return TICKS2USECS(ticks1); 500 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
501
502 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
503 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
504
505 return 0;
506}
507
508static struct clock_event_device timer0_clockevent = {
509 .name = "timer0",
510 .shift = 32,
511 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
512 .set_mode = timer_set_mode,
513 .set_next_event = timer_set_next_event,
514 .rating = 300,
515 .cpumask = CPU_MASK_ALL,
516};
517
518static void __init realview_clockevents_init(unsigned int timer_irq)
519{
520 timer0_clockevent.irq = timer_irq;
521 timer0_clockevent.mult =
522 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
523 timer0_clockevent.max_delta_ns =
524 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
525 timer0_clockevent.min_delta_ns =
526 clockevent_delta2ns(0xf, &timer0_clockevent);
527
528 clockevents_register_device(&timer0_clockevent);
526} 529}
527 530
528/* 531/*
@@ -530,15 +533,12 @@ static unsigned long realview_gettimeoffset(void)
530 */ 533 */
531static irqreturn_t realview_timer_interrupt(int irq, void *dev_id) 534static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
532{ 535{
533 // ...clear the interrupt 536 struct clock_event_device *evt = &timer0_clockevent;
537
538 /* clear the interrupt */
534 writel(1, TIMER0_VA_BASE + TIMER_INTCLR); 539 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
535 540
536 timer_tick(); 541 evt->event_handler(evt);
537
538#if defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
539 smp_send_timer();
540 update_process_times(user_mode(get_irq_regs()));
541#endif
542 542
543 return IRQ_HANDLED; 543 return IRQ_HANDLED;
544} 544}
@@ -549,13 +549,49 @@ static struct irqaction realview_timer_irq = {
549 .handler = realview_timer_interrupt, 549 .handler = realview_timer_interrupt,
550}; 550};
551 551
552static cycle_t realview_get_cycles(void)
553{
554 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
555}
556
557static struct clocksource clocksource_realview = {
558 .name = "timer3",
559 .rating = 200,
560 .read = realview_get_cycles,
561 .mask = CLOCKSOURCE_MASK(32),
562 .shift = 20,
563 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
564};
565
566static void __init realview_clocksource_init(void)
567{
568 /* setup timer 0 as free-running clocksource */
569 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
570 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
571 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
572 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
573 TIMER3_VA_BASE + TIMER_CTRL);
574
575 clocksource_realview.mult =
576 clocksource_khz2mult(1000, clocksource_realview.shift);
577 clocksource_register(&clocksource_realview);
578}
579
552/* 580/*
553 * Set up timer interrupt, and return the current time in seconds. 581 * Set up the clock source and clock events devices
554 */ 582 */
555static void __init realview_timer_init(void) 583void __init realview_timer_init(unsigned int timer_irq)
556{ 584{
557 u32 val; 585 u32 val;
558 586
587#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
588 /*
589 * The dummy clock device has to be registered before the main device
590 * so that the latter will broadcast the clock events
591 */
592 local_timer_setup(smp_processor_id());
593#endif
594
559 /* 595 /*
560 * set clock frequency: 596 * set clock frequency:
561 * REALVIEW_REFCLK is 32KHz 597 * REALVIEW_REFCLK is 32KHz
@@ -576,18 +612,11 @@ static void __init realview_timer_init(void)
576 writel(0, TIMER2_VA_BASE + TIMER_CTRL); 612 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
577 writel(0, TIMER3_VA_BASE + TIMER_CTRL); 613 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
578 614
579 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
580 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
581 writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
582 TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
583
584 /* 615 /*
585 * Make irqs happen for the system timer 616 * Make irqs happen for the system timer
586 */ 617 */
587 setup_irq(IRQ_TIMERINT0_1, &realview_timer_irq); 618 setup_irq(timer_irq, &realview_timer_irq);
588}
589 619
590struct sys_timer realview_timer = { 620 realview_clocksource_init();
591 .init = realview_timer_init, 621 realview_clockevents_init(timer_irq);
592 .offset = realview_gettimeoffset, 622}
593};
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 2b53420f9c1b..492a14c0d604 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -27,8 +27,6 @@
27#include <asm/leds.h> 27#include <asm/leds.h>
28#include <asm/io.h> 28#include <asm/io.h>
29 29
30extern struct sys_timer realview_timer;
31
32#define AMBA_DEVICE(name,busid,base,plat) \ 30#define AMBA_DEVICE(name,busid,base,plat) \
33static struct amba_device name##_device = { \ 31static struct amba_device name##_device = { \
34 .dev = { \ 32 .dev = { \
@@ -38,7 +36,7 @@ static struct amba_device name##_device = { \
38 }, \ 36 }, \
39 .res = { \ 37 .res = { \
40 .start = REALVIEW_##base##_BASE, \ 38 .start = REALVIEW_##base##_BASE, \
41 .end = (REALVIEW_##base##_BASE) + SZ_4K - 1,\ 39 .end = (REALVIEW_##base##_BASE) + SZ_4K - 1, \
42 .flags = IORESOURCE_MEM, \ 40 .flags = IORESOURCE_MEM, \
43 }, \ 41 }, \
44 .dma_mask = ~0, \ 42 .dma_mask = ~0, \
@@ -46,74 +44,19 @@ static struct amba_device name##_device = { \
46 /* .dma = base##_DMA,*/ \ 44 /* .dma = base##_DMA,*/ \
47} 45}
48 46
49/*
50 * These devices are connected via the core APB bridge
51 */
52#define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ }
53#define GPIO2_DMA { 0, 0 }
54#define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ }
55#define GPIO3_DMA { 0, 0 }
56
57#define AACI_IRQ { IRQ_AACI, NO_IRQ }
58#define AACI_DMA { 0x80, 0x81 }
59#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_MMCI0B }
60#define MMCI0_DMA { 0x84, 0 }
61#define KMI0_IRQ { IRQ_KMI0, NO_IRQ }
62#define KMI0_DMA { 0, 0 }
63#define KMI1_IRQ { IRQ_KMI1, NO_IRQ }
64#define KMI1_DMA { 0, 0 }
65
66/*
67 * These devices are connected directly to the multi-layer AHB switch
68 */
69#define SMC_IRQ { NO_IRQ, NO_IRQ }
70#define SMC_DMA { 0, 0 }
71#define MPMC_IRQ { NO_IRQ, NO_IRQ }
72#define MPMC_DMA { 0, 0 }
73#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
74#define CLCD_DMA { 0, 0 }
75#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
76#define DMAC_DMA { 0, 0 }
77
78/*
79 * These devices are connected via the core APB bridge
80 */
81#define SCTL_IRQ { NO_IRQ, NO_IRQ }
82#define SCTL_DMA { 0, 0 }
83#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
84#define WATCHDOG_DMA { 0, 0 }
85#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
86#define GPIO0_DMA { 0, 0 }
87#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
88#define GPIO1_DMA { 0, 0 }
89#define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
90#define RTC_DMA { 0, 0 }
91
92/*
93 * These devices are connected via the DMA APB bridge
94 */
95#define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
96#define SCI_DMA { 7, 6 }
97#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
98#define UART0_DMA { 15, 14 }
99#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
100#define UART1_DMA { 13, 12 }
101#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
102#define UART2_DMA { 11, 10 }
103#define UART3_IRQ { IRQ_UART3, NO_IRQ }
104#define UART3_DMA { 0x86, 0x87 }
105#define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
106#define SSP_DMA { 9, 8 }
107
108
109extern struct platform_device realview_flash_device; 47extern struct platform_device realview_flash_device;
110extern struct platform_device realview_smc91x_device;
111extern struct platform_device realview_i2c_device; 48extern struct platform_device realview_i2c_device;
112extern struct mmc_platform_data realview_mmc0_plat_data; 49extern struct mmc_platform_data realview_mmc0_plat_data;
113extern struct mmc_platform_data realview_mmc1_plat_data; 50extern struct mmc_platform_data realview_mmc1_plat_data;
114extern struct clk realview_clcd_clk; 51extern struct clk realview_clcd_clk;
115extern struct clcd_board clcd_plat_data; 52extern struct clcd_board clcd_plat_data;
53extern void __iomem *gic_cpu_base_addr;
54#ifdef CONFIG_LOCAL_TIMERS
55extern void __iomem *twd_base_addr;
56extern unsigned int twd_size;
57#endif
116 58
117extern void realview_leds_event(led_event_t ledevt); 59extern void realview_leds_event(led_event_t ledevt);
60extern void realview_timer_init(unsigned int timer_irq);
118 61
119#endif 62#endif
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
index c7bdf04ab094..50604360479f 100644
--- a/arch/arm/mach-realview/localtimer.c
+++ b/arch/arm/mach-realview/localtimer.c
@@ -14,19 +14,75 @@
14#include <linux/device.h> 14#include <linux/device.h>
15#include <linux/smp.h> 15#include <linux/smp.h>
16#include <linux/jiffies.h> 16#include <linux/jiffies.h>
17#include <linux/percpu.h>
18#include <linux/clockchips.h>
19#include <linux/irq.h>
17 20
18#include <asm/mach/time.h>
19#include <asm/hardware/arm_twd.h> 21#include <asm/hardware/arm_twd.h>
20#include <asm/hardware/gic.h> 22#include <asm/hardware/gic.h>
21#include <asm/hardware.h> 23#include <asm/hardware.h>
22#include <asm/io.h> 24#include <asm/io.h>
23#include <asm/irq.h> 25#include <asm/irq.h>
24 26
25#define TWD_BASE(cpu) (__io_address(REALVIEW_TWD_BASE) + \ 27static DEFINE_PER_CPU(struct clock_event_device, local_clockevent);
26 ((cpu) * REALVIEW_TWD_SIZE)) 28
29/*
30 * Used on SMP for either the local timer or IPI_TIMER
31 */
32void local_timer_interrupt(void)
33{
34 struct clock_event_device *clk = &__get_cpu_var(local_clockevent);
35
36 clk->event_handler(clk);
37}
38
39#ifdef CONFIG_LOCAL_TIMERS
40
41#define TWD_BASE(cpu) (twd_base_addr + (cpu) * twd_size)
42
43/* set up by the platform code */
44void __iomem *twd_base_addr;
45unsigned int twd_size;
27 46
28static unsigned long mpcore_timer_rate; 47static unsigned long mpcore_timer_rate;
29 48
49static void local_timer_set_mode(enum clock_event_mode mode,
50 struct clock_event_device *clk)
51{
52 void __iomem *base = TWD_BASE(smp_processor_id());
53 unsigned long ctrl;
54
55 switch(mode) {
56 case CLOCK_EVT_MODE_PERIODIC:
57 /* timer load already set up */
58 ctrl = TWD_TIMER_CONTROL_ENABLE | TWD_TIMER_CONTROL_IT_ENABLE
59 | TWD_TIMER_CONTROL_PERIODIC;
60 break;
61 case CLOCK_EVT_MODE_ONESHOT:
62 /* period set, and timer enabled in 'next_event' hook */
63 ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT;
64 break;
65 case CLOCK_EVT_MODE_UNUSED:
66 case CLOCK_EVT_MODE_SHUTDOWN:
67 default:
68 ctrl = 0;
69 }
70
71 __raw_writel(ctrl, base + TWD_TIMER_CONTROL);
72}
73
74static int local_timer_set_next_event(unsigned long evt,
75 struct clock_event_device *unused)
76{
77 void __iomem *base = TWD_BASE(smp_processor_id());
78 unsigned long ctrl = __raw_readl(base + TWD_TIMER_CONTROL);
79
80 __raw_writel(evt, base + TWD_TIMER_COUNTER);
81 __raw_writel(ctrl | TWD_TIMER_CONTROL_ENABLE, base + TWD_TIMER_CONTROL);
82
83 return 0;
84}
85
30/* 86/*
31 * local_timer_ack: checks for a local timer interrupt. 87 * local_timer_ack: checks for a local timer interrupt.
32 * 88 *
@@ -45,12 +101,11 @@ int local_timer_ack(void)
45 return 0; 101 return 0;
46} 102}
47 103
48void __cpuinit local_timer_setup(unsigned int cpu) 104static void __cpuinit twd_calibrate_rate(unsigned int cpu)
49{ 105{
50 void __iomem *base = TWD_BASE(cpu); 106 void __iomem *base = TWD_BASE(cpu);
51 unsigned int load, offset; 107 unsigned long load, count;
52 u64 waitjiffies; 108 u64 waitjiffies;
53 unsigned int count;
54 109
55 /* 110 /*
56 * If this is the first time round, we need to work out how fast 111 * If this is the first time round, we need to work out how fast
@@ -88,36 +143,36 @@ void __cpuinit local_timer_setup(unsigned int cpu)
88 load = mpcore_timer_rate / HZ; 143 load = mpcore_timer_rate / HZ;
89 144
90 __raw_writel(load, base + TWD_TIMER_LOAD); 145 __raw_writel(load, base + TWD_TIMER_LOAD);
91 __raw_writel(0x7, base + TWD_TIMER_CONTROL); 146}
92
93 /*
94 * Now maneuver our local tick into the right part of the jiffy.
95 * Start by working out where within the tick our local timer
96 * interrupt should go.
97 */
98 offset = ((mpcore_timer_rate / HZ) / (NR_CPUS + 1)) * (cpu + 1);
99
100 /*
101 * gettimeoffset() will return a number of us since the last tick.
102 * Convert this number of us to a local timer tick count.
103 * Be careful of integer overflow whilst keeping maximum precision.
104 *
105 * with HZ=100 and 1MHz (fpga) ~ 1GHz processor:
106 * load = 1 ~ 10,000
107 * mpcore_timer_rate/10000 = 100 ~ 100,000
108 *
109 * so the multiply value will be less than 10^9 always.
110 */
111 load = (system_timer->offset() * (mpcore_timer_rate / 10000)) / 100;
112
113 /* Add on our offset to get the load value */
114 load = (load + offset) % (mpcore_timer_rate / HZ);
115 147
116 __raw_writel(load, base + TWD_TIMER_COUNTER); 148/*
149 * Setup the local clock events for a CPU.
150 */
151void __cpuinit local_timer_setup(unsigned int cpu)
152{
153 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
154 unsigned long flags;
155
156 twd_calibrate_rate(cpu);
157
158 clk->name = "local_timer";
159 clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
160 clk->rating = 350;
161 clk->set_mode = local_timer_set_mode;
162 clk->set_next_event = local_timer_set_next_event;
163 clk->irq = IRQ_LOCALTIMER;
164 clk->cpumask = cpumask_of_cpu(cpu);
165 clk->shift = 20;
166 clk->mult = div_sc(mpcore_timer_rate, NSEC_PER_SEC, clk->shift);
167 clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
168 clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
117 169
118 /* Make sure our local interrupt controller has this enabled */ 170 /* Make sure our local interrupt controller has this enabled */
119 __raw_writel(1 << IRQ_LOCALTIMER, 171 local_irq_save(flags);
120 __io_address(REALVIEW_GIC_DIST_BASE) + GIC_DIST_ENABLE_SET); 172 get_irq_chip(IRQ_LOCALTIMER)->unmask(IRQ_LOCALTIMER);
173 local_irq_restore(flags);
174
175 clockevents_register_device(clk);
121} 176}
122 177
123/* 178/*
@@ -127,3 +182,26 @@ void __cpuexit local_timer_stop(unsigned int cpu)
127{ 182{
128 __raw_writel(0, TWD_BASE(cpu) + TWD_TIMER_CONTROL); 183 __raw_writel(0, TWD_BASE(cpu) + TWD_TIMER_CONTROL);
129} 184}
185
186#else /* CONFIG_LOCAL_TIMERS */
187
188static void dummy_timer_set_mode(enum clock_event_mode mode,
189 struct clock_event_device *clk)
190{
191}
192
193void __cpuinit local_timer_setup(unsigned int cpu)
194{
195 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
196
197 clk->name = "dummy_timer";
198 clk->features = CLOCK_EVT_FEAT_DUMMY;
199 clk->rating = 200;
200 clk->set_mode = dummy_timer_set_mode;
201 clk->broadcast = smp_timer_broadcast;
202 clk->cpumask = cpumask_of_cpu(cpu);
203
204 clockevents_register_device(clk);
205}
206
207#endif /* !CONFIG_LOCAL_TIMERS */
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index fce3596f9950..de2b7159557d 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -18,6 +18,7 @@
18#include <asm/hardware/arm_scu.h> 18#include <asm/hardware/arm_scu.h>
19#include <asm/hardware.h> 19#include <asm/hardware.h>
20#include <asm/io.h> 20#include <asm/io.h>
21#include <asm/mach-types.h>
21 22
22extern void realview_secondary_startup(void); 23extern void realview_secondary_startup(void);
23 24
@@ -31,9 +32,13 @@ static unsigned int __init get_core_count(void)
31{ 32{
32 unsigned int ncores; 33 unsigned int ncores;
33 34
34 ncores = __raw_readl(__io_address(REALVIEW_MPCORE_SCU_BASE) + SCU_CONFIG); 35 if (machine_is_realview_eb() && core_tile_eb11mp()) {
36 ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG);
37 ncores = (ncores & 0x03) + 1;
38 } else
39 ncores = 1;
35 40
36 return (ncores & 0x03) + 1; 41 return ncores;
37} 42}
38 43
39static DEFINE_SPINLOCK(boot_lock); 44static DEFINE_SPINLOCK(boot_lock);
@@ -52,7 +57,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
52 * core (e.g. timer irq), then they will not have been enabled 57 * core (e.g. timer irq), then they will not have been enabled
53 * for us: do so 58 * for us: do so
54 */ 59 */
55 gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); 60 gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
56 61
57 /* 62 /*
58 * let the primary processor know we're out of the 63 * let the primary processor know we're out of the
@@ -187,10 +192,15 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
187 if (max_cpus > ncores) 192 if (max_cpus > ncores)
188 max_cpus = ncores; 193 max_cpus = ncores;
189 194
195#ifdef CONFIG_LOCAL_TIMERS
190 /* 196 /*
191 * Enable the local timer for primary CPU 197 * Enable the local timer for primary CPU. If the device is
198 * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
199 * realview_timer_init
192 */ 200 */
193 local_timer_setup(cpu); 201 if (machine_is_realview_eb() && core_tile_eb11mp())
202 local_timer_setup(cpu);
203#endif
194 204
195 /* 205 /*
196 * Initialise the present map, which describes the set of CPUs 206 * Initialise the present map, which describes the set of CPUs
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index ecec2f85c4cd..60d9eb810246 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -36,7 +36,9 @@
36#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
37#include <asm/mach/map.h> 37#include <asm/mach/map.h>
38#include <asm/mach/mmc.h> 38#include <asm/mach/mmc.h>
39#include <asm/mach/time.h>
39 40
41#include <asm/arch/board-eb.h>
40#include <asm/arch/irqs.h> 42#include <asm/arch/irqs.h>
41 43
42#include "core.h" 44#include "core.h"
@@ -58,26 +60,7 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
58 .pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE), 60 .pfn = __phys_to_pfn(REALVIEW_GIC_DIST_BASE),
59 .length = SZ_4K, 61 .length = SZ_4K,
60 .type = MT_DEVICE, 62 .type = MT_DEVICE,
61 },
62#ifdef CONFIG_REALVIEW_MPCORE
63 {
64 .virtual = IO_ADDRESS(REALVIEW_GIC1_CPU_BASE),
65 .pfn = __phys_to_pfn(REALVIEW_GIC1_CPU_BASE),
66 .length = SZ_4K,
67 .type = MT_DEVICE,
68 }, { 63 }, {
69 .virtual = IO_ADDRESS(REALVIEW_GIC1_DIST_BASE),
70 .pfn = __phys_to_pfn(REALVIEW_GIC1_DIST_BASE),
71 .length = SZ_4K,
72 .type = MT_DEVICE,
73 }, {
74 .virtual = IO_ADDRESS(REALVIEW_MPCORE_L220_BASE),
75 .pfn = __phys_to_pfn(REALVIEW_MPCORE_L220_BASE),
76 .length = SZ_8K,
77 .type = MT_DEVICE,
78 },
79#endif
80 {
81 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE), 64 .virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
82 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE), 65 .pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
83 .length = SZ_4K, 66 .length = SZ_4K,
@@ -103,11 +86,95 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
103#endif 86#endif
104}; 87};
105 88
89static struct map_desc realview_eb11mp_io_desc[] __initdata = {
90 {
91 .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE),
92 .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE),
93 .length = SZ_4K,
94 .type = MT_DEVICE,
95 }, {
96 .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE),
97 .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE),
98 .length = SZ_4K,
99 .type = MT_DEVICE,
100 }, {
101 .virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
102 .pfn = __phys_to_pfn(REALVIEW_EB11MP_L220_BASE),
103 .length = SZ_8K,
104 .type = MT_DEVICE,
105 }
106};
107
106static void __init realview_eb_map_io(void) 108static void __init realview_eb_map_io(void)
107{ 109{
108 iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc)); 110 iotable_init(realview_eb_io_desc, ARRAY_SIZE(realview_eb_io_desc));
111 if (core_tile_eb11mp())
112 iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
109} 113}
110 114
115/*
116 * RealView EB AMBA devices
117 */
118
119/*
120 * These devices are connected via the core APB bridge
121 */
122#define GPIO2_IRQ { IRQ_EB_GPIO2, NO_IRQ }
123#define GPIO2_DMA { 0, 0 }
124#define GPIO3_IRQ { IRQ_EB_GPIO3, NO_IRQ }
125#define GPIO3_DMA { 0, 0 }
126
127#define AACI_IRQ { IRQ_EB_AACI, NO_IRQ }
128#define AACI_DMA { 0x80, 0x81 }
129#define MMCI0_IRQ { IRQ_EB_MMCI0A, IRQ_EB_MMCI0B }
130#define MMCI0_DMA { 0x84, 0 }
131#define KMI0_IRQ { IRQ_EB_KMI0, NO_IRQ }
132#define KMI0_DMA { 0, 0 }
133#define KMI1_IRQ { IRQ_EB_KMI1, NO_IRQ }
134#define KMI1_DMA { 0, 0 }
135
136/*
137 * These devices are connected directly to the multi-layer AHB switch
138 */
139#define SMC_IRQ { NO_IRQ, NO_IRQ }
140#define SMC_DMA { 0, 0 }
141#define MPMC_IRQ { NO_IRQ, NO_IRQ }
142#define MPMC_DMA { 0, 0 }
143#define CLCD_IRQ { IRQ_EB_CLCD, NO_IRQ }
144#define CLCD_DMA { 0, 0 }
145#define DMAC_IRQ { IRQ_EB_DMA, NO_IRQ }
146#define DMAC_DMA { 0, 0 }
147
148/*
149 * These devices are connected via the core APB bridge
150 */
151#define SCTL_IRQ { NO_IRQ, NO_IRQ }
152#define SCTL_DMA { 0, 0 }
153#define WATCHDOG_IRQ { IRQ_EB_WDOG, NO_IRQ }
154#define WATCHDOG_DMA { 0, 0 }
155#define GPIO0_IRQ { IRQ_EB_GPIO0, NO_IRQ }
156#define GPIO0_DMA { 0, 0 }
157#define GPIO1_IRQ { IRQ_EB_GPIO1, NO_IRQ }
158#define GPIO1_DMA { 0, 0 }
159#define RTC_IRQ { IRQ_EB_RTC, NO_IRQ }
160#define RTC_DMA { 0, 0 }
161
162/*
163 * These devices are connected via the DMA APB bridge
164 */
165#define SCI_IRQ { IRQ_EB_SCI, NO_IRQ }
166#define SCI_DMA { 7, 6 }
167#define UART0_IRQ { IRQ_EB_UART0, NO_IRQ }
168#define UART0_DMA { 15, 14 }
169#define UART1_IRQ { IRQ_EB_UART1, NO_IRQ }
170#define UART1_DMA { 13, 12 }
171#define UART2_IRQ { IRQ_EB_UART2, NO_IRQ }
172#define UART2_DMA { 11, 10 }
173#define UART3_IRQ { IRQ_EB_UART3, NO_IRQ }
174#define UART3_DMA { 0x86, 0x87 }
175#define SSP_IRQ { IRQ_EB_SSP, NO_IRQ }
176#define SSP_DMA { 9, 8 }
177
111/* FPGA Primecells */ 178/* FPGA Primecells */
112AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); 179AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
113AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data); 180AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &realview_mmc0_plat_data);
@@ -153,38 +220,127 @@ static struct amba_device *amba_devs[] __initdata = {
153 &kmi1_device, 220 &kmi1_device,
154}; 221};
155 222
223/*
224 * RealView EB platform devices
225 */
226
227static struct resource realview_eb_smc91x_resources[] = {
228 [0] = {
229 .start = REALVIEW_ETH_BASE,
230 .end = REALVIEW_ETH_BASE + SZ_64K - 1,
231 .flags = IORESOURCE_MEM,
232 },
233 [1] = {
234 .start = IRQ_EB_ETH,
235 .end = IRQ_EB_ETH,
236 .flags = IORESOURCE_IRQ,
237 },
238};
239
240static struct platform_device realview_eb_smc91x_device = {
241 .name = "smc91x",
242 .id = 0,
243 .num_resources = ARRAY_SIZE(realview_eb_smc91x_resources),
244 .resource = realview_eb_smc91x_resources,
245};
246
156static void __init gic_init_irq(void) 247static void __init gic_init_irq(void)
157{ 248{
158#ifdef CONFIG_REALVIEW_MPCORE 249 if (core_tile_eb11mp()) {
159 unsigned int pldctrl; 250 unsigned int pldctrl;
160 writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK)); 251
161 pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1); 252 /* new irq mode */
162 pldctrl |= 0x00800000; /* New irq mode */ 253 writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
163 writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_MPCORE_SYS_PLD_CTRL1); 254 pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
164 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK)); 255 pldctrl |= 0x00800000;
256 writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_EB11MP_SYS_PLD_CTRL1);
257 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
258
259 /* core tile GIC, primary */
260 gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
261 gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
262 gic_cpu_init(0, gic_cpu_base_addr);
263
264#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
265 /* board GIC, secondary */
266 gic_dist_init(1, __io_address(REALVIEW_GIC_DIST_BASE), 64);
267 gic_cpu_init(1, __io_address(REALVIEW_GIC_CPU_BASE));
268 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
165#endif 269#endif
166 gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29); 270 } else {
167 gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); 271 /* board GIC, primary */
168#if defined(CONFIG_REALVIEW_MPCORE) && !defined(CONFIG_REALVIEW_MPCORE_REVB) 272 gic_cpu_base_addr = __io_address(REALVIEW_GIC_CPU_BASE);
169 gic_dist_init(1, __io_address(REALVIEW_GIC1_DIST_BASE), 64); 273 gic_dist_init(0, __io_address(REALVIEW_GIC_DIST_BASE), 29);
170 gic_cpu_init(1, __io_address(REALVIEW_GIC1_CPU_BASE)); 274 gic_cpu_init(0, gic_cpu_base_addr);
171 gic_cascade_irq(1, IRQ_EB_IRQ1); 275 }
276}
277
278/*
279 * Fix up the IRQ numbers for the RealView EB/ARM11MPCore tile
280 */
281static void realview_eb11mp_fixup(void)
282{
283 /* AMBA devices */
284 dmac_device.irq[0] = IRQ_EB11MP_DMA;
285 uart0_device.irq[0] = IRQ_EB11MP_UART0;
286 uart1_device.irq[0] = IRQ_EB11MP_UART1;
287 uart2_device.irq[0] = IRQ_EB11MP_UART2;
288 uart3_device.irq[0] = IRQ_EB11MP_UART3;
289 clcd_device.irq[0] = IRQ_EB11MP_CLCD;
290 wdog_device.irq[0] = IRQ_EB11MP_WDOG;
291 gpio0_device.irq[0] = IRQ_EB11MP_GPIO0;
292 gpio1_device.irq[0] = IRQ_EB11MP_GPIO1;
293 gpio2_device.irq[0] = IRQ_EB11MP_GPIO2;
294 rtc_device.irq[0] = IRQ_EB11MP_RTC;
295 sci0_device.irq[0] = IRQ_EB11MP_SCI;
296 ssp0_device.irq[0] = IRQ_EB11MP_SSP;
297 aaci_device.irq[0] = IRQ_EB11MP_AACI;
298 mmc0_device.irq[0] = IRQ_EB11MP_MMCI0A;
299 mmc0_device.irq[1] = IRQ_EB11MP_MMCI0B;
300 kmi0_device.irq[0] = IRQ_EB11MP_KMI0;
301 kmi1_device.irq[0] = IRQ_EB11MP_KMI1;
302
303 /* platform devices */
304 realview_eb_smc91x_resources[1].start = IRQ_EB11MP_ETH;
305 realview_eb_smc91x_resources[1].end = IRQ_EB11MP_ETH;
306}
307
308static void __init realview_eb_timer_init(void)
309{
310 unsigned int timer_irq;
311
312 if (core_tile_eb11mp()) {
313#ifdef CONFIG_LOCAL_TIMERS
314 twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE);
315 twd_size = REALVIEW_EB11MP_TWD_SIZE;
172#endif 316#endif
317 timer_irq = IRQ_EB11MP_TIMER0_1;
318 } else
319 timer_irq = IRQ_EB_TIMER0_1;
320
321 realview_timer_init(timer_irq);
173} 322}
174 323
324static struct sys_timer realview_eb_timer = {
325 .init = realview_eb_timer_init,
326};
327
175static void __init realview_eb_init(void) 328static void __init realview_eb_init(void)
176{ 329{
177 int i; 330 int i;
178 331
179#ifdef CONFIG_REALVIEW_MPCORE 332 if (core_tile_eb11mp()) {
180 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled 333 realview_eb11mp_fixup();
181 * Bits: .... ...0 0111 1001 0000 .... .... .... */ 334
182 l2x0_init(__io_address(REALVIEW_MPCORE_L220_BASE), 0x00790000, 0xfe000fff); 335 /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
183#endif 336 * Bits: .... ...0 0111 1001 0000 .... .... .... */
337 l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
338 }
339
184 clk_register(&realview_clcd_clk); 340 clk_register(&realview_clcd_clk);
185 341
186 platform_device_register(&realview_flash_device); 342 platform_device_register(&realview_flash_device);
187 platform_device_register(&realview_smc91x_device); 343 platform_device_register(&realview_eb_smc91x_device);
188 platform_device_register(&realview_i2c_device); 344 platform_device_register(&realview_i2c_device);
189 345
190 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { 346 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
@@ -204,6 +360,6 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
204 .boot_params = 0x00000100, 360 .boot_params = 0x00000100,
205 .map_io = realview_eb_map_io, 361 .map_io = realview_eb_map_io,
206 .init_irq = gic_init_irq, 362 .init_irq = gic_init_irq,
207 .timer = &realview_timer, 363 .timer = &realview_eb_timer,
208 .init_machine = realview_eb_init, 364 .init_machine = realview_eb_init,
209MACHINE_END 365MACHINE_END
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9e13c8358ea7..5c84c604ed86 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -470,7 +470,7 @@ void __init sa1110_mb_disable(void)
470 * If the system is going to use the SA-1111 DMA engines, set up 470 * If the system is going to use the SA-1111 DMA engines, set up
471 * the memory bus request/grant pins. 471 * the memory bus request/grant pins.
472 */ 472 */
473void __init sa1110_mb_enable(void) 473void __devinit sa1110_mb_enable(void)
474{ 474{
475 unsigned long flags; 475 unsigned long flags;
476 476
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index ba3d21d8fba3..6fe481ff4fdf 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -57,8 +57,6 @@ unsigned long iop_gettimeoffset(void)
57static irqreturn_t 57static irqreturn_t
58iop_timer_interrupt(int irq, void *dev_id) 58iop_timer_interrupt(int irq, void *dev_id)
59{ 59{
60 write_seqlock(&xtime_lock);
61
62 write_tisr(1); 60 write_tisr(1);
63 61
64 while ((signed long)(next_jiffy_time - read_tcr1()) 62 while ((signed long)(next_jiffy_time - read_tcr1())
@@ -67,8 +65,6 @@ iop_timer_interrupt(int irq, void *dev_id)
67 next_jiffy_time -= ticks_per_jiffy; 65 next_jiffy_time -= ticks_per_jiffy;
68 } 66 }
69 67
70 write_sequnlock(&xtime_lock);
71
72 return IRQ_HANDLED; 68 return IRQ_HANDLED;
73} 69}
74 70
diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c
index 2ec1daaa0e53..766473b3f98b 100644
--- a/arch/arm/plat-s3c24xx/time.c
+++ b/arch/arm/plat-s3c24xx/time.c
@@ -130,9 +130,7 @@ static unsigned long s3c2410_gettimeoffset (void)
130static irqreturn_t 130static irqreturn_t
131s3c2410_timer_interrupt(int irq, void *dev_id) 131s3c2410_timer_interrupt(int irq, void *dev_id)
132{ 132{
133 write_seqlock(&xtime_lock);
134 timer_tick(); 133 timer_tick();
135 write_sequnlock(&xtime_lock);
136 return IRQ_HANDLED; 134 return IRQ_HANDLED;
137} 135}
138 136
diff --git a/drivers/pcmcia/sa1100_jornada720.c b/drivers/pcmcia/sa1100_jornada720.c
index af485ae38602..6284c35dabc6 100644
--- a/drivers/pcmcia/sa1100_jornada720.c
+++ b/drivers/pcmcia/sa1100_jornada720.c
@@ -101,7 +101,7 @@ static struct pcmcia_low_level jornada720_pcmcia_ops = {
101 .socket_suspend = sa1111_pcmcia_socket_suspend, 101 .socket_suspend = sa1111_pcmcia_socket_suspend,
102}; 102};
103 103
104int __init pcmcia_jornada720_init(struct device *dev) 104int __devinit pcmcia_jornada720_init(struct device *dev)
105{ 105{
106 int ret = -ENODEV; 106 int ret = -ENODEV;
107 107
diff --git a/drivers/serial/21285.c b/drivers/serial/21285.c
index 6a48dfa1efe8..0276471cb25e 100644
--- a/drivers/serial/21285.c
+++ b/drivers/serial/21285.c
@@ -237,6 +237,12 @@ serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
237 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 237 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
238 quot = uart_get_divisor(port, baud); 238 quot = uart_get_divisor(port, baud);
239 239
240 if (port->info && port->info->tty) {
241 struct tty_struct *tty = port->info->tty;
242 unsigned int b = port->uartclk / (16 * quot);
243 tty_encode_baud_rate(tty, b, b);
244 }
245
240 switch (termios->c_cflag & CSIZE) { 246 switch (termios->c_cflag & CSIZE) {
241 case CS5: 247 case CS5:
242 h_lcr = 0x00; 248 h_lcr = 0x00;
@@ -277,8 +283,6 @@ serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
277 if (termios->c_iflag & INPCK) 283 if (termios->c_iflag & INPCK)
278 port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY; 284 port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
279 285
280 tty_encode_baud_rate(tty, baud, baud);
281
282 /* 286 /*
283 * Which character status flags should we ignore? 287 * Which character status flags should we ignore?
284 */ 288 */
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c
index 111da57f5334..60f52904aad0 100644
--- a/drivers/serial/atmel_serial.c
+++ b/drivers/serial/atmel_serial.c
@@ -34,6 +34,7 @@
34#include <linux/tty_flip.h> 34#include <linux/tty_flip.h>
35#include <linux/platform_device.h> 35#include <linux/platform_device.h>
36#include <linux/atmel_pdc.h> 36#include <linux/atmel_pdc.h>
37#include <linux/atmel_serial.h>
37 38
38#include <asm/io.h> 39#include <asm/io.h>
39 40
@@ -45,8 +46,6 @@
45#include <asm/arch/gpio.h> 46#include <asm/arch/gpio.h>
46#endif 47#endif
47 48
48#include "atmel_serial.h"
49
50#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 49#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
51#define SUPPORT_SYSRQ 50#define SUPPORT_SYSRQ
52#endif 51#endif
diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h
index c2e11cc374ba..1551fc24eb43 100644
--- a/include/asm-arm/arch-at91/at91_mci.h
+++ b/include/asm-arm/arch-at91/at91_mci.h
@@ -89,7 +89,7 @@
89#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ 89#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
90#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ 90#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
91#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */ 91#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
92#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */ 92#define AT91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B */
93#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ 93#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
94#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ 94#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
95#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ 95#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h
index 802891a9cd81..e8fc0b1c33f4 100644
--- a/include/asm-arm/arch-at91/at91rm9200.h
+++ b/include/asm-arm/arch-at91/at91rm9200.h
@@ -93,6 +93,11 @@
93#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ 93#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
94#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ 94#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
95 95
96#define AT91_USART0 AT91RM9200_BASE_US0
97#define AT91_USART1 AT91RM9200_BASE_US1
98#define AT91_USART2 AT91RM9200_BASE_US2
99#define AT91_USART3 AT91RM9200_BASE_US3
100
96#define AT91_MATRIX 0 /* not supported */ 101#define AT91_MATRIX 0 /* not supported */
97 102
98/* 103/*
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index 0427f8698c07..c8934fe34dc5 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -99,6 +99,13 @@
99#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 99#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
100#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 100#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
101 101
102#define AT91_USART0 AT91SAM9260_BASE_US0
103#define AT91_USART1 AT91SAM9260_BASE_US1
104#define AT91_USART2 AT91SAM9260_BASE_US2
105#define AT91_USART3 AT91SAM9260_BASE_US3
106#define AT91_USART4 AT91SAM9260_BASE_US4
107#define AT91_USART5 AT91SAM9260_BASE_US5
108
102 109
103/* 110/*
104 * Internal Memory. 111 * Internal Memory.
diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h
index 9eb459570330..c7c4778dac49 100644
--- a/include/asm-arm/arch-at91/at91sam9261.h
+++ b/include/asm-arm/arch-at91/at91sam9261.h
@@ -84,6 +84,10 @@
84#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 84#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
85#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 85#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
86 86
87#define AT91_USART0 AT91SAM9261_BASE_US0
88#define AT91_USART1 AT91SAM9261_BASE_US1
89#define AT91_USART2 AT91SAM9261_BASE_US2
90
87 91
88/* 92/*
89 * Internal Memory. 93 * Internal Memory.
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h
index 115c47ac7ebb..018a647311da 100644
--- a/include/asm-arm/arch-at91/at91sam9263.h
+++ b/include/asm-arm/arch-at91/at91sam9263.h
@@ -101,6 +101,10 @@
101#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) 101#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
102#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 102#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
103 103
104#define AT91_USART0 AT91SAM9263_BASE_US0
105#define AT91_USART1 AT91SAM9263_BASE_US1
106#define AT91_USART2 AT91SAM9263_BASE_US2
107
104#define AT91_SMC AT91_SMC0 108#define AT91_SMC AT91_SMC0
105 109
106/* 110/*
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
index 8a9708a370c6..16d2832f6c0a 100644
--- a/include/asm-arm/arch-at91/at91sam9rl.h
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -94,6 +94,11 @@
94#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 94#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
95#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) 95#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
96 96
97#define AT91_USART0 AT91SAM9RL_BASE_US0
98#define AT91_USART1 AT91SAM9RL_BASE_US1
99#define AT91_USART2 AT91SAM9RL_BASE_US2
100#define AT91_USART3 AT91SAM9RL_BASE_US3
101
97 102
98/* 103/*
99 * Internal Memory. 104 * Internal Memory.
diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h
index 272a7e0dc6cf..f5636a8f6132 100644
--- a/include/asm-arm/arch-at91/uncompress.h
+++ b/include/asm-arm/arch-at91/uncompress.h
@@ -22,7 +22,23 @@
22#define __ASM_ARCH_UNCOMPRESS_H 22#define __ASM_ARCH_UNCOMPRESS_H
23 23
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/arch/at91_dbgu.h> 25#include <linux/atmel_serial.h>
26
27#if defined(CONFIG_AT91_EARLY_DBGU)
28#define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS)
29#elif defined(CONFIG_AT91_EARLY_USART0)
30#define UART_OFFSET AT91_USART0
31#elif defined(CONFIG_AT91_EARLY_USART1)
32#define UART_OFFSET AT91_USART1
33#elif defined(CONFIG_AT91_EARLY_USART2)
34#define UART_OFFSET AT91_USART2
35#elif defined(CONFIG_AT91_EARLY_USART3)
36#define UART_OFFSET AT91_USART3
37#elif defined(CONFIG_AT91_EARLY_USART4)
38#define UART_OFFSET AT91_USART4
39#elif defined(CONFIG_AT91_EARLY_USART5)
40#define UART_OFFSET AT91_USART5
41#endif
26 42
27/* 43/*
28 * The following code assumes the serial port has already been 44 * The following code assumes the serial port has already been
@@ -33,22 +49,22 @@
33 */ 49 */
34static void putc(int c) 50static void putc(int c)
35{ 51{
36#ifdef AT91_DBGU 52#ifdef UART_OFFSET
37 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ 53 void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */
38 54
39 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) 55 while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY))
40 barrier(); 56 barrier();
41 __raw_writel(c, sys + AT91_DBGU_THR); 57 __raw_writel(c, sys + ATMEL_US_THR);
42#endif 58#endif
43} 59}
44 60
45static inline void flush(void) 61static inline void flush(void)
46{ 62{
47#ifdef AT91_DBGU 63#ifdef UART_OFFSET
48 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ 64 void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */
49 65
50 /* wait for transmission to complete */ 66 /* wait for transmission to complete */
51 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) 67 while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
52 barrier(); 68 barrier();
53#endif 69#endif
54} 70}
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
index 66d54119757c..8e1b3ead827f 100644
--- a/include/asm-arm/arch-pxa/pxa3xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -12,6 +12,19 @@
12 12
13#ifndef __ASM_ARCH_PXA3XX_REGS_H 13#ifndef __ASM_ARCH_PXA3XX_REGS_H
14#define __ASM_ARCH_PXA3XX_REGS_H 14#define __ASM_ARCH_PXA3XX_REGS_H
15/*
16 * Service Power Management Unit (MPMU)
17 */
18#define PMCR __REG(0x40F50000) /* Power Manager Control Register */
19#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
20#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
21#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
22#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
23#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
24#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
25#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
26#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
27#define PCMD(x) __REG(0x40F50110 + ((x) << 2))
15 28
16/* 29/*
17 * Slave Power Managment Unit 30 * Slave Power Managment Unit
diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h
new file mode 100644
index 000000000000..3e437b7f425a
--- /dev/null
+++ b/include/asm-arm/arch-realview/board-eb.h
@@ -0,0 +1,171 @@
1/*
2 * include/asm-arm/arch-realview/board-eb.h
3 *
4 * Copyright (C) 2007 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#ifndef __ASM_ARCH_BOARD_EB_H
22#define __ASM_ARCH_BOARD_EB_H
23
24#include <asm/arch/platform.h>
25
26/*
27 * RealView EB + ARM11MPCore peripheral addresses
28 */
29#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
30#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
31#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
32#define REALVIEW_EB11MP_TWD_BASE 0x10100700
33#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
34#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
35#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
36#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
37#else
38#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */
39#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
40#define REALVIEW_EB11MP_TWD_BASE 0x1F000700
41#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
42#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
43#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
44#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
45#endif
46
47#define IRQ_EB_GIC_START 32
48
49/*
50 * RealView EB interrupt sources
51 */
52#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */
53#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */
54#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */
55#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */
56#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */
57#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */
58#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */
59#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */
60#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */
61 /* 9 reserved */
62#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */
63#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */
64#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */
65#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */
66#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */
67#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */
68#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */
69#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */
70#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */
71#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */
72#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */
73#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */
74#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */
75#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */
76#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */
77#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */
78#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */
79#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */
80#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */
81#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */
82#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */
83#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */
84
85/*
86 * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
87 */
88#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0)
89#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1)
90#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2)
91#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3)
92#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4)
93#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5)
94#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6)
95#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7)
96#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8)
97#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9)
98#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */
99#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */
100#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */
101#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */
102#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14)
103#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15)
104
105#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17)
106#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18)
107#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19)
108#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20)
109#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21)
110#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22)
111#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23)
112#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24)
113#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25)
114#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26)
115#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27)
116#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28)
117
118#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29)
119#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30)
120#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31)
121
122#define IRQ_EB11MP_UART2 -1
123#define IRQ_EB11MP_UART3 -1
124#define IRQ_EB11MP_CLCD -1
125#define IRQ_EB11MP_DMA -1
126#define IRQ_EB11MP_WDOG -1
127#define IRQ_EB11MP_GPIO0 -1
128#define IRQ_EB11MP_GPIO1 -1
129#define IRQ_EB11MP_GPIO2 -1
130#define IRQ_EB11MP_SCI -1
131#define IRQ_EB11MP_SSP -1
132
133#define NR_GIC_EB11MP 2
134
135/*
136 * Only define NR_IRQS if less than NR_IRQS_EB
137 */
138#define NR_IRQS_EB (IRQ_EB_GIC_START + 96)
139
140#if defined(CONFIG_MACH_REALVIEW_EB) \
141 && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
142#undef NR_IRQS
143#define NR_IRQS NR_IRQS_EB
144#endif
145
146#if defined(CONFIG_REALVIEW_EB_ARM11MP) \
147 && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
148#undef MAX_GIC_NR
149#define MAX_GIC_NR NR_GIC_EB11MP
150#endif
151
152/*
153 * Core tile identification (REALVIEW_SYS_PROCID)
154 */
155#define REALVIEW_EB_PROC_MASK 0xFF000000
156#define REALVIEW_EB_PROC_ARM7TDMI 0x00000000
157#define REALVIEW_EB_PROC_ARM9 0x02000000
158#define REALVIEW_EB_PROC_ARM11 0x04000000
159#define REALVIEW_EB_PROC_ARM11MP 0x06000000
160
161#define check_eb_proc(proc_type) \
162 ((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \
163 == proc_type)
164
165#ifdef CONFIG_REALVIEW_EB_ARM11MP
166#define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP)
167#else
168#define core_tile_eb11mp() 0
169#endif
170
171#endif /* __ASM_ARCH_BOARD_EB_H */
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
index 3b4e2076603a..cd26306d8e57 100644
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -14,7 +14,8 @@
14 .endm 14 .endm
15 15
16 .macro get_irqnr_preamble, base, tmp 16 .macro get_irqnr_preamble, base, tmp
17 ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) 17 ldr \base, =gic_cpu_base_addr
18 ldr \base, [\base]
18 .endm 19 .endm
19 20
20 .macro arch_ret_to_user, tmp1, tmp2 21 .macro arch_ret_to_user, tmp1, tmp2
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h
index aa78fe087ab2..bad8d7ce9bfe 100644
--- a/include/asm-arm/arch-realview/hardware.h
+++ b/include/asm-arm/arch-realview/hardware.h
@@ -23,7 +23,6 @@
23#define __ASM_ARCH_HARDWARE_H 23#define __ASM_ARCH_HARDWARE_H
24 24
25#include <asm/sizes.h> 25#include <asm/sizes.h>
26#include <asm/arch/platform.h>
27 26
28/* macro to get at IO space when running virtually */ 27/* macro to get at IO space when running virtually */
29#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000) 28#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
index 5a5db56f86b8..ad0c911002fc 100644
--- a/include/asm-arm/arch-realview/irqs.h
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -19,103 +19,18 @@
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21 21
22#include <asm/arch/platform.h> 22#ifndef __ASM_ARCH_IRQS_H
23#define __ASM_ARCH_IRQS_H
23 24
24#define IRQ_LOCALTIMER 29 25#include <asm/arch/board-eb.h>
25#define IRQ_LOCALWDOG 30
26 26
27/* 27#define IRQ_LOCALTIMER 29
28 * IRQ interrupts definitions are the same the INT definitions 28#define IRQ_LOCALWDOG 30
29 * held within platform.h
30 */
31#define IRQ_GIC_START 32
32#define IRQ_WDOGINT (IRQ_GIC_START + INT_WDOGINT)
33#define IRQ_SOFTINT (IRQ_GIC_START + INT_SOFTINT)
34#define IRQ_COMMRx (IRQ_GIC_START + INT_COMMRx)
35#define IRQ_COMMTx (IRQ_GIC_START + INT_COMMTx)
36#define IRQ_TIMERINT0_1 (IRQ_GIC_START + INT_TIMERINT0_1)
37#define IRQ_TIMERINT2_3 (IRQ_GIC_START + INT_TIMERINT2_3)
38#define IRQ_GPIOINT0 (IRQ_GIC_START + INT_GPIOINT0)
39#define IRQ_GPIOINT1 (IRQ_GIC_START + INT_GPIOINT1)
40#define IRQ_GPIOINT2 (IRQ_GIC_START + INT_GPIOINT2)
41#define IRQ_GPIOINT3 (IRQ_GIC_START + INT_GPIOINT3)
42#define IRQ_RTCINT (IRQ_GIC_START + INT_RTCINT)
43#define IRQ_SSPINT (IRQ_GIC_START + INT_SSPINT)
44#define IRQ_UARTINT0 (IRQ_GIC_START + INT_UARTINT0)
45#define IRQ_UARTINT1 (IRQ_GIC_START + INT_UARTINT1)
46#define IRQ_UARTINT2 (IRQ_GIC_START + INT_UARTINT2)
47#define IRQ_UART3 (IRQ_GIC_START + INT_UARTINT3)
48#define IRQ_SCIINT (IRQ_GIC_START + INT_SCIINT)
49#define IRQ_CLCDINT (IRQ_GIC_START + INT_CLCDINT)
50#define IRQ_DMAINT (IRQ_GIC_START + INT_DMAINT)
51#define IRQ_PWRFAILINT (IRQ_GIC_START + INT_PWRFAILINT)
52#define IRQ_MBXINT (IRQ_GIC_START + INT_MBXINT)
53#define IRQ_GNDINT (IRQ_GIC_START + INT_GNDINT)
54#define IRQ_MMCI0B (IRQ_GIC_START + INT_MMCI0B)
55#define IRQ_MMCI1B (IRQ_GIC_START + INT_MMCI1B)
56#define IRQ_KMI0 (IRQ_GIC_START + INT_KMI0)
57#define IRQ_KMI1 (IRQ_GIC_START + INT_KMI1)
58#define IRQ_SCI3 (IRQ_GIC_START + INT_SCI3)
59#define IRQ_CLCD (IRQ_GIC_START + INT_CLCD)
60#define IRQ_TOUCH (IRQ_GIC_START + INT_TOUCH)
61#define IRQ_KEYPAD (IRQ_GIC_START + INT_KEYPAD)
62#define IRQ_DoC (IRQ_GIC_START + INT_DoC)
63#define IRQ_MMCI0A (IRQ_GIC_START + INT_MMCI0A)
64#define IRQ_MMCI1A (IRQ_GIC_START + INT_MMCI1A)
65#define IRQ_AACI (IRQ_GIC_START + INT_AACI)
66#define IRQ_ETH (IRQ_GIC_START + INT_ETH)
67#define IRQ_USB (IRQ_GIC_START + INT_USB)
68#define IRQ_PMU_CPU0 (IRQ_GIC_START + INT_PMU_CPU0)
69#define IRQ_PMU_CPU1 (IRQ_GIC_START + INT_PMU_CPU1)
70#define IRQ_PMU_CPU2 (IRQ_GIC_START + INT_PMU_CPU2)
71#define IRQ_PMU_CPU3 (IRQ_GIC_START + INT_PMU_CPU3)
72#define IRQ_PMU_SCU0 (IRQ_GIC_START + INT_PMU_SCU0)
73#define IRQ_PMU_SCU1 (IRQ_GIC_START + INT_PMU_SCU1)
74#define IRQ_PMU_SCU2 (IRQ_GIC_START + INT_PMU_SCU2)
75#define IRQ_PMU_SCU3 (IRQ_GIC_START + INT_PMU_SCU3)
76#define IRQ_PMU_SCU4 (IRQ_GIC_START + INT_PMU_SCU4)
77#define IRQ_PMU_SCU5 (IRQ_GIC_START + INT_PMU_SCU5)
78#define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6)
79#define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7)
80 29
81#define IRQ_EB_IRQ1 (IRQ_GIC_START + INT_EB_IRQ1) 30#define IRQ_GIC_START 32
82#define IRQ_EB_IRQ2 (IRQ_GIC_START + INT_EB_IRQ2)
83 31
84#define IRQMASK_WDOGINT INTMASK_WDOGINT 32#ifndef NR_IRQS
85#define IRQMASK_SOFTINT INTMASK_SOFTINT 33#error "NR_IRQS not defined by the board-specific files"
86#define IRQMASK_COMMRx INTMASK_COMMRx 34#endif
87#define IRQMASK_COMMTx INTMASK_COMMTx
88#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
89#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
90#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
91#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
92#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
93#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
94#define IRQMASK_RTCINT INTMASK_RTCINT
95#define IRQMASK_SSPINT INTMASK_SSPINT
96#define IRQMASK_UARTINT0 INTMASK_UARTINT0
97#define IRQMASK_UARTINT1 INTMASK_UARTINT1
98#define IRQMASK_UARTINT2 INTMASK_UARTINT2
99#define IRQMASK_SCIINT INTMASK_SCIINT
100#define IRQMASK_CLCDINT INTMASK_CLCDINT
101#define IRQMASK_DMAINT INTMASK_DMAINT
102#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
103#define IRQMASK_MBXINT INTMASK_MBXINT
104#define IRQMASK_GNDINT INTMASK_GNDINT
105#define IRQMASK_MMCI0B INTMASK_MMCI0B
106#define IRQMASK_MMCI1B INTMASK_MMCI1B
107#define IRQMASK_KMI0 INTMASK_KMI0
108#define IRQMASK_KMI1 INTMASK_KMI1
109#define IRQMASK_SCI3 INTMASK_SCI3
110#define IRQMASK_UART3 INTMASK_UART3
111#define IRQMASK_CLCD INTMASK_CLCD
112#define IRQMASK_TOUCH INTMASK_TOUCH
113#define IRQMASK_KEYPAD INTMASK_KEYPAD
114#define IRQMASK_DoC INTMASK_DoC
115#define IRQMASK_MMCI0A INTMASK_MMCI0A
116#define IRQMASK_MMCI1A INTMASK_MMCI1A
117#define IRQMASK_AACI INTMASK_AACI
118#define IRQMASK_ETH INTMASK_ETH
119#define IRQMASK_USB INTMASK_USB
120 35
121#define NR_IRQS (IRQ_GIC_START + 96) 36#endif
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index 6e0eab95a3a2..4fd351b5e4a2 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -18,8 +18,8 @@
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20 20
21#ifndef __address_h 21#ifndef __ASM_ARCH_PLATFORM_H
22#define __address_h 1 22#define __ASM_ARCH_PLATFORM_H
23 23
24/* 24/*
25 * Memory definitions 25 * Memory definitions
@@ -81,11 +81,12 @@
81#define REALVIEW_SYS_24MHz_OFFSET 0x5C 81#define REALVIEW_SYS_24MHz_OFFSET 0x5C
82#define REALVIEW_SYS_MISC_OFFSET 0x60 82#define REALVIEW_SYS_MISC_OFFSET 0x60
83#define REALVIEW_SYS_IOSEL_OFFSET 0x70 83#define REALVIEW_SYS_IOSEL_OFFSET 0x70
84#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80 84#define REALVIEW_SYS_PROCID_OFFSET 0x84
85#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84 85#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
86#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88 86#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
87#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C 87#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
88#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90 88#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
89#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
89 90
90#define REALVIEW_SYS_BASE 0x10000000 91#define REALVIEW_SYS_BASE 0x10000000
91#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) 92#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
@@ -114,6 +115,7 @@
114#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) 115#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
115#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) 116#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
116#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) 117#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
118#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
117#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) 119#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
118#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) 120#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
119#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) 121#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
@@ -203,30 +205,8 @@
203 /* Reserved 0x1001A000 - 0x1001FFFF */ 205 /* Reserved 0x1001A000 - 0x1001FFFF */
204#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ 206#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
205#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ 207#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
206#ifndef CONFIG_REALVIEW_MPCORE
207#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ 208#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
208#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ 209#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
209#else
210#ifdef CONFIG_REALVIEW_MPCORE_REVB
211#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
212#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
213#define REALVIEW_TWD_BASE 0x10100700
214#define REALVIEW_TWD_SIZE 0x00000100
215#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
216#define REALVIEW_MPCORE_L220_BASE 0x10102000 /* L220 registers */
217#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
218#else
219#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */
220#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
221#define REALVIEW_TWD_BASE 0x1F000700
222#define REALVIEW_TWD_SIZE 0x00000100
223#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
224#define REALVIEW_MPCORE_L220_BASE 0x1F002000 /* L220 registers */
225#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
226#endif
227#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
228#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
229#endif
230#define REALVIEW_SMC_BASE 0x10080000 /* SMC */ 210#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
231 /* Reserved 0x10090000 - 0x100EFFFF */ 211 /* Reserved 0x10090000 - 0x100EFFFF */
232 212
@@ -283,134 +263,6 @@
283#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ 263#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
284#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ 264#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
285 265
286/* ------------------------------------------------------------------------
287 * Interrupts - bit assignment (primary)
288 * ------------------------------------------------------------------------
289 */
290#ifndef CONFIG_REALVIEW_MPCORE
291#define INT_WDOGINT 0 /* Watchdog timer */
292#define INT_SOFTINT 1 /* Software interrupt */
293#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
294#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
295#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
296#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
297#define INT_GPIOINT0 6 /* GPIO 0 */
298#define INT_GPIOINT1 7 /* GPIO 1 */
299#define INT_GPIOINT2 8 /* GPIO 2 */
300/* 9 reserved */
301#define INT_RTCINT 10 /* Real Time Clock */
302#define INT_SSPINT 11 /* Synchronous Serial Port */
303#define INT_UARTINT0 12 /* UART 0 on development chip */
304#define INT_UARTINT1 13 /* UART 1 on development chip */
305#define INT_UARTINT2 14 /* UART 2 on development chip */
306#define INT_UARTINT3 15 /* UART 3 on development chip */
307#define INT_SCIINT 16 /* Smart Card Interface */
308#define INT_MMCI0A 17 /* Multimedia Card 0A */
309#define INT_MMCI0B 18 /* Multimedia Card 0B */
310#define INT_AACI 19 /* Audio Codec */
311#define INT_KMI0 20 /* Keyboard/Mouse port 0 */
312#define INT_KMI1 21 /* Keyboard/Mouse port 1 */
313#define INT_CHARLCD 22 /* Character LCD */
314#define INT_CLCDINT 23 /* CLCD controller */
315#define INT_DMAINT 24 /* DMA controller */
316#define INT_PWRFAILINT 25 /* Power failure */
317#define INT_PISMO 26
318#define INT_DoC 27 /* Disk on Chip memory controller */
319#define INT_ETH 28 /* Ethernet controller */
320#define INT_USB 29 /* USB controller */
321#define INT_TSPENINT 30 /* Touchscreen pen */
322#define INT_TSKPADINT 31 /* Touchscreen keypad */
323
324#else
325
326#define MAX_GIC_NR 2
327
328#define INT_AACI 0
329#define INT_TIMERINT0_1 1
330#define INT_TIMERINT2_3 2
331#define INT_USB 3
332#define INT_UARTINT0 4
333#define INT_UARTINT1 5
334#define INT_RTCINT 6
335#define INT_KMI0 7
336#define INT_KMI1 8
337#define INT_ETH 9
338#define INT_EB_IRQ1 10 /* main GIC */
339#define INT_EB_IRQ2 11 /* tile GIC */
340#define INT_EB_FIQ1 12 /* main GIC */
341#define INT_EB_FIQ2 13 /* tile GIC */
342#define INT_MMCI0A 14
343#define INT_MMCI0B 15
344
345#define INT_PMU_CPU0 17
346#define INT_PMU_CPU1 18
347#define INT_PMU_CPU2 19
348#define INT_PMU_CPU3 20
349#define INT_PMU_SCU0 21
350#define INT_PMU_SCU1 22
351#define INT_PMU_SCU2 23
352#define INT_PMU_SCU3 24
353#define INT_PMU_SCU4 25
354#define INT_PMU_SCU5 26
355#define INT_PMU_SCU6 27
356#define INT_PMU_SCU7 28
357
358#define INT_L220_EVENT 29
359#define INT_L220_SLAVE 30
360#define INT_L220_DECODE 31
361
362#define INT_UARTINT2 -1
363#define INT_UARTINT3 -1
364#define INT_CLCDINT -1
365#define INT_DMAINT -1
366#define INT_WDOGINT -1
367#define INT_GPIOINT0 -1
368#define INT_GPIOINT1 -1
369#define INT_GPIOINT2 -1
370#define INT_SCIINT -1
371#define INT_SSPINT -1
372#endif
373
374/*
375 * Interrupt bit positions
376 *
377 */
378#define INTMASK_WDOGINT (1 << INT_WDOGINT)
379#define INTMASK_SOFTINT (1 << INT_SOFTINT)
380#define INTMASK_COMMRx (1 << INT_COMMRx)
381#define INTMASK_COMMTx (1 << INT_COMMTx)
382#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
383#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
384#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
385#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
386#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
387#define INTMASK_RTCINT (1 << INT_RTCINT)
388#define INTMASK_SSPINT (1 << INT_SSPINT)
389#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
390#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
391#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
392#define INTMASK_UARTINT3 (1 << INT_UARTINT3)
393#define INTMASK_SCIINT (1 << INT_SCIINT)
394#define INTMASK_MMCI0A (1 << INT_MMCI0A)
395#define INTMASK_MMCI0B (1 << INT_MMCI0B)
396#define INTMASK_AACI (1 << INT_AACI)
397#define INTMASK_KMI0 (1 << INT_KMI0)
398#define INTMASK_KMI1 (1 << INT_KMI1)
399#define INTMASK_CHARLCD (1 << INT_CHARLCD)
400#define INTMASK_CLCDINT (1 << INT_CLCDINT)
401#define INTMASK_DMAINT (1 << INT_DMAINT)
402#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
403#define INTMASK_PISMO (1 << INT_PISMO)
404#define INTMASK_DoC (1 << INT_DoC)
405#define INTMASK_ETH (1 << INT_ETH)
406#define INTMASK_USB (1 << INT_USB)
407#define INTMASK_TSPENINT (1 << INT_TSPENINT)
408#define INTMASK_TSKPADINT (1 << INT_TSKPADINT)
409
410#define MAXIRQNUM 31
411#define MAXFIQNUM 31
412#define MAXSWINUM 31
413
414/* 266/*
415 * Application Flash 267 * Application Flash
416 * 268 *
@@ -463,6 +315,4 @@
463#define REALVIEW_CSR_BASE 0x10000000 315#define REALVIEW_CSR_BASE 0x10000000
464#define REALVIEW_CSR_SIZE 0x10000000 316#define REALVIEW_CSR_SIZE 0x10000000
465 317
466#endif 318#endif /* __ASM_ARCH_PLATFORM_H */
467
468/* END */
diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h
index cc293640178e..08b3db883c36 100644
--- a/include/asm-arm/arch-realview/scu.h
+++ b/include/asm-arm/arch-realview/scu.h
@@ -1,8 +1,8 @@
1#ifndef __ASMARM_ARCH_SCU_H 1#ifndef __ASMARM_ARCH_SCU_H
2#define __ASMARM_ARCH_SCU_H 2#define __ASMARM_ARCH_SCU_H
3 3
4#include <asm/arch/platform.h> 4#include <asm/arch/board-eb.h>
5 5
6#define SCU_BASE REALVIEW_MPCORE_SCU_BASE 6#define SCU_BASE REALVIEW_EB11MP_SCU_BASE
7 7
8#endif 8#endif
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
index f05631d76743..3d5c2db07a26 100644
--- a/include/asm-arm/arch-realview/uncompress.h
+++ b/include/asm-arm/arch-realview/uncompress.h
@@ -19,6 +19,8 @@
19 */ 19 */
20#include <asm/hardware.h> 20#include <asm/hardware.h>
21 21
22#include <asm/arch/platform.h>
23
22#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00)) 24#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
23#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c)) 25#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
24#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30)) 26#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
diff --git a/include/asm-arm/hardware/arm_twd.h b/include/asm-arm/hardware/arm_twd.h
index 131d5b40e072..e521b70713c8 100644
--- a/include/asm-arm/hardware/arm_twd.h
+++ b/include/asm-arm/hardware/arm_twd.h
@@ -1,7 +1,7 @@
1#ifndef __ASM_HARDWARE_TWD_H 1#ifndef __ASM_HARDWARE_TWD_H
2#define __ASM_HARDWARE_TWD_H 2#define __ASM_HARDWARE_TWD_H
3 3
4#define TWD_TIMER_LOAD 0x00 4#define TWD_TIMER_LOAD 0x00
5#define TWD_TIMER_COUNTER 0x04 5#define TWD_TIMER_COUNTER 0x04
6#define TWD_TIMER_CONTROL 0x08 6#define TWD_TIMER_CONTROL 0x08
7#define TWD_TIMER_INTSTAT 0x0C 7#define TWD_TIMER_INTSTAT 0x0C
@@ -13,4 +13,9 @@
13#define TWD_WDOG_RESETSTAT 0x30 13#define TWD_WDOG_RESETSTAT 0x30
14#define TWD_WDOG_DISABLE 0x34 14#define TWD_WDOG_DISABLE 0x34
15 15
16#define TWD_TIMER_CONTROL_ENABLE (1 << 0)
17#define TWD_TIMER_CONTROL_ONESHOT (0 << 1)
18#define TWD_TIMER_CONTROL_PERIODIC (1 << 1)
19#define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2)
20
16#endif 21#endif
diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h
index 46dcc4d0b9bd..1ee17b6951d0 100644
--- a/include/asm-arm/kexec.h
+++ b/include/asm-arm/kexec.h
@@ -16,6 +16,9 @@
16 16
17#define KEXEC_BOOT_PARAMS_SIZE 1536 17#define KEXEC_BOOT_PARAMS_SIZE 1536
18 18
19#define KEXEC_ARM_ATAGS_OFFSET 0x1000
20#define KEXEC_ARM_ZIMAGE_OFFSET 0x8000
21
19#ifndef __ASSEMBLY__ 22#ifndef __ASSEMBLY__
20 23
21struct kimage; 24struct kimage;
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index f67acce387e7..af99636db400 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -61,6 +61,11 @@ extern void smp_cross_call(cpumask_t callmap);
61extern void smp_send_timer(void); 61extern void smp_send_timer(void);
62 62
63/* 63/*
64 * Broadcast a clock event to other CPUs.
65 */
66extern void smp_timer_broadcast(cpumask_t mask);
67
68/*
64 * Boot a secondary CPU, and assign it the specified idle task. 69 * Boot a secondary CPU, and assign it the specified idle task.
65 * This also gives us the initial stack to use for this CPU. 70 * This also gives us the initial stack to use for this CPU.
66 */ 71 */
@@ -96,11 +101,12 @@ extern void platform_cpu_die(unsigned int cpu);
96extern int platform_cpu_kill(unsigned int cpu); 101extern int platform_cpu_kill(unsigned int cpu);
97extern void platform_cpu_enable(unsigned int cpu); 102extern void platform_cpu_enable(unsigned int cpu);
98 103
99#ifdef CONFIG_LOCAL_TIMERS
100/* 104/*
101 * Setup a local timer interrupt for a CPU. 105 * Local timer interrupt handling function (can be IPI'ed).
102 */ 106 */
103extern void local_timer_setup(unsigned int cpu); 107extern void local_timer_interrupt(void);
108
109#ifdef CONFIG_LOCAL_TIMERS
104 110
105/* 111/*
106 * Stop a local timer interrupt. 112 * Stop a local timer interrupt.
@@ -114,10 +120,6 @@ extern int local_timer_ack(void);
114 120
115#else 121#else
116 122
117static inline void local_timer_setup(unsigned int cpu)
118{
119}
120
121static inline void local_timer_stop(unsigned int cpu) 123static inline void local_timer_stop(unsigned int cpu)
122{ 124{
123} 125}
@@ -125,6 +127,11 @@ static inline void local_timer_stop(unsigned int cpu)
125#endif 127#endif
126 128
127/* 129/*
130 * Setup a local timer interrupt for a CPU.
131 */
132extern void local_timer_setup(unsigned int cpu);
133
134/*
128 * show local interrupt info 135 * show local interrupt info
129 */ 136 */
130extern void show_local_irqs(struct seq_file *); 137extern void show_local_irqs(struct seq_file *);
diff --git a/drivers/serial/atmel_serial.h b/include/linux/atmel_serial.h
index e0141776517c..fd6833764d72 100644
--- a/drivers/serial/atmel_serial.h
+++ b/include/linux/atmel_serial.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * drivers/serial/atmel_serial.h 2 * include/linux/atmel_serial.h
3 * 3 *
4 * Copyright (C) 2005 Ivan Kokshaysky 4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People 5 * Copyright (C) SAN People
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 10:54:11 -0400