120 files changed, 22494 insertions, 8062 deletions

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 3f886e298f62..ab95d3ada5c7 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -1787,6 +1787,11 @@ and is between 256 and 4096 characters. It is defined in the file
                         waiting for the ACK, so if this is set too high
                         interrupts *may* be lost!
 
+        omap_mux=       [OMAP] Override bootloader pin multiplexing.
+                        Format: <mux_mode0.mode_name=value>...
+                        For example, to override I2C bus2:
+                        omap_mux=i2c2_scl.i2c2_scl=0x100,i2c2_sda.i2c2_sda=0x100
+
         opl3=           [HW,OSS]
                         Format: <io>
 
diff --git a/arch/arm/configs/htcherald_defconfig b/arch/arm/configs/htcherald_defconfig
index 338267674075..1b39691b816f 100644
--- a/arch/arm/configs/htcherald_defconfig
+++ b/arch/arm/configs/htcherald_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32-rc6
-# Sat Nov 14 10:56:01 2009
+# Linux kernel version: 2.6.32-rc8
+# Sat Dec  5 12:16:24 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -198,7 +198,9 @@ CONFIG_ARCH_OMAP1=y
 # OMAP Feature Selections
 #
 # CONFIG_OMAP_RESET_CLOCKS is not set
-# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MUX=y
+# CONFIG_OMAP_MUX_DEBUG is not set
+CONFIG_OMAP_MUX_WARNINGS=y
 CONFIG_OMAP_MCBSP=y
 # CONFIG_OMAP_MBOX_FWK is not set
 CONFIG_OMAP_MPU_TIMER=y
@@ -207,6 +209,7 @@ CONFIG_OMAP_LL_DEBUG_UART1=y
 # CONFIG_OMAP_LL_DEBUG_UART2 is not set
 # CONFIG_OMAP_LL_DEBUG_UART3 is not set
 # CONFIG_OMAP_LL_DEBUG_NONE is not set
+CONFIG_OMAP_SERIAL_WAKE=y
 # CONFIG_OMAP_PM_NONE is not set
 CONFIG_OMAP_PM_NOOP=y
 
diff --git a/arch/arm/configs/omap3_touchbook_defconfig b/arch/arm/configs/omap3_touchbook_defconfig
new file mode 100644
index 000000000000..7c8515e65c02
--- /dev/null
+++ b/arch/arm/configs/omap3_touchbook_defconfig
@@ -0,0 +1,2431 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc8
+# Fri Dec  4 16:02:17 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_BCMRING is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+# CONFIG_ARCH_OMAP4 is not set
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MCBSP=y
+# CONFIG_OMAP_MBOX_FWK is not set
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+# CONFIG_OMAP_LL_DEBUG_NONE is not set
+# CONFIG_OMAP_PM_NONE is not set
+CONFIG_OMAP_PM_NOOP=y
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OVERO is not set
+# CONFIG_MACH_OMAP3EVM is not set
+# CONFIG_MACH_OMAP3517EVM is not set
+# CONFIG_MACH_OMAP3_PANDORA is not set
+CONFIG_MACH_OMAP3_TOUCHBOOK=y
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_NOKIA_RX51 is not set
+# CONFIG_MACH_OMAP_ZOOM2 is not set
+# CONFIG_MACH_OMAP_ZOOM3 is not set
+# CONFIG_MACH_CM_T35 is not set
+# CONFIG_MACH_IGEP0020 is not set
+# CONFIG_MACH_OMAP_3630SDP is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=128
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" debug "
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_VERBOSE is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+# CONFIG_DEFAULT_BIC is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=m
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+# CONFIG_IPV6_PIMSM_V2 is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+# CONFIG_NETFILTER_TPROXY is not set
+CONFIG_NETFILTER_XTABLES=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+CONFIG_NETFILTER_XT_TARGET_HL=m
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+CONFIG_IP_VS_DEBUG=y
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+CONFIG_IP_VS_FTP=m
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_DCCP=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+CONFIG_IP_DCCP=m
+CONFIG_INET_DCCP_DIAG=m
+
+#
+# DCCP CCIDs Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=y
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_CCID3_RTO=100
+CONFIG_IP_DCCP_TFRC_LIB=y
+
+#
+# DCCP Kernel Hacking
+#
+# CONFIG_IP_DCCP_DEBUG is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_RDS is not set
+CONFIG_TIPC=m
+# CONFIG_TIPC_ADVANCED is not set
+# CONFIG_TIPC_DEBUG is not set
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+# CONFIG_ATM_CLIP_NO_ICMP is not set
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+# CONFIG_ATM_BR2684_IPFILTER is not set
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+CONFIG_WAN_ROUTER=m
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_FLOW=m
+# CONFIG_NET_EMATCH is not set
+# CONFIG_NET_CLS_ACT is not set
+CONFIG_NET_CLS_IND=y
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=y
+CONFIG_BT_HCIBTSDIO=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIBCM203X=y
+CONFIG_BT_HCIBPA10X=y
+CONFIG_BT_HCIBFUSB=y
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+CONFIG_AF_RXRPC=m
+# CONFIG_AF_RXRPC_DEBUG is not set
+# CONFIG_RXKAD is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211_DEFAULT_PS_VALUE=1
+# CONFIG_CFG80211_DEBUGFS is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=y
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_RC_PID=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
+CONFIG_MAC80211_RC_DEFAULT="pid"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_WIMAX=m
+CONFIG_WIMAX_DEBUG_LEVEL=8
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_OMAP_PREFETCH=y
+# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_CDROM_PKTCDVD_BUFFERS=8
+# CONFIG_CDROM_PKTCDVD_WCACHE is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+CONFIG_EEPROM_93CX6=y
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=m
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+CONFIG_ISCSI_TCP=m
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID6_PQ=m
+# CONFIG_ASYNC_RAID6_TEST is not set
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+# CONFIG_DM_LOG_USERSPACE is not set
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+# CONFIG_DM_MULTIPATH_QL is not set
+# CONFIG_DM_MULTIPATH_ST is not set
+CONFIG_DM_DELAY=m
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+CONFIG_BONDING=m
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+CONFIG_TUN=m
+CONFIG_VETH=m
+# CONFIG_NET_ETHERNET is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_LIBERTAS is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_ATH_COMMON is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_WL12XX is not set
+# CONFIG_IWM is not set
+
+#
+# WiMAX Wireless Broadband devices
+#
+# CONFIG_WIMAX_I2400M_USB is not set
+# CONFIG_WIMAX_I2400M_SDIO is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_ATM_DRIVERS is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOATM is not set
+CONFIG_PPPOL2TP=m
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_TWL4030 is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_TWL4030_PWRBUTTON=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_OMAP24XX=y
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+CONFIG_BATTERY_BQ27x00=y
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+# CONFIG_TWL4030_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_TWL4030_POWER is not set
+# CONFIG_TWL4030_CODEC is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+CONFIG_REGULATOR_TWL4030=y
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_OMAP is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_JACK=y
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_RAWMIDI_SEQ=m
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_OXU210HP_HCD=y
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SOC=y
+
+#
+# OMAP 343x high speed USB support
+#
+# CONFIG_USB_MUSB_HOST is not set
+# CONFIG_USB_MUSB_PERIPHERAL is not set
+CONFIG_USB_MUSB_OTG=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_MUSB_HDRC_HCD=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_USB_INVENTRA_DMA=y
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_MUSB_DEBUG is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+CONFIG_USB_WDM=m
+CONFIG_USB_TMC=m
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_AIRCABLE=m
+CONFIG_USB_SERIAL_ARK3116=m
+CONFIG_USB_SERIAL_BELKIN=m
+CONFIG_USB_SERIAL_CH341=m
+CONFIG_USB_SERIAL_WHITEHEAT=m
+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
+# CONFIG_USB_SERIAL_CP210X is not set
+CONFIG_USB_SERIAL_CYPRESS_M8=m
+CONFIG_USB_SERIAL_EMPEG=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_FUNSOFT=m
+CONFIG_USB_SERIAL_VISOR=m
+CONFIG_USB_SERIAL_IPAQ=m
+CONFIG_USB_SERIAL_IR=m
+CONFIG_USB_SERIAL_EDGEPORT=m
+CONFIG_USB_SERIAL_EDGEPORT_TI=m
+CONFIG_USB_SERIAL_GARMIN=m
+CONFIG_USB_SERIAL_IPW=m
+CONFIG_USB_SERIAL_IUU=m
+CONFIG_USB_SERIAL_KEYSPAN_PDA=m
+CONFIG_USB_SERIAL_KEYSPAN=m
+CONFIG_USB_SERIAL_KEYSPAN_MPR=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19=y
+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
+CONFIG_USB_SERIAL_KLSI=m
+CONFIG_USB_SERIAL_KOBIL_SCT=m
+CONFIG_USB_SERIAL_MCT_U232=m
+CONFIG_USB_SERIAL_MOS7720=m
+CONFIG_USB_SERIAL_MOS7840=m
+CONFIG_USB_SERIAL_MOTOROLA=m
+CONFIG_USB_SERIAL_NAVMAN=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_OTI6858=m
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+CONFIG_USB_SERIAL_SPCP8X5=m
+CONFIG_USB_SERIAL_HP4X=m
+CONFIG_USB_SERIAL_SAFE=m
+# CONFIG_USB_SERIAL_SAFE_PADDED is not set
+CONFIG_USB_SERIAL_SIEMENS_MPI=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+# CONFIG_USB_SERIAL_SYMBOL is not set
+CONFIG_USB_SERIAL_TI=m
+CONFIG_USB_SERIAL_CYBERJACK=m
+CONFIG_USB_SERIAL_XIRCOM=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_SERIAL_OMNINET=m
+CONFIG_USB_SERIAL_OPTICON=m
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+CONFIG_USB_SISUSBVGA=m
+CONFIG_USB_SISUSBVGA_CON=y
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_ATM is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ZERO_HNPTEST=y
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+CONFIG_USB_GPIO_VBUS=y
+# CONFIG_ISP1301_OMAP is not set
+CONFIG_TWL4030_USB=y
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_OMAP is not set
+CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+CONFIG_UIO_PDRV=m
+CONFIG_UIO_PDRV_GENIRQ=m
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+
+#
+# TI VLYNQ
+#
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_USB_IP_COMMON is not set
+# CONFIG_W35UND is not set
+# CONFIG_PRISM2_USB is not set
+# CONFIG_ECHO is not set
+# CONFIG_OTUS is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_INPUT_GPIO is not set
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_PLAN9AUTH is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_USB_SERIAL_QUATECH2 is not set
+# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_FB_UDL is not set
+
+#
+# RAR Register Driver
+#
+# CONFIG_RAR_REGISTER is not set
+# CONFIG_IIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=m
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=m
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=m
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+CONFIG_REISERFS_PROC_INFO=y
+CONFIG_REISERFS_FS_XATTR=y
+# CONFIG_REISERFS_FS_POSIX_ACL is not set
+# CONFIG_REISERFS_FS_SECURITY is not set
+CONFIG_JFS_FS=m
+# CONFIG_JFS_POSIX_ACL is not set
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+# CONFIG_JFFS2_CMODE_PRIORITY is not set
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_CMODE_FAVOURLZO=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS=y
+CONFIG_CIFS_STATS2=y
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+CONFIG_CIFS_EXPERIMENTAL=y
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_FIPS=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index a464ca332a23..2319113c86bf 100644
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -1,26 +1,29 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc7
-# Tue Jun  9 12:36:23 2009
+# Linux kernel version: 2.6.32
+# Sun Dec  6 23:37:45 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_LOCKBREAK=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -39,11 +42,12 @@ CONFIG_BSD_PROCESS_ACCT=y
 #
 # RCU Subsystem
 #
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
 # CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_GROUP_SCHED=y
@@ -52,8 +56,7 @@ CONFIG_FAIR_GROUP_SCHED=y
 CONFIG_USER_SCHED=y
 # CONFIG_CGROUP_SCHED is not set
 # CONFIG_CGROUPS is not set
-# CONFIG_SYSFS_DEPRECATED=y is not set
-# CONFIG_SYSFS_DEPRECATED_V2=y is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -70,7 +73,6 @@ CONFIG_UID16=y
 CONFIG_KALLSYMS=y
 # CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
@@ -83,6 +85,10 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
 CONFIG_COMPAT_BRK=y
@@ -90,13 +96,16 @@ CONFIG_COMPAT_BRK=y
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_USE_GENERIC_SMP_HELPERS=y
 CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
 # CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
@@ -110,7 +119,7 @@ CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_STOP_MACHINE=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -131,6 +140,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 #
 # System Type
 #
+CONFIG_MMU=y
 # CONFIG_ARCH_AAEC2000 is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_REALVIEW is not set
@@ -142,8 +152,10 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -166,10 +178,13 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_DAVINCI is not set
 CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_BCMRING is not set
 
 #
 # TI OMAP Implementations
@@ -190,9 +205,12 @@ CONFIG_ARCH_OMAP4=y
 CONFIG_OMAP_32K_TIMER=y
 CONFIG_OMAP_32K_TIMER_HZ=128
 CONFIG_OMAP_DM_TIMER=y
-CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART1 is not set
 # CONFIG_OMAP_LL_DEBUG_UART2 is not set
-# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+CONFIG_OMAP_LL_DEBUG_UART3=y
+# CONFIG_OMAP_LL_DEBUG_NONE is not set
+# CONFIG_OMAP_PM_NONE is not set
+CONFIG_OMAP_PM_NOOP=y
 
 #
 # OMAP Board Type
@@ -207,7 +225,7 @@ CONFIG_CPU_32v6K=y
 CONFIG_CPU_V7=y
 CONFIG_CPU_32v7=y
 CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_PABRT_V7=y
 CONFIG_CPU_CACHE_V7=y
 CONFIG_CPU_CACHE_VIPT=y
 CONFIG_CPU_COPY_V6=y
@@ -222,9 +240,10 @@ CONFIG_CPU_CP15_MMU=y
 # CONFIG_ARM_THUMB is not set
 # CONFIG_ARM_THUMBEE is not set
 # CONFIG_CPU_ICACHE_DISABLE is not set
-CONFIG_CPU_DCACHE_DISABLE=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_HAS_TLS_REG=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
 # CONFIG_ARM_ERRATA_430973 is not set
 # CONFIG_ARM_ERRATA_458693 is not set
 # CONFIG_ARM_ERRATA_460075 is not set
@@ -245,18 +264,20 @@ CONFIG_ARM_GIC=y
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 CONFIG_SMP=y
 CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
 CONFIG_VMSPLIT_3G=y
 # CONFIG_VMSPLIT_2G is not set
 # CONFIG_VMSPLIT_1G is not set
 CONFIG_PAGE_OFFSET=0xC0000000
 CONFIG_NR_CPUS=2
 # CONFIG_HOTPLUG_CPU is not set
-CONFIG_LOCAL_TIMERS=y
-# CONFIG_PREEMPT is not set
+# CONFIG_LOCAL_TIMERS is not set
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
 CONFIG_HZ=128
+# CONFIG_THUMB2_KERNEL is not set
 CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
+CONFIG_OABI_COMPAT=y
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 # CONFIG_HIGHMEM is not set
@@ -271,10 +292,13 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-# CONFIG_UNEVICTABLE_LRU is not set
 CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 
 #
 # Boot options
@@ -298,9 +322,11 @@ CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600
 #
 # At least one emulation must be selected
 #
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
 CONFIG_VFP=y
 CONFIG_VFPv3=y
-# CONFIG_NEON is not set
+CONFIG_NEON=y
 
 #
 # Userspace binary formats
@@ -325,6 +351,7 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
@@ -342,6 +369,7 @@ CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=16384
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MG_DISK is not set
 # CONFIG_MISC_DEVICES is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
@@ -355,6 +383,7 @@ CONFIG_HAVE_IDE=y
 # CONFIG_SCSI_NETLINK is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
+# CONFIG_PHONE is not set
 
 #
 # Input device support
@@ -427,6 +456,11 @@ CONFIG_HW_RANDOM=y
 # CONFIG_TCG_TPM is not set
 # CONFIG_I2C is not set
 # CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
@@ -447,11 +481,14 @@ CONFIG_GPIOLIB=y
 #
 # SPI GPIO expanders:
 #
+
+#
+# AC97 GPIO expanders:
+#
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -472,21 +509,8 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_T7L66XB is not set
 # CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-CONFIG_DAB=y
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -511,14 +535,17 @@ CONFIG_DUMMY_CONSOLE=y
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
 # CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
-# CONFIG_REGULATOR is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
@@ -535,9 +562,12 @@ CONFIG_JBD=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -601,7 +631,6 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 
 #
 # Partition Types
@@ -673,23 +702,24 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_DETECT_SOFTLOCKUP is not set
 CONFIG_DETECT_HUNG_TASK=y
 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
 CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHED_DEBUG is not set
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_SLUB_DEBUG_ON is not set
 # CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -708,31 +738,22 @@ CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_PAGE_POISONING is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_TRACING_SUPPORT=y
-
-#
-# Tracers
-#
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_EVENT_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_FTRACE is not set
+# CONFIG_BRANCH_PROFILE_NONE is not set
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
@@ -754,7 +775,6 @@ CONFIG_CRYPTO=y
 #
 # Crypto core or helper
 #
-# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD2=y
@@ -796,11 +816,13 @@ CONFIG_CRYPTO_PCBC=m
 #
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
 CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_MICHAEL_MIC is not set
diff --git a/arch/arm/configs/omap_zoom2_defconfig b/arch/arm/configs/omap_zoom2_defconfig
index eef93627fb13..4b00a4306812 100644
--- a/arch/arm/configs/omap_zoom2_defconfig
+++ b/arch/arm/configs/omap_zoom2_defconfig
@@ -610,7 +610,8 @@ CONFIG_INPUT_EVDEV=y
 #
 # Input Device Drivers
 #
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_TWL4030=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
diff --git a/arch/arm/configs/omap_zoom3_defconfig b/arch/arm/configs/omap_zoom3_defconfig
index f0e7d0f85582..0d7e37a3651b 100644
--- a/arch/arm/configs/omap_zoom3_defconfig
+++ b/arch/arm/configs/omap_zoom3_defconfig
@@ -629,7 +629,8 @@ CONFIG_INPUT_EVDEV=y
 #
 # Input Device Drivers
 #
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_TWL4030=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 87e539aa8ad9..9ce17f13d3f1 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,8 @@
 #
 
 # Common support
-obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o
+obj-y := io.o id.o sram.o irq.o mux.o serial.o devices.o
+obj-y += clock.o clock_data.o opp_data.o
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
@@ -17,6 +18,9 @@ obj-$(CONFIG_PM) += pm.o sleep.o
 obj-$(CONFIG_OMAP_MBOX_FWK)     += mailbox_mach.o
 mailbox_mach-objs               := mailbox.o
 
+i2c-omap-$(CONFIG_I2C_OMAP)             := i2c.o
+obj-y                                   += $(i2c-omap-m) $(i2c-omap-y)
+
 led-y := leds.o
 
 # Specific board support
@@ -48,3 +52,7 @@ led-$(CONFIG_MACH_OMAP_INNOVATOR)	+= leds-innovator.o
 led-$(CONFIG_MACH_OMAP_PERSEUS2)        += leds-h2p2-debug.o
 led-$(CONFIG_MACH_OMAP_OSK)             += leds-osk.o
 obj-$(CONFIG_LEDS)                      += $(led-y)
+
+ifneq ($(CONFIG_FB_OMAP),)
+obj-y += lcd_dma.o
+endif
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index f4b72c1654f5..7e70c3c08da6 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -19,6 +19,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/input.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -30,7 +31,6 @@
 #include <mach/gpio.h>
 #include <plat/mux.h>
 #include <plat/fpga.h>
-#include <plat/nand.h>
 #include <plat/keypad.h>
 #include <plat/common.h>
 #include <plat/board.h>
@@ -100,6 +100,12 @@ static int fsample_keymap[] = {
         0
 };
 
+static struct smc91x_platdata smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource smc91x_resources[] = {
         [0] = {
                 .start  = H2P2_DBG_FPGA_ETHR_START,     /* Physical */
@@ -167,8 +173,40 @@ static struct platform_device nor_device = {
         .resource       = &nor_resource,
 };
 
-static struct omap_nand_platform_data nand_data = {
-        .options        = NAND_SAMSUNG_LP_OPTIONS,
+static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long mask;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
+        if (ctrl & NAND_ALE)
+                mask |= 0x04;
+        writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
+}
+
+#define FSAMPLE_NAND_RB_GPIO_PIN        62
+
+static int nand_dev_ready(struct mtd_info *mtd)
+{
+        return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
+}
+
+static const char *part_probes[] = { "cmdlinepart", NULL };
+
+static struct platform_nand_data nand_data = {
+        .chip   = {
+                .nr_chips               = 1,
+                .chip_offset            = 0,
+                .options                = NAND_SAMSUNG_LP_OPTIONS,
+                .part_probe_types       = part_probes,
+        },
+        .ctrl   = {
+                .cmd_ctrl       = nand_cmd_ctl,
+                .dev_ready      = nand_dev_ready,
+        },
 };
 
 static struct resource nand_resource = {
@@ -178,7 +216,7 @@ static struct resource nand_resource = {
 };
 
 static struct platform_device nand_device = {
-        .name           = "omapnand",
+        .name           = "gen_nand",
         .id             = 0,
         .dev            = {
                 .platform_data  = &nand_data,
@@ -190,6 +228,9 @@ static struct platform_device nand_device = {
 static struct platform_device smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(smc91x_resources),
         .resource       = smc91x_resources,
 };
@@ -233,13 +274,6 @@ static struct platform_device *devices[] __initdata = {
         &lcd_device,
 };
 
-#define P2_NAND_RB_GPIO_PIN     62
-
-static int nand_dev_ready(struct omap_nand_platform_data *data)
-{
-        return gpio_get_value(P2_NAND_RB_GPIO_PIN);
-}
-
 static struct omap_lcd_config fsample_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
@@ -250,9 +284,9 @@ static struct omap_board_config_kernel fsample_config[] = {
 
 static void __init omap_fsample_init(void)
 {
-        if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
+        if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
                 BUG();
-        nand_data.dev_ready = nand_dev_ready;
+        gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
 
         omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
         omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 89ba8ec4bbf4..fa7cecea19f9 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -28,6 +28,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/input.h>
 #include <linux/i2c/tps65010.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 #include <asm/gpio.h>
@@ -40,7 +41,6 @@
 #include <plat/mux.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
-#include <plat/nand.h>
 #include <plat/irda.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
@@ -179,11 +179,43 @@ static struct mtd_partition h2_nand_partitions[] = {
         },
 };
 
-/* dip switches control NAND chip access:  8 bit, 16 bit, or neither */
-static struct omap_nand_platform_data h2_nand_data = {
-        .options        = NAND_SAMSUNG_LP_OPTIONS,
-        .parts          = h2_nand_partitions,
-        .nr_parts       = ARRAY_SIZE(h2_nand_partitions),
+static void h2_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long mask;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
+        if (ctrl & NAND_ALE)
+                mask |= 0x04;
+        writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
+}
+
+#define H2_NAND_RB_GPIO_PIN     62
+
+static int h2_nand_dev_ready(struct mtd_info *mtd)
+{
+        return gpio_get_value(H2_NAND_RB_GPIO_PIN);
+}
+
+static const char *h2_part_probes[] = { "cmdlinepart", NULL };
+
+struct platform_nand_data h2_nand_platdata = {
+        .chip   = {
+                .nr_chips               = 1,
+                .chip_offset            = 0,
+                .nr_partitions          = ARRAY_SIZE(h2_nand_partitions),
+                .partitions             = h2_nand_partitions,
+                .options                = NAND_SAMSUNG_LP_OPTIONS,
+                .part_probe_types       = h2_part_probes,
+        },
+        .ctrl   = {
+                .cmd_ctrl       = h2_nand_cmd_ctl,
+                .dev_ready      = h2_nand_dev_ready,
+
+        },
 };
 
 static struct resource h2_nand_resource = {
@@ -191,15 +223,21 @@ static struct resource h2_nand_resource = {
 };
 
 static struct platform_device h2_nand_device = {
-        .name           = "omapnand",
+        .name           = "gen_nand",
         .id             = 0,
         .dev            = {
-                .platform_data  = &h2_nand_data,
+                .platform_data  = &h2_nand_platdata,
         },
         .num_resources  = 1,
         .resource       = &h2_nand_resource,
 };
 
+static struct smc91x_platdata h2_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource h2_smc91x_resources[] = {
         [0] = {
                 .start  = OMAP1610_ETHR_START,          /* Physical */
@@ -216,6 +254,9 @@ static struct resource h2_smc91x_resources[] = {
 static struct platform_device h2_smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &h2_smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(h2_smc91x_resources),
         .resource       = h2_smc91x_resources,
 };
@@ -368,8 +409,6 @@ static struct omap_board_config_kernel h2_config[] __initdata = {
         { OMAP_TAG_LCD,         &h2_lcd_config },
 };
 
-#define H2_NAND_RB_GPIO_PIN     62
-
 static void __init h2_init(void)
 {
         /* Here we assume the NOR boot config:  NOR on CS3 (possibly swapped
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index f5cc0a730524..6a7f9c391cf1 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -28,6 +28,7 @@
 #include <linux/input.h>
 #include <linux/spi/spi.h>
 #include <linux/i2c/tps65010.h>
+#include <linux/smc91x.h>
 
 #include <asm/setup.h>
 #include <asm/page.h>
@@ -42,7 +43,6 @@
 #include <mach/irqs.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
-#include <plat/nand.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
 #include <plat/dma.h>
@@ -181,11 +181,43 @@ static struct mtd_partition nand_partitions[] = {
         },
 };
 
-/* dip switches control NAND chip access:  8 bit, 16 bit, or neither */
-static struct omap_nand_platform_data nand_data = {
-        .options        = NAND_SAMSUNG_LP_OPTIONS,
-        .parts          = nand_partitions,
-        .nr_parts       = ARRAY_SIZE(nand_partitions),
+static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long mask;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
+        if (ctrl & NAND_ALE)
+                mask |= 0x04;
+        writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
+}
+
+#define H3_NAND_RB_GPIO_PIN     10
+
+static int nand_dev_ready(struct mtd_info *mtd)
+{
+        return gpio_get_value(H3_NAND_RB_GPIO_PIN);
+}
+
+static const char *part_probes[] = { "cmdlinepart", NULL };
+
+struct platform_nand_data nand_platdata = {
+        .chip   = {
+                .nr_chips               = 1,
+                .chip_offset            = 0,
+                .nr_partitions          = ARRAY_SIZE(nand_partitions),
+                .partitions             = nand_partitions,
+                .options                = NAND_SAMSUNG_LP_OPTIONS,
+                .part_probe_types       = part_probes,
+        },
+        .ctrl   = {
+                .cmd_ctrl       = nand_cmd_ctl,
+                .dev_ready      = nand_dev_ready,
+
+        },
 };
 
 static struct resource nand_resource = {
@@ -193,15 +225,21 @@ static struct resource nand_resource = {
 };
 
 static struct platform_device nand_device = {
-        .name           = "omapnand",
+        .name           = "gen_nand",
         .id             = 0,
         .dev            = {
-                .platform_data  = &nand_data,
+                .platform_data  = &nand_platdata,
         },
         .num_resources  = 1,
         .resource       = &nand_resource,
 };
 
+static struct smc91x_platdata smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource smc91x_resources[] = {
         [0] = {
                 .start  = OMAP1710_ETHR_START,          /* Physical */
@@ -218,6 +256,9 @@ static struct resource smc91x_resources[] = {
 static struct platform_device smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(smc91x_resources),
         .resource       = smc91x_resources,
 };
@@ -332,13 +373,6 @@ static struct i2c_board_info __initdata h3_i2c_board_info[] = {
         },
 };
 
-#define H3_NAND_RB_GPIO_PIN     10
-
-static int nand_dev_ready(struct omap_nand_platform_data *data)
-{
-        return gpio_get_value(H3_NAND_RB_GPIO_PIN);
-}
-
 static void __init h3_init(void)
 {
         /* Here we assume the NOR boot config:  NOR on CS3 (possibly swapped
@@ -356,7 +390,7 @@ static void __init h3_init(void)
         nand_resource.end += SZ_4K - 1;
         if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0)
                 BUG();
-        nand_data.dev_ready = nand_dev_ready;
+        gpio_direction_input(H3_NAND_RB_GPIO_PIN);
 
         /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
         /* GPIO10 pullup/down register, Enable pullup on GPIO10 */
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 5f28a5ceacac..e36639f66150 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -39,6 +39,7 @@
 #include <plat/common.h>
 #include <plat/board.h>
 #include <plat/keypad.h>
+#include <plat/usb.h>
 
 #include <mach/irqs.h>
 
@@ -140,6 +141,15 @@ static struct platform_device kp_device = {
         .resource       = kp_resources,
 };
 
+/* USB Device */
+static struct omap_usb_config htcherald_usb_config __initdata = {
+        .otg = 0,
+        .register_host = 0,
+        .register_dev  = 1,
+        .hmc_mode = 4,
+        .pins[0] = 2,
+};
+
 /* LCD Device resources */
 static struct platform_device lcd_device = {
         .name           = "lcd_htcherald",
@@ -214,6 +224,57 @@ static void __init htcherald_disable_watchdog(void)
         }
 }
 
+#define HTCHERALD_GPIO_USB_EN1 33
+#define HTCHERALD_GPIO_USB_EN2 73
+#define HTCHERALD_GPIO_USB_DM  35
+#define HTCHERALD_GPIO_USB_DP  36
+
+static void __init htcherald_usb_enable(void)
+{
+        unsigned int tries = 20;
+        unsigned int value = 0;
+
+        /* Request the GPIOs we need to control here */
+        if (gpio_request(HTCHERALD_GPIO_USB_EN1, "herald_usb") < 0)
+                goto err1;
+
+        if (gpio_request(HTCHERALD_GPIO_USB_EN2, "herald_usb") < 0)
+                goto err2;
+
+        if (gpio_request(HTCHERALD_GPIO_USB_DM, "herald_usb") < 0)
+                goto err3;
+
+        if (gpio_request(HTCHERALD_GPIO_USB_DP, "herald_usb") < 0)
+                goto err4;
+
+        /* force USB_EN GPIO to 0 */
+        do {
+                /* output low */
+                gpio_direction_output(HTCHERALD_GPIO_USB_EN1, 0);
+        } while ((value = gpio_get_value(HTCHERALD_GPIO_USB_EN1)) == 1 &&
+                        --tries);
+
+        if (value == 1)
+                printk(KERN_WARNING "Unable to reset USB, trying to continue\n");
+
+        gpio_direction_output(HTCHERALD_GPIO_USB_EN2, 0); /* output low */
+        gpio_direction_input(HTCHERALD_GPIO_USB_DM); /* input */
+        gpio_direction_input(HTCHERALD_GPIO_USB_DP); /* input */
+
+        goto done;
+
+err4:
+        gpio_free(HTCHERALD_GPIO_USB_DM);
+err3:
+        gpio_free(HTCHERALD_GPIO_USB_EN2);
+err2:
+        gpio_free(HTCHERALD_GPIO_USB_EN1);
+err1:
+        printk(KERN_ERR "Unabled to request GPIO for USB\n");
+done:
+        printk(KERN_INFO "USB setup complete.\n");
+}
+
 static void __init htcherald_init(void)
 {
         printk(KERN_INFO "HTC Herald init.\n");
@@ -225,6 +286,9 @@ static void __init htcherald_init(void)
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         htcherald_disable_watchdog();
+
+        htcherald_usb_enable();
+        omap_usb_init(&htcherald_usb_config);
 }
 
 static void __init htcherald_init_irq(void)
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index cf0fdb9c182f..2133b006f6a3 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -23,6 +23,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/input.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -142,6 +143,11 @@ static struct platform_device innovator_kp_device = {
         .resource       = innovator_kp_resources,
 };
 
+static struct smc91x_platdata innovator_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
 
 #ifdef CONFIG_ARCH_OMAP15XX
 
@@ -175,6 +181,9 @@ static struct resource innovator1510_smc91x_resources[] = {
 static struct platform_device innovator1510_smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &innovator_smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(innovator1510_smc91x_resources),
         .resource       = innovator1510_smc91x_resources,
 };
@@ -241,6 +250,9 @@ static struct resource innovator1610_smc91x_resources[] = {
 static struct platform_device innovator1610_smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &innovator_smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(innovator1610_smc91x_resources),
         .resource       = innovator1610_smc91x_resources,
 };
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 50c92c13e48a..ccea4f448e9a 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -33,6 +33,7 @@
 #include <linux/irq.h>
 #include <linux/i2c.h>
 #include <linux/leds.h>
+#include <linux/smc91x.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -115,6 +116,12 @@ static struct platform_device osk5912_flash_device = {
         .resource       = &osk_flash_resource,
 };
 
+static struct smc91x_platdata osk5912_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource osk5912_smc91x_resources[] = {
         [0] = {
                 .start  = OMAP_OSK_ETHR_START,          /* Physical */
@@ -131,6 +138,9 @@ static struct resource osk5912_smc91x_resources[] = {
 static struct platform_device osk5912_smc91x_device = {
         .name           = "smc91x",
         .id             = -1,
+        .dev    = {
+                .platform_data  = &osk5912_smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(osk5912_smc91x_resources),
         .resource       = osk5912_smc91x_resources,
 };
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index ca7df1e93efc..1387a4f15da9 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -19,6 +19,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/input.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -30,7 +31,6 @@
 #include <mach/gpio.h>
 #include <plat/mux.h>
 #include <plat/fpga.h>
-#include <plat/nand.h>
 #include <plat/keypad.h>
 #include <plat/common.h>
 #include <plat/board.h>
@@ -67,6 +67,12 @@ static int p2_keymap[] = {
         0
 };
 
+static struct smc91x_platdata smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource smc91x_resources[] = {
         [0] = {
                 .start  = H2P2_DBG_FPGA_ETHR_START,     /* Physical */
@@ -134,8 +140,40 @@ static struct platform_device nor_device = {
         .resource       = &nor_resource,
 };
 
-static struct omap_nand_platform_data nand_data = {
-        .options        = NAND_SAMSUNG_LP_OPTIONS,
+static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long mask;
+
+        if (cmd == NAND_CMD_NONE)
+                return;
+
+        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
+        if (ctrl & NAND_ALE)
+                mask |= 0x04;
+        writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
+}
+
+#define P2_NAND_RB_GPIO_PIN     62
+
+static int nand_dev_ready(struct mtd_info *mtd)
+{
+        return gpio_get_value(P2_NAND_RB_GPIO_PIN);
+}
+
+static const char *part_probes[] = { "cmdlinepart", NULL };
+
+static struct platform_nand_data nand_data = {
+        .chip   = {
+                .nr_chips               = 1,
+                .chip_offset            = 0,
+                .options                = NAND_SAMSUNG_LP_OPTIONS,
+                .part_probe_types       = part_probes,
+        },
+        .ctrl   = {
+                .cmd_ctrl       = nand_cmd_ctl,
+                .dev_ready      = nand_dev_ready,
+        },
 };
 
 static struct resource nand_resource = {
@@ -145,7 +183,7 @@ static struct resource nand_resource = {
 };
 
 static struct platform_device nand_device = {
-        .name           = "omapnand",
+        .name           = "gen_nand",
         .id             = 0,
         .dev            = {
                 .platform_data  = &nand_data,
@@ -157,6 +195,9 @@ static struct platform_device nand_device = {
 static struct platform_device smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(smc91x_resources),
         .resource       = smc91x_resources,
 };
@@ -201,13 +242,6 @@ static struct platform_device *devices[] __initdata = {
         &lcd_device,
 };
 
-#define P2_NAND_RB_GPIO_PIN     62
-
-static int nand_dev_ready(struct omap_nand_platform_data *data)
-{
-        return gpio_get_value(P2_NAND_RB_GPIO_PIN);
-}
-
 static struct omap_lcd_config perseus2_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
@@ -220,7 +254,7 @@ static void __init omap_perseus2_init(void)
 {
         if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
                 BUG();
-        nand_data.dev_ready = nand_dev_ready;
+        gpio_direction_input(P2_NAND_RB_GPIO_PIN);
 
         omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
         omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 35c75c1bd0aa..169183537997 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -22,6 +22,7 @@
 #include <linux/reboot.h>
 #include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -106,6 +107,12 @@ static struct platform_device voiceblue_flash_device = {
         .resource       = &voiceblue_flash_resource,
 };
 
+static struct smc91x_platdata voiceblue_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource voiceblue_smc91x_resources[] = {
         [0] = {
                 .start  = OMAP_CS2_PHYS + 0x300,
@@ -122,6 +129,9 @@ static struct resource voiceblue_smc91x_resources[] = {
 static struct platform_device voiceblue_smc91x_device = {
         .name           = "smc91x",
         .id             = 0,
+        .dev    = {
+                .platform_data  = &voiceblue_smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(voiceblue_smc91x_resources),
         .resource       = voiceblue_smc91x_resources,
 };
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 42cbe203da36..2ba9ab953731 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/mach-omap1/clock.c
  *
- *  Copyright (C) 2004 - 2005 Nokia corporation
+ *  Copyright (C) 2004 - 2005, 2009 Nokia corporation
  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  *
  *  Modified to use omap shared clock framework by
@@ -26,12 +26,17 @@
 #include <plat/usb.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
-
-static const struct clkops clkops_generic;
-static const struct clkops clkops_uart;
-static const struct clkops clkops_dspck;
+#include <plat/clkdev_omap.h>
 
 #include "clock.h"
+#include "opp.h"
+
+__u32 arm_idlect1_mask;
+struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
+
+/*-------------------------------------------------------------------------
+ * Omap1 specific clock functions
+ *-------------------------------------------------------------------------*/
 
 static int clk_omap1_dummy_enable(struct clk *clk)
 {
@@ -42,134 +47,24 @@ static void clk_omap1_dummy_disable(struct clk *clk)
 {
 }
 
-static const struct clkops clkops_dummy = {
-        .enable = clk_omap1_dummy_enable,
-        .disable = clk_omap1_dummy_disable,
-};
-
-static struct clk dummy_ck = {
-        .name   = "dummy",
-        .ops    = &clkops_dummy,
-        .flags  = RATE_FIXED,
-};
-
-struct omap_clk {
-        u32             cpu;
-        struct clk_lookup lk;
+const struct clkops clkops_dummy = {
+        .enable         = clk_omap1_dummy_enable,
+        .disable        = clk_omap1_dummy_disable,
 };
 
-#define CLK(dev, con, ck, cp)           \
-        {                               \
-                 .cpu = cp,             \
-                .lk = {                 \
-                        .dev_id = dev,  \
-                        .con_id = con,  \
-                        .clk = ck,      \
-                },                      \
-        }
-
-#define CK_310  (1 << 0)
-#define CK_7XX  (1 << 1)
-#define CK_1510 (1 << 2)
-#define CK_16XX (1 << 3)
-
-static struct omap_clk omap_clks[] = {
-        /* non-ULPD clocks */
-        CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
-        CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
-        /* CK_GEN1 clocks */
-        CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
-        CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
-        CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
-        CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
-        CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
-        CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
-        CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
-        CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
-        CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
-        CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
-        /* CK_GEN2 clocks */
-        CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
-        /* CK_GEN3 clocks */
-        CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
-        CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
-        CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX | CK_7XX),
-        CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
-        CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
-        CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
-        CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
-        CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
-        CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
-        CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
-        CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
-        /* ULPD clocks */
-        CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
-        CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
-        CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
-        CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
-        CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
-        CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
-        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
-        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
-        CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
-        CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
-        CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
-        CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
-        CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
-        CLK("mmci-omap.0", "fck",       &mmc3_ck,       CK_7XX),
-        CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
-        CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
-        CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
-        /* Virtual clocks */
-        CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
-        CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310),
-        CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
-        CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310),
-        CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
-        CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
-        CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
-        CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
-        CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
-        CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
-        CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
-        CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
-        CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
-        CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
-};
-
-static int omap1_clk_enable_generic(struct clk * clk);
-static int omap1_clk_enable(struct clk *clk);
-static void omap1_clk_disable_generic(struct clk * clk);
-static void omap1_clk_disable(struct clk *clk);
-
-__u32 arm_idlect1_mask;
-
-/*-------------------------------------------------------------------------
- * Omap1 specific clock functions
- *-------------------------------------------------------------------------*/
-
-static unsigned long omap1_watchdog_recalc(struct clk *clk)
+/* XXX can be replaced with a fixed_divisor_recalc */
+unsigned long omap1_watchdog_recalc(struct clk *clk)
 {
         return clk->parent->rate / 14;
 }
 
-static unsigned long omap1_uart_recalc(struct clk *clk)
+unsigned long omap1_uart_recalc(struct clk *clk)
 {
         unsigned int val = __raw_readl(clk->enable_reg);
         return val & clk->enable_bit ? 48000000 : 12000000;
 }
 
-static unsigned long omap1_sossi_recalc(struct clk *clk)
+unsigned long omap1_sossi_recalc(struct clk *clk)
 {
         u32 div = omap_readl(MOD_CONF_CTRL_1);
 
@@ -179,64 +74,6 @@ static unsigned long omap1_sossi_recalc(struct clk *clk)
         return clk->parent->rate / div;
 }
 
-static int omap1_clk_enable_dsp_domain(struct clk *clk)
-{
-        int retval;
-
-        retval = omap1_clk_enable(&api_ck.clk);
-        if (!retval) {
-                retval = omap1_clk_enable_generic(clk);
-                omap1_clk_disable(&api_ck.clk);
-        }
-
-        return retval;
-}
-
-static void omap1_clk_disable_dsp_domain(struct clk *clk)
-{
-        if (omap1_clk_enable(&api_ck.clk) == 0) {
-                omap1_clk_disable_generic(clk);
-                omap1_clk_disable(&api_ck.clk);
-        }
-}
-
-static const struct clkops clkops_dspck = {
-        .enable         = &omap1_clk_enable_dsp_domain,
-        .disable        = &omap1_clk_disable_dsp_domain,
-};
-
-static int omap1_clk_enable_uart_functional(struct clk *clk)
-{
-        int ret;
-        struct uart_clk *uclk;
-
-        ret = omap1_clk_enable_generic(clk);
-        if (ret == 0) {
-                /* Set smart idle acknowledgement mode */
-                uclk = (struct uart_clk *)clk;
-                omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
-                            uclk->sysc_addr);
-        }
-
-        return ret;
-}
-
-static void omap1_clk_disable_uart_functional(struct clk *clk)
-{
-        struct uart_clk *uclk;
-
-        /* Set force idle acknowledgement mode */
-        uclk = (struct uart_clk *)clk;
-        omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
-
-        omap1_clk_disable_generic(clk);
-}
-
-static const struct clkops clkops_uart = {
-        .enable         = &omap1_clk_enable_uart_functional,
-        .disable        = &omap1_clk_disable_uart_functional,
-};
-
 static void omap1_clk_allow_idle(struct clk *clk)
 {
         struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
@@ -344,7 +181,7 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
         return dsor_exp;
 }
 
-static unsigned long omap1_ckctl_recalc(struct clk *clk)
+unsigned long omap1_ckctl_recalc(struct clk *clk)
 {
         /* Calculate divisor encoded as 2-bit exponent */
         int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
@@ -352,7 +189,7 @@ static unsigned long omap1_ckctl_recalc(struct clk *clk)
         return clk->parent->rate / dsor;
 }
 
-static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
+unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
 {
         int dsor;
 
@@ -363,28 +200,29 @@ static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
          * Note that DSP_CKCTL virt addr = phys addr, so
          * we must use __raw_readw() instead of omap_readw().
          */
-        omap1_clk_enable(&api_ck.clk);
+        omap1_clk_enable(api_ck_p);
         dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
-        omap1_clk_disable(&api_ck.clk);
+        omap1_clk_disable(api_ck_p);
 
         return clk->parent->rate / dsor;
 }
 
 /* MPU virtual clock functions */
-static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
+int omap1_select_table_rate(struct clk *clk, unsigned long rate)
 {
         /* Find the highest supported frequency <= rate and switch to it */
         struct mpu_rate * ptr;
+        unsigned long dpll1_rate, ref_rate;
 
-        if (clk != &virtual_ck_mpu)
-                return -EINVAL;
+        dpll1_rate = clk_get_rate(ck_dpll1_p);
+        ref_rate = clk_get_rate(ck_ref_p);
 
-        for (ptr = rate_table; ptr->rate; ptr++) {
-                if (ptr->xtal != ck_ref.rate)
+        for (ptr = omap1_rate_table; ptr->rate; ptr++) {
+                if (ptr->xtal != ref_rate)
                         continue;
 
                 /* DPLL1 cannot be reprogrammed without risking system crash */
-                if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
+                if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
                         continue;
 
                 /* Can check only after xtal frequency check */
@@ -405,11 +243,13 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
         else
                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 
-        ck_dpll1.rate = ptr->pll_rate;
+        /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
+        ck_dpll1_p->rate = ptr->pll_rate;
+
         return 0;
 }
 
-static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
+int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
 {
         int dsor_exp;
         u16 regval;
@@ -429,7 +269,7 @@ static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
+long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 {
         int dsor_exp = calc_dsor_exp(clk, rate);
         if (dsor_exp < 0)
@@ -439,7 +279,7 @@ static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
         return clk->parent->rate / (1 << dsor_exp);
 }
 
-static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
+int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
 {
         int dsor_exp;
         u16 regval;
@@ -459,19 +299,19 @@ static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
+long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
 {
         /* Find the highest supported frequency <= rate */
         struct mpu_rate * ptr;
-        long  highest_rate;
+        long highest_rate;
+        unsigned long ref_rate;
 
-        if (clk != &virtual_ck_mpu)
-                return -EINVAL;
+        ref_rate = clk_get_rate(ck_ref_p);
 
         highest_rate = -EINVAL;
 
-        for (ptr = rate_table; ptr->rate; ptr++) {
-                if (ptr->xtal != ck_ref.rate)
+        for (ptr = omap1_rate_table; ptr->rate; ptr++) {
+                if (ptr->xtal != ref_rate)
                         continue;
 
                 highest_rate = ptr->rate;
@@ -506,8 +346,8 @@ static unsigned calc_ext_dsor(unsigned long rate)
         return dsor;
 }
 
-/* Only needed on 1510 */
-static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
+/* XXX Only needed on 1510 */
+int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
 {
         unsigned int val;
 
@@ -525,7 +365,7 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
 }
 
 /* External clock (MCLK & BCLK) functions */
-static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
+int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
 {
         unsigned dsor;
         __u16 ratio_bits;
@@ -543,7 +383,7 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
         return 0;
 }
 
-static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
+int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
 {
         u32 l;
         int div;
@@ -566,12 +406,12 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
+long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
 {
         return 96000000 / calc_ext_dsor(rate);
 }
 
-static void omap1_init_ext_clk(struct clk * clk)
+void omap1_init_ext_clk(struct clk *clk)
 {
         unsigned dsor;
         __u16 ratio_bits;
@@ -589,7 +429,7 @@ static void omap1_init_ext_clk(struct clk * clk)
         clk-> rate = 96000000 / dsor;
 }
 
-static int omap1_clk_enable(struct clk *clk)
+int omap1_clk_enable(struct clk *clk)
 {
         int ret = 0;
 
@@ -617,7 +457,7 @@ err:
         return ret;
 }
 
-static void omap1_clk_disable(struct clk *clk)
+void omap1_clk_disable(struct clk *clk)
 {
         if (clk->usecount > 0 && !(--clk->usecount)) {
                 clk->ops->disable(clk);
@@ -672,12 +512,70 @@ static void omap1_clk_disable_generic(struct clk *clk)
         }
 }
 
-static const struct clkops clkops_generic = {
-        .enable         = &omap1_clk_enable_generic,
-        .disable        = &omap1_clk_disable_generic,
+const struct clkops clkops_generic = {
+        .enable         = omap1_clk_enable_generic,
+        .disable        = omap1_clk_disable_generic,
+};
+
+static int omap1_clk_enable_dsp_domain(struct clk *clk)
+{
+        int retval;
+
+        retval = omap1_clk_enable(api_ck_p);
+        if (!retval) {
+                retval = omap1_clk_enable_generic(clk);
+                omap1_clk_disable(api_ck_p);
+        }
+
+        return retval;
+}
+
+static void omap1_clk_disable_dsp_domain(struct clk *clk)
+{
+        if (omap1_clk_enable(api_ck_p) == 0) {
+                omap1_clk_disable_generic(clk);
+                omap1_clk_disable(api_ck_p);
+        }
+}
+
+const struct clkops clkops_dspck = {
+        .enable         = omap1_clk_enable_dsp_domain,
+        .disable        = omap1_clk_disable_dsp_domain,
+};
+
+static int omap1_clk_enable_uart_functional(struct clk *clk)
+{
+        int ret;
+        struct uart_clk *uclk;
+
+        ret = omap1_clk_enable_generic(clk);
+        if (ret == 0) {
+                /* Set smart idle acknowledgement mode */
+                uclk = (struct uart_clk *)clk;
+                omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
+                            uclk->sysc_addr);
+        }
+
+        return ret;
+}
+
+static void omap1_clk_disable_uart_functional(struct clk *clk)
+{
+        struct uart_clk *uclk;
+
+        /* Set force idle acknowledgement mode */
+        uclk = (struct uart_clk *)clk;
+        omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
+
+        omap1_clk_disable_generic(clk);
+}
+
+const struct clkops clkops_uart = {
+        .enable         = omap1_clk_enable_uart_functional,
+        .disable        = omap1_clk_disable_uart_functional,
 };
 
-static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
+long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 {
         if (clk->flags & RATE_FIXED)
                 return clk->rate;
@@ -688,7 +586,7 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
         return clk->rate;
 }
 
-static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
+int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 {
         int  ret = -EINVAL;
 
@@ -703,7 +601,7 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 
-static void __init omap1_clk_disable_unused(struct clk *clk)
+void __init omap1_clk_disable_unused(struct clk *clk)
 {
         __u32 regval32;
 
@@ -724,184 +622,9 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
         if ((regval32 & (1 << clk->enable_bit)) == 0)
                 return;
 
-        /* FIXME: This clock seems to be necessary but no-one
-         * has asked for its activation. */
-        if (clk == &tc2_ck              /* FIX: pm.c (SRAM), CCP, Camera */
-            || clk == &ck_dpll1out.clk  /* FIX: SoSSI, SSR */
-            || clk == &arm_gpio_ck      /* FIX: GPIO code for 1510 */
-                ) {
-                printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
-                       clk->name);
-                return;
-        }
-
         printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
         clk->ops->disable(clk);
         printk(" done\n");
 }
 
-#else
-#define omap1_clk_disable_unused        NULL
 #endif
-
-static struct clk_functions omap1_clk_functions = {
-        .clk_enable             = omap1_clk_enable,
-        .clk_disable            = omap1_clk_disable,
-        .clk_round_rate         = omap1_clk_round_rate,
-        .clk_set_rate           = omap1_clk_set_rate,
-        .clk_disable_unused     = omap1_clk_disable_unused,
-};
-
-int __init omap1_clk_init(void)
-{
-        struct omap_clk *c;
-        const struct omap_clock_config *info;
-        int crystal_type = 0; /* Default 12 MHz */
-        u32 reg, cpu_mask;
-
-#ifdef CONFIG_DEBUG_LL
-        /* Resets some clocks that may be left on from bootloader,
-         * but leaves serial clocks on.
-         */
-        omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
-#endif
-
-        /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
-        reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
-        omap_writew(reg, SOFT_REQ_REG);
-        if (!cpu_is_omap15xx())
-                omap_writew(0, SOFT_REQ_REG2);
-
-        clk_init(&omap1_clk_functions);
-
-        /* By default all idlect1 clocks are allowed to idle */
-        arm_idlect1_mask = ~0;
-
-        for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
-                clk_preinit(c->lk.clk);
-
-        cpu_mask = 0;
-        if (cpu_is_omap16xx())
-                cpu_mask |= CK_16XX;
-        if (cpu_is_omap1510())
-                cpu_mask |= CK_1510;
-        if (cpu_is_omap7xx())
-                cpu_mask |= CK_7XX;
-        if (cpu_is_omap310())
-                cpu_mask |= CK_310;
-
-        for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
-                if (c->cpu & cpu_mask) {
-                        clkdev_add(&c->lk);
-                        clk_register(c->lk.clk);
-                }
-
-        info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
-        if (info != NULL) {
-                if (!cpu_is_omap15xx())
-                        crystal_type = info->system_clock_type;
-        }
-
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        ck_ref.rate = 13000000;
-#elif defined(CONFIG_ARCH_OMAP16XX)
-        if (crystal_type == 2)
-                ck_ref.rate = 19200000;
-#endif
-
-        printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
-               omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
-               omap_readw(ARM_CKCTL));
-
-        /* We want to be in syncronous scalable mode */
-        omap_writew(0x1000, ARM_SYSST);
-
-#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
-        /* Use values set by bootloader. Determine PLL rate and recalculate
-         * dependent clocks as if kernel had changed PLL or divisors.
-         */
-        {
-                unsigned pll_ctl_val = omap_readw(DPLL_CTL);
-
-                ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
-                if (pll_ctl_val & 0x10) {
-                        /* PLL enabled, apply multiplier and divisor */
-                        if (pll_ctl_val & 0xf80)
-                                ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
-                        ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
-                } else {
-                        /* PLL disabled, apply bypass divisor */
-                        switch (pll_ctl_val & 0xc) {
-                        case 0:
-                                break;
-                        case 0x4:
-                                ck_dpll1.rate /= 2;
-                                break;
-                        default:
-                                ck_dpll1.rate /= 4;
-                                break;
-                        }
-                }
-        }
-#else
-        /* Find the highest supported frequency and enable it */
-        if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
-                printk(KERN_ERR "System frequencies not set. Check your config.\n");
-                /* Guess sane values (60MHz) */
-                omap_writew(0x2290, DPLL_CTL);
-                omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
-                ck_dpll1.rate = 60000000;
-        }
-#endif
-        propagate_rate(&ck_dpll1);
-        /* Cache rates for clocks connected to ck_ref (not dpll1) */
-        propagate_rate(&ck_ref);
-        printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
-                "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
-               ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
-               ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
-               arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
-
-#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
-        /* Select slicer output as OMAP input clock */
-        omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
-#endif
-
-        /* Amstrad Delta wants BCLK high when inactive */
-        if (machine_is_ams_delta())
-                omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
-                                (1 << SDW_MCLK_INV_BIT),
-                                ULPD_CLOCK_CTRL);
-
-        /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
-        /* (on 730, bit 13 must not be cleared) */
-        if (cpu_is_omap7xx())
-                omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
-        else
-                omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
-
-        /* Put DSP/MPUI into reset until needed */
-        omap_writew(0, ARM_RSTCT1);
-        omap_writew(1, ARM_RSTCT2);
-        omap_writew(0x400, ARM_IDLECT1);
-
-        /*
-         * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
-         * of the ARM_IDLECT2 register must be set to zero. The power-on
-         * default value of this bit is one.
-         */
-        omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
-
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable(&armper_ck.clk);
-        clk_enable(&armxor_ck.clk);
-        clk_enable(&armtim_ck.clk); /* This should be done by timer code */
-
-        if (cpu_is_omap15xx())
-                clk_enable(&arm_gpio_ck);
-
-        return 0;
-}
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 29ffa97dc7f3..a4190afb8614 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/mach-omap1/clock.h
  *
- *  Copyright (C) 2004 - 2005 Nokia corporation
+ *  Copyright (C) 2004 - 2005, 2009 Nokia corporation
  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  *
@@ -13,30 +13,36 @@
 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
 
-static unsigned long omap1_ckctl_recalc(struct clk *clk);
-static unsigned long omap1_watchdog_recalc(struct clk *clk);
-static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
-static unsigned long omap1_sossi_recalc(struct clk *clk);
-static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
-static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
-static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
-static unsigned long omap1_uart_recalc(struct clk *clk);
-static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
-static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
-static void omap1_init_ext_clk(struct clk * clk);
-static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
-static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
-
-static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
-static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
-
-struct mpu_rate {
-        unsigned long           rate;
-        unsigned long           xtal;
-        unsigned long           pll_rate;
-        __u16                   ckctl_val;
-        __u16                   dpllctl_val;
-};
+#include <linux/clk.h>
+
+#include <plat/clock.h>
+
+extern int __init omap1_clk_init(void);
+extern int omap1_clk_enable(struct clk *clk);
+extern void omap1_clk_disable(struct clk *clk);
+extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
+extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
+extern unsigned long omap1_ckctl_recalc(struct clk *clk);
+extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
+extern unsigned long omap1_sossi_recalc(struct clk *clk);
+extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
+extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
+extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
+extern unsigned long omap1_uart_recalc(struct clk *clk);
+extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
+extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
+extern void omap1_init_ext_clk(struct clk *clk);
+extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
+extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
+extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
+extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
+extern unsigned long omap1_watchdog_recalc(struct clk *clk);
+
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+extern void __init omap1_clk_disable_unused(struct clk *clk);
+#else
+#define omap1_clk_disable_unused        NULL
+#endif
 
 struct uart_clk {
         struct clk      clk;
@@ -96,596 +102,12 @@ struct arm_idlect1_clk {
 #define SOFT_REQ_REG            0xfffe0834
 #define SOFT_REQ_REG2           0xfffe0880
 
-/*-------------------------------------------------------------------------
- * Omap1 MPU rate table
- *-------------------------------------------------------------------------*/
-static struct mpu_rate rate_table[] = {
-        /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
-         * NOTE: Comment order here is different from bits in CKCTL value:
-         * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
-         */
-#if defined(CONFIG_OMAP_ARM_216MHZ)
-        { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_195MHZ)
-        { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_192MHZ)
-        { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
-        { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
-        {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
-        {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
-        {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_182MHZ)
-        { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_168MHZ)
-        { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
-#endif
-#if defined(CONFIG_OMAP_ARM_150MHZ)
-        { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
-#endif
-#if defined(CONFIG_OMAP_ARM_120MHZ)
-        { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
-#endif
-#if defined(CONFIG_OMAP_ARM_96MHZ)
-        {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_60MHZ)
-        {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_30MHZ)
-        {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
-#endif
-        { 0, 0, 0, 0, 0 },
-};
-
-/*-------------------------------------------------------------------------
- * Omap1 clocks
- *-------------------------------------------------------------------------*/
-
-static struct clk ck_ref = {
-        .name           = "ck_ref",
-        .ops            = &clkops_null,
-        .rate           = 12000000,
-};
-
-static struct clk ck_dpll1 = {
-        .name           = "ck_dpll1",
-        .ops            = &clkops_null,
-        .parent         = &ck_ref,
-};
-
-static struct arm_idlect1_clk ck_dpll1out = {
-        .clk = {
-                .name           = "ck_dpll1out",
-                .ops            = &clkops_generic,
-                .parent         = &ck_dpll1,
-                .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_CKOUT_ARM,
-                .recalc         = &followparent_recalc,
-        },
-        .idlect_shift   = 12,
-};
-
-static struct clk sossi_ck = {
-        .name           = "ck_sossi",
-        .ops            = &clkops_generic,
-        .parent         = &ck_dpll1out.clk,
-        .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
-        .enable_bit     = 16,
-        .recalc         = &omap1_sossi_recalc,
-        .set_rate       = &omap1_set_sossi_rate,
-};
-
-static struct clk arm_ck = {
-        .name           = "arm_ck",
-        .ops            = &clkops_null,
-        .parent         = &ck_dpll1,
-        .rate_offset    = CKCTL_ARMDIV_OFFSET,
-        .recalc         = &omap1_ckctl_recalc,
-        .round_rate     = omap1_clk_round_rate_ckctl_arm,
-        .set_rate       = omap1_clk_set_rate_ckctl_arm,
-};
-
-static struct arm_idlect1_clk armper_ck = {
-        .clk = {
-                .name           = "armper_ck",
-                .ops            = &clkops_generic,
-                .parent         = &ck_dpll1,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_PERCK,
-                .rate_offset    = CKCTL_PERDIV_OFFSET,
-                .recalc         = &omap1_ckctl_recalc,
-                .round_rate     = omap1_clk_round_rate_ckctl_arm,
-                .set_rate       = omap1_clk_set_rate_ckctl_arm,
-        },
-        .idlect_shift   = 2,
-};
-
-static struct clk arm_gpio_ck = {
-        .name           = "arm_gpio_ck",
-        .ops            = &clkops_generic,
-        .parent         = &ck_dpll1,
-        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-        .enable_bit     = EN_GPIOCK,
-        .recalc         = &followparent_recalc,
-};
-
-static struct arm_idlect1_clk armxor_ck = {
-        .clk = {
-                .name           = "armxor_ck",
-                .ops            = &clkops_generic,
-                .parent         = &ck_ref,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_XORPCK,
-                .recalc         = &followparent_recalc,
-        },
-        .idlect_shift   = 1,
-};
-
-static struct arm_idlect1_clk armtim_ck = {
-        .clk = {
-                .name           = "armtim_ck",
-                .ops            = &clkops_generic,
-                .parent         = &ck_ref,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_TIMCK,
-                .recalc         = &followparent_recalc,
-        },
-        .idlect_shift   = 9,
-};
-
-static struct arm_idlect1_clk armwdt_ck = {
-        .clk = {
-                .name           = "armwdt_ck",
-                .ops            = &clkops_generic,
-                .parent         = &ck_ref,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_WDTCK,
-                .recalc         = &omap1_watchdog_recalc,
-        },
-        .idlect_shift   = 0,
-};
-
-static struct clk arminth_ck16xx = {
-        .name           = "arminth_ck",
-        .ops            = &clkops_null,
-        .parent         = &arm_ck,
-        .recalc         = &followparent_recalc,
-        /* Note: On 16xx the frequency can be divided by 2 by programming
-         * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
-         *
-         * 1510 version is in TC clocks.
-         */
-};
-
-static struct clk dsp_ck = {
-        .name           = "dsp_ck",
-        .ops            = &clkops_generic,
-        .parent         = &ck_dpll1,
-        .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
-        .enable_bit     = EN_DSPCK,
-        .rate_offset    = CKCTL_DSPDIV_OFFSET,
-        .recalc         = &omap1_ckctl_recalc,
-        .round_rate     = omap1_clk_round_rate_ckctl_arm,
-        .set_rate       = omap1_clk_set_rate_ckctl_arm,
-};
-
-static struct clk dspmmu_ck = {
-        .name           = "dspmmu_ck",
-        .ops            = &clkops_null,
-        .parent         = &ck_dpll1,
-        .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
-        .recalc         = &omap1_ckctl_recalc,
-        .round_rate     = omap1_clk_round_rate_ckctl_arm,
-        .set_rate       = omap1_clk_set_rate_ckctl_arm,
-};
-
-static struct clk dspper_ck = {
-        .name           = "dspper_ck",
-        .ops            = &clkops_dspck,
-        .parent         = &ck_dpll1,
-        .enable_reg     = DSP_IDLECT2,
-        .enable_bit     = EN_PERCK,
-        .rate_offset    = CKCTL_PERDIV_OFFSET,
-        .recalc         = &omap1_ckctl_recalc_dsp_domain,
-        .round_rate     = omap1_clk_round_rate_ckctl_arm,
-        .set_rate       = &omap1_clk_set_rate_dsp_domain,
-};
-
-static struct clk dspxor_ck = {
-        .name           = "dspxor_ck",
-        .ops            = &clkops_dspck,
-        .parent         = &ck_ref,
-        .enable_reg     = DSP_IDLECT2,
-        .enable_bit     = EN_XORPCK,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dsptim_ck = {
-        .name           = "dsptim_ck",
-        .ops            = &clkops_dspck,
-        .parent         = &ck_ref,
-        .enable_reg     = DSP_IDLECT2,
-        .enable_bit     = EN_DSPTIMCK,
-        .recalc         = &followparent_recalc,
-};
-
-/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
-static struct arm_idlect1_clk tc_ck = {
-        .clk = {
-                .name           = "tc_ck",
-                .ops            = &clkops_null,
-                .parent         = &ck_dpll1,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .rate_offset    = CKCTL_TCDIV_OFFSET,
-                .recalc         = &omap1_ckctl_recalc,
-                .round_rate     = omap1_clk_round_rate_ckctl_arm,
-                .set_rate       = omap1_clk_set_rate_ckctl_arm,
-        },
-        .idlect_shift   = 6,
-};
-
-static struct clk arminth_ck1510 = {
-        .name           = "arminth_ck",
-        .ops            = &clkops_null,
-        .parent         = &tc_ck.clk,
-        .recalc         = &followparent_recalc,
-        /* Note: On 1510 the frequency follows TC_CK
-         *
-         * 16xx version is in MPU clocks.
-         */
-};
-
-static struct clk tipb_ck = {
-        /* No-idle controlled by "tc_ck" */
-        .name           = "tipb_ck",
-        .ops            = &clkops_null,
-        .parent         = &tc_ck.clk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk l3_ocpi_ck = {
-        /* No-idle controlled by "tc_ck" */
-        .name           = "l3_ocpi_ck",
-        .ops            = &clkops_generic,
-        .parent         = &tc_ck.clk,
-        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
-        .enable_bit     = EN_OCPI_CK,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk tc1_ck = {
-        .name           = "tc1_ck",
-        .ops            = &clkops_generic,
-        .parent         = &tc_ck.clk,
-        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
-        .enable_bit     = EN_TC1_CK,
-        .recalc         = &followparent_recalc,
-};
+extern __u32 arm_idlect1_mask;
+extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
 
-static struct clk tc2_ck = {
-        .name           = "tc2_ck",
-        .ops            = &clkops_generic,
-        .parent         = &tc_ck.clk,
-        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
-        .enable_bit     = EN_TC2_CK,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dma_ck = {
-        /* No-idle controlled by "tc_ck" */
-        .name           = "dma_ck",
-        .ops            = &clkops_null,
-        .parent         = &tc_ck.clk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dma_lcdfree_ck = {
-        .name           = "dma_lcdfree_ck",
-        .ops            = &clkops_null,
-        .parent         = &tc_ck.clk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct arm_idlect1_clk api_ck = {
-        .clk = {
-                .name           = "api_ck",
-                .ops            = &clkops_generic,
-                .parent         = &tc_ck.clk,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_APICK,
-                .recalc         = &followparent_recalc,
-        },
-        .idlect_shift   = 8,
-};
-
-static struct arm_idlect1_clk lb_ck = {
-        .clk = {
-                .name           = "lb_ck",
-                .ops            = &clkops_generic,
-                .parent         = &tc_ck.clk,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_LBCK,
-                .recalc         = &followparent_recalc,
-        },
-        .idlect_shift   = 4,
-};
-
-static struct clk rhea1_ck = {
-        .name           = "rhea1_ck",
-        .ops            = &clkops_null,
-        .parent         = &tc_ck.clk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk rhea2_ck = {
-        .name           = "rhea2_ck",
-        .ops            = &clkops_null,
-        .parent         = &tc_ck.clk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk lcd_ck_16xx = {
-        .name           = "lcd_ck",
-        .ops            = &clkops_generic,
-        .parent         = &ck_dpll1,
-        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-        .enable_bit     = EN_LCDCK,
-        .rate_offset    = CKCTL_LCDDIV_OFFSET,
-        .recalc         = &omap1_ckctl_recalc,
-        .round_rate     = omap1_clk_round_rate_ckctl_arm,
-        .set_rate       = omap1_clk_set_rate_ckctl_arm,
-};
-
-static struct arm_idlect1_clk lcd_ck_1510 = {
-        .clk = {
-                .name           = "lcd_ck",
-                .ops            = &clkops_generic,
-                .parent         = &ck_dpll1,
-                .flags          = CLOCK_IDLE_CONTROL,
-                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
-                .enable_bit     = EN_LCDCK,
-                .rate_offset    = CKCTL_LCDDIV_OFFSET,
-                .recalc         = &omap1_ckctl_recalc,
-                .round_rate     = omap1_clk_round_rate_ckctl_arm,
-                .set_rate       = omap1_clk_set_rate_ckctl_arm,
-        },
-        .idlect_shift   = 3,
-};
-
-static struct clk uart1_1510 = {
-        .name           = "uart1_ck",
-        .ops            = &clkops_null,
-        /* Direct from ULPD, no real parent */
-        .parent         = &armper_ck.clk,
-        .rate           = 12000000,
-        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-        .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
-        .set_rate       = &omap1_set_uart_rate,
-        .recalc         = &omap1_uart_recalc,
-};
-
-static struct uart_clk uart1_16xx = {
-        .clk    = {
-                .name           = "uart1_ck",
-                .ops            = &clkops_uart,
-                /* Direct from ULPD, no real parent */
-                .parent         = &armper_ck.clk,
-                .rate           = 48000000,
-                .flags          = RATE_FIXED | ENABLE_REG_32BIT |
-                                  CLOCK_NO_IDLE_PARENT,
-                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-                .enable_bit     = 29,
-        },
-        .sysc_addr      = 0xfffb0054,
-};
-
-static struct clk uart2_ck = {
-        .name           = "uart2_ck",
-        .ops            = &clkops_null,
-        /* Direct from ULPD, no real parent */
-        .parent         = &armper_ck.clk,
-        .rate           = 12000000,
-        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-        .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
-        .set_rate       = &omap1_set_uart_rate,
-        .recalc         = &omap1_uart_recalc,
-};
-
-static struct clk uart3_1510 = {
-        .name           = "uart3_ck",
-        .ops            = &clkops_null,
-        /* Direct from ULPD, no real parent */
-        .parent         = &armper_ck.clk,
-        .rate           = 12000000,
-        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-        .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
-        .set_rate       = &omap1_set_uart_rate,
-        .recalc         = &omap1_uart_recalc,
-};
-
-static struct uart_clk uart3_16xx = {
-        .clk    = {
-                .name           = "uart3_ck",
-                .ops            = &clkops_uart,
-                /* Direct from ULPD, no real parent */
-                .parent         = &armper_ck.clk,
-                .rate           = 48000000,
-                .flags          = RATE_FIXED | ENABLE_REG_32BIT |
-                                  CLOCK_NO_IDLE_PARENT,
-                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-                .enable_bit     = 31,
-        },
-        .sysc_addr      = 0xfffb9854,
-};
-
-static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
-        .name           = "usb_clko",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent */
-        .rate           = 6000000,
-        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
-        .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
-        .enable_bit     = USB_MCLK_EN_BIT,
-};
-
-static struct clk usb_hhc_ck1510 = {
-        .name           = "usb_hhc_ck",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent */
-        .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
-        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-        .enable_bit     = USB_HOST_HHC_UHOST_EN,
-};
-
-static struct clk usb_hhc_ck16xx = {
-        .name           = "usb_hhc_ck",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent */
-        .rate           = 48000000,
-        /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
-        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
-        .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
-        .enable_bit     = 8 /* UHOST_EN */,
-};
-
-static struct clk usb_dc_ck = {
-        .name           = "usb_dc_ck",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent */
-        .rate           = 48000000,
-        .flags          = RATE_FIXED,
-        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-        .enable_bit     = 4,
-};
-
-static struct clk usb_dc_ck7xx = {
-        .name           = "usb_dc_ck",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent */
-        .rate           = 48000000,
-        .flags          = RATE_FIXED,
-        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-        .enable_bit     = 8,
-};
-
-static struct clk mclk_1510 = {
-        .name           = "mclk",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-        .rate           = 12000000,
-        .flags          = RATE_FIXED,
-        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-        .enable_bit     = 6,
-};
-
-static struct clk mclk_16xx = {
-        .name           = "mclk",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-        .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
-        .enable_bit     = COM_ULPD_PLL_CLK_REQ,
-        .set_rate       = &omap1_set_ext_clk_rate,
-        .round_rate     = &omap1_round_ext_clk_rate,
-        .init           = &omap1_init_ext_clk,
-};
-
-static struct clk bclk_1510 = {
-        .name           = "bclk",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-        .rate           = 12000000,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk bclk_16xx = {
-        .name           = "bclk",
-        .ops            = &clkops_generic,
-        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
-        .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
-        .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
-        .set_rate       = &omap1_set_ext_clk_rate,
-        .round_rate     = &omap1_round_ext_clk_rate,
-        .init           = &omap1_init_ext_clk,
-};
-
-static struct clk mmc1_ck = {
-        .name           = "mmc_ck",
-        .ops            = &clkops_generic,
-        /* Functional clock is direct from ULPD, interface clock is ARMPER */
-        .parent         = &armper_ck.clk,
-        .rate           = 48000000,
-        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-        .enable_bit     = 23,
-};
-
-static struct clk mmc2_ck = {
-        .name           = "mmc_ck",
-        .id             = 1,
-        .ops            = &clkops_generic,
-        /* Functional clock is direct from ULPD, interface clock is ARMPER */
-        .parent         = &armper_ck.clk,
-        .rate           = 48000000,
-        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
-        .enable_bit     = 20,
-};
-
-static struct clk mmc3_ck = {
-        .name           = "mmc_ck",
-        .id             = 2,
-        .ops            = &clkops_generic,
-        /* Functional clock is direct from ULPD, interface clock is ARMPER */
-        .parent         = &armper_ck.clk,
-        .rate           = 48000000,
-        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
-        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
-        .enable_bit     = 12,
-};
-
-static struct clk virtual_ck_mpu = {
-        .name           = "mpu",
-        .ops            = &clkops_null,
-        .parent         = &arm_ck, /* Is smarter alias for */
-        .recalc         = &followparent_recalc,
-        .set_rate       = &omap1_select_table_rate,
-        .round_rate     = &omap1_round_to_table_rate,
-};
-
-/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
-remains active during MPU idle whenever this is enabled */
-static struct clk i2c_fck = {
-        .name           = "i2c_fck",
-        .id             = 1,
-        .ops            = &clkops_null,
-        .flags          = CLOCK_NO_IDLE_PARENT,
-        .parent         = &armxor_ck.clk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c_ick = {
-        .name           = "i2c_ick",
-        .id             = 1,
-        .ops            = &clkops_null,
-        .flags          = CLOCK_NO_IDLE_PARENT,
-        .parent         = &armper_ck.clk,
-        .recalc         = &followparent_recalc,
-};
+extern const struct clkops clkops_dspck;
+extern const struct clkops clkops_dummy;
+extern const struct clkops clkops_uart;
+extern const struct clkops clkops_generic;
 
 #endif
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
new file mode 100644
index 000000000000..ab995a9c606c
--- /dev/null
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -0,0 +1,843 @@
+/*
+ *  linux/arch/arm/mach-omap1/clock_data.c
+ *
+ *  Copyright (C) 2004 - 2005, 2009 Nokia corporation
+ *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/mach-types.h>  /* for machine_is_* */
+
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/clkdev_omap.h>
+#include <plat/usb.h>   /* for OTG_BASE */
+
+#include "clock.h"
+
+/*------------------------------------------------------------------------
+ * Omap1 clocks
+ *-------------------------------------------------------------------------*/
+
+/* XXX is this necessary? */
+static struct clk dummy_ck = {
+        .name   = "dummy",
+        .ops    = &clkops_dummy,
+        .flags  = RATE_FIXED,
+};
+
+static struct clk ck_ref = {
+        .name           = "ck_ref",
+        .ops            = &clkops_null,
+        .rate           = 12000000,
+};
+
+static struct clk ck_dpll1 = {
+        .name           = "ck_dpll1",
+        .ops            = &clkops_null,
+        .parent         = &ck_ref,
+};
+
+/*
+ * FIXME: This clock seems to be necessary but no-one has asked for its
+ * activation.  [ FIX: SoSSI, SSR ]
+ */
+static struct arm_idlect1_clk ck_dpll1out = {
+        .clk = {
+                .name           = "ck_dpll1out",
+                .ops            = &clkops_generic,
+                .parent         = &ck_dpll1,
+                .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
+                                  ENABLE_ON_INIT,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_CKOUT_ARM,
+                .recalc         = &followparent_recalc,
+        },
+        .idlect_shift   = 12,
+};
+
+static struct clk sossi_ck = {
+        .name           = "ck_sossi",
+        .ops            = &clkops_generic,
+        .parent         = &ck_dpll1out.clk,
+        .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
+        .enable_bit     = 16,
+        .recalc         = &omap1_sossi_recalc,
+        .set_rate       = &omap1_set_sossi_rate,
+};
+
+static struct clk arm_ck = {
+        .name           = "arm_ck",
+        .ops            = &clkops_null,
+        .parent         = &ck_dpll1,
+        .rate_offset    = CKCTL_ARMDIV_OFFSET,
+        .recalc         = &omap1_ckctl_recalc,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = omap1_clk_set_rate_ckctl_arm,
+};
+
+static struct arm_idlect1_clk armper_ck = {
+        .clk = {
+                .name           = "armper_ck",
+                .ops            = &clkops_generic,
+                .parent         = &ck_dpll1,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_PERCK,
+                .rate_offset    = CKCTL_PERDIV_OFFSET,
+                .recalc         = &omap1_ckctl_recalc,
+                .round_rate     = omap1_clk_round_rate_ckctl_arm,
+                .set_rate       = omap1_clk_set_rate_ckctl_arm,
+        },
+        .idlect_shift   = 2,
+};
+
+/*
+ * FIXME: This clock seems to be necessary but no-one has asked for its
+ * activation.  [ GPIO code for 1510 ]
+ */
+static struct clk arm_gpio_ck = {
+        .name           = "arm_gpio_ck",
+        .ops            = &clkops_generic,
+        .parent         = &ck_dpll1,
+        .flags          = ENABLE_ON_INIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+        .enable_bit     = EN_GPIOCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct arm_idlect1_clk armxor_ck = {
+        .clk = {
+                .name           = "armxor_ck",
+                .ops            = &clkops_generic,
+                .parent         = &ck_ref,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_XORPCK,
+                .recalc         = &followparent_recalc,
+        },
+        .idlect_shift   = 1,
+};
+
+static struct arm_idlect1_clk armtim_ck = {
+        .clk = {
+                .name           = "armtim_ck",
+                .ops            = &clkops_generic,
+                .parent         = &ck_ref,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_TIMCK,
+                .recalc         = &followparent_recalc,
+        },
+        .idlect_shift   = 9,
+};
+
+static struct arm_idlect1_clk armwdt_ck = {
+        .clk = {
+                .name           = "armwdt_ck",
+                .ops            = &clkops_generic,
+                .parent         = &ck_ref,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_WDTCK,
+                .recalc         = &omap1_watchdog_recalc,
+        },
+        .idlect_shift   = 0,
+};
+
+static struct clk arminth_ck16xx = {
+        .name           = "arminth_ck",
+        .ops            = &clkops_null,
+        .parent         = &arm_ck,
+        .recalc         = &followparent_recalc,
+        /* Note: On 16xx the frequency can be divided by 2 by programming
+         * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
+         *
+         * 1510 version is in TC clocks.
+         */
+};
+
+static struct clk dsp_ck = {
+        .name           = "dsp_ck",
+        .ops            = &clkops_generic,
+        .parent         = &ck_dpll1,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
+        .enable_bit     = EN_DSPCK,
+        .rate_offset    = CKCTL_DSPDIV_OFFSET,
+        .recalc         = &omap1_ckctl_recalc,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = omap1_clk_set_rate_ckctl_arm,
+};
+
+static struct clk dspmmu_ck = {
+        .name           = "dspmmu_ck",
+        .ops            = &clkops_null,
+        .parent         = &ck_dpll1,
+        .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
+        .recalc         = &omap1_ckctl_recalc,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = omap1_clk_set_rate_ckctl_arm,
+};
+
+static struct clk dspper_ck = {
+        .name           = "dspper_ck",
+        .ops            = &clkops_dspck,
+        .parent         = &ck_dpll1,
+        .enable_reg     = DSP_IDLECT2,
+        .enable_bit     = EN_PERCK,
+        .rate_offset    = CKCTL_PERDIV_OFFSET,
+        .recalc         = &omap1_ckctl_recalc_dsp_domain,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = &omap1_clk_set_rate_dsp_domain,
+};
+
+static struct clk dspxor_ck = {
+        .name           = "dspxor_ck",
+        .ops            = &clkops_dspck,
+        .parent         = &ck_ref,
+        .enable_reg     = DSP_IDLECT2,
+        .enable_bit     = EN_XORPCK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dsptim_ck = {
+        .name           = "dsptim_ck",
+        .ops            = &clkops_dspck,
+        .parent         = &ck_ref,
+        .enable_reg     = DSP_IDLECT2,
+        .enable_bit     = EN_DSPTIMCK,
+        .recalc         = &followparent_recalc,
+};
+
+/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
+static struct arm_idlect1_clk tc_ck = {
+        .clk = {
+                .name           = "tc_ck",
+                .ops            = &clkops_null,
+                .parent         = &ck_dpll1,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .rate_offset    = CKCTL_TCDIV_OFFSET,
+                .recalc         = &omap1_ckctl_recalc,
+                .round_rate     = omap1_clk_round_rate_ckctl_arm,
+                .set_rate       = omap1_clk_set_rate_ckctl_arm,
+        },
+        .idlect_shift   = 6,
+};
+
+static struct clk arminth_ck1510 = {
+        .name           = "arminth_ck",
+        .ops            = &clkops_null,
+        .parent         = &tc_ck.clk,
+        .recalc         = &followparent_recalc,
+        /* Note: On 1510 the frequency follows TC_CK
+         *
+         * 16xx version is in MPU clocks.
+         */
+};
+
+static struct clk tipb_ck = {
+        /* No-idle controlled by "tc_ck" */
+        .name           = "tipb_ck",
+        .ops            = &clkops_null,
+        .parent         = &tc_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk l3_ocpi_ck = {
+        /* No-idle controlled by "tc_ck" */
+        .name           = "l3_ocpi_ck",
+        .ops            = &clkops_generic,
+        .parent         = &tc_ck.clk,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
+        .enable_bit     = EN_OCPI_CK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk tc1_ck = {
+        .name           = "tc1_ck",
+        .ops            = &clkops_generic,
+        .parent         = &tc_ck.clk,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
+        .enable_bit     = EN_TC1_CK,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * FIXME: This clock seems to be necessary but no-one has asked for its
+ * activation.  [ pm.c (SRAM), CCP, Camera ]
+ */
+static struct clk tc2_ck = {
+        .name           = "tc2_ck",
+        .ops            = &clkops_generic,
+        .parent         = &tc_ck.clk,
+        .flags          = ENABLE_ON_INIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
+        .enable_bit     = EN_TC2_CK,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dma_ck = {
+        /* No-idle controlled by "tc_ck" */
+        .name           = "dma_ck",
+        .ops            = &clkops_null,
+        .parent         = &tc_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dma_lcdfree_ck = {
+        .name           = "dma_lcdfree_ck",
+        .ops            = &clkops_null,
+        .parent         = &tc_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct arm_idlect1_clk api_ck = {
+        .clk = {
+                .name           = "api_ck",
+                .ops            = &clkops_generic,
+                .parent         = &tc_ck.clk,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_APICK,
+                .recalc         = &followparent_recalc,
+        },
+        .idlect_shift   = 8,
+};
+
+static struct arm_idlect1_clk lb_ck = {
+        .clk = {
+                .name           = "lb_ck",
+                .ops            = &clkops_generic,
+                .parent         = &tc_ck.clk,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_LBCK,
+                .recalc         = &followparent_recalc,
+        },
+        .idlect_shift   = 4,
+};
+
+static struct clk rhea1_ck = {
+        .name           = "rhea1_ck",
+        .ops            = &clkops_null,
+        .parent         = &tc_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk rhea2_ck = {
+        .name           = "rhea2_ck",
+        .ops            = &clkops_null,
+        .parent         = &tc_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk lcd_ck_16xx = {
+        .name           = "lcd_ck",
+        .ops            = &clkops_generic,
+        .parent         = &ck_dpll1,
+        .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+        .enable_bit     = EN_LCDCK,
+        .rate_offset    = CKCTL_LCDDIV_OFFSET,
+        .recalc         = &omap1_ckctl_recalc,
+        .round_rate     = omap1_clk_round_rate_ckctl_arm,
+        .set_rate       = omap1_clk_set_rate_ckctl_arm,
+};
+
+static struct arm_idlect1_clk lcd_ck_1510 = {
+        .clk = {
+                .name           = "lcd_ck",
+                .ops            = &clkops_generic,
+                .parent         = &ck_dpll1,
+                .flags          = CLOCK_IDLE_CONTROL,
+                .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
+                .enable_bit     = EN_LCDCK,
+                .rate_offset    = CKCTL_LCDDIV_OFFSET,
+                .recalc         = &omap1_ckctl_recalc,
+                .round_rate     = omap1_clk_round_rate_ckctl_arm,
+                .set_rate       = omap1_clk_set_rate_ckctl_arm,
+        },
+        .idlect_shift   = 3,
+};
+
+static struct clk uart1_1510 = {
+        .name           = "uart1_ck",
+        .ops            = &clkops_null,
+        /* Direct from ULPD, no real parent */
+        .parent         = &armper_ck.clk,
+        .rate           = 12000000,
+        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+        .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
+        .set_rate       = &omap1_set_uart_rate,
+        .recalc         = &omap1_uart_recalc,
+};
+
+static struct uart_clk uart1_16xx = {
+        .clk    = {
+                .name           = "uart1_ck",
+                .ops            = &clkops_uart,
+                /* Direct from ULPD, no real parent */
+                .parent         = &armper_ck.clk,
+                .rate           = 48000000,
+                .flags          = RATE_FIXED | ENABLE_REG_32BIT |
+                                  CLOCK_NO_IDLE_PARENT,
+                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+                .enable_bit     = 29,
+        },
+        .sysc_addr      = 0xfffb0054,
+};
+
+static struct clk uart2_ck = {
+        .name           = "uart2_ck",
+        .ops            = &clkops_null,
+        /* Direct from ULPD, no real parent */
+        .parent         = &armper_ck.clk,
+        .rate           = 12000000,
+        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+        .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
+        .set_rate       = &omap1_set_uart_rate,
+        .recalc         = &omap1_uart_recalc,
+};
+
+static struct clk uart3_1510 = {
+        .name           = "uart3_ck",
+        .ops            = &clkops_null,
+        /* Direct from ULPD, no real parent */
+        .parent         = &armper_ck.clk,
+        .rate           = 12000000,
+        .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+        .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
+        .set_rate       = &omap1_set_uart_rate,
+        .recalc         = &omap1_uart_recalc,
+};
+
+static struct uart_clk uart3_16xx = {
+        .clk    = {
+                .name           = "uart3_ck",
+                .ops            = &clkops_uart,
+                /* Direct from ULPD, no real parent */
+                .parent         = &armper_ck.clk,
+                .rate           = 48000000,
+                .flags          = RATE_FIXED | ENABLE_REG_32BIT |
+                                  CLOCK_NO_IDLE_PARENT,
+                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+                .enable_bit     = 31,
+        },
+        .sysc_addr      = 0xfffb9854,
+};
+
+static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
+        .name           = "usb_clko",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent */
+        .rate           = 6000000,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
+        .enable_bit     = USB_MCLK_EN_BIT,
+};
+
+static struct clk usb_hhc_ck1510 = {
+        .name           = "usb_hhc_ck",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent */
+        .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+        .enable_bit     = USB_HOST_HHC_UHOST_EN,
+};
+
+static struct clk usb_hhc_ck16xx = {
+        .name           = "usb_hhc_ck",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent */
+        .rate           = 48000000,
+        /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT,
+        .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
+        .enable_bit     = 8 /* UHOST_EN */,
+};
+
+static struct clk usb_dc_ck = {
+        .name           = "usb_dc_ck",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent */
+        .rate           = 48000000,
+        .flags          = RATE_FIXED,
+        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+        .enable_bit     = 4,
+};
+
+static struct clk usb_dc_ck7xx = {
+        .name           = "usb_dc_ck",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent */
+        .rate           = 48000000,
+        .flags          = RATE_FIXED,
+        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+        .enable_bit     = 8,
+};
+
+static struct clk mclk_1510 = {
+        .name           = "mclk",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
+        .rate           = 12000000,
+        .flags          = RATE_FIXED,
+        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+        .enable_bit     = 6,
+};
+
+static struct clk mclk_16xx = {
+        .name           = "mclk",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
+        .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
+        .enable_bit     = COM_ULPD_PLL_CLK_REQ,
+        .set_rate       = &omap1_set_ext_clk_rate,
+        .round_rate     = &omap1_round_ext_clk_rate,
+        .init           = &omap1_init_ext_clk,
+};
+
+static struct clk bclk_1510 = {
+        .name           = "bclk",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
+        .rate           = 12000000,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk bclk_16xx = {
+        .name           = "bclk",
+        .ops            = &clkops_generic,
+        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
+        .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
+        .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
+        .set_rate       = &omap1_set_ext_clk_rate,
+        .round_rate     = &omap1_round_ext_clk_rate,
+        .init           = &omap1_init_ext_clk,
+};
+
+static struct clk mmc1_ck = {
+        .name           = "mmc_ck",
+        .ops            = &clkops_generic,
+        /* Functional clock is direct from ULPD, interface clock is ARMPER */
+        .parent         = &armper_ck.clk,
+        .rate           = 48000000,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+        .enable_bit     = 23,
+};
+
+static struct clk mmc2_ck = {
+        .name           = "mmc_ck",
+        .id             = 1,
+        .ops            = &clkops_generic,
+        /* Functional clock is direct from ULPD, interface clock is ARMPER */
+        .parent         = &armper_ck.clk,
+        .rate           = 48000000,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
+        .enable_bit     = 20,
+};
+
+static struct clk mmc3_ck = {
+        .name           = "mmc_ck",
+        .id             = 2,
+        .ops            = &clkops_generic,
+        /* Functional clock is direct from ULPD, interface clock is ARMPER */
+        .parent         = &armper_ck.clk,
+        .rate           = 48000000,
+        .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
+        .enable_bit     = 12,
+};
+
+static struct clk virtual_ck_mpu = {
+        .name           = "mpu",
+        .ops            = &clkops_null,
+        .parent         = &arm_ck, /* Is smarter alias for */
+        .recalc         = &followparent_recalc,
+        .set_rate       = &omap1_select_table_rate,
+        .round_rate     = &omap1_round_to_table_rate,
+};
+
+/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
+remains active during MPU idle whenever this is enabled */
+static struct clk i2c_fck = {
+        .name           = "i2c_fck",
+        .id             = 1,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_NO_IDLE_PARENT,
+        .parent         = &armxor_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c_ick = {
+        .name           = "i2c_ick",
+        .id             = 1,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_NO_IDLE_PARENT,
+        .parent         = &armper_ck.clk,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * clkdev integration
+ */
+
+static struct omap_clk omap_clks[] = {
+        /* non-ULPD clocks */
+        CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
+        CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
+        /* CK_GEN1 clocks */
+        CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
+        CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
+        CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
+        CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
+        CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
+        CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
+        CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
+        CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
+        /* CK_GEN2 clocks */
+        CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
+        /* CK_GEN3 clocks */
+        CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
+        CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
+        CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX | CK_7XX),
+        CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
+        CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
+        CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
+        CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
+        CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
+        CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
+        CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
+        CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
+        /* ULPD clocks */
+        CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
+        CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
+        CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
+        CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
+        CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
+        CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
+        CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
+        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
+        CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
+        CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
+        CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
+        CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
+        CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
+        CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
+        CLK("mmci-omap.0", "fck",       &mmc3_ck,       CK_7XX),
+        CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
+        CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
+        CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
+        /* Virtual clocks */
+        CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
+        CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310 | CK_7XX),
+        CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
+        CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310 | CK_7XX),
+        CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
+        CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
+        CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
+        CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
+        CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
+        CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
+        CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
+        CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
+        CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
+};
+
+/*
+ * init
+ */
+
+static struct clk_functions omap1_clk_functions __initdata = {
+        .clk_enable             = omap1_clk_enable,
+        .clk_disable            = omap1_clk_disable,
+        .clk_round_rate         = omap1_clk_round_rate,
+        .clk_set_rate           = omap1_clk_set_rate,
+        .clk_disable_unused     = omap1_clk_disable_unused,
+};
+
+int __init omap1_clk_init(void)
+{
+        struct omap_clk *c;
+        const struct omap_clock_config *info;
+        int crystal_type = 0; /* Default 12 MHz */
+        u32 reg, cpu_mask;
+
+#ifdef CONFIG_DEBUG_LL
+        /*
+         * Resets some clocks that may be left on from bootloader,
+         * but leaves serial clocks on.
+         */
+        omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
+#endif
+
+        /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
+        reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
+        omap_writew(reg, SOFT_REQ_REG);
+        if (!cpu_is_omap15xx())
+                omap_writew(0, SOFT_REQ_REG2);
+
+        clk_init(&omap1_clk_functions);
+
+        /* By default all idlect1 clocks are allowed to idle */
+        arm_idlect1_mask = ~0;
+
+        for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
+                clk_preinit(c->lk.clk);
+
+        cpu_mask = 0;
+        if (cpu_is_omap16xx())
+                cpu_mask |= CK_16XX;
+        if (cpu_is_omap1510())
+                cpu_mask |= CK_1510;
+        if (cpu_is_omap7xx())
+                cpu_mask |= CK_7XX;
+        if (cpu_is_omap310())
+                cpu_mask |= CK_310;
+
+        for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
+                if (c->cpu & cpu_mask) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
+                }
+
+        /* Pointers to these clocks are needed by code in clock.c */
+        api_ck_p = clk_get(NULL, "api_ck");
+        ck_dpll1_p = clk_get(NULL, "ck_dpll1");
+        ck_ref_p = clk_get(NULL, "ck_ref");
+
+        info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
+        if (info != NULL) {
+                if (!cpu_is_omap15xx())
+                        crystal_type = info->system_clock_type;
+        }
+
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+        ck_ref.rate = 13000000;
+#elif defined(CONFIG_ARCH_OMAP16XX)
+        if (crystal_type == 2)
+                ck_ref.rate = 19200000;
+#endif
+
+        pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
+                "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
+                omap_readw(ARM_CKCTL));
+
+        /* We want to be in syncronous scalable mode */
+        omap_writew(0x1000, ARM_SYSST);
+
+#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
+        /* Use values set by bootloader. Determine PLL rate and recalculate
+         * dependent clocks as if kernel had changed PLL or divisors.
+         */
+        {
+                unsigned pll_ctl_val = omap_readw(DPLL_CTL);
+
+                ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
+                if (pll_ctl_val & 0x10) {
+                        /* PLL enabled, apply multiplier and divisor */
+                        if (pll_ctl_val & 0xf80)
+                                ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
+                        ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
+                } else {
+                        /* PLL disabled, apply bypass divisor */
+                        switch (pll_ctl_val & 0xc) {
+                        case 0:
+                                break;
+                        case 0x4:
+                                ck_dpll1.rate /= 2;
+                                break;
+                        default:
+                                ck_dpll1.rate /= 4;
+                                break;
+                        }
+                }
+        }
+#else
+        /* Find the highest supported frequency and enable it */
+        if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
+                printk(KERN_ERR "System frequencies not set. Check your config.\n");
+                /* Guess sane values (60MHz) */
+                omap_writew(0x2290, DPLL_CTL);
+                omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
+                ck_dpll1.rate = 60000000;
+        }
+#endif
+        propagate_rate(&ck_dpll1);
+        /* Cache rates for clocks connected to ck_ref (not dpll1) */
+        propagate_rate(&ck_ref);
+        printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
+                "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
+               ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
+               ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
+               arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
+
+#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
+        /* Select slicer output as OMAP input clock */
+        omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
+#endif
+
+        /* Amstrad Delta wants BCLK high when inactive */
+        if (machine_is_ams_delta())
+                omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
+                                (1 << SDW_MCLK_INV_BIT),
+                                ULPD_CLOCK_CTRL);
+
+        /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
+        /* (on 730, bit 13 must not be cleared) */
+        if (cpu_is_omap7xx())
+                omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
+        else
+                omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
+
+        /* Put DSP/MPUI into reset until needed */
+        omap_writew(0, ARM_RSTCT1);
+        omap_writew(1, ARM_RSTCT2);
+        omap_writew(0x400, ARM_IDLECT1);
+
+        /*
+         * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
+         * of the ARM_IDLECT2 register must be set to zero. The power-on
+         * default value of this bit is one.
+         */
+        omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable(&armper_ck.clk);
+        clk_enable(&armxor_ck.clk);
+        clk_enable(&armtim_ck.clk); /* This should be done by timer code */
+
+        if (cpu_is_omap15xx())
+                clk_enable(&arm_gpio_ck);
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
new file mode 100644
index 000000000000..1bf4735e27a6
--- /dev/null
+++ b/arch/arm/mach-omap1/i2c.c
@@ -0,0 +1,39 @@
+/*
+ * Helper module for board specific I2C bus registration
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <plat/i2c.h>
+#include <plat/mux.h>
+#include <plat/cpu.h>
+
+int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
+                          struct i2c_board_info const *info,
+                          unsigned len)
+{
+        if (cpu_is_omap7xx()) {
+                omap_cfg_reg(I2C_7XX_SDA);
+                omap_cfg_reg(I2C_7XX_SCL);
+        } else {
+                omap_cfg_reg(I2C_SDA);
+                omap_cfg_reg(I2C_SCL);
+        }
+
+        return omap_plat_register_i2c_bus(bus_id, clkrate, info, len);
+}
diff --git a/arch/arm/mach-omap1/include/mach/lcd_dma.h b/arch/arm/mach-omap1/include/mach/lcd_dma.h
new file mode 100644
index 000000000000..d7a457bbcb7f
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/lcd_dma.h
@@ -0,0 +1,78 @@
+/*
+ *  arch/arm/mach-omap1/include/mach/lcd_dma.h
+ *
+ * Extracted from arch/arm/plat-omap/include/plat/dma.h
+ *  Copyright (C) 2003 Nokia Corporation
+ *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __MACH_OMAP1_LCD_DMA_H__
+#define __MACH_OMAP1_LCD_DMA_H__
+
+/* Hardware registers for LCD DMA */
+#define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
+#define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
+#define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
+#define OMAP1510_DMA_LCD_TOP_F1_U       (OMAP1510_DMA_LCD_BASE + 0x04)
+#define OMAP1510_DMA_LCD_BOT_F1_L       (OMAP1510_DMA_LCD_BASE + 0x06)
+#define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
+
+#define OMAP1610_DMA_LCD_BASE           (0xfffee300)
+#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
+#define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
+#define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
+#define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
+#define OMAP1610_DMA_LCD_TOP_B1_U       (OMAP1610_DMA_LCD_BASE + 0xca)
+#define OMAP1610_DMA_LCD_BOT_B1_L       (OMAP1610_DMA_LCD_BASE + 0xcc)
+#define OMAP1610_DMA_LCD_BOT_B1_U       (OMAP1610_DMA_LCD_BASE + 0xce)
+#define OMAP1610_DMA_LCD_TOP_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd0)
+#define OMAP1610_DMA_LCD_TOP_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd2)
+#define OMAP1610_DMA_LCD_BOT_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd4)
+#define OMAP1610_DMA_LCD_BOT_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd6)
+#define OMAP1610_DMA_LCD_SRC_EI_B1      (OMAP1610_DMA_LCD_BASE + 0xd8)
+#define OMAP1610_DMA_LCD_SRC_FI_B1_L    (OMAP1610_DMA_LCD_BASE + 0xda)
+#define OMAP1610_DMA_LCD_SRC_EN_B1      (OMAP1610_DMA_LCD_BASE + 0xe0)
+#define OMAP1610_DMA_LCD_SRC_FN_B1      (OMAP1610_DMA_LCD_BASE + 0xe4)
+#define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
+#define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
+
+/* LCD DMA block numbers */
+enum {
+        OMAP_LCD_DMA_B1_TOP,
+        OMAP_LCD_DMA_B1_BOTTOM,
+        OMAP_LCD_DMA_B2_TOP,
+        OMAP_LCD_DMA_B2_BOTTOM
+};
+
+/* LCD DMA functions */
+extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
+                                void *data);
+extern void omap_free_lcd_dma(void);
+extern void omap_setup_lcd_dma(void);
+extern void omap_enable_lcd_dma(void);
+extern void omap_stop_lcd_dma(void);
+extern void omap_set_lcd_dma_ext_controller(int external);
+extern void omap_set_lcd_dma_single_transfer(int single);
+extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
+                                int data_type);
+extern void omap_set_lcd_dma_b1_rotation(int rotate);
+extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
+extern void omap_set_lcd_dma_b1_mirror(int mirror);
+extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
+
+extern int omap_lcd_dma_running(void);
+
+#endif /* __MACH_OMAP1_LCD_DMA_H__ */
diff --git a/arch/arm/mach-omap1/include/mach/lcdc.h b/arch/arm/mach-omap1/include/mach/lcdc.h
new file mode 100644
index 000000000000..89bd703adaf6
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/lcdc.h
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-omap1/include/mach/lcdc.h
+ *
+ * Extracted from drivers/video/omap/lcdc.c
+ * Copyright (C) 2004 Nokia Corporation
+ * Author: Imre Deak <imre.deak@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __MACH_LCDC_H__
+#define __MACH_LCDC_H__
+
+#define OMAP_LCDC_BASE                  0xfffec000
+#define OMAP_LCDC_SIZE                  256
+#define OMAP_LCDC_IRQ                   INT_LCD_CTRL
+
+#define OMAP_LCDC_CONTROL               (OMAP_LCDC_BASE + 0x00)
+#define OMAP_LCDC_TIMING0               (OMAP_LCDC_BASE + 0x04)
+#define OMAP_LCDC_TIMING1               (OMAP_LCDC_BASE + 0x08)
+#define OMAP_LCDC_TIMING2               (OMAP_LCDC_BASE + 0x0c)
+#define OMAP_LCDC_STATUS                (OMAP_LCDC_BASE + 0x10)
+#define OMAP_LCDC_SUBPANEL              (OMAP_LCDC_BASE + 0x14)
+#define OMAP_LCDC_LINE_INT              (OMAP_LCDC_BASE + 0x18)
+#define OMAP_LCDC_DISPLAY_STATUS        (OMAP_LCDC_BASE + 0x1c)
+
+#define OMAP_LCDC_STAT_DONE             (1 << 0)
+#define OMAP_LCDC_STAT_VSYNC            (1 << 1)
+#define OMAP_LCDC_STAT_SYNC_LOST        (1 << 2)
+#define OMAP_LCDC_STAT_ABC              (1 << 3)
+#define OMAP_LCDC_STAT_LINE_INT         (1 << 4)
+#define OMAP_LCDC_STAT_FUF              (1 << 5)
+#define OMAP_LCDC_STAT_LOADED_PALETTE   (1 << 6)
+
+#define OMAP_LCDC_CTRL_LCD_EN           (1 << 0)
+#define OMAP_LCDC_CTRL_LCD_TFT          (1 << 7)
+#define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
+
+#define OMAP_LCDC_IRQ_VSYNC             (1 << 2)
+#define OMAP_LCDC_IRQ_DONE              (1 << 3)
+#define OMAP_LCDC_IRQ_LOADED_PALETTE    (1 << 4)
+#define OMAP_LCDC_IRQ_LINE_NIRQ         (1 << 5)
+#define OMAP_LCDC_IRQ_LINE              (1 << 6)
+#define OMAP_LCDC_IRQ_MASK              (((1 << 5) - 1) << 2)
+
+#endif /* __MACH_LCDC_H__ */
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 2a6d68aa3489..d9b8d82530ae 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -18,7 +18,8 @@
 #include <plat/mux.h>
 #include <plat/tc.h>
 
-extern int omap1_clk_init(void);
+#include "clock.h"
+
 extern void omap_check_revision(void);
 extern void omap_sram_init(void);
 extern void omapfb_reserve_sdram(void);
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
new file mode 100644
index 000000000000..3be11af687bb
--- /dev/null
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -0,0 +1,448 @@
+/*
+ * linux/arch/arm/mach-omap1/lcd_dma.c
+ *
+ * Extracted from arch/arm/plat-omap/dma.c
+ * Copyright (C) 2003 - 2008 Nokia Corporation
+ * Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
+ * Graphics DMA and LCD DMA graphics tranformations
+ * by Imre Deak <imre.deak@nokia.com>
+ * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
+ * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
+ * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Support functions for the OMAP internal DMA channels.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/lcdc.h>
+#include <plat/dma.h>
+
+int omap_lcd_dma_running(void)
+{
+        /*
+         * On OMAP1510, internal LCD controller will start the transfer
+         * when it gets enabled, so assume DMA running if LCD enabled.
+         */
+        if (cpu_is_omap1510())
+                if (omap_readw(OMAP_LCDC_CONTROL) & OMAP_LCDC_CTRL_LCD_EN)
+                        return 1;
+
+        /* Check if LCD DMA is running */
+        if (cpu_is_omap16xx())
+                if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
+                        return 1;
+
+        return 0;
+}
+
+static struct lcd_dma_info {
+        spinlock_t lock;
+        int reserved;
+        void (*callback)(u16 status, void *data);
+        void *cb_data;
+
+        int active;
+        unsigned long addr, size;
+        int rotate, data_type, xres, yres;
+        int vxres;
+        int mirror;
+        int xscale, yscale;
+        int ext_ctrl;
+        int src_port;
+        int single_transfer;
+} lcd_dma;
+
+void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
+                         int data_type)
+{
+        lcd_dma.addr = addr;
+        lcd_dma.data_type = data_type;
+        lcd_dma.xres = fb_xres;
+        lcd_dma.yres = fb_yres;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1);
+
+void omap_set_lcd_dma_src_port(int port)
+{
+        lcd_dma.src_port = port;
+}
+
+void omap_set_lcd_dma_ext_controller(int external)
+{
+        lcd_dma.ext_ctrl = external;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
+
+void omap_set_lcd_dma_single_transfer(int single)
+{
+        lcd_dma.single_transfer = single;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
+
+void omap_set_lcd_dma_b1_rotation(int rotate)
+{
+        if (cpu_is_omap1510()) {
+                printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
+                BUG();
+                return;
+        }
+        lcd_dma.rotate = rotate;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
+
+void omap_set_lcd_dma_b1_mirror(int mirror)
+{
+        if (cpu_is_omap1510()) {
+                printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
+                BUG();
+        }
+        lcd_dma.mirror = mirror;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
+
+void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
+{
+        if (cpu_is_omap1510()) {
+                printk(KERN_ERR "DMA virtual resulotion is not supported "
+                                "in 1510 mode\n");
+                BUG();
+        }
+        lcd_dma.vxres = vxres;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
+
+void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
+{
+        if (cpu_is_omap1510()) {
+                printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
+                BUG();
+        }
+        lcd_dma.xscale = xscale;
+        lcd_dma.yscale = yscale;
+}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
+
+static void set_b1_regs(void)
+{
+        unsigned long top, bottom;
+        int es;
+        u16 w;
+        unsigned long en, fn;
+        long ei, fi;
+        unsigned long vxres;
+        unsigned int xscale, yscale;
+
+        switch (lcd_dma.data_type) {
+        case OMAP_DMA_DATA_TYPE_S8:
+                es = 1;
+                break;
+        case OMAP_DMA_DATA_TYPE_S16:
+                es = 2;
+                break;
+        case OMAP_DMA_DATA_TYPE_S32:
+                es = 4;
+                break;
+        default:
+                BUG();
+                return;
+        }
+
+        vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
+        xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
+        yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
+        BUG_ON(vxres < lcd_dma.xres);
+
+#define PIXADDR(x, y) (lcd_dma.addr +                                   \
+                ((y) * vxres * yscale + (x) * xscale) * es)
+#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
+
+        switch (lcd_dma.rotate) {
+        case 0:
+                if (!lcd_dma.mirror) {
+                        top = PIXADDR(0, 0);
+                        bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
+                        /* 1510 DMA requires the bottom address to be 2 more
+                         * than the actual last memory access location. */
+                        if (cpu_is_omap1510() &&
+                                lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
+                                        bottom += 2;
+                        ei = PIXSTEP(0, 0, 1, 0);
+                        fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
+                } else {
+                        top = PIXADDR(lcd_dma.xres - 1, 0);
+                        bottom = PIXADDR(0, lcd_dma.yres - 1);
+                        ei = PIXSTEP(1, 0, 0, 0);
+                        fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
+                }
+                en = lcd_dma.xres;
+                fn = lcd_dma.yres;
+                break;
+        case 90:
+                if (!lcd_dma.mirror) {
+                        top = PIXADDR(0, lcd_dma.yres - 1);
+                        bottom = PIXADDR(lcd_dma.xres - 1, 0);
+                        ei = PIXSTEP(0, 1, 0, 0);
+                        fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
+                } else {
+                        top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
+                        bottom = PIXADDR(0, 0);
+                        ei = PIXSTEP(0, 1, 0, 0);
+                        fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
+                }
+                en = lcd_dma.yres;
+                fn = lcd_dma.xres;
+                break;
+        case 180:
+                if (!lcd_dma.mirror) {
+                        top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
+                        bottom = PIXADDR(0, 0);
+                        ei = PIXSTEP(1, 0, 0, 0);
+                        fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
+                } else {
+                        top = PIXADDR(0, lcd_dma.yres - 1);
+                        bottom = PIXADDR(lcd_dma.xres - 1, 0);
+                        ei = PIXSTEP(0, 0, 1, 0);
+                        fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
+                }
+                en = lcd_dma.xres;
+                fn = lcd_dma.yres;
+                break;
+        case 270:
+                if (!lcd_dma.mirror) {
+                        top = PIXADDR(lcd_dma.xres - 1, 0);
+                        bottom = PIXADDR(0, lcd_dma.yres - 1);
+                        ei = PIXSTEP(0, 0, 0, 1);
+                        fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
+                } else {
+                        top = PIXADDR(0, 0);
+                        bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
+                        ei = PIXSTEP(0, 0, 0, 1);
+                        fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
+                }
+                en = lcd_dma.yres;
+                fn = lcd_dma.xres;
+                break;
+        default:
+                BUG();
+                return; /* Suppress warning about uninitialized vars */
+        }
+
+        if (cpu_is_omap1510()) {
+                omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
+                omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
+                omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
+                omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
+
+                return;
+        }
+
+        /* 1610 regs */
+        omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
+        omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
+        omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
+        omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
+
+        omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
+        omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
+
+        w = omap_readw(OMAP1610_DMA_LCD_CSDP);
+        w &= ~0x03;
+        w |= lcd_dma.data_type;
+        omap_writew(w, OMAP1610_DMA_LCD_CSDP);
+
+        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+        /* Always set the source port as SDRAM for now*/
+        w &= ~(0x03 << 6);
+        if (lcd_dma.callback != NULL)
+                w |= 1 << 1;            /* Block interrupt enable */
+        else
+                w &= ~(1 << 1);
+        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+
+        if (!(lcd_dma.rotate || lcd_dma.mirror ||
+              lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
+                return;
+
+        w = omap_readw(OMAP1610_DMA_LCD_CCR);
+        /* Set the double-indexed addressing mode */
+        w |= (0x03 << 12);
+        omap_writew(w, OMAP1610_DMA_LCD_CCR);
+
+        omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
+        omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
+        omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
+}
+
+static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
+{
+        u16 w;
+
+        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+        if (unlikely(!(w & (1 << 3)))) {
+                printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
+                return IRQ_NONE;
+        }
+        /* Ack the IRQ */
+        w |= (1 << 3);
+        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+        lcd_dma.active = 0;
+        if (lcd_dma.callback != NULL)
+                lcd_dma.callback(w, lcd_dma.cb_data);
+
+        return IRQ_HANDLED;
+}
+
+int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
+                         void *data)
+{
+        spin_lock_irq(&lcd_dma.lock);
+        if (lcd_dma.reserved) {
+                spin_unlock_irq(&lcd_dma.lock);
+                printk(KERN_ERR "LCD DMA channel already reserved\n");
+                BUG();
+                return -EBUSY;
+        }
+        lcd_dma.reserved = 1;
+        spin_unlock_irq(&lcd_dma.lock);
+        lcd_dma.callback = callback;
+        lcd_dma.cb_data = data;
+        lcd_dma.active = 0;
+        lcd_dma.single_transfer = 0;
+        lcd_dma.rotate = 0;
+        lcd_dma.vxres = 0;
+        lcd_dma.mirror = 0;
+        lcd_dma.xscale = 0;
+        lcd_dma.yscale = 0;
+        lcd_dma.ext_ctrl = 0;
+        lcd_dma.src_port = 0;
+
+        return 0;
+}
+EXPORT_SYMBOL(omap_request_lcd_dma);
+
+void omap_free_lcd_dma(void)
+{
+        spin_lock(&lcd_dma.lock);
+        if (!lcd_dma.reserved) {
+                spin_unlock(&lcd_dma.lock);
+                printk(KERN_ERR "LCD DMA is not reserved\n");
+                BUG();
+                return;
+        }
+        if (!cpu_is_omap1510())
+                omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
+                            OMAP1610_DMA_LCD_CCR);
+        lcd_dma.reserved = 0;
+        spin_unlock(&lcd_dma.lock);
+}
+EXPORT_SYMBOL(omap_free_lcd_dma);
+
+void omap_enable_lcd_dma(void)
+{
+        u16 w;
+
+        /*
+         * Set the Enable bit only if an external controller is
+         * connected. Otherwise the OMAP internal controller will
+         * start the transfer when it gets enabled.
+         */
+        if (cpu_is_omap1510() || !lcd_dma.ext_ctrl)
+                return;
+
+        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+        w |= 1 << 8;
+        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+
+        lcd_dma.active = 1;
+
+        w = omap_readw(OMAP1610_DMA_LCD_CCR);
+        w |= 1 << 7;
+        omap_writew(w, OMAP1610_DMA_LCD_CCR);
+}
+EXPORT_SYMBOL(omap_enable_lcd_dma);
+
+void omap_setup_lcd_dma(void)
+{
+        BUG_ON(lcd_dma.active);
+        if (!cpu_is_omap1510()) {
+                /* Set some reasonable defaults */
+                omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
+                omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
+                omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
+        }
+        set_b1_regs();
+        if (!cpu_is_omap1510()) {
+                u16 w;
+
+                w = omap_readw(OMAP1610_DMA_LCD_CCR);
+                /*
+                 * If DMA was already active set the end_prog bit to have
+                 * the programmed register set loaded into the active
+                 * register set.
+                 */
+                w |= 1 << 11;           /* End_prog */
+                if (!lcd_dma.single_transfer)
+                        w |= (3 << 8);  /* Auto_init, repeat */
+                omap_writew(w, OMAP1610_DMA_LCD_CCR);
+        }
+}
+EXPORT_SYMBOL(omap_setup_lcd_dma);
+
+void omap_stop_lcd_dma(void)
+{
+        u16 w;
+
+        lcd_dma.active = 0;
+        if (cpu_is_omap1510() || !lcd_dma.ext_ctrl)
+                return;
+
+        w = omap_readw(OMAP1610_DMA_LCD_CCR);
+        w &= ~(1 << 7);
+        omap_writew(w, OMAP1610_DMA_LCD_CCR);
+
+        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+        w &= ~(1 << 8);
+        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+}
+EXPORT_SYMBOL(omap_stop_lcd_dma);
+
+static int __init omap_init_lcd_dma(void)
+{
+        int r;
+
+        if (cpu_is_omap16xx()) {
+                u16 w;
+
+                /* this would prevent OMAP sleep */
+                w = omap_readw(OMAP1610_DMA_LCD_CTRL);
+                w &= ~(1 << 8);
+                omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+        }
+
+        spin_lock_init(&lcd_dma.lock);
+
+        r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
+                        "LCD DMA", NULL);
+        if (r != 0)
+                printk(KERN_ERR "unable to request IRQ for LCD DMA "
+                               "(error %d)\n", r);
+
+        return r;
+}
+
+arch_initcall(omap_init_lcd_dma);
+
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 785371e982fc..07212cc621ae 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -50,12 +50,18 @@ MUX_CFG_7XX("E3_7XX_KBC4",        13,   25,    0,   24,   1, 0)
 
 MUX_CFG_7XX("AA17_7XX_USB_DM",     2,   21,    0,   20,   0, 0)
 MUX_CFG_7XX("W16_7XX_USB_PU_EN",   2,   25,    0,   24,   0, 0)
-MUX_CFG_7XX("W17_7XX_USB_VBUSI",   2,   29,    0,   28,   0, 0)
+MUX_CFG_7XX("W17_7XX_USB_VBUSI",   2,   29,    6,   28,   1, 0)
+MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3,    3,    1,    2,   0, 0)
+MUX_CFG_7XX("W19_7XX_USB_DCRST",   3,    7,    1,    6,   0, 0)
 
 /* MMC Pins */
 MUX_CFG_7XX("MMC_7XX_CMD",         2,    9,    0,    8,   1, 0)
 MUX_CFG_7XX("MMC_7XX_CLK",         2,   13,    0,   12,   1, 0)
 MUX_CFG_7XX("MMC_7XX_DAT0",        2,   17,    0,   16,   1, 0)
+
+/* I2C interface */
+MUX_CFG_7XX("I2C_7XX_SCL",         5,    1,    0,    0,   1, 0)
+MUX_CFG_7XX("I2C_7XX_SDA",         5,    5,    0,    0,   1, 0)
 };
 #define OMAP7XX_PINS_SZ         ARRAY_SIZE(omap7xx_pins)
 #else
diff --git a/arch/arm/mach-omap1/opp.h b/arch/arm/mach-omap1/opp.h
new file mode 100644
index 000000000000..07074d79adce
--- /dev/null
+++ b/arch/arm/mach-omap1/opp.h
@@ -0,0 +1,28 @@
+/*
+ *  linux/arch/arm/mach-omap1/opp.h
+ *
+ *  Copyright (C) 2004 - 2005 Nokia corporation
+ *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP1_OPP_H
+#define __ARCH_ARM_MACH_OMAP1_OPP_H
+
+#include <linux/types.h>
+
+struct mpu_rate {
+        unsigned long           rate;
+        unsigned long           xtal;
+        unsigned long           pll_rate;
+        __u16                   ckctl_val;
+        __u16                   dpllctl_val;
+};
+
+extern struct mpu_rate omap1_rate_table[];
+
+#endif
diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c
new file mode 100644
index 000000000000..75a546514994
--- /dev/null
+++ b/arch/arm/mach-omap1/opp_data.c
@@ -0,0 +1,59 @@
+/*
+ *  linux/arch/arm/mach-omap1/opp_data.c
+ *
+ *  Copyright (C) 2004 - 2005 Nokia corporation
+ *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "opp.h"
+
+/*-------------------------------------------------------------------------
+ * Omap1 MPU rate table
+ *-------------------------------------------------------------------------*/
+struct mpu_rate omap1_rate_table[] = {
+        /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
+         * NOTE: Comment order here is different from bits in CKCTL value:
+         * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
+         */
+#if defined(CONFIG_OMAP_ARM_216MHZ)
+        { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_195MHZ)
+        { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_192MHZ)
+        { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
+        { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
+        {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
+        {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
+        {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_182MHZ)
+        { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_168MHZ)
+        { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
+#endif
+#if defined(CONFIG_OMAP_ARM_150MHZ)
+        { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
+#endif
+#if defined(CONFIG_OMAP_ARM_120MHZ)
+        { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
+#endif
+#if defined(CONFIG_OMAP_ARM_96MHZ)
+        {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
+#endif
+#if defined(CONFIG_OMAP_ARM_60MHZ)
+        {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
+#endif
+#if defined(CONFIG_OMAP_ARM_30MHZ)
+        {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
+#endif
+        { 0, 0, 0, 0, 0 },
+};
+
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 7309aab305a9..76c11ee113e9 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -24,6 +24,18 @@ config ARCH_OMAP3430
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
         select ARCH_OMAP_OTG
 
+config OMAP_PACKAGE_CBC
+       bool
+
+config OMAP_PACKAGE_CBB
+       bool
+
+config OMAP_PACKAGE_CUS
+       bool
+
+config OMAP_PACKAGE_CBP
+       bool
+
 comment "OMAP Board Type"
         depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
 
@@ -52,14 +64,17 @@ config MACH_OMAP_2430SDP
 config MACH_OMAP3_BEAGLE
         bool "OMAP3 BEAGLE board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_LDP
         bool "OMAP3 LDP board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OVERO
         bool "Gumstix Overo board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP3EVM
         bool "OMAP 3530 EVM board"
@@ -68,14 +83,22 @@ config MACH_OMAP3EVM
 config MACH_OMAP3517EVM
         bool "OMAP3517/ AM3517 EVM board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP3_PANDORA
         bool "OMAP3 Pandora"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
+
+config MACH_OMAP3_TOUCHBOOK
+        bool "OMAP3 Touch Book"
+        depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select BACKLIGHT_CLASS_DEVICE
 
 config MACH_OMAP_3430SDP
         bool "OMAP 3430 SDP board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_NOKIA_N800
        bool
@@ -96,26 +119,33 @@ config MACH_NOKIA_N8X0
 config MACH_NOKIA_RX51
         bool "Nokia RX-51 board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_ZOOM2
         bool "OMAP3 Zoom2 board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_ZOOM3
         bool "OMAP3630 Zoom3 board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBP
 
 config MACH_CM_T35
         bool "CompuLab CM-T35 module"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CUS
+        select OMAP_MUX
 
 config MACH_IGEP0020
         bool "IGEP0020"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_3630SDP
         bool "OMAP3630 SDP board"
         depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        select OMAP_PACKAGE_CBP
 
 config MACH_OMAP_4430SDP
         bool "OMAP 4430 SDP board"
@@ -128,3 +158,15 @@ config OMAP3_EMU
         help
           Say Y here to enable debugging hardware of omap3
 
+config OMAP3_SDRC_AC_TIMING
+        bool "Enable SDRC AC timing register changes"
+        depends on ARCH_OMAP3 && ARCH_OMAP34XX
+        default n
+        help
+          If you know that none of your system initiators will attempt to
+          access SDRAM during CORE DVFS, select Y here.  This should boost
+          SDRAM performance at lower CORE OPPs.  There are relatively few
+          users who will wish to say yes at this point - almost everyone will
+          wish to say no.  Selecting yes without understanding what is
+          going on could result in system crashes;
+
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 32548a4510c5..b32678b848bc 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -6,11 +6,14 @@
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
 
 omap-2-3-common                         = irq.o sdrc.o omap_hwmod.o
+omap-3-4-common                         = dpll.o
 prcm-common                             = prcm.o powerdomain.o
-clock-common                            = clock.o clockdomain.o
+clock-common                            = clock.o clock_common_data.o clockdomain.o
 
 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common)
+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
+                            $(omap-3-4-common)
+obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
@@ -23,6 +26,9 @@ obj-$(CONFIG_ARCH_OMAP2420)		+= sram242x.o
 obj-$(CONFIG_ARCH_OMAP2430)             += sram243x.o
 obj-$(CONFIG_ARCH_OMAP3)                += sram34xx.o
 
+# Pin multiplexing
+obj-$(CONFIG_ARCH_OMAP3)                += mux34xx.o
+
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
 # obj-$(CONFIG_ARCH_OMAP3)              += sdrc3xxx.o
@@ -41,8 +47,11 @@ obj-$(CONFIG_ARCH_OMAP3)		+= cm.o
 obj-$(CONFIG_ARCH_OMAP4)                += cm4xxx.o
 
 # Clock framework
-obj-$(CONFIG_ARCH_OMAP2)                += clock24xx.o
-obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o
+obj-$(CONFIG_ARCH_OMAP2)                += clock2xxx.o clock2xxx_data.o
+obj-$(CONFIG_ARCH_OMAP2420)             += opp2420_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += clock34xx.o clock34xx_data.o
+obj-$(CONFIG_ARCH_OMAP2430)             += opp2430_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += clock44xx.o clock44xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)         += emu.o
@@ -55,6 +64,9 @@ iommu-$(CONFIG_ARCH_OMAP3)		+= omap3-iommu.o
 
 obj-$(CONFIG_OMAP_IOMMU)                += $(iommu-y)
 
+i2c-omap-$(CONFIG_I2C_OMAP)             := i2c.o
+obj-y                                   += $(i2c-omap-m) $(i2c-omap-y)
+
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
 obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
@@ -93,7 +105,8 @@ obj-$(CONFIG_MACH_CM_T35)		+= board-cm-t35.o \
                                            mmc-twl4030.o
 obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o \
                                            mmc-twl4030.o
-
+obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o \
+                                           mmc-twl4030.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o
 
 obj-$(CONFIG_MACH_OMAP3517EVM)     += board-am3517evm.o
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 5bda9fdbee9e..4cfb7b68dfad 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -31,7 +31,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/mcspi.h>
-#include <plat/mux.h>
 #include <plat/board.h>
 #include <plat/usb.h>
 #include <plat/common.h>
@@ -42,6 +41,7 @@
 #include <plat/control.h>
 #include <plat/gpmc-smc91x.h>
 
+#include "mux.h"
 #include "sdram-qimonda-hyb18m512160af-6.h"
 #include "mmc-twl4030.h"
 
@@ -625,7 +625,9 @@ static inline void board_smc91x_init(void)
 
 static void enable_board_wakeup_source(void)
 {
-        omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
+        /* T2 interrupt line (keypad) */
+        omap_mux_init_signal("sys_nirq",
+                OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
 static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
@@ -640,8 +642,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap_3430sdp_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap3430_i2c_init();
         platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
         if (omap_rev() > OMAP3430_REV_ES1_0)
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 348b70b98336..739059632811 100755
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -23,6 +23,7 @@
 
 #include <mach/board-zoom.h>
 
+#include "mux.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
@@ -48,7 +49,9 @@ static inline void board_smc91x_init(void)
 
 static void enable_board_wakeup_source(void)
 {
-        omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
+        /* T2 interrupt line (keypad) */
+        omap_mux_init_signal("sys_nirq",
+                OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
 }
 
 static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
@@ -82,8 +85,17 @@ static void __init omap_sdp_init_irq(void)
         omap_gpio_init();
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap_sdp_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
         zoom_peripherals_init();
         board_smc91x_init();
         enable_board_wakeup_source();
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 415a13d767cc..b4e6eca0e8a9 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -30,6 +30,8 @@
 #include <plat/common.h>
 #include <plat/usb.h>
 
+#include "mux.h"
+
 /*
  * Board initialization
  */
@@ -60,8 +62,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init am3517_evm_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         platform_add_devices(am3517_evm_devices,
                                 ARRAY_SIZE(am3517_evm_devices));
 
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 8a2ce77a02ec..fbbd68d69cc8 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -26,6 +26,7 @@
 #include <linux/leds.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -120,6 +121,12 @@ static void __init apollon_flash_init(void)
         apollon_flash_resource[0].end   = base + SZ_128K - 1;
 }
 
+static struct smc91x_platdata appolon_smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource apollon_smc91x_resources[] = {
         [0] = {
                 .flags  = IORESOURCE_MEM,
@@ -134,6 +141,9 @@ static struct resource apollon_smc91x_resources[] = {
 static struct platform_device apollon_smc91x_device = {
         .name           = "smc91x",
         .id             = -1,
+        .dev    = {
+                .platform_data  = &appolon_smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(apollon_smc91x_resources),
         .resource       = apollon_smc91x_resources,
 };
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 22c45290db63..1591aae64500 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -38,13 +38,13 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/mux.h>
 #include <plat/nand.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 
 #include <mach/hardware.h>
 
+#include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
 
@@ -482,8 +482,102 @@ static void __init cm_t35_map_io(void)
         omap2_map_common_io();
 }
 
+static struct omap_board_mux board_mux[] __initdata = {
+        /* nCS and IRQ for CM-T35 ethernet */
+        OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
+        OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
+
+        /* nCS and IRQ for SB-T35 ethernet */
+        OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0),
+        OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
+
+        /* PENDOWN GPIO */
+        OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+
+        /* mUSB */
+        OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+
+        /* MMC 2 */
+        OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+
+        /* McSPI 1 */
+        OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+
+        /* McSPI 4 */
+        OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP),
+
+        /* McBSP 2 */
+        OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+
+        /* serial ports */
+        OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
+        OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+
+        /* DSS */
+        OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+
+        /* TPS IRQ */
+        OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
+                  OMAP_PIN_INPUT_PULLUP),
+
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
 static void __init cm_t35_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
         omap_serial_init();
         cm_t35_init_i2c();
         cm_t35_init_nand();
@@ -492,8 +586,6 @@ static void __init cm_t35_init(void)
         cm_t35_init_led();
 
         usb_musb_init();
-
-        omap_cfg_reg(AF26_34XX_SYS_NIRQ);
 }
 
 MACHINE_START(CM_T35, "Compulab CM-T35")
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index fa62e80c13b7..44239e3ec02e 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -27,9 +27,9 @@
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/gpmc.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 
+#include "mux.h"
 #include "mmc-twl4030.h"
 
 #define IGEP2_SMSC911X_CS       5
@@ -203,8 +203,17 @@ static int __init igep2_i2c_init(void)
         return 0;
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init igep2_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         igep2_i2c_init();
         omap_serial_init();
         usb_musb_init();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index c062238fe881..37431738f1c2 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -43,6 +43,7 @@
 #include <plat/control.h>
 #include <plat/usb.h>
 
+#include "mux.h"
 #include "mmc-twl4030.h"
 
 #define LDP_SMSC911X_CS         1
@@ -374,8 +375,17 @@ static struct platform_device *ldp_devices[] __initdata = {
         &ldp_gpio_keys_device,
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap_ldp_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_i2c_init();
         platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
         ts_gpio = 54;
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 41480bd0e58a..6ada8029f9a8 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -41,10 +41,10 @@
 #include <plat/common.h>
 #include <plat/gpmc.h>
 #include <plat/nand.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/timer-gp.h>
 
+#include "mux.h"
 #include "mmc-twl4030.h"
 
 #define GPMC_CS0_BASE  0x60
@@ -140,10 +140,10 @@ static int beagle_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
         if (system_rev >= 0x20 && system_rev <= 0x34301000) {
-                omap_cfg_reg(AG9_34XX_GPIO23);
+                omap_mux_init_gpio(23, OMAP_PIN_INPUT);
                 mmc[0].gpio_wp = 23;
         } else {
-                omap_cfg_reg(AH8_34XX_GPIO29);
+                omap_mux_init_gpio(29, OMAP_PIN_INPUT);
         }
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
@@ -422,14 +422,23 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap3_beagle_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap3_beagle_i2c_init();
         platform_add_devices(omap3_beagle_devices,
                         ARRAY_SIZE(omap3_beagle_devices));
         omap_serial_init();
 
-        omap_cfg_reg(J25_34XX_GPIO170);
+        omap_mux_init_gpio(170, OMAP_PIN_INPUT);
         gpio_request(170, "DVI_nPD");
         /* REVISIT leave DVI powered down until it's needed ... */
         gpio_direction_output(170, true);
@@ -439,8 +448,8 @@ static void __init omap3_beagle_init(void)
         omap3beagle_flash_init();
 
         /* Ensure SDRC pins are mux'd for self-refresh */
-        omap_cfg_reg(H16_34XX_SDRC_CKE0);
-        omap_cfg_reg(H17_34XX_SDRC_CKE1);
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 }
 
 static void __init omap3_beagle_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 5efc2e9068db..18913e96e34d 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -38,11 +38,11 @@
 #include <asm/mach/map.h>
 
 #include <plat/board.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/common.h>
 #include <plat/mcspi.h>
 
+#include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
 
@@ -223,7 +223,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
-        omap_cfg_reg(L8_34XX_GPIO63);
+        omap_mux_init_gpio(63, OMAP_PIN_INPUT);
         mmc[0].gpio_cd = gpio + 0;
         twl4030_mmc_init(mmc);
 
@@ -422,9 +422,18 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap3_evm_init(void)
 {
         omap3_evm_get_revision();
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 
         omap3_evm_i2c_init();
 
@@ -440,24 +449,24 @@ static void __init omap3_evm_init(void)
 #endif
         if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
                 /* enable EHCI VBUS using GPIO22 */
-                omap_cfg_reg(AF9_34XX_GPIO22);
+                omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP);
                 gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS");
                 gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0);
                 gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1);
 
                 /* Select EHCI port on main board */
-                omap_cfg_reg(U3_34XX_GPIO61);
+                omap_mux_init_gpio(61, OMAP_PIN_INPUT_PULLUP);
                 gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port");
                 gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0);
                 gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0);
 
                 /* setup EHCI phy reset config */
-                omap_cfg_reg(AH14_34XX_GPIO21);
+                omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
                 ehci_pdata.reset_gpio_port[1] = 21;
 
         } else {
                 /* setup EHCI phy reset on MDC */
-                omap_cfg_reg(AF4_34XX_GPIO135_OUT);
+                omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
                 ehci_pdata.reset_gpio_port[1] = 135;
         }
         usb_musb_init();
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 2db5ba5b3bf7..6f6c601eeab7 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -40,8 +40,8 @@
 #include <mach/hardware.h>
 #include <plat/mcspi.h>
 #include <plat/usb.h>
-#include <plat/mux.h>
 
+#include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
 
@@ -98,10 +98,10 @@ static struct gpio_keys_button pandora_gpio_keys[] = {
         GPIO_BUTTON_LOW(103,    KEY_DOWN,       "down"),
         GPIO_BUTTON_LOW(96,     KEY_LEFT,       "left"),
         GPIO_BUTTON_LOW(98,     KEY_RIGHT,      "right"),
-        GPIO_BUTTON_LOW(111,    BTN_A,          "a"),
-        GPIO_BUTTON_LOW(106,    BTN_B,          "b"),
-        GPIO_BUTTON_LOW(109,    BTN_X,          "x"),
-        GPIO_BUTTON_LOW(101,    BTN_Y,          "y"),
+        GPIO_BUTTON_LOW(109,    KEY_KP1,        "game 1"),
+        GPIO_BUTTON_LOW(111,    KEY_KP2,        "game 2"),
+        GPIO_BUTTON_LOW(106,    KEY_KP3,        "game 3"),
+        GPIO_BUTTON_LOW(101,    KEY_KP4,        "game 4"),
         GPIO_BUTTON_LOW(102,    BTN_TL,         "l"),
         GPIO_BUTTON_LOW(97,     BTN_TL2,        "l2"),
         GPIO_BUTTON_LOW(105,    BTN_TR,         "r"),
@@ -315,7 +315,7 @@ static int __init omap3pandora_i2c_init(void)
         omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo,
                         ARRAY_SIZE(omap3pandora_i2c_boardinfo));
         /* i2c2 pins are not connected */
-        omap_register_i2c_bus(3, 400, NULL, 0);
+        omap_register_i2c_bus(3, 100, NULL, 0);
         return 0;
 }
 
@@ -368,23 +368,8 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
         }
 };
 
-static struct platform_device omap3pandora_lcd_device = {
-        .name           = "pandora_lcd",
-        .id             = -1,
-};
-
-static struct omap_lcd_config omap3pandora_lcd_config __initdata = {
-        .ctrl_name      = "internal",
-};
-
-static struct omap_board_config_kernel omap3pandora_config[] __initdata = {
-        { OMAP_TAG_LCD,         &omap3pandora_lcd_config },
-};
-
 static void __init omap3pandora_init_irq(void)
 {
-        omap_board_config = omap3pandora_config;
-        omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
         omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
                              mt46h32m32lf6_sdrc_params);
         omap_init_irq();
@@ -392,7 +377,6 @@ static void __init omap3pandora_init_irq(void)
 }
 
 static struct platform_device *omap3pandora_devices[] __initdata = {
-        &omap3pandora_lcd_device,
         &pandora_leds_gpio,
         &pandora_keys_gpio,
 };
@@ -409,8 +393,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap3pandora_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap3pandora_i2c_init();
         platform_add_devices(omap3pandora_devices,
                         ARRAY_SIZE(omap3pandora_devices));
@@ -423,8 +416,8 @@ static void __init omap3pandora_init(void)
         usb_musb_init();
 
         /* Ensure SDRC pins are mux'd for self-refresh */
-        omap_cfg_reg(H16_34XX_SDRC_CKE0);
-        omap_cfg_reg(H17_34XX_SDRC_CKE1);
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 }
 
 static void __init omap3pandora_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
new file mode 100644
index 000000000000..c9e5ebb4d91d
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -0,0 +1,572 @@
+/*
+ * linux/arch/arm/mach-omap2/board-omap3touchbook.c
+ *
+ * Copyright (C) 2009 Always Innovating
+ *
+ * Modified from mach-omap2/board-omap3beagleboard.c
+ *
+ * Initial code: Grégoire Gentil, Tim Yamin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+
+#include <plat/mcspi.h>
+#include <linux/spi/spi.h>
+
+#include <linux/spi/ads7846.h>
+
+#include <linux/regulator/machine.h>
+#include <linux/i2c/twl4030.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/flash.h>
+
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/gpmc.h>
+#include <plat/nand.h>
+#include <plat/usb.h>
+#include <plat/timer-gp.h>
+
+#include "mux.h"
+#include "mmc-twl4030.h"
+
+#include <asm/setup.h>
+
+#define GPMC_CS0_BASE  0x60
+#define GPMC_CS_SIZE   0x30
+
+#define NAND_BLOCK_SIZE         SZ_128K
+
+#define OMAP3_AC_GPIO           136
+#define OMAP3_TS_GPIO           162
+#define TB_BL_PWM_TIMER         9
+#define TB_KILL_POWER_GPIO      168
+
+unsigned long touchbook_revision;
+
+static struct mtd_partition omap3touchbook_nand_partitions[] = {
+        /* All the partition sizes are listed in terms of NAND block size */
+        {
+                .name           = "X-Loader",
+                .offset         = 0,
+                .size           = 4 * NAND_BLOCK_SIZE,
+                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+        },
+        {
+                .name           = "U-Boot",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
+                .size           = 15 * NAND_BLOCK_SIZE,
+                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
+        },
+        {
+                .name           = "U-Boot Env",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
+                .size           = 1 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "Kernel",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
+                .size           = 32 * NAND_BLOCK_SIZE,
+        },
+        {
+                .name           = "File System",
+                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x680000 */
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct omap_nand_platform_data omap3touchbook_nand_data = {
+        .options        = NAND_BUSWIDTH_16,
+        .parts          = omap3touchbook_nand_partitions,
+        .nr_parts       = ARRAY_SIZE(omap3touchbook_nand_partitions),
+        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
+        .nand_setup     = NULL,
+        .dev_ready      = NULL,
+};
+
+static struct resource omap3touchbook_nand_resource = {
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device omap3touchbook_nand_device = {
+        .name           = "omap2-nand",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &omap3touchbook_nand_data,
+        },
+        .num_resources  = 1,
+        .resource       = &omap3touchbook_nand_resource,
+};
+
+#include "sdram-micron-mt46h32m32lf-6.h"
+
+static struct twl4030_hsmmc_info mmc[] = {
+        {
+                .mmc            = 1,
+                .wires          = 8,
+                .gpio_wp        = 29,
+        },
+        {}      /* Terminator */
+};
+
+static struct platform_device omap3_touchbook_lcd_device = {
+        .name           = "omap3touchbook_lcd",
+        .id             = -1,
+};
+
+static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = {
+        .ctrl_name      = "internal",
+};
+
+static struct regulator_consumer_supply touchbook_vmmc1_supply = {
+        .supply                 = "vmmc",
+};
+
+static struct regulator_consumer_supply touchbook_vsim_supply = {
+        .supply                 = "vmmc_aux",
+};
+
+static struct gpio_led gpio_leds[];
+
+static int touchbook_twl_gpio_setup(struct device *dev,
+                unsigned gpio, unsigned ngpio)
+{
+        if (system_rev >= 0x20 && system_rev <= 0x34301000) {
+                omap_mux_init_gpio(23, OMAP_PIN_INPUT);
+                mmc[0].gpio_wp = 23;
+        } else {
+                omap_mux_init_gpio(29, OMAP_PIN_INPUT);
+        }
+        /* gpio + 0 is "mmc0_cd" (input/IRQ) */
+        mmc[0].gpio_cd = gpio + 0;
+        twl4030_mmc_init(mmc);
+
+        /* link regulators to MMC adapters */
+        touchbook_vmmc1_supply.dev = mmc[0].dev;
+        touchbook_vsim_supply.dev = mmc[0].dev;
+
+        /* REVISIT: need ehci-omap hooks for external VBUS
+         * power switch and overcurrent detect
+         */
+
+        gpio_request(gpio + 1, "EHCI_nOC");
+        gpio_direction_input(gpio + 1);
+
+        /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
+        gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
+        gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+
+        /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
+        gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
+
+        return 0;
+}
+
+static struct twl4030_gpio_platform_data touchbook_gpio_data = {
+        .gpio_base      = OMAP_MAX_GPIO_LINES,
+        .irq_base       = TWL4030_GPIO_IRQ_BASE,
+        .irq_end        = TWL4030_GPIO_IRQ_END,
+        .use_leds       = true,
+        .pullups        = BIT(1),
+        .pulldowns      = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
+                                | BIT(15) | BIT(16) | BIT(17),
+        .setup          = touchbook_twl_gpio_setup,
+};
+
+static struct regulator_consumer_supply touchbook_vdac_supply = {
+        .supply         = "vdac",
+        .dev            = &omap3_touchbook_lcd_device.dev,
+};
+
+static struct regulator_consumer_supply touchbook_vdvi_supply = {
+        .supply         = "vdvi",
+        .dev            = &omap3_touchbook_lcd_device.dev,
+};
+
+/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+static struct regulator_init_data touchbook_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &touchbook_vmmc1_supply,
+};
+
+/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
+static struct regulator_init_data touchbook_vsim = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 3000000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &touchbook_vsim_supply,
+};
+
+/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
+static struct regulator_init_data touchbook_vdac = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &touchbook_vdac_supply,
+};
+
+/* VPLL2 for digital video outputs */
+static struct regulator_init_data touchbook_vpll2 = {
+        .constraints = {
+                .name                   = "VDVI",
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &touchbook_vdvi_supply,
+};
+
+static struct twl4030_usb_data touchbook_usb_data = {
+        .usb_mode       = T2_USB_MODE_ULPI,
+};
+
+static struct twl4030_codec_audio_data touchbook_audio_data = {
+        .audio_mclk = 26000000,
+};
+
+static struct twl4030_codec_data touchbook_codec_data = {
+        .audio_mclk = 26000000,
+        .audio = &touchbook_audio_data,
+};
+
+static struct twl4030_platform_data touchbook_twldata = {
+        .irq_base       = TWL4030_IRQ_BASE,
+        .irq_end        = TWL4030_IRQ_END,
+
+        /* platform_data for children goes here */
+        .usb            = &touchbook_usb_data,
+        .gpio           = &touchbook_gpio_data,
+        .codec          = &touchbook_codec_data,
+        .vmmc1          = &touchbook_vmmc1,
+        .vsim           = &touchbook_vsim,
+        .vdac           = &touchbook_vdac,
+        .vpll2          = &touchbook_vpll2,
+};
+
+static struct i2c_board_info __initdata touchbook_i2c_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("twl4030", 0x48),
+                .flags = I2C_CLIENT_WAKE,
+                .irq = INT_34XX_SYS_NIRQ,
+                .platform_data = &touchbook_twldata,
+        },
+};
+
+static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("bq27200", 0x55),
+        },
+};
+
+static int __init omap3_touchbook_i2c_init(void)
+{
+        /* Standard TouchBook bus */
+        omap_register_i2c_bus(1, 2600, touchbook_i2c_boardinfo,
+                        ARRAY_SIZE(touchbook_i2c_boardinfo));
+
+        /* Additional TouchBook bus */
+        omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
+                        ARRAY_SIZE(touchBook_i2c_boardinfo));
+
+        return 0;
+}
+
+static void __init omap3_ads7846_init(void)
+{
+        if (gpio_request(OMAP3_TS_GPIO, "ads7846_pen_down")) {
+                printk(KERN_ERR "Failed to request GPIO %d for "
+                                "ads7846 pen down IRQ\n", OMAP3_TS_GPIO);
+                return;
+        }
+
+        gpio_direction_input(OMAP3_TS_GPIO);
+        omap_set_gpio_debounce(OMAP3_TS_GPIO, 1);
+        omap_set_gpio_debounce_time(OMAP3_TS_GPIO, 0xa);
+}
+
+static struct ads7846_platform_data ads7846_config = {
+        .x_min                  = 100,
+        .y_min                  = 265,
+        .x_max                  = 3950,
+        .y_max                  = 3750,
+        .x_plate_ohms           = 40,
+        .pressure_max           = 255,
+        .debounce_max           = 10,
+        .debounce_tol           = 5,
+        .debounce_rep           = 1,
+        .gpio_pendown           = OMAP3_TS_GPIO,
+        .keep_vref_on           = 1,
+};
+
+static struct omap2_mcspi_device_config ads7846_mcspi_config = {
+        .turbo_mode     = 0,
+        .single_channel = 1,    /* 0: slave, 1: master */
+};
+
+static struct spi_board_info omap3_ads7846_spi_board_info[] __initdata = {
+        {
+                .modalias               = "ads7846",
+                .bus_num                = 4,
+                .chip_select            = 0,
+                .max_speed_hz           = 1500000,
+                .controller_data        = &ads7846_mcspi_config,
+                .irq                    = OMAP_GPIO_IRQ(OMAP3_TS_GPIO),
+                .platform_data          = &ads7846_config,
+        }
+};
+
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "touchbook::usr0",
+                .default_trigger        = "heartbeat",
+                .gpio                   = 150,
+        },
+        {
+                .name                   = "touchbook::usr1",
+                .default_trigger        = "mmc0",
+                .gpio                   = 149,
+        },
+        {
+                .name                   = "touchbook::pmu_stat",
+                .gpio                   = -EINVAL,      /* gets replaced */
+                .active_low             = true,
+        },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        },
+};
+
+static struct gpio_keys_button gpio_buttons[] = {
+        {
+                .code                   = BTN_EXTRA,
+                .gpio                   = 7,
+                .desc                   = "user",
+                .wakeup                 = 1,
+        },
+        {
+                .code                   = KEY_POWER,
+                .gpio                   = 183,
+                .desc                   = "power",
+                .wakeup                 = 1,
+        },
+};
+
+static struct gpio_keys_platform_data gpio_key_info = {
+        .buttons        = gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(gpio_buttons),
+};
+
+static struct platform_device keys_gpio = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_key_info,
+        },
+};
+
+static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = {
+        { OMAP_TAG_LCD,         &omap3_touchbook_lcd_config },
+};
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
+static void __init omap3_touchbook_init_irq(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_board_config = omap3_touchbook_config;
+        omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
+        omap_init_irq();
+#ifdef CONFIG_OMAP_32K_TIMER
+        omap2_gp_clockevent_set_gptimer(12);
+#endif
+        omap_gpio_init();
+}
+
+static struct platform_device *omap3_touchbook_devices[] __initdata = {
+        &omap3_touchbook_lcd_device,
+        &leds_gpio,
+        &keys_gpio,
+};
+
+static void __init omap3touchbook_flash_init(void)
+{
+        u8 cs = 0;
+        u8 nandcs = GPMC_CS_NUM + 1;
+
+        u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
+
+        /* find out the chip-select on which NAND exists */
+        while (cs < GPMC_CS_NUM) {
+                u32 ret = 0;
+                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+
+                if ((ret & 0xC00) == 0x800) {
+                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
+                        if (nandcs > GPMC_CS_NUM)
+                                nandcs = cs;
+                }
+                cs++;
+        }
+
+        if (nandcs > GPMC_CS_NUM) {
+                printk(KERN_INFO "NAND: Unable to find configuration "
+                                 "in GPMC\n ");
+                return;
+        }
+
+        if (nandcs < GPMC_CS_NUM) {
+                omap3touchbook_nand_data.cs = nandcs;
+                omap3touchbook_nand_data.gpmc_cs_baseaddr = (void *)
+                        (gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
+                omap3touchbook_nand_data.gpmc_baseaddr =
+                                                (void *) (gpmc_base_add);
+
+                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
+                if (platform_device_register(&omap3touchbook_nand_device) < 0)
+                        printk(KERN_ERR "Unable to register NAND device\n");
+        }
+}
+
+static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+
+        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+
+        .phy_reset  = true,
+        .reset_gpio_port[0]  = -EINVAL,
+        .reset_gpio_port[1]  = 147,
+        .reset_gpio_port[2]  = -EINVAL
+};
+
+static void omap3_touchbook_poweroff(void)
+{
+        int r;
+
+        r = gpio_request(TB_KILL_POWER_GPIO, "DVI reset");
+        if (r < 0) {
+                printk(KERN_ERR "Unable to get kill power GPIO\n");
+                return;
+        }
+
+        gpio_direction_output(TB_KILL_POWER_GPIO, 0);
+}
+
+static void __init early_touchbook_revision(char **p)
+{
+        if (!*p)
+                return;
+
+        strict_strtoul(*p, 10, &touchbook_revision);
+}
+__early_param("tbr=", early_touchbook_revision);
+
+static void __init omap3_touchbook_init(void)
+{
+        pm_power_off = omap3_touchbook_poweroff;
+
+        omap3_touchbook_i2c_init();
+        platform_add_devices(omap3_touchbook_devices,
+                        ARRAY_SIZE(omap3_touchbook_devices));
+        omap_serial_init();
+
+        omap_mux_init_gpio(170, OMAP_PIN_INPUT);
+        gpio_request(176, "DVI_nPD");
+        /* REVISIT leave DVI powered down until it's needed ... */
+        gpio_direction_output(176, true);
+
+        /* Touchscreen and accelerometer */
+        spi_register_board_info(omap3_ads7846_spi_board_info,
+                                ARRAY_SIZE(omap3_ads7846_spi_board_info));
+        omap3_ads7846_init();
+        usb_musb_init();
+        usb_ehci_init(&ehci_pdata);
+        omap3touchbook_flash_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
+}
+
+static void __init omap3_touchbook_map_io(void)
+{
+        omap2_set_globals_343x();
+        omap2_map_common_io();
+}
+
+MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
+        /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
+        .phys_io        = 0x48000000,
+        .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_touchbook_map_io,
+        .init_irq       = omap3_touchbook_init_irq,
+        .init_machine   = omap3_touchbook_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 52dfd51a938e..5b78a87217e0 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -44,9 +44,9 @@
 #include <plat/gpmc.h>
 #include <mach/hardware.h>
 #include <plat/nand.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 
+#include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
 
@@ -405,9 +405,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
 
 static void __init overo_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         overo_i2c_init();
         platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
         omap_serial_init();
@@ -418,8 +426,8 @@ static void __init overo_init(void)
         overo_init_smsc911x();
 
         /* Ensure SDRC pins are mux'd for self-refresh */
-        omap_cfg_reg(H16_34XX_SDRC_CKE0);
-        omap_cfg_reg(H17_34XX_SDRC_CKE1);
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 
         if ((gpio_request(OVERO_GPIO_W2W_NRESET,
                           "OVERO_GPIO_W2W_NRESET") == 0) &&
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 15ce6514c5fd..bf26ad31f9ba 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -33,6 +33,7 @@
 #include <plat/onenand.h>
 #include <plat/gpmc-smc91x.h>
 
+#include "mux.h"
 #include "mmc-twl4030.h"
 
 #define SYSTEM_REV_B_USES_VAUX3 0x1699
@@ -59,7 +60,7 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
                 .bus_num                = 4,
                 .chip_select            = 0,
                 .max_speed_hz           = 48000000,
-                .mode                   = SPI_MODE_2,
+                .mode                   = SPI_MODE_3,
                 .controller_data        = &wl1251_mcspi_config,
                 .platform_data          = &wl1251_pdata,
         },
@@ -630,9 +631,9 @@ static struct omap_smc91x_platform_data board_smc91x_data = {
 
 static void __init board_smc91x_init(void)
 {
-        omap_cfg_reg(U8_34XX_GPIO54_DOWN);
-        omap_cfg_reg(G25_34XX_GPIO86_OUT);
-        omap_cfg_reg(H19_34XX_GPIO164_OUT);
+        omap_mux_init_gpio(54, OMAP_PIN_INPUT_PULLDOWN);
+        omap_mux_init_gpio(86, OMAP_PIN_OUTPUT);
+        omap_mux_init_gpio(164, OMAP_PIN_OUTPUT);
 
         gpmc_smc91x_init(&board_smc91x_data);
 }
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 1bb1de245917..67bb3476b707 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -23,13 +23,14 @@
 #include <asm/mach/map.h>
 
 #include <plat/mcspi.h>
-#include <plat/mux.h>
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 
+#include "mux.h"
+
 struct omap_sdrc_params *rx51_get_sdram_timings(void);
 
 static struct omap_lcd_config rx51_lcd_config = {
@@ -69,15 +70,24 @@ static void __init rx51_init_irq(void)
 
 extern void __init rx51_peripherals_init(void);
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init rx51_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_serial_init();
         usb_musb_init();
         rx51_peripherals_init();
 
         /* Ensure SDRC pins are mux'd for self-refresh */
-        omap_cfg_reg(H16_34XX_SDRC_CKE0);
-        omap_cfg_reg(H17_34XX_SDRC_CKE1);
+        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 }
 
 static void __init rx51_map_io(void)
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index f14baa392760..258794db488f 100755
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -152,14 +152,20 @@ static struct regulator_init_data zoom_vsim = {
 
 static struct twl4030_hsmmc_info mmc[] __initdata = {
         {
+                .name           = "external",
                 .mmc            = 1,
                 .wires          = 4,
                 .gpio_wp        = -EINVAL,
+                .power_saving   = true,
         },
         {
+                .name           = "internal",
                 .mmc            = 2,
-                .wires          = 4,
+                .wires          = 8,
+                .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
+                .nonremovable   = true,
+                .power_saving   = true,
         },
         {}      /* Terminator */
 };
@@ -167,11 +173,8 @@ static struct twl4030_hsmmc_info mmc[] __initdata = {
 static int zoom_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
-        /* gpio + 0 is "mmc0_cd" (input/IRQ),
-         * gpio + 1 is "mmc1_cd" (input/IRQ)
-         */
+        /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
-        mmc[1].gpio_cd = gpio + 1;
         twl4030_mmc_init(mmc);
 
         /* link regulators to MMC adapters ... we "know" the
@@ -236,6 +239,7 @@ static struct twl4030_platform_data zoom_twldata = {
         .gpio           = &zoom_gpio_data,
         .keypad         = &zoom_kp_twl4030_data,
         .codec          = &zoom_codec_data,
+        .vmmc1          = &zoom_vmmc1,
         .vmmc2          = &zoom_vmmc2,
         .vsim           = &zoom_vsim,
 
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index d94d047c7dce..bb87cf7878ff 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -23,6 +23,7 @@
 
 #include <mach/board-zoom.h>
 
+#include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 
 static void __init omap_zoom2_init_irq(void)
@@ -68,8 +69,17 @@ static struct twl4030_platform_data zoom2_twldata = {
 
 #endif
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap_zoom2_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         zoom_peripherals_init();
         zoom_debugboard_init();
 }
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c
index 8d965a6516c8..a9fe9181b010 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom3.c
@@ -21,6 +21,7 @@
 #include <plat/common.h>
 #include <plat/board.h>
 
+#include "mux.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
 static void __init omap_zoom_map_io(void)
@@ -42,8 +43,17 @@ static void __init omap_zoom_init_irq(void)
         omap_gpio_init();
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap_zoom_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
         zoom_peripherals_init();
         zoom_debugboard_init();
 }
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 4716206547ac..759c72a48f7f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -70,9 +70,41 @@
 u8 cpu_mask;
 
 /*-------------------------------------------------------------------------
- * OMAP2/3 specific clock functions
+ * OMAP2/3/4 specific clock functions
  *-------------------------------------------------------------------------*/
 
+void omap2_init_dpll_parent(struct clk *clk)
+{
+        u32 v;
+        struct dpll_data *dd;
+
+        dd = clk->dpll_data;
+        if (!dd)
+                return;
+
+        /* Return bypass rate if DPLL is bypassed */
+        v = __raw_readl(dd->control_reg);
+        v &= dd->enable_mask;
+        v >>= __ffs(dd->enable_mask);
+
+        /* Reparent in case the dpll is in bypass */
+        if (cpu_is_omap24xx()) {
+                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
+                        clk_reparent(clk, dd->clk_bypass);
+        } else if (cpu_is_omap34xx()) {
+                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
+                        clk_reparent(clk, dd->clk_bypass);
+        } else if (cpu_is_omap44xx()) {
+                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
+                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
+                        clk_reparent(clk, dd->clk_bypass);
+        }
+        return;
+}
+
 /**
  * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
  * @clk: struct clk *
@@ -149,6 +181,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
  * clockdomain pointer, and save it into the struct clk.  Intended to be
  * called during clk_register().  No return value.
  */
+#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
 void omap2_init_clk_clkdm(struct clk *clk)
 {
         struct clockdomain *clkdm;
@@ -166,6 +199,7 @@ void omap2_init_clk_clkdm(struct clk *clk)
                          "clkdm %s\n", clk->name, clk->clkdm_name);
         }
 }
+#endif
 
 /**
  * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
@@ -247,6 +281,11 @@ u32 omap2_get_dpll_rate(struct clk *clk)
                 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP3XXX_EN_DPLL_FRBYPASS)
                         return dd->clk_bypass->rate;
+        } else if (cpu_is_omap44xx()) {
+                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
+                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
+                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
+                        return dd->clk_bypass->rate;
         }
 
         v = __raw_readl(dd->mult_div1_reg);
@@ -437,8 +476,10 @@ void omap2_clk_disable(struct clk *clk)
                 _omap2_clk_disable(clk);
                 if (clk->parent)
                         omap2_clk_disable(clk->parent);
+#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
                 if (clk->clkdm)
                         omap2_clkdm_clk_disable(clk->clkdm, clk);
+#endif
 
         }
 }
@@ -448,8 +489,10 @@ int omap2_clk_enable(struct clk *clk)
         int ret = 0;
 
         if (clk->usecount++ == 0) {
+#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
                 if (clk->clkdm)
                         omap2_clkdm_clk_enable(clk->clkdm, clk);
+#endif
 
                 if (clk->parent) {
                         ret = omap2_clk_enable(clk->parent);
@@ -468,8 +511,10 @@ int omap2_clk_enable(struct clk *clk)
         return ret;
 
 err:
+#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
         if (clk->clkdm)
                 omap2_clkdm_clk_disable(clk->clkdm, clk);
+#endif
         clk->usecount--;
         return ret;
 }
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 43b6bedaafd6..93c48df3b5b1 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -1,8 +1,8 @@
 /*
  *  linux/arch/arm/mach-omap2/clock.h
  *
- *  Copyright (C) 2005-2008 Texas Instruments, Inc.
- *  Copyright (C) 2004-2008 Nokia Corporation
+ *  Copyright (C) 2005-2009 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2009 Nokia Corporation
  *
  *  Contacts:
  *  Richard Woodruff <r-woodruff2@ti.com>
@@ -36,6 +36,17 @@
 #define OMAP3XXX_EN_DPLL_FRBYPASS               0x6
 #define OMAP3XXX_EN_DPLL_LOCKED                 0x7
 
+/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
+#define OMAP4XXX_EN_DPLL_MNBYPASS               0x4
+#define OMAP4XXX_EN_DPLL_LPBYPASS               0x5
+#define OMAP4XXX_EN_DPLL_FRBYPASS               0x6
+#define OMAP4XXX_EN_DPLL_LOCKED                 0x7
+
+/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
+#define DPLL_LOW_POWER_STOP     0x1
+#define DPLL_LOW_POWER_BYPASS   0x5
+#define DPLL_LOCKED             0x7
+
 int omap2_clk_init(void);
 int omap2_clk_enable(struct clk *clk);
 void omap2_clk_disable(struct clk *clk);
@@ -44,6 +55,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
+unsigned long omap3_dpll_recalc(struct clk *clk);
+unsigned long omap3_clkoutx2_recalc(struct clk *clk);
+void omap3_dpll_allow_idle(struct clk *clk);
+void omap3_dpll_deny_idle(struct clk *clk);
+u32 omap3_dpll_autoidle_read(struct clk *clk);
+int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
+int omap3_noncore_dpll_enable(struct clk *clk);
+void omap3_noncore_dpll_disable(struct clk *clk);
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 void omap2_clk_disable_unused(struct clk *clk);
@@ -63,6 +82,7 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 u32 omap2_get_dpll_rate(struct clk *clk);
+void omap2_init_dpll_parent(struct clk *clk);
 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
 void omap2_clk_prepare_for_reboot(void);
 int omap2_dflt_clk_enable(struct clk *clk);
@@ -72,29 +92,17 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
                                 u8 *idlest_bit);
 
+extern u8 cpu_mask;
+
 extern const struct clkops clkops_omap2_dflt_wait;
 extern const struct clkops clkops_omap2_dflt;
 
-extern u8 cpu_mask;
+extern struct clk_functions omap2_clk_functions;
+extern struct clk *vclk, *sclk;
 
-/* clksel_rate data common to 24xx/343x */
-static const struct clksel_rate gpt_32k_rates[] = {
-         { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
-         { .div = 0 }
-};
-
-static const struct clksel_rate gpt_sys_rates[] = {
-         { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
-         { .div = 0 }
-};
-
-static const struct clksel_rate gfx_l3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
-        { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
-        { .div = 0 }
-};
+extern const struct clksel_rate gpt_32k_rates[];
+extern const struct clksel_rate gpt_sys_rates[];
+extern const struct clksel_rate gfx_l3_rates[];
 
 
 #endif
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
deleted file mode 100644
index 845b478ebeee..000000000000
--- a/arch/arm/mach-omap2/clock24xx.c
+++ /dev/null
@@ -1,805 +0,0 @@
-/*
- *  linux/arch/arm/mach-omap2/clock.c
- *
- *  Copyright (C) 2005-2008 Texas Instruments, Inc.
- *  Copyright (C) 2004-2008 Nokia Corporation
- *
- *  Contacts:
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Paul Walmsley
- *
- *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
- *  Gordon McNutt and RidgeRun, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#undef DEBUG
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/cpufreq.h>
-#include <linux/bitops.h>
-
-#include <plat/clock.h>
-#include <plat/sram.h>
-#include <plat/prcm.h>
-#include <asm/div64.h>
-#include <asm/clkdev.h>
-
-#include <plat/sdrc.h>
-#include "clock.h"
-#include "prm.h"
-#include "prm-regbits-24xx.h"
-#include "cm.h"
-#include "cm-regbits-24xx.h"
-
-static const struct clkops clkops_oscck;
-static const struct clkops clkops_fixed;
-
-static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
-                                           void __iomem **idlest_reg,
-                                           u8 *idlest_bit);
-
-/* 2430 I2CHS has non-standard IDLEST register */
-static const struct clkops clkops_omap2430_i2chs_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_idlest    = omap2430_clk_i2chs_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
-};
-
-#include "clock24xx.h"
-
-struct omap_clk {
-        u32             cpu;
-        struct clk_lookup lk;
-};
-
-#define CLK(dev, con, ck, cp)           \
-        {                               \
-                 .cpu = cp,             \
-                .lk = {                 \
-                        .dev_id = dev,  \
-                        .con_id = con,  \
-                        .clk = ck,      \
-                },                      \
-        }
-
-#define CK_243X                 RATE_IN_243X
-#define CK_242X                 RATE_IN_242X
-
-static struct omap_clk omap24xx_clks[] = {
-        /* external root sources */
-        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X | CK_242X),
-        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
-        CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X | CK_242X),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X | CK_242X),
-        CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X | CK_242X),
-        /* internal analog sources */
-        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X | CK_242X),
-        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X | CK_242X),
-        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X | CK_242X),
-        /* internal prcm root sources */
-        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X | CK_242X),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_243X | CK_242X),
-        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X | CK_242X),
-        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X | CK_242X),
-        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X | CK_242X),
-        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X | CK_242X),
-        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
-        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X | CK_242X),
-        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
-        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
-        CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
-        /* mpu domain clocks */
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X | CK_242X),
-        /* dsp domain clocks */
-        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X | CK_242X),
-        CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
-        CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
-        CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
-        CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
-        CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
-        /* GFX domain clocks */
-        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X | CK_242X),
-        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X | CK_242X),
-        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X | CK_242X),
-        /* Modem domain clocks */
-        CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
-        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
-        /* DSS domain clocks */
-        CLK("omapdss",  "ick",          &dss_ick,       CK_243X | CK_242X),
-        CLK("omapdss",  "dss1_fck",     &dss1_fck,      CK_243X | CK_242X),
-        CLK("omapdss",  "dss2_fck",     &dss2_fck,      CK_243X | CK_242X),
-        CLK("omapdss",  "tv_fck",       &dss_54m_fck,   CK_243X | CK_242X),
-        /* L3 domain clocks */
-        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X | CK_242X),
-        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X | CK_242X),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X | CK_242X),
-        /* L4 domain clocks */
-        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X | CK_242X),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X | CK_242X),
-        /* virtual meta-group clock */
-        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
-        /* general l4 interface ck, multi-parent functional clk */
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X | CK_242X),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X | CK_242X),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X | CK_242X),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X | CK_242X),
-        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_243X | CK_242X),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X | CK_242X),
-        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_243X | CK_242X),
-        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
-        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_243X),
-        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
-        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_243X),
-        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
-        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_243X),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X | CK_242X),
-        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_243X | CK_242X),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X | CK_242X),
-        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_243X | CK_242X),
-        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
-        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_243X),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X | CK_242X),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X | CK_242X),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X | CK_242X),
-        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X | CK_242X),
-        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X | CK_242X),
-        CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_243X | CK_242X),
-        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X | CK_242X),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X | CK_242X),
-        CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
-        CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X | CK_242X),
-        CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X | CK_242X),
-        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
-        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X | CK_242X),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X | CK_242X),
-        CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
-        CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X | CK_242X),
-        CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
-        CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X | CK_242X),
-        CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X | CK_242X),
-        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_243X | CK_242X),
-        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_242X),
-        CLK("i2c_omap.1", "fck",        &i2chs1_fck,    CK_243X),
-        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_243X | CK_242X),
-        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_242X),
-        CLK("i2c_omap.2", "fck",        &i2chs2_fck,    CK_243X),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X | CK_242X),
-        CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
-        CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
-        CLK(NULL,       "des_ick",      &des_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "sha_ick",      &sha_ick,       CK_243X | CK_242X),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "aes_ick",      &aes_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X | CK_242X),
-        CLK("musb_hdrc",        "ick",  &usbhs_ick,     CK_243X),
-        CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
-        CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
-        CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
-        CLK("mmci-omap-hs.1", "fck",    &mmchs2_fck,    CK_243X),
-        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
-        CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
-        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
-        CLK("mmci-omap-hs.0", "mmchsdb_fck",    &mmchsdb1_fck,  CK_243X),
-        CLK("mmci-omap-hs.1", "mmchsdb_fck",    &mmchsdb2_fck,  CK_243X),
-};
-
-/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
-#define EN_APLL_STOPPED                 0
-#define EN_APLL_LOCKED                  3
-
-/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
-#define APLLS_CLKIN_19_2MHZ             0
-#define APLLS_CLKIN_13MHZ               2
-#define APLLS_CLKIN_12MHZ               3
-
-/* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
-
-static struct prcm_config *curr_prcm_set;
-static struct clk *vclk;
-static struct clk *sclk;
-
-static void __iomem *prcm_clksrc_ctrl;
-
-/*-------------------------------------------------------------------------
- * Omap24xx specific clock functions
- *-------------------------------------------------------------------------*/
-
-/**
- * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
- * @clk: struct clk * being enabled
- * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
- * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
- *
- * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
- * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE.  This custom function
- * passes back the correct CM_IDLEST register address for I2CHS
- * modules.  No return value.
- */
-static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
-                                           void __iomem **idlest_reg,
-                                           u8 *idlest_bit)
-{
-        *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
-        *idlest_bit = clk->enable_bit;
-}
-
-
-/**
- * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
- * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
- *
- * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
- * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
- * (the latter is unusual).  This currently should be called with
- * struct clk *dpll_ck, which is a composite clock of dpll_ck and
- * core_ck.
- */
-static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
-{
-        long long core_clk;
-        u32 v;
-
-        core_clk = omap2_get_dpll_rate(clk);
-
-        v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        v &= OMAP24XX_CORE_CLK_SRC_MASK;
-
-        if (v == CORE_CLK_SRC_32K)
-                core_clk = 32768;
-        else
-                core_clk *= v;
-
-        return core_clk;
-}
-
-static int omap2_enable_osc_ck(struct clk *clk)
-{
-        u32 pcc;
-
-        pcc = __raw_readl(prcm_clksrc_ctrl);
-
-        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-
-        return 0;
-}
-
-static void omap2_disable_osc_ck(struct clk *clk)
-{
-        u32 pcc;
-
-        pcc = __raw_readl(prcm_clksrc_ctrl);
-
-        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
-}
-
-static const struct clkops clkops_oscck = {
-        .enable         = &omap2_enable_osc_ck,
-        .disable        = &omap2_disable_osc_ck,
-};
-
-#ifdef OLD_CK
-/* Recalculate SYST_CLK */
-static void omap2_sys_clk_recalc(struct clk * clk)
-{
-        u32 div = PRCM_CLKSRC_CTRL;
-        div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
-        div >>= clk->rate_offset;
-        clk->rate = (clk->parent->rate / div);
-        propagate_rate(clk);
-}
-#endif  /* OLD_CK */
-
-/* Enable an APLL if off */
-static int omap2_clk_fixed_enable(struct clk *clk)
-{
-        u32 cval, apll_mask;
-
-        apll_mask = EN_APLL_LOCKED << clk->enable_bit;
-
-        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
-
-        if ((cval & apll_mask) == apll_mask)
-                return 0;   /* apll already enabled */
-
-        cval &= ~apll_mask;
-        cval |= apll_mask;
-        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
-
-        if (clk == &apll96_ck)
-                cval = OMAP24XX_ST_96M_APLL;
-        else if (clk == &apll54_ck)
-                cval = OMAP24XX_ST_54M_APLL;
-
-        omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
-                             clk->name);
-
-        /*
-         * REVISIT: Should we return an error code if omap2_wait_clock_ready()
-         * fails?
-         */
-        return 0;
-}
-
-/* Stop APLL */
-static void omap2_clk_fixed_disable(struct clk *clk)
-{
-        u32 cval;
-
-        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
-        cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
-        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
-}
-
-static const struct clkops clkops_fixed = {
-        .enable         = &omap2_clk_fixed_enable,
-        .disable        = &omap2_clk_fixed_disable,
-};
-
-/*
- * Uses the current prcm set to tell if a rate is valid.
- * You can go slower, but not faster within a given rate set.
- */
-static long omap2_dpllcore_round_rate(unsigned long target_rate)
-{
-        u32 high, low, core_clk_src;
-
-        core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
-
-        if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
-                high = curr_prcm_set->dpll_speed * 2;
-                low = curr_prcm_set->dpll_speed;
-        } else {                                /* DPLL clockout x 2 */
-                high = curr_prcm_set->dpll_speed;
-                low = curr_prcm_set->dpll_speed / 2;
-        }
-
-#ifdef DOWN_VARIABLE_DPLL
-        if (target_rate > high)
-                return high;
-        else
-                return target_rate;
-#else
-        if (target_rate > low)
-                return high;
-        else
-                return low;
-#endif
-
-}
-
-static unsigned long omap2_dpllcore_recalc(struct clk *clk)
-{
-        return omap2xxx_clk_get_core_rate(clk);
-}
-
-static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
-{
-        u32 cur_rate, low, mult, div, valid_rate, done_rate;
-        u32 bypass = 0;
-        struct prcm_config tmpset;
-        const struct dpll_data *dd;
-
-        cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
-        mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
-
-        if ((rate == (cur_rate / 2)) && (mult == 2)) {
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
-        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-        } else if (rate != cur_rate) {
-                valid_rate = omap2_dpllcore_round_rate(rate);
-                if (valid_rate != rate)
-                        return -EINVAL;
-
-                if (mult == 1)
-                        low = curr_prcm_set->dpll_speed;
-                else
-                        low = curr_prcm_set->dpll_speed / 2;
-
-                dd = clk->dpll_data;
-                if (!dd)
-                        return -EINVAL;
-
-                tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
-                tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
-                                           dd->div1_mask);
-                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
-                tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
-                tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
-                if (rate > low) {
-                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
-                        mult = ((rate / 2) / 1000000);
-                        done_rate = CORE_CLK_SRC_DPLL_X2;
-                } else {
-                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
-                        mult = (rate / 1000000);
-                        done_rate = CORE_CLK_SRC_DPLL;
-                }
-                tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
-                tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
-
-                /* Worst case */
-                tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
-
-                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
-                        bypass = 1;
-
-                /* For omap2xxx_sdrc_init_params() */
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-
-                /* Force dll lock mode */
-                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
-                               bypass);
-
-                /* Errata: ret dll entry state */
-                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
-                omap2xxx_sdrc_reprogram(done_rate, 0);
-        }
-
-        return 0;
-}
-
-/**
- * omap2_table_mpu_recalc - just return the MPU speed
- * @clk: virt_prcm_set struct clk
- *
- * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
- */
-static unsigned long omap2_table_mpu_recalc(struct clk *clk)
-{
-        return curr_prcm_set->mpu_speed;
-}
-
-/*
- * Look for a rate equal or less than the target rate given a configuration set.
- *
- * What's not entirely clear is "which" field represents the key field.
- * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
- * just uses the ARM rates.
- */
-static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
-{
-        struct prcm_config *ptr;
-        long highest_rate;
-
-        if (clk != &virt_prcm_set)
-                return -EINVAL;
-
-        highest_rate = -EINVAL;
-
-        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
-                if (!(ptr->flags & cpu_mask))
-                        continue;
-                if (ptr->xtal_speed != sys_ck.rate)
-                        continue;
-
-                highest_rate = ptr->mpu_speed;
-
-                /* Can check only after xtal frequency check */
-                if (ptr->mpu_speed <= rate)
-                        break;
-        }
-        return highest_rate;
-}
-
-/* Sets basic clocks based on the specified rate */
-static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
-{
-        u32 cur_rate, done_rate, bypass = 0, tmp;
-        struct prcm_config *prcm;
-        unsigned long found_speed = 0;
-        unsigned long flags;
-
-        if (clk != &virt_prcm_set)
-                return -EINVAL;
-
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-
-                if (prcm->mpu_speed <= rate) {
-                        found_speed = prcm->mpu_speed;
-                        break;
-                }
-        }
-
-        if (!found_speed) {
-                printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
-                       rate / 1000000);
-                return -EINVAL;
-        }
-
-        curr_prcm_set = prcm;
-        cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck);
-
-        if (prcm->dpll_speed == cur_rate / 2) {
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
-        } else if (prcm->dpll_speed == cur_rate * 2) {
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-        } else if (prcm->dpll_speed != cur_rate) {
-                local_irq_save(flags);
-
-                if (prcm->dpll_speed == prcm->xtal_speed)
-                        bypass = 1;
-
-                if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
-                    CORE_CLK_SRC_DPLL_X2)
-                        done_rate = CORE_CLK_SRC_DPLL_X2;
-                else
-                        done_rate = CORE_CLK_SRC_DPLL;
-
-                /* MPU divider */
-                cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
-
-                /* dsp + iva1 div(2420), iva2.1(2430) */
-                cm_write_mod_reg(prcm->cm_clksel_dsp,
-                                 OMAP24XX_DSP_MOD, CM_CLKSEL);
-
-                cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
-
-                /* Major subsystem dividers */
-                tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
-                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
-                                 CM_CLKSEL1);
-
-                if (cpu_is_omap2430())
-                        cm_write_mod_reg(prcm->cm_clksel_mdm,
-                                         OMAP2430_MDM_MOD, CM_CLKSEL);
-
-                /* x2 to enter omap2xxx_sdrc_init_params() */
-                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
-
-                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
-                               bypass);
-
-                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
-                omap2xxx_sdrc_reprogram(done_rate, 0);
-
-                local_irq_restore(flags);
-        }
-
-        return 0;
-}
-
-#ifdef CONFIG_CPU_FREQ
-/*
- * Walk PRCM rate table and fillout cpufreq freq_table
- */
-static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
-
-void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
-{
-        struct prcm_config *prcm;
-        int i = 0;
-
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-
-                /* don't put bypass rates in table */
-                if (prcm->dpll_speed == prcm->xtal_speed)
-                        continue;
-
-                freq_table[i].index = i;
-                freq_table[i].frequency = prcm->mpu_speed / 1000;
-                i++;
-        }
-
-        if (i == 0) {
-                printk(KERN_WARNING "%s: failed to initialize frequency "
-                       "table\n", __func__);
-                return;
-        }
-
-        freq_table[i].index = i;
-        freq_table[i].frequency = CPUFREQ_TABLE_END;
-
-        *table = &freq_table[0];
-}
-#endif
-
-static struct clk_functions omap2_clk_functions = {
-        .clk_enable             = omap2_clk_enable,
-        .clk_disable            = omap2_clk_disable,
-        .clk_round_rate         = omap2_clk_round_rate,
-        .clk_set_rate           = omap2_clk_set_rate,
-        .clk_set_parent         = omap2_clk_set_parent,
-        .clk_disable_unused     = omap2_clk_disable_unused,
-#ifdef  CONFIG_CPU_FREQ
-        .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
-#endif
-};
-
-static u32 omap2_get_apll_clkin(void)
-{
-        u32 aplls, srate = 0;
-
-        aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
-        aplls &= OMAP24XX_APLLS_CLKIN_MASK;
-        aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
-
-        if (aplls == APLLS_CLKIN_19_2MHZ)
-                srate = 19200000;
-        else if (aplls == APLLS_CLKIN_13MHZ)
-                srate = 13000000;
-        else if (aplls == APLLS_CLKIN_12MHZ)
-                srate = 12000000;
-
-        return srate;
-}
-
-static u32 omap2_get_sysclkdiv(void)
-{
-        u32 div;
-
-        div = __raw_readl(prcm_clksrc_ctrl);
-        div &= OMAP_SYSCLKDIV_MASK;
-        div >>= OMAP_SYSCLKDIV_SHIFT;
-
-        return div;
-}
-
-static unsigned long omap2_osc_clk_recalc(struct clk *clk)
-{
-        return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
-}
-
-static unsigned long omap2_sys_clk_recalc(struct clk *clk)
-{
-        return clk->parent->rate / omap2_get_sysclkdiv();
-}
-
-/*
- * Set clocks for bypass mode for reboot to work.
- */
-void omap2_clk_prepare_for_reboot(void)
-{
-        u32 rate;
-
-        if (vclk == NULL || sclk == NULL)
-                return;
-
-        rate = clk_get_rate(sclk);
-        clk_set_rate(vclk, rate);
-}
-
-/*
- * Switch the MPU rate if specified on cmdline.
- * We cannot do this early until cmdline is parsed.
- */
-static int __init omap2_clk_arch_init(void)
-{
-        if (!mpurate)
-                return -EINVAL;
-
-        if (clk_set_rate(&virt_prcm_set, mpurate))
-                printk(KERN_ERR "Could not find matching MPU rate\n");
-
-        recalculate_root_clocks();
-
-        printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
-               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-
-        return 0;
-}
-arch_initcall(omap2_clk_arch_init);
-
-int __init omap2_clk_init(void)
-{
-        struct prcm_config *prcm;
-        struct omap_clk *c;
-        u32 clkrate;
-
-        if (cpu_is_omap242x()) {
-                prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
-                cpu_mask = RATE_IN_242X;
-        } else if (cpu_is_omap2430()) {
-                prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
-                cpu_mask = RATE_IN_243X;
-        }
-
-        clk_init(&omap2_clk_functions);
-
-        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
-                clk_preinit(c->lk.clk);
-
-        osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
-        propagate_rate(&osc_ck);
-        sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
-        propagate_rate(&sys_ck);
-
-        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
-                if (c->cpu & cpu_mask) {
-                        clkdev_add(&c->lk);
-                        clk_register(c->lk.clk);
-                        omap2_init_clk_clkdm(c->lk.clk);
-                }
-
-        /* Check the MPU rate set by bootloader */
-        clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-                if (prcm->dpll_speed <= clkrate)
-                         break;
-        }
-        curr_prcm_set = prcm;
-
-        recalculate_root_clocks();
-
-        printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
-               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
-
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable_init_clocks();
-
-        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
-        vclk = clk_get(NULL, "virt_prcm_set");
-        sclk = clk_get(NULL, "sys_ck");
-
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c
new file mode 100644
index 000000000000..d0e3fb7f9298
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -0,0 +1,587 @@
+/*
+ *  linux/arch/arm/mach-omap2/clock.c
+ *
+ *  Copyright (C) 2005-2008 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2008 Nokia Corporation
+ *
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
+ *
+ *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
+ *  Gordon McNutt and RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+#include <linux/bitops.h>
+
+#include <plat/clock.h>
+#include <plat/sram.h>
+#include <plat/prcm.h>
+#include <plat/clkdev_omap.h>
+#include <asm/div64.h>
+#include <asm/clkdev.h>
+
+#include <plat/sdrc.h>
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "cm.h"
+#include "cm-regbits-24xx.h"
+
+
+/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
+#define EN_APLL_STOPPED                 0
+#define EN_APLL_LOCKED                  3
+
+/* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
+#define APLLS_CLKIN_19_2MHZ             0
+#define APLLS_CLKIN_13MHZ               2
+#define APLLS_CLKIN_12MHZ               3
+
+/* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
+
+const struct prcm_config *curr_prcm_set;
+const struct prcm_config *rate_table;
+
+struct clk *vclk, *sclk, *dclk;
+
+void __iomem *prcm_clksrc_ctrl;
+
+/*-------------------------------------------------------------------------
+ * Omap24xx specific clock functions
+ *-------------------------------------------------------------------------*/
+
+/**
+ * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
+ * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE.  This custom function
+ * passes back the correct CM_IDLEST register address for I2CHS
+ * modules.  No return value.
+ */
+static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+                                           void __iomem **idlest_reg,
+                                           u8 *idlest_bit)
+{
+        *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
+        *idlest_bit = clk->enable_bit;
+}
+
+/* 2430 I2CHS has non-standard IDLEST register */
+const struct clkops clkops_omap2430_i2chs_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap2430_clk_i2chs_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
+/**
+ * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
+ * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
+ *
+ * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
+ * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
+ * (the latter is unusual).  This currently should be called with
+ * struct clk *dpll_ck, which is a composite clock of dpll_ck and
+ * core_ck.
+ */
+unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
+{
+        long long core_clk;
+        u32 v;
+
+        core_clk = omap2_get_dpll_rate(clk);
+
+        v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        v &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if (v == CORE_CLK_SRC_32K)
+                core_clk = 32768;
+        else
+                core_clk *= v;
+
+        return core_clk;
+}
+
+static int omap2_enable_osc_ck(struct clk *clk)
+{
+        u32 pcc;
+
+        pcc = __raw_readl(prcm_clksrc_ctrl);
+
+        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+
+        return 0;
+}
+
+static void omap2_disable_osc_ck(struct clk *clk)
+{
+        u32 pcc;
+
+        pcc = __raw_readl(prcm_clksrc_ctrl);
+
+        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+}
+
+const struct clkops clkops_oscck = {
+        .enable         = omap2_enable_osc_ck,
+        .disable        = omap2_disable_osc_ck,
+};
+
+#ifdef OLD_CK
+/* Recalculate SYST_CLK */
+static void omap2_sys_clk_recalc(struct clk *clk)
+{
+        u32 div = PRCM_CLKSRC_CTRL;
+        div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
+        div >>= clk->rate_offset;
+        clk->rate = (clk->parent->rate / div);
+        propagate_rate(clk);
+}
+#endif  /* OLD_CK */
+
+/* Enable an APLL if off */
+static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
+{
+        u32 cval, apll_mask;
+
+        apll_mask = EN_APLL_LOCKED << clk->enable_bit;
+
+        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+
+        if ((cval & apll_mask) == apll_mask)
+                return 0;   /* apll already enabled */
+
+        cval &= ~apll_mask;
+        cval |= apll_mask;
+        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+
+        omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
+                             clk->name);
+
+        /*
+         * REVISIT: Should we return an error code if omap2_wait_clock_ready()
+         * fails?
+         */
+        return 0;
+}
+
+static int omap2_clk_apll96_enable(struct clk *clk)
+{
+        return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL);
+}
+
+static int omap2_clk_apll54_enable(struct clk *clk)
+{
+        return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL);
+}
+
+/* Stop APLL */
+static void omap2_clk_apll_disable(struct clk *clk)
+{
+        u32 cval;
+
+        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
+        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+}
+
+const struct clkops clkops_apll96 = {
+        .enable         = omap2_clk_apll96_enable,
+        .disable        = omap2_clk_apll_disable,
+};
+
+const struct clkops clkops_apll54 = {
+        .enable         = omap2_clk_apll54_enable,
+        .disable        = omap2_clk_apll_disable,
+};
+
+/*
+ * Uses the current prcm set to tell if a rate is valid.
+ * You can go slower, but not faster within a given rate set.
+ */
+long omap2_dpllcore_round_rate(unsigned long target_rate)
+{
+        u32 high, low, core_clk_src;
+
+        core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
+                high = curr_prcm_set->dpll_speed * 2;
+                low = curr_prcm_set->dpll_speed;
+        } else {                                /* DPLL clockout x 2 */
+                high = curr_prcm_set->dpll_speed;
+                low = curr_prcm_set->dpll_speed / 2;
+        }
+
+#ifdef DOWN_VARIABLE_DPLL
+        if (target_rate > high)
+                return high;
+        else
+                return target_rate;
+#else
+        if (target_rate > low)
+                return high;
+        else
+                return low;
+#endif
+
+}
+
+unsigned long omap2_dpllcore_recalc(struct clk *clk)
+{
+        return omap2xxx_clk_get_core_rate(clk);
+}
+
+int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
+{
+        u32 cur_rate, low, mult, div, valid_rate, done_rate;
+        u32 bypass = 0;
+        struct prcm_config tmpset;
+        const struct dpll_data *dd;
+
+        cur_rate = omap2xxx_clk_get_core_rate(dclk);
+        mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
+
+        if ((rate == (cur_rate / 2)) && (mult == 2)) {
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
+        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+        } else if (rate != cur_rate) {
+                valid_rate = omap2_dpllcore_round_rate(rate);
+                if (valid_rate != rate)
+                        return -EINVAL;
+
+                if (mult == 1)
+                        low = curr_prcm_set->dpll_speed;
+                else
+                        low = curr_prcm_set->dpll_speed / 2;
+
+                dd = clk->dpll_data;
+                if (!dd)
+                        return -EINVAL;
+
+                tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+                tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
+                                           dd->div1_mask);
+                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
+                tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+                tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
+                if (rate > low) {
+                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
+                        mult = ((rate / 2) / 1000000);
+                        done_rate = CORE_CLK_SRC_DPLL_X2;
+                } else {
+                        tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
+                        mult = (rate / 1000000);
+                        done_rate = CORE_CLK_SRC_DPLL;
+                }
+                tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
+                tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
+
+                /* Worst case */
+                tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
+
+                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
+                        bypass = 1;
+
+                /* For omap2xxx_sdrc_init_params() */
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+
+                /* Force dll lock mode */
+                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
+                               bypass);
+
+                /* Errata: ret dll entry state */
+                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+                omap2xxx_sdrc_reprogram(done_rate, 0);
+        }
+
+        return 0;
+}
+
+/**
+ * omap2_table_mpu_recalc - just return the MPU speed
+ * @clk: virt_prcm_set struct clk
+ *
+ * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
+ */
+unsigned long omap2_table_mpu_recalc(struct clk *clk)
+{
+        return curr_prcm_set->mpu_speed;
+}
+
+/*
+ * Look for a rate equal or less than the target rate given a configuration set.
+ *
+ * What's not entirely clear is "which" field represents the key field.
+ * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
+ * just uses the ARM rates.
+ */
+long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
+{
+        const struct prcm_config *ptr;
+        long highest_rate;
+        long sys_ck_rate;
+
+        sys_ck_rate = clk_get_rate(sclk);
+
+        highest_rate = -EINVAL;
+
+        for (ptr = rate_table; ptr->mpu_speed; ptr++) {
+                if (!(ptr->flags & cpu_mask))
+                        continue;
+                if (ptr->xtal_speed != sys_ck_rate)
+                        continue;
+
+                highest_rate = ptr->mpu_speed;
+
+                /* Can check only after xtal frequency check */
+                if (ptr->mpu_speed <= rate)
+                        break;
+        }
+        return highest_rate;
+}
+
+/* Sets basic clocks based on the specified rate */
+int omap2_select_table_rate(struct clk *clk, unsigned long rate)
+{
+        u32 cur_rate, done_rate, bypass = 0, tmp;
+        const struct prcm_config *prcm;
+        unsigned long found_speed = 0;
+        unsigned long flags;
+        long sys_ck_rate;
+
+        sys_ck_rate = clk_get_rate(sclk);
+
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+
+                if (prcm->xtal_speed != sys_ck_rate)
+                        continue;
+
+                if (prcm->mpu_speed <= rate) {
+                        found_speed = prcm->mpu_speed;
+                        break;
+                }
+        }
+
+        if (!found_speed) {
+                printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
+                       rate / 1000000);
+                return -EINVAL;
+        }
+
+        curr_prcm_set = prcm;
+        cur_rate = omap2xxx_clk_get_core_rate(dclk);
+
+        if (prcm->dpll_speed == cur_rate / 2) {
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
+        } else if (prcm->dpll_speed == cur_rate * 2) {
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+        } else if (prcm->dpll_speed != cur_rate) {
+                local_irq_save(flags);
+
+                if (prcm->dpll_speed == prcm->xtal_speed)
+                        bypass = 1;
+
+                if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
+                    CORE_CLK_SRC_DPLL_X2)
+                        done_rate = CORE_CLK_SRC_DPLL_X2;
+                else
+                        done_rate = CORE_CLK_SRC_DPLL;
+
+                /* MPU divider */
+                cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
+
+                /* dsp + iva1 div(2420), iva2.1(2430) */
+                cm_write_mod_reg(prcm->cm_clksel_dsp,
+                                 OMAP24XX_DSP_MOD, CM_CLKSEL);
+
+                cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
+
+                /* Major subsystem dividers */
+                tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
+                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
+                                 CM_CLKSEL1);
+
+                if (cpu_is_omap2430())
+                        cm_write_mod_reg(prcm->cm_clksel_mdm,
+                                         OMAP2430_MDM_MOD, CM_CLKSEL);
+
+                /* x2 to enter omap2xxx_sdrc_init_params() */
+                omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
+
+                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
+                               bypass);
+
+                omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+                omap2xxx_sdrc_reprogram(done_rate, 0);
+
+                local_irq_restore(flags);
+        }
+
+        return 0;
+}
+
+#ifdef CONFIG_CPU_FREQ
+/*
+ * Walk PRCM rate table and fillout cpufreq freq_table
+ */
+static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
+
+void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+        struct prcm_config *prcm;
+        int i = 0;
+
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+
+                /* don't put bypass rates in table */
+                if (prcm->dpll_speed == prcm->xtal_speed)
+                        continue;
+
+                freq_table[i].index = i;
+                freq_table[i].frequency = prcm->mpu_speed / 1000;
+                i++;
+        }
+
+        if (i == 0) {
+                printk(KERN_WARNING "%s: failed to initialize frequency "
+                       "table\n", __func__);
+                return;
+        }
+
+        freq_table[i].index = i;
+        freq_table[i].frequency = CPUFREQ_TABLE_END;
+
+        *table = &freq_table[0];
+}
+#endif
+
+struct clk_functions omap2_clk_functions = {
+        .clk_enable             = omap2_clk_enable,
+        .clk_disable            = omap2_clk_disable,
+        .clk_round_rate         = omap2_clk_round_rate,
+        .clk_set_rate           = omap2_clk_set_rate,
+        .clk_set_parent         = omap2_clk_set_parent,
+        .clk_disable_unused     = omap2_clk_disable_unused,
+#ifdef  CONFIG_CPU_FREQ
+        .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
+#endif
+};
+
+static u32 omap2_get_apll_clkin(void)
+{
+        u32 aplls, srate = 0;
+
+        aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+        aplls &= OMAP24XX_APLLS_CLKIN_MASK;
+        aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
+
+        if (aplls == APLLS_CLKIN_19_2MHZ)
+                srate = 19200000;
+        else if (aplls == APLLS_CLKIN_13MHZ)
+                srate = 13000000;
+        else if (aplls == APLLS_CLKIN_12MHZ)
+                srate = 12000000;
+
+        return srate;
+}
+
+static u32 omap2_get_sysclkdiv(void)
+{
+        u32 div;
+
+        div = __raw_readl(prcm_clksrc_ctrl);
+        div &= OMAP_SYSCLKDIV_MASK;
+        div >>= OMAP_SYSCLKDIV_SHIFT;
+
+        return div;
+}
+
+unsigned long omap2_osc_clk_recalc(struct clk *clk)
+{
+        return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
+}
+
+unsigned long omap2_sys_clk_recalc(struct clk *clk)
+{
+        return clk->parent->rate / omap2_get_sysclkdiv();
+}
+
+/*
+ * Set clocks for bypass mode for reboot to work.
+ */
+void omap2_clk_prepare_for_reboot(void)
+{
+        u32 rate;
+
+        if (vclk == NULL || sclk == NULL)
+                return;
+
+        rate = clk_get_rate(sclk);
+        clk_set_rate(vclk, rate);
+}
+
+/*
+ * Switch the MPU rate if specified on cmdline.
+ * We cannot do this early until cmdline is parsed.
+ */
+static int __init omap2_clk_arch_init(void)
+{
+        struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck;
+        unsigned long sys_ck_rate;
+
+        if (!mpurate)
+                return -EINVAL;
+
+        virt_prcm_set = clk_get(NULL, "virt_prcm_set");
+        sys_ck = clk_get(NULL, "sys_ck");
+        dpll_ck = clk_get(NULL, "dpll_ck");
+        mpu_ck = clk_get(NULL, "mpu_ck");
+
+        if (clk_set_rate(virt_prcm_set, mpurate))
+                printk(KERN_ERR "Could not find matching MPU rate\n");
+
+        recalculate_root_clocks();
+
+        sys_ck_rate = clk_get_rate(sys_ck);
+
+        pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): "
+                "%ld.%01ld/%ld/%ld MHz\n",
+                (sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10,
+                (clk_get_rate(dpll_ck) / 1000000),
+                (clk_get_rate(mpu_ck) / 1000000));
+
+        return 0;
+}
+arch_initcall(omap2_clk_arch_init);
+
+
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
new file mode 100644
index 000000000000..e35efde4bd80
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -0,0 +1,41 @@
+/*
+ * OMAP2 clock function prototypes and macros
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2009 Nokia Corporation
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
+
+unsigned long omap2_table_mpu_recalc(struct clk *clk);
+int omap2_select_table_rate(struct clk *clk, unsigned long rate);
+long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
+unsigned long omap2_sys_clk_recalc(struct clk *clk);
+unsigned long omap2_osc_clk_recalc(struct clk *clk);
+unsigned long omap2_sys_clk_recalc(struct clk *clk);
+unsigned long omap2_dpllcore_recalc(struct clk *clk);
+int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
+unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
+
+/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
+#ifdef CONFIG_ARCH_OMAP2420
+#define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
+#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP2420_PRCM_CLKOUT_CTRL
+#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP2420_PRCM_CLKEMUL_CTRL
+#else
+#define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
+#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP2430_PRCM_CLKOUT_CTRL
+#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP2430_PRCM_CLKEMUL_CTRL
+#endif
+
+extern void __iomem *prcm_clksrc_ctrl;
+
+extern struct clk *dclk;
+
+extern const struct clkops clkops_omap2430_i2chs_wait;
+extern const struct clkops clkops_oscck;
+extern const struct clkops clkops_apll96;
+extern const struct clkops clkops_apll54;
+
+#endif
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock2xxx_data.c
index d19cf7a7d8db..97dc7cf7751d 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock2xxx_data.c
@@ -1,8 +1,8 @@
 /*
- *  linux/arch/arm/mach-omap2/clock24xx.h
+ *  linux/arch/arm/mach-omap2/clock2xxx_data.c
  *
- *  Copyright (C) 2005-2008 Texas Instruments, Inc.
- *  Copyright (C) 2004-2008 Nokia Corporation
+ *  Copyright (C) 2005-2009 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2009 Nokia Corporation
  *
  *  Contacts:
  *  Richard Woodruff <r-woodruff2@ti.com>
@@ -13,600 +13,21 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
 
-#include "clock.h"
+#include <plat/clkdev_omap.h>
 
+#include "clock.h"
+#include "clock2xxx.h"
+#include "opp2xxx.h"
 #include "prm.h"
 #include "cm.h"
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
 
-/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
-#ifdef CONFIG_ARCH_OMAP2420
-#define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
-#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP2420_PRCM_CLKOUT_CTRL
-#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP2420_PRCM_CLKEMUL_CTRL
-#else
-#define OMAP_CM_REGADDR                 OMAP2430_CM_REGADDR
-#define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP2430_PRCM_CLKOUT_CTRL
-#define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP2430_PRCM_CLKEMUL_CTRL
-#endif
-
-static unsigned long omap2_table_mpu_recalc(struct clk *clk);
-static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
-static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
-static unsigned long omap2_sys_clk_recalc(struct clk *clk);
-static unsigned long omap2_osc_clk_recalc(struct clk *clk);
-static unsigned long omap2_sys_clk_recalc(struct clk *clk);
-static unsigned long omap2_dpllcore_recalc(struct clk *clk);
-static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
-
-/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
- * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- */
-struct prcm_config {
-        unsigned long xtal_speed;       /* crystal rate */
-        unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
-        unsigned long mpu_speed;        /* speed of MPU */
-        unsigned long cm_clksel_mpu;    /* mpu divider */
-        unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
-        unsigned long cm_clksel_gfx;    /* gfx dividers */
-        unsigned long cm_clksel1_core;  /* major subsystem dividers */
-        unsigned long cm_clksel1_pll;   /* m,n */
-        unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
-        unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
-        unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
-        unsigned char flags;
-};
-
-/*
- * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
- * These configurations are characterized by voltage and speed for clocks.
- * The device is only validated for certain combinations. One way to express
- * these combinations is via the 'ratio's' which the clocks operate with
- * respect to each other. These ratio sets are for a given voltage/DPLL
- * setting. All configurations can be described by a DPLL setting and a ratio
- * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
- *
- * 2430 differs from 2420 in that there are no more phase synchronizers used.
- * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
- * 2430 (iva2.1, NOdsp, mdm)
- */
-
-/* Core fields for cm_clksel, not ratio governed */
-#define RX_CLKSEL_DSS1                  (0x10 << 8)
-#define RX_CLKSEL_DSS2                  (0x0 << 13)
-#define RX_CLKSEL_SSI                   (0x5 << 20)
-
-/*-------------------------------------------------------------------------
- * Voltage/DPLL ratios
- *-------------------------------------------------------------------------*/
-
-/* 2430 Ratio's, 2430-Ratio Config 1 */
-#define R1_CLKSEL_L3                    (4 << 0)
-#define R1_CLKSEL_L4                    (2 << 5)
-#define R1_CLKSEL_USB                   (4 << 25)
-#define R1_CM_CLKSEL1_CORE_VAL          R1_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        R1_CLKSEL_L4 | R1_CLKSEL_L3
-#define R1_CLKSEL_MPU                   (2 << 0)
-#define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
-#define R1_CLKSEL_DSP                   (2 << 0)
-#define R1_CLKSEL_DSP_IF                (2 << 5)
-#define R1_CM_CLKSEL_DSP_VAL            R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
-#define R1_CLKSEL_GFX                   (2 << 0)
-#define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
-#define R1_CLKSEL_MDM                   (4 << 0)
-#define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
-
-/* 2430-Ratio Config 2 */
-#define R2_CLKSEL_L3                    (6 << 0)
-#define R2_CLKSEL_L4                    (2 << 5)
-#define R2_CLKSEL_USB                   (2 << 25)
-#define R2_CM_CLKSEL1_CORE_VAL          R2_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        R2_CLKSEL_L4 | R2_CLKSEL_L3
-#define R2_CLKSEL_MPU                   (2 << 0)
-#define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
-#define R2_CLKSEL_DSP                   (2 << 0)
-#define R2_CLKSEL_DSP_IF                (3 << 5)
-#define R2_CM_CLKSEL_DSP_VAL            R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
-#define R2_CLKSEL_GFX                   (2 << 0)
-#define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
-#define R2_CLKSEL_MDM                   (6 << 0)
-#define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
-
-/* 2430-Ratio Bootm (BYPASS) */
-#define RB_CLKSEL_L3                    (1 << 0)
-#define RB_CLKSEL_L4                    (1 << 5)
-#define RB_CLKSEL_USB                   (1 << 25)
-#define RB_CM_CLKSEL1_CORE_VAL          RB_CLKSEL_USB | RX_CLKSEL_SSI | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        RB_CLKSEL_L4 | RB_CLKSEL_L3
-#define RB_CLKSEL_MPU                   (1 << 0)
-#define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
-#define RB_CLKSEL_DSP                   (1 << 0)
-#define RB_CLKSEL_DSP_IF                (1 << 5)
-#define RB_CM_CLKSEL_DSP_VAL            RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
-#define RB_CLKSEL_GFX                   (1 << 0)
-#define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
-#define RB_CLKSEL_MDM                   (1 << 0)
-#define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
-
-/* 2420 Ratio Equivalents */
-#define RXX_CLKSEL_VLYNQ                (0x12 << 15)
-#define RXX_CLKSEL_SSI                  (0x8 << 20)
-
-/* 2420-PRCM III 532MHz core */
-#define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
-#define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
-#define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
-#define RIII_CM_CLKSEL1_CORE_VAL        RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
-                                        RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
-                                        RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
-                                        RIII_CLKSEL_L3
-#define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
-#define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
-#define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
-#define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
-#define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
-#define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
-#define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
-#define RIII_CM_CLKSEL_DSP_VAL          RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
-                                        RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
-                                        RIII_CLKSEL_DSP
-#define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
-#define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
-
-/* 2420-PRCM II 600MHz core */
-#define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
-#define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
-#define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
-#define RII_CM_CLKSEL1_CORE_VAL         RII_CLKSEL_USB | \
-                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        RII_CLKSEL_L4 | RII_CLKSEL_L3
-#define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
-#define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
-#define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
-#define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
-#define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
-#define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
-#define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
-#define RII_CM_CLKSEL_DSP_VAL           RII_SYNC_IVA | RII_CLKSEL_IVA | \
-                                        RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
-                                        RII_CLKSEL_DSP
-#define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
-#define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
-
-/* 2420-PRCM I 660MHz core */
-#define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
-#define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
-#define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
-#define RI_CM_CLKSEL1_CORE_VAL          RI_CLKSEL_USB | \
-                                        RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
-                                        RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
-                                        RI_CLKSEL_L4 | RI_CLKSEL_L3
-#define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
-#define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
-#define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
-#define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
-#define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
-#define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
-#define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
-#define RI_CM_CLKSEL_DSP_VAL            RI_SYNC_IVA | RI_CLKSEL_IVA | \
-                                        RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
-                                        RI_CLKSEL_DSP
-#define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
-#define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
-
-/* 2420-PRCM VII (boot) */
-#define RVII_CLKSEL_L3                  (1 << 0)
-#define RVII_CLKSEL_L4                  (1 << 5)
-#define RVII_CLKSEL_DSS1                (1 << 8)
-#define RVII_CLKSEL_DSS2                (0 << 13)
-#define RVII_CLKSEL_VLYNQ               (1 << 15)
-#define RVII_CLKSEL_SSI                 (1 << 20)
-#define RVII_CLKSEL_USB                 (1 << 25)
-
-#define RVII_CM_CLKSEL1_CORE_VAL        RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
-                                        RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
-                                        RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
-
-#define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
-#define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
-
-#define RVII_CLKSEL_DSP                 (1 << 0)
-#define RVII_CLKSEL_DSP_IF              (1 << 5)
-#define RVII_SYNC_DSP                   (0 << 7)
-#define RVII_CLKSEL_IVA                 (1 << 8)
-#define RVII_SYNC_IVA                   (0 << 13)
-#define RVII_CM_CLKSEL_DSP_VAL          RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
-                                        RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
-
-#define RVII_CLKSEL_GFX                 (1 << 0)
-#define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
-
-/*-------------------------------------------------------------------------
- * 2430 Target modes: Along with each configuration the CPU has several
- * modes which goes along with them. Modes mainly are the addition of
- * describe DPLL combinations to go along with a ratio.
- *-------------------------------------------------------------------------*/
-
-/* Hardware governed */
-#define MX_48M_SRC                      (0 << 3)
-#define MX_54M_SRC                      (0 << 5)
-#define MX_APLLS_CLIKIN_12              (3 << 23)
-#define MX_APLLS_CLIKIN_13              (2 << 23)
-#define MX_APLLS_CLIKIN_19_2            (0 << 23)
-
-/*
- * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
- * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
- */
-#define M5A_DPLL_MULT_12                (133 << 12)
-#define M5A_DPLL_DIV_12                 (5 << 8)
-#define M5A_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M5A_DPLL_MULT_13                (61 << 12)
-#define M5A_DPLL_DIV_13                 (2 << 8)
-#define M5A_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M5A_DPLL_MULT_19                (55 << 12)
-#define M5A_DPLL_DIV_19                 (3 << 8)
-#define M5A_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
-#define M5B_DPLL_MULT_12                (50 << 12)
-#define M5B_DPLL_DIV_12                 (2 << 8)
-#define M5B_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M5B_DPLL_MULT_13                (200 << 12)
-#define M5B_DPLL_DIV_13                 (12 << 8)
-
-#define M5B_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M5B_DPLL_MULT_19                (125 << 12)
-#define M5B_DPLL_DIV_19                 (31 << 8)
-#define M5B_CM_CLKSEL1_PLL_19_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-/*
- * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
- */
-#define M4_DPLL_MULT_12                 (133 << 12)
-#define M4_DPLL_DIV_12                  (3 << 8)
-#define M4_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-
-#define M4_DPLL_MULT_13                 (399 << 12)
-#define M4_DPLL_DIV_13                  (12 << 8)
-#define M4_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-#define M4_DPLL_MULT_19                 (145 << 12)
-#define M4_DPLL_DIV_19                  (6 << 8)
-#define M4_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-
-/*
- * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
- */
-#define M3_DPLL_MULT_12                 (55 << 12)
-#define M3_DPLL_DIV_12                  (1 << 8)
-#define M3_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define M3_DPLL_MULT_13                 (76 << 12)
-#define M3_DPLL_DIV_13                  (2 << 8)
-#define M3_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-#define M3_DPLL_MULT_19                 (17 << 12)
-#define M3_DPLL_DIV_19                  (0 << 8)
-#define M3_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-
-/*
- * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
- */
-#define M2_DPLL_MULT_12                 (55 << 12)
-#define M2_DPLL_DIV_12                  (1 << 8)
-#define M2_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-
-/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
- * relock time issue */
-/* Core frequency changed from 330/165 to 329/164 MHz*/
-#define M2_DPLL_MULT_13                 (76 << 12)
-#define M2_DPLL_DIV_13                  (2 << 8)
-#define M2_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-#define M2_DPLL_MULT_19                 (17 << 12)
-#define M2_DPLL_DIV_19                  (0 << 8)
-#define M2_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
-                                        MX_APLLS_CLIKIN_19_2
-
-/* boot (boot) */
-#define MB_DPLL_MULT                    (1 << 12)
-#define MB_DPLL_DIV                     (0 << 8)
-#define MB_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_12
-
-#define MB_CM_CLKSEL1_PLL_13_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_13
-
-#define MB_CM_CLKSEL1_PLL_19_VAL        MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
-                                        MB_DPLL_MULT | MX_APLLS_CLIKIN_19
-
-/*
- * 2430 - chassis (sedna)
- * 165 (ratio1) same as above #2
- * 150 (ratio1)
- * 133 (ratio2) same as above #4
- * 110 (ratio2) same as above #3
- * 104 (ratio2)
- * boot (boot)
- */
-
-/* PRCM I target DPLL = 2*330MHz = 660MHz */
-#define MI_DPLL_MULT_12                 (55 << 12)
-#define MI_DPLL_DIV_12                  (1 << 8)
-#define MI_CM_CLKSEL1_PLL_12_VAL        MX_48M_SRC | MX_54M_SRC | \
-                                        MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-
-/*
- * 2420 Equivalent - mode registers
- * PRCM II , target DPLL = 2*300MHz = 600MHz
- */
-#define MII_DPLL_MULT_12                (50 << 12)
-#define MII_DPLL_DIV_12                 (1 << 8)
-#define MII_CM_CLKSEL1_PLL_12_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define MII_DPLL_MULT_13                (300 << 12)
-#define MII_DPLL_DIV_13                 (12 << 8)
-#define MII_CM_CLKSEL1_PLL_13_VAL       MX_48M_SRC | MX_54M_SRC | \
-                                        MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-/* PRCM III target DPLL = 2*266 = 532MHz*/
-#define MIII_DPLL_MULT_12               (133 << 12)
-#define MIII_DPLL_DIV_12                (5 << 8)
-#define MIII_CM_CLKSEL1_PLL_12_VAL      MX_48M_SRC | MX_54M_SRC | \
-                                        MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
-                                        MX_APLLS_CLIKIN_12
-#define MIII_DPLL_MULT_13               (266 << 12)
-#define MIII_DPLL_DIV_13                (12 << 8)
-#define MIII_CM_CLKSEL1_PLL_13_VAL      MX_48M_SRC | MX_54M_SRC | \
-                                        MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
-                                        MX_APLLS_CLIKIN_13
-
-/* PRCM VII (boot bypass) */
-#define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
-#define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
-
-/* High and low operation value */
-#define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
-#define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
-
-/* MPU speed defines */
-#define S12M    12000000
-#define S13M    13000000
-#define S19M    19200000
-#define S26M    26000000
-#define S100M   100000000
-#define S133M   133000000
-#define S150M   150000000
-#define S164M   164000000
-#define S165M   165000000
-#define S199M   199000000
-#define S200M   200000000
-#define S266M   266000000
-#define S300M   300000000
-#define S329M   329000000
-#define S330M   330000000
-#define S399M   399000000
-#define S400M   400000000
-#define S532M   532000000
-#define S600M   600000000
-#define S658M   658000000
-#define S660M   660000000
-#define S798M   798000000
-
-/*-------------------------------------------------------------------------
- * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
- * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
- * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
- * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
- *
- * Filling in table based on H4 boards and 2430-SDPs variants available.
- * There are quite a few more rates combinations which could be defined.
- *
- * When multiple values are defined the start up will try and choose the
- * fastest one. If a 'fast' value is defined, then automatically, the /2
- * one should be included as it can be used.    Generally having more that
- * one fast set does not make sense, as static timings need to be changed
- * to change the set.    The exception is the bypass setting which is
- * availble for low power bypass.
- *
- * Note: This table needs to be sorted, fastest to slowest.
- *-------------------------------------------------------------------------*/
-static struct prcm_config rate_table[] = {
-        /* PRCM I - FAST */
-        {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
-                RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
-                RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
-                RATE_IN_242X},
-
-        /* PRCM II - FAST */
-        {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        /* PRCM III - FAST */
-        {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        /* PRCM II - SLOW */
-        {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
-                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
-                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
-                RATE_IN_242X},
-
-        /* PRCM III - SLOW */
-        {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
-                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
-                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
-                RATE_IN_242X},
-
-        /* PRCM-VII (boot-bypass) */
-        {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
-                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
-                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_242X},
-
-        /* PRCM-VII (boot-bypass) */
-        {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
-                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
-                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_242X},
-
-        /* PRCM #4 - ratio2 (ES2.1) - FAST */
-        {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
-                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
-                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #2 - ratio1 (ES2) - FAST */
-        {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_165MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5a - ratio1 - FAST */
-        {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5b - ratio1 - FAST */
-        {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_100MHz,
-                RATE_IN_243X},
-
-        /* PRCM #4 - ratio1 (ES2.1) - SLOW */
-        {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
-                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
-                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #2 - ratio1 (ES2) - SLOW */
-        {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_165MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5a - ratio1 - SLOW */
-        {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_133MHz,
-                RATE_IN_243X},
-
-        /* PRCM #5b - ratio1 - SLOW*/
-        {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
-                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
-                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_100MHz,
-                RATE_IN_243X},
-
-        /* PRCM-boot/bypass */
-        {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
-                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
-                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_243X},
-
-        /* PRCM-boot/bypass */
-        {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
-                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
-                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
-                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
-                SDRC_RFR_CTRL_BYPASS,
-                RATE_IN_243X},
-
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
-};
-
 /*-------------------------------------------------------------------------
  * 24xx clock tree.
  *
@@ -708,7 +129,7 @@ static struct clk dpll_ck = {
 
 static struct clk apll96_ck = {
         .name           = "apll96_ck",
-        .ops            = &clkops_fixed,
+        .ops            = &clkops_apll96,
         .parent         = &sys_ck,
         .rate           = 96000000,
         .flags          = RATE_FIXED | ENABLE_ON_INIT,
@@ -719,7 +140,7 @@ static struct clk apll96_ck = {
 
 static struct clk apll54_ck = {
         .name           = "apll54_ck",
-        .ops            = &clkops_fixed,
+        .ops            = &clkops_apll54,
         .parent         = &sys_ck,
         .rate           = 54000000,
         .flags          = RATE_FIXED | ENABLE_ON_INIT,
@@ -2653,5 +2074,236 @@ static struct clk virt_prcm_set = {
         .round_rate     = &omap2_round_to_table_rate,
 };
 
-#endif
+
+/*
+ * clkdev integration
+ */
+
+static struct omap_clk omap24xx_clks[] = {
+        /* external root sources */
+        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
+        CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X | CK_242X),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X | CK_242X),
+        CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X | CK_242X),
+        /* internal analog sources */
+        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X | CK_242X),
+        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X | CK_242X),
+        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X | CK_242X),
+        /* internal prcm root sources */
+        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_243X | CK_242X),
+        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_243X | CK_242X),
+        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
+        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X | CK_242X),
+        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
+        CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
+        /* mpu domain clocks */
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X | CK_242X),
+        /* dsp domain clocks */
+        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X | CK_242X),
+        CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
+        CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
+        CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
+        CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
+        CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+        /* GFX domain clocks */
+        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X | CK_242X),
+        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X | CK_242X),
+        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X | CK_242X),
+        /* Modem domain clocks */
+        CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
+        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
+        /* DSS domain clocks */
+        CLK("omapdss",  "ick",          &dss_ick,       CK_243X | CK_242X),
+        CLK("omapdss",  "dss1_fck",     &dss1_fck,      CK_243X | CK_242X),
+        CLK("omapdss",  "dss2_fck",     &dss2_fck,      CK_243X | CK_242X),
+        CLK("omapdss",  "tv_fck",       &dss_54m_fck,   CK_243X | CK_242X),
+        /* L3 domain clocks */
+        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X | CK_242X),
+        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X | CK_242X),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X | CK_242X),
+        /* L4 domain clocks */
+        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X | CK_242X),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X | CK_242X),
+        /* virtual meta-group clock */
+        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
+        /* general l4 interface ck, multi-parent functional clk */
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X | CK_242X),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X | CK_242X),
+        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_243X | CK_242X),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X | CK_242X),
+        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_243X | CK_242X),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
+        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_243X),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
+        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_243X),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
+        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_243X),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X | CK_242X),
+        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_243X | CK_242X),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X | CK_242X),
+        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_243X | CK_242X),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
+        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_243X),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X | CK_242X),
+        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X | CK_242X),
+        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X | CK_242X),
+        CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_243X | CK_242X),
+        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X | CK_242X),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X | CK_242X),
+        CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
+        CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X | CK_242X),
+        CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X | CK_242X),
+        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X | CK_242X),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X | CK_242X),
+        CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
+        CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
+        CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X | CK_242X),
+        CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
+        CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X | CK_242X),
+        CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X | CK_242X),
+        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_243X | CK_242X),
+        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_242X),
+        CLK("i2c_omap.1", "fck",        &i2chs1_fck,    CK_243X),
+        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_243X | CK_242X),
+        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_242X),
+        CLK("i2c_omap.2", "fck",        &i2chs2_fck,    CK_243X),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X | CK_242X),
+        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X | CK_242X),
+        CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
+        CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
+        CLK(NULL,       "des_ick",      &des_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "sha_ick",      &sha_ick,       CK_243X | CK_242X),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "aes_ick",      &aes_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X | CK_242X),
+        CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X | CK_242X),
+        CLK("musb_hdrc",        "ick",  &usbhs_ick,     CK_243X),
+        CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
+        CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
+        CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
+        CLK("mmci-omap-hs.1", "fck",    &mmchs2_fck,    CK_243X),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
+        CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
+        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
+        CLK("mmci-omap-hs.0", "mmchsdb_fck",    &mmchsdb1_fck,  CK_243X),
+        CLK("mmci-omap-hs.1", "mmchsdb_fck",    &mmchsdb2_fck,  CK_243X),
+};
+
+/*
+ * init code
+ */
+
+int __init omap2_clk_init(void)
+{
+        const struct prcm_config *prcm;
+        struct omap_clk *c;
+        u32 clkrate;
+        u16 cpu_clkflg;
+
+        if (cpu_is_omap242x()) {
+                prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
+                cpu_mask = RATE_IN_242X;
+                cpu_clkflg = CK_242X;
+                rate_table = omap2420_rate_table;
+        } else if (cpu_is_omap2430()) {
+                prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
+                cpu_mask = RATE_IN_243X;
+                cpu_clkflg = CK_243X;
+                rate_table = omap2430_rate_table;
+        }
+
+        clk_init(&omap2_clk_functions);
+
+        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
+                clk_preinit(c->lk.clk);
+
+        osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
+        propagate_rate(&osc_ck);
+        sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
+        propagate_rate(&sys_ck);
+
+        for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
+                        omap2_init_clk_clkdm(c->lk.clk);
+                }
+
+        /* Check the MPU rate set by bootloader */
+        clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+                if (prcm->dpll_speed <= clkrate)
+                        break;
+        }
+        curr_prcm_set = prcm;
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
+               (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
+        vclk = clk_get(NULL, "virt_prcm_set");
+        sclk = clk_get(NULL, "sys_ck");
+        dclk = clk_get(NULL, "dpll_ck");
+
+        return 0;
+}
 
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index ecbb5cd8eec8..ded32364f32b 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -30,314 +30,21 @@
 #include <plat/cpu.h>
 #include <plat/clock.h>
 #include <plat/sram.h>
+#include <plat/sdrc.h>
 #include <asm/div64.h>
 #include <asm/clkdev.h>
 
 #include <plat/sdrc.h>
 #include "clock.h"
+#include "clock34xx.h"
+#include "sdrc.h"
 #include "prm.h"
 #include "prm-regbits-34xx.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
 
-static const struct clkops clkops_noncore_dpll_ops;
-
-static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
-                                            void __iomem **idlest_reg,
-                                            u8 *idlest_bit);
-static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
-                                            void __iomem **idlest_reg,
-                                            u8 *idlest_bit);
-static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
-                                                    void __iomem **idlest_reg,
-                                                    u8 *idlest_bit);
-
-static const struct clkops clkops_omap3430es2_ssi_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_idlest    = omap3430es2_clk_ssi_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
-};
-
-static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
-};
-
-static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
-        .enable         = omap2_dflt_clk_enable,
-        .disable        = omap2_dflt_clk_disable,
-        .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
-        .find_companion = omap2_clk_dflt_find_companion,
-};
-
-#include "clock34xx.h"
-
-struct omap_clk {
-        u32             cpu;
-        struct clk_lookup lk;
-};
-
-#define CLK(dev, con, ck, cp)           \
-        {                               \
-                 .cpu = cp,             \
-                .lk = {                 \
-                        .dev_id = dev,  \
-                        .con_id = con,  \
-                        .clk = ck,      \
-                },                      \
-        }
-
-#define CK_343X         (1 << 0)
-#define CK_3430ES1      (1 << 1)
-#define CK_3430ES2      (1 << 2)
-
-static struct omap_clk omap34xx_clks[] = {
-        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_343X),
-        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_343X),
-        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_343X),
-        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
-        CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
-        CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_343X),
-        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
-        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_343X),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_343X),
-        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_343X),
-        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_343X),
-        CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_343X),
-        CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_343X),
-        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_343X),
-        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
-        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
-        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
-        CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_343X),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_343X),
-        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_343X),
-        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_343X),
-        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
-        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_343X),
-        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
-        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
-        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_343X),
-        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_343X),
-        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
-        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_343X),
-        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_343X),
-        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_343X),
-        CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_343X),
-        CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_343X),
-        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
-        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
-        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
-        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
-        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_343X),
-        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
-        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
-        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2),
-        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2),
-        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_343X),
-        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_343X),
-        CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_343X),
-        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_343X),
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_343X),
-        CLK(NULL,       "arm_fck",      &arm_fck,       CK_343X),
-        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
-        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
-        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
-        CLK(NULL,       "l3_ick",       &l3_ick,        CK_343X),
-        CLK(NULL,       "l4_ick",       &l4_ick,        CK_343X),
-        CLK(NULL,       "rm_ick",       &rm_ick,        CK_343X),
-        CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
-        CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
-        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
-        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
-        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
-        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
-        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
-        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
-        CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
-        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
-        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
-        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),
-        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2),
-        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2),
-        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_343X),
-        CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2),
-        CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_343X),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
-        CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_343X),
-        CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_343X),
-        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_343X),
-        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_343X),
-        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_343X),
-        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_343X),
-        CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_343X),
-        CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_343X),
-        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_343X),
-        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_343X),
-        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_343X),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_343X),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_343X),
-        CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
-        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
-        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
-        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
-        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
-        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
-        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
-        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_343X),
-        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2),
-        CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2),
-        CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
-        CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
-        CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
-        CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
-        CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_343X),
-        CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_343X),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_343X),
-        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_343X),
-        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_343X),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_343X),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_343X),
-        CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_343X),
-        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_343X),
-        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_343X),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_343X),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_343X),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_343X),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_343X),
-        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_343X),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_343X),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
-        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
-        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
-        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
-        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
-        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
-        CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
-        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
-        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
-        CLK("omapdss",  "tv_fck",       &dss_tv_fck,    CK_343X),
-        CLK("omapdss",  "video_fck",    &dss_96m_fck,   CK_343X),
-        CLK("omapdss",  "dss2_fck",     &dss2_alwon_fck, CK_343X),
-        CLK("omapdss",  "ick",          &dss_ick_3430es1,       CK_3430ES1),
-        CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2),
-        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
-        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
-        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
-        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
-        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2),
-        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_343X),
-        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_343X),
-        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_343X),
-        CLK("omap_wdt", "fck",          &wdt2_fck,      CK_343X),
-        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
-        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
-        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_343X),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_343X),
-        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_343X),
-        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_343X),
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_343X),
-        CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_343X),
-        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_343X),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_343X),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_343X),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_343X),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_343X),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_343X),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_343X),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_343X),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_343X),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_343X),
-        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
-        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_343X),
-        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_343X),
-        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_343X),
-        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_343X),
-        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_343X),
-        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_343X),
-        CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_343X),
-        CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_343X),
-        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_343X),
-        CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_343X),
-        CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_343X),
-        CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_343X),
-        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_343X),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_343X),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_343X),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_343X),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_343X),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_343X),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_343X),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_343X),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_343X),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_343X),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_343X),
-        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_343X),
-        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_343X),
-        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_343X),
-        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_343X),
-        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_343X),
-        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_343X),
-        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_343X),
-        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_343X),
-        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_343X),
-        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_343X),
-        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_343X),
-        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
-        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
-        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
-        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_343X),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_343X),
-        CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_343X),
-};
-
-/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
-#define DPLL_AUTOIDLE_DISABLE                   0x0
-#define DPLL_AUTOIDLE_LOW_POWER_STOP            0x1
-
-#define MAX_DPLL_WAIT_TRIES             1000000
-
-#define MIN_SDRC_DLL_LOCK_FREQ          83000000
-
 #define CYCLES_PER_MHZ                  1000000
 
-/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
-#define SDRC_MPURATE_SCALE              8
-
-/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
-#define SDRC_MPURATE_BASE_SHIFT         9
-
-/*
- * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
- * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
- */
-#define SDRC_MPURATE_LOOPS              96
-
 /*
  * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
  * that are sourced by DPLL5, and both of these require this clock
@@ -345,6 +52,9 @@ static struct omap_clk omap34xx_clks[] = {
  */
 #define DPLL5_FREQ_FOR_USBHOST          120000000
 
+/* needed by omap3_core_dpll_m2_set_rate() */
+struct clk *sdrc_ick_p, *arm_fck_p;
+
 /**
  * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
  * @clk: struct clk * being enabled
@@ -366,6 +76,13 @@ static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
         *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
 }
 
+const struct clkops clkops_omap3430es2_ssi_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_ssi_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
 /**
  * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
  * @clk: struct clk * being enabled
@@ -391,6 +108,13 @@ static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
         *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
 }
 
+const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
 /**
  * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
  * @clk: struct clk * being enabled
@@ -412,395 +136,19 @@ static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
         *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
 }
 
-/**
- * omap3_dpll_recalc - recalculate DPLL rate
- * @clk: DPLL struct clk
- *
- * Recalculate and propagate the DPLL rate.
- */
-static unsigned long omap3_dpll_recalc(struct clk *clk)
-{
-        return omap2_get_dpll_rate(clk);
-}
-
-/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
-static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
-{
-        const struct dpll_data *dd;
-        u32 v;
-
-        dd = clk->dpll_data;
-
-        v = __raw_readl(dd->control_reg);
-        v &= ~dd->enable_mask;
-        v |= clken_bits << __ffs(dd->enable_mask);
-        __raw_writel(v, dd->control_reg);
-}
-
-/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
-static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
-{
-        const struct dpll_data *dd;
-        int i = 0;
-        int ret = -EINVAL;
-
-        dd = clk->dpll_data;
-
-        state <<= __ffs(dd->idlest_mask);
-
-        while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
-               i < MAX_DPLL_WAIT_TRIES) {
-                i++;
-                udelay(1);
-        }
-
-        if (i == MAX_DPLL_WAIT_TRIES) {
-                printk(KERN_ERR "clock: %s failed transition to '%s'\n",
-                       clk->name, (state) ? "locked" : "bypassed");
-        } else {
-                pr_debug("clock: %s transition to '%s' in %d loops\n",
-                         clk->name, (state) ? "locked" : "bypassed", i);
-
-                ret = 0;
-        }
-
-        return ret;
-}
-
-/* From 3430 TRM ES2 4.7.6.2 */
-static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
-{
-        unsigned long fint;
-        u16 f = 0;
-
-        fint = clk->dpll_data->clk_ref->rate / n;
-
-        pr_debug("clock: fint is %lu\n", fint);
-
-        if (fint >= 750000 && fint <= 1000000)
-                f = 0x3;
-        else if (fint > 1000000 && fint <= 1250000)
-                f = 0x4;
-        else if (fint > 1250000 && fint <= 1500000)
-                f = 0x5;
-        else if (fint > 1500000 && fint <= 1750000)
-                f = 0x6;
-        else if (fint > 1750000 && fint <= 2100000)
-                f = 0x7;
-        else if (fint > 7500000 && fint <= 10000000)
-                f = 0xB;
-        else if (fint > 10000000 && fint <= 12500000)
-                f = 0xC;
-        else if (fint > 12500000 && fint <= 15000000)
-                f = 0xD;
-        else if (fint > 15000000 && fint <= 17500000)
-                f = 0xE;
-        else if (fint > 17500000 && fint <= 21000000)
-                f = 0xF;
-        else
-                pr_debug("clock: unknown freqsel setting for %d\n", n);
-
-        return f;
-}
-
-/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
-
-/*
- * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
- * @clk: pointer to a DPLL struct clk
- *
- * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
- * readiness before returning.  Will save and restore the DPLL's
- * autoidle state across the enable, per the CDP code.  If the DPLL
- * locked successfully, return 0; if the DPLL did not lock in the time
- * allotted, or DPLL3 was passed in, return -EINVAL.
- */
-static int _omap3_noncore_dpll_lock(struct clk *clk)
-{
-        u8 ai;
-        int r;
-
-        if (clk == &dpll3_ck)
-                return -EINVAL;
-
-        pr_debug("clock: locking DPLL %s\n", clk->name);
-
-        ai = omap3_dpll_autoidle_read(clk);
-
-        omap3_dpll_deny_idle(clk);
-
-        _omap3_dpll_write_clken(clk, DPLL_LOCKED);
-
-        r = _omap3_wait_dpll_status(clk, 1);
-
-        if (ai)
-                omap3_dpll_allow_idle(clk);
-
-        return r;
-}
-
-/*
- * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
- * @clk: pointer to a DPLL struct clk
- *
- * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
- * bypass mode, the DPLL's rate is set equal to its parent clock's
- * rate.  Waits for the DPLL to report readiness before returning.
- * Will save and restore the DPLL's autoidle state across the enable,
- * per the CDP code.  If the DPLL entered bypass mode successfully,
- * return 0; if the DPLL did not enter bypass in the time allotted, or
- * DPLL3 was passed in, or the DPLL does not support low-power bypass,
- * return -EINVAL.
- */
-static int _omap3_noncore_dpll_bypass(struct clk *clk)
-{
-        int r;
-        u8 ai;
-
-        if (clk == &dpll3_ck)
-                return -EINVAL;
-
-        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
-                return -EINVAL;
-
-        pr_debug("clock: configuring DPLL %s for low-power bypass\n",
-                 clk->name);
-
-        ai = omap3_dpll_autoidle_read(clk);
-
-        _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
-
-        r = _omap3_wait_dpll_status(clk, 0);
-
-        if (ai)
-                omap3_dpll_allow_idle(clk);
-        else
-                omap3_dpll_deny_idle(clk);
-
-        return r;
-}
-
-/*
- * _omap3_noncore_dpll_stop - instruct a DPLL to stop
- * @clk: pointer to a DPLL struct clk
- *
- * Instructs a non-CORE DPLL to enter low-power stop. Will save and
- * restore the DPLL's autoidle state across the stop, per the CDP
- * code.  If DPLL3 was passed in, or the DPLL does not support
- * low-power stop, return -EINVAL; otherwise, return 0.
- */
-static int _omap3_noncore_dpll_stop(struct clk *clk)
-{
-        u8 ai;
-
-        if (clk == &dpll3_ck)
-                return -EINVAL;
-
-        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
-                return -EINVAL;
-
-        pr_debug("clock: stopping DPLL %s\n", clk->name);
-
-        ai = omap3_dpll_autoidle_read(clk);
-
-        _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
-
-        if (ai)
-                omap3_dpll_allow_idle(clk);
-        else
-                omap3_dpll_deny_idle(clk);
-
-        return 0;
-}
-
-/**
- * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
- * @clk: pointer to a DPLL struct clk
- *
- * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
- * The choice of modes depends on the DPLL's programmed rate: if it is
- * the same as the DPLL's parent clock, it will enter bypass;
- * otherwise, it will enter lock.  This code will wait for the DPLL to
- * indicate readiness before returning, unless the DPLL takes too long
- * to enter the target state.  Intended to be used as the struct clk's
- * enable function.  If DPLL3 was passed in, or the DPLL does not
- * support low-power stop, or if the DPLL took too long to enter
- * bypass or lock, return -EINVAL; otherwise, return 0.
- */
-static int omap3_noncore_dpll_enable(struct clk *clk)
-{
-        int r;
-        struct dpll_data *dd;
-
-        if (clk == &dpll3_ck)
-                return -EINVAL;
-
-        dd = clk->dpll_data;
-        if (!dd)
-                return -EINVAL;
-
-        if (clk->rate == dd->clk_bypass->rate) {
-                WARN_ON(clk->parent != dd->clk_bypass);
-                r = _omap3_noncore_dpll_bypass(clk);
-        } else {
-                WARN_ON(clk->parent != dd->clk_ref);
-                r = _omap3_noncore_dpll_lock(clk);
-        }
-        /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
-        if (!r)
-                clk->rate = omap2_get_dpll_rate(clk);
-
-        return r;
-}
-
-/**
- * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
- * @clk: pointer to a DPLL struct clk
- *
- * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
- * The choice of modes depends on the DPLL's programmed rate: if it is
- * the same as the DPLL's parent clock, it will enter bypass;
- * otherwise, it will enter lock.  This code will wait for the DPLL to
- * indicate readiness before returning, unless the DPLL takes too long
- * to enter the target state.  Intended to be used as the struct clk's
- * enable function.  If DPLL3 was passed in, or the DPLL does not
- * support low-power stop, or if the DPLL took too long to enter
- * bypass or lock, return -EINVAL; otherwise, return 0.
- */
-static void omap3_noncore_dpll_disable(struct clk *clk)
-{
-        if (clk == &dpll3_ck)
-                return;
-
-        _omap3_noncore_dpll_stop(clk);
-}
-
-
-/* Non-CORE DPLL rate set code */
-
-/*
- * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
- * @clk: struct clk * of DPLL to set
- * @m: DPLL multiplier to set
- * @n: DPLL divider to set
- * @freqsel: FREQSEL value to set
- *
- * Program the DPLL with the supplied M, N values, and wait for the DPLL to
- * lock..  Returns -EINVAL upon error, or 0 upon success.
- */
-static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
-{
-        struct dpll_data *dd = clk->dpll_data;
-        u32 v;
-
-        /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
-        _omap3_noncore_dpll_bypass(clk);
-
-        /* Set jitter correction */
-        v = __raw_readl(dd->control_reg);
-        v &= ~dd->freqsel_mask;
-        v |= freqsel << __ffs(dd->freqsel_mask);
-        __raw_writel(v, dd->control_reg);
-
-        /* Set DPLL multiplier, divider */
-        v = __raw_readl(dd->mult_div1_reg);
-        v &= ~(dd->mult_mask | dd->div1_mask);
-        v |= m << __ffs(dd->mult_mask);
-        v |= (n - 1) << __ffs(dd->div1_mask);
-        __raw_writel(v, dd->mult_div1_reg);
-
-        /* We let the clock framework set the other output dividers later */
-
-        /* REVISIT: Set ramp-up delay? */
-
-        _omap3_noncore_dpll_lock(clk);
-
-        return 0;
-}
-
-/**
- * omap3_noncore_dpll_set_rate - set non-core DPLL rate
- * @clk: struct clk * of DPLL to set
- * @rate: rounded target rate
- *
- * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
- * low-power bypass, and the target rate is the bypass source clock
- * rate, then configure the DPLL for bypass.  Otherwise, round the
- * target rate if it hasn't been done already, then program and lock
- * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
- */
-static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
-{
-        struct clk *new_parent = NULL;
-        u16 freqsel;
-        struct dpll_data *dd;
-        int ret;
-
-        if (!clk || !rate)
-                return -EINVAL;
-
-        dd = clk->dpll_data;
-        if (!dd)
-                return -EINVAL;
-
-        if (rate == omap2_get_dpll_rate(clk))
-                return 0;
-
-        /*
-         * Ensure both the bypass and ref clocks are enabled prior to
-         * doing anything; we need the bypass clock running to reprogram
-         * the DPLL.
-         */
-        omap2_clk_enable(dd->clk_bypass);
-        omap2_clk_enable(dd->clk_ref);
-
-        if (dd->clk_bypass->rate == rate &&
-            (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
-                pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
-
-                ret = _omap3_noncore_dpll_bypass(clk);
-                if (!ret)
-                        new_parent = dd->clk_bypass;
-        } else {
-                if (dd->last_rounded_rate != rate)
-                        omap2_dpll_round_rate(clk, rate);
-
-                if (dd->last_rounded_rate == 0)
-                        return -EINVAL;
-
-                freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
-                if (!freqsel)
-                        WARN_ON(1);
-
-                pr_debug("clock: %s: set rate: locking rate to %lu.\n",
-                         clk->name, rate);
-
-                ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
-                                                 dd->last_rounded_n, freqsel);
-                if (!ret)
-                        new_parent = dd->clk_ref;
-        }
-        if (!ret) {
-                /*
-                 * Switch the parent clock in the heirarchy, and make sure
-                 * that the new parent's usecount is correct.  Note: we
-                 * enable the new parent before disabling the old to avoid
-                 * any unnecessary hardware disable->enable transitions.
-                 */
-                if (clk->usecount) {
-                        omap2_clk_enable(new_parent);
-                        omap2_clk_disable(clk->parent);
-                }
-                clk_reparent(clk, new_parent);
-                clk->rate = rate;
-        }
-        omap2_clk_disable(dd->clk_ref);
-        omap2_clk_disable(dd->clk_bypass);
+const struct clkops clkops_omap3430es2_hsotgusb_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
 
-        return 0;
-}
+const struct clkops clkops_noncore_dpll_ops = {
+        .enable         = omap3_noncore_dpll_enable,
+        .disable        = omap3_noncore_dpll_disable,
+};
 
-static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
+int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
 {
         /*
          * According to the 12-5 CDP code from TI, "Limitation 2.5"
@@ -831,12 +179,12 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
  * Program the DPLL M2 divider with the rounded target rate.  Returns
  * -EINVAL upon error, or 0 upon success.
  */
-static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
+int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 {
         u32 new_div = 0;
         u32 unlock_dll = 0;
         u32 c;
-        unsigned long validrate, sdrcrate, mpurate;
+        unsigned long validrate, sdrcrate, _mpurate;
         struct omap_sdrc_params *sdrc_cs0;
         struct omap_sdrc_params *sdrc_cs1;
         int ret;
@@ -844,14 +192,11 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         if (!clk || !rate)
                 return -EINVAL;
 
-        if (clk != &dpll3_m2_ck)
-                return -EINVAL;
-
         validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
         if (validrate != rate)
                 return -EINVAL;
 
-        sdrcrate = sdrc_ick.rate;
+        sdrcrate = sdrc_ick_p->rate;
         if (rate > clk->rate)
                 sdrcrate <<= ((rate / clk->rate) >> 1);
         else
@@ -869,8 +214,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         /*
          * XXX This only needs to be done when the CPU frequency changes
          */
-        mpurate = arm_fck.rate / CYCLES_PER_MHZ;
-        c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
+        _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+        c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
         c += 1;  /* for safety */
         c *= SDRC_MPURATE_LOOPS;
         c >>= SDRC_MPURATE_SCALE;
@@ -906,129 +251,6 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-
-static const struct clkops clkops_noncore_dpll_ops = {
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
-};
-
-/* DPLL autoidle read/set code */
-
-
-/**
- * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
- * @clk: struct clk * of the DPLL to read
- *
- * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
- * -EINVAL if passed a null pointer or if the struct clk does not
- * appear to refer to a DPLL.
- */
-static u32 omap3_dpll_autoidle_read(struct clk *clk)
-{
-        const struct dpll_data *dd;
-        u32 v;
-
-        if (!clk || !clk->dpll_data)
-                return -EINVAL;
-
-        dd = clk->dpll_data;
-
-        v = __raw_readl(dd->autoidle_reg);
-        v &= dd->autoidle_mask;
-        v >>= __ffs(dd->autoidle_mask);
-
-        return v;
-}
-
-/**
- * omap3_dpll_allow_idle - enable DPLL autoidle bits
- * @clk: struct clk * of the DPLL to operate on
- *
- * Enable DPLL automatic idle control.  This automatic idle mode
- * switching takes effect only when the DPLL is locked, at least on
- * OMAP3430.  The DPLL will enter low-power stop when its downstream
- * clocks are gated.  No return value.
- */
-static void omap3_dpll_allow_idle(struct clk *clk)
-{
-        const struct dpll_data *dd;
-        u32 v;
-
-        if (!clk || !clk->dpll_data)
-                return;
-
-        dd = clk->dpll_data;
-
-        /*
-         * REVISIT: CORE DPLL can optionally enter low-power bypass
-         * by writing 0x5 instead of 0x1.  Add some mechanism to
-         * optionally enter this mode.
-         */
-        v = __raw_readl(dd->autoidle_reg);
-        v &= ~dd->autoidle_mask;
-        v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
-        __raw_writel(v, dd->autoidle_reg);
-}
-
-/**
- * omap3_dpll_deny_idle - prevent DPLL from automatically idling
- * @clk: struct clk * of the DPLL to operate on
- *
- * Disable DPLL automatic idle control.  No return value.
- */
-static void omap3_dpll_deny_idle(struct clk *clk)
-{
-        const struct dpll_data *dd;
-        u32 v;
-
-        if (!clk || !clk->dpll_data)
-                return;
-
-        dd = clk->dpll_data;
-
-        v = __raw_readl(dd->autoidle_reg);
-        v &= ~dd->autoidle_mask;
-        v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
-        __raw_writel(v, dd->autoidle_reg);
-}
-
-/* Clock control for DPLL outputs */
-
-/**
- * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
- * @clk: DPLL output struct clk
- *
- * Using parent clock DPLL data, look up DPLL state.  If locked, set our
- * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
- */
-static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
-{
-        const struct dpll_data *dd;
-        unsigned long rate;
-        u32 v;
-        struct clk *pclk;
-
-        /* Walk up the parents of clk, looking for a DPLL */
-        pclk = clk->parent;
-        while (pclk && !pclk->dpll_data)
-                pclk = pclk->parent;
-
-        /* clk does not have a DPLL as a parent? */
-        WARN_ON(!pclk);
-
-        dd = pclk->dpll_data;
-
-        WARN_ON(!dd->enable_mask);
-
-        v = __raw_readl(dd->control_reg) & dd->enable_mask;
-        v >>= __ffs(dd->enable_mask);
-        if (v != OMAP3XXX_EN_DPLL_LOCKED)
-                rate = clk->parent->rate;
-        else
-                rate = clk->parent->rate * 2;
-        return rate;
-}
-
 /* Common clock code */
 
 /*
@@ -1037,7 +259,7 @@ static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
  */
 #if defined(CONFIG_ARCH_OMAP3)
 
-static struct clk_functions omap2_clk_functions = {
+struct clk_functions omap2_clk_functions = {
         .clk_enable             = omap2_clk_enable,
         .clk_disable            = omap2_clk_disable,
         .clk_round_rate         = omap2_clk_round_rate,
@@ -1063,7 +285,7 @@ void omap2_clk_prepare_for_reboot(void)
 #endif
 }
 
-static void omap3_clk_lock_dpll5(void)
+void omap3_clk_lock_dpll5(void)
 {
         struct clk *dpll5_clk;
         struct clk *dpll5_m2_clk;
@@ -1093,19 +315,32 @@ static void omap3_clk_lock_dpll5(void)
  */
 static int __init omap2_clk_arch_init(void)
 {
+        struct clk *osc_sys_ck, *dpll1_ck, *arm_fck, *core_ck;
+        unsigned long osc_sys_rate;
+
         if (!mpurate)
                 return -EINVAL;
 
+        /* XXX test these for success */
+        dpll1_ck = clk_get(NULL, "dpll1_ck");
+        arm_fck = clk_get(NULL, "arm_fck");
+        core_ck = clk_get(NULL, "core_ck");
+        osc_sys_ck = clk_get(NULL, "osc_sys_ck");
+
         /* REVISIT: not yet ready for 343x */
-        if (clk_set_rate(&dpll1_ck, mpurate))
+        if (clk_set_rate(dpll1_ck, mpurate))
                 printk(KERN_ERR "*** Unable to set MPU rate\n");
 
         recalculate_root_clocks();
 
-        printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10),
-               (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ;
+        osc_sys_rate = clk_get_rate(osc_sys_ck);
+
+        pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
+                "%ld.%01ld/%ld/%ld MHz\n",
+                (osc_sys_rate / 1000000),
+                ((osc_sys_rate / 100000) % 10),
+                (clk_get_rate(core_ck) / 1000000),
+                (clk_get_rate(arm_fck) / 1000000));
 
         calibrate_delay();
 
@@ -1113,83 +348,7 @@ static int __init omap2_clk_arch_init(void)
 }
 arch_initcall(omap2_clk_arch_init);
 
-int __init omap2_clk_init(void)
-{
-        /* struct prcm_config *prcm; */
-        struct omap_clk *c;
-        /* u32 clkrate; */
-        u32 cpu_clkflg;
-
-        if (cpu_is_omap34xx()) {
-                cpu_mask = RATE_IN_343X;
-                cpu_clkflg = CK_343X;
-
-                /*
-                 * Update this if there are further clock changes between ES2
-                 * and production parts
-                 */
-                if (omap_rev() == OMAP3430_REV_ES1_0) {
-                        /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
-                        cpu_clkflg |= CK_3430ES1;
-                } else {
-                        cpu_mask |= RATE_IN_3430ES2;
-                        cpu_clkflg |= CK_3430ES2;
-                }
-        }
-
-        clk_init(&omap2_clk_functions);
-
-        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
-                clk_preinit(c->lk.clk);
 
-        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
-                if (c->cpu & cpu_clkflg) {
-                        clkdev_add(&c->lk);
-                        clk_register(c->lk.clk);
-                        omap2_init_clk_clkdm(c->lk.clk);
-                }
-
-        /* REVISIT: Not yet ready for OMAP3 */
-#if 0
-        /* Check the MPU rate set by bootloader */
-        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-                if (prcm->dpll_speed <= clkrate)
-                         break;
-        }
-        curr_prcm_set = prcm;
 #endif
 
-        recalculate_root_clocks();
-
-        printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
-               (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
-
-        /*
-         * Only enable those clocks we will need, let the drivers
-         * enable other clocks as necessary
-         */
-        clk_enable_init_clocks();
-
-        /*
-         * Lock DPLL5 and put it in autoidle.
-         */
-        if (omap_rev() >= OMAP3430_REV_ES2_0)
-                omap3_clk_lock_dpll5();
 
-        /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
-        /* REVISIT: not yet ready for 343x */
-#if 0
-        vclk = clk_get(NULL, "virt_prcm_set");
-        sclk = clk_get(NULL, "sys_ck");
-#endif
-        return 0;
-}
-
-#endif
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 8fe1bcb23dd9..9a2c07eac9ad 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1,2993 +1,24 @@
 /*
- * OMAP3 clock framework
+ * OMAP3 clock function prototypes and macros
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
- *
- * Written by Paul Walmsley
- * With many device clock fixes by Kevin Hilman and Jouni Högander
- * DPLL bypass clock support added by Roman Tereshonkov
- *
- */
-
-/*
- * Virtual clocks are introduced as convenient tools.
- * They are sources for other clocks and not supposed
- * to be requested from drivers directly.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
-
-#include <plat/control.h>
-
-#include "clock.h"
-#include "cm.h"
-#include "cm-regbits-34xx.h"
-#include "prm.h"
-#include "prm-regbits-34xx.h"
-
-#define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
-
-static unsigned long omap3_dpll_recalc(struct clk *clk);
-static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
-static void omap3_dpll_allow_idle(struct clk *clk);
-static void omap3_dpll_deny_idle(struct clk *clk);
-static u32 omap3_dpll_autoidle_read(struct clk *clk);
-static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
-static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
-static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
-
-/* Maximum DPLL multiplier, divider values for OMAP3 */
-#define OMAP3_MAX_DPLL_MULT             2048
-#define OMAP3_MAX_DPLL_DIV              128
-
-/*
- * DPLL1 supplies clock to the MPU.
- * DPLL2 supplies clock to the IVA2.
- * DPLL3 supplies CORE domain clocks.
- * DPLL4 supplies peripheral clocks.
- * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
- */
-
-/* Forward declarations for DPLL bypass clocks */
-static struct clk dpll1_fck;
-static struct clk dpll2_fck;
-
-/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
-#define DPLL_LOW_POWER_STOP             0x1
-#define DPLL_LOW_POWER_BYPASS           0x5
-#define DPLL_LOCKED                     0x7
-
-/* PRM CLOCKS */
-
-/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
-static struct clk omap_32k_fck = {
-        .name           = "omap_32k_fck",
-        .ops            = &clkops_null,
-        .rate           = 32768,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk secure_32k_fck = {
-        .name           = "secure_32k_fck",
-        .ops            = &clkops_null,
-        .rate           = 32768,
-        .flags          = RATE_FIXED,
-};
-
-/* Virtual source clocks for osc_sys_ck */
-static struct clk virt_12m_ck = {
-        .name           = "virt_12m_ck",
-        .ops            = &clkops_null,
-        .rate           = 12000000,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk virt_13m_ck = {
-        .name           = "virt_13m_ck",
-        .ops            = &clkops_null,
-        .rate           = 13000000,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk virt_16_8m_ck = {
-        .name           = "virt_16_8m_ck",
-        .ops            = &clkops_null,
-        .rate           = 16800000,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk virt_19_2m_ck = {
-        .name           = "virt_19_2m_ck",
-        .ops            = &clkops_null,
-        .rate           = 19200000,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk virt_26m_ck = {
-        .name           = "virt_26m_ck",
-        .ops            = &clkops_null,
-        .rate           = 26000000,
-        .flags          = RATE_FIXED,
-};
-
-static struct clk virt_38_4m_ck = {
-        .name           = "virt_38_4m_ck",
-        .ops            = &clkops_null,
-        .rate           = 38400000,
-        .flags          = RATE_FIXED,
-};
-
-static const struct clksel_rate osc_sys_12m_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate osc_sys_13m_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate osc_sys_16_8m_rates[] = {
-        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate osc_sys_19_2m_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate osc_sys_26m_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate osc_sys_38_4m_rates[] = {
-        { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel osc_sys_clksel[] = {
-        { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
-        { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
-        { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
-        { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
-        { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
-        { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
-        { .parent = NULL },
-};
-
-/* Oscillator clock */
-/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
-static struct clk osc_sys_ck = {
-        .name           = "osc_sys_ck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP3430_PRM_CLKSEL,
-        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
-        .clksel         = osc_sys_clksel,
-        /* REVISIT: deal with autoextclkmode? */
-        .flags          = RATE_FIXED,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel_rate div2_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 0 }
-};
-
-static const struct clksel sys_clksel[] = {
-        { .parent = &osc_sys_ck, .rates = div2_rates },
-        { .parent = NULL }
-};
-
-/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
-/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
-static struct clk sys_ck = {
-        .name           = "sys_ck",
-        .ops            = &clkops_null,
-        .parent         = &osc_sys_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
-        .clksel_mask    = OMAP_SYSCLKDIV_MASK,
-        .clksel         = sys_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk sys_altclk = {
-        .name           = "sys_altclk",
-        .ops            = &clkops_null,
-};
-
-/* Optional external clock input for some McBSPs */
-static struct clk mcbsp_clks = {
-        .name           = "mcbsp_clks",
-        .ops            = &clkops_null,
-};
-
-/* PRM EXTERNAL CLOCK OUTPUT */
-
-static struct clk sys_clkout1 = {
-        .name           = "sys_clkout1",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &osc_sys_ck,
-        .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
-        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* DPLLS */
-
-/* CM CLOCKS */
-
-static const struct clksel_rate div16_dpll_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 3, .val = 3, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 5, .val = 5, .flags = RATE_IN_343X },
-        { .div = 6, .val = 6, .flags = RATE_IN_343X },
-        { .div = 7, .val = 7, .flags = RATE_IN_343X },
-        { .div = 8, .val = 8, .flags = RATE_IN_343X },
-        { .div = 9, .val = 9, .flags = RATE_IN_343X },
-        { .div = 10, .val = 10, .flags = RATE_IN_343X },
-        { .div = 11, .val = 11, .flags = RATE_IN_343X },
-        { .div = 12, .val = 12, .flags = RATE_IN_343X },
-        { .div = 13, .val = 13, .flags = RATE_IN_343X },
-        { .div = 14, .val = 14, .flags = RATE_IN_343X },
-        { .div = 15, .val = 15, .flags = RATE_IN_343X },
-        { .div = 16, .val = 16, .flags = RATE_IN_343X },
-        { .div = 0 }
-};
-
-/* DPLL1 */
-/* MPU clock source */
-/* Type: DPLL */
-static struct dpll_data dpll1_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
-        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
-        .clk_bypass     = &dpll1_fck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
-        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
-        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
-        .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
-};
-
-static struct clk dpll1_ck = {
-        .name           = "dpll1_ck",
-        .ops            = &clkops_null,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll1_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .clkdm_name     = "dpll1_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-
-/*
- * This virtual clock provides the CLKOUTX2 output from the DPLL if the
- * DPLL isn't bypassed.
- */
-static struct clk dpll1_x2_ck = {
-        .name           = "dpll1_x2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll1_ck,
-        .clkdm_name     = "dpll1_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
-static const struct clksel div16_dpll1_x2m2_clksel[] = {
-        { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-
-/*
- * Does not exist in the TRM - needed to separate the M2 divider from
- * bypass selection in mpu_ck
- */
-static struct clk dpll1_x2m2_ck = {
-        .name           = "dpll1_x2m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll1_x2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
-        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
-        .clksel         = div16_dpll1_x2m2_clksel,
-        .clkdm_name     = "dpll1_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* DPLL2 */
-/* IVA2 clock source */
-/* Type: DPLL */
-
-static struct dpll_data dpll2_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
-        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
-        .clk_bypass     = &dpll2_fck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
-        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
-                                (1 << DPLL_LOW_POWER_BYPASS),
-        .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
-        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
-        .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
-};
-
-static struct clk dpll2_ck = {
-        .name           = "dpll2_ck",
-        .ops            = &clkops_noncore_dpll_ops,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll2_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .clkdm_name     = "dpll2_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-
-static const struct clksel div16_dpll2_m2x2_clksel[] = {
-        { .parent = &dpll2_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-
-/*
- * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
- * or CLKOUTX2. CLKOUT seems most plausible.
- */
-static struct clk dpll2_m2_ck = {
-        .name           = "dpll2_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
-                                          OMAP3430_CM_CLKSEL2_PLL),
-        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
-        .clksel         = div16_dpll2_m2x2_clksel,
-        .clkdm_name     = "dpll2_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/*
- * DPLL3
- * Source clock for all interfaces and for some device fclks
- * REVISIT: Also supports fast relock bypass - not included below
- */
-static struct dpll_data dpll3_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
-        .clk_bypass     = &sys_ck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
-        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
-        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
-};
-
-static struct clk dpll3_ck = {
-        .name           = "dpll3_ck",
-        .ops            = &clkops_null,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll3_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-
-/*
- * This virtual clock provides the CLKOUTX2 output from the DPLL if the
- * DPLL isn't bypassed
- */
-static struct clk dpll3_x2_ck = {
-        .name           = "dpll3_x2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_ck,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static const struct clksel_rate div31_dpll3_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
-        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
-        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
-        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
-        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
-        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
-        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
-        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
-        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
-        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
-        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
-        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
-        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
-        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
-        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
-        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
-        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
-        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
-        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
-        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
-        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
-        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
-        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
-        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
-        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
-        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
-        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
-        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
-        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
-        { .div = 0 },
-};
-
-static const struct clksel div31_dpll3m2_clksel[] = {
-        { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
-        { .parent = NULL }
-};
-
-/* DPLL3 output M2 - primary control point for CORE speed */
-static struct clk dpll3_m2_ck = {
-        .name           = "dpll3_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
-        .clksel         = div31_dpll3m2_clksel,
-        .clkdm_name     = "dpll3_clkdm",
-        .round_rate     = &omap2_clksel_round_rate,
-        .set_rate       = &omap3_core_dpll_m2_set_rate,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk core_ck = {
-        .name           = "core_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_m2_ck,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dpll3_m2x2_ck = {
-        .name           = "dpll3_m2x2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_m2_ck,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static const struct clksel div16_dpll3_clksel[] = {
-        { .parent = &dpll3_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-
-/* This virtual clock is the source for dpll3_m3x2_ck */
-static struct clk dpll3_m3_ck = {
-        .name           = "dpll3_m3_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
-        .clksel         = div16_dpll3_clksel,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll3_m3x2_ck = {
-        .name           = "dpll3_m3x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll3_m3_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static struct clk emu_core_alwon_ck = {
-        .name           = "emu_core_alwon_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_m3x2_ck,
-        .clkdm_name     = "dpll3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* DPLL4 */
-/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
-/* Type: DPLL */
-static struct dpll_data dpll4_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
-        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
-        .clk_bypass     = &sys_ck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
-        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
-        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
-        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
-};
-
-static struct clk dpll4_ck = {
-        .name           = "dpll4_ck",
-        .ops            = &clkops_noncore_dpll_ops,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll4_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_dpll4_set_rate,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-
-/*
- * This virtual clock provides the CLKOUTX2 output from the DPLL if the
- * DPLL isn't bypassed --
- * XXX does this serve any downstream clocks?
- */
-static struct clk dpll4_x2_ck = {
-        .name           = "dpll4_x2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static const struct clksel div16_dpll4_clksel[] = {
-        { .parent = &dpll4_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-
-/* This virtual clock is the source for dpll4_m2x2_ck */
-static struct clk dpll4_m2_ck = {
-        .name           = "dpll4_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
-        .clksel_mask    = OMAP3430_DIV_96M_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m2x2_ck = {
-        .name           = "dpll4_m2x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-/*
- * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
- * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
- * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
- * CM_96K_(F)CLK.
- */
-static struct clk omap_96m_alwon_fck = {
-        .name           = "omap_96m_alwon_fck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_m2x2_ck,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk cm_96m_fck = {
-        .name           = "cm_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_96m_alwon_fck,
-        .recalc         = &followparent_recalc,
-};
-
-static const struct clksel_rate omap_96m_dpll_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate omap_96m_sys_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel omap_96m_fck_clksel[] = {
-        { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
-        { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
-        { .parent = NULL }
-};
-
-static struct clk omap_96m_fck = {
-        .name           = "omap_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &sys_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
-        .clksel         = omap_96m_fck_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* This virtual clock is the source for dpll4_m3x2_ck */
-static struct clk dpll4_m3_ck = {
-        .name           = "dpll4_m3_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m3x2_ck = {
-        .name           = "dpll4_m3x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m3_ck,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate omap_54m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel omap_54m_clksel[] = {
-        { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
-        { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
-        { .parent = NULL }
-};
-
-static struct clk omap_54m_fck = {
-        .name           = "omap_54m_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
-        .clksel         = omap_54m_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel_rate omap_48m_cm96m_rates[] = {
-        { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate omap_48m_alt_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel omap_48m_clksel[] = {
-        { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
-        { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
-        { .parent = NULL }
-};
-
-static struct clk omap_48m_fck = {
-        .name           = "omap_48m_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
-        .clksel         = omap_48m_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk omap_12m_fck = {
-        .name           = "omap_12m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_48m_fck,
-        .fixed_div      = 4,
-        .recalc         = &omap2_fixed_divisor_recalc,
-};
-
-/* This virstual clock is the source for dpll4_m4x2_ck */
-static struct clk dpll4_m4_ck = {
-        .name           = "dpll4_m4_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-        .set_rate       = &omap2_clksel_set_rate,
-        .round_rate     = &omap2_clksel_round_rate,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m4x2_ck = {
-        .name           = "dpll4_m4x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m4_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-/* This virtual clock is the source for dpll4_m5x2_ck */
-static struct clk dpll4_m5_ck = {
-        .name           = "dpll4_m5_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m5x2_ck = {
-        .name           = "dpll4_m5x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m5_ck,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-/* This virtual clock is the source for dpll4_m6x2_ck */
-static struct clk dpll4_m6_ck = {
-        .name           = "dpll4_m6_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
-        .clksel         = div16_dpll4_clksel,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* The PWRDN bit is apparently only available on 3430ES2 and above */
-static struct clk dpll4_m6x2_ck = {
-        .name           = "dpll4_m6x2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll4_m6_ck,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
-        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
-        .flags          = INVERT_ENABLE,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &omap3_clkoutx2_recalc,
-};
-
-static struct clk emu_per_alwon_ck = {
-        .name           = "emu_per_alwon_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll4_m6x2_ck,
-        .clkdm_name     = "dpll4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* DPLL5 */
-/* Supplies 120MHz clock, USIM source clock */
-/* Type: DPLL */
-/* 3430ES2 only */
-static struct dpll_data dpll5_dd = {
-        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
-        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
-        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
-        .clk_bypass     = &sys_ck,
-        .clk_ref        = &sys_ck,
-        .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
-        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
-        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
-        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
-        .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
-        .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
-        .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
-        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
-        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
-        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
-        .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
-        .max_multiplier = OMAP3_MAX_DPLL_MULT,
-        .min_divider    = 1,
-        .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
-};
-
-static struct clk dpll5_ck = {
-        .name           = "dpll5_ck",
-        .ops            = &clkops_noncore_dpll_ops,
-        .parent         = &sys_ck,
-        .dpll_data      = &dpll5_dd,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .clkdm_name     = "dpll5_clkdm",
-        .recalc         = &omap3_dpll_recalc,
-};
-
-static const struct clksel div16_dpll5_clksel[] = {
-        { .parent = &dpll5_ck, .rates = div16_dpll_rates },
-        { .parent = NULL }
-};
-
-static struct clk dpll5_m2_ck = {
-        .name           = "dpll5_m2_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll5_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
-        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
-        .clksel         = div16_dpll5_clksel,
-        .clkdm_name     = "dpll5_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* CM EXTERNAL CLOCK OUTPUTS */
-
-static const struct clksel_rate clkout2_src_core_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate clkout2_src_sys_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate clkout2_src_96m_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate clkout2_src_54m_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel clkout2_src_clksel[] = {
-        { .parent = &core_ck,           .rates = clkout2_src_core_rates },
-        { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
-        { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
-        { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
-        { .parent = NULL }
-};
-
-static struct clk clkout2_src_ck = {
-        .name           = "clkout2_src_ck",
-        .ops            = &clkops_omap2_dflt,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
-        .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
-        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
-        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
-        .clksel         = clkout2_src_clksel,
-        .clkdm_name     = "core_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel_rate sys_clkout2_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 1, .flags = RATE_IN_343X },
-        { .div = 4, .val = 2, .flags = RATE_IN_343X },
-        { .div = 8, .val = 3, .flags = RATE_IN_343X },
-        { .div = 16, .val = 4, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel sys_clkout2_clksel[] = {
-        { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
-        { .parent = NULL },
-};
-
-static struct clk sys_clkout2 = {
-        .name           = "sys_clkout2",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
-        .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
-        .clksel         = sys_clkout2_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* CM OUTPUT CLOCKS */
-
-static struct clk corex2_fck = {
-        .name           = "corex2_fck",
-        .ops            = &clkops_null,
-        .parent         = &dpll3_m2x2_ck,
-        .recalc         = &followparent_recalc,
-};
-
-/* DPLL power domain clock controls */
-
-static const struct clksel_rate div4_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 0 }
-};
-
-static const struct clksel div4_core_clksel[] = {
-        { .parent = &core_ck, .rates = div4_rates },
-        { .parent = NULL }
-};
-
-/*
- * REVISIT: Are these in DPLL power domain or CM power domain? docs
- * may be inconsistent here?
- */
-static struct clk dpll1_fck = {
-        .name           = "dpll1_fck",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
-        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
-        .clksel         = div4_core_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk mpu_ck = {
-        .name           = "mpu_ck",
-        .ops            = &clkops_null,
-        .parent         = &dpll1_x2m2_ck,
-        .clkdm_name     = "mpu_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
-static const struct clksel_rate arm_fck_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 1, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel arm_fck_clksel[] = {
-        { .parent = &mpu_ck, .rates = arm_fck_rates },
-        { .parent = NULL }
-};
-
-static struct clk arm_fck = {
-        .name           = "arm_fck",
-        .ops            = &clkops_null,
-        .parent         = &mpu_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
-        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
-        .clksel         = arm_fck_clksel,
-        .clkdm_name     = "mpu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* XXX What about neon_clkdm ? */
-
-/*
- * REVISIT: This clock is never specifically defined in the 3430 TRM,
- * although it is referenced - so this is a guess
- */
-static struct clk emu_mpu_alwon_ck = {
-        .name           = "emu_mpu_alwon_ck",
-        .ops            = &clkops_null,
-        .parent         = &mpu_ck,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dpll2_fck = {
-        .name           = "dpll2_fck",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
-        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
-        .clksel         = div4_core_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk iva2_ck = {
-        .name           = "iva2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dpll2_m2_ck,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
-        .clkdm_name     = "iva2_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* Common interface clocks */
-
-static const struct clksel div2_core_clksel[] = {
-        { .parent = &core_ck, .rates = div2_rates },
-        { .parent = NULL }
-};
-
-static struct clk l3_ick = {
-        .name           = "l3_ick",
-        .ops            = &clkops_null,
-        .parent         = &core_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
-        .clksel         = div2_core_clksel,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel div2_l3_clksel[] = {
-        { .parent = &l3_ick, .rates = div2_rates },
-        { .parent = NULL }
-};
-
-static struct clk l4_ick = {
-        .name           = "l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &l3_ick,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
-        .clksel         = div2_l3_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-
-};
-
-static const struct clksel div2_l4_clksel[] = {
-        { .parent = &l4_ick, .rates = div2_rates },
-        { .parent = NULL }
-};
-
-static struct clk rm_ick = {
-        .name           = "rm_ick",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
-        .clksel         = div2_l4_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* GFX power domain */
-
-/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
-
-static const struct clksel gfx_l3_clksel[] = {
-        { .parent = &l3_ick, .rates = gfx_l3_rates },
-        { .parent = NULL }
-};
-
-/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
-static struct clk gfx_l3_ck = {
-        .name           = "gfx_l3_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l3_ick,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP_EN_GFX_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gfx_l3_fck = {
-        .name           = "gfx_l3_fck",
-        .ops            = &clkops_null,
-        .parent         = &gfx_l3_ck,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
-        .clksel         = gfx_l3_clksel,
-        .clkdm_name     = "gfx_3430es1_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gfx_l3_ick = {
-        .name           = "gfx_l3_ick",
-        .ops            = &clkops_null,
-        .parent         = &gfx_l3_ck,
-        .clkdm_name     = "gfx_3430es1_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gfx_cg1_ck = {
-        .name           = "gfx_cg1_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
-        .clkdm_name     = "gfx_3430es1_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gfx_cg2_ck = {
-        .name           = "gfx_cg2_ck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
-        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
-        .clkdm_name     = "gfx_3430es1_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* SGX power domain - 3430ES2 only */
-
-static const struct clksel_rate sgx_core_rates[] = {
-        { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 4, .val = 1, .flags = RATE_IN_343X },
-        { .div = 6, .val = 2, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel_rate sgx_96m_rates[] = {
-        { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 },
-};
-
-static const struct clksel sgx_clksel[] = {
-        { .parent = &core_ck,    .rates = sgx_core_rates },
-        { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
-        { .parent = NULL },
-};
-
-static struct clk sgx_fck = {
-        .name           = "sgx_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
-        .clksel         = sgx_clksel,
-        .clkdm_name     = "sgx_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk sgx_ick = {
-        .name           = "sgx_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
-        .clkdm_name     = "sgx_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* CORE power domain */
-
-static struct clk d2d_26m_fck = {
-        .name           = "d2d_26m_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
-        .clkdm_name     = "d2d_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk modem_fck = {
-        .name           = "modem_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
-        .clkdm_name     = "d2d_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk sad2d_ick = {
-        .name           = "sad2d_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
-        .clkdm_name     = "d2d_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mad2d_ick = {
-        .name           = "mad2d_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
-        .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
-        .clkdm_name     = "d2d_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static const struct clksel omap343x_gpt_clksel[] = {
-        { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
-        { .parent = &sys_ck,       .rates = gpt_sys_rates },
-        { .parent = NULL}
-};
-
-static struct clk gpt10_fck = {
-        .name           = "gpt10_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt11_fck = {
-        .name           = "gpt11_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk cpefuse_fck = {
-        .name           = "cpefuse_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
-        .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk ts_fck = {
-        .name           = "ts_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &omap_32k_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
-        .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk usbtll_fck = {
-        .name           = "usbtll_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &dpll5_m2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
-        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* CORE 96M FCLK-derived clocks */
-
-static struct clk core_96m_fck = {
-        .name           = "core_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_96m_fck,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mmchs3_fck = {
-        .name           = "mmchs_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mmchs2_fck = {
-        .name           = "mmchs_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mspro_fck = {
-        .name           = "mspro_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mmchs1_fck = {
-        .name           = "mmchs_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c3_fck = {
-        .name           = "i2c_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 3,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c2_fck = {
-        .name           = "i2c_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c1_fck = {
-        .name           = "i2c_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/*
- * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
- * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
- */
-static const struct clksel_rate common_mcbsp_96m_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 }
-};
-
-static const struct clksel mcbsp_15_clksel[] = {
-        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
-        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
-        { .parent = NULL }
-};
-
-static struct clk mcbsp5_fck = {
-        .name           = "mcbsp_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 5,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
-        .clksel         = mcbsp_15_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk mcbsp1_fck = {
-        .name           = "mcbsp_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
-        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
-        .clksel         = mcbsp_15_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* CORE_48M_FCK-derived clocks */
-
-static struct clk core_48m_fck = {
-        .name           = "core_48m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_48m_fck,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi4_fck = {
-        .name           = "mcspi_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 4,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi3_fck = {
-        .name           = "mcspi_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 3,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi2_fck = {
-        .name           = "mcspi_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi1_fck = {
-        .name           = "mcspi_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk uart2_fck = {
-        .name           = "uart2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk uart1_fck = {
-        .name           = "uart1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk fshostusb_fck = {
-        .name           = "fshostusb_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* CORE_12M_FCK based clocks */
-
-static struct clk core_12m_fck = {
-        .name           = "core_12m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_12m_fck,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk hdq_fck = {
-        .name           = "hdq_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_12m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* DPLL3-derived clock */
-
-static const struct clksel_rate ssi_ssr_corex2_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 3, .val = 3, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 6, .val = 6, .flags = RATE_IN_343X },
-        { .div = 8, .val = 8, .flags = RATE_IN_343X },
-        { .div = 0 }
-};
-
-static const struct clksel ssi_ssr_clksel[] = {
-        { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
-        { .parent = NULL }
-};
-
-static struct clk ssi_ssr_fck_3430es1 = {
-        .name           = "ssi_ssr_fck",
-        .ops            = &clkops_omap2_dflt,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
-        .clksel         = ssi_ssr_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk ssi_ssr_fck_3430es2 = {
-        .name           = "ssi_ssr_fck",
-        .ops            = &clkops_omap3430es2_ssi_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
-        .clksel         = ssi_ssr_clksel,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk ssi_sst_fck_3430es1 = {
-        .name           = "ssi_sst_fck",
-        .ops            = &clkops_null,
-        .parent         = &ssi_ssr_fck_3430es1,
-        .fixed_div      = 2,
-        .recalc         = &omap2_fixed_divisor_recalc,
-};
-
-static struct clk ssi_sst_fck_3430es2 = {
-        .name           = "ssi_sst_fck",
-        .ops            = &clkops_null,
-        .parent         = &ssi_ssr_fck_3430es2,
-        .fixed_div      = 2,
-        .recalc         = &omap2_fixed_divisor_recalc,
-};
-
-
-
-/* CORE_L3_ICK based clocks */
-
-/*
- * XXX must add clk_enable/clk_disable for these if standard code won't
- * handle it
- */
-static struct clk core_l3_ick = {
-        .name           = "core_l3_ick",
-        .ops            = &clkops_null,
-        .parent         = &l3_ick,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk hsotgusb_ick_3430es1 = {
-        .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &core_l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk hsotgusb_ick_3430es2 = {
-        .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap3430es2_hsotgusb_wait,
-        .parent         = &core_l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk sdrc_ick = {
-        .name           = "sdrc_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
-        .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpmc_fck = {
-        .name           = "gpmc_fck",
-        .ops            = &clkops_null,
-        .parent         = &core_l3_ick,
-        .flags          = ENABLE_ON_INIT, /* huh? */
-        .clkdm_name     = "core_l3_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* SECURITY_L3_ICK based clocks */
-
-static struct clk security_l3_ick = {
-        .name           = "security_l3_ick",
-        .ops            = &clkops_null,
-        .parent         = &l3_ick,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk pka_ick = {
-        .name           = "pka_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &security_l3_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_PKA_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* CORE_L4_ICK based clocks */
-
-static struct clk core_l4_ick = {
-        .name           = "core_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk usbtll_ick = {
-        .name           = "usbtll_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
-        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mmchs3_ick = {
-        .name           = "mmchs_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* Intersystem Communication Registers - chassis mode only */
-static struct clk icr_ick = {
-        .name           = "icr_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_ICR_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk aes2_ick = {
-        .name           = "aes2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_AES2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk sha12_ick = {
-        .name           = "sha12_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk des2_ick = {
-        .name           = "des2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_DES2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mmchs2_ick = {
-        .name           = "mmchs_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mmchs1_ick = {
-        .name           = "mmchs_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mspro_ick = {
-        .name           = "mspro_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk hdq_ick = {
-        .name           = "hdq_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi4_ick = {
-        .name           = "mcspi_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 4,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi3_ick = {
-        .name           = "mcspi_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 3,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi2_ick = {
-        .name           = "mcspi_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcspi1_ick = {
-        .name           = "mcspi_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c3_ick = {
-        .name           = "i2c_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 3,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c2_ick = {
-        .name           = "i2c_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk i2c1_ick = {
-        .name           = "i2c_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk uart2_ick = {
-        .name           = "uart2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk uart1_ick = {
-        .name           = "uart1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt11_ick = {
-        .name           = "gpt11_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt10_ick = {
-        .name           = "gpt10_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcbsp5_ick = {
-        .name           = "mcbsp_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 5,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcbsp1_ick = {
-        .name           = "mcbsp_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 1,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk fac_ick = {
-        .name           = "fac_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mailboxes_ick = {
-        .name           = "mailboxes_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk omapctrl_ick = {
-        .name           = "omapctrl_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &core_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
-        .flags          = ENABLE_ON_INIT,
-        .recalc         = &followparent_recalc,
-};
-
-/* SSI_L4_ICK based clocks */
-
-static struct clk ssi_l4_ick = {
-        .name           = "ssi_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk ssi_ick_3430es1 = {
-        .name           = "ssi_ick",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &ssi_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk ssi_ick_3430es2 = {
-        .name           = "ssi_ick",
-        .ops            = &clkops_omap3430es2_ssi_wait,
-        .parent         = &ssi_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
- * but l4_ick makes more sense to me */
-
-static const struct clksel usb_l4_clksel[] = {
-        { .parent = &l4_ick, .rates = div2_rates },
-        { .parent = NULL },
-};
-
-static struct clk usb_l4_ick = {
-        .name           = "usb_l4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ick,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
-        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
-        .clksel         = usb_l4_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* SECURITY_L4_ICK2 based clocks */
-
-static struct clk security_l4_ick2 = {
-        .name           = "security_l4_ick2",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk aes1_ick = {
-        .name           = "aes1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &security_l4_ick2,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_AES1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk rng_ick = {
-        .name           = "rng_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &security_l4_ick2,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_RNG_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk sha11_ick = {
-        .name           = "sha11_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &security_l4_ick2,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk des1_ick = {
-        .name           = "des1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &security_l4_ick2,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
-        .enable_bit     = OMAP3430_EN_DES1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* DSS */
-static struct clk dss1_alwon_fck_3430es1 = {
-        .name           = "dss1_alwon_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &dpll4_m4x2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dss1_alwon_fck_3430es2 = {
-        .name           = "dss1_alwon_fck",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
-        .parent         = &dpll4_m4x2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dss_tv_fck = {
-        .name           = "dss_tv_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &omap_54m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_TV_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dss_96m_fck = {
-        .name           = "dss_96m_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &omap_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_TV_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dss2_alwon_fck = {
-        .name           = "dss2_alwon_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dss_ick_3430es1 = {
-        /* Handles both L3 and L4 clocks */
-        .name           = "dss_ick",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk dss_ick_3430es2 = {
-        /* Handles both L3 and L4 clocks */
-        .name           = "dss_ick",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
-        .parent         = &l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
-        .clkdm_name     = "dss_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* CAM */
-
-static struct clk cam_mclk = {
-        .name           = "cam_mclk",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &dpll4_m5x2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
-        .clkdm_name     = "cam_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk cam_ick = {
-        /* Handles both L3 and L4 clocks */
-        .name           = "cam_ick",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
-        .clkdm_name     = "cam_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk csi2_96m_fck = {
-        .name           = "csi2_96m_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &core_96m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
-        .clkdm_name     = "cam_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* USBHOST - 3430ES2 only */
-
-static struct clk usbhost_120m_fck = {
-        .name           = "usbhost_120m_fck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &dpll5_m2_ck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
-        .clkdm_name     = "usbhost_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk usbhost_48m_fck = {
-        .name           = "usbhost_48m_fck",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
-        .parent         = &omap_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
-        .clkdm_name     = "usbhost_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk usbhost_ick = {
-        /* Handles both L3 and L4 clocks */
-        .name           = "usbhost_ick",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
-        .parent         = &l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
-        .clkdm_name     = "usbhost_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* WKUP */
-
-static const struct clksel_rate usim_96m_rates[] = {
-        { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 4,  .val = 4, .flags = RATE_IN_343X },
-        { .div = 8,  .val = 5, .flags = RATE_IN_343X },
-        { .div = 10, .val = 6, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel_rate usim_120m_rates[] = {
-        { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
-        { .div = 16, .val = 9,  .flags = RATE_IN_343X },
-        { .div = 20, .val = 10, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel usim_clksel[] = {
-        { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
-        { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
-        { .parent = &sys_ck,            .rates = div2_rates },
-        { .parent = NULL },
-};
-
-/* 3430ES2 only */
-static struct clk usim_fck = {
-        .name           = "usim_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
-        .clksel         = usim_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
-static struct clk gpt1_fck = {
-        .name           = "gpt1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk wkup_32k_fck = {
-        .name           = "wkup_32k_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_32k_fck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio1_dbck = {
-        .name           = "gpio1_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &wkup_32k_fck,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk wdt2_fck = {
-        .name           = "wdt2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_32k_fck,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk wkup_l4_ick = {
-        .name           = "wkup_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &sys_ck,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* 3430ES2 only */
-/* Never specifically named in the TRM, so we have to infer a likely name */
-static struct clk usim_ick = {
-        .name           = "usim_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk wdt2_ick = {
-        .name           = "wdt2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk wdt1_ick = {
-        .name           = "wdt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio1_ick = {
-        .name           = "gpio1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk omap_32ksync_ick = {
-        .name           = "omap_32ksync_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-/* XXX This clock no longer exists in 3430 TRM rev F */
-static struct clk gpt12_ick = {
-        .name           = "gpt12_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt1_ick = {
-        .name           = "gpt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &wkup_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
-        .clkdm_name     = "wkup_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-
-
-/* PER clock domain */
-
-static struct clk per_96m_fck = {
-        .name           = "per_96m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_96m_alwon_fck,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk per_48m_fck = {
-        .name           = "per_48m_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_48m_fck,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk uart3_fck = {
-        .name           = "uart3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt2_fck = {
-        .name           = "gpt2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt3_fck = {
-        .name           = "gpt3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt4_fck = {
-        .name           = "gpt4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt5_fck = {
-        .name           = "gpt5_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt6_fck = {
-        .name           = "gpt6_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt7_fck = {
-        .name           = "gpt7_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt8_fck = {
-        .name           = "gpt8_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk gpt9_fck = {
-        .name           = "gpt9_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
-        .clksel         = omap343x_gpt_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk per_32k_alwon_fck = {
-        .name           = "per_32k_alwon_fck",
-        .ops            = &clkops_null,
-        .parent         = &omap_32k_fck,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio6_dbck = {
-        .name           = "gpio6_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio5_dbck = {
-        .name           = "gpio5_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio4_dbck = {
-        .name           = "gpio4_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio3_dbck = {
-        .name           = "gpio3_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio2_dbck = {
-        .name           = "gpio2_dbck",
-        .ops            = &clkops_omap2_dflt,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk wdt3_fck = {
-        .name           = "wdt3_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_32k_alwon_fck,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk per_l4_ick = {
-        .name           = "per_l4_ick",
-        .ops            = &clkops_null,
-        .parent         = &l4_ick,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio6_ick = {
-        .name           = "gpio6_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio5_ick = {
-        .name           = "gpio5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio4_ick = {
-        .name           = "gpio4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio3_ick = {
-        .name           = "gpio3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpio2_ick = {
-        .name           = "gpio2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk wdt3_ick = {
-        .name           = "wdt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk uart3_ick = {
-        .name           = "uart3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt9_ick = {
-        .name           = "gpt9_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt8_ick = {
-        .name           = "gpt8_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt7_ick = {
-        .name           = "gpt7_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt6_ick = {
-        .name           = "gpt6_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt5_ick = {
-        .name           = "gpt5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt4_ick = {
-        .name           = "gpt4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt3_ick = {
-        .name           = "gpt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk gpt2_ick = {
-        .name           = "gpt2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcbsp2_ick = {
-        .name           = "mcbsp_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcbsp3_ick = {
-        .name           = "mcbsp_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 3,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk mcbsp4_ick = {
-        .name           = "mcbsp_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 4,
-        .parent         = &per_l4_ick,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &followparent_recalc,
-};
-
-static const struct clksel mcbsp_234_clksel[] = {
-        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
-        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
-        { .parent = NULL }
-};
-
-static struct clk mcbsp2_fck = {
-        .name           = "mcbsp_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 2,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
-        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
-        .clksel         = mcbsp_234_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk mcbsp3_fck = {
-        .name           = "mcbsp_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 3,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
-        .clksel         = mcbsp_234_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk mcbsp4_fck = {
-        .name           = "mcbsp_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .id             = 4,
-        .init           = &omap2_init_clksel_parent,
-        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
-        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
-        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
-        .clksel         = mcbsp_234_clksel,
-        .clkdm_name     = "per_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* EMU clocks */
-
-/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
-
-static const struct clksel_rate emu_src_sys_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 },
-};
-
-static const struct clksel_rate emu_src_core_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 },
-};
-
-static const struct clksel_rate emu_src_per_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 },
-};
-
-static const struct clksel_rate emu_src_mpu_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 0 },
-};
-
-static const struct clksel emu_src_clksel[] = {
-        { .parent = &sys_ck,            .rates = emu_src_sys_rates },
-        { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
-        { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
-        { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
-        { .parent = NULL },
-};
-
-/*
- * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
- * to switch the source of some of the EMU clocks.
- * XXX Are there CLKEN bits for these EMU clks?
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  */
-static struct clk emu_src_ck = {
-        .name           = "emu_src_ck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
-        .clksel         = emu_src_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel_rate pclk_emu_rates[] = {
-        { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 3, .val = 3, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 6, .val = 6, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel pclk_emu_clksel[] = {
-        { .parent = &emu_src_ck, .rates = pclk_emu_rates },
-        { .parent = NULL },
-};
-
-static struct clk pclk_fck = {
-        .name           = "pclk_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
-        .clksel         = pclk_emu_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel_rate pclkx2_emu_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 3, .val = 3, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel pclkx2_emu_clksel[] = {
-        { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
-        { .parent = NULL },
-};
-
-static struct clk pclkx2_fck = {
-        .name           = "pclkx2_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
-        .clksel         = pclkx2_emu_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel atclk_emu_clksel[] = {
-        { .parent = &emu_src_ck, .rates = div2_rates },
-        { .parent = NULL },
-};
-
-static struct clk atclk_fck = {
-        .name           = "atclk_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
-        .clksel         = atclk_emu_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static struct clk traceclk_src_fck = {
-        .name           = "traceclk_src_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
-        .clksel         = emu_src_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-static const struct clksel_rate traceclk_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
-        { .div = 2, .val = 2, .flags = RATE_IN_343X },
-        { .div = 4, .val = 4, .flags = RATE_IN_343X },
-        { .div = 0 },
-};
-
-static const struct clksel traceclk_clksel[] = {
-        { .parent = &traceclk_src_fck, .rates = traceclk_rates },
-        { .parent = NULL },
-};
-
-static struct clk traceclk_fck = {
-        .name           = "traceclk_fck",
-        .ops            = &clkops_null,
-        .init           = &omap2_init_clksel_parent,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
-        .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
-        .clksel         = traceclk_clksel,
-        .clkdm_name     = "emu_clkdm",
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* SR clocks */
-
-/* SmartReflex fclk (VDD1) */
-static struct clk sr1_fck = {
-        .name           = "sr1_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
-        .recalc         = &followparent_recalc,
-};
-
-/* SmartReflex fclk (VDD2) */
-static struct clk sr2_fck = {
-        .name           = "sr2_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &sys_ck,
-        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
-        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
-        .recalc         = &followparent_recalc,
-};
 
-static struct clk sr_l4_ick = {
-        .name           = "sr_l4_ick",
-        .ops            = &clkops_null, /* RMK: missing? */
-        .parent         = &l4_ick,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
-};
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK_34XX_H
 
-/* SECURE_32K_FCK clocks */
+int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
+int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
+void omap3_clk_lock_dpll5(void);
 
-static struct clk gpt12_fck = {
-        .name           = "gpt12_fck",
-        .ops            = &clkops_null,
-        .parent         = &secure_32k_fck,
-        .recalc         = &followparent_recalc,
-};
+extern struct clk *sdrc_ick_p;
+extern struct clk *arm_fck_p;
 
-static struct clk wdt1_fck = {
-        .name           = "wdt1_fck",
-        .ops            = &clkops_null,
-        .parent         = &secure_32k_fck,
-        .recalc         = &followparent_recalc,
-};
+/* OMAP34xx-specific clkops */
+extern const struct clkops clkops_omap3430es2_ssi_wait;
+extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
+extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
+extern const struct clkops clkops_noncore_dpll_ops;
 
 #endif
diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
new file mode 100644
index 000000000000..8bdcc9cc7f9a
--- /dev/null
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -0,0 +1,3289 @@
+/*
+ * OMAP3 clock data
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ * With many device clock fixes by Kevin Hilman and Jouni Högander
+ * DPLL bypass clock support added by Roman Tereshonkov
+ *
+ */
+
+/*
+ * Virtual clocks are introduced as convenient tools.
+ * They are sources for other clocks and not supposed
+ * to be requested from drivers directly.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+
+#include <plat/control.h>
+#include <plat/clkdev_omap.h>
+
+#include "clock.h"
+#include "clock34xx.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+
+/*
+ * clocks
+ */
+
+#define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
+
+/* Maximum DPLL multiplier, divider values for OMAP3 */
+#define OMAP3_MAX_DPLL_MULT             2048
+#define OMAP3_MAX_DPLL_DIV              128
+
+/*
+ * DPLL1 supplies clock to the MPU.
+ * DPLL2 supplies clock to the IVA2.
+ * DPLL3 supplies CORE domain clocks.
+ * DPLL4 supplies peripheral clocks.
+ * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
+ */
+
+/* Forward declarations for DPLL bypass clocks */
+static struct clk dpll1_fck;
+static struct clk dpll2_fck;
+
+/* PRM CLOCKS */
+
+/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
+static struct clk omap_32k_fck = {
+        .name           = "omap_32k_fck",
+        .ops            = &clkops_null,
+        .rate           = 32768,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk secure_32k_fck = {
+        .name           = "secure_32k_fck",
+        .ops            = &clkops_null,
+        .rate           = 32768,
+        .flags          = RATE_FIXED,
+};
+
+/* Virtual source clocks for osc_sys_ck */
+static struct clk virt_12m_ck = {
+        .name           = "virt_12m_ck",
+        .ops            = &clkops_null,
+        .rate           = 12000000,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk virt_13m_ck = {
+        .name           = "virt_13m_ck",
+        .ops            = &clkops_null,
+        .rate           = 13000000,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk virt_16_8m_ck = {
+        .name           = "virt_16_8m_ck",
+        .ops            = &clkops_null,
+        .rate           = 16800000,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk virt_19_2m_ck = {
+        .name           = "virt_19_2m_ck",
+        .ops            = &clkops_null,
+        .rate           = 19200000,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk virt_26m_ck = {
+        .name           = "virt_26m_ck",
+        .ops            = &clkops_null,
+        .rate           = 26000000,
+        .flags          = RATE_FIXED,
+};
+
+static struct clk virt_38_4m_ck = {
+        .name           = "virt_38_4m_ck",
+        .ops            = &clkops_null,
+        .rate           = 38400000,
+        .flags          = RATE_FIXED,
+};
+
+static const struct clksel_rate osc_sys_12m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_13m_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_16_8m_rates[] = {
+        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_19_2m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_26m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate osc_sys_38_4m_rates[] = {
+        { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel osc_sys_clksel[] = {
+        { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
+        { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
+        { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
+        { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
+        { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
+        { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
+        { .parent = NULL },
+};
+
+/* Oscillator clock */
+/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
+static struct clk osc_sys_ck = {
+        .name           = "osc_sys_ck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_PRM_CLKSEL,
+        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
+        .clksel         = osc_sys_clksel,
+        /* REVISIT: deal with autoextclkmode? */
+        .flags          = RATE_FIXED,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate div2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel sys_clksel[] = {
+        { .parent = &osc_sys_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
+/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
+static struct clk sys_ck = {
+        .name           = "sys_ck",
+        .ops            = &clkops_null,
+        .parent         = &osc_sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
+        .clksel_mask    = OMAP_SYSCLKDIV_MASK,
+        .clksel         = sys_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk sys_altclk = {
+        .name           = "sys_altclk",
+        .ops            = &clkops_null,
+};
+
+/* Optional external clock input for some McBSPs */
+static struct clk mcbsp_clks = {
+        .name           = "mcbsp_clks",
+        .ops            = &clkops_null,
+};
+
+/* PRM EXTERNAL CLOCK OUTPUT */
+
+static struct clk sys_clkout1 = {
+        .name           = "sys_clkout1",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &osc_sys_ck,
+        .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLLS */
+
+/* CM CLOCKS */
+
+static const struct clksel_rate div16_dpll_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 5, .val = 5, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 7, .val = 7, .flags = RATE_IN_343X },
+        { .div = 8, .val = 8, .flags = RATE_IN_343X },
+        { .div = 9, .val = 9, .flags = RATE_IN_343X },
+        { .div = 10, .val = 10, .flags = RATE_IN_343X },
+        { .div = 11, .val = 11, .flags = RATE_IN_343X },
+        { .div = 12, .val = 12, .flags = RATE_IN_343X },
+        { .div = 13, .val = 13, .flags = RATE_IN_343X },
+        { .div = 14, .val = 14, .flags = RATE_IN_343X },
+        { .div = 15, .val = 15, .flags = RATE_IN_343X },
+        { .div = 16, .val = 16, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+/* DPLL1 */
+/* MPU clock source */
+/* Type: DPLL */
+static struct dpll_data dpll1_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
+        .clk_bypass     = &dpll1_fck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+};
+
+static struct clk dpll1_ck = {
+        .name           = "dpll1_ck",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll1_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .clkdm_name     = "dpll1_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed.
+ */
+static struct clk dpll1_x2_ck = {
+        .name           = "dpll1_x2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll1_ck,
+        .clkdm_name     = "dpll1_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
+static const struct clksel div16_dpll1_x2m2_clksel[] = {
+        { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/*
+ * Does not exist in the TRM - needed to separate the M2 divider from
+ * bypass selection in mpu_ck
+ */
+static struct clk dpll1_x2m2_ck = {
+        .name           = "dpll1_x2m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll1_x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
+        .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div16_dpll1_x2m2_clksel,
+        .clkdm_name     = "dpll1_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* DPLL2 */
+/* IVA2 clock source */
+/* Type: DPLL */
+
+static struct dpll_data dpll2_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
+        .clk_bypass     = &dpll2_fck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
+        .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
+                                (1 << DPLL_LOW_POWER_BYPASS),
+        .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
+        .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
+        .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+};
+
+static struct clk dpll2_ck = {
+        .name           = "dpll2_ck",
+        .ops            = &clkops_noncore_dpll_ops,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll2_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .clkdm_name     = "dpll2_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll2_m2x2_clksel[] = {
+        { .parent = &dpll2_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/*
+ * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
+ * or CLKOUTX2. CLKOUT seems most plausible.
+ */
+static struct clk dpll2_m2_ck = {
+        .name           = "dpll2_m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
+                                          OMAP3430_CM_CLKSEL2_PLL),
+        .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div16_dpll2_m2x2_clksel,
+        .clkdm_name     = "dpll2_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/*
+ * DPLL3
+ * Source clock for all interfaces and for some device fclks
+ * REVISIT: Also supports fast relock bypass - not included below
+ */
+static struct dpll_data dpll3_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
+        .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+};
+
+static struct clk dpll3_ck = {
+        .name           = "dpll3_ck",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll3_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed
+ */
+static struct clk dpll3_x2_ck = {
+        .name           = "dpll3_x2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_ck,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel_rate div31_dpll3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
+        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
+        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
+        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
+        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
+        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
+        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
+        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
+        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
+        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
+        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
+        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
+        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
+        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
+        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
+        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
+        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
+        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
+        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
+        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
+        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
+        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
+        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
+        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
+        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
+        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
+        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
+        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
+        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
+        { .div = 0 },
+};
+
+static const struct clksel div31_dpll3m2_clksel[] = {
+        { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
+        { .parent = NULL }
+};
+
+/* DPLL3 output M2 - primary control point for CORE speed */
+static struct clk dpll3_m2_ck = {
+        .name           = "dpll3_m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
+        .clksel         = div31_dpll3m2_clksel,
+        .clkdm_name     = "dpll3_clkdm",
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap3_core_dpll_m2_set_rate,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk core_ck = {
+        .name           = "core_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m2_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dpll3_m2x2_ck = {
+        .name           = "dpll3_m2x2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m2_ck,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static const struct clksel div16_dpll3_clksel[] = {
+        { .parent = &dpll3_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/* This virtual clock is the source for dpll3_m3x2_ck */
+static struct clk dpll3_m3_ck = {
+        .name           = "dpll3_m3_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
+        .clksel         = div16_dpll3_clksel,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll3_m3x2_ck = {
+        .name           = "dpll3_m3x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll3_m3_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static struct clk emu_core_alwon_ck = {
+        .name           = "emu_core_alwon_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m3x2_ck,
+        .clkdm_name     = "dpll3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL4 */
+/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
+/* Type: DPLL */
+static struct dpll_data dpll4_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
+        .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
+        .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
+        .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+};
+
+static struct clk dpll4_ck = {
+        .name           = "dpll4_ck",
+        .ops            = &clkops_noncore_dpll_ops,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll4_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_dpll4_set_rate,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * This virtual clock provides the CLKOUTX2 output from the DPLL if the
+ * DPLL isn't bypassed --
+ * XXX does this serve any downstream clocks?
+ */
+static struct clk dpll4_x2_ck = {
+        .name           = "dpll4_x2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel div16_dpll4_clksel[] = {
+        { .parent = &dpll4_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+/* This virtual clock is the source for dpll4_m2x2_ck */
+static struct clk dpll4_m2_ck = {
+        .name           = "dpll4_m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
+        .clksel_mask    = OMAP3430_DIV_96M_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m2x2_ck = {
+        .name           = "dpll4_m2x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/*
+ * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
+ * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
+ * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
+ * CM_96K_(F)CLK.
+ */
+static struct clk omap_96m_alwon_fck = {
+        .name           = "omap_96m_alwon_fck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_m2x2_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cm_96m_fck = {
+        .name           = "cm_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_96m_alwon_fck,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel_rate omap_96m_dpll_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_96m_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_96m_fck_clksel[] = {
+        { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
+        { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_96m_fck = {
+        .name           = "omap_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
+        .clksel         = omap_96m_fck_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m3x2_ck */
+static struct clk dpll4_m3_ck = {
+        .name           = "dpll4_m3_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m3x2_ck = {
+        .name           = "dpll4_m3x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_54m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_54m_clksel[] = {
+        { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
+        { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_54m_fck = {
+        .name           = "omap_54m_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
+        .clksel         = omap_54m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate omap_48m_cm96m_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate omap_48m_alt_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel omap_48m_clksel[] = {
+        { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
+        { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
+        { .parent = NULL }
+};
+
+static struct clk omap_48m_fck = {
+        .name           = "omap_48m_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
+        .clksel         = omap_48m_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk omap_12m_fck = {
+        .name           = "omap_12m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_48m_fck,
+        .fixed_div      = 4,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+/* This virstual clock is the source for dpll4_m4x2_ck */
+static struct clk dpll4_m4_ck = {
+        .name           = "dpll4_m4_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+        .set_rate       = &omap2_clksel_set_rate,
+        .round_rate     = &omap2_clksel_round_rate,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m4x2_ck = {
+        .name           = "dpll4_m4x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m4_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m5x2_ck */
+static struct clk dpll4_m5_ck = {
+        .name           = "dpll4_m5_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m5x2_ck = {
+        .name           = "dpll4_m5x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m5_ck,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+/* This virtual clock is the source for dpll4_m6x2_ck */
+static struct clk dpll4_m6_ck = {
+        .name           = "dpll4_m6_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
+        .clksel         = div16_dpll4_clksel,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* The PWRDN bit is apparently only available on 3430ES2 and above */
+static struct clk dpll4_m6x2_ck = {
+        .name           = "dpll4_m6x2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll4_m6_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
+        .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
+        .flags          = INVERT_ENABLE,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static struct clk emu_per_alwon_ck = {
+        .name           = "emu_per_alwon_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll4_m6x2_ck,
+        .clkdm_name     = "dpll4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL5 */
+/* Supplies 120MHz clock, USIM source clock */
+/* Type: DPLL */
+/* 3430ES2 only */
+static struct dpll_data dpll5_dd = {
+        .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
+        .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
+        .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
+        .clk_bypass     = &sys_ck,
+        .clk_ref        = &sys_ck,
+        .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
+        .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
+        .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
+        .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
+        .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
+        .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
+        .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
+        .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
+        .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
+        .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
+        .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
+        .max_multiplier = OMAP3_MAX_DPLL_MULT,
+        .min_divider    = 1,
+        .max_divider    = OMAP3_MAX_DPLL_DIV,
+        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
+};
+
+static struct clk dpll5_ck = {
+        .name           = "dpll5_ck",
+        .ops            = &clkops_noncore_dpll_ops,
+        .parent         = &sys_ck,
+        .dpll_data      = &dpll5_dd,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .clkdm_name     = "dpll5_clkdm",
+        .recalc         = &omap3_dpll_recalc,
+};
+
+static const struct clksel div16_dpll5_clksel[] = {
+        { .parent = &dpll5_ck, .rates = div16_dpll_rates },
+        { .parent = NULL }
+};
+
+static struct clk dpll5_m2_ck = {
+        .name           = "dpll5_m2_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll5_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
+        .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
+        .clksel         = div16_dpll5_clksel,
+        .clkdm_name     = "dpll5_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CM EXTERNAL CLOCK OUTPUTS */
+
+static const struct clksel_rate clkout2_src_core_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_sys_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_96m_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate clkout2_src_54m_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel clkout2_src_clksel[] = {
+        { .parent = &core_ck,           .rates = clkout2_src_core_rates },
+        { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
+        { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
+        { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
+        { .parent = NULL }
+};
+
+static struct clk clkout2_src_ck = {
+        .name           = "clkout2_src_ck",
+        .ops            = &clkops_omap2_dflt,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
+        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
+        .clksel         = clkout2_src_clksel,
+        .clkdm_name     = "core_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate sys_clkout2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_343X },
+        { .div = 4, .val = 2, .flags = RATE_IN_343X },
+        { .div = 8, .val = 3, .flags = RATE_IN_343X },
+        { .div = 16, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel sys_clkout2_clksel[] = {
+        { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
+        { .parent = NULL },
+};
+
+static struct clk sys_clkout2 = {
+        .name           = "sys_clkout2",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
+        .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
+        .clksel         = sys_clkout2_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CM OUTPUT CLOCKS */
+
+static struct clk corex2_fck = {
+        .name           = "corex2_fck",
+        .ops            = &clkops_null,
+        .parent         = &dpll3_m2x2_ck,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL power domain clock controls */
+
+static const struct clksel_rate div4_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel div4_core_clksel[] = {
+        { .parent = &core_ck, .rates = div4_rates },
+        { .parent = NULL }
+};
+
+/*
+ * REVISIT: Are these in DPLL power domain or CM power domain? docs
+ * may be inconsistent here?
+ */
+static struct clk dpll1_fck = {
+        .name           = "dpll1_fck",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
+        .clksel         = div4_core_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mpu_ck = {
+        .name           = "mpu_ck",
+        .ops            = &clkops_null,
+        .parent         = &dpll1_x2m2_ck,
+        .clkdm_name     = "mpu_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
+static const struct clksel_rate arm_fck_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 1, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel arm_fck_clksel[] = {
+        { .parent = &mpu_ck, .rates = arm_fck_rates },
+        { .parent = NULL }
+};
+
+static struct clk arm_fck = {
+        .name           = "arm_fck",
+        .ops            = &clkops_null,
+        .parent         = &mpu_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
+        .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
+        .clksel         = arm_fck_clksel,
+        .clkdm_name     = "mpu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* XXX What about neon_clkdm ? */
+
+/*
+ * REVISIT: This clock is never specifically defined in the 3430 TRM,
+ * although it is referenced - so this is a guess
+ */
+static struct clk emu_mpu_alwon_ck = {
+        .name           = "emu_mpu_alwon_ck",
+        .ops            = &clkops_null,
+        .parent         = &mpu_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dpll2_fck = {
+        .name           = "dpll2_fck",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
+        .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
+        .clksel         = div4_core_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk iva2_ck = {
+        .name           = "iva2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &dpll2_m2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
+        .clkdm_name     = "iva2_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* Common interface clocks */
+
+static const struct clksel div2_core_clksel[] = {
+        { .parent = &core_ck, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+static struct clk l3_ick = {
+        .name           = "l3_ick",
+        .ops            = &clkops_null,
+        .parent         = &core_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
+        .clksel         = div2_core_clksel,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel div2_l3_clksel[] = {
+        { .parent = &l3_ick, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+static struct clk l4_ick = {
+        .name           = "l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &l3_ick,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
+        .clksel         = div2_l3_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+
+};
+
+static const struct clksel div2_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL }
+};
+
+static struct clk rm_ick = {
+        .name           = "rm_ick",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
+        .clksel         = div2_l4_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* GFX power domain */
+
+/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
+
+static const struct clksel gfx_l3_clksel[] = {
+        { .parent = &l3_ick, .rates = gfx_l3_rates },
+        { .parent = NULL }
+};
+
+/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
+static struct clk gfx_l3_ck = {
+        .name           = "gfx_l3_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l3_ick,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP_EN_GFX_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gfx_l3_fck = {
+        .name           = "gfx_l3_fck",
+        .ops            = &clkops_null,
+        .parent         = &gfx_l3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
+        .clksel         = gfx_l3_clksel,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gfx_l3_ick = {
+        .name           = "gfx_l3_ick",
+        .ops            = &clkops_null,
+        .parent         = &gfx_l3_ck,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gfx_cg1_ck = {
+        .name           = "gfx_cg1_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gfx_cg2_ck = {
+        .name           = "gfx_cg2_ck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &gfx_l3_fck, /* REVISIT: correct? */
+        .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
+        .clkdm_name     = "gfx_3430es1_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* SGX power domain - 3430ES2 only */
+
+static const struct clksel_rate sgx_core_rates[] = {
+        { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 4, .val = 1, .flags = RATE_IN_343X },
+        { .div = 6, .val = 2, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel_rate sgx_96m_rates[] = {
+        { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel sgx_clksel[] = {
+        { .parent = &core_ck,    .rates = sgx_core_rates },
+        { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
+        { .parent = NULL },
+};
+
+static struct clk sgx_fck = {
+        .name           = "sgx_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
+        .clksel         = sgx_clksel,
+        .clkdm_name     = "sgx_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk sgx_ick = {
+        .name           = "sgx_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
+        .clkdm_name     = "sgx_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE power domain */
+
+static struct clk d2d_26m_fck = {
+        .name           = "d2d_26m_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk modem_fck = {
+        .name           = "modem_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sad2d_ick = {
+        .name           = "sad2d_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mad2d_ick = {
+        .name           = "mad2d_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
+        .clkdm_name     = "d2d_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel omap343x_gpt_clksel[] = {
+        { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
+        { .parent = &sys_ck,       .rates = gpt_sys_rates },
+        { .parent = NULL}
+};
+
+static struct clk gpt10_fck = {
+        .name           = "gpt10_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt11_fck = {
+        .name           = "gpt11_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk cpefuse_fck = {
+        .name           = "cpefuse_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ts_fck = {
+        .name           = "ts_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &omap_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbtll_fck = {
+        .name           = "usbtll_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &dpll5_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE 96M FCLK-derived clocks */
+
+static struct clk core_96m_fck = {
+        .name           = "core_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_96m_fck,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs3_fck = {
+        .name           = "mmchs_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_fck = {
+        .name           = "mmchs_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_fck = {
+        .name           = "mspro_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_fck = {
+        .name           = "mmchs_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c3_fck = {
+        .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 3,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_fck = {
+        .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_fck = {
+        .name           = "i2c_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
+ * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
+ */
+static const struct clksel_rate common_mcbsp_96m_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 }
+};
+
+static const struct clksel mcbsp_15_clksel[] = {
+        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
+static struct clk mcbsp5_fck = {
+        .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 5,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
+        .clksel         = mcbsp_15_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp1_fck = {
+        .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
+        .clksel         = mcbsp_15_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* CORE_48M_FCK-derived clocks */
+
+static struct clk core_48m_fck = {
+        .name           = "core_48m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_48m_fck,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi4_fck = {
+        .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 4,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_fck = {
+        .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 3,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_fck = {
+        .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_fck = {
+        .name           = "mcspi_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_fck = {
+        .name           = "uart2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_fck = {
+        .name           = "uart1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fshostusb_fck = {
+        .name           = "fshostusb_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE_12M_FCK based clocks */
+
+static struct clk core_12m_fck = {
+        .name           = "core_12m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_12m_fck,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_fck = {
+        .name           = "hdq_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_12m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* DPLL3-derived clock */
+
+static const struct clksel_rate ssi_ssr_corex2_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 8, .val = 8, .flags = RATE_IN_343X },
+        { .div = 0 }
+};
+
+static const struct clksel ssi_ssr_clksel[] = {
+        { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
+        { .parent = NULL }
+};
+
+static struct clk ssi_ssr_fck_3430es1 = {
+        .name           = "ssi_ssr_fck",
+        .ops            = &clkops_omap2_dflt,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk ssi_ssr_fck_3430es2 = {
+        .name           = "ssi_ssr_fck",
+        .ops            = &clkops_omap3430es2_ssi_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk ssi_sst_fck_3430es1 = {
+        .name           = "ssi_sst_fck",
+        .ops            = &clkops_null,
+        .parent         = &ssi_ssr_fck_3430es1,
+        .fixed_div      = 2,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+static struct clk ssi_sst_fck_3430es2 = {
+        .name           = "ssi_sst_fck",
+        .ops            = &clkops_null,
+        .parent         = &ssi_ssr_fck_3430es2,
+        .fixed_div      = 2,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+
+
+/* CORE_L3_ICK based clocks */
+
+/*
+ * XXX must add clk_enable/clk_disable for these if standard code won't
+ * handle it
+ */
+static struct clk core_l3_ick = {
+        .name           = "core_l3_ick",
+        .ops            = &clkops_null,
+        .parent         = &l3_ick,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick_3430es1 = {
+        .name           = "hsotgusb_ick",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick_3430es2 = {
+        .name           = "hsotgusb_ick",
+        .ops            = &clkops_omap3430es2_hsotgusb_wait,
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpmc_fck = {
+        .name           = "gpmc_fck",
+        .ops            = &clkops_null,
+        .parent         = &core_l3_ick,
+        .flags          = ENABLE_ON_INIT, /* huh? */
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* SECURITY_L3_ICK based clocks */
+
+static struct clk security_l3_ick = {
+        .name           = "security_l3_ick",
+        .ops            = &clkops_null,
+        .parent         = &l3_ick,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk pka_ick = {
+        .name           = "pka_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &security_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_PKA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* CORE_L4_ICK based clocks */
+
+static struct clk core_l4_ick = {
+        .name           = "core_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbtll_ick = {
+        .name           = "usbtll_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs3_ick = {
+        .name           = "mmchs_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* Intersystem Communication Registers - chassis mode only */
+static struct clk icr_ick = {
+        .name           = "icr_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_ICR_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes2_ick = {
+        .name           = "aes2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_AES2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha12_ick = {
+        .name           = "sha12_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des2_ick = {
+        .name           = "des2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_DES2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs2_ick = {
+        .name           = "mmchs_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmchs1_ick = {
+        .name           = "mmchs_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mspro_ick = {
+        .name           = "mspro_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hdq_ick = {
+        .name           = "hdq_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi4_ick = {
+        .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 4,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_ick = {
+        .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_ick = {
+        .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi1_ick = {
+        .name           = "mcspi_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c3_ick = {
+        .name           = "i2c_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 3,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_ick = {
+        .name           = "i2c_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c1_ick = {
+        .name           = "i2c_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_ick = {
+        .name           = "uart2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART2_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_ick = {
+        .name           = "uart1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_UART1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt11_ick = {
+        .name           = "gpt11_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt10_ick = {
+        .name           = "gpt10_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp5_ick = {
+        .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 5,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp1_ick = {
+        .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 1,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk fac_ick = {
+        .name           = "fac_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mailboxes_ick = {
+        .name           = "mailboxes_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk omapctrl_ick = {
+        .name           = "omapctrl_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
+        .flags          = ENABLE_ON_INIT,
+        .recalc         = &followparent_recalc,
+};
+
+/* SSI_L4_ICK based clocks */
+
+static struct clk ssi_l4_ick = {
+        .name           = "ssi_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ssi_ick_3430es1 = {
+        .name           = "ssi_ick",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &ssi_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ssi_ick_3430es2 = {
+        .name           = "ssi_ick",
+        .ops            = &clkops_omap3430es2_ssi_wait,
+        .parent         = &ssi_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
+ * but l4_ick makes more sense to me */
+
+static const struct clksel usb_l4_clksel[] = {
+        { .parent = &l4_ick, .rates = div2_rates },
+        { .parent = NULL },
+};
+
+static struct clk usb_l4_ick = {
+        .name           = "usb_l4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
+        .clksel         = usb_l4_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* SECURITY_L4_ICK2 based clocks */
+
+static struct clk security_l4_ick2 = {
+        .name           = "security_l4_ick2",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes1_ick = {
+        .name           = "aes1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_AES1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk rng_ick = {
+        .name           = "rng_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_RNG_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha11_ick = {
+        .name           = "sha11_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des1_ick = {
+        .name           = "des1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &security_l4_ick2,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
+        .enable_bit     = OMAP3430_EN_DES1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* DSS */
+static struct clk dss1_alwon_fck_3430es1 = {
+        .name           = "dss1_alwon_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &dpll4_m4x2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss1_alwon_fck_3430es2 = {
+        .name           = "dss1_alwon_fck",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &dpll4_m4x2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_tv_fck = {
+        .name           = "dss_tv_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &omap_54m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_96m_fck = {
+        .name           = "dss_96m_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &omap_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_TV_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss2_alwon_fck = {
+        .name           = "dss2_alwon_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_ick_3430es1 = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "dss_ick",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dss_ick_3430es2 = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "dss_ick",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* CAM */
+
+static struct clk cam_mclk = {
+        .name           = "cam_mclk",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &dpll4_m5x2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .clkdm_name     = "cam_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cam_ick = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "cam_ick",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_CAM_SHIFT,
+        .clkdm_name     = "cam_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk csi2_96m_fck = {
+        .name           = "csi2_96m_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &core_96m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
+        .clkdm_name     = "cam_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* USBHOST - 3430ES2 only */
+
+static struct clk usbhost_120m_fck = {
+        .name           = "usbhost_120m_fck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &dpll5_m2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
+        .clkdm_name     = "usbhost_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_48m_fck = {
+        .name           = "usbhost_48m_fck",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &omap_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
+        .clkdm_name     = "usbhost_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbhost_ick = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "usbhost_ick",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
+        .clkdm_name     = "usbhost_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* WKUP */
+
+static const struct clksel_rate usim_96m_rates[] = {
+        { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 4,  .val = 4, .flags = RATE_IN_343X },
+        { .div = 8,  .val = 5, .flags = RATE_IN_343X },
+        { .div = 10, .val = 6, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel_rate usim_120m_rates[] = {
+        { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
+        { .div = 16, .val = 9,  .flags = RATE_IN_343X },
+        { .div = 20, .val = 10, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel usim_clksel[] = {
+        { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
+        { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
+        { .parent = &sys_ck,            .rates = div2_rates },
+        { .parent = NULL },
+};
+
+/* 3430ES2 only */
+static struct clk usim_fck = {
+        .name           = "usim_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
+        .clksel         = usim_clksel,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
+static struct clk gpt1_fck = {
+        .name           = "gpt1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk wkup_32k_fck = {
+        .name           = "wkup_32k_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_32k_fck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio1_dbck = {
+        .name           = "gpio1_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &wkup_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt2_fck = {
+        .name           = "wdt2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_32k_fck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wkup_l4_ick = {
+        .name           = "wkup_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* 3430ES2 only */
+/* Never specifically named in the TRM, so we have to infer a likely name */
+static struct clk usim_ick = {
+        .name           = "usim_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt2_ick = {
+        .name           = "wdt2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt1_ick = {
+        .name           = "wdt1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio1_ick = {
+        .name           = "gpio1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk omap_32ksync_ick = {
+        .name           = "omap_32ksync_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* XXX This clock no longer exists in 3430 TRM rev F */
+static struct clk gpt12_ick = {
+        .name           = "gpt12_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt1_ick = {
+        .name           = "gpt1_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &wkup_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+
+
+/* PER clock domain */
+
+static struct clk per_96m_fck = {
+        .name           = "per_96m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_96m_alwon_fck,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk per_48m_fck = {
+        .name           = "per_48m_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_48m_fck,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_fck = {
+        .name           = "uart3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_fck = {
+        .name           = "gpt2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt3_fck = {
+        .name           = "gpt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt4_fck = {
+        .name           = "gpt4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt5_fck = {
+        .name           = "gpt5_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt6_fck = {
+        .name           = "gpt6_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt7_fck = {
+        .name           = "gpt7_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt8_fck = {
+        .name           = "gpt8_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpt9_fck = {
+        .name           = "gpt9_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
+        .clksel         = omap343x_gpt_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk per_32k_alwon_fck = {
+        .name           = "per_32k_alwon_fck",
+        .ops            = &clkops_null,
+        .parent         = &omap_32k_fck,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio6_dbck = {
+        .name           = "gpio6_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_dbck = {
+        .name           = "gpio5_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio4_dbck = {
+        .name           = "gpio4_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_dbck = {
+        .name           = "gpio3_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_dbck = {
+        .name           = "gpio2_dbck",
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_fck = {
+        .name           = "wdt3_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_32k_alwon_fck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk per_l4_ick = {
+        .name           = "per_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &l4_ick,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio6_ick = {
+        .name           = "gpio6_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_ick = {
+        .name           = "gpio5_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio4_ick = {
+        .name           = "gpio4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_ick = {
+        .name           = "gpio3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_ick = {
+        .name           = "gpio2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_ick = {
+        .name           = "wdt3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_ick = {
+        .name           = "uart3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_UART3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt9_ick = {
+        .name           = "gpt9_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt8_ick = {
+        .name           = "gpt8_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt7_ick = {
+        .name           = "gpt7_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt6_ick = {
+        .name           = "gpt6_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt5_ick = {
+        .name           = "gpt5_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt4_ick = {
+        .name           = "gpt4_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt3_ick = {
+        .name           = "gpt3_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpt2_ick = {
+        .name           = "gpt2_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp2_ick = {
+        .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp3_ick = {
+        .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 3,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcbsp4_ick = {
+        .name           = "mcbsp_ick",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 4,
+        .parent         = &per_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel mcbsp_234_clksel[] = {
+        { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
+        { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
+        { .parent = NULL }
+};
+
+static struct clk mcbsp2_fck = {
+        .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 2,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
+        .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp3_fck = {
+        .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 3,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk mcbsp4_fck = {
+        .name           = "mcbsp_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .id             = 4,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
+        .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
+        .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
+        .clksel         = mcbsp_234_clksel,
+        .clkdm_name     = "per_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* EMU clocks */
+
+/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
+
+static const struct clksel_rate emu_src_sys_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_core_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_per_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel_rate emu_src_mpu_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 0 },
+};
+
+static const struct clksel emu_src_clksel[] = {
+        { .parent = &sys_ck,            .rates = emu_src_sys_rates },
+        { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
+        { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
+        { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
+        { .parent = NULL },
+};
+
+/*
+ * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
+ * to switch the source of some of the EMU clocks.
+ * XXX Are there CLKEN bits for these EMU clks?
+ */
+static struct clk emu_src_ck = {
+        .name           = "emu_src_ck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
+        .clksel         = emu_src_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate pclk_emu_rates[] = {
+        { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 6, .val = 6, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel pclk_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = pclk_emu_rates },
+        { .parent = NULL },
+};
+
+static struct clk pclk_fck = {
+        .name           = "pclk_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
+        .clksel         = pclk_emu_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate pclkx2_emu_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 3, .val = 3, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel pclkx2_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
+        { .parent = NULL },
+};
+
+static struct clk pclkx2_fck = {
+        .name           = "pclkx2_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
+        .clksel         = pclkx2_emu_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel atclk_emu_clksel[] = {
+        { .parent = &emu_src_ck, .rates = div2_rates },
+        { .parent = NULL },
+};
+
+static struct clk atclk_fck = {
+        .name           = "atclk_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
+        .clksel         = atclk_emu_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk traceclk_src_fck = {
+        .name           = "traceclk_src_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
+        .clksel         = emu_src_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate traceclk_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
+        { .div = 2, .val = 2, .flags = RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_343X },
+        { .div = 0 },
+};
+
+static const struct clksel traceclk_clksel[] = {
+        { .parent = &traceclk_src_fck, .rates = traceclk_rates },
+        { .parent = NULL },
+};
+
+static struct clk traceclk_fck = {
+        .name           = "traceclk_fck",
+        .ops            = &clkops_null,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
+        .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
+        .clksel         = traceclk_clksel,
+        .clkdm_name     = "emu_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* SR clocks */
+
+/* SmartReflex fclk (VDD1) */
+static struct clk sr1_fck = {
+        .name           = "sr1_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR1_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/* SmartReflex fclk (VDD2) */
+static struct clk sr2_fck = {
+        .name           = "sr2_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &sys_ck,
+        .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_SR2_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sr_l4_ick = {
+        .name           = "sr_l4_ick",
+        .ops            = &clkops_null, /* RMK: missing? */
+        .parent         = &l4_ick,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+/* SECURE_32K_FCK clocks */
+
+static struct clk gpt12_fck = {
+        .name           = "gpt12_fck",
+        .ops            = &clkops_null,
+        .parent         = &secure_32k_fck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt1_fck = {
+        .name           = "wdt1_fck",
+        .ops            = &clkops_null,
+        .parent         = &secure_32k_fck,
+        .recalc         = &followparent_recalc,
+};
+
+
+/*
+ * clkdev
+ */
+
+static struct omap_clk omap34xx_clks[] = {
+        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_343X),
+        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_343X),
+        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_343X),
+        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
+        CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
+        CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_343X),
+        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
+        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_343X),
+        CLK(NULL,       "sys_ck",       &sys_ck,        CK_343X),
+        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_343X),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_343X),
+        CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_343X),
+        CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_343X),
+        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_343X),
+        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
+        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
+        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
+        CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_343X),
+        CLK(NULL,       "core_ck",      &core_ck,       CK_343X),
+        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_343X),
+        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_343X),
+        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
+        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_343X),
+        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
+        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
+        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_343X),
+        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_343X),
+        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
+        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_343X),
+        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_343X),
+        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_343X),
+        CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_343X),
+        CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_343X),
+        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
+        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
+        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
+        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
+        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_343X),
+        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
+        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
+        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2),
+        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2),
+        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_343X),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_343X),
+        CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_343X),
+        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_343X),
+        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_343X),
+        CLK(NULL,       "arm_fck",      &arm_fck,       CK_343X),
+        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
+        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
+        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
+        CLK(NULL,       "l3_ick",       &l3_ick,        CK_343X),
+        CLK(NULL,       "l4_ick",       &l4_ick,        CK_343X),
+        CLK(NULL,       "rm_ick",       &rm_ick,        CK_343X),
+        CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
+        CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
+        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
+        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
+        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
+        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
+        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
+        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
+        CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
+        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
+        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
+        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),
+        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2),
+        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2),
+        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_343X),
+        CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2),
+        CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_343X),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
+        CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_343X),
+        CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_343X),
+        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_343X),
+        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_343X),
+        CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_343X),
+        CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_343X),
+        CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_343X),
+        CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_343X),
+        CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_343X),
+        CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_343X),
+        CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_343X),
+        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_343X),
+        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_343X),
+        CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
+        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
+        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
+        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
+        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
+        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
+        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_343X),
+        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2),
+        CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2),
+        CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
+        CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
+        CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
+        CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
+        CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_343X),
+        CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_343X),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
+        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_343X),
+        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_343X),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_343X),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_343X),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_343X),
+        CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_343X),
+        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_343X),
+        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_343X),
+        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_343X),
+        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_343X),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_343X),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_343X),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_343X),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_343X),
+        CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
+        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
+        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
+        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
+        CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
+        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
+        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
+        CLK("omapdss",  "tv_fck",       &dss_tv_fck,    CK_343X),
+        CLK("omapdss",  "video_fck",    &dss_96m_fck,   CK_343X),
+        CLK("omapdss",  "dss2_fck",     &dss2_alwon_fck, CK_343X),
+        CLK("omapdss",  "ick",          &dss_ick_3430es1,       CK_3430ES1),
+        CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2),
+        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
+        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
+        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
+        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
+        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2),
+        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_343X),
+        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_343X),
+        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_343X),
+        CLK("omap_wdt", "fck",          &wdt2_fck,      CK_343X),
+        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
+        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
+        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_343X),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_343X),
+        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_343X),
+        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_343X),
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_343X),
+        CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_343X),
+        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_343X),
+        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_343X),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_343X),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_343X),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_343X),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_343X),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_343X),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_343X),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_343X),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_343X),
+        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
+        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_343X),
+        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_343X),
+        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_343X),
+        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_343X),
+        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_343X),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_343X),
+        CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_343X),
+        CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_343X),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_343X),
+        CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_343X),
+        CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_343X),
+        CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_343X),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_343X),
+        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_343X),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_343X),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_343X),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_343X),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_343X),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_343X),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_343X),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_343X),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_343X),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_343X),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_343X),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_343X),
+        CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_343X),
+        CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_343X),
+        CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_343X),
+        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_343X),
+        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_343X),
+        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_343X),
+        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_343X),
+        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_343X),
+        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_343X),
+        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
+        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
+        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
+        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_343X),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_343X),
+        CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_343X),
+};
+
+
+int __init omap2_clk_init(void)
+{
+        /* struct prcm_config *prcm; */
+        struct omap_clk *c;
+        /* u32 clkrate; */
+        u32 cpu_clkflg;
+
+        if (cpu_is_omap34xx()) {
+                cpu_mask = RATE_IN_343X;
+                cpu_clkflg = CK_343X;
+
+                /*
+                 * Update this if there are further clock changes between ES2
+                 * and production parts
+                 */
+                if (omap_rev() == OMAP3430_REV_ES1_0) {
+                        /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
+                        cpu_clkflg |= CK_3430ES1;
+                } else {
+                        cpu_mask |= RATE_IN_3430ES2;
+                        cpu_clkflg |= CK_3430ES2;
+                }
+        }
+
+        clk_init(&omap2_clk_functions);
+
+        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
+                clk_preinit(c->lk.clk);
+
+        for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
+                        omap2_init_clk_clkdm(c->lk.clk);
+                }
+
+        /* REVISIT: Not yet ready for OMAP3 */
+#if 0
+        /* Check the MPU rate set by bootloader */
+        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
+        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+                if (!(prcm->flags & cpu_mask))
+                        continue;
+                if (prcm->xtal_speed != sys_ck.rate)
+                        continue;
+                if (prcm->dpll_speed <= clkrate)
+                        break;
+        }
+        curr_prcm_set = prcm;
+#endif
+
+        recalculate_root_clocks();
+
+        printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
+               "%ld.%01ld/%ld/%ld MHz\n",
+               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+               (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        /*
+         * Lock DPLL5 and put it in autoidle.
+         */
+        if (omap_rev() >= OMAP3430_REV_ES2_0)
+                omap3_clk_lock_dpll5();
+
+        /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
+        sdrc_ick_p = clk_get(NULL, "sdrc_ick");
+        arm_fck_p = clk_get(NULL, "arm_fck");
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clock44xx.c b/arch/arm/mach-omap2/clock44xx.c
new file mode 100644
index 000000000000..e370868a79a8
--- /dev/null
+++ b/arch/arm/mach-omap2/clock44xx.c
@@ -0,0 +1,33 @@
+/*
+ * OMAP4-specific clock framework functions
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ *
+ * Rajendra Nayak (rnayak@ti.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/errno.h>
+#include "clock.h"
+
+struct clk_functions omap2_clk_functions = {
+        .clk_enable             = omap2_clk_enable,
+        .clk_disable            = omap2_clk_disable,
+        .clk_round_rate         = omap2_clk_round_rate,
+        .clk_set_rate           = omap2_clk_set_rate,
+        .clk_set_parent         = omap2_clk_set_parent,
+        .clk_disable_unused     = omap2_clk_disable_unused,
+};
+
+const struct clkops clkops_noncore_dpll_ops = {
+        .enable         = &omap3_noncore_dpll_enable,
+        .disable        = &omap3_noncore_dpll_disable,
+};
+
+void omap2_clk_prepare_for_reboot(void)
+{
+        return;
+}
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h
new file mode 100644
index 000000000000..59b9ced4daa1
--- /dev/null
+++ b/arch/arm/mach-omap2/clock44xx.h
@@ -0,0 +1,15 @@
+/*
+ * OMAP4 clock function prototypes and macros
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
+
+#define OMAP4430_MAX_DPLL_MULT  2048
+#define OMAP4430_MAX_DPLL_DIV   128
+
+extern const struct clkops clkops_noncore_dpll_ops;
+
+#endif
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
new file mode 100644
index 000000000000..2210e227d78a
--- /dev/null
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -0,0 +1,2766 @@
+/*
+ * OMAP4 Clock data
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+
+#include <plat/control.h>
+#include <plat/clkdev_omap.h>
+
+#include "clock.h"
+#include "clock44xx.h"
+#include "cm.h"
+#include "cm-regbits-44xx.h"
+#include "prm.h"
+#include "prm-regbits-44xx.h"
+
+/* Root clocks */
+
+static struct clk extalt_clkin_ck = {
+        .name           = "extalt_clkin_ck",
+        .rate           = 59000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk pad_clks_ck = {
+        .name           = "pad_clks_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk pad_slimbus_core_clks_ck = {
+        .name           = "pad_slimbus_core_clks_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk secure_32k_clk_src_ck = {
+        .name           = "secure_32k_clk_src_ck",
+        .rate           = 32768,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk slimbus_clk = {
+        .name           = "slimbus_clk",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk sys_32k_ck = {
+        .name           = "sys_32k_ck",
+        .rate           = 32768,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk virt_12000000_ck = {
+        .name           = "virt_12000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 12000000,
+};
+
+static struct clk virt_13000000_ck = {
+        .name           = "virt_13000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 13000000,
+};
+
+static struct clk virt_16800000_ck = {
+        .name           = "virt_16800000_ck",
+        .ops            = &clkops_null,
+        .rate           = 16800000,
+};
+
+static struct clk virt_19200000_ck = {
+        .name           = "virt_19200000_ck",
+        .ops            = &clkops_null,
+        .rate           = 19200000,
+};
+
+static struct clk virt_26000000_ck = {
+        .name           = "virt_26000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 26000000,
+};
+
+static struct clk virt_27000000_ck = {
+        .name           = "virt_27000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 27000000,
+};
+
+static struct clk virt_38400000_ck = {
+        .name           = "virt_38400000_ck",
+        .ops            = &clkops_null,
+        .rate           = 38400000,
+};
+
+static const struct clksel_rate div_1_0_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_1_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_2_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_3_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_4_rates[] = {
+        { .div = 1, .val = 4, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_5_rates[] = {
+        { .div = 1, .val = 5, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_6_rates[] = {
+        { .div = 1, .val = 6, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel_rate div_1_7_rates[] = {
+        { .div = 1, .val = 7, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel sys_clkin_sel[] = {
+        { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
+        { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
+        { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
+        { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
+        { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
+        { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
+        { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
+        { .parent = NULL },
+};
+
+static struct clk sys_clkin_ck = {
+        .name           = "sys_clkin_ck",
+        .rate           = 38400000,
+        .clksel         = sys_clkin_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_SYS_CLKSEL,
+        .clksel_mask    = OMAP4430_SYS_CLKSEL_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk utmi_phy_clkout_ck = {
+        .name           = "utmi_phy_clkout_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk xclk60mhsp1_ck = {
+        .name           = "xclk60mhsp1_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk xclk60mhsp2_ck = {
+        .name           = "xclk60mhsp2_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+static struct clk xclk60motg_ck = {
+        .name           = "xclk60motg_ck",
+        .rate           = 60000000,
+        .ops            = &clkops_null,
+        .flags          = CLOCK_IN_OMAP4430 | ALWAYS_ENABLED,
+};
+
+/* Module clocks and DPLL outputs */
+
+static const struct clksel_rate div2_1to2_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel dpll_sys_ref_clk_div[] = {
+        { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_sys_ref_clk = {
+        .name           = "dpll_sys_ref_clk",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dpll_sys_ref_clk_div,
+        .clksel_reg     = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel abe_dpll_refclk_mux_sel[] = {
+        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk abe_dpll_refclk_mux_ck = {
+        .name           = "abe_dpll_refclk_mux_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .clksel         = abe_dpll_refclk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_ABE */
+static struct dpll_data dpll_abe_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &abe_dpll_refclk_mux_ck,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_abe_ck = {
+        .name           = "dpll_abe_ck",
+        .parent         = &abe_dpll_refclk_mux_ck,
+        .dpll_data      = &dpll_abe_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_abe_m2x2_ck = {
+        .name           = "dpll_abe_m2x2_ck",
+        .parent         = &dpll_abe_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk abe_24m_fclk = {
+        .name           = "abe_24m_fclk",
+        .parent         = &dpll_abe_m2x2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div3_1to4_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel abe_clk_div[] = {
+        { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
+static struct clk abe_clk = {
+        .name           = "abe_clk",
+        .parent         = &dpll_abe_m2x2_ck,
+        .clksel         = abe_clk_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .clksel_mask    = OMAP4430_CLKSEL_OPP_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel aess_fclk_div[] = {
+        { .parent = &abe_clk, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
+static struct clk aess_fclk = {
+        .name           = "aess_fclk",
+        .parent         = &abe_clk,
+        .clksel         = aess_fclk_div,
+        .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div31_1to31_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 3, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 5, .val = 4, .flags = RATE_IN_4430 },
+        { .div = 6, .val = 5, .flags = RATE_IN_4430 },
+        { .div = 7, .val = 6, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 7, .flags = RATE_IN_4430 },
+        { .div = 9, .val = 8, .flags = RATE_IN_4430 },
+        { .div = 10, .val = 9, .flags = RATE_IN_4430 },
+        { .div = 11, .val = 10, .flags = RATE_IN_4430 },
+        { .div = 12, .val = 11, .flags = RATE_IN_4430 },
+        { .div = 13, .val = 12, .flags = RATE_IN_4430 },
+        { .div = 14, .val = 13, .flags = RATE_IN_4430 },
+        { .div = 15, .val = 14, .flags = RATE_IN_4430 },
+        { .div = 16, .val = 15, .flags = RATE_IN_4430 },
+        { .div = 17, .val = 16, .flags = RATE_IN_4430 },
+        { .div = 18, .val = 17, .flags = RATE_IN_4430 },
+        { .div = 19, .val = 18, .flags = RATE_IN_4430 },
+        { .div = 20, .val = 19, .flags = RATE_IN_4430 },
+        { .div = 21, .val = 20, .flags = RATE_IN_4430 },
+        { .div = 22, .val = 21, .flags = RATE_IN_4430 },
+        { .div = 23, .val = 22, .flags = RATE_IN_4430 },
+        { .div = 24, .val = 23, .flags = RATE_IN_4430 },
+        { .div = 25, .val = 24, .flags = RATE_IN_4430 },
+        { .div = 26, .val = 25, .flags = RATE_IN_4430 },
+        { .div = 27, .val = 26, .flags = RATE_IN_4430 },
+        { .div = 28, .val = 27, .flags = RATE_IN_4430 },
+        { .div = 29, .val = 28, .flags = RATE_IN_4430 },
+        { .div = 30, .val = 29, .flags = RATE_IN_4430 },
+        { .div = 31, .val = 30, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel dpll_abe_m3_div[] = {
+        { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_abe_m3_ck = {
+        .name           = "dpll_abe_m3_ck",
+        .parent         = &dpll_abe_ck,
+        .clksel         = dpll_abe_m3_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel core_hsd_byp_clk_mux_sel[] = {
+        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk core_hsd_byp_clk_mux_ck = {
+        .name           = "core_hsd_byp_clk_mux_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .clksel         = core_hsd_byp_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_CORE,
+        .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_CORE */
+static struct dpll_data dpll_core_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
+        .clk_bypass     = &core_hsd_byp_clk_mux_ck,
+        .clk_ref        = &dpll_sys_ref_clk,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_core_ck = {
+        .name           = "dpll_core_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .dpll_data      = &dpll_core_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_dpll_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dpll_core_m6_div[] = {
+        { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_core_m6_ck = {
+        .name           = "dpll_core_m6_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dbgclk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk dbgclk_mux_ck = {
+        .name           = "dbgclk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_core_m2_ck = {
+        .name           = "dpll_core_m2_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk ddrphy_ck = {
+        .name           = "ddrphy_ck",
+        .parent         = &dpll_core_m2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_core_m5_ck = {
+        .name           = "dpll_core_m5_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel div_core_div[] = {
+        { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
+static struct clk div_core_ck = {
+        .name           = "div_core_ck",
+        .parent         = &dpll_core_m5_ck,
+        .clksel         = div_core_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
+        .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div4_1to8_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel div_iva_hs_clk_div[] = {
+        { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
+        { .parent = NULL },
+};
+
+static struct clk div_iva_hs_clk = {
+        .name           = "div_iva_hs_clk",
+        .parent         = &dpll_core_m5_ck,
+        .clksel         = div_iva_hs_clk_div,
+        .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
+        .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk div_mpu_hs_clk = {
+        .name           = "div_mpu_hs_clk",
+        .parent         = &dpll_core_m5_ck,
+        .clksel         = div_iva_hs_clk_div,
+        .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
+        .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_core_m4_ck = {
+        .name           = "dpll_core_m4_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dll_clk_div_ck = {
+        .name           = "dll_clk_div_ck",
+        .parent         = &dpll_core_m4_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_abe_m2_ck = {
+        .name           = "dpll_abe_m2_ck",
+        .parent         = &dpll_abe_ck,
+        .clksel         = dpll_abe_m3_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_core_m3_ck = {
+        .name           = "dpll_core_m3_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_core_m7_ck = {
+        .name           = "dpll_core_m7_ck",
+        .parent         = &dpll_core_ck,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
+        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk iva_hsd_byp_clk_mux_ck = {
+        .name           = "iva_hsd_byp_clk_mux_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_IVA */
+static struct dpll_data dpll_iva_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
+        .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
+        .clk_ref        = &dpll_sys_ref_clk,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_iva_ck = {
+        .name           = "dpll_iva_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .dpll_data      = &dpll_iva_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dpll_iva_m4_div[] = {
+        { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_iva_m4_ck = {
+        .name           = "dpll_iva_m4_ck",
+        .parent         = &dpll_iva_ck,
+        .clksel         = dpll_iva_m4_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_iva_m5_ck = {
+        .name           = "dpll_iva_m5_ck",
+        .parent         = &dpll_iva_ck,
+        .clksel         = dpll_iva_m4_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_MPU */
+static struct dpll_data dpll_mpu_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
+        .clk_bypass     = &div_mpu_hs_clk,
+        .clk_ref        = &dpll_sys_ref_clk,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_mpu_ck = {
+        .name           = "dpll_mpu_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .dpll_data      = &dpll_mpu_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dpll_mpu_m2_div[] = {
+        { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_mpu_m2_ck = {
+        .name           = "dpll_mpu_m2_ck",
+        .parent         = &dpll_mpu_ck,
+        .clksel         = dpll_mpu_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk per_hs_clk_div_ck = {
+        .name           = "per_hs_clk_div_ck",
+        .parent         = &dpll_abe_m3_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel per_hsd_byp_clk_mux_sel[] = {
+        { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
+        { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk per_hsd_byp_clk_mux_ck = {
+        .name           = "per_hsd_byp_clk_mux_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .clksel         = per_hsd_byp_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_PER,
+        .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_PER */
+static struct dpll_data dpll_per_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
+        .clk_bypass     = &per_hsd_byp_clk_mux_ck,
+        .clk_ref        = &dpll_sys_ref_clk,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_per_ck = {
+        .name           = "dpll_per_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .dpll_data      = &dpll_per_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dpll_per_m2_div[] = {
+        { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_per_m2_ck = {
+        .name           = "dpll_per_m2_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_per_m2x2_ck = {
+        .name           = "dpll_per_m2x2_ck",
+        .parent         = &dpll_per_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_per_m3_ck = {
+        .name           = "dpll_per_m3_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_per_m4_ck = {
+        .name           = "dpll_per_m4_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_per_m5_ck = {
+        .name           = "dpll_per_m5_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_per_m6_ck = {
+        .name           = "dpll_per_m6_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_per_m7_ck = {
+        .name           = "dpll_per_m7_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
+        .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_UNIPRO */
+static struct dpll_data dpll_unipro_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
+        .clk_bypass     = &dpll_sys_ref_clk,
+        .clk_ref        = &dpll_sys_ref_clk,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_unipro_ck = {
+        .name           = "dpll_unipro_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .dpll_data      = &dpll_unipro_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dpll_unipro_m2x2_div[] = {
+        { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_unipro_m2x2_ck = {
+        .name           = "dpll_unipro_m2x2_ck",
+        .parent         = &dpll_unipro_ck,
+        .clksel         = dpll_unipro_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk usb_hs_clk_div_ck = {
+        .name           = "usb_hs_clk_div_ck",
+        .parent         = &dpll_abe_m3_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* DPLL_USB */
+static struct dpll_data dpll_usb_dd = {
+        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
+        .clk_bypass     = &usb_hs_clk_div_ck,
+        .clk_ref        = &dpll_sys_ref_clk,
+        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
+        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
+        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
+        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
+        .enable_mask    = OMAP4430_DPLL_EN_MASK,
+        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
+        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .max_multiplier = OMAP4430_MAX_DPLL_MULT,
+        .max_divider    = OMAP4430_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+
+static struct clk dpll_usb_ck = {
+        .name           = "dpll_usb_ck",
+        .parent         = &dpll_sys_ref_clk,
+        .dpll_data      = &dpll_usb_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk dpll_usb_clkdcoldo_ck = {
+        .name           = "dpll_usb_clkdcoldo_ck",
+        .parent         = &dpll_usb_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel dpll_usb_m2_div[] = {
+        { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_usb_m2_ck = {
+        .name           = "dpll_usb_m2_ck",
+        .parent         = &dpll_usb_ck,
+        .clksel         = dpll_usb_m2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel ducati_clk_mux_sel[] = {
+        { .parent = &div_core_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk ducati_clk_mux_ck = {
+        .name           = "ducati_clk_mux_ck",
+        .parent         = &div_core_ck,
+        .clksel         = ducati_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk func_12m_fclk = {
+        .name           = "func_12m_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk func_24m_clk = {
+        .name           = "func_24m_clk",
+        .parent         = &dpll_per_m2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk func_24mc_fclk = {
+        .name           = "func_24mc_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div2_4to8_rates[] = {
+        { .div = 4, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel func_48m_fclk_div[] = {
+        { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
+        { .parent = NULL },
+};
+
+static struct clk func_48m_fclk = {
+        .name           = "func_48m_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .clksel         = func_48m_fclk_div,
+        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
+        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk func_48mc_fclk = {
+        .name           = "func_48mc_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div2_2to4_rates[] = {
+        { .div = 2, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel func_64m_fclk_div[] = {
+        { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
+        { .parent = NULL },
+};
+
+static struct clk func_64m_fclk = {
+        .name           = "func_64m_fclk",
+        .parent         = &dpll_per_m4_ck,
+        .clksel         = func_64m_fclk_div,
+        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
+        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel func_96m_fclk_div[] = {
+        { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
+        { .parent = NULL },
+};
+
+static struct clk func_96m_fclk = {
+        .name           = "func_96m_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .clksel         = func_96m_fclk_div,
+        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
+        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel hsmmc6_fclk_sel[] = {
+        { .parent = &func_64m_fclk, .rates = div_1_0_rates },
+        { .parent = &func_96m_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk hsmmc6_fclk = {
+        .name           = "hsmmc6_fclk",
+        .parent         = &func_64m_fclk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div2_1to8_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel init_60m_fclk_div[] = {
+        { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
+        { .parent = NULL },
+};
+
+static struct clk init_60m_fclk = {
+        .name           = "init_60m_fclk",
+        .parent         = &dpll_usb_m2_ck,
+        .clksel         = init_60m_fclk_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_USB_60MHZ,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel l3_div_div[] = {
+        { .parent = &div_core_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
+static struct clk l3_div_ck = {
+        .name           = "l3_div_ck",
+        .parent         = &div_core_ck,
+        .clksel         = l3_div_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
+        .clksel_mask    = OMAP4430_CLKSEL_L3_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel l4_div_div[] = {
+        { .parent = &l3_div_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
+static struct clk l4_div_ck = {
+        .name           = "l4_div_ck",
+        .parent         = &l3_div_ck,
+        .clksel         = l4_div_div,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
+        .clksel_mask    = OMAP4430_CLKSEL_L4_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk lp_clk_div_ck = {
+        .name           = "lp_clk_div_ck",
+        .parent         = &dpll_abe_m2x2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel l4_wkup_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk l4_wkup_clk_mux_ck = {
+        .name           = "l4_wkup_clk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = l4_wkup_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4_WKUP_CLKSEL,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel per_abe_nc_fclk_div[] = {
+        { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
+        { .parent = NULL },
+};
+
+static struct clk per_abe_nc_fclk = {
+        .name           = "per_abe_nc_fclk",
+        .parent         = &dpll_abe_m2_ck,
+        .clksel         = per_abe_nc_fclk_div,
+        .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
+        .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel mcasp2_fclk_sel[] = {
+        { .parent = &func_96m_fclk, .rates = div_1_0_rates },
+        { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk mcasp2_fclk = {
+        .name           = "mcasp2_fclk",
+        .parent         = &func_96m_fclk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk mcasp3_fclk = {
+        .name           = "mcasp3_fclk",
+        .parent         = &func_96m_fclk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk ocp_abe_iclk = {
+        .name           = "ocp_abe_iclk",
+        .parent         = &aess_fclk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk per_abe_24m_fclk = {
+        .name           = "per_abe_24m_fclk",
+        .parent         = &dpll_abe_m2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel pmd_stm_clock_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+static struct clk pmd_stm_clock_mux_ck = {
+        .name           = "pmd_stm_clock_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk pmd_trace_clk_mux_ck = {
+        .name           = "pmd_trace_clk_mux_ck",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static struct clk syc_clk_div_ck = {
+        .name           = "syc_clk_div_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dpll_sys_ref_clk_div,
+        .clksel_reg     = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
+        .clksel_mask    = OMAP4430_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/* Leaf clocks controlled by modules */
+
+static struct clk aes1_ck = {
+        .name           = "aes1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aes2_ck = {
+        .name           = "aes2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk aess_ck = {
+        .name           = "aess_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &aess_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cust_efuse_ck = {
+        .name           = "cust_efuse_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_cefuse_clkdm",
+        .parent         = &sys_clkin_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk des3des_ck = {
+        .name           = "des3des_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel dmic_sync_mux_sel[] = {
+        { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
+        { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
+        { .parent = &func_24m_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+static struct clk dmic_sync_mux_ck = {
+        .name           = "dmic_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel func_dmic_abe_gfclk_sel[] = {
+        { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+/* Merged func_dmic_abe_gfclk into dmic_ck */
+static struct clk dmic_ck = {
+        .name           = "dmic_ck",
+        .parent         = &dmic_sync_mux_ck,
+        .clksel         = func_dmic_abe_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+static struct clk dss_ck = {
+        .name           = "dss_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_dss_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ducati_ck = {
+        .name           = "ducati_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "ducati_clkdm",
+        .parent         = &ducati_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk emif1_ck = {
+        .name           = "emif1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_emif_clkdm",
+        .parent         = &ddrphy_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk emif2_ck = {
+        .name           = "emif2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_emif_clkdm",
+        .parent         = &ddrphy_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel fdif_fclk_div[] = {
+        { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
+/* Merged fdif_fclk into fdif_ck */
+static struct clk fdif_ck = {
+        .name           = "fdif_ck",
+        .parent         = &dpll_per_m4_ck,
+        .clksel         = fdif_fclk_div,
+        .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "iss_clkdm",
+};
+
+static const struct clksel per_sgx_fclk_div[] = {
+        { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
+static struct clk per_sgx_fclk = {
+        .name           = "per_sgx_fclk",
+        .parent         = &dpll_per_m2x2_ck,
+        .clksel         = per_sgx_fclk_div,
+        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PER_192M_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel sgx_clk_mux_sel[] = {
+        { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
+        { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+/* Merged sgx_clk_mux into gfx_ck */
+static struct clk gfx_ck = {
+        .name           = "gfx_ck",
+        .parent         = &dpll_core_m7_ck,
+        .clksel         = sgx_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SGX_FCLK_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_gfx_clkdm",
+};
+
+static struct clk gpio1_ck = {
+        .name           = "gpio1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_ck = {
+        .name           = "gpio2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_ck = {
+        .name           = "gpio3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio4_ck = {
+        .name           = "gpio4_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio5_ck = {
+        .name           = "gpio5_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio6_ck = {
+        .name           = "gpio6_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpmc_ck = {
+        .name           = "gpmc_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_2_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel dmt1_clk_mux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+/* Merged dmt1_clk_mux into gptimer1_ck */
+static struct clk gptimer1_ck = {
+        .name           = "gptimer1_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+
+/* Merged cm2_dm10_mux into gptimer10_ck */
+static struct clk gptimer10_ck = {
+        .name           = "gptimer10_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm11_mux into gptimer11_ck */
+static struct clk gptimer11_ck = {
+        .name           = "gptimer11_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm2_mux into gptimer2_ck */
+static struct clk gptimer2_ck = {
+        .name           = "gptimer2_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm3_mux into gptimer3_ck */
+static struct clk gptimer3_ck = {
+        .name           = "gptimer3_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+/* Merged cm2_dm4_mux into gptimer4_ck */
+static struct clk gptimer4_ck = {
+        .name           = "gptimer4_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+static const struct clksel timer5_sync_mux_sel[] = {
+        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
+        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+/* Merged timer5_sync_mux into gptimer5_ck */
+static struct clk gptimer5_ck = {
+        .name           = "gptimer5_ck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer6_sync_mux into gptimer6_ck */
+static struct clk gptimer6_ck = {
+        .name           = "gptimer6_ck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer7_sync_mux into gptimer7_ck */
+static struct clk gptimer7_ck = {
+        .name           = "gptimer7_ck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged timer8_sync_mux into gptimer8_ck */
+static struct clk gptimer8_ck = {
+        .name           = "gptimer8_ck",
+        .parent         = &syc_clk_div_ck,
+        .clksel         = timer5_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+/* Merged cm2_dm9_mux into gptimer9_ck */
+static struct clk gptimer9_ck = {
+        .name           = "gptimer9_ck",
+        .parent         = &sys_clkin_ck,
+        .clksel         = dmt1_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+static struct clk hdq1w_ck = {
+        .name           = "hdq1w_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_12m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+/* Merged hsi_fclk into hsi_ck */
+static struct clk hsi_ck = {
+        .name           = "hsi_ck",
+        .parent         = &dpll_per_m2x2_ck,
+        .clksel         = per_sgx_fclk_div,
+        .clksel_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_24_25_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+};
+
+static struct clk i2c1_ck = {
+        .name           = "i2c1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c2_ck = {
+        .name           = "i2c2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c3_ck = {
+        .name           = "i2c3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk i2c4_ck = {
+        .name           = "i2c4_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk iss_ck = {
+        .name           = "iss_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CAM_ISS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "iss_clkdm",
+        .parent         = &ducati_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ivahd_ck = {
+        .name           = "ivahd_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "ivahd_clkdm",
+        .parent         = &dpll_iva_m5_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk keyboard_ck = {
+        .name           = "keyboard_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk l3_instr_interconnect_ck = {
+        .name           = "l3_instr_interconnect_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_instr_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk l3_interconnect_3_ck = {
+        .name           = "l3_interconnect_3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_instr_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcasp_sync_mux_ck = {
+        .name           = "mcasp_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel func_mcasp_abe_gfclk_sel[] = {
+        { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+/* Merged func_mcasp_abe_gfclk into mcasp_ck */
+static struct clk mcasp_ck = {
+        .name           = "mcasp_ck",
+        .parent         = &mcasp_sync_mux_ck,
+        .clksel         = func_mcasp_abe_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+static struct clk mcbsp1_sync_mux_ck = {
+        .name           = "mcbsp1_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel func_mcbsp1_gfclk_sel[] = {
+        { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+/* Merged func_mcbsp1_gfclk into mcbsp1_ck */
+static struct clk mcbsp1_ck = {
+        .name           = "mcbsp1_ck",
+        .parent         = &mcbsp1_sync_mux_ck,
+        .clksel         = func_mcbsp1_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+static struct clk mcbsp2_sync_mux_ck = {
+        .name           = "mcbsp2_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel func_mcbsp2_gfclk_sel[] = {
+        { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+/* Merged func_mcbsp2_gfclk into mcbsp2_ck */
+static struct clk mcbsp2_ck = {
+        .name           = "mcbsp2_ck",
+        .parent         = &mcbsp2_sync_mux_ck,
+        .clksel         = func_mcbsp2_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+static struct clk mcbsp3_sync_mux_ck = {
+        .name           = "mcbsp3_sync_mux_ck",
+        .parent         = &abe_24m_fclk,
+        .clksel         = dmic_sync_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel func_mcbsp3_gfclk_sel[] = {
+        { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = &slimbus_clk, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+/* Merged func_mcbsp3_gfclk into mcbsp3_ck */
+static struct clk mcbsp3_ck = {
+        .name           = "mcbsp3_ck",
+        .parent         = &mcbsp3_sync_mux_ck,
+        .clksel         = func_mcbsp3_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+};
+
+static struct clk mcbsp4_sync_mux_ck = {
+        .name           = "mcbsp4_sync_mux_ck",
+        .parent         = &func_96m_fclk,
+        .clksel         = mcasp2_fclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel per_mcbsp4_gfclk_sel[] = {
+        { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
+        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+/* Merged per_mcbsp4_gfclk into mcbsp4_ck */
+static struct clk mcbsp4_ck = {
+        .name           = "mcbsp4_ck",
+        .parent         = &mcbsp4_sync_mux_ck,
+        .clksel         = per_mcbsp4_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+};
+
+static struct clk mcspi1_ck = {
+        .name           = "mcspi1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi2_ck = {
+        .name           = "mcspi2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi3_ck = {
+        .name           = "mcspi3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcspi4_ck = {
+        .name           = "mcspi4_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+/* Merged hsmmc1_fclk into mmc1_ck */
+static struct clk mmc1_ck = {
+        .name           = "mmc1_ck",
+        .parent         = &func_64m_fclk,
+        .clksel         = hsmmc6_fclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+};
+
+/* Merged hsmmc2_fclk into mmc2_ck */
+static struct clk mmc2_ck = {
+        .name           = "mmc2_ck",
+        .parent         = &func_64m_fclk,
+        .clksel         = hsmmc6_fclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_MASK,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+        .enable_reg     = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+};
+
+static struct clk mmc3_ck = {
+        .name           = "mmc3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmc4_ck = {
+        .name           = "mmc4_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmc5_ck = {
+        .name           = "mmc5_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ocp_wp1_ck = {
+        .name           = "ocp_wp1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_instr_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk pdm_ck = {
+        .name           = "pdm_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_PDM_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &pad_clks_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk pkaeip29_ck = {
+        .name           = "pkaeip29_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk rng_ck = {
+        .name           = "rng_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sha2md51_ck = {
+        .name           = "sha2md51_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_secure_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sl2_ck = {
+        .name           = "sl2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "ivahd_clkdm",
+        .parent         = &dpll_iva_m5_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus1_ck = {
+        .name           = "slimbus1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &ocp_abe_iclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk slimbus2_ck = {
+        .name           = "slimbus2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sr_core_ck = {
+        .name           = "sr_core_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sr_iva_ck = {
+        .name           = "sr_iva_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sr_mpu_ck = {
+        .name           = "sr_mpu_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_ao_clkdm",
+        .parent         = &l4_wkup_clk_mux_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk tesla_ck = {
+        .name           = "tesla_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "tesla_clkdm",
+        .parent         = &dpll_iva_m4_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart1_ck = {
+        .name           = "uart1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_UART1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart2_ck = {
+        .name           = "uart2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_UART2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart3_ck = {
+        .name           = "uart3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_UART3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk uart4_ck = {
+        .name           = "uart4_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L4PER_UART4_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_per_clkdm",
+        .parent         = &func_48m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk unipro1_ck = {
+        .name           = "unipro1_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &func_96m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_host_ck = {
+        .name           = "usb_host_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_host_fs_ck = {
+        .name           = "usb_host_fs_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &func_48mc_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_otg_ck = {
+        .name           = "usb_otg_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l3_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_tll_ck = {
+        .name           = "usb_tll_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usbphyocp2scp_ck = {
+        .name           = "usbphyocp2scp_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &l4_div_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usim_ck = {
+        .name           = "usim_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt2_ck = {
+        .name           = "wdt2_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk wdt3_ck = {
+        .name           = "wdt3_ck",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL,
+        .clkdm_name     = "abe_clkdm",
+        .parent         = &sys_32k_ck,
+        .recalc         = &followparent_recalc,
+};
+
+/* Remaining optional clocks */
+static const struct clksel otg_60m_gfclk_sel[] = {
+        { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
+        { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk otg_60m_gfclk_ck = {
+        .name           = "otg_60m_gfclk_ck",
+        .parent         = &utmi_phy_clkout_ck,
+        .clksel         = otg_60m_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_60M_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel stm_clk_div_div[] = {
+        { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
+static struct clk stm_clk_div_ck = {
+        .name           = "stm_clk_div_ck",
+        .parent         = &pmd_stm_clock_mux_ck,
+        .clksel         = stm_clk_div_div,
+        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel trace_clk_div_div[] = {
+        { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
+        { .parent = NULL },
+};
+
+static struct clk trace_clk_div_ck = {
+        .name           = "trace_clk_div_ck",
+        .parent         = &pmd_trace_clk_mux_ck,
+        .clksel         = trace_clk_div_div,
+        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel_rate div2_14to18_rates[] = {
+        { .div = 14, .val = 0, .flags = RATE_IN_4430 },
+        { .div = 18, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel usim_fclk_div[] = {
+        { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
+        { .parent = NULL },
+};
+
+static struct clk usim_fclk = {
+        .name           = "usim_fclk",
+        .parent         = &dpll_per_m4_ck,
+        .clksel         = usim_fclk_div,
+        .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel utmi_p1_gfclk_sel[] = {
+        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
+        { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk utmi_p1_gfclk_ck = {
+        .name           = "utmi_p1_gfclk_ck",
+        .parent         = &init_60m_fclk,
+        .clksel         = utmi_p1_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+static const struct clksel utmi_p2_gfclk_sel[] = {
+        { .parent = &init_60m_fclk, .rates = div_1_0_rates },
+        { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk utmi_p2_gfclk_ck = {
+        .name           = "utmi_p2_gfclk_ck",
+        .parent         = &init_60m_fclk,
+        .clksel         = utmi_p2_gfclk_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .clksel_mask    = OMAP4430_CLKSEL_UTMI_P2_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .flags          = CLOCK_IN_OMAP4430,
+};
+
+/*
+ * clkdev
+ */
+
+static struct omap_clk omap44xx_clks[] = {
+        CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
+        CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
+        CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
+        CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
+        CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
+        CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
+        CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
+        CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
+        CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
+        CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
+        CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
+        CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
+        CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
+        CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
+        CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
+        CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
+        CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
+        CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
+        CLK(NULL,       "dpll_sys_ref_clk",             &dpll_sys_ref_clk,      CK_443X),
+        CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
+        CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
+        CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
+        CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
+        CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
+        CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
+        CLK(NULL,       "dpll_abe_m3_ck",               &dpll_abe_m3_ck,        CK_443X),
+        CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
+        CLK(NULL,       "dpll_core_m6_ck",              &dpll_core_m6_ck,       CK_443X),
+        CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
+        CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
+        CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
+        CLK(NULL,       "dpll_core_m5_ck",              &dpll_core_m5_ck,       CK_443X),
+        CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
+        CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
+        CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
+        CLK(NULL,       "dpll_core_m4_ck",              &dpll_core_m4_ck,       CK_443X),
+        CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
+        CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
+        CLK(NULL,       "dpll_core_m3_ck",              &dpll_core_m3_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_m7_ck",              &dpll_core_m7_ck,       CK_443X),
+        CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
+        CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
+        CLK(NULL,       "dpll_iva_m4_ck",               &dpll_iva_m4_ck,        CK_443X),
+        CLK(NULL,       "dpll_iva_m5_ck",               &dpll_iva_m5_ck,        CK_443X),
+        CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
+        CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
+        CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
+        CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
+        CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m3_ck",               &dpll_per_m3_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m4_ck",               &dpll_per_m4_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m5_ck",               &dpll_per_m5_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m6_ck",               &dpll_per_m6_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m7_ck",               &dpll_per_m7_ck,        CK_443X),
+        CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
+        CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
+        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
+        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
+        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
+        CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
+        CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
+        CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
+        CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
+        CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
+        CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
+        CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
+        CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
+        CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
+        CLK(NULL,       "hsmmc6_fclk",                  &hsmmc6_fclk,   CK_443X),
+        CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
+        CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
+        CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
+        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
+        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
+        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
+        CLK(NULL,       "mcasp2_fclk",                  &mcasp2_fclk,   CK_443X),
+        CLK(NULL,       "mcasp3_fclk",                  &mcasp3_fclk,   CK_443X),
+        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
+        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
+        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
+        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
+        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
+        CLK(NULL,       "aes1_ck",                      &aes1_ck,       CK_443X),
+        CLK(NULL,       "aes2_ck",                      &aes2_ck,       CK_443X),
+        CLK(NULL,       "aess_ck",                      &aess_ck,       CK_443X),
+        CLK(NULL,       "cust_efuse_ck",                &cust_efuse_ck, CK_443X),
+        CLK(NULL,       "des3des_ck",                   &des3des_ck,    CK_443X),
+        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
+        CLK(NULL,       "dmic_ck",                      &dmic_ck,       CK_443X),
+        CLK(NULL,       "dss_ck",                       &dss_ck,        CK_443X),
+        CLK(NULL,       "ducati_ck",                    &ducati_ck,     CK_443X),
+        CLK(NULL,       "emif1_ck",                     &emif1_ck,      CK_443X),
+        CLK(NULL,       "emif2_ck",                     &emif2_ck,      CK_443X),
+        CLK(NULL,       "fdif_ck",                      &fdif_ck,       CK_443X),
+        CLK(NULL,       "per_sgx_fclk",                 &per_sgx_fclk,  CK_443X),
+        CLK(NULL,       "gfx_ck",                       &gfx_ck,        CK_443X),
+        CLK(NULL,       "gpio1_ck",                     &gpio1_ck,      CK_443X),
+        CLK(NULL,       "gpio2_ck",                     &gpio2_ck,      CK_443X),
+        CLK(NULL,       "gpio3_ck",                     &gpio3_ck,      CK_443X),
+        CLK(NULL,       "gpio4_ck",                     &gpio4_ck,      CK_443X),
+        CLK(NULL,       "gpio5_ck",                     &gpio5_ck,      CK_443X),
+        CLK(NULL,       "gpio6_ck",                     &gpio6_ck,      CK_443X),
+        CLK(NULL,       "gpmc_ck",                      &gpmc_ck,       CK_443X),
+        CLK(NULL,       "gptimer1_ck",                  &gptimer1_ck,   CK_443X),
+        CLK(NULL,       "gptimer10_ck",                 &gptimer10_ck,  CK_443X),
+        CLK(NULL,       "gptimer11_ck",                 &gptimer11_ck,  CK_443X),
+        CLK(NULL,       "gptimer2_ck",                  &gptimer2_ck,   CK_443X),
+        CLK(NULL,       "gptimer3_ck",                  &gptimer3_ck,   CK_443X),
+        CLK(NULL,       "gptimer4_ck",                  &gptimer4_ck,   CK_443X),
+        CLK(NULL,       "gptimer5_ck",                  &gptimer5_ck,   CK_443X),
+        CLK(NULL,       "gptimer6_ck",                  &gptimer6_ck,   CK_443X),
+        CLK(NULL,       "gptimer7_ck",                  &gptimer7_ck,   CK_443X),
+        CLK(NULL,       "gptimer8_ck",                  &gptimer8_ck,   CK_443X),
+        CLK(NULL,       "gptimer9_ck",                  &gptimer9_ck,   CK_443X),
+        CLK("omap2_hdq.0",      "ick",                          &hdq1w_ck,      CK_443X),
+        CLK(NULL,       "hsi_ck",                       &hsi_ck,        CK_443X),
+        CLK("i2c_omap.1",       "ick",                          &i2c1_ck,       CK_443X),
+        CLK("i2c_omap.2",       "ick",                          &i2c2_ck,       CK_443X),
+        CLK("i2c_omap.3",       "ick",                          &i2c3_ck,       CK_443X),
+        CLK("i2c_omap.4",       "ick",                          &i2c4_ck,       CK_443X),
+        CLK(NULL,       "iss_ck",                       &iss_ck,        CK_443X),
+        CLK(NULL,       "ivahd_ck",                     &ivahd_ck,      CK_443X),
+        CLK(NULL,       "keyboard_ck",                  &keyboard_ck,   CK_443X),
+        CLK(NULL,       "l3_instr_interconnect_ck",     &l3_instr_interconnect_ck,      CK_443X),
+        CLK(NULL,       "l3_interconnect_3_ck",         &l3_interconnect_3_ck,  CK_443X),
+        CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
+        CLK(NULL,       "mcasp_ck",                     &mcasp_ck,      CK_443X),
+        CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
+        CLK("omap-mcbsp.1",     "fck",                          &mcbsp1_ck,     CK_443X),
+        CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
+        CLK("omap-mcbsp.2",     "fck",                          &mcbsp2_ck,     CK_443X),
+        CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
+        CLK("omap-mcbsp.3",     "fck",                          &mcbsp3_ck,     CK_443X),
+        CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
+        CLK("omap-mcbsp.4",     "fck",                          &mcbsp4_ck,     CK_443X),
+        CLK("omap2_mcspi.1",    "fck",                          &mcspi1_ck,     CK_443X),
+        CLK("omap2_mcspi.2",    "fck",                          &mcspi2_ck,     CK_443X),
+        CLK("omap2_mcspi.3",    "fck",                          &mcspi3_ck,     CK_443X),
+        CLK("omap2_mcspi.4",    "fck",                          &mcspi4_ck,     CK_443X),
+        CLK("mmci-omap-hs.0",   "fck",                          &mmc1_ck,       CK_443X),
+        CLK("mmci-omap-hs.1",   "fck",                          &mmc2_ck,       CK_443X),
+        CLK("mmci-omap-hs.2",   "fck",                          &mmc3_ck,       CK_443X),
+        CLK("mmci-omap-hs.3",   "fck",                          &mmc4_ck,       CK_443X),
+        CLK("mmci-omap-hs.4",   "fck",                          &mmc5_ck,       CK_443X),
+        CLK(NULL,       "ocp_wp1_ck",                   &ocp_wp1_ck,    CK_443X),
+        CLK(NULL,       "pdm_ck",                       &pdm_ck,        CK_443X),
+        CLK(NULL,       "pkaeip29_ck",                  &pkaeip29_ck,   CK_443X),
+        CLK("omap_rng", "ick",                          &rng_ck,        CK_443X),
+        CLK(NULL,       "sha2md51_ck",                  &sha2md51_ck,   CK_443X),
+        CLK(NULL,       "sl2_ck",                       &sl2_ck,        CK_443X),
+        CLK(NULL,       "slimbus1_ck",                  &slimbus1_ck,   CK_443X),
+        CLK(NULL,       "slimbus2_ck",                  &slimbus2_ck,   CK_443X),
+        CLK(NULL,       "sr_core_ck",                   &sr_core_ck,    CK_443X),
+        CLK(NULL,       "sr_iva_ck",                    &sr_iva_ck,     CK_443X),
+        CLK(NULL,       "sr_mpu_ck",                    &sr_mpu_ck,     CK_443X),
+        CLK(NULL,       "tesla_ck",                     &tesla_ck,      CK_443X),
+        CLK(NULL,       "uart1_ck",                     &uart1_ck,      CK_443X),
+        CLK(NULL,       "uart2_ck",                     &uart2_ck,      CK_443X),
+        CLK(NULL,       "uart3_ck",                     &uart3_ck,      CK_443X),
+        CLK(NULL,       "uart4_ck",                     &uart4_ck,      CK_443X),
+        CLK(NULL,       "unipro1_ck",                   &unipro1_ck,    CK_443X),
+        CLK(NULL,       "usb_host_ck",                  &usb_host_ck,   CK_443X),
+        CLK(NULL,       "usb_host_fs_ck",               &usb_host_fs_ck,        CK_443X),
+        CLK("musb_hdrc",        "ick",                          &usb_otg_ck,    CK_443X),
+        CLK(NULL,       "usb_tll_ck",                   &usb_tll_ck,    CK_443X),
+        CLK(NULL,       "usbphyocp2scp_ck",             &usbphyocp2scp_ck,      CK_443X),
+        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
+        CLK("omap_wdt", "fck",                          &wdt2_ck,       CK_443X),
+        CLK(NULL,       "wdt3_ck",                      &wdt3_ck,       CK_443X),
+        CLK(NULL,       "otg_60m_gfclk_ck",             &otg_60m_gfclk_ck,      CK_443X),
+        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
+        CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
+        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
+        CLK(NULL,       "utmi_p1_gfclk_ck",             &utmi_p1_gfclk_ck,      CK_443X),
+        CLK(NULL,       "utmi_p2_gfclk_ck",             &utmi_p2_gfclk_ck,      CK_443X),
+};
+
+int __init omap2_clk_init(void)
+{
+        /* struct prcm_config *prcm; */
+        struct omap_clk *c;
+        /* u32 clkrate; */
+        u32 cpu_clkflg;
+
+        if (cpu_is_omap44xx()) {
+                cpu_mask = RATE_IN_4430;
+                cpu_clkflg = CK_443X;
+        }
+
+        clk_init(&omap2_clk_functions);
+
+        for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
+                                                                          c++)
+                clk_preinit(c->lk.clk);
+
+        for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
+                                                                          c++)
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
+                        /* TODO
+                        omap2_init_clk_clkdm(c->lk.clk);
+                        */
+                }
+
+        recalculate_root_clocks();
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
new file mode 100644
index 000000000000..f69096b88cdb
--- /dev/null
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -0,0 +1,39 @@
+/*
+ *  linux/arch/arm/mach-omap2/clock_common_data.c
+ *
+ *  Copyright (C) 2005-2009 Texas Instruments, Inc.
+ *  Copyright (C) 2004-2009 Nokia Corporation
+ *
+ *  Contacts:
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *  Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains clock data that is common to both the OMAP2xxx and
+ * OMAP3xxx clock definition files.
+ */
+
+#include "clock.h"
+
+/* clksel_rate data common to 24xx/343x */
+const struct clksel_rate gpt_32k_rates[] = {
+         { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+         { .div = 0 }
+};
+
+const struct clksel_rate gpt_sys_rates[] = {
+         { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+         { .div = 0 }
+};
+
+const struct clksel_rate gfx_l3_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
+        { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
+        { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
+        { .div = 0 }
+};
+
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index fcd82320a6a3..1a45ed1e8ba1 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -2,7 +2,7 @@
  * OMAP2/3 clockdomain framework functions
  *
  * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2008-2009 Nokia Corporation
  *
  * Written by Paul Walmsley and Jouni Högander
  *
@@ -10,9 +10,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#ifdef CONFIG_OMAP_DEBUG_CLOCKDOMAIN
-#  define DEBUG
-#endif
+#undef DEBUG
 
 #include <linux/module.h>
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
new file mode 100644
index 000000000000..0e67f75aa35c
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -0,0 +1,1474 @@
+/*
+ * OMAP44xx Clock Management register bits
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
+
+#include "cm.h"
+
+
+/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+#define OMAP4430_ABE_DYNDEP_SHIFT                               (1 << 3)
+#define OMAP4430_ABE_DYNDEP_MASK                                BITFIELD(3, 3)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
+ * CM_TESLA_STATICDEP
+ */
+#define OMAP4430_ABE_STATDEP_SHIFT                              (1 << 3)
+#define OMAP4430_ABE_STATDEP_MASK                               BITFIELD(3, 3)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         (1 << 16)
+#define OMAP4430_ALWONCORE_DYNDEP_MASK                          BITFIELD(16, 16)
+
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
+#define OMAP4430_ALWONCORE_STATDEP_SHIFT                        (1 << 16)
+#define OMAP4430_ALWONCORE_STATDEP_MASK                         BITFIELD(16, 16)
+
+/*
+ * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB,
+ * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
+ * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU
+ */
+#define OMAP4430_AUTO_DPLL_MODE_SHIFT                           (1 << 0)
+#define OMAP4430_AUTO_DPLL_MODE_MASK                            BITFIELD(0, 2)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_CEFUSE_DYNDEP_SHIFT                            (1 << 17)
+#define OMAP4430_CEFUSE_DYNDEP_MASK                             BITFIELD(17, 17)
+
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
+#define OMAP4430_CEFUSE_STATDEP_SHIFT                           (1 << 17)
+#define OMAP4430_CEFUSE_STATDEP_MASK                            BITFIELD(17, 17)
+
+/* Used by CM1_ABE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                (1 << 13)
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 BITFIELD(13, 13)
+
+/* Used by CM1_ABE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            (1 << 12)
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             BITFIELD(12, 12)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   (1 << 9)
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    BITFIELD(9, 9)
+
+/* Used by CM1_ABE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   (1 << 11)
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    BITFIELD(11, 11)
+
+/* Used by CM1_ABE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   (1 << 8)
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    BITFIELD(8, 8)
+
+/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                (1 << 11)
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 BITFIELD(11, 11)
+
+/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               (1 << 12)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                BITFIELD(12, 12)
+
+/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               (1 << 13)
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                BITFIELD(13, 13)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            (1 << 9)
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             BITFIELD(9, 9)
+
+/* Used by CM_EMU_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            (1 << 9)
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             BITFIELD(9, 9)
+
+/* Used by CM_CEFUSE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           (1 << 9)
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            BITFIELD(9, 9)
+
+/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      (1 << 9)
+#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       BITFIELD(9, 9)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  (1 << 9)
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   BITFIELD(9, 9)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  (1 << 10)
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   BITFIELD(10, 10)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   (1 << 11)
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    BITFIELD(11, 11)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   (1 << 12)
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    BITFIELD(12, 12)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   (1 << 13)
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    BITFIELD(13, 13)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   (1 << 14)
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    BITFIELD(14, 14)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            (1 << 10)
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             BITFIELD(10, 10)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     (1 << 9)
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      BITFIELD(9, 9)
+
+/* Used by CM_DUCATI_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  (1 << 8)
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT               (1 << 10)
+#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK                BITFIELD(10, 10)
+
+/* Used by CM_EMU_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  (1 << 8)
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   BITFIELD(8, 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   (1 << 10)
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    BITFIELD(10, 10)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               (1 << 15)
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                BITFIELD(15, 15)
+
+/* Used by CM1_ABE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               (1 << 10)
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                BITFIELD(10, 10)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         (1 << 11)
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          BITFIELD(11, 11)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           (1 << 20)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            BITFIELD(20, 20)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                (1 << 26)
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 BITFIELD(26, 26)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           (1 << 21)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            BITFIELD(21, 21)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                (1 << 27)
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 BITFIELD(27, 27)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT               (1 << 31)
+#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK                BITFIELD(31, 31)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              (1 << 13)
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               BITFIELD(13, 13)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               (1 << 12)
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                BITFIELD(12, 12)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            (1 << 28)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             BITFIELD(28, 28)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            (1 << 29)
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             BITFIELD(29, 29)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               (1 << 11)
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                BITFIELD(11, 11)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               (1 << 16)
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                BITFIELD(16, 16)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            (1 << 17)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             BITFIELD(17, 17)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            (1 << 18)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             BITFIELD(18, 18)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            (1 << 19)
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             BITFIELD(19, 19)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     (1 << 8)
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      BITFIELD(8, 8)
+
+/* Used by CM_IVAHD_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               (1 << 8)
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT        (1 << 14)
+#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK         BITFIELD(14, 14)
+
+/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    BITFIELD(8, 8)
+
+/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    BITFIELD(8, 8)
+
+/* Used by CM_D2D_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_SDMA_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 BITFIELD(8, 8)
+
+/* Used by CM_GFX_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 BITFIELD(8, 8)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                BITFIELD(8, 8)
+
+/* Used by CM_L4SEC_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              (1 << 8)
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               BITFIELD(8, 8)
+
+/* Used by CM_ALWON_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    BITFIELD(8, 8)
+
+/* Used by CM_CEFUSE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               BITFIELD(8, 8)
+
+/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_D2D_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 (1 << 9)
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  BITFIELD(9, 9)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                (1 << 9)
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 BITFIELD(9, 9)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_L4SEC_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              (1 << 9)
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               BITFIELD(9, 9)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                (1 << 12)
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 BITFIELD(12, 12)
+
+/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 (1 << 8)
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  BITFIELD(8, 8)
+
+/* Used by CM1_ABE_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                (1 << 9)
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 BITFIELD(9, 9)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               (1 << 16)
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                BITFIELD(16, 16)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                (1 << 17)
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 BITFIELD(17, 17)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                (1 << 18)
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 BITFIELD(18, 18)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                (1 << 19)
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 BITFIELD(19, 19)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            (1 << 25)
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             BITFIELD(25, 25)
+
+/* Used by CM_EMU_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT             (1 << 10)
+#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK              BITFIELD(10, 10)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             (1 << 20)
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              BITFIELD(20, 20)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT             (1 << 21)
+#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK              BITFIELD(21, 21)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             (1 << 22)
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              BITFIELD(22, 22)
+
+/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                (1 << 24)
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 BITFIELD(24, 24)
+
+/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 (1 << 10)
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  BITFIELD(10, 10)
+
+/* Used by CM_GFX_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    (1 << 9)
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     BITFIELD(9, 9)
+
+/* Used by CM_ALWON_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               (1 << 11)
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                BITFIELD(11, 11)
+
+/* Used by CM_ALWON_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                (1 << 10)
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 BITFIELD(10, 10)
+
+/* Used by CM_ALWON_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                (1 << 9)
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 BITFIELD(9, 9)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      (1 << 8)
+#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       BITFIELD(8, 8)
+
+/* Used by CM_TESLA_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               (1 << 8)
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                (1 << 22)
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 BITFIELD(22, 22)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                (1 << 23)
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 BITFIELD(23, 23)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                (1 << 24)
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 BITFIELD(24, 24)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              (1 << 15)
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               BITFIELD(15, 15)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   (1 << 10)
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    BITFIELD(10, 10)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                (1 << 30)
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 BITFIELD(30, 30)
+
+/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              (1 << 25)
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               BITFIELD(25, 25)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               (1 << 11)
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                BITFIELD(11, 11)
+
+/*
+ * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
+ * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
+ * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
+ * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL,
+ * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL
+ */
+#define OMAP4430_CLKSEL_SHIFT                                   (1 << 24)
+#define OMAP4430_CLKSEL_MASK                                    BITFIELD(24, 24)
+
+/*
+ * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
+ * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT,
+ * CM_CLKSEL_USB_60MHZ
+ */
+#define OMAP4430_CLKSEL_0_0_SHIFT                               (1 << 0)
+#define OMAP4430_CLKSEL_0_0_MASK                                BITFIELD(0, 0)
+
+/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
+#define OMAP4430_CLKSEL_0_1_SHIFT                               (1 << 0)
+#define OMAP4430_CLKSEL_0_1_MASK                                BITFIELD(0, 1)
+
+/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
+#define OMAP4430_CLKSEL_24_25_SHIFT                             (1 << 24)
+#define OMAP4430_CLKSEL_24_25_MASK                              BITFIELD(24, 25)
+
+/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
+#define OMAP4430_CLKSEL_60M_SHIFT                               (1 << 24)
+#define OMAP4430_CLKSEL_60M_MASK                                BITFIELD(24, 24)
+
+/* Used by CM1_ABE_AESS_CLKCTRL */
+#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         (1 << 24)
+#define OMAP4430_CLKSEL_AESS_FCLK_MASK                          BITFIELD(24, 24)
+
+/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+#define OMAP4430_CLKSEL_CORE_SHIFT                              (1 << 0)
+#define OMAP4430_CLKSEL_CORE_MASK                               BITFIELD(0, 0)
+
+/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          (1 << 1)
+#define OMAP4430_CLKSEL_CORE_1_1_MASK                           BITFIELD(1, 1)
+
+/* Used by CM_WKUP_USIM_CLKCTRL */
+#define OMAP4430_CLKSEL_DIV_SHIFT                               (1 << 24)
+#define OMAP4430_CLKSEL_DIV_MASK                                BITFIELD(24, 24)
+
+/* Used by CM_CAM_FDIF_CLKCTRL */
+#define OMAP4430_CLKSEL_FCLK_SHIFT                              (1 << 24)
+#define OMAP4430_CLKSEL_FCLK_MASK                               BITFIELD(24, 25)
+
+/* Used by CM_L4PER_MCBSP4_CLKCTRL */
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   (1 << 25)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    BITFIELD(25, 25)
+
+/*
+ * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
+ * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
+ * CM1_ABE_MCBSP3_CLKCTRL
+ */
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      (1 << 26)
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       BITFIELD(26, 27)
+
+/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+#define OMAP4430_CLKSEL_L3_SHIFT                                (1 << 4)
+#define OMAP4430_CLKSEL_L3_MASK                                 BITFIELD(4, 4)
+
+/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         (1 << 2)
+#define OMAP4430_CLKSEL_L3_SHADOW_MASK                          BITFIELD(2, 2)
+
+/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */
+#define OMAP4430_CLKSEL_L4_SHIFT                                (1 << 8)
+#define OMAP4430_CLKSEL_L4_MASK                                 BITFIELD(8, 8)
+
+/* Used by CM_CLKSEL_ABE */
+#define OMAP4430_CLKSEL_OPP_SHIFT                               (1 << 0)
+#define OMAP4430_CLKSEL_OPP_MASK                                BITFIELD(0, 1)
+
+/* Used by CM_GFX_GFX_CLKCTRL */
+#define OMAP4430_CLKSEL_PER_192M_SHIFT                          (1 << 25)
+#define OMAP4430_CLKSEL_PER_192M_MASK                           BITFIELD(25, 26)
+
+/* Used by CM_EMU_DEBUGSS_CLKCTRL */
+#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       (1 << 27)
+#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        BITFIELD(27, 29)
+
+/* Used by CM_EMU_DEBUGSS_CLKCTRL */
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     (1 << 24)
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      BITFIELD(24, 26)
+
+/* Used by CM_GFX_GFX_CLKCTRL */
+#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          (1 << 24)
+#define OMAP4430_CLKSEL_SGX_FCLK_MASK                           BITFIELD(24, 24)
+
+/*
+ * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
+ * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
+ */
+#define OMAP4430_CLKSEL_SOURCE_SHIFT                            (1 << 24)
+#define OMAP4430_CLKSEL_SOURCE_MASK                             BITFIELD(24, 25)
+
+/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
+#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      (1 << 24)
+#define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       BITFIELD(24, 24)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           (1 << 24)
+#define OMAP4430_CLKSEL_UTMI_P1_MASK                            BITFIELD(24, 24)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           (1 << 25)
+#define OMAP4430_CLKSEL_UTMI_P2_MASK                            BITFIELD(25, 25)
+
+/*
+ * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL,
+ * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
+ * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL,
+ * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
+ * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL,
+ * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE,
+ * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE,
+ * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL,
+ * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
+ * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE
+ */
+#define OMAP4430_CLKTRCTRL_SHIFT                                (1 << 0)
+#define OMAP4430_CLKTRCTRL_MASK                                 BITFIELD(0, 1)
+
+/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
+#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        (1 << 0)
+#define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         BITFIELD(0, 6)
+
+/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
+#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       (1 << 8)
+#define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        BITFIELD(8, 18)
+
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_D2D_DYNDEP_SHIFT                               (1 << 18)
+#define OMAP4430_D2D_DYNDEP_MASK                                BITFIELD(18, 18)
+
+/* Used by CM_MPU_STATICDEP */
+#define OMAP4430_D2D_STATDEP_SHIFT                              (1 << 18)
+#define OMAP4430_D2D_STATDEP_MASK                               BITFIELD(18, 18)
+
+/*
+ * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
+ * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE,
+ * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
+ * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
+ * CM_SSC_DELTAMSTEP_DPLL_MPU
+ */
+#define OMAP4430_DELTAMSTEP_SHIFT                               (1 << 0)
+#define OMAP4430_DELTAMSTEP_MASK                                BITFIELD(0, 19)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DLL_OVERRIDE_SHIFT                             (1 << 2)
+#define OMAP4430_DLL_OVERRIDE_MASK                              BITFIELD(2, 2)
+
+/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
+#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT                         (1 << 0)
+#define OMAP4430_DLL_OVERRIDE_0_0_MASK                          BITFIELD(0, 0)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DLL_RESET_SHIFT                                (1 << 3)
+#define OMAP4430_DLL_RESET_MASK                                 BITFIELD(3, 3)
+
+/*
+ * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ */
+#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          (1 << 23)
+#define OMAP4430_DPLL_BYP_CLKSEL_MASK                           BITFIELD(23, 23)
+
+/* Used by CM_CLKDCOLDO_DPLL_USB */
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 (1 << 8)
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    (1 << 20)
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     BITFIELD(20, 20)
+
+/*
+ * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
+ * CM_DIV_M3_DPLL_CORE
+ */
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       (1 << 0)
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        BITFIELD(0, 4)
+
+/*
+ * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
+ * CM_DIV_M3_DPLL_CORE
+ */
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  (1 << 5)
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   BITFIELD(5, 5)
+
+/*
+ * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
+ * CM_DIV_M3_DPLL_CORE
+ */
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 (1 << 8)
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  BITFIELD(8, 8)
+
+/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  (1 << 10)
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   BITFIELD(10, 10)
+
+/*
+ * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
+ */
+#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          (1 << 0)
+#define OMAP4430_DPLL_CLKOUT_DIV_MASK                           BITFIELD(0, 4)
+
+/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      (1 << 0)
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       BITFIELD(0, 6)
+
+/*
+ * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO,
+ * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU
+ */
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     (1 << 5)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      BITFIELD(5, 5)
+
+/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              (1 << 7)
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               BITFIELD(7, 7)
+
+/*
+ * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE,
+ * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU
+ */
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    (1 << 8)
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     BITFIELD(8, 8)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        (1 << 8)
+#define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         BITFIELD(8, 10)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         (1 << 11)
+#define OMAP4430_DPLL_CORE_M2_DIV_MASK                          BITFIELD(11, 15)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         (1 << 3)
+#define OMAP4430_DPLL_CORE_M5_DIV_MASK                          BITFIELD(3, 7)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT                 (1 << 1)
+#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK                  BITFIELD(1, 1)
+
+/*
+ * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ */
+#define OMAP4430_DPLL_DIV_SHIFT                                 (1 << 0)
+#define OMAP4430_DPLL_DIV_MASK                                  BITFIELD(0, 6)
+
+/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
+#define OMAP4430_DPLL_DIV_0_7_SHIFT                             (1 << 0)
+#define OMAP4430_DPLL_DIV_0_7_MASK                              BITFIELD(0, 7)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       (1 << 8)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        BITFIELD(8, 8)
+
+/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   (1 << 3)
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    BITFIELD(3, 3)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_EN_SHIFT                                  (1 << 0)
+#define OMAP4430_DPLL_EN_MASK                                   BITFIELD(0, 2)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_LPMODE_EN_SHIFT                           (1 << 10)
+#define OMAP4430_DPLL_LPMODE_EN_MASK                            BITFIELD(10, 10)
+
+/*
+ * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
+ * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
+ * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU
+ */
+#define OMAP4430_DPLL_MULT_SHIFT                                (1 << 8)
+#define OMAP4430_DPLL_MULT_MASK                                 BITFIELD(8, 18)
+
+/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
+#define OMAP4430_DPLL_MULT_USB_SHIFT                            (1 << 8)
+#define OMAP4430_DPLL_MULT_USB_MASK                             BITFIELD(8, 19)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_REGM4XEN_SHIFT                            (1 << 11)
+#define OMAP4430_DPLL_REGM4XEN_MASK                             BITFIELD(11, 11)
+
+/* Used by CM_CLKSEL_DPLL_USB */
+#define OMAP4430_DPLL_SD_DIV_SHIFT                              (1 << 24)
+#define OMAP4430_DPLL_SD_DIV_MASK                               BITFIELD(24, 31)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_SSC_ACK_SHIFT                             (1 << 13)
+#define OMAP4430_DPLL_SSC_ACK_MASK                              BITFIELD(13, 13)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      (1 << 14)
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       BITFIELD(14, 14)
+
+/*
+ * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB,
+ * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
+ * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU
+ */
+#define OMAP4430_DPLL_SSC_EN_SHIFT                              (1 << 12)
+#define OMAP4430_DPLL_SSC_EN_MASK                               BITFIELD(12, 12)
+
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP4430_DSS_DYNDEP_SHIFT                               (1 << 8)
+#define OMAP4430_DSS_DYNDEP_MASK                                BITFIELD(8, 8)
+
+/*
+ * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
+ * CM_MPU_STATICDEP
+ */
+#define OMAP4430_DSS_STATDEP_SHIFT                              (1 << 8)
+#define OMAP4430_DSS_STATDEP_MASK                               BITFIELD(8, 8)
+
+/* Used by CM_L3_2_DYNAMICDEP */
+#define OMAP4430_DUCATI_DYNDEP_SHIFT                            (1 << 0)
+#define OMAP4430_DUCATI_DYNDEP_MASK                             BITFIELD(0, 0)
+
+/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */
+#define OMAP4430_DUCATI_STATDEP_SHIFT                           (1 << 0)
+#define OMAP4430_DUCATI_STATDEP_MASK                            BITFIELD(0, 0)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_FREQ_UPDATE_SHIFT                              (1 << 0)
+#define OMAP4430_FREQ_UPDATE_MASK                               BITFIELD(0, 0)
+
+/* Used by CM_L3_2_DYNAMICDEP */
+#define OMAP4430_GFX_DYNDEP_SHIFT                               (1 << 10)
+#define OMAP4430_GFX_DYNDEP_MASK                                BITFIELD(10, 10)
+
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP4430_GFX_STATDEP_SHIFT                              (1 << 10)
+#define OMAP4430_GFX_STATDEP_MASK                               BITFIELD(10, 10)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         (1 << 0)
+#define OMAP4430_GPMC_FREQ_UPDATE_MASK                          BITFIELD(0, 0)
+
+/*
+ * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     BITFIELD(0, 4)
+
+/*
+ * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                BITFIELD(5, 5)
+
+/*
+ * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               BITFIELD(8, 8)
+
+/*
+ * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    BITFIELD(12, 12)
+
+/*
+ * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     BITFIELD(0, 4)
+
+/*
+ * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                BITFIELD(5, 5)
+
+/*
+ * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               BITFIELD(8, 8)
+
+/*
+ * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    BITFIELD(12, 12)
+
+/*
+ * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     BITFIELD(0, 4)
+
+/*
+ * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                BITFIELD(5, 5)
+
+/*
+ * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               BITFIELD(8, 8)
+
+/*
+ * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    BITFIELD(12, 12)
+
+/*
+ * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_CORE
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    (1 << 0)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     BITFIELD(0, 4)
+
+/*
+ * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_CORE
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               (1 << 5)
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                BITFIELD(5, 5)
+
+/*
+ * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_CORE
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              (1 << 8)
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               BITFIELD(8, 8)
+
+/*
+ * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_CORE
+ */
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   (1 << 12)
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    BITFIELD(12, 12)
+
+/*
+ * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL,
+ * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL,
+ * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL,
+ * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL,
+ * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL,
+ * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
+ * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
+ * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
+ * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
+ * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
+ * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
+ * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
+ * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
+ * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
+ * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
+ * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
+ * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
+ * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
+ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE,
+ * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
+ * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL,
+ * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL,
+ * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
+ * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL,
+ * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL,
+ * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL,
+ * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL,
+ * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
+ * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
+ */
+#define OMAP4430_IDLEST_SHIFT                                   (1 << 16)
+#define OMAP4430_IDLEST_MASK                                    BITFIELD(16, 17)
+
+/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_ISS_DYNDEP_SHIFT                               (1 << 9)
+#define OMAP4430_ISS_DYNDEP_MASK                                BITFIELD(9, 9)
+
+/*
+ * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
+ * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_ISS_STATDEP_SHIFT                              (1 << 9)
+#define OMAP4430_ISS_STATDEP_MASK                               BITFIELD(9, 9)
+
+/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
+#define OMAP4430_IVAHD_DYNDEP_SHIFT                             (1 << 2)
+#define OMAP4430_IVAHD_DYNDEP_MASK                              BITFIELD(2, 2)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP,
+ * CM_TESLA_STATICDEP
+ */
+#define OMAP4430_IVAHD_STATDEP_SHIFT                            (1 << 2)
+#define OMAP4430_IVAHD_STATDEP_MASK                             BITFIELD(2, 2)
+
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP4430_L3INIT_DYNDEP_SHIFT                            (1 << 7)
+#define OMAP4430_L3INIT_DYNDEP_MASK                             BITFIELD(7, 7)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_L3INIT_STATDEP_SHIFT                           (1 << 7)
+#define OMAP4430_L3INIT_STATDEP_MASK                            BITFIELD(7, 7)
+
+/*
+ * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
+ * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ */
+#define OMAP4430_L3_1_DYNDEP_SHIFT                              (1 << 5)
+#define OMAP4430_L3_1_DYNDEP_MASK                               BITFIELD(5, 5)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
+ * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_L3_1_STATDEP_SHIFT                             (1 << 5)
+#define OMAP4430_L3_1_STATDEP_MASK                              BITFIELD(5, 5)
+
+/*
+ * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
+ * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP,
+ * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
+ * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP
+ */
+#define OMAP4430_L3_2_DYNDEP_SHIFT                              (1 << 6)
+#define OMAP4430_L3_2_DYNDEP_MASK                               BITFIELD(6, 6)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
+ * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_L3_2_STATDEP_SHIFT                             (1 << 6)
+#define OMAP4430_L3_2_STATDEP_MASK                              BITFIELD(6, 6)
+
+/* Used by CM_L3_1_DYNAMICDEP */
+#define OMAP4430_L4CFG_DYNDEP_SHIFT                             (1 << 12)
+#define OMAP4430_L4CFG_DYNDEP_MASK                              BITFIELD(12, 12)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP,
+ * CM_TESLA_STATICDEP
+ */
+#define OMAP4430_L4CFG_STATDEP_SHIFT                            (1 << 12)
+#define OMAP4430_L4CFG_STATDEP_MASK                             BITFIELD(12, 12)
+
+/* Used by CM_L3_2_DYNAMICDEP */
+#define OMAP4430_L4PER_DYNDEP_SHIFT                             (1 << 13)
+#define OMAP4430_L4PER_DYNDEP_MASK                              BITFIELD(13, 13)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
+ * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_L4PER_STATDEP_SHIFT                            (1 << 13)
+#define OMAP4430_L4PER_STATDEP_MASK                             BITFIELD(13, 13)
+
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP4430_L4SEC_DYNDEP_SHIFT                             (1 << 14)
+#define OMAP4430_L4SEC_DYNDEP_MASK                              BITFIELD(14, 14)
+
+/*
+ * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP
+ */
+#define OMAP4430_L4SEC_STATDEP_SHIFT                            (1 << 14)
+#define OMAP4430_L4SEC_STATDEP_MASK                             BITFIELD(14, 14)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_L4WKUP_DYNDEP_SHIFT                            (1 << 15)
+#define OMAP4430_L4WKUP_DYNDEP_MASK                             BITFIELD(15, 15)
+
+/*
+ * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_L4WKUP_STATDEP_SHIFT                           (1 << 15)
+#define OMAP4430_L4WKUP_STATDEP_MASK                            BITFIELD(15, 15)
+
+/*
+ * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_MPU_DYNAMICDEP
+ */
+#define OMAP4430_MEMIF_DYNDEP_SHIFT                             (1 << 4)
+#define OMAP4430_MEMIF_DYNDEP_MASK                              BITFIELD(4, 4)
+
+/*
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP,
+ * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP,
+ * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP,
+ * CM_MPU_STATICDEP, CM_TESLA_STATICDEP
+ */
+#define OMAP4430_MEMIF_STATDEP_SHIFT                            (1 << 4)
+#define OMAP4430_MEMIF_STATDEP_MASK                             BITFIELD(4, 4)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
+ * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,
+ * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
+ * CM_SSC_MODFREQDIV_DPLL_MPU
+ */
+#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      (1 << 8)
+#define OMAP4430_MODFREQDIV_EXPONENT_MASK                       BITFIELD(8, 10)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
+ * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,
+ * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
+ * CM_SSC_MODFREQDIV_DPLL_MPU
+ */
+#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      (1 << 0)
+#define OMAP4430_MODFREQDIV_MANTISSA_MASK                       BITFIELD(0, 6)
+
+/*
+ * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL,
+ * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL,
+ * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL,
+ * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL,
+ * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL,
+ * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
+ * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
+ * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
+ * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
+ * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
+ * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
+ * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
+ * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
+ * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
+ * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
+ * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
+ * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
+ * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
+ * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
+ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE,
+ * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
+ * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL,
+ * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL,
+ * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
+ * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL,
+ * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL,
+ * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL,
+ * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL,
+ * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL,
+ * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL
+ */
+#define OMAP4430_MODULEMODE_SHIFT                               (1 << 0)
+#define OMAP4430_MODULEMODE_MASK                                BITFIELD(0, 1)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      (1 << 9)
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       BITFIELD(9, 9)
+
+/* Used by CM_WKUP_BANDGAP_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       (1 << 8)
+#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         (1 << 9)
+#define OMAP4430_OPTFCLKEN_CLK32K_MASK                          BITFIELD(9, 9)
+
+/* Used by CM_CAM_ISS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        (1 << 8)
+#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         BITFIELD(8, 8)
+
+/*
+ * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
+ * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE
+ */
+#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          (1 << 8)
+#define OMAP4430_OPTFCLKEN_DBCLK_MASK                           BITFIELD(8, 8)
+
+/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        (1 << 8)
+#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         BITFIELD(8, 8)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         (1 << 8)
+#define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          BITFIELD(8, 8)
+
+/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          (1 << 8)
+#define OMAP4430_OPTFCLKEN_FCLK0_MASK                           BITFIELD(8, 8)
+
+/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          (1 << 9)
+#define OMAP4430_OPTFCLKEN_FCLK1_MASK                           BITFIELD(9, 9)
+
+/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          (1 << 10)
+#define OMAP4430_OPTFCLKEN_FCLK2_MASK                           BITFIELD(10, 10)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     (1 << 15)
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      BITFIELD(15, 15)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                (1 << 13)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 BITFIELD(13, 13)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                (1 << 14)
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 BITFIELD(14, 14)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 (1 << 11)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  BITFIELD(11, 11)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 (1 << 12)
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  BITFIELD(12, 12)
+
+/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  (1 << 8)
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   BITFIELD(8, 8)
+
+/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                (1 << 9)
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 BITFIELD(9, 9)
+
+/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        (1 << 8)
+#define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         BITFIELD(8, 8)
+
+/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    (1 << 10)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     BITFIELD(10, 10)
+
+/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              (1 << 11)
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               BITFIELD(11, 11)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        (1 << 10)
+#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         BITFIELD(10, 10)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         (1 << 11)
+#define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          BITFIELD(11, 11)
+
+/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       (1 << 8)
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    (1 << 8)
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    (1 << 9)
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     BITFIELD(9, 9)
+
+/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    (1 << 10)
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     BITFIELD(10, 10)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    (1 << 8)
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     BITFIELD(8, 8)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    (1 << 9)
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     BITFIELD(9, 9)
+
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    (1 << 10)
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     BITFIELD(10, 10)
+
+/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
+#define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           (1 << 8)
+#define OMAP4430_OPTFCLKEN_XCLK_MASK                            BITFIELD(8, 8)
+
+/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */
+#define OMAP4430_OVERRIDE_ENABLE_SHIFT                          (1 << 19)
+#define OMAP4430_OVERRIDE_ENABLE_MASK                           BITFIELD(19, 19)
+
+/* Used by CM_CLKSEL_ABE */
+#define OMAP4430_PAD_CLKS_GATE_SHIFT                            (1 << 8)
+#define OMAP4430_PAD_CLKS_GATE_MASK                             BITFIELD(8, 8)
+
+/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
+#define OMAP4430_PERF_CURRENT_SHIFT                             (1 << 0)
+#define OMAP4430_PERF_CURRENT_MASK                              BITFIELD(0, 7)
+
+/*
+ * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
+ * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
+ * CM_IVA_DVFS_PERF_TESLA
+ */
+#define OMAP4430_PERF_REQ_SHIFT                                 (1 << 0)
+#define OMAP4430_PERF_REQ_MASK                                  BITFIELD(0, 7)
+
+/* Used by CM_EMU_OVERRIDE_DPLL_PER */
+#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT                         (1 << 0)
+#define OMAP4430_PER_DPLL_EMU_DIV_MASK                          BITFIELD(0, 6)
+
+/* Used by CM_EMU_OVERRIDE_DPLL_PER */
+#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT                        (1 << 8)
+#define OMAP4430_PER_DPLL_EMU_MULT_MASK                         BITFIELD(8, 18)
+
+/* Used by CM_RESTORE_ST */
+#define OMAP4430_PHASE1_COMPLETED_SHIFT                         (1 << 0)
+#define OMAP4430_PHASE1_COMPLETED_MASK                          BITFIELD(0, 0)
+
+/* Used by CM_RESTORE_ST */
+#define OMAP4430_PHASE2A_COMPLETED_SHIFT                        (1 << 1)
+#define OMAP4430_PHASE2A_COMPLETED_MASK                         BITFIELD(1, 1)
+
+/* Used by CM_RESTORE_ST */
+#define OMAP4430_PHASE2B_COMPLETED_SHIFT                        (1 << 2)
+#define OMAP4430_PHASE2B_COMPLETED_MASK                         BITFIELD(2, 2)
+
+/* Used by CM_EMU_DEBUGSS_CLKCTRL */
+#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         (1 << 20)
+#define OMAP4430_PMD_STM_MUX_CTRL_MASK                          BITFIELD(20, 21)
+
+/* Used by CM_EMU_DEBUGSS_CLKCTRL */
+#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       (1 << 22)
+#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        BITFIELD(22, 23)
+
+/* Used by CM_DYN_DEP_PRESCAL */
+#define OMAP4430_PRESCAL_SHIFT                                  (1 << 0)
+#define OMAP4430_PRESCAL_MASK                                   BITFIELD(0, 5)
+
+/* Used by REVISION_CM2, REVISION_CM1 */
+#define OMAP4430_REV_SHIFT                                      (1 << 0)
+#define OMAP4430_REV_MASK                                       BITFIELD(0, 7)
+
+/*
+ * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
+ */
+#define OMAP4430_SAR_MODE_SHIFT                                 (1 << 4)
+#define OMAP4430_SAR_MODE_MASK                                  BITFIELD(4, 4)
+
+/* Used by CM_SCALE_FCLK */
+#define OMAP4430_SCALE_FCLK_SHIFT                               (1 << 0)
+#define OMAP4430_SCALE_FCLK_MASK                                BITFIELD(0, 0)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_SDMA_DYNDEP_SHIFT                              (1 << 11)
+#define OMAP4430_SDMA_DYNDEP_MASK                               BITFIELD(11, 11)
+
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP4430_SDMA_STATDEP_SHIFT                             (1 << 11)
+#define OMAP4430_SDMA_STATDEP_MASK                              BITFIELD(11, 11)
+
+/* Used by CM_CLKSEL_ABE */
+#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         (1 << 10)
+#define OMAP4430_SLIMBUS_CLK_GATE_MASK                          BITFIELD(10, 10)
+
+/*
+ * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
+ * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
+ * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL
+ */
+#define OMAP4430_STBYST_SHIFT                                   (1 << 18)
+#define OMAP4430_STBYST_MASK                                    BITFIELD(18, 18)
+
+/*
+ * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB,
+ * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
+ * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU
+ */
+#define OMAP4430_ST_DPLL_CLK_SHIFT                              (1 << 0)
+#define OMAP4430_ST_DPLL_CLK_MASK                               BITFIELD(0, 0)
+
+/* Used by CM_CLKDCOLDO_DPLL_USB */
+#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        (1 << 9)
+#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         BITFIELD(9, 9)
+
+/*
+ * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE,
+ * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU
+ */
+#define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           (1 << 9)
+#define OMAP4430_ST_DPLL_CLKOUT_MASK                            BITFIELD(9, 9)
+
+/*
+ * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE,
+ * CM_DIV_M3_DPLL_CORE
+ */
+#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        (1 << 9)
+#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         BITFIELD(9, 9)
+
+/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */
+#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         (1 << 11)
+#define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          BITFIELD(11, 11)
+
+/*
+ * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE,
+ * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA
+ */
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      BITFIELD(9, 9)
+
+/*
+ * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE,
+ * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA
+ */
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      BITFIELD(9, 9)
+
+/*
+ * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE,
+ * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY
+ */
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      BITFIELD(9, 9)
+
+/*
+ * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE,
+ * CM_DIV_M7_DPLL_CORE
+ */
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     (1 << 9)
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      BITFIELD(9, 9)
+
+/* Used by CM_SYS_CLKSEL */
+#define OMAP4430_SYS_CLKSEL_SHIFT                               (1 << 0)
+#define OMAP4430_SYS_CLKSEL_MASK                                BITFIELD(0, 2)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP4430_TESLA_DYNDEP_SHIFT                             (1 << 1)
+#define OMAP4430_TESLA_DYNDEP_MASK                              BITFIELD(1, 1)
+
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP4430_TESLA_STATDEP_SHIFT                            (1 << 1)
+#define OMAP4430_TESLA_STATDEP_MASK                             BITFIELD(1, 1)
+
+/*
+ * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
+ * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ */
+#define OMAP4430_WINDOWSIZE_SHIFT                               (1 << 24)
+#define OMAP4430_WINDOWSIZE_MASK                                BITFIELD(24, 27)
+#endif
diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c
index 8eb2dab8c7db..58e4a1c557d8 100644
--- a/arch/arm/mach-omap2/cm.c
+++ b/arch/arm/mach-omap2/cm.c
@@ -21,6 +21,8 @@
 
 #include <asm/atomic.h>
 
+#include <plat/common.h>
+
 #include "cm.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
@@ -61,9 +63,8 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
         mask = 1 << idlest_shift;
 
         /* XXX should be OMAP2 CM */
-        while (((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) != ena) &&
-               (i++ < MAX_MODULE_READY_TIME))
-                udelay(1);
+        omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
+                          MAX_MODULE_READY_TIME, i);
 
         return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 }
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index a2fcfcc253cc..90a4086fbdf4 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -4,8 +4,8 @@
 /*
  * OMAP2/3 Clock Management (CM) register definitions
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -22,6 +22,12 @@
                         OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
 #define OMAP34XX_CM_REGADDR(module, reg)                                \
                         OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+#define OMAP44XX_CM1_REGADDR(module, reg)                               \
+                        OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
+#define OMAP44XX_CM2_REGADDR(module, reg)                               \
+                        OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
+
+#include "cm44xx.h"
 
 /*
  * Architecture-specific global CM registers
@@ -89,6 +95,11 @@
 #define OMAP3430_CM_CLKSEL2_EMU                         0x0050
 #define OMAP3430_CM_CLKSEL3_EMU                         0x0054
 
+/* CM2.CEFUSE_CM2 register offsets */
+
+/* OMAP4 modulemode control */
+#define OMAP4430_MODULEMODE_HWCTRL                      0
+#define OMAP4430_MODULEMODE_SWCTRL                      1
 
 /* Clock management domain register get/set */
 
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
new file mode 100644
index 000000000000..c575b9b0c041
--- /dev/null
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -0,0 +1,358 @@
+/*
+ * OMAP44xx CM1 & CM2 instance offset macros
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM44XX_H
+
+
+/* CM1 */
+
+
+/* CM1.OCP_SOCKET_CM1 register offsets */
+#define OMAP4430_REVISION_CM1                           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000)
+#define OMAP4430_CM_CM1_PROFILING_CLKCTRL               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040)
+
+/* CM1.CKGEN_CM1 register offsets */
+#define OMAP4430_CM_CLKSEL_CORE                         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000)
+#define OMAP4430_CM_CLKSEL_ABE                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008)
+#define OMAP4430_CM_DLL_CTRL                            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010)
+#define OMAP4430_CM_CLKMODE_DPLL_CORE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020)
+#define OMAP4430_CM_IDLEST_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024)
+#define OMAP4430_CM_AUTOIDLE_DPLL_CORE                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028)
+#define OMAP4430_CM_CLKSEL_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c)
+#define OMAP4430_CM_DIV_M2_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030)
+#define OMAP4430_CM_DIV_M3_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034)
+#define OMAP4430_CM_DIV_M4_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038)
+#define OMAP4430_CM_DIV_M5_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c)
+#define OMAP4430_CM_DIV_M6_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040)
+#define OMAP4430_CM_DIV_M7_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c)
+#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE              OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050)
+#define OMAP4430_CM_CLKMODE_DPLL_MPU                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060)
+#define OMAP4430_CM_IDLEST_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064)
+#define OMAP4430_CM_AUTOIDLE_DPLL_MPU                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068)
+#define OMAP4430_CM_CLKSEL_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c)
+#define OMAP4430_CM_DIV_M2_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c)
+#define OMAP4430_CM_BYPCLK_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c)
+#define OMAP4430_CM_CLKMODE_DPLL_IVA                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0)
+#define OMAP4430_CM_IDLEST_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4)
+#define OMAP4430_CM_AUTOIDLE_DPLL_IVA                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8)
+#define OMAP4430_CM_CLKSEL_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac)
+#define OMAP4430_CM_DIV_M4_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8)
+#define OMAP4430_CM_DIV_M5_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc)
+#define OMAP4430_CM_BYPCLK_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc)
+#define OMAP4430_CM_CLKMODE_DPLL_ABE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0)
+#define OMAP4430_CM_IDLEST_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4)
+#define OMAP4430_CM_AUTOIDLE_DPLL_ABE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8)
+#define OMAP4430_CM_CLKSEL_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec)
+#define OMAP4430_CM_DIV_M2_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0)
+#define OMAP4430_CM_DIV_M3_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c)
+#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120)
+#define OMAP4430_CM_IDLEST_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124)
+#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128)
+#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c)
+#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130)
+#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138)
+#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c)
+#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c)
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG1                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160)
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG2                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164)
+#define OMAP4430_CM_DYN_DEP_PRESCAL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170)
+#define OMAP4430_CM_RESTORE_ST                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180)
+
+/* CM1.MPU_CM1 register offsets */
+#define OMAP4430_CM_MPU_CLKSTCTRL                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000)
+#define OMAP4430_CM_MPU_STATICDEP                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004)
+#define OMAP4430_CM_MPU_DYNAMICDEP                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008)
+#define OMAP4430_CM_MPU_MPU_CLKCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020)
+
+/* CM1.TESLA_CM1 register offsets */
+#define OMAP4430_CM_TESLA_CLKSTCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000)
+#define OMAP4430_CM_TESLA_STATICDEP                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004)
+#define OMAP4430_CM_TESLA_DYNAMICDEP                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008)
+#define OMAP4430_CM_TESLA_TESLA_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020)
+
+/* CM1.ABE_CM1 register offsets */
+#define OMAP4430_CM1_ABE_CLKSTCTRL                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000)
+#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020)
+#define OMAP4430_CM1_ABE_AESS_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028)
+#define OMAP4430_CM1_ABE_PDM_CLKCTRL                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030)
+#define OMAP4430_CM1_ABE_DMIC_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038)
+#define OMAP4430_CM1_ABE_MCASP_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040)
+#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048)
+#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050)
+#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058)
+#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060)
+#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068)
+#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070)
+#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078)
+#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080)
+#define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
+
+/* CM1.RESTORE_CM1 register offsets */
+#define OMAP4430_CM_CLKSEL_CORE_RESTORE                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
+#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
+#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
+#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
+#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
+#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
+#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
+#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
+#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
+#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
+#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
+
+/* CM2 */
+
+
+/* CM2.OCP_SOCKET_CM2 register offsets */
+#define OMAP4430_REVISION_CM2                           OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000)
+#define OMAP4430_CM_CM2_PROFILING_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040)
+
+/* CM2.CKGEN_CM2 register offsets */
+#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000)
+#define OMAP4430_CM_CLKSEL_USB_60MHZ                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004)
+#define OMAP4430_CM_SCALE_FCLK                          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008)
+#define OMAP4430_CM_CORE_DVFS_PERF1                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010)
+#define OMAP4430_CM_CORE_DVFS_PERF2                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014)
+#define OMAP4430_CM_CORE_DVFS_PERF3                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018)
+#define OMAP4430_CM_CORE_DVFS_PERF4                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c)
+#define OMAP4430_CM_CORE_DVFS_CURRENT                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024)
+#define OMAP4430_CM_IVA_DVFS_PERF_TESLA                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028)
+#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c)
+#define OMAP4430_CM_IVA_DVFS_PERF_ABE                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030)
+#define OMAP4430_CM_IVA_DVFS_CURRENT                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038)
+#define OMAP4430_CM_CLKMODE_DPLL_PER                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040)
+#define OMAP4430_CM_IDLEST_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044)
+#define OMAP4430_CM_AUTOIDLE_DPLL_PER                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048)
+#define OMAP4430_CM_CLKSEL_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c)
+#define OMAP4430_CM_DIV_M2_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050)
+#define OMAP4430_CM_DIV_M3_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054)
+#define OMAP4430_CM_DIV_M4_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058)
+#define OMAP4430_CM_DIV_M5_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c)
+#define OMAP4430_CM_DIV_M6_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060)
+#define OMAP4430_CM_DIV_M7_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
+#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
+#define OMAP4430_CM_CLKMODE_DPLL_USB                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
+#define OMAP4430_CM_IDLEST_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084)
+#define OMAP4430_CM_AUTOIDLE_DPLL_USB                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088)
+#define OMAP4430_CM_CLKSEL_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c)
+#define OMAP4430_CM_DIV_M2_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac)
+#define OMAP4430_CM_CLKDCOLDO_DPLL_USB                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4)
+#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0)
+#define OMAP4430_CM_IDLEST_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4)
+#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8)
+#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc)
+#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0)
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8)
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec)
+
+/* CM2.ALWAYS_ON_CM2 register offsets */
+#define OMAP4430_CM_ALWON_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000)
+#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020)
+#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028)
+#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
+#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
+
+/* CM2.CORE_CM2 register offsets */
+#define OMAP4430_CM_L3_1_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000)
+#define OMAP4430_CM_L3_1_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008)
+#define OMAP4430_CM_L3_1_L3_1_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020)
+#define OMAP4430_CM_L3_2_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100)
+#define OMAP4430_CM_L3_2_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108)
+#define OMAP4430_CM_L3_2_L3_2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120)
+#define OMAP4430_CM_L3_2_GPMC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128)
+#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130)
+#define OMAP4430_CM_DUCATI_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200)
+#define OMAP4430_CM_DUCATI_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204)
+#define OMAP4430_CM_DUCATI_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208)
+#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220)
+#define OMAP4430_CM_SDMA_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300)
+#define OMAP4430_CM_SDMA_STATICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304)
+#define OMAP4430_CM_SDMA_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308)
+#define OMAP4430_CM_SDMA_SDMA_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320)
+#define OMAP4430_CM_MEMIF_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400)
+#define OMAP4430_CM_MEMIF_DMM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420)
+#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428)
+#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430)
+#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438)
+#define OMAP4430_CM_MEMIF_DLL_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440)
+#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450)
+#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458)
+#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460)
+#define OMAP4430_CM_D2D_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500)
+#define OMAP4430_CM_D2D_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504)
+#define OMAP4430_CM_D2D_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508)
+#define OMAP4430_CM_D2D_SAD2D_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520)
+#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528)
+#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530)
+#define OMAP4430_CM_L4CFG_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600)
+#define OMAP4430_CM_L4CFG_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608)
+#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620)
+#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628)
+#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630)
+#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638)
+#define OMAP4430_CM_L3INSTR_CLKSTCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700)
+#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720)
+#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728)
+#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740)
+
+/* CM2.IVAHD_CM2 register offsets */
+#define OMAP4430_CM_IVAHD_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000)
+#define OMAP4430_CM_IVAHD_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004)
+#define OMAP4430_CM_IVAHD_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008)
+#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020)
+#define OMAP4430_CM_IVAHD_SL2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028)
+
+/* CM2.CAM_CM2 register offsets */
+#define OMAP4430_CM_CAM_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000)
+#define OMAP4430_CM_CAM_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004)
+#define OMAP4430_CM_CAM_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008)
+#define OMAP4430_CM_CAM_ISS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020)
+#define OMAP4430_CM_CAM_FDIF_CLKCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028)
+
+/* CM2.DSS_CM2 register offsets */
+#define OMAP4430_CM_DSS_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000)
+#define OMAP4430_CM_DSS_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004)
+#define OMAP4430_CM_DSS_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008)
+#define OMAP4430_CM_DSS_DSS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020)
+#define OMAP4430_CM_DSS_DEISS_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028)
+
+/* CM2.GFX_CM2 register offsets */
+#define OMAP4430_CM_GFX_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000)
+#define OMAP4430_CM_GFX_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004)
+#define OMAP4430_CM_GFX_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008)
+#define OMAP4430_CM_GFX_GFX_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020)
+
+/* CM2.L3INIT_CM2 register offsets */
+#define OMAP4430_CM_L3INIT_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000)
+#define OMAP4430_CM_L3INIT_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004)
+#define OMAP4430_CM_L3INIT_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008)
+#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028)
+#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030)
+#define OMAP4430_CM_L3INIT_HSI_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038)
+#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040)
+#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058)
+#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060)
+#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068)
+#define OMAP4430_CM_L3INIT_P1500_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078)
+#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080)
+#define OMAP4430_CM_L3INIT_SATA_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088)
+#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090)
+#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098)
+#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8)
+#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0)
+#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8)
+#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0)
+#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0)
+
+/* CM2.L4PER_CM2 register offsets */
+#define OMAP4430_CM_L4PER_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000)
+#define OMAP4430_CM_L4PER_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008)
+#define OMAP4430_CM_L4PER_ADC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020)
+#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028)
+#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030)
+#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038)
+#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040)
+#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048)
+#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050)
+#define OMAP4430_CM_L4PER_ELM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058)
+#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060)
+#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068)
+#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070)
+#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078)
+#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080)
+#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088)
+#define OMAP4430_CM_L4PER_HECC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090)
+#define OMAP4430_CM_L4PER_HECC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098)
+#define OMAP4430_CM_L4PER_I2C1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0)
+#define OMAP4430_CM_L4PER_I2C2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8)
+#define OMAP4430_CM_L4PER_I2C3_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0)
+#define OMAP4430_CM_L4PER_I2C4_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8)
+#define OMAP4430_CM_L4PER_L4PER_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0)
+#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0)
+#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8)
+#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0)
+#define OMAP4430_CM_L4PER_MGATE_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8)
+#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0)
+#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8)
+#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100)
+#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108)
+#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120)
+#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128)
+#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130)
+#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138)
+#define OMAP4430_CM_L4PER_UART1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140)
+#define OMAP4430_CM_L4PER_UART2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148)
+#define OMAP4430_CM_L4PER_UART3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150)
+#define OMAP4430_CM_L4PER_UART4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158)
+#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160)
+#define OMAP4430_CM_L4PER_I2C5_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168)
+#define OMAP4430_CM_L4SEC_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180)
+#define OMAP4430_CM_L4SEC_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184)
+#define OMAP4430_CM_L4SEC_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188)
+#define OMAP4430_CM_L4SEC_AES1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0)
+#define OMAP4430_CM_L4SEC_AES2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8)
+#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0)
+#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8)
+#define OMAP4430_CM_L4SEC_RNG_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0)
+#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8)
+#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8)
+
+/* CM2.CEFUSE_CM2 register offsets */
+#define OMAP4430_CM_CEFUSE_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
+#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
+
+/* CM2.RESTORE_CM2 register offsets */
+#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
+#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
+#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
+#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
+#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
+#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
+#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
+#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
+#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
+#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
+#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
+#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
+#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
+#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
+#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
+#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
+#define OMAP4430_CM_SDMA_STATICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
+#endif
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 733d3dcff98b..18ad93160abb 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -27,6 +27,8 @@
 #include <mach/gpio.h>
 #include <plat/mmc.h>
 
+#include "mux.h"
+
 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
 
 static struct resource cam_resources[] = {
@@ -595,27 +597,40 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
 
         if (cpu_is_omap34xx()) {
                 if (controller_nr == 0) {
-                        omap_cfg_reg(N28_3430_MMC1_CLK);
-                        omap_cfg_reg(M27_3430_MMC1_CMD);
-                        omap_cfg_reg(N27_3430_MMC1_DAT0);
+                        omap_mux_init_signal("sdmmc1_clk",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc1_cmd",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc1_dat0",
+                                OMAP_PIN_INPUT_PULLUP);
                         if (mmc_controller->slots[0].wires == 4 ||
                                 mmc_controller->slots[0].wires == 8) {
-                                omap_cfg_reg(N26_3430_MMC1_DAT1);
-                                omap_cfg_reg(N25_3430_MMC1_DAT2);
-                                omap_cfg_reg(P28_3430_MMC1_DAT3);
+                                omap_mux_init_signal("sdmmc1_dat1",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat2",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat3",
+                                        OMAP_PIN_INPUT_PULLUP);
                         }
                         if (mmc_controller->slots[0].wires == 8) {
-                                omap_cfg_reg(P27_3430_MMC1_DAT4);
-                                omap_cfg_reg(P26_3430_MMC1_DAT5);
-                                omap_cfg_reg(R27_3430_MMC1_DAT6);
-                                omap_cfg_reg(R25_3430_MMC1_DAT7);
+                                omap_mux_init_signal("sdmmc1_dat4",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat5",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat6",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat7",
+                                        OMAP_PIN_INPUT_PULLUP);
                         }
                 }
                 if (controller_nr == 1) {
                         /* MMC2 */
-                        omap_cfg_reg(AE2_3430_MMC2_CLK);
-                        omap_cfg_reg(AG5_3430_MMC2_CMD);
-                        omap_cfg_reg(AH5_3430_MMC2_DAT0);
+                        omap_mux_init_signal("sdmmc2_clk",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc2_cmd",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc2_dat0",
+                                OMAP_PIN_INPUT_PULLUP);
 
                         /*
                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
@@ -623,15 +638,22 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                          */
                         if (mmc_controller->slots[0].wires == 4 ||
                                 mmc_controller->slots[0].wires == 8) {
-                                omap_cfg_reg(AH4_3430_MMC2_DAT1);
-                                omap_cfg_reg(AG4_3430_MMC2_DAT2);
-                                omap_cfg_reg(AF4_3430_MMC2_DAT3);
+                                omap_mux_init_signal("sdmmc2_dat1",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat2",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat3",
+                                        OMAP_PIN_INPUT_PULLUP);
                         }
                         if (mmc_controller->slots[0].wires == 8) {
-                                omap_cfg_reg(AE4_3430_MMC2_DAT4);
-                                omap_cfg_reg(AH3_3430_MMC2_DAT5);
-                                omap_cfg_reg(AF3_3430_MMC2_DAT6);
-                                omap_cfg_reg(AE3_3430_MMC2_DAT7);
+                                omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
+                                        OMAP_PIN_INPUT_PULLUP);
                         }
                 }
 
diff --git a/arch/arm/mach-omap2/dpll.c b/arch/arm/mach-omap2/dpll.c
new file mode 100644
index 000000000000..f6055b493294
--- /dev/null
+++ b/arch/arm/mach-omap2/dpll.c
@@ -0,0 +1,538 @@
+/*
+ * OMAP3/4 - specific DPLL control functions
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ * Testing and integration fixes by Jouni Högander
+ *
+ * Parts of this code are based on code written by
+ * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/limits.h>
+#include <linux/bitops.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/sram.h>
+#include <asm/div64.h>
+#include <asm/clkdev.h>
+
+#include "clock.h"
+#include "prm.h"
+#include "prm-regbits-34xx.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+
+/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
+#define DPLL_AUTOIDLE_DISABLE                   0x0
+#define DPLL_AUTOIDLE_LOW_POWER_STOP            0x1
+
+#define MAX_DPLL_WAIT_TRIES             1000000
+
+
+/**
+ * omap3_dpll_recalc - recalculate DPLL rate
+ * @clk: DPLL struct clk
+ *
+ * Recalculate and propagate the DPLL rate.
+ */
+unsigned long omap3_dpll_recalc(struct clk *clk)
+{
+        return omap2_get_dpll_rate(clk);
+}
+
+/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
+static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
+{
+        const struct dpll_data *dd;
+        u32 v;
+
+        dd = clk->dpll_data;
+
+        v = __raw_readl(dd->control_reg);
+        v &= ~dd->enable_mask;
+        v |= clken_bits << __ffs(dd->enable_mask);
+        __raw_writel(v, dd->control_reg);
+}
+
+/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
+static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
+{
+        const struct dpll_data *dd;
+        int i = 0;
+        int ret = -EINVAL;
+
+        dd = clk->dpll_data;
+
+        state <<= __ffs(dd->idlest_mask);
+
+        while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
+               i < MAX_DPLL_WAIT_TRIES) {
+                i++;
+                udelay(1);
+        }
+
+        if (i == MAX_DPLL_WAIT_TRIES) {
+                printk(KERN_ERR "clock: %s failed transition to '%s'\n",
+                       clk->name, (state) ? "locked" : "bypassed");
+        } else {
+                pr_debug("clock: %s transition to '%s' in %d loops\n",
+                         clk->name, (state) ? "locked" : "bypassed", i);
+
+                ret = 0;
+        }
+
+        return ret;
+}
+
+/* From 3430 TRM ES2 4.7.6.2 */
+static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
+{
+        unsigned long fint;
+        u16 f = 0;
+
+        fint = clk->dpll_data->clk_ref->rate / n;
+
+        pr_debug("clock: fint is %lu\n", fint);
+
+        if (fint >= 750000 && fint <= 1000000)
+                f = 0x3;
+        else if (fint > 1000000 && fint <= 1250000)
+                f = 0x4;
+        else if (fint > 1250000 && fint <= 1500000)
+                f = 0x5;
+        else if (fint > 1500000 && fint <= 1750000)
+                f = 0x6;
+        else if (fint > 1750000 && fint <= 2100000)
+                f = 0x7;
+        else if (fint > 7500000 && fint <= 10000000)
+                f = 0xB;
+        else if (fint > 10000000 && fint <= 12500000)
+                f = 0xC;
+        else if (fint > 12500000 && fint <= 15000000)
+                f = 0xD;
+        else if (fint > 15000000 && fint <= 17500000)
+                f = 0xE;
+        else if (fint > 17500000 && fint <= 21000000)
+                f = 0xF;
+        else
+                pr_debug("clock: unknown freqsel setting for %d\n", n);
+
+        return f;
+}
+
+/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
+
+/*
+ * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to lock.  Waits for the DPLL to report
+ * readiness before returning.  Will save and restore the DPLL's
+ * autoidle state across the enable, per the CDP code.  If the DPLL
+ * locked successfully, return 0; if the DPLL did not lock in the time
+ * allotted, or DPLL3 was passed in, return -EINVAL.
+ */
+static int _omap3_noncore_dpll_lock(struct clk *clk)
+{
+        u8 ai;
+        int r;
+
+        pr_debug("clock: locking DPLL %s\n", clk->name);
+
+        ai = omap3_dpll_autoidle_read(clk);
+
+        omap3_dpll_deny_idle(clk);
+
+        _omap3_dpll_write_clken(clk, DPLL_LOCKED);
+
+        r = _omap3_wait_dpll_status(clk, 1);
+
+        if (ai)
+                omap3_dpll_allow_idle(clk);
+
+        return r;
+}
+
+/*
+ * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enter low-power bypass mode.  In
+ * bypass mode, the DPLL's rate is set equal to its parent clock's
+ * rate.  Waits for the DPLL to report readiness before returning.
+ * Will save and restore the DPLL's autoidle state across the enable,
+ * per the CDP code.  If the DPLL entered bypass mode successfully,
+ * return 0; if the DPLL did not enter bypass in the time allotted, or
+ * DPLL3 was passed in, or the DPLL does not support low-power bypass,
+ * return -EINVAL.
+ */
+static int _omap3_noncore_dpll_bypass(struct clk *clk)
+{
+        int r;
+        u8 ai;
+
+        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
+                return -EINVAL;
+
+        pr_debug("clock: configuring DPLL %s for low-power bypass\n",
+                 clk->name);
+
+        ai = omap3_dpll_autoidle_read(clk);
+
+        _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
+
+        r = _omap3_wait_dpll_status(clk, 0);
+
+        if (ai)
+                omap3_dpll_allow_idle(clk);
+        else
+                omap3_dpll_deny_idle(clk);
+
+        return r;
+}
+
+/*
+ * _omap3_noncore_dpll_stop - instruct a DPLL to stop
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enter low-power stop. Will save and
+ * restore the DPLL's autoidle state across the stop, per the CDP
+ * code.  If DPLL3 was passed in, or the DPLL does not support
+ * low-power stop, return -EINVAL; otherwise, return 0.
+ */
+static int _omap3_noncore_dpll_stop(struct clk *clk)
+{
+        u8 ai;
+
+        if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
+                return -EINVAL;
+
+        pr_debug("clock: stopping DPLL %s\n", clk->name);
+
+        ai = omap3_dpll_autoidle_read(clk);
+
+        _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
+
+        if (ai)
+                omap3_dpll_allow_idle(clk);
+        else
+                omap3_dpll_deny_idle(clk);
+
+        return 0;
+}
+
+/**
+ * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
+ * The choice of modes depends on the DPLL's programmed rate: if it is
+ * the same as the DPLL's parent clock, it will enter bypass;
+ * otherwise, it will enter lock.  This code will wait for the DPLL to
+ * indicate readiness before returning, unless the DPLL takes too long
+ * to enter the target state.  Intended to be used as the struct clk's
+ * enable function.  If DPLL3 was passed in, or the DPLL does not
+ * support low-power stop, or if the DPLL took too long to enter
+ * bypass or lock, return -EINVAL; otherwise, return 0.
+ */
+int omap3_noncore_dpll_enable(struct clk *clk)
+{
+        int r;
+        struct dpll_data *dd;
+
+        dd = clk->dpll_data;
+        if (!dd)
+                return -EINVAL;
+
+        if (clk->rate == dd->clk_bypass->rate) {
+                WARN_ON(clk->parent != dd->clk_bypass);
+                r = _omap3_noncore_dpll_bypass(clk);
+        } else {
+                WARN_ON(clk->parent != dd->clk_ref);
+                r = _omap3_noncore_dpll_lock(clk);
+        }
+        /*
+         *FIXME: this is dubious - if clk->rate has changed, what about
+         * propagating?
+         */
+        if (!r)
+                clk->rate = omap2_get_dpll_rate(clk);
+
+        return r;
+}
+
+/**
+ * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
+ * @clk: pointer to a DPLL struct clk
+ *
+ * Instructs a non-CORE DPLL to enter low-power stop.  This function is
+ * intended for use in struct clkops.  No return value.
+ */
+void omap3_noncore_dpll_disable(struct clk *clk)
+{
+        _omap3_noncore_dpll_stop(clk);
+}
+
+
+/* Non-CORE DPLL rate set code */
+
+/*
+ * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
+ * @clk: struct clk * of DPLL to set
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ * @freqsel: FREQSEL value to set
+ *
+ * Program the DPLL with the supplied M, N values, and wait for the DPLL to
+ * lock..  Returns -EINVAL upon error, or 0 upon success.
+ */
+int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
+{
+        struct dpll_data *dd = clk->dpll_data;
+        u32 v;
+
+        /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
+        _omap3_noncore_dpll_bypass(clk);
+
+        /* Set jitter correction */
+        if (!cpu_is_omap44xx()) {
+                v = __raw_readl(dd->control_reg);
+                v &= ~dd->freqsel_mask;
+                v |= freqsel << __ffs(dd->freqsel_mask);
+                __raw_writel(v, dd->control_reg);
+        }
+
+        /* Set DPLL multiplier, divider */
+        v = __raw_readl(dd->mult_div1_reg);
+        v &= ~(dd->mult_mask | dd->div1_mask);
+        v |= m << __ffs(dd->mult_mask);
+        v |= (n - 1) << __ffs(dd->div1_mask);
+        __raw_writel(v, dd->mult_div1_reg);
+
+        /* We let the clock framework set the other output dividers later */
+
+        /* REVISIT: Set ramp-up delay? */
+
+        _omap3_noncore_dpll_lock(clk);
+
+        return 0;
+}
+
+/**
+ * omap3_noncore_dpll_set_rate - set non-core DPLL rate
+ * @clk: struct clk * of DPLL to set
+ * @rate: rounded target rate
+ *
+ * Set the DPLL CLKOUT to the target rate.  If the DPLL can enter
+ * low-power bypass, and the target rate is the bypass source clock
+ * rate, then configure the DPLL for bypass.  Otherwise, round the
+ * target rate if it hasn't been done already, then program and lock
+ * the DPLL.  Returns -EINVAL upon error, or 0 upon success.
+ */
+int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct clk *new_parent = NULL;
+        u16 freqsel = 0;
+        struct dpll_data *dd;
+        int ret;
+
+        if (!clk || !rate)
+                return -EINVAL;
+
+        dd = clk->dpll_data;
+        if (!dd)
+                return -EINVAL;
+
+        if (rate == omap2_get_dpll_rate(clk))
+                return 0;
+
+        /*
+         * Ensure both the bypass and ref clocks are enabled prior to
+         * doing anything; we need the bypass clock running to reprogram
+         * the DPLL.
+         */
+        omap2_clk_enable(dd->clk_bypass);
+        omap2_clk_enable(dd->clk_ref);
+
+        if (dd->clk_bypass->rate == rate &&
+            (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
+                pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
+
+                ret = _omap3_noncore_dpll_bypass(clk);
+                if (!ret)
+                        new_parent = dd->clk_bypass;
+        } else {
+                if (dd->last_rounded_rate != rate)
+                        omap2_dpll_round_rate(clk, rate);
+
+                if (dd->last_rounded_rate == 0)
+                        return -EINVAL;
+
+                /* No freqsel on OMAP4 */
+                if (!cpu_is_omap44xx()) {
+                        freqsel = _omap3_dpll_compute_freqsel(clk,
+                                                dd->last_rounded_n);
+                        if (!freqsel)
+                                WARN_ON(1);
+                }
+
+                pr_debug("clock: %s: set rate: locking rate to %lu.\n",
+                         clk->name, rate);
+
+                ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
+                                                 dd->last_rounded_n, freqsel);
+                if (!ret)
+                        new_parent = dd->clk_ref;
+        }
+        if (!ret) {
+                /*
+                 * Switch the parent clock in the heirarchy, and make sure
+                 * that the new parent's usecount is correct.  Note: we
+                 * enable the new parent before disabling the old to avoid
+                 * any unnecessary hardware disable->enable transitions.
+                 */
+                if (clk->usecount) {
+                        omap2_clk_enable(new_parent);
+                        omap2_clk_disable(clk->parent);
+                }
+                clk_reparent(clk, new_parent);
+                clk->rate = rate;
+        }
+        omap2_clk_disable(dd->clk_ref);
+        omap2_clk_disable(dd->clk_bypass);
+
+        return 0;
+}
+
+/* DPLL autoidle read/set code */
+
+/**
+ * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
+ * @clk: struct clk * of the DPLL to read
+ *
+ * Return the DPLL's autoidle bits, shifted down to bit 0.  Returns
+ * -EINVAL if passed a null pointer or if the struct clk does not
+ * appear to refer to a DPLL.
+ */
+u32 omap3_dpll_autoidle_read(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        u32 v;
+
+        if (!clk || !clk->dpll_data)
+                return -EINVAL;
+
+        dd = clk->dpll_data;
+
+        v = __raw_readl(dd->autoidle_reg);
+        v &= dd->autoidle_mask;
+        v >>= __ffs(dd->autoidle_mask);
+
+        return v;
+}
+
+/**
+ * omap3_dpll_allow_idle - enable DPLL autoidle bits
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Enable DPLL automatic idle control.  This automatic idle mode
+ * switching takes effect only when the DPLL is locked, at least on
+ * OMAP3430.  The DPLL will enter low-power stop when its downstream
+ * clocks are gated.  No return value.
+ */
+void omap3_dpll_allow_idle(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        u32 v;
+
+        if (!clk || !clk->dpll_data)
+                return;
+
+        dd = clk->dpll_data;
+
+        /*
+         * REVISIT: CORE DPLL can optionally enter low-power bypass
+         * by writing 0x5 instead of 0x1.  Add some mechanism to
+         * optionally enter this mode.
+         */
+        v = __raw_readl(dd->autoidle_reg);
+        v &= ~dd->autoidle_mask;
+        v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
+        __raw_writel(v, dd->autoidle_reg);
+}
+
+/**
+ * omap3_dpll_deny_idle - prevent DPLL from automatically idling
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Disable DPLL automatic idle control.  No return value.
+ */
+void omap3_dpll_deny_idle(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        u32 v;
+
+        if (!clk || !clk->dpll_data)
+                return;
+
+        dd = clk->dpll_data;
+
+        v = __raw_readl(dd->autoidle_reg);
+        v &= ~dd->autoidle_mask;
+        v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
+        __raw_writel(v, dd->autoidle_reg);
+
+}
+
+/* Clock control for DPLL outputs */
+
+/**
+ * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
+ * @clk: DPLL output struct clk
+ *
+ * Using parent clock DPLL data, look up DPLL state.  If locked, set our
+ * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
+ */
+unsigned long omap3_clkoutx2_recalc(struct clk *clk)
+{
+        const struct dpll_data *dd;
+        unsigned long rate;
+        u32 v;
+        struct clk *pclk;
+
+        /* Walk up the parents of clk, looking for a DPLL */
+        pclk = clk->parent;
+        while (pclk && !pclk->dpll_data)
+                pclk = pclk->parent;
+
+        /* clk does not have a DPLL as a parent? */
+        WARN_ON(!pclk);
+
+        dd = pclk->dpll_data;
+
+        WARN_ON(!dd->enable_mask);
+
+        v = __raw_readl(dd->control_reg) & dd->enable_mask;
+        v >>= __ffs(dd->enable_mask);
+        if (v != OMAP3XXX_EN_DPLL_LOCKED)
+                rate = clk->parent->rate;
+        else
+                rate = clk->parent->rate * 2;
+        return rate;
+}
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 6083e21b3be6..877c6f5807b7 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -33,17 +33,19 @@ static struct resource gpmc_smc91x_resources[] = {
 };
 
 static struct smc91x_platdata gpmc_smc91x_info = {
-        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
 };
 
 static struct platform_device gpmc_smc91x_device = {
         .name           = "smc91x",
         .id             = -1,
-        .num_resources  = ARRAY_SIZE(gpmc_smc91x_resources),
-        .resource       = gpmc_smc91x_resources,
         .dev            = {
                 .platform_data = &gpmc_smc91x_info,
         },
+        .num_resources  = ARRAY_SIZE(gpmc_smc91x_resources),
+        .resource       = gpmc_smc91x_resources,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index e86f5ca180ea..bd8cb5974726 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -517,7 +517,7 @@ void __init gpmc_init(void)
                 ck = "gpmc_fck";
                 l = OMAP34XX_GPMC_BASE;
         } else if (cpu_is_omap44xx()) {
-                ck = "gpmc_fck";
+                ck = "gpmc_ck";
                 l = OMAP44XX_GPMC_BASE;
         }
 
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
new file mode 100644
index 000000000000..789ca8c02f0c
--- /dev/null
+++ b/arch/arm/mach-omap2/i2c.c
@@ -0,0 +1,56 @@
+/*
+ * Helper module for board specific I2C bus registration
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <plat/cpu.h>
+#include <plat/i2c.h>
+#include <plat/mux.h>
+
+#include "mux.h"
+
+int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
+                          struct i2c_board_info const *info,
+                          unsigned len)
+{
+        if (cpu_is_omap24xx()) {
+                const int omap24xx_pins[][2] = {
+                        { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
+                        { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
+                };
+                int scl, sda;
+
+                scl = omap24xx_pins[bus_id - 1][0];
+                sda = omap24xx_pins[bus_id - 1][1];
+                omap_cfg_reg(sda);
+                omap_cfg_reg(scl);
+        }
+
+        /* First I2C bus is not muxable */
+        if (cpu_is_omap34xx() && bus_id > 1) {
+                char mux_name[sizeof("i2c2_scl.i2c2_scl")];
+
+                sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
+                omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
+                sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
+                omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
+        }
+
+        return omap_plat_register_i2c_bus(bus_id, clkrate, info, len);
+}
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index f48a4b2654dd..a091b53657b9 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -246,6 +246,31 @@ void __init omap3_check_revision(void)
         }
 }
 
+void __init omap4_check_revision(void)
+{
+        u32 idcode;
+        u16 hawkeye;
+        u8 rev;
+        char *rev_name = "ES1.0";
+
+        /*
+         * The IC rev detection is done with hawkeye and rev.
+         * Note that rev does not map directly to defined processor
+         * revision numbers as ES1.0 uses value 0.
+         */
+        idcode = read_tap_reg(OMAP_TAP_IDCODE);
+        hawkeye = (idcode >> 12) & 0xffff;
+        rev = (idcode >> 28) & 0xff;
+
+        if ((hawkeye == 0xb852) && (rev == 0x0)) {
+                omap_revision = OMAP4430_REV_ES1_0;
+                pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
+                return;
+        }
+
+        pr_err("Unknown OMAP4 CPU id\n");
+}
+
 #define OMAP3_SHOW_FEATURE(feat)                \
         if (omap3_has_ ##feat())                \
                 printk(#feat" ");
@@ -277,10 +302,10 @@ void __init omap3_cpuinfo(void)
         } else if (omap3_has_iva() && omap3_has_sgx()) {
                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
                 strcpy(cpu_name, "OMAP3430/3530");
-        } else if (omap3_has_sgx()) {
+        } else if (omap3_has_iva()) {
                 omap_revision = OMAP3525_REV(rev);
                 strcpy(cpu_name, "OMAP3525");
-        } else if (omap3_has_iva()) {
+        } else if (omap3_has_sgx()) {
                 omap_revision = OMAP3515_REV(rev);
                 strcpy(cpu_name, "OMAP3515");
         } else {
@@ -336,7 +361,7 @@ void __init omap2_check_revision(void)
                 omap3_check_features();
                 omap3_cpuinfo();
         } else if (cpu_is_omap44xx()) {
-                printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
+                omap4_check_revision();
                 return;
         } else {
                 pr_err("OMAP revision unknown, please fix!\n");
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 6a4d8e468703..a8749e8017b9 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -33,9 +33,9 @@
 #include <plat/sdrc.h>
 #include <plat/gpmc.h>
 #include <plat/serial.h>
+#include <plat/mux.h>
 #include <plat/vram.h>
 
-#ifndef CONFIG_ARCH_OMAP4       /* FIXME: Remove this once clkdev is ready */
 #include "clock.h"
 
 #include <plat/omap-pm.h>
@@ -44,7 +44,6 @@
 
 #include <plat/clockdomain.h>
 #include "clockdomains.h"
-#endif
 #include <plat/omap_hwmod.h>
 #include "omap_hwmod_2420.h"
 #include "omap_hwmod_2430.h"
@@ -321,8 +320,8 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
         omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
         pwrdm_init(powerdomains_omap);
         clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
-        omap2_clk_init();
 #endif
+        omap2_clk_init();
         omap_serial_early_init();
 #ifndef CONFIG_ARCH_OMAP4
         omap_hwmod_late_init();
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index c18a94eca641..e071b3fd1878 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -27,19 +27,52 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/ctype.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
 
 #include <asm/system.h>
 
 #include <plat/control.h>
 #include <plat/mux.h>
 
-#ifdef CONFIG_OMAP_MUX
+#include "mux.h"
+
+#define OMAP_MUX_BASE_OFFSET            0x30    /* Offset from CTRL_BASE */
+#define OMAP_MUX_BASE_SZ                0x5ca
+
+struct omap_mux_entry {
+        struct omap_mux         mux;
+        struct list_head        node;
+};
+
+static unsigned long mux_phys;
+static void __iomem *mux_base;
+
+static inline u16 omap_mux_read(u16 reg)
+{
+        if (cpu_is_omap24xx())
+                return __raw_readb(mux_base + reg);
+        else
+                return __raw_readw(mux_base + reg);
+}
+
+static inline void omap_mux_write(u16 val, u16 reg)
+{
+        if (cpu_is_omap24xx())
+                __raw_writeb(val, mux_base + reg);
+        else
+                __raw_writew(val, mux_base + reg);
+}
+
+#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX)
 
 static struct omap_mux_cfg arch_mux_cfg;
 
 /* NOTE: See mux.h for the enumeration */
 
-#ifdef CONFIG_ARCH_OMAP24XX
 static struct pin_config __initdata_or_module omap24xx_pins[] = {
 /*
  *      description                     mux     mux     pull    pull    debug
@@ -249,342 +282,14 @@ MUX_CFG_24XX("AF19_2430_GPIO_85",	0x0113,	3,	0,	0,	1)
 
 #define OMAP24XX_PINS_SZ        ARRAY_SIZE(omap24xx_pins)
 
-#else
-#define omap24xx_pins           NULL
-#define OMAP24XX_PINS_SZ        0
-#endif  /* CONFIG_ARCH_OMAP24XX */
-
-#ifdef CONFIG_ARCH_OMAP34XX
-static struct pin_config __initdata_or_module omap34xx_pins[] = {
-/*
- *              Name, reg-offset,
- *              mux-mode | [active-mode | off-mode]
- */
-
-/* 34xx I2C */
-MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-
-/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
-MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-
-/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
-MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
-
-/* TLL - HSUSB: 12-pin TLL Port 1*/
-MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-
-/* TLL - HSUSB: 12-pin TLL Port 2*/
-MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
-
-/* TLL - HSUSB: 12-pin TLL Port 3*/
-MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-
-/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
-MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
-
-/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
-MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de,
-                OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
-
-/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
-MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
-                OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
-
-
-/* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix.
- * (Always specify PIN_INPUT, except for names suffixed by "_OUT".)
- * No internal pullup/pulldown without "_UP" or "_DOWN" suffix.
- */
-MUX_CFG_34XX("AF26_34XX_GPIO0", 0x1e0,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("AF22_34XX_GPIO9", 0xa18,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("AG9_34XX_GPIO23", 0x5ee,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("U8_34XX_GPIO54_OUT", 0x0b4,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("U8_34XX_GPIO54_DOWN", 0x0b4,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN)
-MUX_CFG_34XX("L8_34XX_GPIO63", 0x0ce,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("G25_34XX_GPIO86_OUT", 0x0fc,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AG4_34XX_GPIO134_OUT", 0x160,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AF4_34XX_GPIO135_OUT", 0x162,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AE4_34XX_GPIO136_OUT", 0x164,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("AF6_34XX_GPIO140_UP", 0x16c,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AE6_34XX_GPIO141", 0x16e,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("AF5_34XX_GPIO142", 0x170,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("AE5_34XX_GPIO143", 0x172,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
-                OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
-
-/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
-MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
-MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
-
-/* MMC1 */
-MUX_CFG_34XX("N28_3430_MMC1_CLK", 0x144,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("M27_3430_MMC1_CMD", 0x146,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("N27_3430_MMC1_DAT0", 0x148,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("N26_3430_MMC1_DAT1", 0x14a,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("N25_3430_MMC1_DAT2", 0x14c,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("P28_3430_MMC1_DAT3", 0x14e,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("P27_3430_MMC1_DAT4", 0x150,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("P26_3430_MMC1_DAT5", 0x152,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("R27_3430_MMC1_DAT6", 0x154,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("R25_3430_MMC1_DAT7", 0x156,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-
-/* MMC2 */
-MUX_CFG_34XX("AE2_3430_MMC2_CLK", 0x158,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AG5_3430_MMC2_CMD", 0x15A,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AH5_3430_MMC2_DAT0", 0x15c,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AH4_3430_MMC2_DAT1", 0x15e,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AG4_3430_MMC2_DAT2", 0x160,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF4_3430_MMC2_DAT3", 0x162,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AE4_3430_MMC2_DAT4", 0x164,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AH3_3430_MMC2_DAT5", 0x166,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF3_3430_MMC2_DAT6", 0x168,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AE3_3430_MMC2_DAT7", 0x16A,
-                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
-
-/* MMC3 */
-MUX_CFG_34XX("AF10_3430_MMC3_CLK", 0x5d8,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AC3_3430_MMC3_CMD", 0x1d0,
-                OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AE11_3430_MMC3_DAT0", 0x5e4,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AH9_3430_MMC3_DAT1", 0x5e6,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF13_3430_MMC3_DAT2", 0x5e8,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF13_3430_MMC3_DAT3", 0x5e2,
-                OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
-
-/* SYS_NIRQ T2 INT1 */
-MUX_CFG_34XX("AF26_34XX_SYS_NIRQ", 0x1E0,
-                OMAP3_WAKEUP_EN | OMAP34XX_PIN_INPUT_PULLUP |
-                OMAP34XX_MUX_MODE0)
-/* EHCI GPIO's on OMAP3EVM (Rev >= E) */
-MUX_CFG_34XX("AH14_34XX_GPIO21", 0x5ea,
-        OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("AF9_34XX_GPIO22", 0x5ec,
-        OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
-MUX_CFG_34XX("U3_34XX_GPIO61", 0x0c8,
-        OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
-};
-
-#define OMAP34XX_PINS_SZ        ARRAY_SIZE(omap34xx_pins)
-
-#else
-#define omap34xx_pins           NULL
-#define OMAP34XX_PINS_SZ        0
-#endif  /* CONFIG_ARCH_OMAP34XX */
-
 #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
+
 static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
 {
         u16 orig;
         u8 warn = 0, debug = 0;
 
-        if (cpu_is_omap24xx())
-                orig = omap_ctrl_readb(cfg->mux_reg);
-        else
-                orig = omap_ctrl_readw(cfg->mux_reg);
+        orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
 
 #ifdef  CONFIG_OMAP_MUX_DEBUG
         debug = cfg->debug;
@@ -600,7 +305,6 @@ static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 r
 #define omap2_cfg_debug(x, y)   do {} while (0)
 #endif
 
-#ifdef CONFIG_ARCH_OMAP24XX
 static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
 {
         static DEFINE_SPINLOCK(mux_spin_lock);
@@ -614,47 +318,692 @@ static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
         if (cfg->pu_pd_val)
                 reg |= OMAP2_PULL_UP;
         omap2_cfg_debug(cfg, reg);
-        omap_ctrl_writeb(reg, cfg->mux_reg);
+        omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
         spin_unlock_irqrestore(&mux_spin_lock, flags);
 
         return 0;
 }
+
+int __init omap2_mux_init(void)
+{
+        u32 mux_pbase;
+
+        if (cpu_is_omap2420())
+                mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
+        else if (cpu_is_omap2430())
+                mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
+        else
+                return -ENODEV;
+
+        mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ);
+        if (!mux_base) {
+                printk(KERN_ERR "mux: Could not ioremap\n");
+                return -ENODEV;
+        }
+
+        if (cpu_is_omap24xx()) {
+                arch_mux_cfg.pins       = omap24xx_pins;
+                arch_mux_cfg.size       = OMAP24XX_PINS_SZ;
+                arch_mux_cfg.cfg_reg    = omap24xx_cfg_reg;
+
+                return omap_mux_register(&arch_mux_cfg);
+        }
+
+        return 0;
+}
+
 #else
-#define omap24xx_cfg_reg        NULL
-#endif
+int __init omap2_mux_init(void)
+{
+        return 0;
+}
+#endif  /* CONFIG_OMAP_MUX */
+
+/*----------------------------------------------------------------------------*/
 
 #ifdef CONFIG_ARCH_OMAP34XX
-static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
+static LIST_HEAD(muxmodes);
+static DEFINE_MUTEX(muxmode_mutex);
+
+#ifdef CONFIG_OMAP_MUX
+
+static char *omap_mux_options;
+
+int __init omap_mux_init_gpio(int gpio, int val)
 {
-        static DEFINE_SPINLOCK(mux_spin_lock);
-        unsigned long flags;
-        u16 reg = 0;
+        struct omap_mux_entry *e;
+        int found = 0;
+
+        if (!gpio)
+                return -EINVAL;
+
+        list_for_each_entry(e, &muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+                if (gpio == m->gpio) {
+                        u16 old_mode;
+                        u16 mux_mode;
+
+                        old_mode = omap_mux_read(m->reg_offset);
+                        mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
+                        mux_mode |= OMAP_MUX_MODE4;
+                        printk(KERN_DEBUG "mux: Setting signal "
+                                "%s.gpio%i 0x%04x -> 0x%04x\n",
+                                m->muxnames[0], gpio, old_mode, mux_mode);
+                        omap_mux_write(mux_mode, m->reg_offset);
+                        found++;
+                }
+        }
 
-        spin_lock_irqsave(&mux_spin_lock, flags);
-        reg |= cfg->mux_val;
-        omap2_cfg_debug(cfg, reg);
-        omap_ctrl_writew(reg, cfg->mux_reg);
-        spin_unlock_irqrestore(&mux_spin_lock, flags);
+        if (found == 1)
+                return 0;
+
+        if (found > 1) {
+                printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio);
+                return -EINVAL;
+        }
+
+        printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
+
+        return -ENODEV;
+}
+
+int __init omap_mux_init_signal(char *muxname, int val)
+{
+        struct omap_mux_entry *e;
+        char *m0_name = NULL, *mode_name = NULL;
+        int found = 0;
+
+        mode_name = strchr(muxname, '.');
+        if (mode_name) {
+                *mode_name = '\0';
+                mode_name++;
+                m0_name = muxname;
+        } else {
+                mode_name = muxname;
+        }
+
+        list_for_each_entry(e, &muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+                char *m0_entry = m->muxnames[0];
+                int i;
+
+                if (m0_name && strcmp(m0_name, m0_entry))
+                        continue;
+
+                for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
+                        char *mode_cur = m->muxnames[i];
+
+                        if (!mode_cur)
+                                continue;
+
+                        if (!strcmp(mode_name, mode_cur)) {
+                                u16 old_mode;
+                                u16 mux_mode;
+
+                                old_mode = omap_mux_read(m->reg_offset);
+                                mux_mode = val | i;
+                                printk(KERN_DEBUG "mux: Setting signal "
+                                        "%s.%s 0x%04x -> 0x%04x\n",
+                                        m0_entry, muxname, old_mode, mux_mode);
+                                omap_mux_write(mux_mode, m->reg_offset);
+                                found++;
+                        }
+                }
+        }
+
+        if (found == 1)
+                return 0;
+
+        if (found > 1) {
+                printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n",
+                                found, muxname);
+                return -EINVAL;
+        }
+
+        printk(KERN_ERR "mux: Could not set signal %s\n", muxname);
+
+        return -ENODEV;
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+#define OMAP_MUX_MAX_NR_FLAGS   10
+#define OMAP_MUX_TEST_FLAG(val, mask)                           \
+        if (((val) & (mask)) == (mask)) {                       \
+                i++;                                            \
+                flags[i] =  #mask;                              \
+        }
+
+/* REVISIT: Add checking for non-optimal mux settings */
+static inline void omap_mux_decode(struct seq_file *s, u16 val)
+{
+        char *flags[OMAP_MUX_MAX_NR_FLAGS];
+        char mode[14];
+        int i = -1;
+
+        sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
+        i++;
+        flags[i] = mode;
+
+        OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
+        if (val & OMAP_OFF_EN) {
+                if (!(val & OMAP_OFFOUT_EN)) {
+                        if (!(val & OMAP_OFF_PULL_UP)) {
+                                OMAP_MUX_TEST_FLAG(val,
+                                        OMAP_PIN_OFF_INPUT_PULLDOWN);
+                        } else {
+                                OMAP_MUX_TEST_FLAG(val,
+                                        OMAP_PIN_OFF_INPUT_PULLUP);
+                        }
+                } else {
+                        if (!(val & OMAP_OFFOUT_VAL)) {
+                                OMAP_MUX_TEST_FLAG(val,
+                                        OMAP_PIN_OFF_OUTPUT_LOW);
+                        } else {
+                                OMAP_MUX_TEST_FLAG(val,
+                                        OMAP_PIN_OFF_OUTPUT_HIGH);
+                        }
+                }
+        }
+
+        if (val & OMAP_INPUT_EN) {
+                if (val & OMAP_PULL_ENA) {
+                        if (!(val & OMAP_PULL_UP)) {
+                                OMAP_MUX_TEST_FLAG(val,
+                                        OMAP_PIN_INPUT_PULLDOWN);
+                        } else {
+                                OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
+                        }
+                } else {
+                        OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
+                }
+        } else {
+                i++;
+                flags[i] = "OMAP_PIN_OUTPUT";
+        }
+
+        do {
+                seq_printf(s, "%s", flags[i]);
+                if (i > 0)
+                        seq_printf(s, " | ");
+        } while (i-- > 0);
+}
+
+#define OMAP_MUX_DEFNAME_LEN    16
+
+static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
+{
+        struct omap_mux_entry *e;
+
+        list_for_each_entry(e, &muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+                char m0_def[OMAP_MUX_DEFNAME_LEN];
+                char *m0_name = m->muxnames[0];
+                u16 val;
+                int i, mode;
+
+                if (!m0_name)
+                        continue;
+
+                for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
+                        if (m0_name[i] == '\0') {
+                                m0_def[i] = m0_name[i];
+                                break;
+                        }
+                        m0_def[i] = toupper(m0_name[i]);
+                }
+                val = omap_mux_read(m->reg_offset);
+                mode = val & OMAP_MUX_MODE7;
+
+                seq_printf(s, "OMAP%i_MUX(%s, ",
+                                        cpu_is_omap34xx() ? 3 : 0, m0_def);
+                omap_mux_decode(s, val);
+                seq_printf(s, "),\n");
+        }
+
+        return 0;
+}
+
+static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, omap_mux_dbg_board_show, &inode->i_private);
+}
+
+static const struct file_operations omap_mux_dbg_board_fops = {
+        .open           = omap_mux_dbg_board_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
+{
+        struct omap_mux *m = s->private;
+        const char *none = "NA";
+        u16 val;
+        int mode;
+
+        val = omap_mux_read(m->reg_offset);
+        mode = val & OMAP_MUX_MODE7;
+
+        seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n",
+                        m->muxnames[0], m->muxnames[mode],
+                        mux_phys + m->reg_offset, m->reg_offset, val,
+                        m->balls[0] ? m->balls[0] : none,
+                        m->balls[1] ? m->balls[1] : none);
+        seq_printf(s, "mode: ");
+        omap_mux_decode(s, val);
+        seq_printf(s, "\n");
+        seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
+                        m->muxnames[0] ? m->muxnames[0] : none,
+                        m->muxnames[1] ? m->muxnames[1] : none,
+                        m->muxnames[2] ? m->muxnames[2] : none,
+                        m->muxnames[3] ? m->muxnames[3] : none,
+                        m->muxnames[4] ? m->muxnames[4] : none,
+                        m->muxnames[5] ? m->muxnames[5] : none,
+                        m->muxnames[6] ? m->muxnames[6] : none,
+                        m->muxnames[7] ? m->muxnames[7] : none);
 
         return 0;
 }
+
+#define OMAP_MUX_MAX_ARG_CHAR  7
+
+static ssize_t omap_mux_dbg_signal_write(struct file *file,
+                                                const char __user *user_buf,
+                                                size_t count, loff_t *ppos)
+{
+        char buf[OMAP_MUX_MAX_ARG_CHAR];
+        struct seq_file *seqf;
+        struct omap_mux *m;
+        unsigned long val;
+        int buf_size, ret;
+
+        if (count > OMAP_MUX_MAX_ARG_CHAR)
+                return -EINVAL;
+
+        memset(buf, 0, sizeof(buf));
+        buf_size = min(count, sizeof(buf) - 1);
+
+        if (copy_from_user(buf, user_buf, buf_size))
+                return -EFAULT;
+
+        ret = strict_strtoul(buf, 0x10, &val);
+        if (ret < 0)
+                return ret;
+
+        if (val > 0xffff)
+                return -EINVAL;
+
+        seqf = file->private_data;
+        m = seqf->private;
+
+        omap_mux_write((u16)val, m->reg_offset);
+        *ppos += count;
+
+        return count;
+}
+
+static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
+}
+
+static const struct file_operations omap_mux_dbg_signal_fops = {
+        .open           = omap_mux_dbg_signal_open,
+        .read           = seq_read,
+        .write          = omap_mux_dbg_signal_write,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static struct dentry *mux_dbg_dir;
+
+static void __init omap_mux_dbg_init(void)
+{
+        struct omap_mux_entry *e;
+
+        mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
+        if (!mux_dbg_dir)
+                return;
+
+        (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir,
+                                        NULL, &omap_mux_dbg_board_fops);
+
+        list_for_each_entry(e, &muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+
+                (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
+                                        m, &omap_mux_dbg_signal_fops);
+        }
+}
+
 #else
-#define omap34xx_cfg_reg        NULL
+static inline void omap_mux_dbg_init(void)
+{
+}
+#endif  /* CONFIG_DEBUG_FS */
+
+static void __init omap_mux_free_names(struct omap_mux *m)
+{
+        int i;
+
+        for (i = 0; i < OMAP_MUX_NR_MODES; i++)
+                kfree(m->muxnames[i]);
+
+#ifdef CONFIG_DEBUG_FS
+        for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
+                kfree(m->balls[i]);
 #endif
 
-int __init omap2_mux_init(void)
+}
+
+/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
+static int __init omap_mux_late_init(void)
 {
-        if (cpu_is_omap24xx()) {
-                arch_mux_cfg.pins       = omap24xx_pins;
-                arch_mux_cfg.size       = OMAP24XX_PINS_SZ;
-                arch_mux_cfg.cfg_reg    = omap24xx_cfg_reg;
-        } else if (cpu_is_omap34xx()) {
-                arch_mux_cfg.pins       = omap34xx_pins;
-                arch_mux_cfg.size       = OMAP34XX_PINS_SZ;
-                arch_mux_cfg.cfg_reg    = omap34xx_cfg_reg;
+        struct omap_mux_entry *e, *tmp;
+
+        list_for_each_entry_safe(e, tmp, &muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+                u16 mode = omap_mux_read(m->reg_offset);
+
+                if (OMAP_MODE_GPIO(mode))
+                        continue;
+
+#ifndef CONFIG_DEBUG_FS
+                mutex_lock(&muxmode_mutex);
+                list_del(&e->node);
+                mutex_unlock(&muxmode_mutex);
+                omap_mux_free_names(m);
+                kfree(m);
+#endif
+
+        }
+
+        omap_mux_dbg_init();
+
+        return 0;
+}
+late_initcall(omap_mux_late_init);
+
+static void __init omap_mux_package_fixup(struct omap_mux *p,
+                                        struct omap_mux *superset)
+{
+        while (p->reg_offset !=  OMAP_MUX_TERMINATOR) {
+                struct omap_mux *s = superset;
+                int found = 0;
+
+                while (s->reg_offset != OMAP_MUX_TERMINATOR) {
+                        if (s->reg_offset == p->reg_offset) {
+                                *s = *p;
+                                found++;
+                                break;
+                        }
+                        s++;
+                }
+                if (!found)
+                        printk(KERN_ERR "mux: Unknown entry offset 0x%x\n",
+                                        p->reg_offset);
+                p++;
+        }
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+static void __init omap_mux_package_init_balls(struct omap_ball *b,
+                                struct omap_mux *superset)
+{
+        while (b->reg_offset != OMAP_MUX_TERMINATOR) {
+                struct omap_mux *s = superset;
+                int found = 0;
+
+                while (s->reg_offset != OMAP_MUX_TERMINATOR) {
+                        if (s->reg_offset == b->reg_offset) {
+                                s->balls[0] = b->balls[0];
+                                s->balls[1] = b->balls[1];
+                                found++;
+                                break;
+                        }
+                        s++;
+                }
+                if (!found)
+                        printk(KERN_ERR "mux: Unknown ball offset 0x%x\n",
+                                        b->reg_offset);
+                b++;
+        }
+}
+
+#else   /* CONFIG_DEBUG_FS */
+
+static inline void omap_mux_package_init_balls(struct omap_ball *b,
+                                        struct omap_mux *superset)
+{
+}
+
+#endif  /* CONFIG_DEBUG_FS */
+
+static int __init omap_mux_setup(char *options)
+{
+        if (!options)
+                return 0;
+
+        omap_mux_options = options;
+
+        return 1;
+}
+__setup("omap_mux=", omap_mux_setup);
+
+/*
+ * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
+ * cmdline options only override the bootloader values.
+ * During development, please enable CONFIG_DEBUG_FS, and use the
+ * signal specific entries under debugfs.
+ */
+static void __init omap_mux_set_cmdline_signals(void)
+{
+        char *options, *next_opt, *token;
+
+        if (!omap_mux_options)
+                return;
+
+        options = kmalloc(strlen(omap_mux_options) + 1, GFP_KERNEL);
+        if (!options)
+                return;
+
+        strcpy(options, omap_mux_options);
+        next_opt = options;
+
+        while ((token = strsep(&next_opt, ",")) != NULL) {
+                char *keyval, *name;
+                unsigned long val;
+
+                keyval = token;
+                name = strsep(&keyval, "=");
+                if (name) {
+                        int res;
+
+                        res = strict_strtoul(keyval, 0x10, &val);
+                        if (res < 0)
+                                continue;
+
+                        omap_mux_init_signal(name, (u16)val);
+                }
+        }
+
+        kfree(options);
+}
+
+static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux)
+{
+        while (board_mux->reg_offset !=  OMAP_MUX_TERMINATOR) {
+                omap_mux_write(board_mux->value, board_mux->reg_offset);
+                board_mux++;
+        }
+}
+
+static int __init omap_mux_copy_names(struct omap_mux *src,
+                                        struct omap_mux *dst)
+{
+        int i;
+
+        for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
+                if (src->muxnames[i]) {
+                        dst->muxnames[i] =
+                                kmalloc(strlen(src->muxnames[i]) + 1,
+                                        GFP_KERNEL);
+                        if (!dst->muxnames[i])
+                                goto free;
+                        strcpy(dst->muxnames[i], src->muxnames[i]);
+                }
+        }
+
+#ifdef CONFIG_DEBUG_FS
+        for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
+                if (src->balls[i]) {
+                        dst->balls[i] =
+                                kmalloc(strlen(src->balls[i]) + 1,
+                                        GFP_KERNEL);
+                        if (!dst->balls[i])
+                                goto free;
+                        strcpy(dst->balls[i], src->balls[i]);
+                }
+        }
+#endif
+
+        return 0;
+
+free:
+        omap_mux_free_names(dst);
+        return -ENOMEM;
+
+}
+
+#endif  /* CONFIG_OMAP_MUX */
+
+static u16 omap_mux_get_by_gpio(int gpio)
+{
+        struct omap_mux_entry *e;
+        u16 offset = OMAP_MUX_TERMINATOR;
+
+        list_for_each_entry(e, &muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+                if (m->gpio == gpio) {
+                        offset = m->reg_offset;
+                        break;
+                }
+        }
+
+        return offset;
+}
+
+/* Needed for dynamic muxing of GPIO pins for off-idle */
+u16 omap_mux_get_gpio(int gpio)
+{
+        u16 offset;
+
+        offset = omap_mux_get_by_gpio(gpio);
+        if (offset == OMAP_MUX_TERMINATOR) {
+                printk(KERN_ERR "mux: Could not get gpio%i\n", gpio);
+                return offset;
+        }
+
+        return omap_mux_read(offset);
+}
+
+/* Needed for dynamic muxing of GPIO pins for off-idle */
+void omap_mux_set_gpio(u16 val, int gpio)
+{
+        u16 offset;
+
+        offset = omap_mux_get_by_gpio(gpio);
+        if (offset == OMAP_MUX_TERMINATOR) {
+                printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
+                return;
+        }
+
+        omap_mux_write(val, offset);
+}
+
+static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
+{
+        struct omap_mux_entry *entry;
+        struct omap_mux *m;
+
+        entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
+        if (!entry)
+                return NULL;
+
+        m = &entry->mux;
+        memcpy(m, src, sizeof(struct omap_mux_entry));
+
+#ifdef CONFIG_OMAP_MUX
+        if (omap_mux_copy_names(src, m)) {
+                kfree(entry);
+                return NULL;
         }
+#endif
+
+        mutex_lock(&muxmode_mutex);
+        list_add_tail(&entry->node, &muxmodes);
+        mutex_unlock(&muxmode_mutex);
 
-        return omap_mux_register(&arch_mux_cfg);
+        return m;
 }
 
+/*
+ * Note if CONFIG_OMAP_MUX is not selected, we will only initialize
+ * the GPIO to mux offset mapping that is needed for dynamic muxing
+ * of GPIO pins for off-idle.
+ */
+static void __init omap_mux_init_list(struct omap_mux *superset)
+{
+        while (superset->reg_offset !=  OMAP_MUX_TERMINATOR) {
+                struct omap_mux *entry;
+
+#ifndef CONFIG_OMAP_MUX
+                /* Skip pins that are not muxed as GPIO by bootloader */
+                if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
+                        superset++;
+                        continue;
+                }
 #endif
+
+                entry = omap_mux_list_add(superset);
+                if (!entry) {
+                        printk(KERN_ERR "mux: Could not add entry\n");
+                        return;
+                }
+                superset++;
+        }
+}
+
+int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
+                                struct omap_mux *superset,
+                                struct omap_mux *package_subset,
+                                struct omap_board_mux *board_mux,
+                                struct omap_ball *package_balls)
+{
+        if (mux_base)
+                return -EBUSY;
+
+        mux_phys = mux_pbase;
+        mux_base = ioremap(mux_pbase, mux_size);
+        if (!mux_base) {
+                printk(KERN_ERR "mux: Could not ioremap\n");
+                return -ENODEV;
+        }
+
+#ifdef CONFIG_OMAP_MUX
+        omap_mux_package_fixup(package_subset, superset);
+        omap_mux_package_init_balls(package_balls, superset);
+        omap_mux_set_cmdline_signals();
+        omap_mux_set_board_signals(board_mux);
+#endif
+
+        omap_mux_init_list(superset);
+
+        return 0;
+}
+
+#endif  /* CONFIG_ARCH_OMAP34XX */
+
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
new file mode 100644
index 000000000000..d8b4d5ad2278
--- /dev/null
+++ b/arch/arm/mach-omap2/mux.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "mux34xx.h"
+
+#define OMAP_MUX_TERMINATOR     0xffff
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define OMAP_MUX_MODE0      0
+#define OMAP_MUX_MODE1      1
+#define OMAP_MUX_MODE2      2
+#define OMAP_MUX_MODE3      3
+#define OMAP_MUX_MODE4      4
+#define OMAP_MUX_MODE5      5
+#define OMAP_MUX_MODE6      6
+#define OMAP_MUX_MODE7      7
+
+/* 24xx/34xx mux bit defines */
+#define OMAP_PULL_ENA                   (1 << 3)
+#define OMAP_PULL_UP                    (1 << 4)
+#define OMAP_ALTELECTRICALSEL           (1 << 5)
+
+/* 34xx specific mux bit defines */
+#define OMAP_INPUT_EN                   (1 << 8)
+#define OMAP_OFF_EN                     (1 << 9)
+#define OMAP_OFFOUT_EN                  (1 << 10)
+#define OMAP_OFFOUT_VAL                 (1 << 11)
+#define OMAP_OFF_PULL_EN                (1 << 12)
+#define OMAP_OFF_PULL_UP                (1 << 13)
+#define OMAP_WAKEUP_EN                  (1 << 14)
+
+/* Active pin states */
+#define OMAP_PIN_OUTPUT                 0
+#define OMAP_PIN_INPUT                  OMAP_INPUT_EN
+#define OMAP_PIN_INPUT_PULLUP           (OMAP_PULL_ENA | OMAP_INPUT_EN \
+                                                | OMAP_PULL_UP)
+#define OMAP_PIN_INPUT_PULLDOWN         (OMAP_PULL_ENA | OMAP_INPUT_EN)
+
+/* Off mode states */
+#define OMAP_PIN_OFF_NONE               0
+#define OMAP_PIN_OFF_OUTPUT_HIGH        (OMAP_OFF_EN | OMAP_OFFOUT_EN \
+                                                | OMAP_OFFOUT_VAL)
+#define OMAP_PIN_OFF_OUTPUT_LOW         (OMAP_OFF_EN | OMAP_OFFOUT_EN)
+#define OMAP_PIN_OFF_INPUT_PULLUP       (OMAP_OFF_EN | OMAP_OFF_PULL_EN \
+                                                | OMAP_OFF_PULL_UP)
+#define OMAP_PIN_OFF_INPUT_PULLDOWN     (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
+#define OMAP_PIN_OFF_WAKEUPENABLE       OMAP_WAKEUP_EN
+
+#define OMAP_MODE_GPIO(x)       (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
+
+/* Flags for omap_mux_init */
+#define OMAP_PACKAGE_MASK               0xffff
+#define OMAP_PACKAGE_CBP                4               /* 515-pin 0.40 0.50 */
+#define OMAP_PACKAGE_CUS                3               /* 423-pin 0.65 */
+#define OMAP_PACKAGE_CBB                2               /* 515-pin 0.40 0.50 */
+#define OMAP_PACKAGE_CBC                1               /* 515-pin 0.50 0.65 */
+
+
+#define OMAP_MUX_NR_MODES       8                       /* Available modes */
+#define OMAP_MUX_NR_SIDES       2                       /* Bottom & top */
+
+/**
+ * struct omap_mux - data for omap mux register offset and it's value
+ * @reg_offset: mux register offset from the mux base
+ * @gpio:       GPIO number
+ * @muxnames:   available signal modes for a ball
+ */
+struct omap_mux {
+        u16     reg_offset;
+        u16     gpio;
+#ifdef CONFIG_OMAP_MUX
+        char    *muxnames[OMAP_MUX_NR_MODES];
+#ifdef CONFIG_DEBUG_FS
+        char    *balls[OMAP_MUX_NR_SIDES];
+#endif
+#endif
+};
+
+/**
+ * struct omap_ball - data for balls on omap package
+ * @reg_offset: mux register offset from the mux base
+ * @balls:      available balls on the package
+ */
+struct omap_ball {
+        u16     reg_offset;
+        char    *balls[OMAP_MUX_NR_SIDES];
+};
+
+/**
+ * struct omap_board_mux - data for initializing mux registers
+ * @reg_offset: mux register offset from the mux base
+ * @mux_value:  desired mux value to set
+ */
+struct omap_board_mux {
+        u16     reg_offset;
+        u16     value;
+};
+
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP34XX)
+
+/**
+ * omap_mux_init_gpio - initialize a signal based on the GPIO number
+ * @gpio:               GPIO number
+ * @val:                Options for the mux register value
+ */
+int omap_mux_init_gpio(int gpio, int val);
+
+/**
+ * omap_mux_init_signal - initialize a signal based on the signal name
+ * @muxname:            Mux name in mode0_name.signal_name format
+ * @val:                Options for the mux register value
+ */
+int omap_mux_init_signal(char *muxname, int val);
+
+#else
+
+static inline int omap_mux_init_gpio(int gpio, int val)
+{
+        return 0;
+}
+static inline int omap_mux_init_signal(char *muxname, int val)
+{
+        return 0;
+}
+
+#endif
+
+/**
+ * omap_mux_get_gpio() - get mux register value based on GPIO number
+ * @gpio:               GPIO number
+ *
+ */
+u16 omap_mux_get_gpio(int gpio);
+
+/**
+ * omap_mux_set_gpio() - set mux register value based on GPIO number
+ * @val:                New mux register value
+ * @gpio:               GPIO number
+ *
+ */
+void omap_mux_set_gpio(u16 val, int gpio);
+
+/**
+ * omap3_mux_init() - initialize mux system with board specific set
+ * @board_mux:          Board specific mux table
+ * @flags:              OMAP package type used for the board
+ */
+int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
+
+/**
+ * omap_mux_init - private mux init function, do not call
+ */
+int omap_mux_init(u32 mux_pbase, u32 mux_size,
+                                struct omap_mux *superset,
+                                struct omap_mux *package_subset,
+                                struct omap_board_mux *board_mux,
+                                struct omap_ball *package_balls);
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
new file mode 100644
index 000000000000..68e0a595f9a1
--- /dev/null
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -0,0 +1,2099 @@
+/*
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_OMAP_MUX
+
+#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)          \
+{                                                                       \
+        .reg_offset     = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET),        \
+        .gpio           = (g),                                          \
+        .muxnames       = { m0, m1, m2, m3, m4, m5, m6, m7 },           \
+}
+
+#else
+
+#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)          \
+{                                                                       \
+        .reg_offset     = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET),        \
+        .gpio           = (g),                                          \
+}
+
+#endif
+
+#define _OMAP3_BALLENTRY(M0, bb, bt)                                    \
+{                                                                       \
+        .reg_offset     = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET),        \
+        .balls          = { bb, bt },                                   \
+}
+
+/*
+ * Superset of all mux modes for omap3
+ */
+static struct omap_mux __initdata omap3_muxmodes[] = {
+        _OMAP3_MUXENTRY(CAM_D0, 99,
+                "cam_d0", NULL, NULL, NULL,
+                "gpio_99", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D1, 100,
+                "cam_d1", NULL, NULL, NULL,
+                "gpio_100", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D10, 109,
+                "cam_d10", NULL, NULL, NULL,
+                "gpio_109", "hw_dbg8", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D11, 110,
+                "cam_d11", NULL, NULL, NULL,
+                "gpio_110", "hw_dbg9", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D2, 101,
+                "cam_d2", NULL, NULL, NULL,
+                "gpio_101", "hw_dbg4", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D3, 102,
+                "cam_d3", NULL, NULL, NULL,
+                "gpio_102", "hw_dbg5", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D4, 103,
+                "cam_d4", NULL, NULL, NULL,
+                "gpio_103", "hw_dbg6", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D5, 104,
+                "cam_d5", NULL, NULL, NULL,
+                "gpio_104", "hw_dbg7", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D6, 105,
+                "cam_d6", NULL, NULL, NULL,
+                "gpio_105", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D7, 106,
+                "cam_d7", NULL, NULL, NULL,
+                "gpio_106", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D8, 107,
+                "cam_d8", NULL, NULL, NULL,
+                "gpio_107", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D9, 108,
+                "cam_d9", NULL, NULL, NULL,
+                "gpio_108", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_FLD, 98,
+                "cam_fld", NULL, "cam_global_reset", NULL,
+                "gpio_98", "hw_dbg3", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_HS, 94,
+                "cam_hs", NULL, NULL, NULL,
+                "gpio_94", "hw_dbg0", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_PCLK, 97,
+                "cam_pclk", NULL, NULL, NULL,
+                "gpio_97", "hw_dbg2", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_STROBE, 126,
+                "cam_strobe", NULL, NULL, NULL,
+                "gpio_126", "hw_dbg11", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_VS, 95,
+                "cam_vs", NULL, NULL, NULL,
+                "gpio_95", "hw_dbg1", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_WEN, 167,
+                "cam_wen", NULL, "cam_shutter", NULL,
+                "gpio_167", "hw_dbg10", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_XCLKA, 96,
+                "cam_xclka", NULL, NULL, NULL,
+                "gpio_96", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_XCLKB, 111,
+                "cam_xclkb", NULL, NULL, NULL,
+                "gpio_111", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CSI2_DX0, 112,
+                "csi2_dx0", NULL, NULL, NULL,
+                "gpio_112", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CSI2_DX1, 114,
+                "csi2_dx1", NULL, NULL, NULL,
+                "gpio_114", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CSI2_DY0, 113,
+                "csi2_dy0", NULL, NULL, NULL,
+                "gpio_113", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CSI2_DY1, 115,
+                "csi2_dy1", NULL, NULL, NULL,
+                "gpio_115", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_ACBIAS, 69,
+                "dss_acbias", NULL, NULL, NULL,
+                "gpio_69", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA0, 70,
+                "dss_data0", NULL, "uart1_cts", NULL,
+                "gpio_70", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA1, 71,
+                "dss_data1", NULL, "uart1_rts", NULL,
+                "gpio_71", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA10, 80,
+                "dss_data10", NULL, NULL, NULL,
+                "gpio_80", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA11, 81,
+                "dss_data11", NULL, NULL, NULL,
+                "gpio_81", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA12, 82,
+                "dss_data12", NULL, NULL, NULL,
+                "gpio_82", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA13, 83,
+                "dss_data13", NULL, NULL, NULL,
+                "gpio_83", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA14, 84,
+                "dss_data14", NULL, NULL, NULL,
+                "gpio_84", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA15, 85,
+                "dss_data15", NULL, NULL, NULL,
+                "gpio_85", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA16, 86,
+                "dss_data16", NULL, NULL, NULL,
+                "gpio_86", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA17, 87,
+                "dss_data17", NULL, NULL, NULL,
+                "gpio_87", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA18, 88,
+                "dss_data18", NULL, "mcspi3_clk", "dss_data0",
+                "gpio_88", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA19, 89,
+                "dss_data19", NULL, "mcspi3_simo", "dss_data1",
+                "gpio_89", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA20, 90,
+                "dss_data20", NULL, "mcspi3_somi", "dss_data2",
+                "gpio_90", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA21, 91,
+                "dss_data21", NULL, "mcspi3_cs0", "dss_data3",
+                "gpio_91", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA22, 92,
+                "dss_data22", NULL, "mcspi3_cs1", "dss_data4",
+                "gpio_92", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA23, 93,
+                "dss_data23", NULL, NULL, "dss_data5",
+                "gpio_93", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA2, 72,
+                "dss_data2", NULL, NULL, NULL,
+                "gpio_72", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA3, 73,
+                "dss_data3", NULL, NULL, NULL,
+                "gpio_73", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA4, 74,
+                "dss_data4", NULL, "uart3_rx_irrx", NULL,
+                "gpio_74", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA5, 75,
+                "dss_data5", NULL, "uart3_tx_irtx", NULL,
+                "gpio_75", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA6, 76,
+                "dss_data6", NULL, "uart1_tx", NULL,
+                "gpio_76", "hw_dbg14", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA7, 77,
+                "dss_data7", NULL, "uart1_rx", NULL,
+                "gpio_77", "hw_dbg15", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA8, 78,
+                "dss_data8", NULL, NULL, NULL,
+                "gpio_78", "hw_dbg16", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA9, 79,
+                "dss_data9", NULL, NULL, NULL,
+                "gpio_79", "hw_dbg17", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_HSYNC, 67,
+                "dss_hsync", NULL, NULL, NULL,
+                "gpio_67", "hw_dbg13", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_PCLK, 66,
+                "dss_pclk", NULL, NULL, NULL,
+                "gpio_66", "hw_dbg12", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_VSYNC, 68,
+                "dss_vsync", NULL, NULL, NULL,
+                "gpio_68", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(ETK_CLK, 12,
+                "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
+                "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", "hw_dbg0"),
+        _OMAP3_MUXENTRY(ETK_CTL, 13,
+                "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
+                "gpio_13", NULL, "hsusb1_tll_clk", "hw_dbg1"),
+        _OMAP3_MUXENTRY(ETK_D0, 14,
+                "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
+                "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", "hw_dbg2"),
+        _OMAP3_MUXENTRY(ETK_D1, 15,
+                "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
+                "gpio_15", "mm1_txse0", "hsusb1_tll_data1", "hw_dbg3"),
+        _OMAP3_MUXENTRY(ETK_D10, 24,
+                "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
+                "gpio_24", NULL, "hsusb2_tll_clk", "hw_dbg12"),
+        _OMAP3_MUXENTRY(ETK_D11, 25,
+                "etk_d11", NULL, NULL, "hsusb2_stp",
+                "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", "hw_dbg13"),
+        _OMAP3_MUXENTRY(ETK_D12, 26,
+                "etk_d12", NULL, NULL, "hsusb2_dir",
+                "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
+        _OMAP3_MUXENTRY(ETK_D13, 27,
+                "etk_d13", NULL, NULL, "hsusb2_nxt",
+                "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", "hw_dbg15"),
+        _OMAP3_MUXENTRY(ETK_D14, 28,
+                "etk_d14", NULL, NULL, "hsusb2_data0",
+                "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", "hw_dbg16"),
+        _OMAP3_MUXENTRY(ETK_D15, 29,
+                "etk_d15", NULL, NULL, "hsusb2_data1",
+                "gpio_29", "mm2_txse0", "hsusb2_tll_data1", "hw_dbg17"),
+        _OMAP3_MUXENTRY(ETK_D2, 16,
+                "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
+                "gpio_16", "mm1_txdat", "hsusb1_tll_data2", "hw_dbg4"),
+        _OMAP3_MUXENTRY(ETK_D3, 17,
+                "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
+                "gpio_17", NULL, "hsusb1_tll_data7", "hw_dbg5"),
+        _OMAP3_MUXENTRY(ETK_D4, 18,
+                "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
+                "gpio_18", NULL, "hsusb1_tll_data4", "hw_dbg6"),
+        _OMAP3_MUXENTRY(ETK_D5, 19,
+                "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
+                "gpio_19", NULL, "hsusb1_tll_data5", "hw_dbg7"),
+        _OMAP3_MUXENTRY(ETK_D6, 20,
+                "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
+                "gpio_20", NULL, "hsusb1_tll_data6", "hw_dbg8"),
+        _OMAP3_MUXENTRY(ETK_D7, 21,
+                "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
+                "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", "hw_dbg9"),
+        _OMAP3_MUXENTRY(ETK_D8, 22,
+                "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
+                "gpio_22", NULL, "hsusb1_tll_dir", "hw_dbg10"),
+        _OMAP3_MUXENTRY(ETK_D9, 23,
+                "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
+                "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", "hw_dbg11"),
+        _OMAP3_MUXENTRY(GPMC_A1, 34,
+                "gpmc_a1", NULL, NULL, NULL,
+                "gpio_34", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A10, 43,
+                "gpmc_a10", "sys_ndmareq3", NULL, NULL,
+                "gpio_43", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A2, 35,
+                "gpmc_a2", NULL, NULL, NULL,
+                "gpio_35", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A3, 36,
+                "gpmc_a3", NULL, NULL, NULL,
+                "gpio_36", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A4, 37,
+                "gpmc_a4", NULL, NULL, NULL,
+                "gpio_37", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A5, 38,
+                "gpmc_a5", NULL, NULL, NULL,
+                "gpio_38", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A6, 39,
+                "gpmc_a6", NULL, NULL, NULL,
+                "gpio_39", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A7, 40,
+                "gpmc_a7", NULL, NULL, NULL,
+                "gpio_40", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A8, 41,
+                "gpmc_a8", NULL, NULL, NULL,
+                "gpio_41", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_A9, 42,
+                "gpmc_a9", "sys_ndmareq2", NULL, NULL,
+                "gpio_42", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_CLK, 59,
+                "gpmc_clk", NULL, NULL, NULL,
+                "gpio_59", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D10, 46,
+                "gpmc_d10", NULL, NULL, NULL,
+                "gpio_46", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D11, 47,
+                "gpmc_d11", NULL, NULL, NULL,
+                "gpio_47", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D12, 48,
+                "gpmc_d12", NULL, NULL, NULL,
+                "gpio_48", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D13, 49,
+                "gpmc_d13", NULL, NULL, NULL,
+                "gpio_49", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D14, 50,
+                "gpmc_d14", NULL, NULL, NULL,
+                "gpio_50", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D15, 51,
+                "gpmc_d15", NULL, NULL, NULL,
+                "gpio_51", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D8, 44,
+                "gpmc_d8", NULL, NULL, NULL,
+                "gpio_44", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_D9, 45,
+                "gpmc_d9", NULL, NULL, NULL,
+                "gpio_45", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NBE0_CLE, 60,
+                "gpmc_nbe0_cle", NULL, NULL, NULL,
+                "gpio_60", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NBE1, 61,
+                "gpmc_nbe1", NULL, NULL, NULL,
+                "gpio_61", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS1, 52,
+                "gpmc_ncs1", NULL, NULL, NULL,
+                "gpio_52", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS2, 53,
+                "gpmc_ncs2", NULL, NULL, NULL,
+                "gpio_53", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS3, 54,
+                "gpmc_ncs3", "sys_ndmareq0", NULL, NULL,
+                "gpio_54", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS4, 55,
+                "gpmc_ncs4", "sys_ndmareq1", "mcbsp4_clkx", "gpt9_pwm_evt",
+                "gpio_55", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS5, 56,
+                "gpmc_ncs5", "sys_ndmareq2", "mcbsp4_dr", "gpt10_pwm_evt",
+                "gpio_56", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS6, 57,
+                "gpmc_ncs6", "sys_ndmareq3", "mcbsp4_dx", "gpt11_pwm_evt",
+                "gpio_57", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NCS7, 58,
+                "gpmc_ncs7", "gpmc_io_dir", "mcbsp4_fsx", "gpt8_pwm_evt",
+                "gpio_58", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_NWP, 62,
+                "gpmc_nwp", NULL, NULL, NULL,
+                "gpio_62", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_WAIT1, 63,
+                "gpmc_wait1", NULL, NULL, NULL,
+                "gpio_63", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_WAIT2, 64,
+                "gpmc_wait2", NULL, NULL, NULL,
+                "gpio_64", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_WAIT3, 65,
+                "gpmc_wait3", "sys_ndmareq1", NULL, NULL,
+                "gpio_65", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HDQ_SIO, 170,
+                "hdq_sio", "sys_altclk", "i2c2_sccbe", "i2c3_sccbe",
+                "gpio_170", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_CLK, 120,
+                "hsusb0_clk", NULL, NULL, NULL,
+                "gpio_120", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
+                "hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
+                "gpio_125", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
+                "hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
+                "gpio_130", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
+                "hsusb0_data2", NULL, "uart3_rts_sd", NULL,
+                "gpio_131", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
+                "hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
+                "gpio_169", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA4, 188,
+                "hsusb0_data4", NULL, NULL, NULL,
+                "gpio_188", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA5, 189,
+                "hsusb0_data5", NULL, NULL, NULL,
+                "gpio_189", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA6, 190,
+                "hsusb0_data6", NULL, NULL, NULL,
+                "gpio_190", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA7, 191,
+                "hsusb0_data7", NULL, NULL, NULL,
+                "gpio_191", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DIR, 122,
+                "hsusb0_dir", NULL, NULL, NULL,
+                "gpio_122", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_NXT, 124,
+                "hsusb0_nxt", NULL, NULL, NULL,
+                "gpio_124", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_STP, 121,
+                "hsusb0_stp", NULL, NULL, NULL,
+                "gpio_121", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(I2C2_SCL, 168,
+                "i2c2_scl", NULL, NULL, NULL,
+                "gpio_168", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(I2C2_SDA, 183,
+                "i2c2_sda", NULL, NULL, NULL,
+                "gpio_183", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(I2C3_SCL, 184,
+                "i2c3_scl", NULL, NULL, NULL,
+                "gpio_184", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(I2C3_SDA, 185,
+                "i2c3_sda", NULL, NULL, NULL,
+                "gpio_185", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(I2C4_SCL, 0,
+                "i2c4_scl", "sys_nvmode1", NULL, NULL,
+                NULL, NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(I2C4_SDA, 0,
+                "i2c4_sda", "sys_nvmode2", NULL, NULL,
+                NULL, NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(JTAG_EMU0, 11,
+                "jtag_emu0", NULL, NULL, NULL,
+                "gpio_11", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(JTAG_EMU1, 31,
+                "jtag_emu1", NULL, NULL, NULL,
+                "gpio_31", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
+                "mcbsp1_clkr", "mcspi4_clk", NULL, NULL,
+                "gpio_156", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_CLKX, 162,
+                "mcbsp1_clkx", NULL, "mcbsp3_clkx", NULL,
+                "gpio_162", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_DR, 159,
+                "mcbsp1_dr", "mcspi4_somi", "mcbsp3_dr", NULL,
+                "gpio_159", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_DX, 158,
+                "mcbsp1_dx", "mcspi4_simo", "mcbsp3_dx", NULL,
+                "gpio_158", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_FSR, 157,
+                "mcbsp1_fsr", NULL, "cam_global_reset", NULL,
+                "gpio_157", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_FSX, 161,
+                "mcbsp1_fsx", "mcspi4_cs0", "mcbsp3_fsx", NULL,
+                "gpio_161", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP2_CLKX, 117,
+                "mcbsp2_clkx", NULL, NULL, NULL,
+                "gpio_117", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP2_DR, 118,
+                "mcbsp2_dr", NULL, NULL, NULL,
+                "gpio_118", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP2_DX, 119,
+                "mcbsp2_dx", NULL, NULL, NULL,
+                "gpio_119", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP2_FSX, 116,
+                "mcbsp2_fsx", NULL, NULL, NULL,
+                "gpio_116", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
+                "mcbsp3_clkx", "uart2_tx", NULL, NULL,
+                "gpio_142", "hsusb3_tll_data6", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_DR, 141,
+                "mcbsp3_dr", "uart2_rts", NULL, NULL,
+                "gpio_141", "hsusb3_tll_data5", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_DX, 140,
+                "mcbsp3_dx", "uart2_cts", NULL, NULL,
+                "gpio_140", "hsusb3_tll_data4", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_FSX, 143,
+                "mcbsp3_fsx", "uart2_rx", NULL, NULL,
+                "gpio_143", "hsusb3_tll_data7", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
+                "mcbsp4_clkx", NULL, NULL, NULL,
+                "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_DR, 153,
+                "mcbsp4_dr", NULL, NULL, NULL,
+                "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_DX, 154,
+                "mcbsp4_dx", NULL, NULL, NULL,
+                "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_FSX, 155,
+                "mcbsp4_fsx", NULL, NULL, NULL,
+                "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP_CLKS, 160,
+                "mcbsp_clks", NULL, "cam_shutter", NULL,
+                "gpio_160", "uart1_cts", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_CLK, 171,
+                "mcspi1_clk", "sdmmc2_dat4", NULL, NULL,
+                "gpio_171", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_CS0, 174,
+                "mcspi1_cs0", "sdmmc2_dat7", NULL, NULL,
+                "gpio_174", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_CS1, 175,
+                "mcspi1_cs1", NULL, NULL, "sdmmc3_cmd",
+                "gpio_175", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_CS2, 176,
+                "mcspi1_cs2", NULL, NULL, "sdmmc3_clk",
+                "gpio_176", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_CS3, 177,
+                "mcspi1_cs3", NULL, "hsusb2_tll_data2", "hsusb2_data2",
+                "gpio_177", "mm2_txdat", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_SIMO, 172,
+                "mcspi1_simo", "sdmmc2_dat5", NULL, NULL,
+                "gpio_172", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_SOMI, 173,
+                "mcspi1_somi", "sdmmc2_dat6", NULL, NULL,
+                "gpio_173", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI2_CLK, 178,
+                "mcspi2_clk", NULL, "hsusb2_tll_data7", "hsusb2_data7",
+                "gpio_178", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI2_CS0, 181,
+                "mcspi2_cs0", "gpt11_pwm_evt",
+                "hsusb2_tll_data6", "hsusb2_data6",
+                "gpio_181", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI2_CS1, 182,
+                "mcspi2_cs1", "gpt8_pwm_evt",
+                "hsusb2_tll_data3", "hsusb2_data3",
+                "gpio_182", "mm2_txen_n", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI2_SIMO, 179,
+                "mcspi2_simo", "gpt9_pwm_evt",
+                "hsusb2_tll_data4", "hsusb2_data4",
+                "gpio_179", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI2_SOMI, 180,
+                "mcspi2_somi", "gpt10_pwm_evt",
+                "hsusb2_tll_data5", "hsusb2_data5",
+                "gpio_180", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_CLK, 120,
+                "sdmmc1_clk", NULL, NULL, NULL,
+                "gpio_120", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_CMD, 121,
+                "sdmmc1_cmd", NULL, NULL, NULL,
+                "gpio_121", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
+                "sdmmc1_dat0", NULL, NULL, NULL,
+                "gpio_122", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
+                "sdmmc1_dat1", NULL, NULL, NULL,
+                "gpio_123", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
+                "sdmmc1_dat2", NULL, NULL, NULL,
+                "gpio_124", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
+                "sdmmc1_dat3", NULL, NULL, NULL,
+                "gpio_125", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT4, 126,
+                "sdmmc1_dat4", NULL, "sim_io", NULL,
+                "gpio_126", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT5, 127,
+                "sdmmc1_dat5", NULL, "sim_clk", NULL,
+                "gpio_127", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT6, 128,
+                "sdmmc1_dat6", NULL, "sim_pwrctrl", NULL,
+                "gpio_128", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT7, 129,
+                "sdmmc1_dat7", NULL, "sim_rst", NULL,
+                "gpio_129", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_CLK, 130,
+                "sdmmc2_clk", "mcspi3_clk", NULL, NULL,
+                "gpio_130", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_CMD, 131,
+                "sdmmc2_cmd", "mcspi3_simo", NULL, NULL,
+                "gpio_131", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT0, 132,
+                "sdmmc2_dat0", "mcspi3_somi", NULL, NULL,
+                "gpio_132", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT1, 133,
+                "sdmmc2_dat1", NULL, NULL, NULL,
+                "gpio_133", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT2, 134,
+                "sdmmc2_dat2", "mcspi3_cs1", NULL, NULL,
+                "gpio_134", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT3, 135,
+                "sdmmc2_dat3", "mcspi3_cs0", NULL, NULL,
+                "gpio_135", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT4, 136,
+                "sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, "sdmmc3_dat0",
+                "gpio_136", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
+                "sdmmc2_dat5", "sdmmc2_dir_dat1",
+                "cam_global_reset", "sdmmc3_dat1",
+                "gpio_137", "hsusb3_tll_stp", "mm3_rxdp", "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
+                "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
+                "gpio_138", "hsusb3_tll_dir", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
+                "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
+                "gpio_139", "hsusb3_tll_nxt", "mm3_rxdm", "safe_mode"),
+        _OMAP3_MUXENTRY(SDRC_CKE0, 0,
+                "sdrc_cke0", NULL, NULL, NULL,
+                NULL, NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDRC_CKE1, 0,
+                "sdrc_cke1", NULL, NULL, NULL,
+                NULL, NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT0, 2,
+                "sys_boot0", NULL, NULL, NULL,
+                "gpio_2", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT1, 3,
+                "sys_boot1", NULL, NULL, NULL,
+                "gpio_3", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT2, 4,
+                "sys_boot2", NULL, NULL, NULL,
+                "gpio_4", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT3, 5,
+                "sys_boot3", NULL, NULL, NULL,
+                "gpio_5", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT4, 6,
+                "sys_boot4", "sdmmc2_dir_dat2", NULL, NULL,
+                "gpio_6", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT5, 7,
+                "sys_boot5", "sdmmc2_dir_dat3", NULL, NULL,
+                "gpio_7", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT6, 8,
+                "sys_boot6", NULL, NULL, NULL,
+                "gpio_8", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_CLKOUT1, 10,
+                "sys_clkout1", NULL, NULL, NULL,
+                "gpio_10", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_CLKOUT2, 186,
+                "sys_clkout2", NULL, NULL, NULL,
+                "gpio_186", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_CLKREQ, 1,
+                "sys_clkreq", NULL, NULL, NULL,
+                "gpio_1", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_NIRQ, 0,
+                "sys_nirq", NULL, NULL, NULL,
+                "gpio_0", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_NRESWARM, 30,
+                "sys_nreswarm", NULL, NULL, NULL,
+                "gpio_30", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_OFF_MODE, 9,
+                "sys_off_mode", NULL, NULL, NULL,
+                "gpio_9", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_CTS, 150,
+                "uart1_cts", NULL, NULL, NULL,
+                "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_RTS, 149,
+                "uart1_rts", NULL, NULL, NULL,
+                "gpio_149", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_RX, 151,
+                "uart1_rx", NULL, "mcbsp1_clkr", "mcspi4_clk",
+                "gpio_151", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_TX, 148,
+                "uart1_tx", NULL, NULL, NULL,
+                "gpio_148", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART2_CTS, 144,
+                "uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,
+                "gpio_144", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART2_RTS, 145,
+                "uart2_rts", "mcbsp3_dr", "gpt10_pwm_evt", NULL,
+                "gpio_145", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART2_RX, 147,
+                "uart2_rx", "mcbsp3_fsx", "gpt8_pwm_evt", NULL,
+                "gpio_147", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART2_TX, 146,
+                "uart2_tx", "mcbsp3_clkx", "gpt11_pwm_evt", NULL,
+                "gpio_146", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART3_CTS_RCTX, 163,
+                "uart3_cts_rctx", NULL, NULL, NULL,
+                "gpio_163", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART3_RTS_SD, 164,
+                "uart3_rts_sd", NULL, NULL, NULL,
+                "gpio_164", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART3_RX_IRRX, 165,
+                "uart3_rx_irrx", NULL, NULL, NULL,
+                "gpio_165", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
+                "uart3_tx_irtx", NULL, NULL, NULL,
+                "gpio_166", NULL, NULL, "safe_mode"),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Signals different on CBC package compared to the superset
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC)
+struct omap_mux __initdata omap3_cbc_subset[] = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap3_cbc_subset        NULL
+#endif
+
+/*
+ * Balls for CBC package
+ * 515-pin s-PBGA Package, 0.65mm Ball Pitch (Top), 0.50mm Ball Pitch (Bottom)
+ *
+ * FIXME: What's up with the outdated TI documentation? See:
+ *
+ * http://wiki.davincidsp.com/index.php/Datasheet_Errata_for_OMAP35x_CBC_Package
+ * http://community.ti.com/forums/t/10982.aspx
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)        \
+                && defined(CONFIG_OMAP_PACKAGE_CBC)
+struct omap_ball __initdata omap3_cbc_ball[] = {
+        _OMAP3_BALLENTRY(CAM_D0, "ae16", NULL),
+        _OMAP3_BALLENTRY(CAM_D1, "ae15", NULL),
+        _OMAP3_BALLENTRY(CAM_D10, "d25", NULL),
+        _OMAP3_BALLENTRY(CAM_D11, "e26", NULL),
+        _OMAP3_BALLENTRY(CAM_D2, "a24", NULL),
+        _OMAP3_BALLENTRY(CAM_D3, "b24", NULL),
+        _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
+        _OMAP3_BALLENTRY(CAM_D5, "c24", NULL),
+        _OMAP3_BALLENTRY(CAM_D6, "p25", NULL),
+        _OMAP3_BALLENTRY(CAM_D7, "p26", NULL),
+        _OMAP3_BALLENTRY(CAM_D8, "n25", NULL),
+        _OMAP3_BALLENTRY(CAM_D9, "n26", NULL),
+        _OMAP3_BALLENTRY(CAM_FLD, "b23", NULL),
+        _OMAP3_BALLENTRY(CAM_HS, "c23", NULL),
+        _OMAP3_BALLENTRY(CAM_PCLK, "c26", NULL),
+        _OMAP3_BALLENTRY(CAM_STROBE, "d26", NULL),
+        _OMAP3_BALLENTRY(CAM_VS, "d23", NULL),
+        _OMAP3_BALLENTRY(CAM_WEN, "a23", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKB, "e25", NULL),
+        _OMAP3_BALLENTRY(CSI2_DX0, "ad17", NULL),
+        _OMAP3_BALLENTRY(CSI2_DX1, "ae18", NULL),
+        _OMAP3_BALLENTRY(CSI2_DY0, "ad16", NULL),
+        _OMAP3_BALLENTRY(CSI2_DY1, "ae17", NULL),
+        _OMAP3_BALLENTRY(DSS_ACBIAS, "f26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA0, "ae21", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA1, "ae22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA10, "ac26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA11, "ad26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA12, "aa25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA13, "y25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA14, "aa26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA15, "ab26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA16, "l25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA17, "l26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA18, "m24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA19, "m26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA2, "ae23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA20, "f25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA21, "n24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA22, "ac25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA23, "ab25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA3, "ae24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA4, "ad23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA5, "ad24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA6, "g26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA7, "h25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA8, "h26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA9, "j26", NULL),
+        _OMAP3_BALLENTRY(DSS_HSYNC, "k24", NULL),
+        _OMAP3_BALLENTRY(DSS_PCLK, "g25", NULL),
+        _OMAP3_BALLENTRY(DSS_VSYNC, "m25", NULL),
+        _OMAP3_BALLENTRY(ETK_CLK, "ab2", NULL),
+        _OMAP3_BALLENTRY(ETK_CTL, "ab3", NULL),
+        _OMAP3_BALLENTRY(ETK_D0, "ac3", NULL),
+        _OMAP3_BALLENTRY(ETK_D1, "ad4", NULL),
+        _OMAP3_BALLENTRY(ETK_D10, "ae4", NULL),
+        _OMAP3_BALLENTRY(ETK_D11, "af6", NULL),
+        _OMAP3_BALLENTRY(ETK_D12, "ae6", NULL),
+        _OMAP3_BALLENTRY(ETK_D13, "af7", NULL),
+        _OMAP3_BALLENTRY(ETK_D14, "af9", NULL),
+        _OMAP3_BALLENTRY(ETK_D15, "ae9", NULL),
+        _OMAP3_BALLENTRY(ETK_D2, "ad3", NULL),
+        _OMAP3_BALLENTRY(ETK_D3, "aa3", NULL),
+        _OMAP3_BALLENTRY(ETK_D4, "y3", NULL),
+        _OMAP3_BALLENTRY(ETK_D5, "ab1", NULL),
+        _OMAP3_BALLENTRY(ETK_D6, "ae3", NULL),
+        _OMAP3_BALLENTRY(ETK_D7, "ad2", NULL),
+        _OMAP3_BALLENTRY(ETK_D8, "aa4", NULL),
+        _OMAP3_BALLENTRY(ETK_D9, "v2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A1, "j2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A10, "d2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A2, "h1", NULL),
+        _OMAP3_BALLENTRY(GPMC_A3, "h2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A4, "g2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A5, "f1", NULL),
+        _OMAP3_BALLENTRY(GPMC_A6, "f2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A7, "e1", NULL),
+        _OMAP3_BALLENTRY(GPMC_A8, "e2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A9, "d1", NULL),
+        _OMAP3_BALLENTRY(GPMC_CLK, "n1", "l1"),
+        _OMAP3_BALLENTRY(GPMC_D10, "t1", "n1"),
+        _OMAP3_BALLENTRY(GPMC_D11, "u2", "p2"),
+        _OMAP3_BALLENTRY(GPMC_D12, "u1", "p1"),
+        _OMAP3_BALLENTRY(GPMC_D13, "p1", "m1"),
+        _OMAP3_BALLENTRY(GPMC_D14, "l2", "j2"),
+        _OMAP3_BALLENTRY(GPMC_D15, "m2", "k2"),
+        _OMAP3_BALLENTRY(GPMC_D8, "v1", "r1"),
+        _OMAP3_BALLENTRY(GPMC_D9, "y1", "t1"),
+        _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k2", NULL),
+        _OMAP3_BALLENTRY(GPMC_NBE1, "j1", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS1, "ad1", "w1"),
+        _OMAP3_BALLENTRY(GPMC_NCS2, "a3", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS3, "b6", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS4, "b4", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS5, "c4", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS6, "b5", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS7, "c5", NULL),
+        _OMAP3_BALLENTRY(GPMC_NWP, "ac6", "y5"),
+        _OMAP3_BALLENTRY(GPMC_WAIT1, "ac8", "y8"),
+        _OMAP3_BALLENTRY(GPMC_WAIT2, "b3", NULL),
+        _OMAP3_BALLENTRY(GPMC_WAIT3, "c6", NULL),
+        _OMAP3_BALLENTRY(HDQ_SIO, "j23", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_CLK, "w19", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA0, "v20", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA1, "y20", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA2, "v18", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA3, "w20", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA4, "w17", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA5, "y18", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA6, "y19", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA7, "y17", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DIR, "v19", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_NXT, "w18", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_STP, "u20", NULL),
+        _OMAP3_BALLENTRY(I2C2_SCL, "c2", NULL),
+        _OMAP3_BALLENTRY(I2C2_SDA, "c1", NULL),
+        _OMAP3_BALLENTRY(I2C3_SCL, "ab4", NULL),
+        _OMAP3_BALLENTRY(I2C3_SDA, "ac4", NULL),
+        _OMAP3_BALLENTRY(I2C4_SCL, "ad15", NULL),
+        _OMAP3_BALLENTRY(I2C4_SDA, "w16", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU0, "y15", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU1, "y14", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKR, "u19", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKX, "t17", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DR, "t20", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DX, "u17", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSR, "v17", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSX, "p20", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_CLKX, "r18", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DR, "t18", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DX, "r19", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_FSX, "u18", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_CLKX, "u3", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DR, "n3", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DX, "p3", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_FSX, "w3", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_CLKX, "v3", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_DR, "u4", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_DX, "r3", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_FSX, "t3", NULL),
+        _OMAP3_BALLENTRY(MCBSP_CLKS, "t19", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CLK, "p9", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS0, "r7", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS1, "r8", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS2, "r9", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS3, "t8", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SIMO, "p8", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SOMI, "p7", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CLK, "w7", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS0, "v8", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS1, "v9", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SIMO, "w8", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SOMI, "u8", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CLK, "n19", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CMD, "l18", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT0, "m19", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT1, "m18", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT2, "k18", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT3, "n20", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT4, "m20", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT5, "p17", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT6, "p18", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT7, "p19", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CLK, "w10", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CMD, "r10", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT0, "t10", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT1, "t9", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT2, "u10", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT3, "u9", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT4, "v10", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT5, "m3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT6, "l3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT7, "k3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT0, "f3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT1, "d3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT2, "c3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT3, "e3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT4, "e4", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT5, "g3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT6, "d4", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT1, "ae14", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT2, "w11", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKREQ, "w15", NULL),
+        _OMAP3_BALLENTRY(SYS_NIRQ, "v16", NULL),
+        _OMAP3_BALLENTRY(SYS_NRESWARM, "ad7", "aa5"),
+        _OMAP3_BALLENTRY(SYS_OFF_MODE, "v12", NULL),
+        _OMAP3_BALLENTRY(UART1_CTS, "w2", NULL),
+        _OMAP3_BALLENTRY(UART1_RTS, "r2", NULL),
+        _OMAP3_BALLENTRY(UART1_RX, "h3", NULL),
+        _OMAP3_BALLENTRY(UART1_TX, "l4", NULL),
+        _OMAP3_BALLENTRY(UART2_CTS, "y24", NULL),
+        _OMAP3_BALLENTRY(UART2_RTS, "aa24", NULL),
+        _OMAP3_BALLENTRY(UART2_RX, "ad21", NULL),
+        _OMAP3_BALLENTRY(UART2_TX, "ad22", NULL),
+        _OMAP3_BALLENTRY(UART3_CTS_RCTX, "f23", NULL),
+        _OMAP3_BALLENTRY(UART3_RTS_SD, "f24", NULL),
+        _OMAP3_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
+        _OMAP3_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap3_cbc_ball   NULL
+#endif
+
+/*
+ * Signals different on CUS package compared to superset
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS)
+struct omap_mux __initdata omap3_cus_subset[] = {
+        _OMAP3_MUXENTRY(CAM_D10, 109,
+                "cam_d10", NULL, NULL, NULL,
+                "gpio_109", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D11, 110,
+                "cam_d11", NULL, NULL, NULL,
+                "gpio_110", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D2, 101,
+                "cam_d2", NULL, NULL, NULL,
+                "gpio_101", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D3, 102,
+                "cam_d3", NULL, NULL, NULL,
+                "gpio_102", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D4, 103,
+                "cam_d4", NULL, NULL, NULL,
+                "gpio_103", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D5, 104,
+                "cam_d5", NULL, NULL, NULL,
+                "gpio_104", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_FLD, 98,
+                "cam_fld", NULL, "cam_global_reset", NULL,
+                "gpio_98", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_HS, 94,
+                "cam_hs", NULL, NULL, NULL,
+                "gpio_94", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_PCLK, 97,
+                "cam_pclk", NULL, NULL, NULL,
+                "gpio_97", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_STROBE, 126,
+                "cam_strobe", NULL, NULL, NULL,
+                "gpio_126", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_VS, 95,
+                "cam_vs", NULL, NULL, NULL,
+                "gpio_95", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_WEN, 167,
+                "cam_wen", NULL, "cam_shutter", NULL,
+                "gpio_167", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA6, 76,
+                "dss_data6", NULL, "uart1_tx", NULL,
+                "gpio_76", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA7, 77,
+                "dss_data7", NULL, "uart1_rx", NULL,
+                "gpio_77", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA8, 78,
+                "dss_data8", NULL, NULL, NULL,
+                "gpio_78", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA9, 79,
+                "dss_data9", NULL, NULL, NULL,
+                "gpio_79", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_HSYNC, 67,
+                "dss_hsync", NULL, NULL, NULL,
+                "gpio_67", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_PCLK, 66,
+                "dss_pclk", NULL, NULL, NULL,
+                "gpio_66", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(ETK_CLK, 12,
+                "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
+                "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
+        _OMAP3_MUXENTRY(ETK_CTL, 13,
+                "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
+                "gpio_13", NULL, "hsusb1_tll_clk", NULL),
+        _OMAP3_MUXENTRY(ETK_D0, 14,
+                "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
+                "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
+        _OMAP3_MUXENTRY(ETK_D1, 15,
+                "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
+                "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
+        _OMAP3_MUXENTRY(ETK_D10, 24,
+                "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
+                "gpio_24", NULL, "hsusb2_tll_clk", NULL),
+        _OMAP3_MUXENTRY(ETK_D11, 25,
+                "etk_d11", NULL, NULL, "hsusb2_stp",
+                "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
+        _OMAP3_MUXENTRY(ETK_D12, 26,
+                "etk_d12", NULL, NULL, "hsusb2_dir",
+                "gpio_26", NULL, "hsusb2_tll_dir", NULL),
+        _OMAP3_MUXENTRY(ETK_D13, 27,
+                "etk_d13", NULL, NULL, "hsusb2_nxt",
+                "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
+        _OMAP3_MUXENTRY(ETK_D14, 28,
+                "etk_d14", NULL, NULL, "hsusb2_data0",
+                "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
+        _OMAP3_MUXENTRY(ETK_D15, 29,
+                "etk_d15", NULL, NULL, "hsusb2_data1",
+                "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
+        _OMAP3_MUXENTRY(ETK_D2, 16,
+                "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
+                "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
+        _OMAP3_MUXENTRY(ETK_D3, 17,
+                "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
+                "gpio_17", NULL, "hsusb1_tll_data7", NULL),
+        _OMAP3_MUXENTRY(ETK_D4, 18,
+                "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
+                "gpio_18", NULL, "hsusb1_tll_data4", NULL),
+        _OMAP3_MUXENTRY(ETK_D5, 19,
+                "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
+                "gpio_19", NULL, "hsusb1_tll_data5", NULL),
+        _OMAP3_MUXENTRY(ETK_D6, 20,
+                "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
+                "gpio_20", NULL, "hsusb1_tll_data6", NULL),
+        _OMAP3_MUXENTRY(ETK_D7, 21,
+                "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
+                "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
+        _OMAP3_MUXENTRY(ETK_D8, 22,
+                "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
+                "gpio_22", NULL, "hsusb1_tll_dir", NULL),
+        _OMAP3_MUXENTRY(ETK_D9, 23,
+                "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
+                "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
+        _OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
+                "mcbsp3_clkx", "uart2_tx", NULL, NULL,
+                "gpio_142", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_DR, 141,
+                "mcbsp3_dr", "uart2_rts", NULL, NULL,
+                "gpio_141", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_DX, 140,
+                "mcbsp3_dx", "uart2_cts", NULL, NULL,
+                "gpio_140", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP3_FSX, 143,
+                "mcbsp3_fsx", "uart2_rx", NULL, NULL,
+                "gpio_143", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
+                "sdmmc2_dat5", "sdmmc2_dir_dat1",
+                "cam_global_reset", "sdmmc3_dat1",
+                "gpio_137", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
+                "sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
+                "gpio_138", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
+                "sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
+                "gpio_139", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_CTS, 150,
+                "uart1_cts", NULL, NULL, NULL,
+                "gpio_150", NULL, NULL, "safe_mode"),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap3_cus_subset        NULL
+#endif
+
+/*
+ * Balls for CUS package
+ * 423-pin s-PBGA Package, 0.65mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
+                && defined(CONFIG_OMAP_PACKAGE_CUS)
+struct omap_ball __initdata omap3_cus_ball[] = {
+        _OMAP3_BALLENTRY(CAM_D0, "ab18", NULL),
+        _OMAP3_BALLENTRY(CAM_D1, "ac18", NULL),
+        _OMAP3_BALLENTRY(CAM_D10, "f21", NULL),
+        _OMAP3_BALLENTRY(CAM_D11, "g21", NULL),
+        _OMAP3_BALLENTRY(CAM_D2, "g19", NULL),
+        _OMAP3_BALLENTRY(CAM_D3, "f19", NULL),
+        _OMAP3_BALLENTRY(CAM_D4, "g20", NULL),
+        _OMAP3_BALLENTRY(CAM_D5, "b21", NULL),
+        _OMAP3_BALLENTRY(CAM_D6, "l24", NULL),
+        _OMAP3_BALLENTRY(CAM_D7, "k24", NULL),
+        _OMAP3_BALLENTRY(CAM_D8, "j23", NULL),
+        _OMAP3_BALLENTRY(CAM_D9, "k23", NULL),
+        _OMAP3_BALLENTRY(CAM_FLD, "h24", NULL),
+        _OMAP3_BALLENTRY(CAM_HS, "a22", NULL),
+        _OMAP3_BALLENTRY(CAM_PCLK, "j19", NULL),
+        _OMAP3_BALLENTRY(CAM_STROBE, "j20", NULL),
+        _OMAP3_BALLENTRY(CAM_VS, "e18", NULL),
+        _OMAP3_BALLENTRY(CAM_WEN, "f18", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKA, "b22", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKB, "c22", NULL),
+        _OMAP3_BALLENTRY(DSS_ACBIAS, "j21", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA0, "ac19", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA1, "ab19", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA10, "ac22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA11, "ac23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA12, "ab22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA13, "y22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA14, "w22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA15, "v22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA16, "j22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA17, "g23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA18, "g24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA19, "h23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA2, "ad20", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA20, "d23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA21, "k22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA22, "v21", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA23, "w21", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA3, "ac20", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA4, "ad21", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA5, "ac21", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA6, "d24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA7, "e23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA8, "e24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA9, "f23", NULL),
+        _OMAP3_BALLENTRY(DSS_HSYNC, "e22", NULL),
+        _OMAP3_BALLENTRY(DSS_PCLK, "g22", NULL),
+        _OMAP3_BALLENTRY(DSS_VSYNC, "f22", NULL),
+        _OMAP3_BALLENTRY(ETK_CLK, "ac1", NULL),
+        _OMAP3_BALLENTRY(ETK_CTL, "ad3", NULL),
+        _OMAP3_BALLENTRY(ETK_D0, "ad6", NULL),
+        _OMAP3_BALLENTRY(ETK_D1, "ac6", NULL),
+        _OMAP3_BALLENTRY(ETK_D10, "ac3", NULL),
+        _OMAP3_BALLENTRY(ETK_D11, "ac9", NULL),
+        _OMAP3_BALLENTRY(ETK_D12, "ac10", NULL),
+        _OMAP3_BALLENTRY(ETK_D13, "ad11", NULL),
+        _OMAP3_BALLENTRY(ETK_D14, "ac11", NULL),
+        _OMAP3_BALLENTRY(ETK_D15, "ad12", NULL),
+        _OMAP3_BALLENTRY(ETK_D2, "ac7", NULL),
+        _OMAP3_BALLENTRY(ETK_D3, "ad8", NULL),
+        _OMAP3_BALLENTRY(ETK_D4, "ac5", NULL),
+        _OMAP3_BALLENTRY(ETK_D5, "ad2", NULL),
+        _OMAP3_BALLENTRY(ETK_D6, "ac8", NULL),
+        _OMAP3_BALLENTRY(ETK_D7, "ad9", NULL),
+        _OMAP3_BALLENTRY(ETK_D8, "ac4", NULL),
+        _OMAP3_BALLENTRY(ETK_D9, "ad5", NULL),
+        _OMAP3_BALLENTRY(GPMC_A1, "k4", NULL),
+        _OMAP3_BALLENTRY(GPMC_A10, "g2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A2, "k3", NULL),
+        _OMAP3_BALLENTRY(GPMC_A3, "k2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A4, "j4", NULL),
+        _OMAP3_BALLENTRY(GPMC_A5, "j3", NULL),
+        _OMAP3_BALLENTRY(GPMC_A6, "j2", NULL),
+        _OMAP3_BALLENTRY(GPMC_A7, "j1", NULL),
+        _OMAP3_BALLENTRY(GPMC_A8, "h1", NULL),
+        _OMAP3_BALLENTRY(GPMC_A9, "h2", NULL),
+        _OMAP3_BALLENTRY(GPMC_CLK, "w2", NULL),
+        _OMAP3_BALLENTRY(GPMC_D10, "u1", NULL),
+        _OMAP3_BALLENTRY(GPMC_D11, "r3", NULL),
+        _OMAP3_BALLENTRY(GPMC_D12, "t3", NULL),
+        _OMAP3_BALLENTRY(GPMC_D13, "u2", NULL),
+        _OMAP3_BALLENTRY(GPMC_D14, "v1", NULL),
+        _OMAP3_BALLENTRY(GPMC_D15, "v2", NULL),
+        _OMAP3_BALLENTRY(GPMC_D8, "r2", NULL),
+        _OMAP3_BALLENTRY(GPMC_D9, "t2", NULL),
+        _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k5", NULL),
+        _OMAP3_BALLENTRY(GPMC_NBE1, "l1", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS3, "d2", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS4, "f4", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS5, "g5", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS6, "f3", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS7, "g4", NULL),
+        _OMAP3_BALLENTRY(GPMC_NWP, "e1", NULL),
+        _OMAP3_BALLENTRY(GPMC_WAIT3, "c2", NULL),
+        _OMAP3_BALLENTRY(HDQ_SIO, "a24", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_CLK, "r21", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA0, "t24", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA1, "t23", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA2, "u24", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA3, "u23", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA4, "w24", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA5, "v23", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA6, "w23", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA7, "t22", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DIR, "p23", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_NXT, "r22", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_STP, "r23", NULL),
+        _OMAP3_BALLENTRY(I2C2_SCL, "ac15", NULL),
+        _OMAP3_BALLENTRY(I2C2_SDA, "ac14", NULL),
+        _OMAP3_BALLENTRY(I2C3_SCL, "ac13", NULL),
+        _OMAP3_BALLENTRY(I2C3_SDA, "ac12", NULL),
+        _OMAP3_BALLENTRY(I2C4_SCL, "y16", NULL),
+        _OMAP3_BALLENTRY(I2C4_SDA, "y15", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU0, "ac24", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU1, "ad24", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKR, "w19", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKX, "v18", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DR, "y18", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DX, "w18", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSR, "ab20", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSX, "aa19", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_CLKX, "t21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DR, "v19", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DX, "r20", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_FSX, "v20", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_CLKX, "w4", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DR, "v5", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DX, "v6", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_FSX, "v4", NULL),
+        _OMAP3_BALLENTRY(MCBSP_CLKS, "aa18", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CLK, "t5", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS0, "t6", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS3, "r5", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SIMO, "r4", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SOMI, "t4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CLK, "n5", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS0, "m5", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS1, "m4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SIMO, "n4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SOMI, "n3", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CLK, "m23", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CMD, "l23", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT0, "m22", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT1, "m21", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT2, "m20", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT3, "n23", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT4, "n22", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT5, "n21", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT6, "n20", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT7, "p24", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CLK, "y1", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CMD, "ab5", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT0, "ab3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT1, "y3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT2, "w3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT3, "v3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT4, "ab2", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT5, "aa2", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT6, "y2", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT7, "aa1", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT0, "ab12", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT1, "ac16", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT2, "ad17", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT3, "ad18", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT4, "ac17", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT5, "ab16", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT6, "aa15", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT1, "y7", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT2, "aa6", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKREQ, "y13", NULL),
+        _OMAP3_BALLENTRY(SYS_NIRQ, "w16", NULL),
+        _OMAP3_BALLENTRY(SYS_NRESWARM, "y10", NULL),
+        _OMAP3_BALLENTRY(SYS_OFF_MODE, "ad23", NULL),
+        _OMAP3_BALLENTRY(UART1_CTS, "ac2", NULL),
+        _OMAP3_BALLENTRY(UART1_RTS, "w6", NULL),
+        _OMAP3_BALLENTRY(UART1_RX, "v7", NULL),
+        _OMAP3_BALLENTRY(UART1_TX, "w7", NULL),
+        _OMAP3_BALLENTRY(UART3_CTS_RCTX, "a23", NULL),
+        _OMAP3_BALLENTRY(UART3_RTS_SD, "b23", NULL),
+        _OMAP3_BALLENTRY(UART3_RX_IRRX, "b24", NULL),
+        _OMAP3_BALLENTRY(UART3_TX_IRTX, "c23", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap3_cus_ball   NULL
+#endif
+
+/*
+ * Signals different on CBB package comapared to superset
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
+struct omap_mux __initdata omap3_cbb_subset[] = {
+        _OMAP3_MUXENTRY(CAM_D10, 109,
+                "cam_d10", NULL, NULL, NULL,
+                "gpio_109", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D11, 110,
+                "cam_d11", NULL, NULL, NULL,
+                "gpio_110", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D2, 101,
+                "cam_d2", NULL, NULL, NULL,
+                "gpio_101", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D3, 102,
+                "cam_d3", NULL, NULL, NULL,
+                "gpio_102", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D4, 103,
+                "cam_d4", NULL, NULL, NULL,
+                "gpio_103", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D5, 104,
+                "cam_d5", NULL, NULL, NULL,
+                "gpio_104", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_FLD, 98,
+                "cam_fld", NULL, "cam_global_reset", NULL,
+                "gpio_98", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_HS, 94,
+                "cam_hs", NULL, NULL, NULL,
+                "gpio_94", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_PCLK, 97,
+                "cam_pclk", NULL, NULL, NULL,
+                "gpio_97", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_STROBE, 126,
+                "cam_strobe", NULL, NULL, NULL,
+                "gpio_126", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_VS, 95,
+                "cam_vs", NULL, NULL, NULL,
+                "gpio_95", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_WEN, 167,
+                "cam_wen", NULL, "cam_shutter", NULL,
+                "gpio_167", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA6, 76,
+                "dss_data6", NULL, "uart1_tx", NULL,
+                "gpio_76", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA7, 77,
+                "dss_data7", NULL, "uart1_rx", NULL,
+                "gpio_77", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA8, 78,
+                "dss_data8", NULL, NULL, NULL,
+                "gpio_78", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA9, 79,
+                "dss_data9", NULL, NULL, NULL,
+                "gpio_79", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_HSYNC, 67,
+                "dss_hsync", NULL, NULL, NULL,
+                "gpio_67", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_PCLK, 66,
+                "dss_pclk", NULL, NULL, NULL,
+                "gpio_66", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(ETK_CLK, 12,
+                "etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
+                "gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
+        _OMAP3_MUXENTRY(ETK_CTL, 13,
+                "etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
+                "gpio_13", NULL, "hsusb1_tll_clk", NULL),
+        _OMAP3_MUXENTRY(ETK_D0, 14,
+                "etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
+                "gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
+        _OMAP3_MUXENTRY(ETK_D1, 15,
+                "etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
+                "gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
+        _OMAP3_MUXENTRY(ETK_D10, 24,
+                "etk_d10", NULL, "uart1_rx", "hsusb2_clk",
+                "gpio_24", NULL, "hsusb2_tll_clk", NULL),
+        _OMAP3_MUXENTRY(ETK_D11, 25,
+                "etk_d11", NULL, NULL, "hsusb2_stp",
+                "gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
+        _OMAP3_MUXENTRY(ETK_D12, 26,
+                "etk_d12", NULL, NULL, "hsusb2_dir",
+                "gpio_26", NULL, "hsusb2_tll_dir", NULL),
+        _OMAP3_MUXENTRY(ETK_D13, 27,
+                "etk_d13", NULL, NULL, "hsusb2_nxt",
+                "gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
+        _OMAP3_MUXENTRY(ETK_D14, 28,
+                "etk_d14", NULL, NULL, "hsusb2_data0",
+                "gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
+        _OMAP3_MUXENTRY(ETK_D15, 29,
+                "etk_d15", NULL, NULL, "hsusb2_data1",
+                "gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
+        _OMAP3_MUXENTRY(ETK_D2, 16,
+                "etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
+                "gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
+        _OMAP3_MUXENTRY(ETK_D3, 17,
+                "etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
+                "gpio_17", NULL, "hsusb1_tll_data7", NULL),
+        _OMAP3_MUXENTRY(ETK_D4, 18,
+                "etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
+                "gpio_18", NULL, "hsusb1_tll_data4", NULL),
+        _OMAP3_MUXENTRY(ETK_D5, 19,
+                "etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
+                "gpio_19", NULL, "hsusb1_tll_data5", NULL),
+        _OMAP3_MUXENTRY(ETK_D6, 20,
+                "etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
+                "gpio_20", NULL, "hsusb1_tll_data6", NULL),
+        _OMAP3_MUXENTRY(ETK_D7, 21,
+                "etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
+                "gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
+        _OMAP3_MUXENTRY(ETK_D8, 22,
+                "etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
+                "gpio_22", NULL, "hsusb1_tll_dir", NULL),
+        _OMAP3_MUXENTRY(ETK_D9, 23,
+                "etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
+                "gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap3_cbb_subset        NULL
+#endif
+
+/*
+ * Balls for CBB package
+ * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
+                && defined(CONFIG_OMAP_PACKAGE_CBB)
+struct omap_ball __initdata omap3_cbb_ball[] = {
+        _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
+        _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
+        _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
+        _OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
+        _OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
+        _OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
+        _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
+        _OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
+        _OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
+        _OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
+        _OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
+        _OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
+        _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
+        _OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
+        _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
+        _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
+        _OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
+        _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
+        _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
+        _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
+        _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
+        _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
+        _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
+        _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
+        _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
+        _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
+        _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
+        _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
+        _OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
+        _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
+        _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
+        _OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
+        _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
+        _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
+        _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
+        _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
+        _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
+        _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
+        _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
+        _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
+        _OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
+        _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
+        _OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
+        _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
+        _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
+        _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
+        _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
+        _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
+        _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
+        _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
+        _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
+        _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
+        _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
+        _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
+        _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
+        _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
+        _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
+        _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
+        _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
+        _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
+        _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
+        _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
+        _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
+        _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
+        _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
+        _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
+        _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
+        _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
+        _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
+        _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
+        _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
+        _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
+        _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
+        _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
+        _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
+        _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
+        _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT4, "p27", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT5, "p26", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT6, "r27", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT7, "r25", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
+        _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
+        _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
+        _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
+        _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
+        _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
+        _OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
+        _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
+        _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
+        _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
+        _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
+        _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
+        _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
+        _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
+        _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
+        _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap3_cbb_ball   NULL
+#endif
+
+/*
+ * Signals different on 36XX CBP package comapared to 34XX CBC package
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP)
+struct omap_mux __initdata omap36xx_cbp_subset[] = {
+        _OMAP3_MUXENTRY(CAM_D0, 99,
+                "cam_d0", NULL, "csi2_dx2", NULL,
+                "gpio_99", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D1, 100,
+                "cam_d1", NULL, "csi2_dy2", NULL,
+                "gpio_100", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D10, 109,
+                "cam_d10", "ssi2_wake", NULL, NULL,
+                "gpio_109", "hw_dbg8", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D2, 101,
+                "cam_d2", "ssi2_rdy_tx", NULL, NULL,
+                "gpio_101", "hw_dbg4", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D3, 102,
+                "cam_d3", "ssi2_dat_rx", NULL, NULL,
+                "gpio_102", "hw_dbg5", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D4, 103,
+                "cam_d4", "ssi2_flag_rx", NULL, NULL,
+                "gpio_103", "hw_dbg6", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_D5, 104,
+                "cam_d5", "ssi2_rdy_rx", NULL, NULL,
+                "gpio_104", "hw_dbg7", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_HS, 94,
+                "cam_hs", "ssi2_dat_tx", NULL, NULL,
+                "gpio_94", "hw_dbg0", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(CAM_VS, 95,
+                "cam_vs", "ssi2_flag_tx", NULL, NULL,
+                "gpio_95", "hw_dbg1", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA0, 70,
+                "dss_data0", "dsi_dx0", "uart1_cts", NULL,
+                "gpio_70", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA1, 71,
+                "dss_data1", "dsi_dy0", "uart1_rts", NULL,
+                "gpio_71", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA2, 72,
+                "dss_data2", "dsi_dx1", NULL, NULL,
+                "gpio_72", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA3, 73,
+                "dss_data3", "dsi_dy1", NULL, NULL,
+                "gpio_73", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA4, 74,
+                "dss_data4", "dsi_dx2", "uart3_rx_irrx", NULL,
+                "gpio_74", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA5, 75,
+                "dss_data5", "dsi_dy2", "uart3_tx_irtx", NULL,
+                "gpio_75", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA6, 76,
+                "dss_data6", NULL, "uart1_tx", "dssvenc656_data6",
+                "gpio_76", "hw_dbg14", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA7, 77,
+                "dss_data7", NULL, "uart1_rx", "dssvenc656_data7",
+                "gpio_77", "hw_dbg15", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA8, 78,
+                "dss_data8", NULL, "uart3_rx_irrx", NULL,
+                "gpio_78", "hw_dbg16", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(DSS_DATA9, 79,
+                "dss_data9", NULL, "uart3_tx_irtx", NULL,
+                "gpio_79", "hw_dbg17", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(ETK_D12, 26,
+                "etk_d12", "sys_drm_msecure", NULL, "hsusb2_dir",
+                "gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
+        _OMAP3_MUXENTRY(GPMC_A11, 0,
+                "gpmc_a11", NULL, NULL, NULL,
+                NULL, NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_WAIT2, 64,
+                "gpmc_wait2", NULL, "uart4_tx", NULL,
+                "gpio_64", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(GPMC_WAIT3, 65,
+                "gpmc_wait3", "sys_ndmareq1", "uart4_rx", NULL,
+                "gpio_65", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
+                "hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
+                "gpio_125", "uart2_tx", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
+                "hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
+                "gpio_130", "uart2_rx", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
+                "hsusb0_data2", NULL, "uart3_rts_sd", NULL,
+                "gpio_131", "uart2_rts", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
+                "hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
+                "gpio_169", "uart2_cts", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
+                "mcbsp1_clkr", "mcspi4_clk", "sim_cd", NULL,
+                "gpio_156", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP1_FSR, 157,
+                "mcbsp1_fsr", "adpllv2d_dithering_en1",
+                "cam_global_reset", NULL,
+                "gpio_157", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
+                "mcbsp4_clkx", "ssi1_dat_rx", NULL, NULL,
+                "gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_DR, 153,
+                "mcbsp4_dr", "ssi1_flag_rx", NULL, NULL,
+                "gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_DX, 154,
+                "mcbsp4_dx", "ssi1_rdy_rx", NULL, NULL,
+                "gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
+        _OMAP3_MUXENTRY(MCBSP4_FSX, 155,
+                "mcbsp4_fsx", "ssi1_wake", NULL, NULL,
+                "gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
+        _OMAP3_MUXENTRY(MCSPI1_CS1, 175,
+                "mcspi1_cs1", "adpllv2d_dithering_en2", NULL, "sdmmc3_cmd",
+                "gpio_175", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
+                "sad2d_mbusflag", "mad2d_sbusflag", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
+                "sad2d_mcad28", "mad2d_mcad28", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
+                "sad2d_mcad29", "mad2d_mcad29", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
+                "sad2d_mcad32", "mad2d_mcad32", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
+                "sad2d_mcad33", "mad2d_mcad33", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
+                "sad2d_mcad34", "mad2d_mcad34", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
+                "sad2d_mcad35", "mad2d_mcad35", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
+                "sad2d_mcad36", "mad2d_mcad36", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MREAD, 0,
+                "sad2d_mread", "mad2d_sread", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
+                "sad2d_mwrite", "mad2d_swrite", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
+                "sad2d_sbusflag", "mad2d_mbusflag", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_SREAD, 0,
+                "sad2d_sread", "mad2d_mread", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
+                "sad2d_swrite", "mad2d_mwrite", NULL, NULL,
+                NULL, NULL, NULL, NULL),
+        _OMAP3_MUXENTRY(SDMMC1_CLK, 120,
+                "sdmmc1_clk", "ms_clk", NULL, NULL,
+                "gpio_120", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_CMD, 121,
+                "sdmmc1_cmd", "ms_bs", NULL, NULL,
+                "gpio_121", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
+                "sdmmc1_dat0", "ms_dat0", NULL, NULL,
+                "gpio_122", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
+                "sdmmc1_dat1", "ms_dat1", NULL, NULL,
+                "gpio_123", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
+                "sdmmc1_dat2", "ms_dat2", NULL, NULL,
+                "gpio_124", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
+                "sdmmc1_dat3", "ms_dat3", NULL, NULL,
+                "gpio_125", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SDRC_CKE0, 0,
+                "sdrc_cke0", NULL, NULL, NULL,
+                NULL, NULL, NULL, "safe_mode_out1"),
+        _OMAP3_MUXENTRY(SDRC_CKE1, 0,
+                "sdrc_cke1", NULL, NULL, NULL,
+                NULL, NULL, NULL, "safe_mode_out1"),
+        _OMAP3_MUXENTRY(SIM_IO, 126,
+                "sim_io", "sim_io_low_impedance", NULL, NULL,
+                "gpio_126", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SIM_CLK, 127,
+                "sim_clk", NULL, NULL, NULL,
+                "gpio_127", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SIM_PWRCTRL, 128,
+                "sim_pwrctrl", NULL, NULL, NULL,
+                "gpio_128", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SIM_RST, 129,
+                "sim_rst", NULL, NULL, NULL,
+                "gpio_129", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT0, 2,
+                "sys_boot0", NULL, NULL, "dss_data18",
+                "gpio_2", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT1, 3,
+                "sys_boot1", NULL, NULL, "dss_data19",
+                "gpio_3", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT3, 5,
+                "sys_boot3", NULL, NULL, "dss_data20",
+                "gpio_5", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT4, 6,
+                "sys_boot4", "sdmmc2_dir_dat2", NULL, "dss_data21",
+                "gpio_6", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT5, 7,
+                "sys_boot5", "sdmmc2_dir_dat3", NULL, "dss_data22",
+                "gpio_7", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(SYS_BOOT6, 8,
+                "sys_boot6", NULL, NULL, "dss_data23",
+                "gpio_8", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_CTS, 150,
+                "uart1_cts", "ssi1_rdy_tx", NULL, NULL,
+                "gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_RTS, 149,
+                "uart1_rts", "ssi1_flag_tx", NULL, NULL,
+                "gpio_149", NULL, NULL, "safe_mode"),
+        _OMAP3_MUXENTRY(UART1_TX, 148,
+                "uart1_tx", "ssi1_dat_tx", NULL, NULL,
+                "gpio_148", NULL, NULL, "safe_mode"),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap36xx_cbp_subset     NULL
+#endif
+
+/*
+ * Balls for 36XX CBP package
+ * 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
+                && defined (CONFIG_OMAP_PACKAGE_CBP)
+struct omap_ball __initdata omap36xx_cbp_ball[] = {
+        _OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
+        _OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
+        _OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
+        _OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
+        _OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
+        _OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
+        _OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
+        _OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
+        _OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
+        _OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
+        _OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
+        _OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
+        _OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
+        _OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
+        _OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
+        _OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
+        _OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
+        _OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
+        _OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
+        _OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
+        _OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
+        _OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
+        _OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
+        _OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
+        _OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
+        _OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
+        _OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
+        _OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
+        _OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
+        _OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
+        _OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
+        _OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
+        _OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
+        _OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
+        _OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
+        _OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
+        _OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
+        _OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
+        _OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
+        _OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
+        _OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
+        _OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
+        _OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
+        _OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
+        _OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
+        _OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
+        _OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
+        _OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
+        _OMAP3_BALLENTRY(GPMC_A11, NULL, "ac20"),
+        _OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
+        _OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
+        _OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
+        _OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
+        _OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
+        _OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
+        _OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
+        _OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
+        _OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
+        _OMAP3_BALLENTRY(GPMC_D0, "k1", "m2"),
+        _OMAP3_BALLENTRY(GPMC_D1, "l1", "m1"),
+        _OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
+        _OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
+        _OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
+        _OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
+        _OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
+        _OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
+        _OMAP3_BALLENTRY(GPMC_D2, "l2", "n2"),
+        _OMAP3_BALLENTRY(GPMC_D3, "p2", "n1"),
+        _OMAP3_BALLENTRY(GPMC_D4, "t1", "r2"),
+        _OMAP3_BALLENTRY(GPMC_D5, "v1", "r1"),
+        _OMAP3_BALLENTRY(GPMC_D6, "v2", "t2"),
+        _OMAP3_BALLENTRY(GPMC_D7, "w2", "t1"),
+        _OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
+        _OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
+        _OMAP3_BALLENTRY(GPMC_NADV_ALE, "f3", "w1"),
+        _OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
+        _OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS0, "g4", "y2"),
+        _OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
+        _OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
+        _OMAP3_BALLENTRY(GPMC_NOE, "g2", "v2"),
+        _OMAP3_BALLENTRY(GPMC_NWE, "f4", "v1"),
+        _OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
+        _OMAP3_BALLENTRY(GPMC_WAIT0, "m8", "ab12"),
+        _OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
+        _OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
+        _OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
+        _OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
+        _OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
+        _OMAP3_BALLENTRY(I2C1_SCL, "k21", NULL),
+        _OMAP3_BALLENTRY(I2C1_SDA, "j21", NULL),
+        _OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
+        _OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
+        _OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
+        _OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
+        _OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
+        _OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
+        _OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
+        _OMAP3_BALLENTRY(JTAG_RTCK, "aa12", NULL),
+        _OMAP3_BALLENTRY(JTAG_TCK, "aa13", NULL),
+        _OMAP3_BALLENTRY(JTAG_TDI, "aa20", NULL),
+        _OMAP3_BALLENTRY(JTAG_TDO, "aa19", NULL),
+        _OMAP3_BALLENTRY(JTAG_TMS_TMSC, "aa18", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
+        _OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
+        _OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
+        _OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
+        _OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
+        _OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
+        _OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
+        _OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
+        _OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
+        _OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
+        _OMAP3_BALLENTRY(SDRC_A0, NULL, "n22"),
+        _OMAP3_BALLENTRY(SDRC_A1, NULL, "n23"),
+        _OMAP3_BALLENTRY(SDRC_A10, NULL, "v22"),
+        _OMAP3_BALLENTRY(SDRC_A11, NULL, "v23"),
+        _OMAP3_BALLENTRY(SDRC_A12, NULL, "w22"),
+        _OMAP3_BALLENTRY(SDRC_A13, NULL, "w23"),
+        _OMAP3_BALLENTRY(SDRC_A14, NULL, "y22"),
+        _OMAP3_BALLENTRY(SDRC_A2, NULL, "p22"),
+        _OMAP3_BALLENTRY(SDRC_A3, NULL, "p23"),
+        _OMAP3_BALLENTRY(SDRC_A4, NULL, "r22"),
+        _OMAP3_BALLENTRY(SDRC_A5, NULL, "r23"),
+        _OMAP3_BALLENTRY(SDRC_A6, NULL, "t22"),
+        _OMAP3_BALLENTRY(SDRC_A7, NULL, "t23"),
+        _OMAP3_BALLENTRY(SDRC_A8, NULL, "u22"),
+        _OMAP3_BALLENTRY(SDRC_A9, NULL, "u23"),
+        _OMAP3_BALLENTRY(SDRC_BA0, "h9", "ab21"),
+        _OMAP3_BALLENTRY(SDRC_BA1, "h10", "ac21"),
+        _OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"),
+        _OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"),
+        _OMAP3_BALLENTRY(SDRC_CLK, "a13", "a11"),
+        _OMAP3_BALLENTRY(SDRC_D0, NULL, "j2"),
+        _OMAP3_BALLENTRY(SDRC_D1, NULL, "j1"),
+        _OMAP3_BALLENTRY(SDRC_D10, "c15", "b14"),
+        _OMAP3_BALLENTRY(SDRC_D11, "b16", "a14"),
+        _OMAP3_BALLENTRY(SDRC_D12, "d17", "b16"),
+        _OMAP3_BALLENTRY(SDRC_D13, "c17", "a16"),
+        _OMAP3_BALLENTRY(SDRC_D14, "b17", "b19"),
+        _OMAP3_BALLENTRY(SDRC_D15, "d18", "a19"),
+        _OMAP3_BALLENTRY(SDRC_D16, NULL, "b3"),
+        _OMAP3_BALLENTRY(SDRC_D17, NULL, "a3"),
+        _OMAP3_BALLENTRY(SDRC_D18, NULL, "b5"),
+        _OMAP3_BALLENTRY(SDRC_D19, NULL, "a5"),
+        _OMAP3_BALLENTRY(SDRC_D2, NULL, "g2"),
+        _OMAP3_BALLENTRY(SDRC_D20, NULL, "b8"),
+        _OMAP3_BALLENTRY(SDRC_D21, NULL, "a8"),
+        _OMAP3_BALLENTRY(SDRC_D22, NULL, "b9"),
+        _OMAP3_BALLENTRY(SDRC_D23, NULL, "a9"),
+        _OMAP3_BALLENTRY(SDRC_D24, NULL, "b21"),
+        _OMAP3_BALLENTRY(SDRC_D25, NULL, "a21"),
+        _OMAP3_BALLENTRY(SDRC_D26, NULL, "d22"),
+        _OMAP3_BALLENTRY(SDRC_D27, NULL, "d23"),
+        _OMAP3_BALLENTRY(SDRC_D28, NULL, "e22"),
+        _OMAP3_BALLENTRY(SDRC_D29, NULL, "e23"),
+        _OMAP3_BALLENTRY(SDRC_D3, NULL, "g1"),
+        _OMAP3_BALLENTRY(SDRC_D30, NULL, "g22"),
+        _OMAP3_BALLENTRY(SDRC_D31, NULL, "g23"),
+        _OMAP3_BALLENTRY(SDRC_D4, NULL, "f2"),
+        _OMAP3_BALLENTRY(SDRC_D5, NULL, "f1"),
+        _OMAP3_BALLENTRY(SDRC_D6, NULL, "d2"),
+        _OMAP3_BALLENTRY(SDRC_D7, NULL, "d1"),
+        _OMAP3_BALLENTRY(SDRC_D8, "c14", "b13"),
+        _OMAP3_BALLENTRY(SDRC_D9, "b14", "a13"),
+        _OMAP3_BALLENTRY(SDRC_DM0, NULL, "c1"),
+        _OMAP3_BALLENTRY(SDRC_DM1, "a16", "a17"),
+        _OMAP3_BALLENTRY(SDRC_DM2, NULL, "a6"),
+        _OMAP3_BALLENTRY(SDRC_DM3, NULL, "a20"),
+        _OMAP3_BALLENTRY(SDRC_DQS0, NULL, "c2"),
+        _OMAP3_BALLENTRY(SDRC_DQS1, "a17", "b17"),
+        _OMAP3_BALLENTRY(SDRC_DQS2, NULL, "b6"),
+        _OMAP3_BALLENTRY(SDRC_DQS3, NULL, "b20"),
+        _OMAP3_BALLENTRY(SDRC_NCAS, "h13", "l22"),
+        _OMAP3_BALLENTRY(SDRC_NCLK, "a14", "b11"),
+        _OMAP3_BALLENTRY(SDRC_NCS0, "h11", "m22"),
+        _OMAP3_BALLENTRY(SDRC_NCS1, "h12", "m23"),
+        _OMAP3_BALLENTRY(SDRC_NRAS, "h14", "l23"),
+        _OMAP3_BALLENTRY(SDRC_NWE, "h15", "k23"),
+        _OMAP3_BALLENTRY(SIM_CLK, "p26", NULL),
+        _OMAP3_BALLENTRY(SIM_IO, "p27", NULL),
+        _OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL),
+        _OMAP3_BALLENTRY(SIM_RST, "r25", NULL),
+        _OMAP3_BALLENTRY(SYS_32K, "ae25", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
+        _OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
+        _OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
+        _OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
+        _OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
+        _OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
+        _OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
+        _OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
+        _OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
+        _OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
+        _OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
+        _OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
+        _OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
+        _OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
+        _OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
+        _OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
+        _OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
+        _OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap36xx_cbp_ball        NULL
+#endif
+
+int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
+{
+        struct omap_mux *package_subset;
+        struct omap_ball *package_balls;
+
+        switch (flags & OMAP_PACKAGE_MASK) {
+        case (OMAP_PACKAGE_CBC):
+                package_subset = omap3_cbc_subset;
+                package_balls = omap3_cbc_ball;
+                break;
+        case (OMAP_PACKAGE_CBB):
+                package_subset = omap3_cbb_subset;
+                package_balls = omap3_cbb_ball;
+                break;
+        case (OMAP_PACKAGE_CUS):
+                package_subset = omap3_cus_subset;
+                package_balls = omap3_cus_ball;
+                break;
+        case (OMAP_PACKAGE_CBP):
+                package_subset = omap36xx_cbp_subset;
+                package_balls = omap36xx_cbp_ball;
+                break;
+        default:
+                printk(KERN_ERR "mux: Unknown omap package, mux disabled\n");
+                return -EINVAL;
+        }
+
+        return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE,
+                             OMAP3_CONTROL_PADCONF_MUX_SIZE,
+                                omap3_muxmodes, package_subset, board_subset,
+                                package_balls);
+}
diff --git a/arch/arm/mach-omap2/mux34xx.h b/arch/arm/mach-omap2/mux34xx.h
new file mode 100644
index 000000000000..6543ebf8ecfc
--- /dev/null
+++ b/arch/arm/mach-omap2/mux34xx.h
@@ -0,0 +1,398 @@
+/*
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define OMAP3_CONTROL_PADCONF_MUX_PBASE                         0x48002030LU
+
+#define OMAP3_MUX(mode0, mux_value)                                     \
+{                                                                       \
+        .reg_offset     = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET),     \
+        .value          = (mux_value),                                  \
+}
+
+/*
+ * OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
+ *
+ * Extracted from the TRM.  Add 0x48002030 to these values to get the
+ * absolute addresses.  The name in the macro is the mode-0 name of
+ * the pin.  NOTE: These registers are 16-bits wide.
+ *
+ * Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
+ * of CHASSIS for some registers. For the defines, we follow the
+ * 36XX naming, and use SDMMC and CHASSIS.
+ */
+#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET                    0x000
+#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET                    0x002
+#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET                    0x004
+#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET                    0x006
+#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET                    0x008
+#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET                    0x00a
+#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET                    0x00c
+#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET                    0x00e
+#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET                    0x010
+#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET                    0x012
+#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET                   0x014
+#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET                   0x016
+#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET                   0x018
+#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET                   0x01a
+#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET                   0x01c
+#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET                   0x01e
+#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET                   0x020
+#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET                   0x022
+#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET                   0x024
+#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET                   0x026
+#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET                   0x028
+#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET                   0x02a
+#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET                   0x02c
+#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET                   0x02e
+#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET                   0x030
+#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET                   0x032
+#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET                   0x034
+#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET                   0x036
+#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET                   0x038
+#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET                   0x03a
+#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET                   0x03c
+#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET                   0x03e
+#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET                   0x040
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET                  0x042
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET                  0x044
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET                  0x046
+#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET                  0x048
+#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET                    0x04a
+#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET                    0x04c
+#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET                    0x04e
+#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET                    0x050
+#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET                    0x052
+#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET                    0x054
+#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET                    0x056
+#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET                    0x058
+#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET                    0x05a
+#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET                   0x05c
+#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET                    0x05e
+#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET                    0x060
+#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET                    0x062
+#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET                    0x064
+#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET                    0x066
+#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET                    0x068
+#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET                    0x06a
+#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET                    0x06c
+#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET                    0x06e
+#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET                    0x070
+#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET                   0x072
+#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET                   0x074
+#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET                   0x076
+#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET                   0x078
+#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET                   0x07a
+#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET                   0x07c
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET                  0x07e
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET                  0x080
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET                  0x082
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET                  0x084
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET                  0x086
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET                  0x088
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET                  0x08a
+#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET                  0x08c
+#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET                   0x08e
+#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET              0x090
+#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET                   0x092
+#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET                   0x094
+#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET              0x096
+#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET                  0x098
+#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET                   0x09a
+#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET                 0x09c
+#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET                 0x09e
+#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET                 0x0a0
+#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET                 0x0a2
+#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET                   0x0a4
+#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET                  0x0a6
+#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET                  0x0a8
+#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET                 0x0aa
+#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET                  0x0ac
+#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET                  0x0ae
+#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET                  0x0b0
+#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET                  0x0b2
+#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET                  0x0b4
+#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET                  0x0b6
+#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET                  0x0b8
+#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET                  0x0ba
+#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET                  0x0bc
+#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET                  0x0be
+#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET                 0x0c0
+#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET                 0x0c2
+#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET                 0x0c4
+#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET                 0x0c6
+#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET                 0x0c8
+#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET                 0x0ca
+#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET                 0x0cc
+#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET                 0x0ce
+#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET                 0x0d0
+#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET                 0x0d2
+#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET                 0x0d4
+#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET                 0x0d6
+#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET                 0x0d8
+#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET                 0x0da
+#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET                     0x0dc
+#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET                     0x0de
+#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET                  0x0e0
+#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET                   0x0e2
+#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET                    0x0e4
+#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET                     0x0e6
+#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET                     0x0e8
+#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET                     0x0ea
+#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET                     0x0ec
+#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET                     0x0ee
+#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET                     0x0f0
+#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET                     0x0f2
+#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET                     0x0f4
+#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET                     0x0f6
+#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET                     0x0f8
+#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET                    0x0fa
+#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET                    0x0fc
+#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET                  0x0fe
+#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET                    0x100
+#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET                 0x102
+#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET                   0x104
+#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET                   0x106
+#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET                   0x108
+#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET                   0x10a
+#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET                 0x10c
+#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET                0x10e
+#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET                  0x110
+#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET                  0x112
+#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET                 0x114
+#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET                 0x116
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET                0x118
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET                0x11a
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET                0x11c
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET                0x11e
+
+/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET                0x120
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET                0x122
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET                0x124
+#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET                0x126
+
+#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET                 0x128
+#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET                 0x12a
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET                0x12c
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET                0x12e
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET                0x130
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET                0x132
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET                0x134
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET                0x136
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET                0x138
+#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET                0x13a
+#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET                  0x13c
+#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET                  0x13e
+#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET                0x140
+#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET                 0x142
+#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET                  0x144
+#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET                  0x146
+#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET                   0x148
+#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET                   0x14a
+#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET                   0x14c
+#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET                  0x14e
+#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET                  0x150
+#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET                   0x152
+#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET                0x154
+#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET                  0x156
+#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET                  0x158
+#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET                 0x15a
+#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET                0x15c
+#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET                 0x15e
+#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET                  0x160
+#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET                  0x162
+#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET                 0x164
+#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET                 0x166
+#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET                0x168
+#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET             0x16a
+#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET               0x16c
+#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET              0x16e
+#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET              0x170
+#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET                 0x172
+#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET                 0x174
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET                 0x176
+#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET                 0x178
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET               0x17a
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET               0x17c
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET               0x17e
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET               0x180
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET               0x182
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET               0x184
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET               0x186
+#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET               0x188
+#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET                   0x18a
+#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET                   0x18c
+#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET                   0x18e
+#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET                   0x190
+#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET                   0x192
+#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET                   0x194
+#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET                    0x196
+#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET                 0x198
+#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET                0x19a
+#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET                0x19c
+#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET                 0x19e
+#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET                 0x1a0
+#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET                 0x1a2
+#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET                 0x1a4
+#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET                 0x1a6
+#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET                0x1a8
+#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET                0x1aa
+#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET                 0x1ac
+#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET                 0x1ae
+#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET                   0x1b0
+#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET                0x1b2
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET                0x1b4
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET                0x1b6
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET                0x1b8
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET                0x1ba
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET                0x1bc
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET                0x1be
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET                0x1c0
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET                0x1c2
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET                0x1c4
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET                0x1c6
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET               0x1c8
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET               0x1ca
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET               0x1cc
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET               0x1ce
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET               0x1d0
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET               0x1d2
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET               0x1d4
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET               0x1d6
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET               0x1d8
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET               0x1da
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET               0x1dc
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET               0x1de
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET               0x1e0
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET               0x1e2
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET               0x1e4
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET               0x1e6
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET               0x1e8
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET               0x1ea
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET               0x1ec
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET               0x1ee
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET               0x1f0
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET               0x1f2
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET               0x1f4
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET               0x1f6
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET               0x1f8
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET               0x1fa
+#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET               0x1fc
+
+/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
+#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET            0x1fe
+#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET          0x200
+#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET           0x202
+#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET               0x204
+#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET                0x206
+#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET             0x208
+#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET             0x20a
+#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET            0x20c
+#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET            0x20e
+#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET            0x210
+#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET            0x212
+#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET              0x214
+#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET                0x216
+#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET                0x218
+#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET                0x21a
+#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET                0x21c
+#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET               0x21e
+#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET             0x220
+#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET            0x222
+#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET            0x224
+
+#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET               0x226
+#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET               0x228
+#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET                0x22a
+#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET                0x22c
+#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET             0x22e
+#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET             0x230
+#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET                  0x232
+#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET                  0x234
+
+/* 36xx only */
+#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET                   0x236
+#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET                   0x570
+#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET                   0x572
+#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET                    0x574
+#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET                    0x576
+#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET                    0x578
+#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET                    0x57a
+#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET                    0x57c
+#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET                    0x57e
+#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET                    0x580
+#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET                    0x582
+#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET                    0x584
+#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET                    0x586
+#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET                   0x588
+#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET                   0x58a
+#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET                   0x58c
+#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET                   0x58e
+#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET                   0x590
+#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET                  0x592
+#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET                  0x594
+#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET                  0x596
+#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET                  0x598
+#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET                  0x59a
+#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET                   0x59c
+#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET                   0x59e
+#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET                   0x5a0
+#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET                   0x5a2
+#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET                   0x5a4
+
+/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
+#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET                     0x120
+#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET                    0x122
+#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET                0x124
+#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET                    0x126
+
+#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET                    0x5a8
+#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET                    0x5aa
+#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET                     0x5ac
+#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET                     0x5ae
+#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET                     0x5b0
+#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET                     0x5b2
+#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET                     0x5b4
+#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET                     0x5b6
+#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET                     0x5b8
+#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET                     0x5ba
+#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET                     0x5bc
+#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET                     0x5be
+#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET                    0x5c0
+#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET                    0x5c2
+#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET                    0x5c4
+#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET                    0x5c6
+#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET                    0x5c8
+#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET                    0x5ca
+#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET                   0x9d0
+#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET                   0x9d2
+#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET                    0x9d4
+#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET                 0x9d6
+#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET               0x9d8
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET                  0x9da
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET                  0x9dc
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET                  0x9de
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET                  0x9e0
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET                  0x9e2
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET                  0x9e4
+#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET                  0x9e6
+#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET               0x9e8
+#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET                0x9ea
+#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET                 0x9ec
+#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET                   0x9ee
+#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET              0x9f0
+#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET                   0x9f2
+#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET                  0x9f4
+#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET                  0x9f6
+#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET              0xa1c
+#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET                  0xa1e
+#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET                   0xa20
+
+#define OMAP3_CONTROL_PADCONF_MUX_SIZE                          \
+                (OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x2)
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 4afadba09477..aa3f65c2ac97 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -27,20 +27,39 @@
  * OMAP4 specific entry point for secondary CPU to jump from ROM
  * code.  This routine also provides a holding flag into which
  * secondary core is held until we're ready for it to initialise.
- * The primary core will update the this flag using a hardware
- * register AuxCoreBoot1.
+ * The primary core will update this flag using a hardware
+ * register AuxCoreBoot0.
  */
 ENTRY(omap_secondary_startup)
-        mrc     p15, 0, r0, c0, c0, 5
-        and     r0, r0, #0x0f
-hold:   ldr     r1, =OMAP4_AUX_CORE_BOOT1_PA    @ read from AuxCoreBoot1
-        ldr     r2, [r1]
-        cmp     r2, r0
+hold:   ldr     r12,=0x103
+        dsb
+        smc                             @ read from AuxCoreBoot0
+        mov     r0, r0, lsr #9
+        mrc     p15, 0, r4, c0, c0, 5
+        and     r4, r4, #0x0f
+        cmp     r0, r4
         bne     hold
 
         /*
-         * we've been released from the cpu_release,secondary_stack
+         * we've been released from the wait loop,secondary_stack
          * should now contain the SVC stack for this core
          */
         b       secondary_startup
+END(omap_secondary_startup)
 
+
+ENTRY(omap_modify_auxcoreboot0)
+        stmfd   sp!, {r1-r12, lr}
+        ldr     r12, =0x104
+        dsb
+        smc
+        ldmfd   sp!, {r1-r12, pc}
+END(omap_modify_auxcoreboot0)
+
+ENTRY(omap_auxcoreboot_addr)
+        stmfd   sp!, {r2-r12, lr}
+        ldr     r12, =0x105
+        dsb
+        smc
+        ldmfd   sp!, {r2-r12, pc}
+END(omap_auxcoreboot_addr)
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 4890bcf4dadd..38153e5fbca0 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -17,19 +17,15 @@
  */
 #include <linux/init.h>
 #include <linux/device.h>
-#include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 
+#include <asm/cacheflush.h>
 #include <asm/localtimer.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 #include <plat/common.h>
 
-/* Registers used for communicating startup information */
-static void __iomem *omap4_auxcoreboot_reg0;
-static void __iomem *omap4_auxcoreboot_reg1;
-
 /* SCU base address */
 static void __iomem *scu_base;
 
@@ -65,8 +61,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        unsigned long timeout;
-
         /*
          * Set synchronisation state between this boot processor
          * and the secondary one
@@ -74,18 +68,15 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         spin_lock(&boot_lock);
 
         /*
-         * Update the AuxCoreBoot1 with boot state for secondary core.
+         * Update the AuxCoreBoot0 with boot state for secondary core.
          * omap_secondary_startup() routine will hold the secondary core till
          * the AuxCoreBoot1 register is updated with cpu state
          * A barrier is added to ensure that write buffer is drained
          */
-        __raw_writel(cpu, omap4_auxcoreboot_reg1);
+        omap_modify_auxcoreboot0(0x200, 0x0);
+        flush_cache_all();
         smp_wmb();
 
-        timeout = jiffies + (1 * HZ);
-        while (time_before(jiffies, timeout))
-                ;
-
         /*
          * Now the secondary core is starting up let it run its
          * calibrations, then wait for it to finish
@@ -99,17 +90,18 @@ static void __init wakeup_secondary(void)
 {
         /*
          * Write the address of secondary startup routine into the
-         * AuxCoreBoot0 where ROM code will jump and start executing
+         * AuxCoreBoot1 where ROM code will jump and start executing
          * on secondary core once out of WFE
          * A barrier is added to ensure that write buffer is drained
          */
-        __raw_writel(virt_to_phys(omap_secondary_startup),         \
-                                        omap4_auxcoreboot_reg0);
+        omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
         smp_wmb();
 
         /*
          * Send a 'sev' to wake the secondary core from WFE.
+         * Drain the outstanding writes to memory
          */
+        dsb();
         set_event();
         mb();
 }
@@ -136,7 +128,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 {
         unsigned int ncores = get_core_count();
         unsigned int cpu = smp_processor_id();
-        void __iomem *omap4_wkupgen_base;
         int i;
 
         /* sanity check */
@@ -168,12 +159,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         for (i = 0; i < max_cpus; i++)
                 set_cpu_present(i, true);
 
-        /* Never released */
-        omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
-        BUG_ON(!omap4_wkupgen_base);
-        omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800;
-        omap4_auxcoreboot_reg1 = omap4_wkupgen_base + 0x804;
-
         if (max_cpus > 1) {
                 /*
                  * Enable the local timer or broadcast device for the
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 633b216a8b26..d8c8545875b1 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -45,6 +45,7 @@
 #include <linux/mutex.h>
 #include <linux/bootmem.h>
 
+#include <plat/common.h>
 #include <plat/cpu.h>
 #include <plat/clockdomain.h>
 #include <plat/powerdomain.h>
@@ -210,6 +211,32 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v)
 }
 
 /**
+ * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
+ * @oh: struct omap_hwmod *
+ * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
+ * @v: pointer to register contents to modify
+ *
+ * Update the module autoidle bit in @v to be @autoidle for the @oh
+ * hwmod.  The autoidle bit controls whether the module can gate
+ * internal clocks automatically when it isn't doing anything; the
+ * exact function of this bit varies on a per-module basis.  This
+ * function does not write to the hardware.  Returns -EINVAL upon
+ * error or 0 upon success.
+ */
+static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
+                                u32 *v)
+{
+        if (!oh->sysconfig ||
+            !(oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE))
+                return -EINVAL;
+
+        *v &= ~SYSC_AUTOIDLE_MASK;
+        *v |= autoidle << SYSC_AUTOIDLE_SHIFT;
+
+        return 0;
+}
+
+/**
  * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
  * @oh: struct omap_hwmod *
  *
@@ -326,6 +353,9 @@ static int _init_main_clk(struct omap_hwmod *oh)
                 ret = -EINVAL;
         oh->_clk = c;
 
+        WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n",
+             oh->clkdev_con_id, c->name);
+
         return ret;
 }
 
@@ -557,8 +587,19 @@ static void _sysc_enable(struct omap_hwmod *oh)
                 _set_master_standbymode(oh, idlemode, &v);
         }
 
-        /* XXX OCP AUTOIDLE bit? */
+        if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) {
+                idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
+                        0 : 1;
+                _set_module_autoidle(oh, idlemode, &v);
+        }
+
+        /* XXX OCP ENAWAKEUP bit? */
 
+        /*
+         * XXX The clock framework should handle this, by
+         * calling into this code.  But this must wait until the
+         * clock structures are tagged with omap_hwmod entries
+         */
         if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT &&
             oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)
                 _set_clockactivity(oh, oh->sysconfig->clockact, &v);
@@ -622,7 +663,8 @@ static void _sysc_shutdown(struct omap_hwmod *oh)
         if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE)
                 _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
 
-        /* XXX clear OCP AUTOIDLE bit? */
+        if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE)
+                _set_module_autoidle(oh, 1, &v);
 
         _write_sysconfig(v, oh);
 }
@@ -736,7 +778,7 @@ static int _wait_target_ready(struct omap_hwmod *oh)
 static int _reset(struct omap_hwmod *oh)
 {
         u32 r, v;
-        int c;
+        int c = 0;
 
         if (!oh->sysconfig ||
             !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) ||
@@ -758,13 +800,9 @@ static int _reset(struct omap_hwmod *oh)
                 return r;
         _write_sysconfig(v, oh);
 
-        c = 0;
-        while (c < MAX_MODULE_RESET_WAIT &&
-               !(omap_hwmod_readl(oh, oh->sysconfig->syss_offs) &
-                 SYSS_RESETDONE_MASK)) {
-                udelay(1);
-                c++;
-        }
+        omap_test_timeout((omap_hwmod_readl(oh, oh->sysconfig->syss_offs) &
+                           SYSS_RESETDONE_MASK),
+                          MAX_MODULE_RESET_WAIT, c);
 
         if (c == MAX_MODULE_RESET_WAIT)
                 WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n",
@@ -884,33 +922,6 @@ static int _shutdown(struct omap_hwmod *oh)
 }
 
 /**
- * _write_clockact_lock - set the module's clockactivity bits
- * @oh: struct omap_hwmod *
- * @clockact: CLOCKACTIVITY field bits
- *
- * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- * OCP_SYSCONFIG register.  Returns -EINVAL if the hwmod is in the
- * wrong state or returns 0.
- */
-static int _write_clockact_lock(struct omap_hwmod *oh, u8 clockact)
-{
-        u32 v;
-
-        if (!oh->sysconfig ||
-            !(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
-                return -EINVAL;
-
-        mutex_lock(&omap_hwmod_mutex);
-        v = oh->_sysc_cache;
-        _set_clockactivity(oh, clockact, &v);
-        _write_sysconfig(v, oh);
-        mutex_unlock(&omap_hwmod_mutex);
-
-        return 0;
-}
-
-
-/**
  * _setup - do initial configuration of omap_hwmod
  * @oh: struct omap_hwmod *
  *
@@ -948,11 +959,19 @@ static int _setup(struct omap_hwmod *oh)
 
         _enable(oh);
 
-        if (!(oh->flags & HWMOD_INIT_NO_RESET))
-                _reset(oh);
-
-        /* XXX OCP AUTOIDLE bit? */
-        /* XXX OCP ENAWAKEUP bit? */
+        if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
+                /*
+                 * XXX Do the OCP_SYSCONFIG bits need to be
+                 * reprogrammed after a reset?  If not, then this can
+                 * be removed.  If they do, then probably the
+                 * _enable() function should be split to avoid the
+                 * rewrite of the OCP_SYSCONFIG register.
+                 */
+                if (oh->sysconfig) {
+                        _update_sysc_cache(oh);
+                        _sysc_enable(oh);
+                }
+        }
 
         if (!(oh->flags & HWMOD_INIT_NO_IDLE))
                 _idle(oh);
@@ -1348,8 +1367,9 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
         /* For each IRQ, DMA, memory area, fill in array.*/
 
         for (i = 0; i < oh->mpu_irqs_cnt; i++) {
-                (res + r)->start = *(oh->mpu_irqs + i);
-                (res + r)->end = *(oh->mpu_irqs + i);
+                (res + r)->name = (oh->mpu_irqs + i)->name;
+                (res + r)->start = (oh->mpu_irqs + i)->irq;
+                (res + r)->end = (oh->mpu_irqs + i)->irq;
                 (res + r)->flags = IORESOURCE_IRQ;
                 r++;
         }
@@ -1454,62 +1474,6 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
 }
 
 /**
- * omap_hwmod_set_clockact_none - set clockactivity test to BOTH
- * @oh: struct omap_hwmod *
- *
- * On some modules, this function can affect the wakeup latency vs.
- * power consumption balance.  Intended to be called by the
- * omap_device layer.  Passes along the return value from
- * _write_clockact_lock().
- */
-int omap_hwmod_set_clockact_both(struct omap_hwmod *oh)
-{
-        return _write_clockact_lock(oh, CLOCKACT_TEST_BOTH);
-}
-
-/**
- * omap_hwmod_set_clockact_none - set clockactivity test to MAIN
- * @oh: struct omap_hwmod *
- *
- * On some modules, this function can affect the wakeup latency vs.
- * power consumption balance.  Intended to be called by the
- * omap_device layer.  Passes along the return value from
- * _write_clockact_lock().
- */
-int omap_hwmod_set_clockact_main(struct omap_hwmod *oh)
-{
-        return _write_clockact_lock(oh, CLOCKACT_TEST_MAIN);
-}
-
-/**
- * omap_hwmod_set_clockact_none - set clockactivity test to ICLK
- * @oh: struct omap_hwmod *
- *
- * On some modules, this function can affect the wakeup latency vs.
- * power consumption balance.  Intended to be called by the
- * omap_device layer.  Passes along the return value from
- * _write_clockact_lock().
- */
-int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh)
-{
-        return _write_clockact_lock(oh, CLOCKACT_TEST_ICLK);
-}
-
-/**
- * omap_hwmod_set_clockact_none - set clockactivity test to NONE
- * @oh: struct omap_hwmod *
- *
- * On some modules, this function can affect the wakeup latency vs.
- * power consumption balance.  Intended to be called by the
- * omap_device layer.  Passes along the return value from
- * _write_clockact_lock().
- */
-int omap_hwmod_set_clockact_none(struct omap_hwmod *oh)
-{
-        return _write_clockact_lock(oh, CLOCKACT_TEST_NONE);
-}
-
-/**
  * omap_hwmod_enable_wakeup - allow device to wake up the system
  * @oh: struct omap_hwmod *
  *
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
new file mode 100644
index 000000000000..126a9396b3a8
--- /dev/null
+++ b/arch/arm/mach-omap2/opp2420_data.c
@@ -0,0 +1,126 @@
+/*
+ * opp2420_data.c - old-style "OPP" table for OMAP2420
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2009 Nokia Corporation
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
+ * These configurations are characterized by voltage and speed for clocks.
+ * The device is only validated for certain combinations. One way to express
+ * these combinations is via the 'ratio's' which the clocks operate with
+ * respect to each other. These ratio sets are for a given voltage/DPLL
+ * setting. All configurations can be described by a DPLL setting and a ratio
+ * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
+ *
+ * 2430 differs from 2420 in that there are no more phase synchronizers used.
+ * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
+ * 2430 (iva2.1, NOdsp, mdm)
+ *
+ * XXX Missing voltage data.
+ *
+ * THe format described in this file is deprecated.  Once a reasonable
+ * OPP API exists, the data in this file should be converted to use it.
+ *
+ * This is technically part of the OMAP2xxx clock code.
+ */
+
+#include "opp2xxx.h"
+#include "sdrc.h"
+#include "clock.h"
+
+/*-------------------------------------------------------------------------
+ * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
+ * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
+ * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ *
+ * Filling in table based on H4 boards and 2430-SDPs variants available.
+ * There are quite a few more rates combinations which could be defined.
+ *
+ * When multiple values are defined the start up will try and choose the
+ * fastest one. If a 'fast' value is defined, then automatically, the /2
+ * one should be included as it can be used.    Generally having more that
+ * one fast set does not make sense, as static timings need to be changed
+ * to change the set.    The exception is the bypass setting which is
+ * availble for low power bypass.
+ *
+ * Note: This table needs to be sorted, fastest to slowest.
+ *-------------------------------------------------------------------------*/
+const struct prcm_config omap2420_rate_table[] = {
+        /* PRCM I - FAST */
+        {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
+                RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
+                RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
+                RATE_IN_242X},
+
+        /* PRCM II - FAST */
+        {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL,             /* 300MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        /* PRCM III - FAST */
+        {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL,            /* 266MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        /* PRCM II - SLOW */
+        {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL,             /* 150MHz ARM */
+                RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
+                RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
+                RATE_IN_242X},
+
+        /* PRCM III - SLOW */
+        {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL,            /* 133MHz ARM */
+                RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
+                RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
+                RATE_IN_242X},
+
+        /* PRCM-VII (boot-bypass) */
+        {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL,              /* 12MHz ARM*/
+                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
+                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_242X},
+
+        /* PRCM-VII (boot-bypass) */
+        {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL,              /* 13MHz ARM */
+                RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
+                RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_242X},
+
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+};
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
new file mode 100644
index 000000000000..edb81672c844
--- /dev/null
+++ b/arch/arm/mach-omap2/opp2430_data.c
@@ -0,0 +1,133 @@
+/*
+ * opp2420_data.c - old-style "OPP" table for OMAP2420
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2009 Nokia Corporation
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
+ * These configurations are characterized by voltage and speed for clocks.
+ * The device is only validated for certain combinations. One way to express
+ * these combinations is via the 'ratio's' which the clocks operate with
+ * respect to each other. These ratio sets are for a given voltage/DPLL
+ * setting. All configurations can be described by a DPLL setting and a ratio
+ * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
+ *
+ * 2430 differs from 2420 in that there are no more phase synchronizers used.
+ * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
+ * 2430 (iva2.1, NOdsp, mdm)
+ *
+ * XXX Missing voltage data.
+ *
+ * THe format described in this file is deprecated.  Once a reasonable
+ * OPP API exists, the data in this file should be converted to use it.
+ *
+ * This is technically part of the OMAP2xxx clock code.
+ */
+
+#include "opp2xxx.h"
+#include "sdrc.h"
+#include "clock.h"
+
+/*-------------------------------------------------------------------------
+ * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
+ * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
+ * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ *
+ * Filling in table based on H4 boards and 2430-SDPs variants available.
+ * There are quite a few more rates combinations which could be defined.
+ *
+ * When multiple values are defined the start up will try and choose the
+ * fastest one. If a 'fast' value is defined, then automatically, the /2
+ * one should be included as it can be used.    Generally having more that
+ * one fast set does not make sense, as static timings need to be changed
+ * to change the set.    The exception is the bypass setting which is
+ * availble for low power bypass.
+ *
+ * Note: This table needs to be sorted, fastest to slowest.
+ *-------------------------------------------------------------------------*/
+const struct prcm_config omap2430_rate_table[] = {
+        /* PRCM #4 - ratio2 (ES2.1) - FAST */
+        {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL,              /* 399MHz ARM */
+                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
+                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #2 - ratio1 (ES2) - FAST */
+        {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL,              /* 330MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_165MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5a - ratio1 - FAST */
+        {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL,              /* 266MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5b - ratio1 - FAST */
+        {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_100MHz,
+                RATE_IN_243X},
+
+        /* PRCM #4 - ratio1 (ES2.1) - SLOW */
+        {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL,              /* 200MHz ARM */
+                R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
+                R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #2 - ratio1 (ES2) - SLOW */
+        {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL,              /* 165MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_165MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5a - ratio1 - SLOW */
+        {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL,              /* 133MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_133MHz,
+                RATE_IN_243X},
+
+        /* PRCM #5b - ratio1 - SLOW*/
+        {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL,              /* 100MHz ARM */
+                R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
+                R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_100MHz,
+                RATE_IN_243X},
+
+        /* PRCM-boot/bypass */
+        {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL,                /* 13Mhz */
+                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
+                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_243X},
+
+        /* PRCM-boot/bypass */
+        {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL,                /* 12Mhz */
+                RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
+                RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
+                MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
+                SDRC_RFR_CTRL_BYPASS,
+                RATE_IN_243X},
+
+        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+};
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
new file mode 100644
index 000000000000..ed6df04e2f29
--- /dev/null
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -0,0 +1,424 @@
+/*
+ * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
+ *
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2009 Nokia Corporation
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
+ * These configurations are characterized by voltage and speed for clocks.
+ * The device is only validated for certain combinations. One way to express
+ * these combinations is via the 'ratio's' which the clocks operate with
+ * respect to each other. These ratio sets are for a given voltage/DPLL
+ * setting. All configurations can be described by a DPLL setting and a ratio
+ * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
+ *
+ * 2430 differs from 2420 in that there are no more phase synchronizers used.
+ * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
+ * 2430 (iva2.1, NOdsp, mdm)
+ *
+ * XXX Missing voltage data.
+ *
+ * THe format described in this file is deprecated.  Once a reasonable
+ * OPP API exists, the data in this file should be converted to use it.
+ *
+ * This is technically part of the OMAP2xxx clock code.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
+#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
+
+/**
+ * struct prcm_config - define clock rates on a per-OPP basis (24xx)
+ *
+ * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
+ * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
+ * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
+ *
+ * This is deprecated.  As soon as we have a decent OPP API, we should
+ * move all this stuff to it.
+ */
+struct prcm_config {
+        unsigned long xtal_speed;       /* crystal rate */
+        unsigned long dpll_speed;       /* dpll: out*xtal*M/(N-1)table_recalc */
+        unsigned long mpu_speed;        /* speed of MPU */
+        unsigned long cm_clksel_mpu;    /* mpu divider */
+        unsigned long cm_clksel_dsp;    /* dsp+iva1 div(2420), iva2.1(2430) */
+        unsigned long cm_clksel_gfx;    /* gfx dividers */
+        unsigned long cm_clksel1_core;  /* major subsystem dividers */
+        unsigned long cm_clksel1_pll;   /* m,n */
+        unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
+        unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
+        unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
+        unsigned char flags;
+};
+
+
+/* Core fields for cm_clksel, not ratio governed */
+#define RX_CLKSEL_DSS1                  (0x10 << 8)
+#define RX_CLKSEL_DSS2                  (0x0 << 13)
+#define RX_CLKSEL_SSI                   (0x5 << 20)
+
+/*-------------------------------------------------------------------------
+ * Voltage/DPLL ratios
+ *-------------------------------------------------------------------------*/
+
+/* 2430 Ratio's, 2430-Ratio Config 1 */
+#define R1_CLKSEL_L3                    (4 << 0)
+#define R1_CLKSEL_L4                    (2 << 5)
+#define R1_CLKSEL_USB                   (4 << 25)
+#define R1_CM_CLKSEL1_CORE_VAL          (R1_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                         R1_CLKSEL_L4 | R1_CLKSEL_L3)
+#define R1_CLKSEL_MPU                   (2 << 0)
+#define R1_CM_CLKSEL_MPU_VAL            R1_CLKSEL_MPU
+#define R1_CLKSEL_DSP                   (2 << 0)
+#define R1_CLKSEL_DSP_IF                (2 << 5)
+#define R1_CM_CLKSEL_DSP_VAL            (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF)
+#define R1_CLKSEL_GFX                   (2 << 0)
+#define R1_CM_CLKSEL_GFX_VAL            R1_CLKSEL_GFX
+#define R1_CLKSEL_MDM                   (4 << 0)
+#define R1_CM_CLKSEL_MDM_VAL            R1_CLKSEL_MDM
+
+/* 2430-Ratio Config 2 */
+#define R2_CLKSEL_L3                    (6 << 0)
+#define R2_CLKSEL_L4                    (2 << 5)
+#define R2_CLKSEL_USB                   (2 << 25)
+#define R2_CM_CLKSEL1_CORE_VAL          (R2_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                         R2_CLKSEL_L4 | R2_CLKSEL_L3)
+#define R2_CLKSEL_MPU                   (2 << 0)
+#define R2_CM_CLKSEL_MPU_VAL            R2_CLKSEL_MPU
+#define R2_CLKSEL_DSP                   (2 << 0)
+#define R2_CLKSEL_DSP_IF                (3 << 5)
+#define R2_CM_CLKSEL_DSP_VAL            (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF)
+#define R2_CLKSEL_GFX                   (2 << 0)
+#define R2_CM_CLKSEL_GFX_VAL            R2_CLKSEL_GFX
+#define R2_CLKSEL_MDM                   (6 << 0)
+#define R2_CM_CLKSEL_MDM_VAL            R2_CLKSEL_MDM
+
+/* 2430-Ratio Bootm (BYPASS) */
+#define RB_CLKSEL_L3                    (1 << 0)
+#define RB_CLKSEL_L4                    (1 << 5)
+#define RB_CLKSEL_USB                   (1 << 25)
+#define RB_CM_CLKSEL1_CORE_VAL          (RB_CLKSEL_USB | RX_CLKSEL_SSI | \
+                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                         RB_CLKSEL_L4 | RB_CLKSEL_L3)
+#define RB_CLKSEL_MPU                   (1 << 0)
+#define RB_CM_CLKSEL_MPU_VAL            RB_CLKSEL_MPU
+#define RB_CLKSEL_DSP                   (1 << 0)
+#define RB_CLKSEL_DSP_IF                (1 << 5)
+#define RB_CM_CLKSEL_DSP_VAL            (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF)
+#define RB_CLKSEL_GFX                   (1 << 0)
+#define RB_CM_CLKSEL_GFX_VAL            RB_CLKSEL_GFX
+#define RB_CLKSEL_MDM                   (1 << 0)
+#define RB_CM_CLKSEL_MDM_VAL            RB_CLKSEL_MDM
+
+/* 2420 Ratio Equivalents */
+#define RXX_CLKSEL_VLYNQ                (0x12 << 15)
+#define RXX_CLKSEL_SSI                  (0x8 << 20)
+
+/* 2420-PRCM III 532MHz core */
+#define RIII_CLKSEL_L3                  (4 << 0)        /* 133MHz */
+#define RIII_CLKSEL_L4                  (2 << 5)        /* 66.5MHz */
+#define RIII_CLKSEL_USB                 (4 << 25)       /* 33.25MHz */
+#define RIII_CM_CLKSEL1_CORE_VAL        (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
+                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
+                                         RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
+                                         RIII_CLKSEL_L3)
+#define RIII_CLKSEL_MPU                 (2 << 0)        /* 266MHz */
+#define RIII_CM_CLKSEL_MPU_VAL          RIII_CLKSEL_MPU
+#define RIII_CLKSEL_DSP                 (3 << 0)        /* c5x - 177.3MHz */
+#define RIII_CLKSEL_DSP_IF              (2 << 5)        /* c5x - 88.67MHz */
+#define RIII_SYNC_DSP                   (1 << 7)        /* Enable sync */
+#define RIII_CLKSEL_IVA                 (6 << 8)        /* iva1 - 88.67MHz */
+#define RIII_SYNC_IVA                   (1 << 13)       /* Enable sync */
+#define RIII_CM_CLKSEL_DSP_VAL          (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
+                                         RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
+                                         RIII_CLKSEL_DSP)
+#define RIII_CLKSEL_GFX                 (2 << 0)        /* 66.5MHz */
+#define RIII_CM_CLKSEL_GFX_VAL          RIII_CLKSEL_GFX
+
+/* 2420-PRCM II 600MHz core */
+#define RII_CLKSEL_L3                   (6 << 0)        /* 100MHz */
+#define RII_CLKSEL_L4                   (2 << 5)        /* 50MHz */
+#define RII_CLKSEL_USB                  (2 << 25)       /* 50MHz */
+#define RII_CM_CLKSEL1_CORE_VAL         (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \
+                                         RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
+                                         RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \
+                                         RII_CLKSEL_L3)
+#define RII_CLKSEL_MPU                  (2 << 0)        /* 300MHz */
+#define RII_CM_CLKSEL_MPU_VAL           RII_CLKSEL_MPU
+#define RII_CLKSEL_DSP                  (3 << 0)        /* c5x - 200MHz */
+#define RII_CLKSEL_DSP_IF               (2 << 5)        /* c5x - 100MHz */
+#define RII_SYNC_DSP                    (0 << 7)        /* Bypass sync */
+#define RII_CLKSEL_IVA                  (3 << 8)        /* iva1 - 200MHz */
+#define RII_SYNC_IVA                    (0 << 13)       /* Bypass sync */
+#define RII_CM_CLKSEL_DSP_VAL           (RII_SYNC_IVA | RII_CLKSEL_IVA | \
+                                         RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
+                                         RII_CLKSEL_DSP)
+#define RII_CLKSEL_GFX                  (2 << 0)        /* 50MHz */
+#define RII_CM_CLKSEL_GFX_VAL           RII_CLKSEL_GFX
+
+/* 2420-PRCM I 660MHz core */
+#define RI_CLKSEL_L3                    (4 << 0)        /* 165MHz */
+#define RI_CLKSEL_L4                    (2 << 5)        /* 82.5MHz */
+#define RI_CLKSEL_USB                   (4 << 25)       /* 41.25MHz */
+#define RI_CM_CLKSEL1_CORE_VAL          (RI_CLKSEL_USB |                \
+                                         RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
+                                         RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
+                                         RI_CLKSEL_L4 | RI_CLKSEL_L3)
+#define RI_CLKSEL_MPU                   (2 << 0)        /* 330MHz */
+#define RI_CM_CLKSEL_MPU_VAL            RI_CLKSEL_MPU
+#define RI_CLKSEL_DSP                   (3 << 0)        /* c5x - 220MHz */
+#define RI_CLKSEL_DSP_IF                (2 << 5)        /* c5x - 110MHz */
+#define RI_SYNC_DSP                     (1 << 7)        /* Activate sync */
+#define RI_CLKSEL_IVA                   (4 << 8)        /* iva1 - 165MHz */
+#define RI_SYNC_IVA                     (0 << 13)       /* Bypass sync */
+#define RI_CM_CLKSEL_DSP_VAL            (RI_SYNC_IVA | RI_CLKSEL_IVA |  \
+                                         RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
+                                         RI_CLKSEL_DSP)
+#define RI_CLKSEL_GFX                   (1 << 0)        /* 165MHz */
+#define RI_CM_CLKSEL_GFX_VAL            RI_CLKSEL_GFX
+
+/* 2420-PRCM VII (boot) */
+#define RVII_CLKSEL_L3                  (1 << 0)
+#define RVII_CLKSEL_L4                  (1 << 5)
+#define RVII_CLKSEL_DSS1                (1 << 8)
+#define RVII_CLKSEL_DSS2                (0 << 13)
+#define RVII_CLKSEL_VLYNQ               (1 << 15)
+#define RVII_CLKSEL_SSI                 (1 << 20)
+#define RVII_CLKSEL_USB                 (1 << 25)
+
+#define RVII_CM_CLKSEL1_CORE_VAL        (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
+                                         RVII_CLKSEL_VLYNQ | \
+                                         RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \
+                                         RVII_CLKSEL_L4 | RVII_CLKSEL_L3)
+
+#define RVII_CLKSEL_MPU                 (1 << 0) /* all divide by 1 */
+#define RVII_CM_CLKSEL_MPU_VAL          RVII_CLKSEL_MPU
+
+#define RVII_CLKSEL_DSP                 (1 << 0)
+#define RVII_CLKSEL_DSP_IF              (1 << 5)
+#define RVII_SYNC_DSP                   (0 << 7)
+#define RVII_CLKSEL_IVA                 (1 << 8)
+#define RVII_SYNC_IVA                   (0 << 13)
+#define RVII_CM_CLKSEL_DSP_VAL          (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \
+                                         RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \
+                                         RVII_CLKSEL_DSP)
+
+#define RVII_CLKSEL_GFX                 (1 << 0)
+#define RVII_CM_CLKSEL_GFX_VAL          RVII_CLKSEL_GFX
+
+/*-------------------------------------------------------------------------
+ * 2430 Target modes: Along with each configuration the CPU has several
+ * modes which goes along with them. Modes mainly are the addition of
+ * describe DPLL combinations to go along with a ratio.
+ *-------------------------------------------------------------------------*/
+
+/* Hardware governed */
+#define MX_48M_SRC                      (0 << 3)
+#define MX_54M_SRC                      (0 << 5)
+#define MX_APLLS_CLIKIN_12              (3 << 23)
+#define MX_APLLS_CLIKIN_13              (2 << 23)
+#define MX_APLLS_CLIKIN_19_2            (0 << 23)
+
+/*
+ * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
+ * #5a  (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
+ */
+#define M5A_DPLL_MULT_12                (133 << 12)
+#define M5A_DPLL_DIV_12                 (5 << 8)
+#define M5A_CM_CLKSEL1_PLL_12_VAL       (MX_48M_SRC | MX_54M_SRC | \
+                                         M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+#define M5A_DPLL_MULT_13                (61 << 12)
+#define M5A_DPLL_DIV_13                 (2 << 8)
+#define M5A_CM_CLKSEL1_PLL_13_VAL       (MX_48M_SRC | MX_54M_SRC | \
+                                         M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
+                                         MX_APLLS_CLIKIN_13)
+#define M5A_DPLL_MULT_19                (55 << 12)
+#define M5A_DPLL_DIV_19                 (3 << 8)
+#define M5A_CM_CLKSEL1_PLL_19_VAL       (MX_48M_SRC | MX_54M_SRC | \
+                                         M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
+                                         MX_APLLS_CLIKIN_19_2)
+/* #5b  (ratio1) target DPLL = 200*2 = 400MHz */
+#define M5B_DPLL_MULT_12                (50 << 12)
+#define M5B_DPLL_DIV_12                 (2 << 8)
+#define M5B_CM_CLKSEL1_PLL_12_VAL       (MX_48M_SRC | MX_54M_SRC | \
+                                         M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+#define M5B_DPLL_MULT_13                (200 << 12)
+#define M5B_DPLL_DIV_13                 (12 << 8)
+
+#define M5B_CM_CLKSEL1_PLL_13_VAL       (MX_48M_SRC | MX_54M_SRC | \
+                                         M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
+                                         MX_APLLS_CLIKIN_13)
+#define M5B_DPLL_MULT_19                (125 << 12)
+#define M5B_DPLL_DIV_19                 (31 << 8)
+#define M5B_CM_CLKSEL1_PLL_19_VAL       (MX_48M_SRC | MX_54M_SRC | \
+                                         M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
+                                         MX_APLLS_CLIKIN_19_2)
+/*
+ * #4   (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
+ */
+#define M4_DPLL_MULT_12                 (133 << 12)
+#define M4_DPLL_DIV_12                  (3 << 8)
+#define M4_CM_CLKSEL1_PLL_12_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+
+#define M4_DPLL_MULT_13                 (399 << 12)
+#define M4_DPLL_DIV_13                  (12 << 8)
+#define M4_CM_CLKSEL1_PLL_13_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
+                                         MX_APLLS_CLIKIN_13)
+
+#define M4_DPLL_MULT_19                 (145 << 12)
+#define M4_DPLL_DIV_19                  (6 << 8)
+#define M4_CM_CLKSEL1_PLL_19_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
+                                         MX_APLLS_CLIKIN_19_2)
+
+/*
+ * #3   (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
+ */
+#define M3_DPLL_MULT_12                 (55 << 12)
+#define M3_DPLL_DIV_12                  (1 << 8)
+#define M3_CM_CLKSEL1_PLL_12_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+#define M3_DPLL_MULT_13                 (76 << 12)
+#define M3_DPLL_DIV_13                  (2 << 8)
+#define M3_CM_CLKSEL1_PLL_13_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
+                                         MX_APLLS_CLIKIN_13)
+#define M3_DPLL_MULT_19                 (17 << 12)
+#define M3_DPLL_DIV_19                  (0 << 8)
+#define M3_CM_CLKSEL1_PLL_19_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
+                                         MX_APLLS_CLIKIN_19_2)
+
+/*
+ * #2   (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
+ */
+#define M2_DPLL_MULT_12                 (55 << 12)
+#define M2_DPLL_DIV_12                  (1 << 8)
+#define M2_CM_CLKSEL1_PLL_12_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+
+/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
+ * relock time issue */
+/* Core frequency changed from 330/165 to 329/164 MHz*/
+#define M2_DPLL_MULT_13                 (76 << 12)
+#define M2_DPLL_DIV_13                  (2 << 8)
+#define M2_CM_CLKSEL1_PLL_13_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
+                                         MX_APLLS_CLIKIN_13)
+
+#define M2_DPLL_MULT_19                 (17 << 12)
+#define M2_DPLL_DIV_19                  (0 << 8)
+#define M2_CM_CLKSEL1_PLL_19_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
+                                         MX_APLLS_CLIKIN_19_2)
+
+/* boot (boot) */
+#define MB_DPLL_MULT                    (1 << 12)
+#define MB_DPLL_DIV                     (0 << 8)
+#define MB_CM_CLKSEL1_PLL_12_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         MB_DPLL_DIV | MB_DPLL_MULT | \
+                                         MX_APLLS_CLIKIN_12)
+
+#define MB_CM_CLKSEL1_PLL_13_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         MB_DPLL_DIV | MB_DPLL_MULT | \
+                                         MX_APLLS_CLIKIN_13)
+
+#define MB_CM_CLKSEL1_PLL_19_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         MB_DPLL_DIV | MB_DPLL_MULT | \
+                                         MX_APLLS_CLIKIN_19)
+
+/*
+ * 2430 - chassis (sedna)
+ * 165 (ratio1) same as above #2
+ * 150 (ratio1)
+ * 133 (ratio2) same as above #4
+ * 110 (ratio2) same as above #3
+ * 104 (ratio2)
+ * boot (boot)
+ */
+
+/* PRCM I target DPLL = 2*330MHz = 660MHz */
+#define MI_DPLL_MULT_12                 (55 << 12)
+#define MI_DPLL_DIV_12                  (1 << 8)
+#define MI_CM_CLKSEL1_PLL_12_VAL        (MX_48M_SRC | MX_54M_SRC | \
+                                         MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+
+/*
+ * 2420 Equivalent - mode registers
+ * PRCM II , target DPLL = 2*300MHz = 600MHz
+ */
+#define MII_DPLL_MULT_12                (50 << 12)
+#define MII_DPLL_DIV_12                 (1 << 8)
+#define MII_CM_CLKSEL1_PLL_12_VAL       (MX_48M_SRC | MX_54M_SRC |      \
+                                         MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
+                                         MX_APLLS_CLIKIN_12)
+#define MII_DPLL_MULT_13                (300 << 12)
+#define MII_DPLL_DIV_13                 (12 << 8)
+#define MII_CM_CLKSEL1_PLL_13_VAL       (MX_48M_SRC | MX_54M_SRC |      \
+                                         MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
+                                         MX_APLLS_CLIKIN_13)
+
+/* PRCM III target DPLL = 2*266 = 532MHz*/
+#define MIII_DPLL_MULT_12               (133 << 12)
+#define MIII_DPLL_DIV_12                (5 << 8)
+#define MIII_CM_CLKSEL1_PLL_12_VAL      (MX_48M_SRC | MX_54M_SRC |      \
+                                         MIII_DPLL_DIV_12 | \
+                                         MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12)
+#define MIII_DPLL_MULT_13               (266 << 12)
+#define MIII_DPLL_DIV_13                (12 << 8)
+#define MIII_CM_CLKSEL1_PLL_13_VAL      (MX_48M_SRC | MX_54M_SRC |      \
+                                         MIII_DPLL_DIV_13 | \
+                                         MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13)
+
+/* PRCM VII (boot bypass) */
+#define MVII_CM_CLKSEL1_PLL_12_VAL      MB_CM_CLKSEL1_PLL_12_VAL
+#define MVII_CM_CLKSEL1_PLL_13_VAL      MB_CM_CLKSEL1_PLL_13_VAL
+
+/* High and low operation value */
+#define MX_CLKSEL2_PLL_2x_VAL           (2 << 0)
+#define MX_CLKSEL2_PLL_1x_VAL           (1 << 0)
+
+/* MPU speed defines */
+#define S12M    12000000
+#define S13M    13000000
+#define S19M    19200000
+#define S26M    26000000
+#define S100M   100000000
+#define S133M   133000000
+#define S150M   150000000
+#define S164M   164000000
+#define S165M   165000000
+#define S199M   199000000
+#define S200M   200000000
+#define S266M   266000000
+#define S300M   300000000
+#define S329M   329000000
+#define S330M   330000000
+#define S399M   399000000
+#define S400M   400000000
+#define S532M   532000000
+#define S600M   600000000
+#define S658M   658000000
+#define S660M   660000000
+#define S798M   798000000
+
+
+extern const struct prcm_config omap2420_rate_table[];
+extern const struct prcm_config omap2430_rate_table[];
+extern const struct prcm_config *rate_table;
+extern const struct prcm_config *curr_prcm_set;
+
+#endif
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 8baa30d2acfb..860b755d2220 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -326,7 +326,7 @@ int pm_dbg_regset_save(int reg_set)
         return 0;
 }
 
-static const char pwrdm_state_names[][4] = {
+static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
         "OFF",
         "RET",
         "INA",
@@ -381,7 +381,7 @@ static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
 
         seq_printf(s, "%s (%s)", pwrdm->name,
                         pwrdm_state_names[pwrdm->state]);
-        for (i = 0; i < 4; i++)
+        for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
                 seq_printf(s, ",%s:%d", pwrdm_state_names[i],
                         pwrdm->state_counter[i]);
 
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index b6990e377783..26b3f3ee82a3 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -10,9 +10,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#ifdef CONFIG_OMAP_DEBUG_POWERDOMAIN
-# define DEBUG
-#endif
+#undef DEBUG
 
 #include <linux/kernel.h>
 #include <linux/module.h>
@@ -160,7 +158,7 @@ static __init void _pwrdm_setup(struct powerdomain *pwrdm)
 {
         int i;
 
-        for (i = 0; i < 4; i++)
+        for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
                 pwrdm->state_counter[i] = 0;
 
         pwrdm_wait_transition(pwrdm);
@@ -480,7 +478,7 @@ int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
         if (IS_ERR(p)) {
                 pr_debug("powerdomain: hardware cannot set/clear wake up of "
                          "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
-                return IS_ERR(p);
+                return PTR_ERR(p);
         }
 
         pr_debug("powerdomain: hardware will wake up %s when %s wakes up\n",
@@ -513,7 +511,7 @@ int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
         if (IS_ERR(p)) {
                 pr_debug("powerdomain: hardware cannot set/clear wake up of "
                          "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
-                return IS_ERR(p);
+                return PTR_ERR(p);
         }
 
         pr_debug("powerdomain: hardware will no longer wake up %s after %s "
@@ -550,7 +548,7 @@ int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
         if (IS_ERR(p)) {
                 pr_debug("powerdomain: hardware cannot set/clear wake up of "
                          "%s when %s wakes up\n", pwrdm1->name, pwrdm2->name);
-                return IS_ERR(p);
+                return PTR_ERR(p);
         }
 
         return prm_read_mod_bits_shift(pwrdm1->prcm_offs, PM_WKDEP,
@@ -573,10 +571,10 @@ int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
 {
         struct powerdomain *p;
 
-        if (!pwrdm1)
+        if (!cpu_is_omap34xx())
                 return -EINVAL;
 
-        if (!cpu_is_omap34xx())
+        if (!pwrdm1)
                 return -EINVAL;
 
         p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
@@ -584,7 +582,7 @@ int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
                 pr_debug("powerdomain: hardware cannot set/clear sleep "
                          "dependency affecting %s from %s\n", pwrdm1->name,
                          pwrdm2->name);
-                return IS_ERR(p);
+                return PTR_ERR(p);
         }
 
         pr_debug("powerdomain: will prevent %s from sleeping if %s is active\n",
@@ -612,10 +610,10 @@ int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
 {
         struct powerdomain *p;
 
-        if (!pwrdm1)
+        if (!cpu_is_omap34xx())
                 return -EINVAL;
 
-        if (!cpu_is_omap34xx())
+        if (!pwrdm1)
                 return -EINVAL;
 
         p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
@@ -623,7 +621,7 @@ int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
                 pr_debug("powerdomain: hardware cannot set/clear sleep "
                          "dependency affecting %s from %s\n", pwrdm1->name,
                          pwrdm2->name);
-                return IS_ERR(p);
+                return PTR_ERR(p);
         }
 
         pr_debug("powerdomain: will no longer prevent %s from sleeping if "
@@ -655,10 +653,10 @@ int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
 {
         struct powerdomain *p;
 
-        if (!pwrdm1)
+        if (!cpu_is_omap34xx())
                 return -EINVAL;
 
-        if (!cpu_is_omap34xx())
+        if (!pwrdm1)
                 return -EINVAL;
 
         p = _pwrdm_deps_lookup(pwrdm2, pwrdm1->sleepdep_srcs);
@@ -666,7 +664,7 @@ int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2)
                 pr_debug("powerdomain: hardware cannot set/clear sleep "
                          "dependency affecting %s from %s\n", pwrdm1->name,
                          pwrdm2->name);
-                return IS_ERR(p);
+                return PTR_ERR(p);
         }
 
         return prm_read_mod_bits_shift(pwrdm1->prcm_offs, OMAP3430_CM_SLEEPDEP,
@@ -985,6 +983,9 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
         if (pwrdm->banks < (bank + 1))
                 return -EEXIST;
 
+        if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
+                bank = 1;
+
         /*
          * The register bit names below may not correspond to the
          * actual names of the bits in each powerdomain's register,
@@ -1032,6 +1033,9 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
         if (pwrdm->banks < (bank + 1))
                 return -EEXIST;
 
+        if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
+                bank = 1;
+
         /*
          * The register bit names below may not correspond to the
          * actual names of the bits in each powerdomain's register,
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index fd09b0827df0..588f7e07d0ea 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -190,6 +190,7 @@ static struct powerdomain mpu_34xx_pwrdm = {
         .wkdep_srcs       = mpu_34xx_wkdeps,
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .flags            = PWRDM_HAS_MPU_QUIRK,
         .banks            = 1,
         .pwrsts_mem_ret   = {
                 [0] = PWRSTS_OFF_RET,
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index cb1ae84e0925..61ac2a418bd0 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -4,10 +4,12 @@
 /*
  * OMAP2/3 PRCM base and module definitions
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
+ * OMAP4 defines in this file are automatically generated from the OMAP hardware
+ * databases.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -49,6 +51,73 @@
 #define OMAP3430_NEON_MOD                               0xb00
 #define OMAP3430ES2_USBHOST_MOD                         0xc00
 
+#define BITS(n_bit)     \
+        (((1 << n_bit) - 1) | (1 << n_bit))
+
+#define BITFIELD(l_bit, u_bit)  \
+        (BITS(u_bit) & ~((BITS(l_bit)) >> 1))
+
+/* OMAP44XX specific module offsets */
+
+/* CM1 instances */
+
+#define OMAP4430_CM1_OCP_SOCKET_MOD     0x0000
+#define OMAP4430_CM1_CKGEN_MOD          0x0100
+#define OMAP4430_CM1_MPU_MOD            0x0300
+#define OMAP4430_CM1_TESLA_MOD          0x0400
+#define OMAP4430_CM1_ABE_MOD            0x0500
+#define OMAP4430_CM1_RESTORE_MOD        0x0e00
+#define OMAP4430_CM1_INSTR_MOD          0x0f00
+
+/* CM2 instances */
+
+#define OMAP4430_CM2_OCP_SOCKET_MOD     0x0000
+#define OMAP4430_CM2_CKGEN_MOD          0x0100
+#define OMAP4430_CM2_ALWAYS_ON_MOD      0x0600
+#define OMAP4430_CM2_CORE_MOD           0x0700
+#define OMAP4430_CM2_IVAHD_MOD          0x0f00
+#define OMAP4430_CM2_CAM_MOD            0x1000
+#define OMAP4430_CM2_DSS_MOD            0x1100
+#define OMAP4430_CM2_GFX_MOD            0x1200
+#define OMAP4430_CM2_L3INIT_MOD         0x1300
+#define OMAP4430_CM2_L4PER_MOD          0x1400
+#define OMAP4430_CM2_CEFUSE_MOD         0x1600
+#define OMAP4430_CM2_RESTORE_MOD        0x1e00
+#define OMAP4430_CM2_INSTR_MOD          0x1f00
+
+/* PRM instances */
+
+#define OMAP4430_PRM_OCP_SOCKET_MOD     0x0000
+#define OMAP4430_PRM_CKGEN_MOD          0x0100
+#define OMAP4430_PRM_MPU_MOD            0x0300
+#define OMAP4430_PRM_TESLA_MOD          0x0400
+#define OMAP4430_PRM_ABE_MOD            0x0500
+#define OMAP4430_PRM_ALWAYS_ON_MOD      0x0600
+#define OMAP4430_PRM_CORE_MOD           0x0700
+#define OMAP4430_PRM_IVAHD_MOD          0x0f00
+#define OMAP4430_PRM_CAM_MOD            0x1000
+#define OMAP4430_PRM_DSS_MOD            0x1100
+#define OMAP4430_PRM_GFX_MOD            0x1200
+#define OMAP4430_PRM_L3INIT_MOD         0x1300
+#define OMAP4430_PRM_L4PER_MOD          0x1400
+#define OMAP4430_PRM_CEFUSE_MOD         0x1600
+#define OMAP4430_PRM_WKUP_MOD           0x1700
+#define OMAP4430_PRM_WKUP_CM_MOD        0x1800
+#define OMAP4430_PRM_EMU_MOD            0x1900
+#define OMAP4430_PRM_EMU_CM_MOD         0x1a00
+#define OMAP4430_PRM_DEVICE_MOD         0x1b00
+#define OMAP4430_PRM_INSTR_MOD          0x1f00
+
+/* SCRM instances */
+
+#define OMAP4430_SCRM_SCRM_MOD  0x0000
+
+/* CHIRONSS instances */
+
+#define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD  0x0000
+#define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD       0x0200
+#define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD             0x0400
+#define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD             0x0800
 
 /* 24XX register bits shared between CM & PRM registers */
 
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 029d376198d4..3ea8177ffb25 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -34,6 +34,7 @@
 
 static void __iomem *prm_base;
 static void __iomem *cm_base;
+static void __iomem *cm2_base;
 
 #define MAX_MODULE_ENABLE_WAIT          100000
 
@@ -170,14 +171,12 @@ u32 prm_read_mod_reg(s16 module, u16 idx)
 {
         return __omap_prcm_read(prm_base, module, idx);
 }
-EXPORT_SYMBOL(prm_read_mod_reg);
 
 /* Write into a register in a PRM module */
 void prm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
         __omap_prcm_write(val, prm_base, module, idx);
 }
-EXPORT_SYMBOL(prm_write_mod_reg);
 
 /* Read-modify-write a register in a PRM module. Caller must lock */
 u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
@@ -191,21 +190,18 @@ u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 
         return v;
 }
-EXPORT_SYMBOL(prm_rmw_mod_reg_bits);
 
 /* Read a register in a CM module */
 u32 cm_read_mod_reg(s16 module, u16 idx)
 {
         return __omap_prcm_read(cm_base, module, idx);
 }
-EXPORT_SYMBOL(cm_read_mod_reg);
 
 /* Write into a register in a CM module */
 void cm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
         __omap_prcm_write(val, cm_base, module, idx);
 }
-EXPORT_SYMBOL(cm_write_mod_reg);
 
 /* Read-modify-write a register in a CM module. Caller must lock */
 u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
@@ -219,7 +215,6 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 
         return v;
 }
-EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
 
 /**
  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
@@ -247,9 +242,8 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
                 BUG();
 
         /* Wait for lock */
-        while (((__raw_readl(reg) & mask) != ena) &&
-               (i++ < MAX_MODULE_ENABLE_WAIT))
-                udelay(1);
+        omap_test_timeout(((__raw_readl(reg) & mask) == ena),
+                          MAX_MODULE_ENABLE_WAIT, i);
 
         if (i < MAX_MODULE_ENABLE_WAIT)
                 pr_debug("cm: Module associated with clock %s ready after %d "
@@ -265,6 +259,7 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 {
         prm_base = omap2_globals->prm;
         cm_base = omap2_globals->cm;
+        cm2_base = omap2_globals->cm2;
 }
 
 #ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
new file mode 100644
index 000000000000..301c810fb269
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -0,0 +1,2205 @@
+/*
+ * OMAP44xx Power Management register bits
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
+
+#include "prm.h"
+
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT                                (1 << 1)
+#define OMAP4430_ABBOFF_ACT_EXPORT_MASK                                 BITFIELD(1, 1)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT                              (1 << 2)
+#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK                               BITFIELD(2, 2)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_ABB_IVA_DONE_EN_SHIFT                                  (1 << 31)
+#define OMAP4430_ABB_IVA_DONE_EN_MASK                                   BITFIELD(31, 31)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_ABB_IVA_DONE_ST_SHIFT                                  (1 << 31)
+#define OMAP4430_ABB_IVA_DONE_ST_MASK                                   BITFIELD(31, 31)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_ABB_MPU_DONE_EN_SHIFT                                  (1 << 7)
+#define OMAP4430_ABB_MPU_DONE_EN_MASK                                   BITFIELD(7, 7)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_ABB_MPU_DONE_ST_SHIFT                                  (1 << 7)
+#define OMAP4430_ABB_MPU_DONE_ST_MASK                                   BITFIELD(7, 7)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_ACTIVE_FBB_SEL_SHIFT                                   (1 << 2)
+#define OMAP4430_ACTIVE_FBB_SEL_MASK                                    BITFIELD(2, 2)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_ACTIVE_RBB_SEL_SHIFT                                   (1 << 1)
+#define OMAP4430_ACTIVE_RBB_SEL_MASK                                    BITFIELD(1, 1)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP4430_AESSMEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_AESSMEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP4430_AESSMEM_RETSTATE_SHIFT                                 (1 << 8)
+#define OMAP4430_AESSMEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+
+/* Used by PM_ABE_PWRSTST */
+#define OMAP4430_AESSMEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_AESSMEM_STATEST_MASK                                   BITFIELD(4, 5)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_AIPOFF_SHIFT                                           (1 << 8)
+#define OMAP4430_AIPOFF_MASK                                            BITFIELD(8, 8)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT                             (1 << 0)
+#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK                              BITFIELD(0, 1)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT                              (1 << 4)
+#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK                               BITFIELD(4, 5)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT                              (1 << 2)
+#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK                               BITFIELD(2, 3)
+
+/* Used by PM_CAM_PWRSTCTRL */
+#define OMAP4430_CAM_MEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_CAM_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+
+/* Used by PM_CAM_PWRSTST */
+#define OMAP4430_CAM_MEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_CAM_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+
+/* Used by PRM_CLKREQCTRL */
+#define OMAP4430_CLKREQ_COND_SHIFT                                      (1 << 0)
+#define OMAP4430_CLKREQ_COND_MASK                                       BITFIELD(0, 2)
+
+/* Used by PRM_VC_VAL_SMPS_RA_CMD */
+#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT                                 (1 << 0)
+#define OMAP4430_CMDRA_VDD_CORE_L_MASK                                  BITFIELD(0, 7)
+
+/* Used by PRM_VC_VAL_SMPS_RA_CMD */
+#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT                                  (1 << 8)
+#define OMAP4430_CMDRA_VDD_IVA_L_MASK                                   BITFIELD(8, 15)
+
+/* Used by PRM_VC_VAL_SMPS_RA_CMD */
+#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT                                  (1 << 16)
+#define OMAP4430_CMDRA_VDD_MPU_L_MASK                                   BITFIELD(16, 23)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_CMD_VDD_CORE_L_SHIFT                                   (1 << 4)
+#define OMAP4430_CMD_VDD_CORE_L_MASK                                    BITFIELD(4, 4)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_CMD_VDD_IVA_L_SHIFT                                    (1 << 12)
+#define OMAP4430_CMD_VDD_IVA_L_MASK                                     BITFIELD(12, 12)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_CMD_VDD_MPU_L_SHIFT                                    (1 << 17)
+#define OMAP4430_CMD_VDD_MPU_L_MASK                                     BITFIELD(17, 17)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT                              (1 << 18)
+#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK                               BITFIELD(18, 19)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT                             (1 << 9)
+#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK                              BITFIELD(9, 9)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT                              (1 << 6)
+#define OMAP4430_CORE_OCMRAM_STATEST_MASK                               BITFIELD(6, 7)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT                          (1 << 16)
+#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK                           BITFIELD(16, 17)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT                         (1 << 8)
+#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK                          BITFIELD(8, 8)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT                          (1 << 4)
+#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK                           BITFIELD(4, 5)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP4430_DATA_SHIFT                                             (1 << 16)
+#define OMAP4430_DATA_MASK                                              BITFIELD(16, 23)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT                                (1 << 0)
+#define OMAP4430_DEVICE_OFF_ENABLE_MASK                                 BITFIELD(0, 0)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP4430_DFILTEREN_SHIFT                                        (1 << 6)
+#define OMAP4430_DFILTEREN_MASK                                         BITFIELD(6, 6)
+
+/* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
+#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT                                (1 << 4)
+#define OMAP4430_DPLL_ABE_RECAL_EN_MASK                                 BITFIELD(4, 4)
+
+/* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
+#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT                                (1 << 4)
+#define OMAP4430_DPLL_ABE_RECAL_ST_MASK                                 BITFIELD(4, 4)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT                               (1 << 0)
+#define OMAP4430_DPLL_CORE_RECAL_EN_MASK                                BITFIELD(0, 0)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT                               (1 << 0)
+#define OMAP4430_DPLL_CORE_RECAL_ST_MASK                                BITFIELD(0, 0)
+
+/* Used by PRM_IRQENABLE_MPU */
+#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT                             (1 << 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK                              BITFIELD(6, 6)
+
+/* Used by PRM_IRQSTATUS_MPU */
+#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT                             (1 << 6)
+#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK                              BITFIELD(6, 6)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
+#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT                                (1 << 2)
+#define OMAP4430_DPLL_IVA_RECAL_EN_MASK                                 BITFIELD(2, 2)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
+#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT                                (1 << 2)
+#define OMAP4430_DPLL_IVA_RECAL_ST_MASK                                 BITFIELD(2, 2)
+
+/* Used by PRM_IRQENABLE_MPU */
+#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT                                (1 << 1)
+#define OMAP4430_DPLL_MPU_RECAL_EN_MASK                                 BITFIELD(1, 1)
+
+/* Used by PRM_IRQSTATUS_MPU */
+#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT                                (1 << 1)
+#define OMAP4430_DPLL_MPU_RECAL_ST_MASK                                 BITFIELD(1, 1)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT                                (1 << 3)
+#define OMAP4430_DPLL_PER_RECAL_EN_MASK                                 BITFIELD(3, 3)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT                                (1 << 3)
+#define OMAP4430_DPLL_PER_RECAL_ST_MASK                                 BITFIELD(3, 3)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT                             (1 << 7)
+#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK                              BITFIELD(7, 7)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT                             (1 << 7)
+#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK                              BITFIELD(7, 7)
+
+/* Used by PRM_IRQENABLE_MPU */
+#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT                                (1 << 5)
+#define OMAP4430_DPLL_USB_RECAL_EN_MASK                                 BITFIELD(5, 5)
+
+/* Used by PRM_IRQSTATUS_MPU */
+#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT                                (1 << 5)
+#define OMAP4430_DPLL_USB_RECAL_ST_MASK                                 BITFIELD(5, 5)
+
+/* Used by PM_DSS_PWRSTCTRL */
+#define OMAP4430_DSS_MEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_DSS_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+
+/* Used by PM_DSS_PWRSTCTRL */
+#define OMAP4430_DSS_MEM_RETSTATE_SHIFT                                 (1 << 8)
+#define OMAP4430_DSS_MEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+
+/* Used by PM_DSS_PWRSTST */
+#define OMAP4430_DSS_MEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_DSS_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT                             (1 << 20)
+#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK                              BITFIELD(20, 21)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT                            (1 << 10)
+#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK                             BITFIELD(10, 10)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT                             (1 << 8)
+#define OMAP4430_DUCATI_L2RAM_STATEST_MASK                              BITFIELD(8, 9)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT                          (1 << 22)
+#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK                           BITFIELD(22, 23)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT                         (1 << 11)
+#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK                          BITFIELD(11, 11)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT                          (1 << 10)
+#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK                           BITFIELD(10, 11)
+
+/* Used by RM_MPU_RSTST */
+#define OMAP4430_EMULATION_RST_SHIFT                                    (1 << 0)
+#define OMAP4430_EMULATION_RST_MASK                                     BITFIELD(0, 0)
+
+/* Used by RM_DUCATI_RSTST */
+#define OMAP4430_EMULATION_RST1ST_SHIFT                                 (1 << 3)
+#define OMAP4430_EMULATION_RST1ST_MASK                                  BITFIELD(3, 3)
+
+/* Used by RM_DUCATI_RSTST */
+#define OMAP4430_EMULATION_RST2ST_SHIFT                                 (1 << 4)
+#define OMAP4430_EMULATION_RST2ST_MASK                                  BITFIELD(4, 4)
+
+/* Used by RM_IVAHD_RSTST */
+#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT                            (1 << 3)
+#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK                             BITFIELD(3, 3)
+
+/* Used by RM_IVAHD_RSTST */
+#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT                            (1 << 4)
+#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK                             BITFIELD(4, 4)
+
+/* Used by PM_EMU_PWRSTCTRL */
+#define OMAP4430_EMU_BANK_ONSTATE_SHIFT                                 (1 << 16)
+#define OMAP4430_EMU_BANK_ONSTATE_MASK                                  BITFIELD(16, 17)
+
+/* Used by PM_EMU_PWRSTST */
+#define OMAP4430_EMU_BANK_STATEST_SHIFT                                 (1 << 4)
+#define OMAP4430_EMU_BANK_STATEST_MASK                                  BITFIELD(4, 5)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
+ */
+#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT                                (1 << 0)
+#define OMAP4430_ENABLE_RTA_EXPORT_MASK                                 BITFIELD(0, 0)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_ENFUNC1_SHIFT                                          (1 << 3)
+#define OMAP4430_ENFUNC1_MASK                                           BITFIELD(3, 3)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_ENFUNC3_SHIFT                                          (1 << 5)
+#define OMAP4430_ENFUNC3_MASK                                           BITFIELD(5, 5)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_ENFUNC4_SHIFT                                          (1 << 6)
+#define OMAP4430_ENFUNC4_MASK                                           BITFIELD(6, 6)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
+ * PRM_LDO_SRAM_MPU_SETUP
+ */
+#define OMAP4430_ENFUNC5_SHIFT                                          (1 << 7)
+#define OMAP4430_ENFUNC5_MASK                                           BITFIELD(7, 7)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_ERRORGAIN_SHIFT                                        (1 << 16)
+#define OMAP4430_ERRORGAIN_MASK                                         BITFIELD(16, 23)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_ERROROFFSET_SHIFT                                      (1 << 24)
+#define OMAP4430_ERROROFFSET_MASK                                       BITFIELD(24, 31)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_EXTERNAL_WARM_RST_SHIFT                                (1 << 5)
+#define OMAP4430_EXTERNAL_WARM_RST_MASK                                 BITFIELD(5, 5)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_FORCEUPDATE_SHIFT                                      (1 << 1)
+#define OMAP4430_FORCEUPDATE_MASK                                       BITFIELD(1, 1)
+
+/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+#define OMAP4430_FORCEUPDATEWAIT_SHIFT                                  (1 << 8)
+#define OMAP4430_FORCEUPDATEWAIT_MASK                                   BITFIELD(8, 31)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
+#define OMAP4430_FORCEWKUP_EN_SHIFT                                     (1 << 10)
+#define OMAP4430_FORCEWKUP_EN_MASK                                      BITFIELD(10, 10)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
+#define OMAP4430_FORCEWKUP_ST_SHIFT                                     (1 << 10)
+#define OMAP4430_FORCEWKUP_ST_MASK                                      BITFIELD(10, 10)
+
+/* Used by PM_GFX_PWRSTCTRL */
+#define OMAP4430_GFX_MEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_GFX_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+
+/* Used by PM_GFX_PWRSTST */
+#define OMAP4430_GFX_MEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_GFX_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_GLOBAL_COLD_RST_SHIFT                                  (1 << 0)
+#define OMAP4430_GLOBAL_COLD_RST_MASK                                   BITFIELD(0, 0)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT                               (1 << 1)
+#define OMAP4430_GLOBAL_WARM_SW_RST_MASK                                BITFIELD(1, 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_GLOBAL_WUEN_SHIFT                                      (1 << 16)
+#define OMAP4430_GLOBAL_WUEN_MASK                                       BITFIELD(16, 16)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP4430_HSMCODE_SHIFT                                          (1 << 0)
+#define OMAP4430_HSMCODE_MASK                                           BITFIELD(0, 2)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP4430_HSMODEEN_SHIFT                                         (1 << 3)
+#define OMAP4430_HSMODEEN_MASK                                          BITFIELD(3, 3)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP4430_HSSCLH_SHIFT                                           (1 << 16)
+#define OMAP4430_HSSCLH_MASK                                            BITFIELD(16, 23)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP4430_HSSCLL_SHIFT                                           (1 << 24)
+#define OMAP4430_HSSCLL_MASK                                            BITFIELD(24, 31)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_HWA_MEM_ONSTATE_SHIFT                                  (1 << 16)
+#define OMAP4430_HWA_MEM_ONSTATE_MASK                                   BITFIELD(16, 17)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_HWA_MEM_RETSTATE_SHIFT                                 (1 << 8)
+#define OMAP4430_HWA_MEM_RETSTATE_MASK                                  BITFIELD(8, 8)
+
+/* Used by PM_IVAHD_PWRSTST */
+#define OMAP4430_HWA_MEM_STATEST_SHIFT                                  (1 << 4)
+#define OMAP4430_HWA_MEM_STATEST_MASK                                   BITFIELD(4, 5)
+
+/* Used by RM_MPU_RSTST */
+#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT                               (1 << 1)
+#define OMAP4430_ICECRUSHER_MPU_RST_MASK                                BITFIELD(1, 1)
+
+/* Used by RM_DUCATI_RSTST */
+#define OMAP4430_ICECRUSHER_RST1ST_SHIFT                                (1 << 5)
+#define OMAP4430_ICECRUSHER_RST1ST_MASK                                 BITFIELD(5, 5)
+
+/* Used by RM_DUCATI_RSTST */
+#define OMAP4430_ICECRUSHER_RST2ST_SHIFT                                (1 << 6)
+#define OMAP4430_ICECRUSHER_RST2ST_MASK                                 BITFIELD(6, 6)
+
+/* Used by RM_IVAHD_RSTST */
+#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT                           (1 << 5)
+#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK                            BITFIELD(5, 5)
+
+/* Used by RM_IVAHD_RSTST */
+#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT                           (1 << 6)
+#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK                            BITFIELD(6, 6)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_ICEPICK_RST_SHIFT                                      (1 << 9)
+#define OMAP4430_ICEPICK_RST_MASK                                       BITFIELD(9, 9)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_INITVDD_SHIFT                                          (1 << 2)
+#define OMAP4430_INITVDD_MASK                                           BITFIELD(2, 2)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_INITVOLTAGE_SHIFT                                      (1 << 8)
+#define OMAP4430_INITVOLTAGE_MASK                                       BITFIELD(8, 15)
+
+/*
+ * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ */
+#define OMAP4430_INTRANSITION_SHIFT                                     (1 << 20)
+#define OMAP4430_INTRANSITION_MASK                                      BITFIELD(20, 20)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_IO_EN_SHIFT                                            (1 << 9)
+#define OMAP4430_IO_EN_MASK                                             BITFIELD(9, 9)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_IO_ON_STATUS_SHIFT                                     (1 << 5)
+#define OMAP4430_IO_ON_STATUS_MASK                                      BITFIELD(5, 5)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_IO_ST_SHIFT                                            (1 << 9)
+#define OMAP4430_IO_ST_MASK                                             BITFIELD(9, 9)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_ISOCLK_OVERRIDE_SHIFT                                  (1 << 0)
+#define OMAP4430_ISOCLK_OVERRIDE_MASK                                   BITFIELD(0, 0)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_ISOCLK_STATUS_SHIFT                                    (1 << 1)
+#define OMAP4430_ISOCLK_STATUS_MASK                                     BITFIELD(1, 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_ISOOVR_EXTEND_SHIFT                                    (1 << 4)
+#define OMAP4430_ISOOVR_EXTEND_MASK                                     BITFIELD(4, 4)
+
+/* Used by PRM_IO_COUNT */
+#define OMAP4430_ISO_2_ON_TIME_SHIFT                                    (1 << 0)
+#define OMAP4430_ISO_2_ON_TIME_MASK                                     BITFIELD(0, 7)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT                             (1 << 16)
+#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK                              BITFIELD(16, 17)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT                            (1 << 8)
+#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK                             BITFIELD(8, 8)
+
+/* Used by PM_L3INIT_PWRSTST */
+#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT                             (1 << 4)
+#define OMAP4430_L3INIT_BANK1_STATEST_MASK                              BITFIELD(4, 5)
+
+/*
+ * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL,
+ * PM_IVAHD_PWRSTCTRL
+ */
+#define OMAP4430_LOGICRETSTATE_SHIFT                                    (1 << 2)
+#define OMAP4430_LOGICRETSTATE_MASK                                     BITFIELD(2, 2)
+
+/*
+ * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ */
+#define OMAP4430_LOGICSTATEST_SHIFT                                     (1 << 2)
+#define OMAP4430_LOGICSTATEST_MASK                                      BITFIELD(2, 2)
+
+/*
+ * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT,
+ * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT,
+ * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT,
+ * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT,
+ * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT,
+ * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
+ * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT,
+ * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT,
+ * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT,
+ * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT,
+ * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
+ * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
+ * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
+ * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
+ * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
+ * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
+ * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
+ * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
+ * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT,
+ * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT,
+ * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT,
+ * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT,
+ * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT,
+ * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT,
+ * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT,
+ * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
+ * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT,
+ * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT,
+ * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
+ * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
+ * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
+ * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT,
+ * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT,
+ * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT
+ */
+#define OMAP4430_LOSTCONTEXT_DFF_SHIFT                                  (1 << 0)
+#define OMAP4430_LOSTCONTEXT_DFF_MASK                                   BITFIELD(0, 0)
+
+/*
+ * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
+ * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
+ * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
+ * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
+ * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT,
+ * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
+ * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT,
+ * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT,
+ * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT,
+ * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT,
+ * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT,
+ * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT,
+ * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
+ * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT,
+ * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT,
+ * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT
+ */
+#define OMAP4430_LOSTCONTEXT_RFF_SHIFT                                  (1 << 1)
+#define OMAP4430_LOSTCONTEXT_RFF_MASK                                   BITFIELD(1, 1)
+
+/* Used by RM_ABE_AESS_CONTEXT */
+#define OMAP4430_LOSTMEM_AESSMEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_AESSMEM_MASK                                   BITFIELD(8, 8)
+
+/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
+#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_CAM_MEM_MASK                                   BITFIELD(8, 8)
+
+/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT                           (1 << 8)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK                            BITFIELD(8, 8)
+
+/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT                       (1 << 9)
+#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK                        BITFIELD(9, 9)
+
+/* Used by RM_L3_2_OCMC_RAM_CONTEXT */
+#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT                              (1 << 8)
+#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK                               BITFIELD(8, 8)
+
+/*
+ * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
+ * RM_SDMA_SDMA_CONTEXT
+ */
+#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT                          (1 << 8)
+#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK                           BITFIELD(8, 8)
+
+/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
+#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_DSS_MEM_MASK                                   BITFIELD(8, 8)
+
+/* Used by RM_DUCATI_DUCATI_CONTEXT */
+#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT                             (1 << 9)
+#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK                              BITFIELD(9, 9)
+
+/* Used by RM_DUCATI_DUCATI_CONTEXT */
+#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT                          (1 << 8)
+#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK                           BITFIELD(8, 8)
+
+/* Used by RM_EMU_DEBUGSS_CONTEXT */
+#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT                                 (1 << 8)
+#define OMAP4430_LOSTMEM_EMU_BANK_MASK                                  BITFIELD(8, 8)
+
+/* Used by RM_GFX_GFX_CONTEXT */
+#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_GFX_MEM_MASK                                   BITFIELD(8, 8)
+
+/* Used by RM_IVAHD_IVAHD_CONTEXT */
+#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT                                  (1 << 10)
+#define OMAP4430_LOSTMEM_HWA_MEM_MASK                                   BITFIELD(10, 10)
+
+/*
+ * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
+ * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT,
+ * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
+ * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
+ */
+#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT                             (1 << 8)
+#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK                              BITFIELD(8, 8)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define OMAP4430_LOSTMEM_MPU_L1_SHIFT                                   (1 << 8)
+#define OMAP4430_LOSTMEM_MPU_L1_MASK                                    BITFIELD(8, 8)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define OMAP4430_LOSTMEM_MPU_L2_SHIFT                                   (1 << 9)
+#define OMAP4430_LOSTMEM_MPU_L2_MASK                                    BITFIELD(9, 9)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT                                  (1 << 10)
+#define OMAP4430_LOSTMEM_MPU_RAM_MASK                                   BITFIELD(10, 10)
+
+/*
+ * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
+ * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
+ * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
+ */
+#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT                         (1 << 8)
+#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK                          BITFIELD(8, 8)
+
+/*
+ * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
+ * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
+ */
+#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT                                (1 << 8)
+#define OMAP4430_LOSTMEM_PERIHPMEM_MASK                                 BITFIELD(8, 8)
+
+/*
+ * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
+ * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
+ * RM_L4SEC_CRYPTODMA_CONTEXT
+ */
+#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT                            (1 << 8)
+#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK                             BITFIELD(8, 8)
+
+/* Used by RM_IVAHD_SL2_CONTEXT */
+#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT                                  (1 << 8)
+#define OMAP4430_LOSTMEM_SL2_MEM_MASK                                   BITFIELD(8, 8)
+
+/* Used by RM_IVAHD_IVAHD_CONTEXT */
+#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT                                 (1 << 8)
+#define OMAP4430_LOSTMEM_TCM1_MEM_MASK                                  BITFIELD(8, 8)
+
+/* Used by RM_IVAHD_IVAHD_CONTEXT */
+#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT                                 (1 << 9)
+#define OMAP4430_LOSTMEM_TCM2_MEM_MASK                                  BITFIELD(9, 9)
+
+/* Used by RM_TESLA_TESLA_CONTEXT */
+#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT                               (1 << 10)
+#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK                                BITFIELD(10, 10)
+
+/* Used by RM_TESLA_TESLA_CONTEXT */
+#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT                                 (1 << 8)
+#define OMAP4430_LOSTMEM_TESLA_L1_MASK                                  BITFIELD(8, 8)
+
+/* Used by RM_TESLA_TESLA_CONTEXT */
+#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT                                 (1 << 9)
+#define OMAP4430_LOSTMEM_TESLA_L2_MASK                                  BITFIELD(9, 9)
+
+/* Used by RM_WKUP_SARRAM_CONTEXT */
+#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT                                (1 << 8)
+#define OMAP4430_LOSTMEM_WKUP_BANK_MASK                                 BITFIELD(8, 8)
+
+/*
+ * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
+ * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
+ * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
+ */
+#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT                              (1 << 4)
+#define OMAP4430_LOWPOWERSTATECHANGE_MASK                               BITFIELD(4, 4)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_MEMORYCHANGE_SHIFT                                     (1 << 3)
+#define OMAP4430_MEMORYCHANGE_MASK                                      BITFIELD(3, 3)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP4430_MODEM_READY_SHIFT                                      (1 << 1)
+#define OMAP4430_MODEM_READY_MASK                                       BITFIELD(1, 1)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT                               (1 << 9)
+#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK                                BITFIELD(9, 9)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP4430_MODEM_SLEEP_ST_SHIFT                                   (1 << 16)
+#define OMAP4430_MODEM_SLEEP_ST_MASK                                    BITFIELD(16, 16)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP4430_MODEM_WAKE_IRQ_SHIFT                                   (1 << 8)
+#define OMAP4430_MODEM_WAKE_IRQ_MASK                                    BITFIELD(8, 8)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP4430_MPU_L1_ONSTATE_SHIFT                                   (1 << 16)
+#define OMAP4430_MPU_L1_ONSTATE_MASK                                    BITFIELD(16, 17)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP4430_MPU_L1_RETSTATE_SHIFT                                  (1 << 8)
+#define OMAP4430_MPU_L1_RETSTATE_MASK                                   BITFIELD(8, 8)
+
+/* Used by PM_MPU_PWRSTST */
+#define OMAP4430_MPU_L1_STATEST_SHIFT                                   (1 << 4)
+#define OMAP4430_MPU_L1_STATEST_MASK                                    BITFIELD(4, 5)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP4430_MPU_L2_ONSTATE_SHIFT                                   (1 << 18)
+#define OMAP4430_MPU_L2_ONSTATE_MASK                                    BITFIELD(18, 19)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP4430_MPU_L2_RETSTATE_SHIFT                                  (1 << 9)
+#define OMAP4430_MPU_L2_RETSTATE_MASK                                   BITFIELD(9, 9)
+
+/* Used by PM_MPU_PWRSTST */
+#define OMAP4430_MPU_L2_STATEST_SHIFT                                   (1 << 6)
+#define OMAP4430_MPU_L2_STATEST_MASK                                    BITFIELD(6, 7)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP4430_MPU_RAM_ONSTATE_SHIFT                                  (1 << 20)
+#define OMAP4430_MPU_RAM_ONSTATE_MASK                                   BITFIELD(20, 21)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP4430_MPU_RAM_RETSTATE_SHIFT                                 (1 << 10)
+#define OMAP4430_MPU_RAM_RETSTATE_MASK                                  BITFIELD(10, 10)
+
+/* Used by PM_MPU_PWRSTST */
+#define OMAP4430_MPU_RAM_STATEST_SHIFT                                  (1 << 8)
+#define OMAP4430_MPU_RAM_STATEST_MASK                                   BITFIELD(8, 9)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT                            (1 << 2)
+#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK                             BITFIELD(2, 2)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_MPU_WDT_RST_SHIFT                                      (1 << 3)
+#define OMAP4430_MPU_WDT_RST_MASK                                       BITFIELD(3, 3)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT                         (1 << 18)
+#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK                          BITFIELD(18, 19)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT                        (1 << 9)
+#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK                         BITFIELD(9, 9)
+
+/* Used by PM_L4PER_PWRSTST */
+#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT                         (1 << 6)
+#define OMAP4430_NONRETAINED_BANK_STATEST_MASK                          BITFIELD(6, 7)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT                            (1 << 24)
+#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK                             BITFIELD(24, 25)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT                           (1 << 12)
+#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK                            BITFIELD(12, 12)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT                            (1 << 12)
+#define OMAP4430_OCP_NRET_BANK_STATEST_MASK                             BITFIELD(12, 13)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP4430_OFF_SHIFT                                              (1 << 0)
+#define OMAP4430_OFF_MASK                                               BITFIELD(0, 7)
+
+/* Used by PRM_LDO_BANDGAP_CTRL */
+#define OMAP4430_OFF_ENABLE_SHIFT                                       (1 << 0)
+#define OMAP4430_OFF_ENABLE_MASK                                        BITFIELD(0, 0)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP4430_ON_SHIFT                                               (1 << 24)
+#define OMAP4430_ON_MASK                                                BITFIELD(24, 31)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP4430_ONLP_SHIFT                                             (1 << 16)
+#define OMAP4430_ONLP_MASK                                              BITFIELD(16, 23)
+
+/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+#define OMAP4430_OPP_CHANGE_SHIFT                                       (1 << 2)
+#define OMAP4430_OPP_CHANGE_MASK                                        BITFIELD(2, 2)
+
+/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+#define OMAP4430_OPP_SEL_SHIFT                                          (1 << 0)
+#define OMAP4430_OPP_SEL_MASK                                           BITFIELD(0, 1)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP4430_PCHARGECNT_VALUE_SHIFT                                 (1 << 0)
+#define OMAP4430_PCHARGECNT_VALUE_MASK                                  BITFIELD(0, 5)
+
+/* Used by PRM_PSCON_COUNT */
+#define OMAP4430_PCHARGE_TIME_SHIFT                                     (1 << 0)
+#define OMAP4430_PCHARGE_TIME_MASK                                      BITFIELD(0, 7)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT                                (1 << 20)
+#define OMAP4430_PERIPHMEM_ONSTATE_MASK                                 BITFIELD(20, 21)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT                               (1 << 10)
+#define OMAP4430_PERIPHMEM_RETSTATE_MASK                                BITFIELD(10, 10)
+
+/* Used by PM_ABE_PWRSTST */
+#define OMAP4430_PERIPHMEM_STATEST_SHIFT                                (1 << 8)
+#define OMAP4430_PERIPHMEM_STATEST_MASK                                 BITFIELD(8, 9)
+
+/* Used by PRM_PHASE1_CNDP */
+#define OMAP4430_PHASE1_CNDP_SHIFT                                      (1 << 0)
+#define OMAP4430_PHASE1_CNDP_MASK                                       BITFIELD(0, 31)
+
+/* Used by PRM_PHASE2A_CNDP */
+#define OMAP4430_PHASE2A_CNDP_SHIFT                                     (1 << 0)
+#define OMAP4430_PHASE2A_CNDP_MASK                                      BITFIELD(0, 31)
+
+/* Used by PRM_PHASE2B_CNDP */
+#define OMAP4430_PHASE2B_CNDP_SHIFT                                     (1 << 0)
+#define OMAP4430_PHASE2B_CNDP_MASK                                      BITFIELD(0, 31)
+
+/* Used by PRM_PSCON_COUNT */
+#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT                            (1 << 8)
+#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK                             BITFIELD(8, 15)
+
+/*
+ * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL,
+ * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL,
+ * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
+ * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL
+ */
+#define OMAP4430_POWERSTATE_SHIFT                                       (1 << 0)
+#define OMAP4430_POWERSTATE_MASK                                        BITFIELD(0, 1)
+
+/*
+ * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST,
+ * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST
+ */
+#define OMAP4430_POWERSTATEST_SHIFT                                     (1 << 0)
+#define OMAP4430_POWERSTATEST_MASK                                      BITFIELD(0, 1)
+
+/* Used by PRM_PWRREQCTRL */
+#define OMAP4430_PWRREQ_COND_SHIFT                                      (1 << 0)
+#define OMAP4430_PWRREQ_COND_MASK                                       BITFIELD(0, 1)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RACEN_VDD_CORE_L_SHIFT                                 (1 << 3)
+#define OMAP4430_RACEN_VDD_CORE_L_MASK                                  BITFIELD(3, 3)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RACEN_VDD_IVA_L_SHIFT                                  (1 << 11)
+#define OMAP4430_RACEN_VDD_IVA_L_MASK                                   BITFIELD(11, 11)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RACEN_VDD_MPU_L_SHIFT                                  (1 << 20)
+#define OMAP4430_RACEN_VDD_MPU_L_MASK                                   BITFIELD(20, 20)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RAC_VDD_CORE_L_SHIFT                                   (1 << 2)
+#define OMAP4430_RAC_VDD_CORE_L_MASK                                    BITFIELD(2, 2)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RAC_VDD_IVA_L_SHIFT                                    (1 << 10)
+#define OMAP4430_RAC_VDD_IVA_L_MASK                                     BITFIELD(10, 10)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RAC_VDD_MPU_L_SHIFT                                    (1 << 19)
+#define OMAP4430_RAC_VDD_MPU_L_MASK                                     BITFIELD(19, 19)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP4430_RAMP_DOWN_COUNT_SHIFT                                  (1 << 16)
+#define OMAP4430_RAMP_DOWN_COUNT_MASK                                   BITFIELD(16, 21)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT                                (1 << 24)
+#define OMAP4430_RAMP_DOWN_PRESCAL_MASK                                 BITFIELD(24, 25)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP4430_RAMP_UP_COUNT_SHIFT                                    (1 << 0)
+#define OMAP4430_RAMP_UP_COUNT_MASK                                     BITFIELD(0, 5)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP4430_RAMP_UP_PRESCAL_SHIFT                                  (1 << 8)
+#define OMAP4430_RAMP_UP_PRESCAL_MASK                                   BITFIELD(8, 9)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RAV_VDD_CORE_L_SHIFT                                   (1 << 1)
+#define OMAP4430_RAV_VDD_CORE_L_MASK                                    BITFIELD(1, 1)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RAV_VDD_IVA_L_SHIFT                                    (1 << 9)
+#define OMAP4430_RAV_VDD_IVA_L_MASK                                     BITFIELD(9, 9)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_RAV_VDD_MPU_L_SHIFT                                    (1 << 18)
+#define OMAP4430_RAV_VDD_MPU_L_MASK                                     BITFIELD(18, 18)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP4430_REGADDR_SHIFT                                          (1 << 8)
+#define OMAP4430_REGADDR_MASK                                           BITFIELD(8, 15)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP4430_RET_SHIFT                                              (1 << 8)
+#define OMAP4430_RET_MASK                                               BITFIELD(8, 15)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT                            (1 << 16)
+#define OMAP4430_RETAINED_BANK_ONSTATE_MASK                             BITFIELD(16, 17)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT                           (1 << 8)
+#define OMAP4430_RETAINED_BANK_RETSTATE_MASK                            BITFIELD(8, 8)
+
+/* Used by PM_L4PER_PWRSTST */
+#define OMAP4430_RETAINED_BANK_STATEST_SHIFT                            (1 << 4)
+#define OMAP4430_RETAINED_BANK_STATEST_MASK                             BITFIELD(4, 5)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
+ * PRM_LDO_SRAM_MPU_CTRL
+ */
+#define OMAP4430_RETMODE_ENABLE_SHIFT                                   (1 << 0)
+#define OMAP4430_RETMODE_ENABLE_MASK                                    BITFIELD(0, 0)
+
+/* Used by REVISION_PRM */
+#define OMAP4430_REV_SHIFT                                              (1 << 0)
+#define OMAP4430_REV_MASK                                               BITFIELD(0, 7)
+
+/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
+#define OMAP4430_RST1_SHIFT                                             (1 << 0)
+#define OMAP4430_RST1_MASK                                              BITFIELD(0, 0)
+
+/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
+#define OMAP4430_RST1ST_SHIFT                                           (1 << 0)
+#define OMAP4430_RST1ST_MASK                                            BITFIELD(0, 0)
+
+/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
+#define OMAP4430_RST2_SHIFT                                             (1 << 1)
+#define OMAP4430_RST2_MASK                                              BITFIELD(1, 1)
+
+/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */
+#define OMAP4430_RST2ST_SHIFT                                           (1 << 1)
+#define OMAP4430_RST2ST_MASK                                            BITFIELD(1, 1)
+
+/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
+#define OMAP4430_RST3_SHIFT                                             (1 << 2)
+#define OMAP4430_RST3_MASK                                              BITFIELD(2, 2)
+
+/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
+#define OMAP4430_RST3ST_SHIFT                                           (1 << 2)
+#define OMAP4430_RST3ST_MASK                                            BITFIELD(2, 2)
+
+/* Used by PRM_RSTTIME */
+#define OMAP4430_RSTTIME1_SHIFT                                         (1 << 0)
+#define OMAP4430_RSTTIME1_MASK                                          BITFIELD(0, 9)
+
+/* Used by PRM_RSTTIME */
+#define OMAP4430_RSTTIME2_SHIFT                                         (1 << 10)
+#define OMAP4430_RSTTIME2_MASK                                          BITFIELD(10, 14)
+
+/* Used by PRM_RSTCTRL */
+#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT                               (1 << 1)
+#define OMAP4430_RST_GLOBAL_COLD_SW_MASK                                BITFIELD(1, 1)
+
+/* Used by PRM_RSTCTRL */
+#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT                               (1 << 0)
+#define OMAP4430_RST_GLOBAL_WARM_SW_MASK                                BITFIELD(0, 0)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_SA_VDD_CORE_L_SHIFT                                    (1 << 0)
+#define OMAP4430_SA_VDD_CORE_L_MASK                                     BITFIELD(0, 0)
+
+/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
+#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT                                (1 << 0)
+#define OMAP4430_SA_VDD_CORE_L_0_6_MASK                                 BITFIELD(0, 6)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_SA_VDD_IVA_L_SHIFT                                     (1 << 8)
+#define OMAP4430_SA_VDD_IVA_L_MASK                                      BITFIELD(8, 8)
+
+/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
+#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT                      (1 << 8)
+#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK                       BITFIELD(8, 14)
+
+/* Used by PRM_VC_CFG_CHANNEL */
+#define OMAP4430_SA_VDD_MPU_L_SHIFT                                     (1 << 16)
+#define OMAP4430_SA_VDD_MPU_L_MASK                                      BITFIELD(16, 16)
+
+/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
+#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT                      (1 << 16)
+#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK                       BITFIELD(16, 22)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP4430_SCLH_SHIFT                                             (1 << 0)
+#define OMAP4430_SCLH_MASK                                              BITFIELD(0, 7)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP4430_SCLL_SHIFT                                             (1 << 8)
+#define OMAP4430_SCLL_MASK                                              BITFIELD(8, 15)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_SECURE_WDT_RST_SHIFT                                   (1 << 4)
+#define OMAP4430_SECURE_WDT_RST_MASK                                    BITFIELD(4, 4)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_SL2_MEM_ONSTATE_SHIFT                                  (1 << 18)
+#define OMAP4430_SL2_MEM_ONSTATE_MASK                                   BITFIELD(18, 19)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_SL2_MEM_RETSTATE_SHIFT                                 (1 << 9)
+#define OMAP4430_SL2_MEM_RETSTATE_MASK                                  BITFIELD(9, 9)
+
+/* Used by PM_IVAHD_PWRSTST */
+#define OMAP4430_SL2_MEM_STATEST_SHIFT                                  (1 << 6)
+#define OMAP4430_SL2_MEM_STATEST_MASK                                   BITFIELD(6, 7)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP4430_SLAVEADDR_SHIFT                                        (1 << 0)
+#define OMAP4430_SLAVEADDR_MASK                                         BITFIELD(0, 6)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_SLEEP_RBB_SEL_SHIFT                                    (1 << 3)
+#define OMAP4430_SLEEP_RBB_SEL_MASK                                     BITFIELD(3, 3)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP4430_SLPCNT_VALUE_SHIFT                                     (1 << 16)
+#define OMAP4430_SLPCNT_VALUE_MASK                                      BITFIELD(16, 23)
+
+/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+#define OMAP4430_SMPSWAITTIMEMAX_SHIFT                                  (1 << 8)
+#define OMAP4430_SMPSWAITTIMEMAX_MASK                                   BITFIELD(8, 23)
+
+/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+#define OMAP4430_SMPSWAITTIMEMIN_SHIFT                                  (1 << 8)
+#define OMAP4430_SMPSWAITTIMEMIN_MASK                                   BITFIELD(8, 23)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_SR2EN_SHIFT                                            (1 << 0)
+#define OMAP4430_SR2EN_MASK                                             BITFIELD(0, 0)
+
+/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+#define OMAP4430_SR2_IN_TRANSITION_SHIFT                                (1 << 6)
+#define OMAP4430_SR2_IN_TRANSITION_MASK                                 BITFIELD(6, 6)
+
+/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
+#define OMAP4430_SR2_STATUS_SHIFT                                       (1 << 3)
+#define OMAP4430_SR2_STATUS_MASK                                        BITFIELD(3, 4)
+
+/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
+#define OMAP4430_SR2_WTCNT_VALUE_SHIFT                                  (1 << 8)
+#define OMAP4430_SR2_WTCNT_VALUE_MASK                                   BITFIELD(8, 15)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
+ * PRM_LDO_SRAM_MPU_CTRL
+ */
+#define OMAP4430_SRAMLDO_STATUS_SHIFT                                   (1 << 8)
+#define OMAP4430_SRAMLDO_STATUS_MASK                                    BITFIELD(8, 8)
+
+/*
+ * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
+ * PRM_LDO_SRAM_MPU_CTRL
+ */
+#define OMAP4430_SRAM_IN_TRANSITION_SHIFT                               (1 << 9)
+#define OMAP4430_SRAM_IN_TRANSITION_MASK                                BITFIELD(9, 9)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP4430_SRMODEEN_SHIFT                                         (1 << 4)
+#define OMAP4430_SRMODEEN_MASK                                          BITFIELD(4, 4)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define OMAP4430_STABLE_COUNT_SHIFT                                     (1 << 0)
+#define OMAP4430_STABLE_COUNT_MASK                                      BITFIELD(0, 5)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define OMAP4430_STABLE_PRESCAL_SHIFT                                   (1 << 8)
+#define OMAP4430_STABLE_PRESCAL_MASK                                    BITFIELD(8, 9)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT                                 (1 << 20)
+#define OMAP4430_TCM1_MEM_ONSTATE_MASK                                  BITFIELD(20, 21)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT                                (1 << 10)
+#define OMAP4430_TCM1_MEM_RETSTATE_MASK                                 BITFIELD(10, 10)
+
+/* Used by PM_IVAHD_PWRSTST */
+#define OMAP4430_TCM1_MEM_STATEST_SHIFT                                 (1 << 8)
+#define OMAP4430_TCM1_MEM_STATEST_MASK                                  BITFIELD(8, 9)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT                                 (1 << 22)
+#define OMAP4430_TCM2_MEM_ONSTATE_MASK                                  BITFIELD(22, 23)
+
+/* Used by PM_IVAHD_PWRSTCTRL */
+#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT                                (1 << 11)
+#define OMAP4430_TCM2_MEM_RETSTATE_MASK                                 BITFIELD(11, 11)
+
+/* Used by PM_IVAHD_PWRSTST */
+#define OMAP4430_TCM2_MEM_STATEST_SHIFT                                 (1 << 10)
+#define OMAP4430_TCM2_MEM_STATEST_MASK                                  BITFIELD(10, 11)
+
+/* Used by RM_TESLA_RSTST */
+#define OMAP4430_TESLASS_EMU_RSTST_SHIFT                                (1 << 2)
+#define OMAP4430_TESLASS_EMU_RSTST_MASK                                 BITFIELD(2, 2)
+
+/* Used by RM_TESLA_RSTST */
+#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT                          (1 << 3)
+#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK                           BITFIELD(3, 3)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT                               (1 << 20)
+#define OMAP4430_TESLA_EDMA_ONSTATE_MASK                                BITFIELD(20, 21)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT                              (1 << 10)
+#define OMAP4430_TESLA_EDMA_RETSTATE_MASK                               BITFIELD(10, 10)
+
+/* Used by PM_TESLA_PWRSTST */
+#define OMAP4430_TESLA_EDMA_STATEST_SHIFT                               (1 << 8)
+#define OMAP4430_TESLA_EDMA_STATEST_MASK                                BITFIELD(8, 9)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_L1_ONSTATE_SHIFT                                 (1 << 16)
+#define OMAP4430_TESLA_L1_ONSTATE_MASK                                  BITFIELD(16, 17)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_L1_RETSTATE_SHIFT                                (1 << 8)
+#define OMAP4430_TESLA_L1_RETSTATE_MASK                                 BITFIELD(8, 8)
+
+/* Used by PM_TESLA_PWRSTST */
+#define OMAP4430_TESLA_L1_STATEST_SHIFT                                 (1 << 4)
+#define OMAP4430_TESLA_L1_STATEST_MASK                                  BITFIELD(4, 5)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_L2_ONSTATE_SHIFT                                 (1 << 18)
+#define OMAP4430_TESLA_L2_ONSTATE_MASK                                  BITFIELD(18, 19)
+
+/* Used by PM_TESLA_PWRSTCTRL */
+#define OMAP4430_TESLA_L2_RETSTATE_SHIFT                                (1 << 9)
+#define OMAP4430_TESLA_L2_RETSTATE_MASK                                 BITFIELD(9, 9)
+
+/* Used by PM_TESLA_PWRSTST */
+#define OMAP4430_TESLA_L2_STATEST_SHIFT                                 (1 << 6)
+#define OMAP4430_TESLA_L2_STATEST_MASK                                  BITFIELD(6, 7)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP4430_TIMEOUT_SHIFT                                          (1 << 0)
+#define OMAP4430_TIMEOUT_MASK                                           BITFIELD(0, 15)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_TIMEOUTEN_SHIFT                                        (1 << 3)
+#define OMAP4430_TIMEOUTEN_MASK                                         BITFIELD(3, 3)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_TRANSITION_EN_SHIFT                                    (1 << 8)
+#define OMAP4430_TRANSITION_EN_MASK                                     BITFIELD(8, 8)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_TRANSITION_ST_SHIFT                                    (1 << 8)
+#define OMAP4430_TRANSITION_ST_MASK                                     BITFIELD(8, 8)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP4430_VALID_SHIFT                                            (1 << 24)
+#define OMAP4430_VALID_MASK                                             BITFIELD(24, 24)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_BYPASSACK_EN_SHIFT                                  (1 << 14)
+#define OMAP4430_VC_BYPASSACK_EN_MASK                                   BITFIELD(14, 14)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_BYPASSACK_ST_SHIFT                                  (1 << 14)
+#define OMAP4430_VC_BYPASSACK_ST_MASK                                   BITFIELD(14, 14)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_IVA_VPACK_EN_SHIFT                                  (1 << 30)
+#define OMAP4430_VC_IVA_VPACK_EN_MASK                                   BITFIELD(30, 30)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_IVA_VPACK_ST_SHIFT                                  (1 << 30)
+#define OMAP4430_VC_IVA_VPACK_ST_MASK                                   BITFIELD(30, 30)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VC_MPU_VPACK_EN_SHIFT                                  (1 << 6)
+#define OMAP4430_VC_MPU_VPACK_EN_MASK                                   BITFIELD(6, 6)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VC_MPU_VPACK_ST_SHIFT                                  (1 << 6)
+#define OMAP4430_VC_MPU_VPACK_ST_MASK                                   BITFIELD(6, 6)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_RAERR_EN_SHIFT                                      (1 << 12)
+#define OMAP4430_VC_RAERR_EN_MASK                                       BITFIELD(12, 12)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_RAERR_ST_SHIFT                                      (1 << 12)
+#define OMAP4430_VC_RAERR_ST_MASK                                       BITFIELD(12, 12)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_SAERR_EN_SHIFT                                      (1 << 11)
+#define OMAP4430_VC_SAERR_EN_MASK                                       BITFIELD(11, 11)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_SAERR_ST_SHIFT                                      (1 << 11)
+#define OMAP4430_VC_SAERR_ST_MASK                                       BITFIELD(11, 11)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VC_TOERR_EN_SHIFT                                      (1 << 13)
+#define OMAP4430_VC_TOERR_EN_MASK                                       BITFIELD(13, 13)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VC_TOERR_ST_SHIFT                                      (1 << 13)
+#define OMAP4430_VC_TOERR_ST_MASK                                       BITFIELD(13, 13)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP4430_VDDMAX_SHIFT                                           (1 << 24)
+#define OMAP4430_VDDMAX_MASK                                            BITFIELD(24, 31)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP4430_VDDMIN_SHIFT                                           (1 << 16)
+#define OMAP4430_VDDMIN_MASK                                            BITFIELD(16, 23)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT                             (1 << 12)
+#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK                              BITFIELD(12, 12)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT                            (1 << 8)
+#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK                             BITFIELD(8, 8)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT                              (1 << 14)
+#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK                               BITFIELD(14, 14)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_IVA_PRESENCE_SHIFT                                 (1 << 9)
+#define OMAP4430_VDD_IVA_PRESENCE_MASK                                  BITFIELD(9, 9)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT                             (1 << 7)
+#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK                              BITFIELD(7, 7)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT                              (1 << 13)
+#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK                               BITFIELD(13, 13)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP4430_VDD_MPU_PRESENCE_SHIFT                                 (1 << 8)
+#define OMAP4430_VDD_MPU_PRESENCE_MASK                                  BITFIELD(8, 8)
+
+/* Used by PRM_RSTST */
+#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT                             (1 << 6)
+#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK                              BITFIELD(6, 6)
+
+/* Used by PRM_VC_VAL_SMPS_RA_VOL */
+#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT                                 (1 << 0)
+#define OMAP4430_VOLRA_VDD_CORE_L_MASK                                  BITFIELD(0, 7)
+
+/* Used by PRM_VC_VAL_SMPS_RA_VOL */
+#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT                                  (1 << 8)
+#define OMAP4430_VOLRA_VDD_IVA_L_MASK                                   BITFIELD(8, 15)
+
+/* Used by PRM_VC_VAL_SMPS_RA_VOL */
+#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT                                  (1 << 16)
+#define OMAP4430_VOLRA_VDD_MPU_L_MASK                                   BITFIELD(16, 23)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP4430_VPENABLE_SHIFT                                         (1 << 0)
+#define OMAP4430_VPENABLE_MASK                                          BITFIELD(0, 0)
+
+/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
+#define OMAP4430_VPINIDLE_SHIFT                                         (1 << 0)
+#define OMAP4430_VPINIDLE_MASK                                          BITFIELD(0, 0)
+
+/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+#define OMAP4430_VPVOLTAGE_SHIFT                                        (1 << 0)
+#define OMAP4430_VPVOLTAGE_MASK                                         BITFIELD(0, 7)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT                               (1 << 20)
+#define OMAP4430_VP_CORE_EQVALUE_EN_MASK                                BITFIELD(20, 20)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT                               (1 << 20)
+#define OMAP4430_VP_CORE_EQVALUE_ST_MASK                                BITFIELD(20, 20)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT                                (1 << 18)
+#define OMAP4430_VP_CORE_MAXVDD_EN_MASK                                 BITFIELD(18, 18)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT                                (1 << 18)
+#define OMAP4430_VP_CORE_MAXVDD_ST_MASK                                 BITFIELD(18, 18)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT                                (1 << 17)
+#define OMAP4430_VP_CORE_MINVDD_EN_MASK                                 BITFIELD(17, 17)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT                                (1 << 17)
+#define OMAP4430_VP_CORE_MINVDD_ST_MASK                                 BITFIELD(17, 17)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT                             (1 << 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK                              BITFIELD(19, 19)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT                             (1 << 19)
+#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK                              BITFIELD(19, 19)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT                         (1 << 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK                          BITFIELD(16, 16)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT                         (1 << 16)
+#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK                          BITFIELD(16, 16)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT                             (1 << 21)
+#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK                              BITFIELD(21, 21)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT                             (1 << 21)
+#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK                              BITFIELD(21, 21)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT                                (1 << 28)
+#define OMAP4430_VP_IVA_EQVALUE_EN_MASK                                 BITFIELD(28, 28)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT                                (1 << 28)
+#define OMAP4430_VP_IVA_EQVALUE_ST_MASK                                 BITFIELD(28, 28)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT                                 (1 << 26)
+#define OMAP4430_VP_IVA_MAXVDD_EN_MASK                                  BITFIELD(26, 26)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT                                 (1 << 26)
+#define OMAP4430_VP_IVA_MAXVDD_ST_MASK                                  BITFIELD(26, 26)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT                                 (1 << 25)
+#define OMAP4430_VP_IVA_MINVDD_EN_MASK                                  BITFIELD(25, 25)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT                                 (1 << 25)
+#define OMAP4430_VP_IVA_MINVDD_ST_MASK                                  BITFIELD(25, 25)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT                              (1 << 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK                               BITFIELD(27, 27)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT                              (1 << 27)
+#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK                               BITFIELD(27, 27)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT                          (1 << 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK                           BITFIELD(24, 24)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT                          (1 << 24)
+#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK                           BITFIELD(24, 24)
+
+/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
+#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT                              (1 << 29)
+#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK                               BITFIELD(29, 29)
+
+/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
+#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT                              (1 << 29)
+#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK                               BITFIELD(29, 29)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT                                (1 << 4)
+#define OMAP4430_VP_MPU_EQVALUE_EN_MASK                                 BITFIELD(4, 4)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT                                (1 << 4)
+#define OMAP4430_VP_MPU_EQVALUE_ST_MASK                                 BITFIELD(4, 4)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT                                 (1 << 2)
+#define OMAP4430_VP_MPU_MAXVDD_EN_MASK                                  BITFIELD(2, 2)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT                                 (1 << 2)
+#define OMAP4430_VP_MPU_MAXVDD_ST_MASK                                  BITFIELD(2, 2)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT                                 (1 << 1)
+#define OMAP4430_VP_MPU_MINVDD_EN_MASK                                  BITFIELD(1, 1)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT                                 (1 << 1)
+#define OMAP4430_VP_MPU_MINVDD_ST_MASK                                  BITFIELD(1, 1)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT                              (1 << 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK                               BITFIELD(3, 3)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT                              (1 << 3)
+#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK                               BITFIELD(3, 3)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT                          (1 << 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK                           BITFIELD(0, 0)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT                          (1 << 0)
+#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK                           BITFIELD(0, 0)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT                              (1 << 5)
+#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK                               BITFIELD(5, 5)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT                              (1 << 5)
+#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK                               BITFIELD(5, 5)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP4430_VSETUPCNT_VALUE_SHIFT                                  (1 << 8)
+#define OMAP4430_VSETUPCNT_VALUE_MASK                                   BITFIELD(8, 15)
+
+/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+#define OMAP4430_VSTEPMAX_SHIFT                                         (1 << 0)
+#define OMAP4430_VSTEPMAX_MASK                                          BITFIELD(0, 7)
+
+/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+#define OMAP4430_VSTEPMIN_SHIFT                                         (1 << 0)
+#define OMAP4430_VSTEPMIN_MASK                                          BITFIELD(0, 7)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP4430_WAKE_MODEM_SHIFT                                       (1 << 0)
+#define OMAP4430_WAKE_MODEM_MASK                                        BITFIELD(0, 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT                             (1 << 1)
+#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK                              BITFIELD(1, 1)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_DISPC_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK                                BITFIELD(3, 3)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT                              (1 << 2)
+#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK                               BITFIELD(2, 2)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK                             BITFIELD(7, 7)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT                           (1 << 6)
+#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK                            BITFIELD(6, 6)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT                           (1 << 2)
+#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK                            BITFIELD(2, 2)
+
+/* Used by PM_L4PER_DMTIMER10_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT                            (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK                             BITFIELD(0, 0)
+
+/* Used by PM_L4PER_DMTIMER11_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT                         (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK                          BITFIELD(1, 1)
+
+/* Used by PM_L4PER_DMTIMER11_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT                            (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK                             BITFIELD(0, 0)
+
+/* Used by PM_L4PER_DMTIMER2_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_DMTIMER3_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_DMTIMER3_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_DMTIMER4_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_DMTIMER4_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_DMTIMER9_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_DMTIMER9_WKDEP */
+#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT                              (1 << 5)
+#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK                               BITFIELD(5, 5)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT                                 (1 << 4)
+#define OMAP4430_WKUPDEP_DSI1_MPU_MASK                                  BITFIELD(4, 4)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT                                (1 << 7)
+#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK                                 BITFIELD(7, 7)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT                               (1 << 6)
+#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK                                BITFIELD(6, 6)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT                              (1 << 9)
+#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK                               BITFIELD(9, 9)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT                                 (1 << 8)
+#define OMAP4430_WKUPDEP_DSI2_MPU_MASK                                  BITFIELD(8, 8)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT                                (1 << 11)
+#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK                                 BITFIELD(11, 11)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT                               (1 << 10)
+#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK                                BITFIELD(10, 10)
+
+/* Used by PM_WKUP_GPIO1_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT                        (1 << 1)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK                         BITFIELD(1, 1)
+
+/* Used by PM_WKUP_GPIO1_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_WKUP_GPIO1_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT                        (1 << 1)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK                         BITFIELD(1, 1)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT                             (1 << 19)
+#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK                              BITFIELD(19, 19)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT                           (1 << 13)
+#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK                            BITFIELD(13, 13)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT                              (1 << 12)
+#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK                               BITFIELD(12, 12)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT                            (1 << 14)
+#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK                             BITFIELD(14, 14)
+
+/* Used by PM_L4PER_HECC1_WKDEP */
+#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_HECC1_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_L4PER_HECC2_WKDEP */
+#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_HECC2_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT                            (1 << 6)
+#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK                             BITFIELD(6, 6)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK                            BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK                             BITFIELD(7, 7)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK                             BITFIELD(7, 7)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK                             BITFIELD(7, 7)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK                             BITFIELD(7, 7)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L4PER_I2C5_WKDEP */
+#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT                            (1 << 7)
+#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK                             BITFIELD(7, 7)
+
+/* Used by PM_L4PER_I2C5_WKDEP */
+#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_WKUP_KEYBOARD_WKDEP */
+#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT                          (1 << 7)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK                           BITFIELD(7, 7)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT                         (1 << 2)
+#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+
+/* Used by PM_L4PER_MCASP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT                          (1 << 7)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK                           BITFIELD(7, 7)
+
+/* Used by PM_L4PER_MCASP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_MCASP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCASP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT                         (1 << 2)
+#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+
+/* Used by PM_L4PER_MCASP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT                          (1 << 7)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK                           BITFIELD(7, 7)
+
+/* Used by PM_L4PER_MCASP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT                         (1 << 6)
+#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK                          BITFIELD(6, 6)
+
+/* Used by PM_L4PER_MCASP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT                           (1 << 0)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK                            BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCASP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT                         (1 << 2)
+#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK                          BITFIELD(2, 2)
+
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_L4PER_MCBSP4_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCBSP4_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L4PER_MCBSP4_WKDEP */
+#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK                             BITFIELD(1, 1)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK                             BITFIELD(1, 1)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK                               BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_MMC1_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT                                (1 << 3)
+#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK                                 BITFIELD(3, 3)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT                               (1 << 2)
+#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK                                BITFIELD(2, 2)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK                               BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_MMC2_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT                                (1 << 3)
+#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK                                 BITFIELD(3, 3)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT                               (1 << 2)
+#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK                                BITFIELD(2, 2)
+
+/* Used by PM_L3INIT_MMC6_WKDEP */
+#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK                               BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_MMC6_WKDEP */
+#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_MMC6_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_MMC6_WKDEP */
+#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT                               (1 << 2)
+#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK                                BITFIELD(2, 2)
+
+/* Used by PM_L4PER_MMCSD3_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK                             BITFIELD(1, 1)
+
+/* Used by PM_L4PER_MMCSD3_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MMCSD3_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L4PER_MMCSD4_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK                             BITFIELD(1, 1)
+
+/* Used by PM_L4PER_MMCSD4_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MMCSD4_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L4PER_MMCSD5_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK                             BITFIELD(1, 1)
+
+/* Used by PM_L4PER_MMCSD5_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L4PER_MMCSD5_WKDEP */
+#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT                              (1 << 3)
+#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK                               BITFIELD(3, 3)
+
+/* Used by PM_L3INIT_PCIESS_WKDEP */
+#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_PCIESS_WKDEP */
+#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_ABE_PDM_WKDEP */
+#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT                             (1 << 7)
+#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK                              BITFIELD(7, 7)
+
+/* Used by PM_ABE_PDM_WKDEP */
+#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT                            (1 << 6)
+#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK                             BITFIELD(6, 6)
+
+/* Used by PM_ABE_PDM_WKDEP */
+#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_ABE_PDM_WKDEP */
+#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT                            (1 << 2)
+#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK                             BITFIELD(2, 2)
+
+/* Used by PM_WKUP_RTC_WKDEP */
+#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT                                  (1 << 0)
+#define OMAP4430_WKUPDEP_RTC_MPU_MASK                                   BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_SATA_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT                               (1 << 2)
+#define OMAP4430_WKUPDEP_SATA_TESLA_MASK                                BITFIELD(2, 2)
+
+/* Used by PM_ABE_SLIMBUS_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT                        (1 << 7)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                         BITFIELD(7, 7)
+
+/* Used by PM_ABE_SLIMBUS_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT                       (1 << 6)
+#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK                        BITFIELD(6, 6)
+
+/* Used by PM_ABE_SLIMBUS_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT                         (1 << 0)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                          BITFIELD(0, 0)
+
+/* Used by PM_ABE_SLIMBUS_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT                       (1 << 2)
+#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK                        BITFIELD(2, 2)
+
+/* Used by PM_L4PER_SLIMBUS2_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT                        (1 << 7)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK                         BITFIELD(7, 7)
+
+/* Used by PM_L4PER_SLIMBUS2_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT                       (1 << 6)
+#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK                        BITFIELD(6, 6)
+
+/* Used by PM_L4PER_SLIMBUS2_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT                         (1 << 0)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK                          BITFIELD(0, 0)
+
+/* Used by PM_L4PER_SLIMBUS2_WKDEP */
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT                       (1 << 2)
+#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK                        BITFIELD(2, 2)
+
+/* Used by PM_ALWON_SR_CORE_WKDEP */
+#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK                            BITFIELD(1, 1)
+
+/* Used by PM_ALWON_SR_CORE_WKDEP */
+#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_ALWON_SR_IVA_WKDEP */
+#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT                            (1 << 1)
+#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK                             BITFIELD(1, 1)
+
+/* Used by PM_ALWON_SR_IVA_WKDEP */
+#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ALWON_SR_MPU_WKDEP */
+#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_WKUP_TIMER12_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_WKUP_TIMER1_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_TIMER5_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_TIMER5_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_ABE_TIMER6_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_TIMER6_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_ABE_TIMER7_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_TIMER7_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_ABE_TIMER8_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT                               (1 << 0)
+#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK                                BITFIELD(0, 0)
+
+/* Used by PM_ABE_TIMER8_WKDEP */
+#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT                             (1 << 2)
+#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK                              BITFIELD(2, 2)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_UART1_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_UART1_SDMA_MASK                                BITFIELD(3, 3)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_UART2_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_UART2_SDMA_MASK                                BITFIELD(3, 3)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT                             (1 << 1)
+#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK                              BITFIELD(1, 1)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_UART3_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_UART3_SDMA_MASK                                BITFIELD(3, 3)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT                              (1 << 2)
+#define OMAP4430_WKUPDEP_UART3_TESLA_MASK                               BITFIELD(2, 2)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT                                (1 << 0)
+#define OMAP4430_WKUPDEP_UART4_MPU_MASK                                 BITFIELD(0, 0)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT                               (1 << 3)
+#define OMAP4430_WKUPDEP_UART4_SDMA_MASK                                BITFIELD(3, 3)
+
+/* Used by PM_L3INIT_UNIPRO1_WKDEP */
+#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK                            BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_UNIPRO1_WKDEP */
+#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_USB_HOST_WKDEP */
+#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT                          (1 << 1)
+#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK                           BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
+#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT                       (1 << 1)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK                        BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
+#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT                          (1 << 0)
+#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK                           BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_USB_HOST_WKDEP */
+#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT                             (1 << 0)
+#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK                              BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_USB_OTG_WKDEP */
+#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK                            BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_USB_OTG_WKDEP */
+#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_USB_TLL_WKDEP */
+#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT                           (1 << 1)
+#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK                            BITFIELD(1, 1)
+
+/* Used by PM_L3INIT_USB_TLL_WKDEP */
+#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT                              (1 << 0)
+#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK                               BITFIELD(0, 0)
+
+/* Used by PM_WKUP_USIM_WKDEP */
+#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_USIM_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_WKUP_USIM_WKDEP */
+#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT                                (1 << 3)
+#define OMAP4430_WKUPDEP_USIM_SDMA_MASK                                 BITFIELD(3, 3)
+
+/* Used by PM_WKUP_WDT2_WKDEP */
+#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK                               BITFIELD(1, 1)
+
+/* Used by PM_WKUP_WDT2_WKDEP */
+#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_WDT2_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_ABE_WDT3_WKDEP */
+#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT                                 (1 << 0)
+#define OMAP4430_WKUPDEP_WDT3_MPU_MASK                                  BITFIELD(0, 0)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT                         (1 << 8)
+#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK                          BITFIELD(8, 8)
+
+/* Used by PM_L3INIT_XHPI_WKDEP */
+#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT                              (1 << 1)
+#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK                               BITFIELD(1, 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_WUCLK_CTRL_SHIFT                                       (1 << 8)
+#define OMAP4430_WUCLK_CTRL_MASK                                        BITFIELD(8, 8)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP4430_WUCLK_STATUS_SHIFT                                     (1 << 9)
+#define OMAP4430_WUCLK_STATUS_MASK                                      BITFIELD(9, 9)
+#endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index a117f853ea39..ea050ce188a7 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -4,8 +4,8 @@
 /*
  * OMAP2/3 Power/Reset Management (PRM) register definitions
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  *
@@ -22,6 +22,10 @@
                 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
 #define OMAP34XX_PRM_REGADDR(module, reg)                               \
                 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+#define OMAP44XX_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
+
+#include "prm44xx.h"
 
 /*
  * Architecture-specific global PRM registers
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
new file mode 100644
index 000000000000..89be97f0589d
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -0,0 +1,411 @@
+/*
+ * OMAP44xx PRM instance offset macros
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
+
+
+/* PRM */
+
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define OMAP4430_REVISION_PRM                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000)
+#define OMAP4430_PRM_IRQSTATUS_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010)
+#define OMAP4430_PRM_IRQSTATUS_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014)
+#define OMAP4430_PRM_IRQENABLE_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018)
+#define OMAP4430_PRM_IRQENABLE_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c)
+#define OMAP4430_PRM_IRQSTATUS_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020)
+#define OMAP4430_PRM_IRQENABLE_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028)
+#define OMAP4430_PRM_IRQSTATUS_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
+#define OMAP4430_PRM_IRQENABLE_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
+#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
+
+/* PRM.CKGEN_PRM register offsets */
+#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
+#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
+#define OMAP4430_CM_L4_WKUP_CLKSEL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
+#define OMAP4430_CM_ABE_PLL_REF_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c)
+#define OMAP4430_CM_SYS_CLKSEL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010)
+
+/* PRM.MPU_PRM register offsets */
+#define OMAP4430_PM_MPU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000)
+#define OMAP4430_PM_MPU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004)
+#define OMAP4430_RM_MPU_RSTST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014)
+#define OMAP4430_RM_MPU_MPU_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024)
+
+/* PRM.TESLA_PRM register offsets */
+#define OMAP4430_PM_TESLA_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000)
+#define OMAP4430_PM_TESLA_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004)
+#define OMAP4430_RM_TESLA_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010)
+#define OMAP4430_RM_TESLA_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014)
+#define OMAP4430_RM_TESLA_TESLA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024)
+
+/* PRM.ABE_PRM register offsets */
+#define OMAP4430_PM_ABE_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000)
+#define OMAP4430_PM_ABE_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004)
+#define OMAP4430_RM_ABE_AESS_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c)
+#define OMAP4430_PM_ABE_PDM_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030)
+#define OMAP4430_RM_ABE_PDM_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034)
+#define OMAP4430_PM_ABE_DMIC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038)
+#define OMAP4430_RM_ABE_DMIC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c)
+#define OMAP4430_PM_ABE_MCASP_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040)
+#define OMAP4430_RM_ABE_MCASP_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044)
+#define OMAP4430_PM_ABE_MCBSP1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048)
+#define OMAP4430_RM_ABE_MCBSP1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c)
+#define OMAP4430_PM_ABE_MCBSP2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050)
+#define OMAP4430_RM_ABE_MCBSP2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054)
+#define OMAP4430_PM_ABE_MCBSP3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058)
+#define OMAP4430_RM_ABE_MCBSP3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c)
+#define OMAP4430_PM_ABE_SLIMBUS_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060)
+#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064)
+#define OMAP4430_PM_ABE_TIMER5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068)
+#define OMAP4430_RM_ABE_TIMER5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c)
+#define OMAP4430_PM_ABE_TIMER6_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070)
+#define OMAP4430_RM_ABE_TIMER6_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074)
+#define OMAP4430_PM_ABE_TIMER7_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078)
+#define OMAP4430_RM_ABE_TIMER7_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c)
+#define OMAP4430_PM_ABE_TIMER8_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080)
+#define OMAP4430_RM_ABE_TIMER8_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084)
+#define OMAP4430_PM_ABE_WDT3_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088)
+#define OMAP4430_RM_ABE_WDT3_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c)
+
+/* PRM.ALWAYS_ON_PRM register offsets */
+#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024)
+#define OMAP4430_PM_ALWON_SR_MPU_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028)
+#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c)
+#define OMAP4430_PM_ALWON_SR_IVA_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030)
+#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034)
+#define OMAP4430_PM_ALWON_SR_CORE_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038)
+#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c)
+
+/* PRM.CORE_PRM register offsets */
+#define OMAP4430_PM_CORE_PWRSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000)
+#define OMAP4430_PM_CORE_PWRSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004)
+#define OMAP4430_RM_L3_1_L3_1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024)
+#define OMAP4430_RM_L3_2_L3_2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124)
+#define OMAP4430_RM_L3_2_GPMC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c)
+#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134)
+#define OMAP4430_RM_DUCATI_RSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210)
+#define OMAP4430_RM_DUCATI_RSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214)
+#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224)
+#define OMAP4430_RM_SDMA_SDMA_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324)
+#define OMAP4430_RM_MEMIF_DMM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424)
+#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c)
+#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434)
+#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c)
+#define OMAP4430_RM_MEMIF_DLL_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444)
+#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454)
+#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c)
+#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464)
+#define OMAP4430_RM_D2D_SAD2D_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524)
+#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c)
+#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534)
+#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624)
+#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c)
+#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634)
+#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c)
+#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724)
+#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c)
+#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744)
+
+/* PRM.IVAHD_PRM register offsets */
+#define OMAP4430_PM_IVAHD_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000)
+#define OMAP4430_PM_IVAHD_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004)
+#define OMAP4430_RM_IVAHD_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010)
+#define OMAP4430_RM_IVAHD_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014)
+#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024)
+#define OMAP4430_RM_IVAHD_SL2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c)
+
+/* PRM.CAM_PRM register offsets */
+#define OMAP4430_PM_CAM_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000)
+#define OMAP4430_PM_CAM_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004)
+#define OMAP4430_RM_CAM_ISS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024)
+#define OMAP4430_RM_CAM_FDIF_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c)
+
+/* PRM.DSS_PRM register offsets */
+#define OMAP4430_PM_DSS_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000)
+#define OMAP4430_PM_DSS_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004)
+#define OMAP4430_PM_DSS_DSS_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020)
+#define OMAP4430_RM_DSS_DSS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024)
+#define OMAP4430_RM_DSS_DEISS_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c)
+
+/* PRM.GFX_PRM register offsets */
+#define OMAP4430_PM_GFX_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000)
+#define OMAP4430_PM_GFX_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004)
+#define OMAP4430_RM_GFX_GFX_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024)
+
+/* PRM.L3INIT_PRM register offsets */
+#define OMAP4430_PM_L3INIT_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000)
+#define OMAP4430_PM_L3INIT_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004)
+#define OMAP4430_PM_L3INIT_MMC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028)
+#define OMAP4430_RM_L3INIT_MMC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c)
+#define OMAP4430_PM_L3INIT_MMC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030)
+#define OMAP4430_RM_L3INIT_MMC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034)
+#define OMAP4430_PM_L3INIT_HSI_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038)
+#define OMAP4430_RM_L3INIT_HSI_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c)
+#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040)
+#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044)
+#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058)
+#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c)
+#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060)
+#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064)
+#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068)
+#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c)
+#define OMAP4430_RM_L3INIT_P1500_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c)
+#define OMAP4430_RM_L3INIT_EMAC_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084)
+#define OMAP4430_PM_L3INIT_SATA_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088)
+#define OMAP4430_RM_L3INIT_SATA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c)
+#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094)
+#define OMAP4430_PM_L3INIT_PCIESS_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098)
+#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c)
+#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac)
+#define OMAP4430_PM_L3INIT_XHPI_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0)
+#define OMAP4430_RM_L3INIT_XHPI_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4)
+#define OMAP4430_PM_L3INIT_MMC6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8)
+#define OMAP4430_RM_L3INIT_MMC6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc)
+#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0)
+#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4)
+#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4)
+
+/* PRM.L4PER_PRM register offsets */
+#define OMAP4430_PM_L4PER_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000)
+#define OMAP4430_PM_L4PER_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004)
+#define OMAP4430_RM_L4PER_ADC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024)
+#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028)
+#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c)
+#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030)
+#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034)
+#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038)
+#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c)
+#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040)
+#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044)
+#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048)
+#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c)
+#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050)
+#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054)
+#define OMAP4430_RM_L4PER_ELM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c)
+#define OMAP4430_PM_L4PER_GPIO2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060)
+#define OMAP4430_RM_L4PER_GPIO2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064)
+#define OMAP4430_PM_L4PER_GPIO3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068)
+#define OMAP4430_RM_L4PER_GPIO3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c)
+#define OMAP4430_PM_L4PER_GPIO4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070)
+#define OMAP4430_RM_L4PER_GPIO4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074)
+#define OMAP4430_PM_L4PER_GPIO5_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078)
+#define OMAP4430_RM_L4PER_GPIO5_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c)
+#define OMAP4430_PM_L4PER_GPIO6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080)
+#define OMAP4430_RM_L4PER_GPIO6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084)
+#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c)
+#define OMAP4430_PM_L4PER_HECC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090)
+#define OMAP4430_RM_L4PER_HECC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094)
+#define OMAP4430_PM_L4PER_HECC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098)
+#define OMAP4430_RM_L4PER_HECC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c)
+#define OMAP4430_PM_L4PER_I2C1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0)
+#define OMAP4430_RM_L4PER_I2C1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4)
+#define OMAP4430_PM_L4PER_I2C2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8)
+#define OMAP4430_RM_L4PER_I2C2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac)
+#define OMAP4430_PM_L4PER_I2C3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0)
+#define OMAP4430_RM_L4PER_I2C3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4)
+#define OMAP4430_PM_L4PER_I2C4_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8)
+#define OMAP4430_RM_L4PER_I2C4_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc)
+#define OMAP4430_RM_L4PER_L4_PER_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0)
+#define OMAP4430_PM_L4PER_MCASP2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0)
+#define OMAP4430_RM_L4PER_MCASP2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4)
+#define OMAP4430_PM_L4PER_MCASP3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8)
+#define OMAP4430_RM_L4PER_MCASP3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc)
+#define OMAP4430_PM_L4PER_MCBSP4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0)
+#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4)
+#define OMAP4430_RM_L4PER_MGATE_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec)
+#define OMAP4430_PM_L4PER_MCSPI1_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0)
+#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4)
+#define OMAP4430_PM_L4PER_MCSPI2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8)
+#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc)
+#define OMAP4430_PM_L4PER_MCSPI3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100)
+#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104)
+#define OMAP4430_PM_L4PER_MCSPI4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108)
+#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c)
+#define OMAP4430_PM_L4PER_MMCSD3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120)
+#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124)
+#define OMAP4430_PM_L4PER_MMCSD4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128)
+#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c)
+#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134)
+#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138)
+#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c)
+#define OMAP4430_PM_L4PER_UART1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140)
+#define OMAP4430_RM_L4PER_UART1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144)
+#define OMAP4430_PM_L4PER_UART2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148)
+#define OMAP4430_RM_L4PER_UART2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c)
+#define OMAP4430_PM_L4PER_UART3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150)
+#define OMAP4430_RM_L4PER_UART3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154)
+#define OMAP4430_PM_L4PER_UART4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158)
+#define OMAP4430_RM_L4PER_UART4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c)
+#define OMAP4430_PM_L4PER_MMCSD5_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160)
+#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164)
+#define OMAP4430_PM_L4PER_I2C5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168)
+#define OMAP4430_RM_L4PER_I2C5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c)
+#define OMAP4430_RM_L4SEC_AES1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4)
+#define OMAP4430_RM_L4SEC_AES2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac)
+#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4)
+#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc)
+#define OMAP4430_RM_L4SEC_RNG_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4)
+#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc)
+#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc)
+
+/* PRM.CEFUSE_PRM register offsets */
+#define OMAP4430_PM_CEFUSE_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000)
+#define OMAP4430_PM_CEFUSE_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004)
+#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024)
+
+/* PRM.WKUP_PRM register offsets */
+#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024)
+#define OMAP4430_RM_WKUP_WDT1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c)
+#define OMAP4430_PM_WKUP_WDT2_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030)
+#define OMAP4430_RM_WKUP_WDT2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034)
+#define OMAP4430_PM_WKUP_GPIO1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038)
+#define OMAP4430_RM_WKUP_GPIO1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c)
+#define OMAP4430_PM_WKUP_TIMER1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040)
+#define OMAP4430_RM_WKUP_TIMER1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044)
+#define OMAP4430_PM_WKUP_TIMER12_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048)
+#define OMAP4430_RM_WKUP_TIMER12_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c)
+#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054)
+#define OMAP4430_PM_WKUP_USIM_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058)
+#define OMAP4430_RM_WKUP_USIM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c)
+#define OMAP4430_RM_WKUP_SARRAM_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064)
+#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078)
+#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c)
+#define OMAP4430_PM_WKUP_RTC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080)
+#define OMAP4430_RM_WKUP_RTC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084)
+
+/* PRM.WKUP_CM register offsets */
+#define OMAP4430_CM_WKUP_CLKSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000)
+#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020)
+#define OMAP4430_CM_WKUP_WDT1_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028)
+#define OMAP4430_CM_WKUP_WDT2_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030)
+#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038)
+#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040)
+#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048)
+#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050)
+#define OMAP4430_CM_WKUP_USIM_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058)
+#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060)
+#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078)
+#define OMAP4430_CM_WKUP_RTC_CLKCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080)
+#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088)
+
+/* PRM.EMU_PRM register offsets */
+#define OMAP4430_PM_EMU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000)
+#define OMAP4430_PM_EMU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004)
+#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024)
+
+/* PRM.EMU_CM register offsets */
+#define OMAP4430_CM_EMU_CLKSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000)
+#define OMAP4430_CM_EMU_DYNAMICDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008)
+#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020)
+
+/* PRM.DEVICE_PRM register offsets */
+#define OMAP4430_PRM_RSTCTRL                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000)
+#define OMAP4430_PRM_RSTST                              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004)
+#define OMAP4430_PRM_RSTTIME                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008)
+#define OMAP4430_PRM_CLKREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c)
+#define OMAP4430_PRM_VOLTCTRL                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010)
+#define OMAP4430_PRM_PWRREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014)
+#define OMAP4430_PRM_PSCON_COUNT                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018)
+#define OMAP4430_PRM_IO_COUNT                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c)
+#define OMAP4430_PRM_IO_PMCTRL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020)
+#define OMAP4430_PRM_VOLTSETUP_WARMRESET                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024)
+#define OMAP4430_PRM_VOLTSETUP_CORE_OFF                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028)
+#define OMAP4430_PRM_VOLTSETUP_MPU_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c)
+#define OMAP4430_PRM_VOLTSETUP_IVA_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030)
+#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034)
+#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038)
+#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c)
+#define OMAP4430_PRM_VP_CORE_CONFIG                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040)
+#define OMAP4430_PRM_VP_CORE_STATUS                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044)
+#define OMAP4430_PRM_VP_CORE_VLIMITTO                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048)
+#define OMAP4430_PRM_VP_CORE_VOLTAGE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c)
+#define OMAP4430_PRM_VP_CORE_VSTEPMAX                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050)
+#define OMAP4430_PRM_VP_CORE_VSTEPMIN                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054)
+#define OMAP4430_PRM_VP_MPU_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058)
+#define OMAP4430_PRM_VP_MPU_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c)
+#define OMAP4430_PRM_VP_MPU_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060)
+#define OMAP4430_PRM_VP_MPU_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064)
+#define OMAP4430_PRM_VP_MPU_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068)
+#define OMAP4430_PRM_VP_MPU_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c)
+#define OMAP4430_PRM_VP_IVA_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070)
+#define OMAP4430_PRM_VP_IVA_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074)
+#define OMAP4430_PRM_VP_IVA_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078)
+#define OMAP4430_PRM_VP_IVA_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c)
+#define OMAP4430_PRM_VP_IVA_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080)
+#define OMAP4430_PRM_VP_IVA_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084)
+#define OMAP4430_PRM_VC_SMPS_SA                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088)
+#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c)
+#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090)
+#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094)
+#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098)
+#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c)
+#define OMAP4430_PRM_VC_VAL_BYPASS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0)
+#define OMAP4430_PRM_VC_CFG_CHANNEL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4)
+#define OMAP4430_PRM_VC_CFG_I2C_MODE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8)
+#define OMAP4430_PRM_VC_CFG_I2C_CLK                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac)
+#define OMAP4430_PRM_SRAM_COUNT                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0)
+#define OMAP4430_PRM_SRAM_WKUP_SETUP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4)
+#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8)
+#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc)
+#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0)
+#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4)
+#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8)
+#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc)
+#define OMAP4430_PRM_LDO_ABB_MPU_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0)
+#define OMAP4430_PRM_LDO_ABB_MPU_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4)
+#define OMAP4430_PRM_LDO_ABB_IVA_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
+#define OMAP4430_PRM_LDO_ABB_IVA_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
+#define OMAP4430_PRM_LDO_BANDGAP_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
+#define OMAP4430_PRM_DEVICE_OFF_CTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
+#define OMAP4430_PRM_PHASE1_CNDP                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8)
+#define OMAP4430_PRM_PHASE2A_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec)
+#define OMAP4430_PRM_PHASE2B_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
+#define OMAP4430_PRM_MODEM_IF_CTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
+
+/* CHIRON_PRCM */
+
+
+/* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */
+#define OMAP4430_REVISION_PRCM                          OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000)
+
+/* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */
+#define OMAP4430_CHIRON_PRCM_PRM_RSTST                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000)
+
+/* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */
+#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000)
+#define OMAP4430_PM_PDA_CPU0_PWRSTST                    OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004)
+#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008)
+#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c)
+#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST                 OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010)
+#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014)
+#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018)
+
+/* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */
+#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000)
+#define OMAP4430_PM_PDA_CPU1_PWRSTST                    OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004)
+#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008)
+#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c)
+#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST                 OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010)
+#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014)
+#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018)
+#endif
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 48207b018989..68f57bb67fc5 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -18,6 +18,9 @@
 #include <plat/sdrc.h>
 
 #ifndef __ASSEMBLER__
+
+#include <linux/io.h>
+
 extern void __iomem *omap2_sdrc_base;
 extern void __iomem *omap2_sms_base;
 
@@ -56,4 +59,20 @@ static inline u32 sms_read_reg(u16 reg)
                         OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
 #endif  /* __ASSEMBLER__ */
 
+/* Minimum frequency that the SDRC DLL can lock at */
+#define MIN_SDRC_DLL_LOCK_FREQ          83000000
+
+/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
+#define SDRC_MPURATE_SCALE              8
+
+/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
+#define SDRC_MPURATE_BASE_SHIFT         9
+
+/*
+ * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
+ * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
+ */
+#define SDRC_MPURATE_LOOPS              96
+
+
 #endif
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 2e17b57f5b23..39b797bc14d6 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -33,6 +33,7 @@
 #include "pm.h"
 #include "prm-regbits-34xx.h"
 
+#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
 
 #define DEFAULT_TIMEOUT (5 * HZ)
@@ -572,6 +573,23 @@ static struct omap_uart_state omap_uart[] = {
 #endif
 };
 
+/*
+ * Override the default 8250 read handler: mem_serial_in()
+ * Empty RX fifo read causes an abort on omap3630 and omap4
+ * This function makes sure that an empty rx fifo is not read on these silicons
+ * (OMAP1/2/3430 are not affected)
+ */
+static unsigned int serial_in_override(struct uart_port *up, int offset)
+{
+        if (UART_RX == offset) {
+                unsigned int lsr;
+                lsr = serial_read_reg(omap_uart[up->line].p, UART_LSR);
+                if (!(lsr & UART_LSR_DR))
+                        return -EPERM;
+        }
+        return serial_read_reg(omap_uart[up->line].p, offset);
+}
+
 void __init omap_serial_early_init(void)
 {
         int i;
@@ -631,24 +649,64 @@ void __init omap_serial_early_init(void)
         }
 }
 
-void __init omap_serial_init(void)
+/**
+ * omap_serial_init_port() - initialize single serial port
+ * @port: serial port number (0-3)
+ *
+ * This function initialies serial driver for given @port only.
+ * Platforms can call this function instead of omap_serial_init()
+ * if they don't plan to use all available UARTs as serial ports.
+ *
+ * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
+ * use only one of the two.
+ */
+void __init omap_serial_init_port(int port)
 {
-        int i;
+        struct omap_uart_state *uart;
+        struct platform_device *pdev;
+        struct device *dev;
 
-        for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
-                struct omap_uart_state *uart = &omap_uart[i];
-                struct platform_device *pdev = &uart->pdev;
-                struct device *dev = &pdev->dev;
+        BUG_ON(port < 0);
+        BUG_ON(port >= ARRAY_SIZE(omap_uart));
 
-                omap_uart_reset(uart);
-                omap_uart_idle_init(uart);
+        uart = &omap_uart[port];
+        pdev = &uart->pdev;
+        dev = &pdev->dev;
 
-                if (WARN_ON(platform_device_register(pdev)))
-                        continue;
-                if ((cpu_is_omap34xx() && uart->padconf) ||
-                    (uart->wk_en && uart->wk_mask)) {
-                        device_init_wakeup(dev, true);
-                        DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
-                }
+        omap_uart_reset(uart);
+        omap_uart_idle_init(uart);
+
+        if (WARN_ON(platform_device_register(pdev)))
+                return;
+
+        if ((cpu_is_omap34xx() && uart->padconf) ||
+            (uart->wk_en && uart->wk_mask)) {
+                device_init_wakeup(dev, true);
+                DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
         }
+
+                /* omap44xx: Never read empty UART fifo
+                 * omap3xxx: Never read empty UART fifo on UARTs
+                 * with IP rev >=0x52
+                 */
+                if (cpu_is_omap44xx())
+                        uart->p->serial_in = serial_in_override;
+                else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
+                                >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
+                        uart->p->serial_in = serial_in_override;
+}
+
+/**
+ * omap_serial_init() - intialize all supported serial ports
+ *
+ * Initializes all available UARTs as serial ports. Platforms
+ * can call this function when they want to have default behaviour
+ * for serial ports (e.g initialize them all as serial ports).
+ */
+void __init omap_serial_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(omap_uart); i++)
+                omap_serial_init_port(i);
 }
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 82aa4a3d160c..de99ba2a57ab 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -91,8 +91,19 @@
  *  new SDRC_ACTIM_CTRL_B_1 register contents
  *  new SDRC_MR_1 register value
  *
- * If the param SDRC_RFR_CTRL_1 is 0, the parameters
- *  are not programmed into the SDRC CS1 registers
+ * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
+ * the SDRC CS1 registers
+ *
+ * NOTE: This code no longer attempts to program the SDRC AC timing and MR
+ * registers.  This is because the code currently cannot ensure that all
+ * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
+ * SDRAM when the registers are written.  If the registers are changed while
+ * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
+ * may enter an unpredictable state.  In the future, the intent is to
+ * re-enable this code in cases where we can ensure that no initiators are
+ * touching the SDRAM.  Until that time, users who know that their use case
+ * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
+ * option.
  */
 ENTRY(omap3_sram_configure_core_dpll)
         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
@@ -219,6 +230,7 @@ configure_sdrc:
         ldr     r12, omap_sdrc_rfr_ctrl_0_val   @ fetch value from SRAM
         ldr     r11, omap3_sdrc_rfr_ctrl_0      @ fetch addr from SRAM
         str     r12, [r11]                      @ store
+#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
         ldr     r12, omap_sdrc_actim_ctrl_a_0_val
         ldr     r11, omap3_sdrc_actim_ctrl_a_0
         str     r12, [r11]
@@ -228,11 +240,13 @@ configure_sdrc:
         ldr     r12, omap_sdrc_mr_0_val
         ldr     r11, omap3_sdrc_mr_0
         str     r12, [r11]
+#endif
         ldr     r12, omap_sdrc_rfr_ctrl_1_val
         cmp     r12, #0                 @ if SDRC_RFR_CTRL_1 is 0,
         beq     skip_cs1_prog           @  do not program cs1 params
         ldr     r11, omap3_sdrc_rfr_ctrl_1
         str     r12, [r11]
+#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
         ldr     r12, omap_sdrc_actim_ctrl_a_1_val
         ldr     r11, omap3_sdrc_actim_ctrl_a_1
         str     r12, [r11]
@@ -242,6 +256,7 @@ configure_sdrc:
         ldr     r12, omap_sdrc_mr_1_val
         ldr     r11, omap3_sdrc_mr_1
         str     r12, [r11]
+#endif
 skip_cs1_prog:
         ldr     r12, [r11]              @ posted-write barrier for SDRC
         bx      lr
diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
index e448abd5ec5d..f1df873d59db 100644
--- a/arch/arm/mach-omap2/usb-ehci.c
+++ b/arch/arm/mach-omap2/usb-ehci.c
@@ -27,6 +27,8 @@
 #include <mach/irqs.h>
 #include <plat/usb.h>
 
+#include "mux.h"
+
 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
 
 static struct resource ehci_resources[] = {
@@ -72,32 +74,44 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
 {
         switch (port_mode[0]) {
         case EHCI_HCD_OMAP_MODE_PHY:
-                omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
-                omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
-                omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
-                omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
-                omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
-                omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
-                omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
-                omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
-                omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
-                omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
-                omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
-                omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
+                omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
                 break;
         case EHCI_HCD_OMAP_MODE_TLL:
-                omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
-                omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
-                omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
-                omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
-                omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
-                omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
-                omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
-                omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
-                omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
-                omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
-                omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
-                omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
+                omap_mux_init_signal("hsusb1_tll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("hsusb1_tll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb1_tll_data7",
+                        OMAP_PIN_INPUT_PULLDOWN);
                 break;
         case EHCI_HCD_OMAP_MODE_UNKNOWN:
                 /* FALLTHROUGH */
@@ -107,32 +121,52 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
 
         switch (port_mode[1]) {
         case EHCI_HCD_OMAP_MODE_PHY:
-                omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
-                omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
-                omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
-                omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
-                omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
-                omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
-                omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
-                omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
-                omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
-                omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
-                omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
-                omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
+                omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_data7",
+                        OMAP_PIN_INPUT_PULLDOWN);
                 break;
         case EHCI_HCD_OMAP_MODE_TLL:
-                omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
-                omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
-                omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
-                omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
-                omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
-                omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
-                omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
-                omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
-                omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
-                omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
-                omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
-                omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
+                omap_mux_init_signal("hsusb2_tll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("hsusb2_tll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb2_tll_data7",
+                        OMAP_PIN_INPUT_PULLDOWN);
                 break;
         case EHCI_HCD_OMAP_MODE_UNKNOWN:
                 /* FALLTHROUGH */
@@ -145,18 +179,30 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
                 printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
                 break;
         case EHCI_HCD_OMAP_MODE_TLL:
-                omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
-                omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
-                omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
-                omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
-                omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
-                omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
-                omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
-                omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
-                omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
-                omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
-                omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
-                omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
+                omap_mux_init_signal("hsusb3_tll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("hsusb3_tll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("hsusb3_tll_data7",
+                        OMAP_PIN_INPUT_PULLDOWN);
                 break;
         case EHCI_HCD_OMAP_MODE_UNKNOWN:
                 /* FALLTHROUGH */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index f348ddfb0492..e2ea04a4c8a1 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -27,6 +27,7 @@ config ARCH_OMAP4
         bool "TI OMAP4"
         select CPU_V7
         select ARM_GIC
+        select COMMON_CLKDEV
 
 endchoice
 
@@ -42,28 +43,6 @@ config OMAP_DEBUG_LEDS
         depends on OMAP_DEBUG_DEVICES
         default y if LEDS || LEDS_OMAP_DEBUG
 
-config OMAP_DEBUG_POWERDOMAIN
-        bool "Emit debug messages from powerdomain layer"
-        depends on ARCH_OMAP2 || ARCH_OMAP3
-        help
-          Say Y here if you want to compile in powerdomain layer
-          debugging messages for OMAP2/3.   These messages can
-          provide more detail as to why some powerdomain calls
-          may be failing, and will also emit a descriptive message
-          for every powerdomain register write.  However, the
-          extra detail costs some memory.
-
-config OMAP_DEBUG_CLOCKDOMAIN
-        bool "Emit debug messages from clockdomain layer"
-        depends on ARCH_OMAP2 || ARCH_OMAP3
-        help
-          Say Y here if you want to compile in clockdomain layer
-          debugging messages for OMAP2/3.   These messages can
-          provide more detail as to why some clockdomain calls
-          may be failing, and will also emit a descriptive message
-          for every clockdomain register write.  However, the
-          extra detail costs some memory.
-
 config OMAP_RESET_CLOCKS
         bool "Reset unused clocks during boot"
         depends on ARCH_OMAP
@@ -78,28 +57,28 @@ config OMAP_RESET_CLOCKS
 
 config OMAP_MUX
         bool "OMAP multiplexing support"
-        depends on ARCH_OMAP
+        depends on ARCH_OMAP
         default y
-        help
-          Pin multiplexing support for OMAP boards. If your bootloader
-          sets the multiplexing correctly, say N. Otherwise, or if unsure,
-          say Y.
+        help
+          Pin multiplexing support for OMAP boards. If your bootloader
+          sets the multiplexing correctly, say N. Otherwise, or if unsure,
+          say Y.
 
 config OMAP_MUX_DEBUG
         bool "Multiplexing debug output"
-        depends on OMAP_MUX
-        help
-          Makes the multiplexing functions print out a lot of debug info.
-          This is useful if you want to find out the correct values of the
-          multiplexing registers.
+        depends on OMAP_MUX
+        help
+          Makes the multiplexing functions print out a lot of debug info.
+          This is useful if you want to find out the correct values of the
+          multiplexing registers.
 
 config OMAP_MUX_WARNINGS
         bool "Warn about pins the bootloader didn't set up"
-        depends on OMAP_MUX
-        default y
-        help
+        depends on OMAP_MUX
+        default y
+        help
           Choose Y here to warn whenever driver initialization logic needs
-          to change the pin multiplexing setup.  When there are no warnings
+          to change the pin multiplexing setup.  When there are no warnings
           printed, it's safe to deselect OMAP_MUX for your product.
 
 config OMAP_MCBSP
@@ -125,7 +104,7 @@ config OMAP_IOMMU_DEBUG
         tristate
 
 choice
-        prompt "System timer"
+        prompt "System timer"
         default OMAP_MPU_TIMER
 
 config OMAP_MPU_TIMER
@@ -148,11 +127,11 @@ config OMAP_32K_TIMER
 endchoice
 
 config OMAP_32K_TIMER_HZ
-       int "Kernel internal timer frequency for 32KHz timer"
-       range 32 1024
-       depends on OMAP_32K_TIMER
-       default "128"
-       help
+        int "Kernel internal timer frequency for 32KHz timer"
+        range 32 1024
+        depends on OMAP_32K_TIMER
+        default "128"
+        help
           Kernel internal timer frequency should be a divisor of 32768,
           such as 64 or 128.
 
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 681bfc37ebb2..89cafc937249 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -40,36 +40,10 @@ static struct clk_functions *arch_clock;
  * clock framework is not up , it is defined here to avoid rework in
  * every driver. Also dummy prcm reset function is added */
 
-/* Dummy hooks only for OMAP4.For rest OMAPs, common clkdev is used */
-#if defined(CONFIG_ARCH_OMAP4)
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        return NULL;
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
-void omap2_clk_prepare_for_reboot(void)
-{
-}
-EXPORT_SYMBOL(omap2_clk_prepare_for_reboot);
-
-void omap_prcm_arch_reset(char mode)
-{
-}
-EXPORT_SYMBOL(omap_prcm_arch_reset);
-#endif
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
         int ret = 0;
-        if (cpu_is_omap44xx())
-                /* OMAP4 clk framework not supported yet */
-                return 0;
 
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index cc050b3313bd..bf1eaf3a27d4 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -280,16 +280,18 @@ void __init omap2_set_globals_343x(void)
 #if defined(CONFIG_ARCH_OMAP4)
 static struct omap_globals omap4_globals = {
         .class  = OMAP443X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(0x4830a000),
+        .tap    = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
         .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
         .prm    = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
         .cm     = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
+        .cm2    = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
 };
 
 void __init omap2_set_globals_443x(void)
 {
         omap2_set_globals_tap(&omap4_globals);
         omap2_set_globals_control(&omap4_globals);
+        omap2_set_globals_prcm(&omap4_globals);
 }
 #endif
 
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index 09c1107637f6..923c9621096b 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/smc91x.h>
 
 #include <mach/hardware.h>
 
@@ -24,6 +25,12 @@
  * platforms include H2, H3, H4, and Perseus2.
  */
 
+static struct smc91x_platdata smc91x_info = {
+        .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
 static struct resource smc91x_resources[] = {
         [0] = {
                 .flags  = IORESOURCE_MEM,
@@ -36,6 +43,9 @@ static struct resource smc91x_resources[] = {
 static struct platform_device smc91x_device = {
         .name           = "smc91x",
         .id             = -1,
+        .dev            = {
+                .platform_data = &smc91x_info,
+        },
         .num_resources  = ARRAY_SIZE(smc91x_resources),
         .resource       = smc91x_resources,
 };
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index f86617869b38..30b5db73017a 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -242,6 +242,39 @@ fail:
 
 /*-------------------------------------------------------------------------*/
 
+#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
+
+#ifdef CONFIG_ARCH_OMAP24XX
+#define OMAP_RNG_BASE           0x480A0000
+#else
+#define OMAP_RNG_BASE           0xfffe5000
+#endif
+
+static struct resource rng_resources[] = {
+        {
+                .start          = OMAP_RNG_BASE,
+                .end            = OMAP_RNG_BASE + 0x4f,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device omap_rng_device = {
+        .name           = "omap_rng",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(rng_resources),
+        .resource       = rng_resources,
+};
+
+static void omap_init_rng(void)
+{
+        (void) platform_device_register(&omap_rng_device);
+}
+#else
+static inline void omap_init_rng(void) {}
+#endif
+
+/*-------------------------------------------------------------------------*/
+
 /* Numbering for the SPI-capable controllers when used for SPI:
  * spi          = 1
  * uwire        = 2
@@ -324,39 +357,6 @@ static void omap_init_wdt(void)
 static inline void omap_init_wdt(void) {}
 #endif
 
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
-
-#ifdef CONFIG_ARCH_OMAP24XX
-#define OMAP_RNG_BASE           0x480A0000
-#else
-#define OMAP_RNG_BASE           0xfffe5000
-#endif
-
-static struct resource rng_resources[] = {
-        {
-                .start          = OMAP_RNG_BASE,
-                .end            = OMAP_RNG_BASE + 0x4f,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device omap_rng_device = {
-        .name      = "omap_rng",
-        .id          = -1,
-        .num_resources  = ARRAY_SIZE(rng_resources),
-        .resource       = rng_resources,
-};
-
-static void omap_init_rng(void)
-{
-        (void) platform_device_register(&omap_rng_device);
-}
-#else
-static inline void omap_init_rng(void) {}
-#endif
-
 /*
  * This gets called after board-specific INIT_MACHINE, and initializes most
  * on-chip peripherals accessible on this board (except for few like USB):
@@ -384,9 +384,9 @@ static int __init omap_init_devices(void)
          */
         omap_init_dsp();
         omap_init_kp();
+        omap_init_rng();
         omap_init_uwire();
         omap_init_wdt();
-        omap_init_rng();
         return 0;
 }
 arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index d17375e06a1e..09d82b3c66ce 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -47,7 +47,6 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
 #endif
 
 #define OMAP_DMA_ACTIVE                 0x01
-#define OMAP_DMA_CCR_EN                 (1 << 7)
 #define OMAP2_DMA_CSR_CLEAR_MASK        0xffe
 
 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
@@ -1120,17 +1119,8 @@ int omap_dma_running(void)
 {
         int lch;
 
-        /*
-         * On OMAP1510, internal LCD controller will start the transfer
-         * when it gets enabled, so assume DMA running if LCD enabled.
-         */
-        if (cpu_is_omap1510())
-                if (omap_readw(0xfffec000 + 0x00) & (1 << 0))
-                        return 1;
-
-        /* Check if LCD DMA is running */
-        if (cpu_is_omap16xx())
-                if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
+        if (cpu_class_is_omap1())
+                if (omap_lcd_dma_running())
                         return 1;
 
         for (lch = 0; lch < dma_chan_count; lch++)
@@ -1990,377 +1980,6 @@ static struct irqaction omap24xx_dma_irq;
 
 /*----------------------------------------------------------------------------*/
 
-static struct lcd_dma_info {
-        spinlock_t lock;
-        int reserved;
-        void (*callback)(u16 status, void *data);
-        void *cb_data;
-
-        int active;
-        unsigned long addr, size;
-        int rotate, data_type, xres, yres;
-        int vxres;
-        int mirror;
-        int xscale, yscale;
-        int ext_ctrl;
-        int src_port;
-        int single_transfer;
-} lcd_dma;
-
-void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
-                         int data_type)
-{
-        lcd_dma.addr = addr;
-        lcd_dma.data_type = data_type;
-        lcd_dma.xres = fb_xres;
-        lcd_dma.yres = fb_yres;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1);
-
-void omap_set_lcd_dma_src_port(int port)
-{
-        lcd_dma.src_port = port;
-}
-
-void omap_set_lcd_dma_ext_controller(int external)
-{
-        lcd_dma.ext_ctrl = external;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
-
-void omap_set_lcd_dma_single_transfer(int single)
-{
-        lcd_dma.single_transfer = single;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
-
-void omap_set_lcd_dma_b1_rotation(int rotate)
-{
-        if (omap_dma_in_1510_mode()) {
-                printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
-                BUG();
-                return;
-        }
-        lcd_dma.rotate = rotate;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
-
-void omap_set_lcd_dma_b1_mirror(int mirror)
-{
-        if (omap_dma_in_1510_mode()) {
-                printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
-                BUG();
-        }
-        lcd_dma.mirror = mirror;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
-
-void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
-{
-        if (omap_dma_in_1510_mode()) {
-                printk(KERN_ERR "DMA virtual resulotion is not supported "
-                                "in 1510 mode\n");
-                BUG();
-        }
-        lcd_dma.vxres = vxres;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
-
-void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
-{
-        if (omap_dma_in_1510_mode()) {
-                printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
-                BUG();
-        }
-        lcd_dma.xscale = xscale;
-        lcd_dma.yscale = yscale;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
-
-static void set_b1_regs(void)
-{
-        unsigned long top, bottom;
-        int es;
-        u16 w;
-        unsigned long en, fn;
-        long ei, fi;
-        unsigned long vxres;
-        unsigned int xscale, yscale;
-
-        switch (lcd_dma.data_type) {
-        case OMAP_DMA_DATA_TYPE_S8:
-                es = 1;
-                break;
-        case OMAP_DMA_DATA_TYPE_S16:
-                es = 2;
-                break;
-        case OMAP_DMA_DATA_TYPE_S32:
-                es = 4;
-                break;
-        default:
-                BUG();
-                return;
-        }
-
-        vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
-        xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
-        yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
-        BUG_ON(vxres < lcd_dma.xres);
-
-#define PIXADDR(x, y) (lcd_dma.addr +                                   \
-                ((y) * vxres * yscale + (x) * xscale) * es)
-#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
-
-        switch (lcd_dma.rotate) {
-        case 0:
-                if (!lcd_dma.mirror) {
-                        top = PIXADDR(0, 0);
-                        bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                        /* 1510 DMA requires the bottom address to be 2 more
-                         * than the actual last memory access location. */
-                        if (omap_dma_in_1510_mode() &&
-                                lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
-                                        bottom += 2;
-                        ei = PIXSTEP(0, 0, 1, 0);
-                        fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
-                } else {
-                        top = PIXADDR(lcd_dma.xres - 1, 0);
-                        bottom = PIXADDR(0, lcd_dma.yres - 1);
-                        ei = PIXSTEP(1, 0, 0, 0);
-                        fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
-                }
-                en = lcd_dma.xres;
-                fn = lcd_dma.yres;
-                break;
-        case 90:
-                if (!lcd_dma.mirror) {
-                        top = PIXADDR(0, lcd_dma.yres - 1);
-                        bottom = PIXADDR(lcd_dma.xres - 1, 0);
-                        ei = PIXSTEP(0, 1, 0, 0);
-                        fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
-                } else {
-                        top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                        bottom = PIXADDR(0, 0);
-                        ei = PIXSTEP(0, 1, 0, 0);
-                        fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
-                }
-                en = lcd_dma.yres;
-                fn = lcd_dma.xres;
-                break;
-        case 180:
-                if (!lcd_dma.mirror) {
-                        top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                        bottom = PIXADDR(0, 0);
-                        ei = PIXSTEP(1, 0, 0, 0);
-                        fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
-                } else {
-                        top = PIXADDR(0, lcd_dma.yres - 1);
-                        bottom = PIXADDR(lcd_dma.xres - 1, 0);
-                        ei = PIXSTEP(0, 0, 1, 0);
-                        fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
-                }
-                en = lcd_dma.xres;
-                fn = lcd_dma.yres;
-                break;
-        case 270:
-                if (!lcd_dma.mirror) {
-                        top = PIXADDR(lcd_dma.xres - 1, 0);
-                        bottom = PIXADDR(0, lcd_dma.yres - 1);
-                        ei = PIXSTEP(0, 0, 0, 1);
-                        fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
-                } else {
-                        top = PIXADDR(0, 0);
-                        bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
-                        ei = PIXSTEP(0, 0, 0, 1);
-                        fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
-                }
-                en = lcd_dma.yres;
-                fn = lcd_dma.xres;
-                break;
-        default:
-                BUG();
-                return; /* Suppress warning about uninitialized vars */
-        }
-
-        if (omap_dma_in_1510_mode()) {
-                omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
-                omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
-                omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
-                omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
-
-                return;
-        }
-
-        /* 1610 regs */
-        omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
-        omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
-        omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
-        omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
-
-        omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
-        omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
-
-        w = omap_readw(OMAP1610_DMA_LCD_CSDP);
-        w &= ~0x03;
-        w |= lcd_dma.data_type;
-        omap_writew(w, OMAP1610_DMA_LCD_CSDP);
-
-        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-        /* Always set the source port as SDRAM for now*/
-        w &= ~(0x03 << 6);
-        if (lcd_dma.callback != NULL)
-                w |= 1 << 1;            /* Block interrupt enable */
-        else
-                w &= ~(1 << 1);
-        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-
-        if (!(lcd_dma.rotate || lcd_dma.mirror ||
-              lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
-                return;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CCR);
-        /* Set the double-indexed addressing mode */
-        w |= (0x03 << 12);
-        omap_writew(w, OMAP1610_DMA_LCD_CCR);
-
-        omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
-        omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
-        omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
-}
-
-static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
-{
-        u16 w;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-        if (unlikely(!(w & (1 << 3)))) {
-                printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
-                return IRQ_NONE;
-        }
-        /* Ack the IRQ */
-        w |= (1 << 3);
-        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-        lcd_dma.active = 0;
-        if (lcd_dma.callback != NULL)
-                lcd_dma.callback(w, lcd_dma.cb_data);
-
-        return IRQ_HANDLED;
-}
-
-int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
-                         void *data)
-{
-        spin_lock_irq(&lcd_dma.lock);
-        if (lcd_dma.reserved) {
-                spin_unlock_irq(&lcd_dma.lock);
-                printk(KERN_ERR "LCD DMA channel already reserved\n");
-                BUG();
-                return -EBUSY;
-        }
-        lcd_dma.reserved = 1;
-        spin_unlock_irq(&lcd_dma.lock);
-        lcd_dma.callback = callback;
-        lcd_dma.cb_data = data;
-        lcd_dma.active = 0;
-        lcd_dma.single_transfer = 0;
-        lcd_dma.rotate = 0;
-        lcd_dma.vxres = 0;
-        lcd_dma.mirror = 0;
-        lcd_dma.xscale = 0;
-        lcd_dma.yscale = 0;
-        lcd_dma.ext_ctrl = 0;
-        lcd_dma.src_port = 0;
-
-        return 0;
-}
-EXPORT_SYMBOL(omap_request_lcd_dma);
-
-void omap_free_lcd_dma(void)
-{
-        spin_lock(&lcd_dma.lock);
-        if (!lcd_dma.reserved) {
-                spin_unlock(&lcd_dma.lock);
-                printk(KERN_ERR "LCD DMA is not reserved\n");
-                BUG();
-                return;
-        }
-        if (!enable_1510_mode)
-                omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
-                            OMAP1610_DMA_LCD_CCR);
-        lcd_dma.reserved = 0;
-        spin_unlock(&lcd_dma.lock);
-}
-EXPORT_SYMBOL(omap_free_lcd_dma);
-
-void omap_enable_lcd_dma(void)
-{
-        u16 w;
-
-        /*
-         * Set the Enable bit only if an external controller is
-         * connected. Otherwise the OMAP internal controller will
-         * start the transfer when it gets enabled.
-         */
-        if (enable_1510_mode || !lcd_dma.ext_ctrl)
-                return;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-        w |= 1 << 8;
-        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-
-        lcd_dma.active = 1;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CCR);
-        w |= 1 << 7;
-        omap_writew(w, OMAP1610_DMA_LCD_CCR);
-}
-EXPORT_SYMBOL(omap_enable_lcd_dma);
-
-void omap_setup_lcd_dma(void)
-{
-        BUG_ON(lcd_dma.active);
-        if (!enable_1510_mode) {
-                /* Set some reasonable defaults */
-                omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
-                omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
-                omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
-        }
-        set_b1_regs();
-        if (!enable_1510_mode) {
-                u16 w;
-
-                w = omap_readw(OMAP1610_DMA_LCD_CCR);
-                /*
-                 * If DMA was already active set the end_prog bit to have
-                 * the programmed register set loaded into the active
-                 * register set.
-                 */
-                w |= 1 << 11;           /* End_prog */
-                if (!lcd_dma.single_transfer)
-                        w |= (3 << 8);  /* Auto_init, repeat */
-                omap_writew(w, OMAP1610_DMA_LCD_CCR);
-        }
-}
-EXPORT_SYMBOL(omap_setup_lcd_dma);
-
-void omap_stop_lcd_dma(void)
-{
-        u16 w;
-
-        lcd_dma.active = 0;
-        if (enable_1510_mode || !lcd_dma.ext_ctrl)
-                return;
-
-        w = omap_readw(OMAP1610_DMA_LCD_CCR);
-        w &= ~(1 << 7);
-        omap_writew(w, OMAP1610_DMA_LCD_CCR);
-
-        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-        w &= ~(1 << 8);
-        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-}
-EXPORT_SYMBOL(omap_stop_lcd_dma);
-
 void omap_dma_global_context_save(void)
 {
         omap_dma_global_context.dma_irqenable_l0 =
@@ -2465,14 +2084,6 @@ static int __init omap_init_dma(void)
                         dma_chan_count = 16;
                 } else
                         dma_chan_count = 9;
-                if (cpu_is_omap16xx()) {
-                        u16 w;
-
-                        /* this would prevent OMAP sleep */
-                        w = omap_readw(OMAP1610_DMA_LCD_CTRL);
-                        w &= ~(1 << 8);
-                        omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-                }
         } else if (cpu_class_is_omap2()) {
                 u8 revision = dma_read(REVISION) & 0xff;
                 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
@@ -2483,7 +2094,6 @@ static int __init omap_init_dma(void)
                 return 0;
         }
 
-        spin_lock_init(&lcd_dma.lock);
         spin_lock_init(&dma_chan_lock);
 
         for (ch = 0; ch < dma_chan_count; ch++) {
@@ -2548,22 +2158,6 @@ static int __init omap_init_dma(void)
                 }
         }
 
-
-        /* FIXME: Update LCD DMA to work on 24xx */
-        if (cpu_class_is_omap1()) {
-                r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
-                                "LCD DMA", NULL);
-                if (r != 0) {
-                        int i;
-
-                        printk(KERN_ERR "unable to request IRQ for LCD DMA "
-                               "(error %d)\n", r);
-                        for (i = 0; i < dma_chan_count; i++)
-                                free_irq(omap1_dma_irq[i], (void *) (i + 1));
-                        goto out_free;
-                }
-        }
-
         return 0;
 
 out_free:
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index c08362dbb8ed..33fff4ef382d 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -80,47 +80,8 @@ static struct platform_device omap_i2c_devices[] = {
 #endif
 };
 
-#if defined(CONFIG_ARCH_OMAP24XX)
-static const int omap24xx_pins[][2] = {
-        { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
-        { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
-};
-#else
-static const int omap24xx_pins[][2] = {};
-#endif
-#if defined(CONFIG_ARCH_OMAP34XX)
-static const int omap34xx_pins[][2] = {
-        { K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA},
-        { AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA},
-        { AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA},
-};
-#else
-static const int omap34xx_pins[][2] = {};
-#endif
-
 #define OMAP_I2C_CMDLINE_SETUP  (BIT(31))
 
-static void __init omap_i2c_mux_pins(int bus)
-{
-        int scl, sda;
-
-        if (cpu_class_is_omap1()) {
-                scl = I2C_SCL;
-                sda = I2C_SDA;
-        } else if (cpu_is_omap24xx()) {
-                scl = omap24xx_pins[bus][0];
-                sda = omap24xx_pins[bus][1];
-        } else if (cpu_is_omap34xx()) {
-                scl = omap34xx_pins[bus][0];
-                sda = omap34xx_pins[bus][1];
-        } else {
-                return;
-        }
-
-        omap_cfg_reg(sda);
-        omap_cfg_reg(scl);
-}
-
 static int __init omap_i2c_nr_ports(void)
 {
         int ports = 0;
@@ -156,7 +117,6 @@ static int __init omap_i2c_add_bus(int bus_id)
                 res[1].start = irq;
         }
 
-        omap_i2c_mux_pins(bus_id - 1);
         return platform_device_register(pdev);
 }
 
@@ -209,7 +169,7 @@ out:
 subsys_initcall(omap_register_i2c_bus_cmdline);
 
 /**
- * omap_register_i2c_bus - register I2C bus with device descriptors
+ * omap_plat_register_i2c_bus - register I2C bus with device descriptors
  * @bus_id: bus id counting from number 1
  * @clkrate: clock rate of the bus in kHz
  * @info: pointer into I2C device descriptor table or NULL
@@ -217,7 +177,7 @@ subsys_initcall(omap_register_i2c_bus_cmdline);
  *
  * Returns 0 on success or an error code.
  */
-int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
+int __init omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
                           struct i2c_board_info const *info,
                           unsigned len)
 {
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index abb17b604f82..376ce18216ff 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -114,15 +114,6 @@ struct omap_pwm_led_platform_data {
         void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
 };
 
-/* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */
-struct omap_gpio_switch_config {
-        char name[12];
-        u16 gpio;
-        int flags:4;
-        int type:4;
-        int key_code:24; /* Linux key code */
-};
-
 struct omap_uart_config {
         /* Bit field of UARTs present; bit 0 --> UART1 */
         unsigned int enabled_uarts;
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
new file mode 100644
index 000000000000..35b36caf5f91
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -0,0 +1,41 @@
+/*
+ * clkdev <-> OMAP integration
+ *
+ * Russell King <linux@arm.linux.org.uk>
+ *
+ */
+
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
+
+#include <asm/clkdev.h>
+
+struct omap_clk {
+        u16                             cpu;
+        struct clk_lookup               lk;
+};
+
+#define CLK(dev, con, ck, cp)           \
+        {                               \
+                 .cpu = cp,             \
+                .lk = {                 \
+                        .dev_id = dev,  \
+                        .con_id = con,  \
+                        .clk = ck,      \
+                },                      \
+        }
+
+
+#define CK_310          (1 << 0)
+#define CK_7XX          (1 << 1)
+#define CK_1510         (1 << 2)
+#define CK_16XX         (1 << 3)
+#define CK_243X         (1 << 4)
+#define CK_242X         (1 << 5)
+#define CK_343X         (1 << 6)
+#define CK_3430ES1      (1 << 7)
+#define CK_3430ES2      (1 << 8)
+#define CK_443X         (1 << 9)
+
+#endif
+
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 4b8b0d65cbf2..309b6d1dccdb 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -13,6 +13,8 @@
 #ifndef __ARCH_ARM_OMAP_CLOCK_H
 #define __ARCH_ARM_OMAP_CLOCK_H
 
+#include <linux/list.h>
+
 struct module;
 struct clk;
 struct clockdomain;
@@ -148,6 +150,8 @@ extern const struct clkops clkops_null;
 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
 #define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
 #define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
+#define CLOCK_IN_OMAP4430       (1 << 13)
+#define ALWAYS_ENABLED          (1 << 14)
 /* bits 13-31 are currently free */
 
 /* Clksel_rate flags */
@@ -156,6 +160,7 @@ extern const struct clkops clkops_null;
 #define RATE_IN_243X            (1 << 2)
 #define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
 #define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
+#define RATE_IN_4430            (1 << 5)
 
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 064f1730f43b..32c22272425d 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -27,7 +27,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
 #define __ARCH_ARM_MACH_OMAP_COMMON_H
 
-#include <linux/i2c.h>
+#include <plat/i2c.h>
 
 struct sys_timer;
 
@@ -36,18 +36,6 @@ extern void __iomem *gic_cpu_base_addr;
 
 extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
-#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
-extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
-                                 struct i2c_board_info const *info,
-                                 unsigned len);
-#else
-static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
-                                 struct i2c_board_info const *info,
-                                 unsigned len)
-{
-        return 0;
-}
-#endif
 
 /* IO bases for various OMAP processors */
 struct omap_globals {
@@ -58,6 +46,7 @@ struct omap_globals {
         void __iomem    *ctrl;          /* System Control Module */
         void __iomem    *prm;           /* Power and Reset Management */
         void __iomem    *cm;            /* Clock Management */
+        void __iomem    *cm2;
 };
 
 void omap2_set_globals_242x(void);
@@ -71,4 +60,24 @@ void omap2_set_globals_sdrc(struct omap_globals *);
 void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
 
+/**
+ * omap_test_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ */
+#define omap_test_timeout(cond, timeout, index)                 \
+({                                                              \
+        for (index = 0; index < timeout; index++) {             \
+                if (cond)                                       \
+                        break;                                  \
+                udelay(1);                                      \
+        }                                                       \
+})
+
 #endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 2e1789001dfe..9a028bdebb06 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -176,11 +176,13 @@ IS_OMAP_CLASS(15xx, 0x15)
 IS_OMAP_CLASS(16xx, 0x16)
 IS_OMAP_CLASS(24xx, 0x24)
 IS_OMAP_CLASS(34xx, 0x34)
+IS_OMAP_CLASS(44xx, 0x44)
 
 IS_OMAP_SUBCLASS(242x, 0x242)
 IS_OMAP_SUBCLASS(243x, 0x243)
 IS_OMAP_SUBCLASS(343x, 0x343)
 IS_OMAP_SUBCLASS(363x, 0x363)
+IS_OMAP_SUBCLASS(443x, 0x443)
 
 #define cpu_is_omap7xx()                0
 #define cpu_is_omap15xx()               0
@@ -393,11 +395,11 @@ IS_OMAP_TYPE(3517, 0x3517)
                                                 (!omap3_has_iva()) &&   \
                                                 (!omap3_has_sgx()))
 # define cpu_is_omap3515()              (cpu_is_omap3430() &&           \
-                                                (omap3_has_iva()) &&    \
-                                                (!omap3_has_sgx()))
+                                                (!omap3_has_iva()) &&   \
+                                                (omap3_has_sgx()))
 # define cpu_is_omap3525()              (cpu_is_omap3430() &&           \
-                                                (omap3_has_sgx()) &&    \
-                                                (!omap3_has_iva()))
+                                                (!omap3_has_sgx()) &&   \
+                                                (omap3_has_iva()))
 # define cpu_is_omap3530()              (cpu_is_omap3430())
 # define cpu_is_omap3505()              is_omap3505()
 # define cpu_is_omap3517()              is_omap3517()
@@ -408,8 +410,8 @@ IS_OMAP_TYPE(3517, 0x3517)
 # if defined(CONFIG_ARCH_OMAP4)
 # undef cpu_is_omap44xx
 # undef cpu_is_omap443x
-# define cpu_is_omap44xx()              1
-# define cpu_is_omap443x()              1
+# define cpu_is_omap44xx()              is_omap44xx()
+# define cpu_is_omap443x()              is_omap443x()
 # endif
 
 /* Macros to detect if we have OMAP1 or OMAP2 */
@@ -436,14 +438,15 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP3630_REV_ES1_0      0x36300034
 
 #define OMAP35XX_CLASS          0x35000034
-#define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 12))
-#define OMAP3515_REV(v)         (OMAP35XX_CLASS | (0x3515 << 16) | (v << 12))
-#define OMAP3525_REV(v)         (OMAP35XX_CLASS | (0x3525 << 16) | (v << 12))
-#define OMAP3530_REV(v)         (OMAP35XX_CLASS | (0x3530 << 16) | (v << 12))
-#define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 12))
-#define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 12))
-
-#define OMAP443X_CLASS          0x44300034
+#define OMAP3503_REV(v)         (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
+#define OMAP3515_REV(v)         (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
+#define OMAP3525_REV(v)         (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
+#define OMAP3530_REV(v)         (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
+#define OMAP3505_REV(v)         (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
+#define OMAP3517_REV(v)         (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
+
+#define OMAP443X_CLASS          0x44300044
+#define OMAP4430_REV_ES1_0      0x44300044
 
 /*
  * omap_chip bits
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 1c017b29b7e9..4ede9e17a0be 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -401,33 +401,6 @@
 
 /*----------------------------------------------------------------------------*/
 
-/* Hardware registers for LCD DMA */
-#define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
-#define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
-#define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
-#define OMAP1510_DMA_LCD_TOP_F1_U       (OMAP1510_DMA_LCD_BASE + 0x04)
-#define OMAP1510_DMA_LCD_BOT_F1_L       (OMAP1510_DMA_LCD_BASE + 0x06)
-#define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
-
-#define OMAP1610_DMA_LCD_BASE           (0xfffee300)
-#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
-#define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
-#define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
-#define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
-#define OMAP1610_DMA_LCD_TOP_B1_U       (OMAP1610_DMA_LCD_BASE + 0xca)
-#define OMAP1610_DMA_LCD_BOT_B1_L       (OMAP1610_DMA_LCD_BASE + 0xcc)
-#define OMAP1610_DMA_LCD_BOT_B1_U       (OMAP1610_DMA_LCD_BASE + 0xce)
-#define OMAP1610_DMA_LCD_TOP_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd0)
-#define OMAP1610_DMA_LCD_TOP_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd2)
-#define OMAP1610_DMA_LCD_BOT_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd4)
-#define OMAP1610_DMA_LCD_BOT_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd6)
-#define OMAP1610_DMA_LCD_SRC_EI_B1      (OMAP1610_DMA_LCD_BASE + 0xd8)
-#define OMAP1610_DMA_LCD_SRC_FI_B1_L    (OMAP1610_DMA_LCD_BASE + 0xda)
-#define OMAP1610_DMA_LCD_SRC_EN_B1      (OMAP1610_DMA_LCD_BASE + 0xe0)
-#define OMAP1610_DMA_LCD_SRC_FN_B1      (OMAP1610_DMA_LCD_BASE + 0xe4)
-#define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
-#define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
-
 #define OMAP1_DMA_TOUT_IRQ              (1 << 0)
 #define OMAP_DMA_DROP_IRQ               (1 << 1)
 #define OMAP_DMA_HALF_IRQ               (1 << 2)
@@ -441,6 +414,8 @@
 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
 #define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
 
+#define OMAP_DMA_CCR_EN                 (1 << 7)
+
 #define OMAP_DMA_DATA_TYPE_S8           0x00
 #define OMAP_DMA_DATA_TYPE_S16          0x01
 #define OMAP_DMA_DATA_TYPE_S32          0x02
@@ -503,14 +478,6 @@
 #define DMA_CH_PRIO_HIGH                0x1
 #define DMA_CH_PRIO_LOW                 0x0 /* Def */
 
-/* LCD DMA block numbers */
-enum {
-        OMAP_LCD_DMA_B1_TOP,
-        OMAP_LCD_DMA_B1_BOTTOM,
-        OMAP_LCD_DMA_B2_TOP,
-        OMAP_LCD_DMA_B2_BOTTOM
-};
-
 enum omap_dma_burst_mode {
         OMAP_DMA_DATA_BURST_DIS = 0,
         OMAP_DMA_DATA_BURST_4,
@@ -661,20 +628,13 @@ extern int omap_modify_dma_chain_params(int chain_id,
 extern int omap_dma_chain_status(int chain_id);
 #endif
 
-/* LCD DMA functions */
-extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
-                                void *data);
-extern void omap_free_lcd_dma(void);
-extern void omap_setup_lcd_dma(void);
-extern void omap_enable_lcd_dma(void);
-extern void omap_stop_lcd_dma(void);
-extern void omap_set_lcd_dma_ext_controller(int external);
-extern void omap_set_lcd_dma_single_transfer(int single);
-extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
-                                int data_type);
-extern void omap_set_lcd_dma_b1_rotation(int rotate);
-extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
-extern void omap_set_lcd_dma_b1_mirror(int mirror);
-extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
+#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
+#include <mach/lcd_dma.h>
+#else
+static inline int omap_lcd_dma_running(void)
+{
+        return 0;
+}
+#endif
 
 #endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 696e0ca051b7..e081338e0b23 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -45,7 +45,7 @@
 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
-#define GPMC_CONFIG1_DEVICETYPE_NAND    GPMC_CONFIG1_DEVICETYPE(1)
+#define GPMC_CONFIG1_DEVICETYPE_NAND    GPMC_CONFIG1_DEVICETYPE(2)
 #define GPMC_CONFIG1_MUXADDDATA         (1 << 9)
 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
new file mode 100644
index 000000000000..585d9ca68b97
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -0,0 +1,39 @@
+/*
+ * Helper module for board specific I2C bus registration
+ *
+ * Copyright (C) 2009 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/i2c.h>
+
+#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
+extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len);
+#else
+static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len)
+{
+        return 0;
+}
+#endif
+
+int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
+                                 struct i2c_board_info const *info,
+                                 unsigned len);
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index ba77de601501..8f069cc80350 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -130,58 +130,11 @@
 #define OMAP2_PULL_UP           (1 << 4)
 #define OMAP2_ALTELECTRICALSEL  (1 << 5)
 
-/* 34xx specific mux bit defines */
-#define OMAP3_INPUT_EN          (1 << 8)
-#define OMAP3_OFF_EN            (1 << 9)
-#define OMAP3_OFFOUT_EN         (1 << 10)
-#define OMAP3_OFFOUT_VAL        (1 << 11)
-#define OMAP3_OFF_PULL_EN       (1 << 12)
-#define OMAP3_OFF_PULL_UP       (1 << 13)
-#define OMAP3_WAKEUP_EN         (1 << 14)
-
-/* 34xx mux mode options for each pin. See TRM for options */
-#define OMAP34XX_MUX_MODE0      0
-#define OMAP34XX_MUX_MODE1      1
-#define OMAP34XX_MUX_MODE2      2
-#define OMAP34XX_MUX_MODE3      3
-#define OMAP34XX_MUX_MODE4      4
-#define OMAP34XX_MUX_MODE5      5
-#define OMAP34XX_MUX_MODE6      6
-#define OMAP34XX_MUX_MODE7      7
-
-/* 34xx active pin states */
-#define OMAP34XX_PIN_OUTPUT             0
-#define OMAP34XX_PIN_INPUT              OMAP3_INPUT_EN
-#define OMAP34XX_PIN_INPUT_PULLUP       (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
-                                                | OMAP2_PULL_UP)
-#define OMAP34XX_PIN_INPUT_PULLDOWN     (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
-
-/* 34xx off mode states */
-#define OMAP34XX_PIN_OFF_NONE           0
-#define OMAP34XX_PIN_OFF_OUTPUT_HIGH    (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
-                                                | OMAP3_OFFOUT_VAL)
-#define OMAP34XX_PIN_OFF_OUTPUT_LOW     (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
-#define OMAP34XX_PIN_OFF_INPUT_PULLUP   (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
-                                                | OMAP3_OFF_PULL_UP)
-#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
-#define OMAP34XX_PIN_OFF_WAKEUPENABLE   OMAP3_WAKEUP_EN
-
-#define MUX_CFG_34XX(desc, reg_offset, mux_value) {             \
-        .name           = desc,                                 \
-        .debug          = 0,                                    \
-        .mux_reg        = reg_offset,                           \
-        .mux_val        = mux_value                             \
-},
-
 struct pin_config {
         char                    *name;
         const unsigned int      mux_reg;
         unsigned char           debug;
 
-#if     defined(CONFIG_ARCH_OMAP34XX)
-        u16                     mux_val; /* Wake-up, off mode, pull, mux mode */
-#endif
-
 #if     defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
         const unsigned char mask_offset;
         const unsigned char mask;
@@ -219,11 +172,17 @@ enum omap7xx_index {
         AA17_7XX_USB_DM,
         W16_7XX_USB_PU_EN,
         W17_7XX_USB_VBUSI,
+        W18_7XX_USB_DMCK_OUT,
+        W19_7XX_USB_DCRST,
 
         /* MMC */
         MMC_7XX_CMD,
         MMC_7XX_CLK,
         MMC_7XX_DAT0,
+
+        /* I2C */
+        I2C_7XX_SCL,
+        I2C_7XX_SDA,
 };
 
 enum omap1xxx_index {
@@ -681,181 +640,6 @@ enum omap24xx_index {
 
 };
 
-enum omap34xx_index {
-        /* 34xx I2C */
-        K21_34XX_I2C1_SCL,
-        J21_34XX_I2C1_SDA,
-        AF15_34XX_I2C2_SCL,
-        AE15_34XX_I2C2_SDA,
-        AF14_34XX_I2C3_SCL,
-        AG14_34XX_I2C3_SDA,
-        AD26_34XX_I2C4_SCL,
-        AE26_34XX_I2C4_SDA,
-
-        /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
-        Y8_3430_USB1HS_PHY_CLK,
-        Y9_3430_USB1HS_PHY_STP,
-        AA14_3430_USB1HS_PHY_DIR,
-        AA11_3430_USB1HS_PHY_NXT,
-        W13_3430_USB1HS_PHY_DATA0,
-        W12_3430_USB1HS_PHY_DATA1,
-        W11_3430_USB1HS_PHY_DATA2,
-        Y11_3430_USB1HS_PHY_DATA3,
-        W9_3430_USB1HS_PHY_DATA4,
-        Y12_3430_USB1HS_PHY_DATA5,
-        W8_3430_USB1HS_PHY_DATA6,
-        Y13_3430_USB1HS_PHY_DATA7,
-
-        /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
-        AA8_3430_USB2HS_PHY_CLK,
-        AA10_3430_USB2HS_PHY_STP,
-        AA9_3430_USB2HS_PHY_DIR,
-        AB11_3430_USB2HS_PHY_NXT,
-        AB10_3430_USB2HS_PHY_DATA0,
-        AB9_3430_USB2HS_PHY_DATA1,
-        W3_3430_USB2HS_PHY_DATA2,
-        T4_3430_USB2HS_PHY_DATA3,
-        T3_3430_USB2HS_PHY_DATA4,
-        R3_3430_USB2HS_PHY_DATA5,
-        R4_3430_USB2HS_PHY_DATA6,
-        T2_3430_USB2HS_PHY_DATA7,
-
-
-        /* TLL - HSUSB: 12-pin TLL Port 1*/
-        Y8_3430_USB1HS_TLL_CLK,
-        Y9_3430_USB1HS_TLL_STP,
-        AA14_3430_USB1HS_TLL_DIR,
-        AA11_3430_USB1HS_TLL_NXT,
-        W13_3430_USB1HS_TLL_DATA0,
-        W12_3430_USB1HS_TLL_DATA1,
-        W11_3430_USB1HS_TLL_DATA2,
-        Y11_3430_USB1HS_TLL_DATA3,
-        W9_3430_USB1HS_TLL_DATA4,
-        Y12_3430_USB1HS_TLL_DATA5,
-        W8_3430_USB1HS_TLL_DATA6,
-        Y13_3430_USB1HS_TLL_DATA7,
-
-        /* TLL - HSUSB: 12-pin TLL Port 2*/
-        AA8_3430_USB2HS_TLL_CLK,
-        AA10_3430_USB2HS_TLL_STP,
-        AA9_3430_USB2HS_TLL_DIR,
-        AB11_3430_USB2HS_TLL_NXT,
-        AB10_3430_USB2HS_TLL_DATA0,
-        AB9_3430_USB2HS_TLL_DATA1,
-        W3_3430_USB2HS_TLL_DATA2,
-        T4_3430_USB2HS_TLL_DATA3,
-        T3_3430_USB2HS_TLL_DATA4,
-        R3_3430_USB2HS_TLL_DATA5,
-        R4_3430_USB2HS_TLL_DATA6,
-        T2_3430_USB2HS_TLL_DATA7,
-
-        /* TLL - HSUSB: 12-pin TLL Port 3*/
-        AA6_3430_USB3HS_TLL_CLK,
-        AB3_3430_USB3HS_TLL_STP,
-        AA3_3430_USB3HS_TLL_DIR,
-        Y3_3430_USB3HS_TLL_NXT,
-        AA5_3430_USB3HS_TLL_DATA0,
-        Y4_3430_USB3HS_TLL_DATA1,
-        Y5_3430_USB3HS_TLL_DATA2,
-        W5_3430_USB3HS_TLL_DATA3,
-        AB12_3430_USB3HS_TLL_DATA4,
-        AB13_3430_USB3HS_TLL_DATA5,
-        AA13_3430_USB3HS_TLL_DATA6,
-        AA12_3430_USB3HS_TLL_DATA7,
-
-        /* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
-        AF10_3430_USB1FS_PHY_MM1_RXDP,
-        AG9_3430_USB1FS_PHY_MM1_RXDM,
-        W13_3430_USB1FS_PHY_MM1_RXRCV,
-        W12_3430_USB1FS_PHY_MM1_TXSE0,
-        W11_3430_USB1FS_PHY_MM1_TXDAT,
-        Y11_3430_USB1FS_PHY_MM1_TXEN_N,
-
-        /* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
-        AF7_3430_USB2FS_PHY_MM2_RXDP,
-        AH7_3430_USB2FS_PHY_MM2_RXDM,
-        AB10_3430_USB2FS_PHY_MM2_RXRCV,
-        AB9_3430_USB2FS_PHY_MM2_TXSE0,
-        W3_3430_USB2FS_PHY_MM2_TXDAT,
-        T4_3430_USB2FS_PHY_MM2_TXEN_N,
-
-        /* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
-        AH3_3430_USB3FS_PHY_MM3_RXDP,
-        AE3_3430_USB3FS_PHY_MM3_RXDM,
-        AD1_3430_USB3FS_PHY_MM3_RXRCV,
-        AE1_3430_USB3FS_PHY_MM3_TXSE0,
-        AD2_3430_USB3FS_PHY_MM3_TXDAT,
-        AC1_3430_USB3FS_PHY_MM3_TXEN_N,
-
-        /* 34xx GPIO
-         *  - normally these are bidirectional, no internal pullup/pulldown
-         *  - "_UP" suffix (GPIO3_UP) if internal pullup is configured
-         *  - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
-         *  - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
-         */
-        AF26_34XX_GPIO0,
-        AF22_34XX_GPIO9,
-        AG9_34XX_GPIO23,
-        AH8_34XX_GPIO29,
-        U8_34XX_GPIO54_OUT,
-        U8_34XX_GPIO54_DOWN,
-        L8_34XX_GPIO63,
-        G25_34XX_GPIO86_OUT,
-        AG4_34XX_GPIO134_OUT,
-        AF4_34XX_GPIO135_OUT,
-        AE4_34XX_GPIO136_OUT,
-        AF6_34XX_GPIO140_UP,
-        AE6_34XX_GPIO141,
-        AF5_34XX_GPIO142,
-        AE5_34XX_GPIO143,
-        H19_34XX_GPIO164_OUT,
-        J25_34XX_GPIO170,
-
-        /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
-        H16_34XX_SDRC_CKE0,
-        H17_34XX_SDRC_CKE1,
-
-        /* MMC1 */
-        N28_3430_MMC1_CLK,
-        M27_3430_MMC1_CMD,
-        N27_3430_MMC1_DAT0,
-        N26_3430_MMC1_DAT1,
-        N25_3430_MMC1_DAT2,
-        P28_3430_MMC1_DAT3,
-        P27_3430_MMC1_DAT4,
-        P26_3430_MMC1_DAT5,
-        R27_3430_MMC1_DAT6,
-        R25_3430_MMC1_DAT7,
-
-        /* MMC2 */
-        AE2_3430_MMC2_CLK,
-        AG5_3430_MMC2_CMD,
-        AH5_3430_MMC2_DAT0,
-        AH4_3430_MMC2_DAT1,
-        AG4_3430_MMC2_DAT2,
-        AF4_3430_MMC2_DAT3,
-        AE4_3430_MMC2_DAT4,
-        AH3_3430_MMC2_DAT5,
-        AF3_3430_MMC2_DAT6,
-        AE3_3430_MMC2_DAT7,
-
-        /* MMC3 */
-        AF10_3430_MMC3_CLK,
-        AC3_3430_MMC3_CMD,
-        AE11_3430_MMC3_DAT0,
-        AH9_3430_MMC3_DAT1,
-        AF13_3430_MMC3_DAT2,
-        AF13_3430_MMC3_DAT3,
-
-        /* SYS_NIRQ T2 INT1 */
-        AF26_34XX_SYS_NIRQ,
-
-        /* EHCI GPIO's for OMAP3EVM (Rev >= E) */
-        AH14_34XX_GPIO21,
-        AF9_34XX_GPIO22,
-        U3_34XX_GPIO61,
-};
-
 struct omap_mux_cfg {
         struct pin_config       *pins;
         unsigned long           size;
@@ -865,14 +649,14 @@ struct omap_mux_cfg {
 #ifdef  CONFIG_OMAP_MUX
 /* setup pin muxing in Linux */
 extern int omap1_mux_init(void);
-extern int omap2_mux_init(void);
 extern int omap_mux_register(struct omap_mux_cfg *);
 extern int omap_cfg_reg(unsigned long reg_cfg);
 #else
 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
 static inline int omap1_mux_init(void) { return 0; }
-static inline int omap2_mux_init(void) { return 0; }
 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
 #endif
 
+extern int omap2_mux_init(void);
+
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index e52902a15c1a..ef870de43c29 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -26,8 +26,10 @@
 #define OMAP44XX_EMIF2_BASE             0x4d000000
 #define OMAP44XX_DMM_BASE               0x4e000000
 #define OMAP4430_32KSYNCT_BASE          0x4a304000
-#define OMAP4430_CM_BASE                0x4a004000
-#define OMAP4430_PRM_BASE               0x48306000
+#define OMAP4430_CM1_BASE               0x4a004000
+#define OMAP4430_CM_BASE                OMAP4430_CM1_BASE
+#define OMAP4430_CM2_BASE               0x4a008000
+#define OMAP4430_PRM_BASE               0x4a306000
 #define OMAP44XX_GPMC_BASE              0x50000000
 #define OMAP443X_SCM_BASE               0x4a002000
 #define OMAP443X_CTRL_BASE              OMAP443X_SCM_BASE
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 11a9773a4e7f..dc1fac1d805c 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -50,8 +50,8 @@
  * @pm_lats: ptr to an omap_device_pm_latency table
  * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
  * @pm_lat_level: array index of the last odpl entry executed - -1 if never
- * @dev_wakeup_lat: dev wakeup latency in microseconds
- * @_dev_wakeup_lat_limit: dev wakeup latency limit in usec - set by OMAP PM
+ * @dev_wakeup_lat: dev wakeup latency in nanoseconds
+ * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
  * @_state: one of OMAP_DEVICE_STATE_* (see above)
  * @flags: device flags
  *
@@ -137,5 +137,7 @@ struct omap_device_pm_latency {
 };
 
 
-#endif
+/* Get omap_device pointer from platform_device pointer */
+#define to_omap_device(x) container_of((x), struct omap_device, pdev)
 
+#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index dbdd123eca16..007935a921ea 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -50,6 +50,8 @@ struct omap_device;
 #define SYSC_ENAWAKEUP_MASK             (1 << SYSC_ENAWAKEUP_SHIFT)
 #define SYSC_SOFTRESET_SHIFT            1
 #define SYSC_SOFTRESET_MASK             (1 << SYSC_SOFTRESET_SHIFT)
+#define SYSC_AUTOIDLE_SHIFT             0
+#define SYSC_AUTOIDLE_MASK              (1 << SYSC_AUTOIDLE_SHIFT)
 
 /* OCP SYSSTATUS bit shifts/masks */
 #define SYSS_RESETDONE_SHIFT            0
@@ -62,7 +64,21 @@ struct omap_device;
 
 
 /**
- * struct omap_hwmod_dma_info - MPU address space handled by the hwmod
+ * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
+ * @name: name of the IRQ channel (module local name)
+ * @irq_ch: IRQ channel ID
+ *
+ * @name should be something short, e.g., "tx" or "rx".  It is for use
+ * by platform_get_resource_byname().  It is defined locally to the
+ * hwmod.
+ */
+struct omap_hwmod_irq_info {
+        const char      *name;
+        u16             irq;
+};
+
+/**
+ * struct omap_hwmod_dma_info - DMA channels used by the hwmod
  * @name: name of the DMA channel (module local name)
  * @dma_ch: DMA channel ID
  *
@@ -294,13 +310,17 @@ struct omap_hwmod_omap4_prcm {
  *     SDRAM controller, etc.
  * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
  *     controller, etc.
+ * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
+ *     when module is enabled, rather than the default, which is to
+ *     enable autoidle
  * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
  */
 #define HWMOD_SWSUP_SIDLE                       (1 << 0)
 #define HWMOD_SWSUP_MSTANDBY                    (1 << 1)
 #define HWMOD_INIT_NO_RESET                     (1 << 2)
 #define HWMOD_INIT_NO_IDLE                      (1 << 3)
-#define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 4)
+#define HWMOD_NO_OCP_AUTOIDLE                   (1 << 4)
+#define HWMOD_SET_DEFAULT_CLOCKACT              (1 << 5)
 
 /*
  * omap_hwmod._int_flags definitions
@@ -373,7 +393,7 @@ struct omap_hwmod_omap4_prcm {
 struct omap_hwmod {
         const char                      *name;
         struct omap_device              *od;
-        u8                              *mpu_irqs;
+        struct omap_hwmod_irq_info      *mpu_irqs;
         struct omap_hwmod_dma_info      *sdma_chs;
         union {
                 struct omap_hwmod_omap2_prcm omap2;
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index 3d45ee1d3cf4..0b960051eaed 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -28,6 +28,8 @@
 #define PWRDM_POWER_INACTIVE    0x2
 #define PWRDM_POWER_ON          0x3
 
+#define PWRDM_MAX_PWRSTS        4
+
 /* Powerdomain allowable state bitfields */
 #define PWRSTS_OFF_ON           ((1 << PWRDM_POWER_OFF) | \
                                  (1 << PWRDM_POWER_ON))
@@ -40,7 +42,10 @@
 
 /* Powerdomain flags */
 #define PWRDM_HAS_HDWR_SAR      (1 << 0) /* hardware save-and-restore support */
-
+#define PWRDM_HAS_MPU_QUIRK     (1 << 1) /* MPU pwr domain has MEM bank 0 bits
+                                          * in MEM bank 1 position. This is
+                                          * true for OMAP3430
+                                          */
 
 /*
  * Number of memory banks that are power-controllable.  On OMAP3430, the
@@ -85,15 +90,15 @@ struct powerdomain {
         /* Used to represent the OMAP chip types containing this pwrdm */
         const struct omap_chip_id omap_chip;
 
-        /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
-        const u8 dep_bit;
-
         /* Powerdomains that can be told to wake this powerdomain up */
         struct pwrdm_dep *wkdep_srcs;
 
         /* Powerdomains that can be told to keep this pwrdm from inactivity */
         struct pwrdm_dep *sleepdep_srcs;
 
+        /* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
+        const u8 dep_bit;
+
         /* Possible powerdomain power states */
         const u8 pwrsts;
 
@@ -118,11 +123,11 @@ struct powerdomain {
         struct list_head node;
 
         int state;
-        unsigned state_counter[4];
+        unsigned state_counter[PWRDM_MAX_PWRSTS];
 
 #ifdef CONFIG_PM_DEBUG
         s64 timer;
-        s64 state_timer[4];
+        s64 state_timer[PWRDM_MAX_PWRSTS];
 #endif
 };
 
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 9951345a25d6..f5a4a92393ef 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -53,6 +53,7 @@
 #ifndef __ASSEMBLER__
 extern void __init omap_serial_early_init(void);
 extern void omap_serial_init(void);
+extern void omap_serial_init_port(int port);
 extern int omap_uart_can_sleep(void);
 extern void omap_uart_check_wakeup(void);
 extern void omap_uart_prepare_suspend(void);
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index dcaa8fde7063..8983d54c4fd2 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -28,6 +28,8 @@
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
+extern void omap_auxcoreboot_addr(u32 cpu_addr);
 
 /*
  * We use Soft IRQ1 as the IPI
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 05aebcad215b..06703635ace1 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -54,8 +54,12 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
 {
         struct pin_config *reg;
 
-        if (cpu_is_omap44xx())
-                return 0;
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
+                                index);
+                WARN_ON(1);
+                return -EINVAL;
+        }
 
         if (mux_cfg == NULL) {
                 printk(KERN_ERR "Pin mux table not initialized\n");
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index bb16e624a557..1e5648d3e3d8 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -134,18 +134,18 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
                     (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
                         break;
 
-                getnstimeofday(&a);
+                read_persistent_clock(&a);
 
                 /* XXX check return code */
                 odpl->activate_func(od);
 
-                getnstimeofday(&b);
+                read_persistent_clock(&b);
 
                 c = timespec_sub(b, a);
-                act_lat = timespec_to_ns(&c) * NSEC_PER_USEC;
+                act_lat = timespec_to_ns(&c);
 
                 pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time "
-                         "%llu usec\n", od->pdev.name, od->pm_lat_level,
+                         "%llu nsec\n", od->pdev.name, od->pm_lat_level,
                          act_lat);
 
                 WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: "
@@ -190,18 +190,18 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
                      od->_dev_wakeup_lat_limit))
                         break;
 
-                getnstimeofday(&a);
+                read_persistent_clock(&a);
 
                 /* XXX check return code */
                 odpl->deactivate_func(od);
 
-                getnstimeofday(&b);
+                read_persistent_clock(&b);
 
                 c = timespec_sub(b, a);
-                deact_lat = timespec_to_ns(&c) * NSEC_PER_USEC;
+                deact_lat = timespec_to_ns(&c);
 
                 pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time "
-                         "%llu usec\n", od->pdev.name, od->pm_lat_level,
+                         "%llu nsec\n", od->pdev.name, od->pm_lat_level,
                          deact_lat);
 
                 WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: "
@@ -459,7 +459,7 @@ int omap_device_enable(struct platform_device *pdev)
         ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT);
 
         od->dev_wakeup_lat = 0;
-        od->_dev_wakeup_lat_limit = INT_MAX;
+        od->_dev_wakeup_lat_limit = UINT_MAX;
         od->_state = OMAP_DEVICE_STATE_ENABLED;
 
         return ret;
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index ad2bf07d30b5..d8d5094b37ed 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -48,8 +48,10 @@
 #define OMAP3_SRAM_VA           0xfe400000
 #define OMAP3_SRAM_PUB_PA       0x40208000
 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
-#define OMAP4_SRAM_PA           0x40200000              /*0x402f0000*/
-#define OMAP4_SRAM_VA           0xfe400000              /*0xfe4f0000*/
+#define OMAP4_SRAM_PA           0x40300000
+#define OMAP4_SRAM_VA           0xfe400000
+#define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
+#define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
 
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 #define SRAM_BOOTLOADER_SZ      0x00
@@ -140,6 +142,10 @@ void __init omap_detect_sram(void)
                                 } else {
                                         omap_sram_size = 0x8000; /* 32K */
                                 }
+                        } else if (cpu_is_omap44xx()) {
+                                omap_sram_base = OMAP4_SRAM_PUB_VA;
+                                omap_sram_start = OMAP4_SRAM_PUB_PA;
+                                omap_sram_size = 0xa000; /* 40K */
                         } else {
                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
@@ -153,7 +159,7 @@ void __init omap_detect_sram(void)
                         } else if (cpu_is_omap44xx()) {
                                 omap_sram_base = OMAP4_SRAM_VA;
                                 omap_sram_start = OMAP4_SRAM_PA;
-                                omap_sram_size = 0x8000; /* 32K */
+                                omap_sram_size = 0xe000; /* 56K */
                         } else {
                                 omap_sram_base = OMAP2_SRAM_VA;
                                 omap_sram_start = OMAP2_SRAM_PA;
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 51033a4503c3..d3bf17cd36f3 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -137,7 +137,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
         if (is_device) {
                 if (cpu_is_omap24xx())
                         omap_cfg_reg(J20_24XX_USB0_PUEN);
-                else
+                else if (cpu_is_omap7xx()) {
+                        omap_cfg_reg(AA17_7XX_USB_DM);
+                        omap_cfg_reg(W16_7XX_USB_PU_EN);
+                        omap_cfg_reg(W17_7XX_USB_VBUSI);
+                        omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
+                        omap_cfg_reg(W19_7XX_USB_DCRST);
+                } else
                         omap_cfg_reg(W4_USB_PUEN);
         }
 
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index 7815bfc300f5..54799544bda3 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -206,21 +206,6 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
         }
 }
 
-#elif   defined(CONFIG_ARCH_OMAP)
-
-/* We can only do 16-bit reads and writes in the static memory space. */
-#define SMC_CAN_USE_8BIT        0
-#define SMC_CAN_USE_16BIT       1
-#define SMC_CAN_USE_32BIT       0
-#define SMC_IO_SHIFT            0
-#define SMC_NOWAIT              1
-
-#define SMC_inw(a, r)           readw((a) + (r))
-#define SMC_outw(v, a, r)       writew(v, (a) + (r))
-#define SMC_insw(a, r, p, l)    readsw((a) + (r), p, l)
-#define SMC_outsw(a, r, p, l)   writesw((a) + (r), p, l)
-#define SMC_IRQ_FLAGS           (-1)    /* from resource */
-
 #elif   defined(CONFIG_SH_SH4202_MICRODEV)
 
 #define SMC_CAN_USE_8BIT        0
diff --git a/drivers/video/omap/lcdc.c b/drivers/video/omap/lcdc.c
index b831e1df629e..a33483910dc8 100644
--- a/drivers/video/omap/lcdc.c
+++ b/drivers/video/omap/lcdc.c
@@ -29,6 +29,7 @@
 #include <linux/vmalloc.h>
 #include <linux/clk.h>
 
+#include <mach/lcdc.h>
 #include <plat/dma.h>
 
 #include <asm/mach-types.h>
@@ -39,38 +40,6 @@
 
 #define MODULE_NAME                     "lcdc"
 
-#define OMAP_LCDC_BASE                  0xfffec000
-#define OMAP_LCDC_SIZE                  256
-#define OMAP_LCDC_IRQ                   INT_LCD_CTRL
-
-#define OMAP_LCDC_CONTROL               (OMAP_LCDC_BASE + 0x00)
-#define OMAP_LCDC_TIMING0               (OMAP_LCDC_BASE + 0x04)
-#define OMAP_LCDC_TIMING1               (OMAP_LCDC_BASE + 0x08)
-#define OMAP_LCDC_TIMING2               (OMAP_LCDC_BASE + 0x0c)
-#define OMAP_LCDC_STATUS                (OMAP_LCDC_BASE + 0x10)
-#define OMAP_LCDC_SUBPANEL              (OMAP_LCDC_BASE + 0x14)
-#define OMAP_LCDC_LINE_INT              (OMAP_LCDC_BASE + 0x18)
-#define OMAP_LCDC_DISPLAY_STATUS        (OMAP_LCDC_BASE + 0x1c)
-
-#define OMAP_LCDC_STAT_DONE             (1 << 0)
-#define OMAP_LCDC_STAT_VSYNC            (1 << 1)
-#define OMAP_LCDC_STAT_SYNC_LOST        (1 << 2)
-#define OMAP_LCDC_STAT_ABC              (1 << 3)
-#define OMAP_LCDC_STAT_LINE_INT         (1 << 4)
-#define OMAP_LCDC_STAT_FUF              (1 << 5)
-#define OMAP_LCDC_STAT_LOADED_PALETTE   (1 << 6)
-
-#define OMAP_LCDC_CTRL_LCD_EN           (1 << 0)
-#define OMAP_LCDC_CTRL_LCD_TFT          (1 << 7)
-#define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
-
-#define OMAP_LCDC_IRQ_VSYNC             (1 << 2)
-#define OMAP_LCDC_IRQ_DONE              (1 << 3)
-#define OMAP_LCDC_IRQ_LOADED_PALETTE    (1 << 4)
-#define OMAP_LCDC_IRQ_LINE_NIRQ         (1 << 5)
-#define OMAP_LCDC_IRQ_LINE              (1 << 6)
-#define OMAP_LCDC_IRQ_MASK              (((1 << 5) - 1) << 2)
-
 #define MAX_PALETTE_SIZE                PAGE_SIZE
 
 enum lcdc_load_mode {