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-rw-r--r--arch/mips/Kconfig28
-rw-r--r--arch/mips/Makefile4
-rw-r--r--arch/mips/au1000/common/irq.c63
-rw-r--r--arch/mips/au1000/pb1200/board_setup.c8
-rw-r--r--arch/mips/cobalt/irq.c31
-rw-r--r--arch/mips/cobalt/setup.c16
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq_5477.c23
-rw-r--r--arch/mips/dec/ecc-berr.c6
-rw-r--r--arch/mips/dec/int-handler.S2
-rw-r--r--arch/mips/dec/ioasic-irq.c74
-rw-r--r--arch/mips/dec/kn02-irq.c53
-rw-r--r--arch/mips/dec/setup.c6
-rw-r--r--arch/mips/dec/time.c4
-rw-r--r--arch/mips/emma2rh/common/irq_emma2rh.c35
-rw-r--r--arch/mips/emma2rh/markeins/irq_markeins.c56
-rw-r--r--arch/mips/gt64120/ev64120/irq.c40
-rw-r--r--arch/mips/jazz/irq.c27
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c32
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c4
-rw-r--r--arch/mips/kernel/Makefile3
-rw-r--r--arch/mips/kernel/cpu-probe.c19
-rw-r--r--arch/mips/kernel/dma-no-isa.c28
-rw-r--r--arch/mips/kernel/genex.S63
-rw-r--r--arch/mips/kernel/head.S3
-rw-r--r--arch/mips/kernel/i8259.c21
-rw-r--r--arch/mips/kernel/irq-msc01.c47
-rw-r--r--arch/mips/kernel/irq-mv6434x.c54
-rw-r--r--arch/mips/kernel/irq-rm7000.c54
-rw-r--r--arch/mips/kernel/irq-rm9000.c47
-rw-r--r--arch/mips/kernel/irq.c32
-rw-r--r--arch/mips/kernel/irq_cpu.c80
-rw-r--r--arch/mips/kernel/machine_kexec.c85
-rw-r--r--arch/mips/kernel/module.c15
-rw-r--r--arch/mips/kernel/relocate_kernel.S80
-rw-r--r--arch/mips/kernel/scall32-o32.S2
-rw-r--r--arch/mips/kernel/scall64-64.S2
-rw-r--r--arch/mips/kernel/scall64-n32.S2
-rw-r--r--arch/mips/kernel/scall64-o32.S2
-rw-r--r--arch/mips/kernel/setup.c87
-rw-r--r--arch/mips/kernel/signal_n32.c1
-rw-r--r--arch/mips/kernel/smp-mt.c2
-rw-r--r--arch/mips/kernel/smtc.c1
-rw-r--r--arch/mips/kernel/time.c64
-rw-r--r--arch/mips/kernel/traps.c72
-rw-r--r--arch/mips/lasat/interrupt.c36
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c29
-rw-r--r--arch/mips/mips-boards/generic/time.c1
-rw-r--r--arch/mips/mips-boards/sim/sim_time.c18
-rw-r--r--arch/mips/mm/c-r4k.c22
-rw-r--r--arch/mips/mm/fault.c4
-rw-r--r--arch/mips/mm/init.c42
-rw-r--r--arch/mips/mm/pgtable-64.c3
-rw-r--r--arch/mips/mm/tlbex.c55
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c53
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c56
-rw-r--r--arch/mips/oprofile/Makefile1
-rw-r--r--arch/mips/oprofile/common.c3
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c32
-rw-r--r--arch/mips/pci/fixup-cobalt.c11
-rw-r--r--arch/mips/pci/ops-gt64111.c16
-rw-r--r--arch/mips/philips/pnx8550/common/int.c68
-rw-r--r--arch/mips/pmc-sierra/yosemite/smp.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c33
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c109
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c17
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c32
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c133
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c30
-rw-r--r--arch/mips/sibyte/bcm1480/time.c6
-rw-r--r--arch/mips/sibyte/sb1250/irq.c30
-rw-r--r--arch/mips/sibyte/sb1250/time.c8
-rw-r--r--arch/mips/sni/irq.c40
-rw-r--r--arch/mips/tx4927/common/tx4927_irq.c164
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c184
-rw-r--r--arch/mips/tx4938/common/irq.c115
-rw-r--r--arch/mips/tx4938/common/setup.c1
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/irq.c54
-rw-r--r--arch/mips/vr41xx/common/icu.c48
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/irq.c20
-rw-r--r--include/asm-mips/addrspace.h40
-rw-r--r--include/asm-mips/atomic.h10
-rw-r--r--include/asm-mips/bitops.h65
-rw-r--r--include/asm-mips/bug.h12
-rw-r--r--include/asm-mips/cpu-info.h10
-rw-r--r--include/asm-mips/dec/kn02.h2
-rw-r--r--include/asm-mips/dma.h2
-rw-r--r--include/asm-mips/gt64120.h14
-rw-r--r--include/asm-mips/io.h2
-rw-r--r--include/asm-mips/irq.h8
-rw-r--r--include/asm-mips/kexec.h32
-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h29
-rw-r--r--include/asm-mips/mach-cobalt/mach-gt64120.h28
-rw-r--r--include/asm-mips/mipsregs.h56
-rw-r--r--include/asm-mips/page.h16
-rw-r--r--include/asm-mips/pgtable-64.h13
-rw-r--r--include/asm-mips/pgtable.h2
-rw-r--r--include/asm-mips/ptrace.h2
-rw-r--r--include/asm-mips/time.h9
-rw-r--r--include/linux/kexec.h2
99 files changed, 1081 insertions, 2127 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 22bb540b5c05..27f83e642968 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -266,8 +266,8 @@ config MIPS_MALTA
266 select BOOT_ELF32 266 select BOOT_ELF32
267 select HAVE_STD_PC_SERIAL_PORT 267 select HAVE_STD_PC_SERIAL_PORT
268 select DMA_NONCOHERENT 268 select DMA_NONCOHERENT
269 select IRQ_CPU
270 select GENERIC_ISA_DMA 269 select GENERIC_ISA_DMA
270 select IRQ_CPU
271 select HW_HAS_PCI 271 select HW_HAS_PCI
272 select I8259 272 select I8259
273 select MIPS_BOARDS_GEN 273 select MIPS_BOARDS_GEN
@@ -534,7 +534,7 @@ config SGI_IP22
534 select HW_HAS_EISA 534 select HW_HAS_EISA
535 select IP22_CPU_SCACHE 535 select IP22_CPU_SCACHE
536 select IRQ_CPU 536 select IRQ_CPU
537 select NO_ISA if ISA 537 select GENERIC_ISA_DMA_SUPPORT_BROKEN
538 select SWAP_IO_SPACE 538 select SWAP_IO_SPACE
539 select SYS_HAS_CPU_R4X00 539 select SYS_HAS_CPU_R4X00
540 select SYS_HAS_CPU_R5000 540 select SYS_HAS_CPU_R5000
@@ -766,6 +766,23 @@ config TOSHIBA_RBTX4938
766 766
767endchoice 767endchoice
768 768
769config KEXEC
770 bool "Kexec system call (EXPERIMENTAL)"
771 depends on EXPERIMENTAL
772 help
773 kexec is a system call that implements the ability to shutdown your
774 current kernel, and to start another kernel. It is like a reboot
775 but it is indepedent of the system firmware. And like a reboot
776 you can start any kernel with it, not just Linux.
777
778 The name comes from the similiarity to the exec system call.
779
780 It is an ongoing process to be certain the hardware in a machine
781 is properly shutdown, so do not be surprised if this code does not
782 initially work for you. It may help to enable device hotplugging
783 support. As of this writing the exact hardware interface is
784 strongly in flux, so no good recommendation can be made.
785
769source "arch/mips/ddb5xxx/Kconfig" 786source "arch/mips/ddb5xxx/Kconfig"
770source "arch/mips/gt64120/ev64120/Kconfig" 787source "arch/mips/gt64120/ev64120/Kconfig"
771source "arch/mips/jazz/Kconfig" 788source "arch/mips/jazz/Kconfig"
@@ -864,6 +881,9 @@ config MIPS_NILE4
864config MIPS_DISABLE_OBSOLETE_IDE 881config MIPS_DISABLE_OBSOLETE_IDE
865 bool 882 bool
866 883
884config GENERIC_ISA_DMA_SUPPORT_BROKEN
885 bool
886
867# 887#
868# Endianess selection. Sufficiently obscure so many users don't know what to 888# Endianess selection. Sufficiently obscure so many users don't know what to
869# answer,so we try hard to limit the available choices. Also the use of a 889# answer,so we try hard to limit the available choices. Also the use of a
@@ -1835,13 +1855,11 @@ source "drivers/pci/Kconfig"
1835config ISA 1855config ISA
1836 bool 1856 bool
1837 1857
1838config NO_ISA
1839 bool
1840
1841config EISA 1858config EISA
1842 bool "EISA support" 1859 bool "EISA support"
1843 depends on HW_HAS_EISA 1860 depends on HW_HAS_EISA
1844 select ISA 1861 select ISA
1862 select GENERIC_ISA_DMA
1845 ---help--- 1863 ---help---
1846 The Extended Industry Standard Architecture (EISA) bus was 1864 The Extended Industry Standard Architecture (EISA) bus was
1847 developed as an open alternative to the IBM MicroChannel bus. 1865 developed as an open alternative to the IBM MicroChannel bus.
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index d580d46f967b..641aa30b3638 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -63,9 +63,7 @@ cflags-y += -mabi=64
63ifdef CONFIG_BUILD_ELF64 63ifdef CONFIG_BUILD_ELF64
64cflags-y += $(call cc-option,-mno-explicit-relocs) 64cflags-y += $(call cc-option,-mno-explicit-relocs)
65else 65else
66# -msym32 can not be used for modules since they are loaded into XKSEG 66cflags-y += $(call cc-option,-msym32)
67CFLAGS_MODULE += $(call cc-option,-mno-explicit-relocs)
68CFLAGS_KERNEL += $(call cc-option,-msym32)
69endif 67endif
70endif 68endif
71 69
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index 2abe132bb07d..9cf7b6715836 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -70,7 +70,6 @@ extern irq_cpustat_t irq_stat [NR_CPUS];
70extern void mips_timer_interrupt(void); 70extern void mips_timer_interrupt(void);
71 71
72static void setup_local_irq(unsigned int irq, int type, int int_req); 72static void setup_local_irq(unsigned int irq, int type, int int_req);
73static unsigned int startup_irq(unsigned int irq);
74static void end_irq(unsigned int irq_nr); 73static void end_irq(unsigned int irq_nr);
75static inline void mask_and_ack_level_irq(unsigned int irq_nr); 74static inline void mask_and_ack_level_irq(unsigned int irq_nr);
76static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); 75static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
@@ -84,20 +83,6 @@ void (*board_init_irq)(void);
84static DEFINE_SPINLOCK(irq_lock); 83static DEFINE_SPINLOCK(irq_lock);
85 84
86 85
87static unsigned int startup_irq(unsigned int irq_nr)
88{
89 local_enable_irq(irq_nr);
90 return 0;
91}
92
93
94static void shutdown_irq(unsigned int irq_nr)
95{
96 local_disable_irq(irq_nr);
97 return;
98}
99
100
101inline void local_enable_irq(unsigned int irq_nr) 86inline void local_enable_irq(unsigned int irq_nr)
102{ 87{
103 if (irq_nr > AU1000_LAST_INTC0_INT) { 88 if (irq_nr > AU1000_LAST_INTC0_INT) {
@@ -249,41 +234,37 @@ void restore_local_and_enable(int controller, unsigned long mask)
249 234
250static struct irq_chip rise_edge_irq_type = { 235static struct irq_chip rise_edge_irq_type = {
251 .typename = "Au1000 Rise Edge", 236 .typename = "Au1000 Rise Edge",
252 .startup = startup_irq,
253 .shutdown = shutdown_irq,
254 .enable = local_enable_irq,
255 .disable = local_disable_irq,
256 .ack = mask_and_ack_rise_edge_irq, 237 .ack = mask_and_ack_rise_edge_irq,
238 .mask = local_disable_irq,
239 .mask_ack = mask_and_ack_rise_edge_irq,
240 .unmask = local_enable_irq,
257 .end = end_irq, 241 .end = end_irq,
258}; 242};
259 243
260static struct irq_chip fall_edge_irq_type = { 244static struct irq_chip fall_edge_irq_type = {
261 .typename = "Au1000 Fall Edge", 245 .typename = "Au1000 Fall Edge",
262 .startup = startup_irq,
263 .shutdown = shutdown_irq,
264 .enable = local_enable_irq,
265 .disable = local_disable_irq,
266 .ack = mask_and_ack_fall_edge_irq, 246 .ack = mask_and_ack_fall_edge_irq,
247 .mask = local_disable_irq,
248 .mask_ack = mask_and_ack_fall_edge_irq,
249 .unmask = local_enable_irq,
267 .end = end_irq, 250 .end = end_irq,
268}; 251};
269 252
270static struct irq_chip either_edge_irq_type = { 253static struct irq_chip either_edge_irq_type = {
271 .typename = "Au1000 Rise or Fall Edge", 254 .typename = "Au1000 Rise or Fall Edge",
272 .startup = startup_irq,
273 .shutdown = shutdown_irq,
274 .enable = local_enable_irq,
275 .disable = local_disable_irq,
276 .ack = mask_and_ack_either_edge_irq, 255 .ack = mask_and_ack_either_edge_irq,
256 .mask = local_disable_irq,
257 .mask_ack = mask_and_ack_either_edge_irq,
258 .unmask = local_enable_irq,
277 .end = end_irq, 259 .end = end_irq,
278}; 260};
279 261
280static struct irq_chip level_irq_type = { 262static struct irq_chip level_irq_type = {
281 .typename = "Au1000 Level", 263 .typename = "Au1000 Level",
282 .startup = startup_irq,
283 .shutdown = shutdown_irq,
284 .enable = local_enable_irq,
285 .disable = local_disable_irq,
286 .ack = mask_and_ack_level_irq, 264 .ack = mask_and_ack_level_irq,
265 .mask = local_disable_irq,
266 .mask_ack = mask_and_ack_level_irq,
267 .unmask = local_enable_irq,
287 .end = end_irq, 268 .end = end_irq,
288}; 269};
289 270
@@ -328,31 +309,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
328 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 309 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
329 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 310 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
330 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 311 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
331 irq_desc[irq_nr].chip = &rise_edge_irq_type; 312 set_irq_chip(irq_nr, &rise_edge_irq_type);
332 break; 313 break;
333 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 314 case INTC_INT_FALL_EDGE: /* 0:1:0 */
334 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 315 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
335 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 316 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
336 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 317 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
337 irq_desc[irq_nr].chip = &fall_edge_irq_type; 318 set_irq_chip(irq_nr, &fall_edge_irq_type);
338 break; 319 break;
339 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 320 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
340 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 321 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
341 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 322 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
342 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 323 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
343 irq_desc[irq_nr].chip = &either_edge_irq_type; 324 set_irq_chip(irq_nr, &either_edge_irq_type);
344 break; 325 break;
345 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 326 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
346 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 327 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
347 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 328 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
348 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 329 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
349 irq_desc[irq_nr].chip = &level_irq_type; 330 set_irq_chip(irq_nr, &level_irq_type);
350 break; 331 break;
351 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 332 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
352 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 333 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
353 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 334 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
354 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 335 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
355 irq_desc[irq_nr].chip = &level_irq_type; 336 set_irq_chip(irq_nr, &level_irq_type);
356 break; 337 break;
357 case INTC_INT_DISABLED: /* 0:0:0 */ 338 case INTC_INT_DISABLED: /* 0:0:0 */
358 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 339 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
@@ -380,31 +361,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
380 au_writel(1<<irq_nr, IC0_CFG2CLR); 361 au_writel(1<<irq_nr, IC0_CFG2CLR);
381 au_writel(1<<irq_nr, IC0_CFG1CLR); 362 au_writel(1<<irq_nr, IC0_CFG1CLR);
382 au_writel(1<<irq_nr, IC0_CFG0SET); 363 au_writel(1<<irq_nr, IC0_CFG0SET);
383 irq_desc[irq_nr].chip = &rise_edge_irq_type; 364 set_irq_chip(irq_nr, &rise_edge_irq_type);
384 break; 365 break;
385 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 366 case INTC_INT_FALL_EDGE: /* 0:1:0 */
386 au_writel(1<<irq_nr, IC0_CFG2CLR); 367 au_writel(1<<irq_nr, IC0_CFG2CLR);
387 au_writel(1<<irq_nr, IC0_CFG1SET); 368 au_writel(1<<irq_nr, IC0_CFG1SET);
388 au_writel(1<<irq_nr, IC0_CFG0CLR); 369 au_writel(1<<irq_nr, IC0_CFG0CLR);
389 irq_desc[irq_nr].chip = &fall_edge_irq_type; 370 set_irq_chip(irq_nr, &fall_edge_irq_type);
390 break; 371 break;
391 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 372 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
392 au_writel(1<<irq_nr, IC0_CFG2CLR); 373 au_writel(1<<irq_nr, IC0_CFG2CLR);
393 au_writel(1<<irq_nr, IC0_CFG1SET); 374 au_writel(1<<irq_nr, IC0_CFG1SET);
394 au_writel(1<<irq_nr, IC0_CFG0SET); 375 au_writel(1<<irq_nr, IC0_CFG0SET);
395 irq_desc[irq_nr].chip = &either_edge_irq_type; 376 set_irq_chip(irq_nr, &either_edge_irq_type);
396 break; 377 break;
397 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 378 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
398 au_writel(1<<irq_nr, IC0_CFG2SET); 379 au_writel(1<<irq_nr, IC0_CFG2SET);
399 au_writel(1<<irq_nr, IC0_CFG1CLR); 380 au_writel(1<<irq_nr, IC0_CFG1CLR);
400 au_writel(1<<irq_nr, IC0_CFG0SET); 381 au_writel(1<<irq_nr, IC0_CFG0SET);
401 irq_desc[irq_nr].chip = &level_irq_type; 382 set_irq_chip(irq_nr, &level_irq_type);
402 break; 383 break;
403 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 384 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
404 au_writel(1<<irq_nr, IC0_CFG2SET); 385 au_writel(1<<irq_nr, IC0_CFG2SET);
405 au_writel(1<<irq_nr, IC0_CFG1SET); 386 au_writel(1<<irq_nr, IC0_CFG1SET);
406 au_writel(1<<irq_nr, IC0_CFG0CLR); 387 au_writel(1<<irq_nr, IC0_CFG0CLR);
407 irq_desc[irq_nr].chip = &level_irq_type; 388 set_irq_chip(irq_nr, &level_irq_type);
408 break; 389 break;
409 case INTC_INT_DISABLED: /* 0:0:0 */ 390 case INTC_INT_DISABLED: /* 0:0:0 */
410 au_writel(1<<irq_nr, IC0_CFG0CLR); 391 au_writel(1<<irq_nr, IC0_CFG0CLR);
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c
index 8b953b9fc25c..043302b7fe58 100644
--- a/arch/mips/au1000/pb1200/board_setup.c
+++ b/arch/mips/au1000/pb1200/board_setup.c
@@ -55,7 +55,7 @@
55#endif 55#endif
56 56
57extern void _board_init_irq(void); 57extern void _board_init_irq(void);
58extern void (*board_init_irq)(void); 58extern void (*board_init_irq)(void);
59 59
60void board_reset (void) 60void board_reset (void)
61{ 61{
@@ -151,11 +151,7 @@ void __init board_setup(void)
151#endif 151#endif
152 152
153 /* Setup Pb1200 External Interrupt Controller */ 153 /* Setup Pb1200 External Interrupt Controller */
154 { 154 board_init_irq = _board_init_irq;
155 extern void (*board_init_irq)(void);
156 extern void _board_init_irq(void);
157 board_init_irq = _board_init_irq;
158 }
159} 155}
160 156
161int 157int
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index 82e569d5b02c..4c46f0e73783 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -45,25 +45,22 @@ static inline void galileo_irq(void)
45{ 45{
46 unsigned int mask, pending, devfn; 46 unsigned int mask, pending, devfn;
47 47
48 mask = GALILEO_INL(GT_INTRMASK_OFS); 48 mask = GT_READ(GT_INTRMASK_OFS);
49 pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask; 49 pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
50 50
51 if (pending & GALILEO_INTR_T0EXP) { 51 if (pending & GT_INTR_T0EXP_MSK) {
52 52 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
53 GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
54 do_IRQ(COBALT_GALILEO_IRQ); 53 do_IRQ(COBALT_GALILEO_IRQ);
55 54 } else if (pending & GT_INTR_RETRYCTR0_MSK) {
56 } else if (pending & GALILEO_INTR_RETRY_CTR) { 55 devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
57 56 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
58 devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8; 57 printk(KERN_WARNING
59 GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS); 58 "Galileo: PCI retry count exceeded (%02x.%u)\n",
60 printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n", 59 PCI_SLOT(devfn), PCI_FUNC(devfn));
61 PCI_SLOT(devfn), PCI_FUNC(devfn));
62
63 } else { 60 } else {
64 61 GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
65 GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS); 62 printk(KERN_WARNING
66 printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending); 63 "Galileo: masking unexpected interrupt %08x\n", pending);
67 } 64 }
68} 65}
69 66
@@ -104,7 +101,7 @@ void __init arch_init_irq(void)
104 * Mask all Galileo interrupts. The Galileo 101 * Mask all Galileo interrupts. The Galileo
105 * handler is set in cobalt_timer_setup() 102 * handler is set in cobalt_timer_setup()
106 */ 103 */
107 GALILEO_OUTL(0, GT_INTRMASK_OFS); 104 GT_WRITE(GT_INTRMASK_OFS, 0);
108 105
109 init_i8259_irqs(); /* 0 ... 15 */ 106 init_i8259_irqs(); /* 0 ... 15 */
110 mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */ 107 mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index bf9dc72b9720..e8f0f20b852d 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -51,23 +51,23 @@ const char *get_system_type(void)
51void __init plat_timer_setup(struct irqaction *irq) 51void __init plat_timer_setup(struct irqaction *irq)
52{ 52{
53 /* Load timer value for HZ (TCLK is 50MHz) */ 53 /* Load timer value for HZ (TCLK is 50MHz) */
54 GALILEO_OUTL(50*1000*1000 / HZ, GT_TC0_OFS); 54 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
55 55
56 /* Enable timer */ 56 /* Enable timer */
57 GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS); 57 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
58 58
59 /* Register interrupt */ 59 /* Register interrupt */
60 setup_irq(COBALT_GALILEO_IRQ, irq); 60 setup_irq(COBALT_GALILEO_IRQ, irq);
61 61
62 /* Enable interrupt */ 62 /* Enable interrupt */
63 GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); 63 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
64} 64}
65 65
66extern struct pci_ops gt64111_pci_ops; 66extern struct pci_ops gt64111_pci_ops;
67 67
68static struct resource cobalt_mem_resource = { 68static struct resource cobalt_mem_resource = {
69 .start = GT64111_MEM_BASE, 69 .start = GT_DEF_PCI0_MEM0_BASE,
70 .end = GT64111_MEM_END, 70 .end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
71 .name = "PCI memory", 71 .name = "PCI memory",
72 .flags = IORESOURCE_MEM 72 .flags = IORESOURCE_MEM
73}; 73};
@@ -115,7 +115,7 @@ static struct pci_controller cobalt_pci_controller = {
115 .mem_resource = &cobalt_mem_resource, 115 .mem_resource = &cobalt_mem_resource,
116 .mem_offset = 0, 116 .mem_offset = 0,
117 .io_resource = &cobalt_io_resource, 117 .io_resource = &cobalt_io_resource,
118 .io_offset = 0 - GT64111_IO_BASE 118 .io_offset = 0 - GT_DEF_PCI0_IO_BASE,
119}; 119};
120 120
121void __init plat_mem_setup(void) 121void __init plat_mem_setup(void)
@@ -128,7 +128,7 @@ void __init plat_mem_setup(void)
128 _machine_halt = cobalt_machine_halt; 128 _machine_halt = cobalt_machine_halt;
129 pm_power_off = cobalt_machine_power_off; 129 pm_power_off = cobalt_machine_power_off;
130 130
131 set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE)); 131 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
132 132
133 /* I/O port resource must include UART and LCD/buttons */ 133 /* I/O port resource must include UART and LCD/buttons */
134 ioport_resource.end = 0x0fffffff; 134 ioport_resource.end = 0x0fffffff;
@@ -139,7 +139,7 @@ void __init plat_mem_setup(void)
139 139
140 /* Read the cobalt id register out of the PCI config space */ 140 /* Read the cobalt id register out of the PCI config space */
141 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); 141 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
142 cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 142 cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);
143 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8); 143 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
144 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); 144 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
145 145
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
index ba52705a2738..96249aa5df5d 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq_5477.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
@@ -53,14 +53,6 @@ vrc5477_irq_disable(unsigned int irq)
53 ll_vrc5477_irq_disable(irq - vrc5477_irq_base); 53 ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
54} 54}
55 55
56static unsigned int vrc5477_irq_startup(unsigned int irq)
57{
58 vrc5477_irq_enable(irq);
59 return 0;
60}
61
62#define vrc5477_irq_shutdown vrc5477_irq_disable
63
64static void 56static void
65vrc5477_irq_ack(unsigned int irq) 57vrc5477_irq_ack(unsigned int irq)
66{ 58{
@@ -91,11 +83,10 @@ vrc5477_irq_end(unsigned int irq)
91 83
92struct irq_chip vrc5477_irq_controller = { 84struct irq_chip vrc5477_irq_controller = {
93 .typename = "vrc5477_irq", 85 .typename = "vrc5477_irq",
94 .startup = vrc5477_irq_startup,
95 .shutdown = vrc5477_irq_shutdown,
96 .enable = vrc5477_irq_enable,
97 .disable = vrc5477_irq_disable,
98 .ack = vrc5477_irq_ack, 86 .ack = vrc5477_irq_ack,
87 .mask = vrc5477_irq_disable,
88 .mask_ack = vrc5477_irq_ack,
89 .unmask = vrc5477_irq_enable,
99 .end = vrc5477_irq_end 90 .end = vrc5477_irq_end
100}; 91};
101 92
@@ -103,12 +94,8 @@ void __init vrc5477_irq_init(u32 irq_base)
103{ 94{
104 u32 i; 95 u32 i;
105 96
106 for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++) { 97 for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++)
107 irq_desc[i].status = IRQ_DISABLED; 98 set_irq_chip(i, &vrc5477_irq_controller);
108 irq_desc[i].action = NULL;
109 irq_desc[i].depth = 1;
110 irq_desc[i].chip = &vrc5477_irq_controller;
111 }
112 99
113 vrc5477_irq_base = irq_base; 100 vrc5477_irq_base = irq_base;
114} 101}
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 3e374d05978f..c8430c07355e 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -18,7 +18,6 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/sched.h> 20#include <linux/sched.h>
21#include <linux/spinlock.h>
22#include <linux/types.h> 21#include <linux/types.h>
23 22
24#include <asm/addrspace.h> 23#include <asm/addrspace.h>
@@ -231,13 +230,10 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id)
231static inline void dec_kn02_be_init(void) 230static inline void dec_kn02_be_init(void)
232{ 231{
233 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); 232 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
234 unsigned long flags;
235 233
236 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); 234 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
237 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); 235 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
238 236
239 spin_lock_irqsave(&kn02_lock, flags);
240
241 /* Preset write-only bits of the Control Register cache. */ 237 /* Preset write-only bits of the Control Register cache. */
242 cached_kn02_csr = *csr | KN02_CSR_LEDS; 238 cached_kn02_csr = *csr | KN02_CSR_LEDS;
243 239
@@ -247,8 +243,6 @@ static inline void dec_kn02_be_init(void)
247 cached_kn02_csr |= KN02_CSR_CORRECT; 243 cached_kn02_csr |= KN02_CSR_CORRECT;
248 *csr = cached_kn02_csr; 244 *csr = cached_kn02_csr;
249 iob(); 245 iob();
250
251 spin_unlock_irqrestore(&kn02_lock, flags);
252} 246}
253 247
254static inline void dec_kn03_be_init(void) 248static inline void dec_kn03_be_init(void)
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index 31dd47d1002d..b251ef864c33 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -267,7 +267,7 @@ handle_it:
267 LONG_L s0, TI_REGS($28) 267 LONG_L s0, TI_REGS($28)
268 LONG_S sp, TI_REGS($28) 268 LONG_S sp, TI_REGS($28)
269 PTR_LA ra, ret_from_irq 269 PTR_LA ra, ret_from_irq
270 j do_IRQ 270 j dec_irq_dispatch
271 nop 271 nop
272 272
273#ifdef CONFIG_32BIT 273#ifdef CONFIG_32BIT
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 41cd2a96148b..269b22b34313 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -13,7 +13,6 @@
13 13
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <linux/spinlock.h>
17#include <linux/types.h> 16#include <linux/types.h>
18 17
19#include <asm/dec/ioasic.h> 18#include <asm/dec/ioasic.h>
@@ -21,8 +20,6 @@
21#include <asm/dec/ioasic_ints.h> 20#include <asm/dec/ioasic_ints.h>
22 21
23 22
24static DEFINE_SPINLOCK(ioasic_lock);
25
26static int ioasic_irq_base; 23static int ioasic_irq_base;
27 24
28 25
@@ -52,65 +49,31 @@ static inline void clear_ioasic_irq(unsigned int irq)
52 ioasic_write(IO_REG_SIR, sir); 49 ioasic_write(IO_REG_SIR, sir);
53} 50}
54 51
55static inline void enable_ioasic_irq(unsigned int irq)
56{
57 unsigned long flags;
58
59 spin_lock_irqsave(&ioasic_lock, flags);
60 unmask_ioasic_irq(irq);
61 spin_unlock_irqrestore(&ioasic_lock, flags);
62}
63
64static inline void disable_ioasic_irq(unsigned int irq)
65{
66 unsigned long flags;
67
68 spin_lock_irqsave(&ioasic_lock, flags);
69 mask_ioasic_irq(irq);
70 spin_unlock_irqrestore(&ioasic_lock, flags);
71}
72
73
74static inline unsigned int startup_ioasic_irq(unsigned int irq)
75{
76 enable_ioasic_irq(irq);
77 return 0;
78}
79
80#define shutdown_ioasic_irq disable_ioasic_irq
81
82static inline void ack_ioasic_irq(unsigned int irq) 52static inline void ack_ioasic_irq(unsigned int irq)
83{ 53{
84 spin_lock(&ioasic_lock);
85 mask_ioasic_irq(irq); 54 mask_ioasic_irq(irq);
86 spin_unlock(&ioasic_lock);
87 fast_iob(); 55 fast_iob();
88} 56}
89 57
90static inline void end_ioasic_irq(unsigned int irq) 58static inline void end_ioasic_irq(unsigned int irq)
91{ 59{
92 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 60 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
93 enable_ioasic_irq(irq); 61 unmask_ioasic_irq(irq);
94} 62}
95 63
96static struct irq_chip ioasic_irq_type = { 64static struct irq_chip ioasic_irq_type = {
97 .typename = "IO-ASIC", 65 .typename = "IO-ASIC",
98 .startup = startup_ioasic_irq,
99 .shutdown = shutdown_ioasic_irq,
100 .enable = enable_ioasic_irq,
101 .disable = disable_ioasic_irq,
102 .ack = ack_ioasic_irq, 66 .ack = ack_ioasic_irq,
67 .mask = mask_ioasic_irq,
68 .mask_ack = ack_ioasic_irq,
69 .unmask = unmask_ioasic_irq,
103 .end = end_ioasic_irq, 70 .end = end_ioasic_irq,
104}; 71};
105 72
106 73
107#define startup_ioasic_dma_irq startup_ioasic_irq 74#define unmask_ioasic_dma_irq unmask_ioasic_irq
108
109#define shutdown_ioasic_dma_irq shutdown_ioasic_irq
110
111#define enable_ioasic_dma_irq enable_ioasic_irq
112 75
113#define disable_ioasic_dma_irq disable_ioasic_irq 76#define mask_ioasic_dma_irq mask_ioasic_irq
114 77
115#define ack_ioasic_dma_irq ack_ioasic_irq 78#define ack_ioasic_dma_irq ack_ioasic_irq
116 79
@@ -123,11 +86,10 @@ static inline void end_ioasic_dma_irq(unsigned int irq)
123 86
124static struct irq_chip ioasic_dma_irq_type = { 87static struct irq_chip ioasic_dma_irq_type = {
125 .typename = "IO-ASIC-DMA", 88 .typename = "IO-ASIC-DMA",
126 .startup = startup_ioasic_dma_irq,
127 .shutdown = shutdown_ioasic_dma_irq,
128 .enable = enable_ioasic_dma_irq,
129 .disable = disable_ioasic_dma_irq,
130 .ack = ack_ioasic_dma_irq, 89 .ack = ack_ioasic_dma_irq,
90 .mask = mask_ioasic_dma_irq,
91 .mask_ack = ack_ioasic_dma_irq,
92 .unmask = unmask_ioasic_dma_irq,
131 .end = end_ioasic_dma_irq, 93 .end = end_ioasic_dma_irq,
132}; 94};
133 95
@@ -140,18 +102,12 @@ void __init init_ioasic_irqs(int base)
140 ioasic_write(IO_REG_SIMR, 0); 102 ioasic_write(IO_REG_SIMR, 0);
141 fast_iob(); 103 fast_iob();
142 104
143 for (i = base; i < base + IO_INR_DMA; i++) { 105 for (i = base; i < base + IO_INR_DMA; i++)
144 irq_desc[i].status = IRQ_DISABLED; 106 set_irq_chip_and_handler(i, &ioasic_irq_type,
145 irq_desc[i].action = 0; 107 handle_level_irq);
146 irq_desc[i].depth = 1; 108 for (; i < base + IO_IRQ_LINES; i++)
147 irq_desc[i].chip = &ioasic_irq_type; 109 set_irq_chip_and_handler(i, &ioasic_dma_irq_type,
148 } 110 handle_level_irq);
149 for (; i < base + IO_IRQ_LINES; i++) {
150 irq_desc[i].status = IRQ_DISABLED;
151 irq_desc[i].action = 0;
152 irq_desc[i].depth = 1;
153 irq_desc[i].chip = &ioasic_dma_irq_type;
154 }
155 111
156 ioasic_irq_base = base; 112 ioasic_irq_base = base;
157} 113}
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index 04a367a60a57..5a9be4c93584 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -14,7 +14,6 @@
14 14
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/spinlock.h>
18#include <linux/types.h> 17#include <linux/types.h>
19 18
20#include <asm/dec/kn02.h> 19#include <asm/dec/kn02.h>
@@ -29,7 +28,6 @@
29 * There is no default value -- it has to be initialized. 28 * There is no default value -- it has to be initialized.
30 */ 29 */
31u32 cached_kn02_csr; 30u32 cached_kn02_csr;
32DEFINE_SPINLOCK(kn02_lock);
33 31
34 32
35static int kn02_irq_base; 33static int kn02_irq_base;
@@ -53,54 +51,24 @@ static inline void mask_kn02_irq(unsigned int irq)
53 *csr = cached_kn02_csr; 51 *csr = cached_kn02_csr;
54} 52}
55 53
56static inline void enable_kn02_irq(unsigned int irq)
57{
58 unsigned long flags;
59
60 spin_lock_irqsave(&kn02_lock, flags);
61 unmask_kn02_irq(irq);
62 spin_unlock_irqrestore(&kn02_lock, flags);
63}
64
65static inline void disable_kn02_irq(unsigned int irq)
66{
67 unsigned long flags;
68
69 spin_lock_irqsave(&kn02_lock, flags);
70 mask_kn02_irq(irq);
71 spin_unlock_irqrestore(&kn02_lock, flags);
72}
73
74
75static unsigned int startup_kn02_irq(unsigned int irq)
76{
77 enable_kn02_irq(irq);
78 return 0;
79}
80
81#define shutdown_kn02_irq disable_kn02_irq
82
83static void ack_kn02_irq(unsigned int irq) 54static void ack_kn02_irq(unsigned int irq)
84{ 55{
85 spin_lock(&kn02_lock);
86 mask_kn02_irq(irq); 56 mask_kn02_irq(irq);
87 spin_unlock(&kn02_lock);
88 iob(); 57 iob();
89} 58}
90 59
91static void end_kn02_irq(unsigned int irq) 60static void end_kn02_irq(unsigned int irq)
92{ 61{
93 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 62 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
94 enable_kn02_irq(irq); 63 unmask_kn02_irq(irq);
95} 64}
96 65
97static struct irq_chip kn02_irq_type = { 66static struct irq_chip kn02_irq_type = {
98 .typename = "KN02-CSR", 67 .typename = "KN02-CSR",
99 .startup = startup_kn02_irq,
100 .shutdown = shutdown_kn02_irq,
101 .enable = enable_kn02_irq,
102 .disable = disable_kn02_irq,
103 .ack = ack_kn02_irq, 68 .ack = ack_kn02_irq,
69 .mask = mask_kn02_irq,
70 .mask_ack = ack_kn02_irq,
71 .unmask = unmask_kn02_irq,
104 .end = end_kn02_irq, 72 .end = end_kn02_irq,
105}; 73};
106 74
@@ -109,22 +77,15 @@ void __init init_kn02_irqs(int base)
109{ 77{
110 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 78 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
111 KN02_CSR); 79 KN02_CSR);
112 unsigned long flags;
113 int i; 80 int i;
114 81
115 /* Mask interrupts. */ 82 /* Mask interrupts. */
116 spin_lock_irqsave(&kn02_lock, flags);
117 cached_kn02_csr &= ~KN02_CSR_IOINTEN; 83 cached_kn02_csr &= ~KN02_CSR_IOINTEN;
118 *csr = cached_kn02_csr; 84 *csr = cached_kn02_csr;
119 iob(); 85 iob();
120 spin_unlock_irqrestore(&kn02_lock, flags); 86
121 87 for (i = base; i < base + KN02_IRQ_LINES; i++)
122 for (i = base; i < base + KN02_IRQ_LINES; i++) { 88 set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
123 irq_desc[i].status = IRQ_DISABLED;
124 irq_desc[i].action = 0;
125 irq_desc[i].depth = 1;
126 irq_desc[i].chip = &kn02_irq_type;
127 }
128 89
129 kn02_irq_base = base; 90 kn02_irq_base = base;
130} 91}
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index 6b7481e97bec..d34032ac492a 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -761,3 +761,9 @@ void __init arch_init_irq(void)
761 if (dec_interrupt[DEC_IRQ_HALT] >= 0) 761 if (dec_interrupt[DEC_IRQ_HALT] >= 0)
762 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); 762 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
763} 763}
764
765asmlinkage unsigned int dec_irq_dispatch(unsigned int irq)
766{
767 do_IRQ(irq);
768 return 0;
769}
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 69e424e9ab6f..8b7e0c17ac35 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -151,7 +151,7 @@ static void dec_timer_ack(void)
151 CMOS_READ(RTC_REG_C); /* Ack the RTC interrupt. */ 151 CMOS_READ(RTC_REG_C); /* Ack the RTC interrupt. */
152} 152}
153 153
154static unsigned int dec_ioasic_hpt_read(void) 154static cycle_t dec_ioasic_hpt_read(void)
155{ 155{
156 /* 156 /*
157 * The free-running counter is 32-bit which is good for about 157 * The free-running counter is 32-bit which is good for about
@@ -171,7 +171,7 @@ void __init dec_time_init(void)
171 171
172 if (!cpu_has_counter && IOASIC) 172 if (!cpu_has_counter && IOASIC)
173 /* For pre-R4k systems we use the I/O ASIC's counter. */ 173 /* For pre-R4k systems we use the I/O ASIC's counter. */
174 mips_hpt_read = dec_ioasic_hpt_read; 174 clocksource_mips.read = dec_ioasic_hpt_read;
175 175
176 /* Set up the rate of periodic DS1287 interrupts. */ 176 /* Set up the rate of periodic DS1287 interrupts. */
177 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A); 177 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);
diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c
index 197ed4c2ba04..59b98299c896 100644
--- a/arch/mips/emma2rh/common/irq_emma2rh.c
+++ b/arch/mips/emma2rh/common/irq_emma2rh.c
@@ -56,22 +56,6 @@ static void emma2rh_irq_disable(unsigned int irq)
56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base); 56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
57} 57}
58 58
59static unsigned int emma2rh_irq_startup(unsigned int irq)
60{
61 emma2rh_irq_enable(irq);
62 return 0;
63}
64
65#define emma2rh_irq_shutdown emma2rh_irq_disable
66
67static void emma2rh_irq_ack(unsigned int irq)
68{
69 /* disable interrupt - some handler will re-enable the irq
70 * and if the interrupt is leveled, we will have infinite loop
71 */
72 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
73}
74
75static void emma2rh_irq_end(unsigned int irq) 59static void emma2rh_irq_end(unsigned int irq)
76{ 60{
77 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 61 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -80,25 +64,20 @@ static void emma2rh_irq_end(unsigned int irq)
80 64
81struct irq_chip emma2rh_irq_controller = { 65struct irq_chip emma2rh_irq_controller = {
82 .typename = "emma2rh_irq", 66 .typename = "emma2rh_irq",
83 .startup = emma2rh_irq_startup, 67 .ack = emma2rh_irq_disable,
84 .shutdown = emma2rh_irq_shutdown, 68 .mask = emma2rh_irq_disable,
85 .enable = emma2rh_irq_enable, 69 .mask_ack = emma2rh_irq_disable,
86 .disable = emma2rh_irq_disable, 70 .unmask = emma2rh_irq_enable,
87 .ack = emma2rh_irq_ack,
88 .end = emma2rh_irq_end, 71 .end = emma2rh_irq_end,
89 .set_affinity = NULL /* no affinity stuff for UP */
90}; 72};
91 73
92void emma2rh_irq_init(u32 irq_base) 74void emma2rh_irq_init(u32 irq_base)
93{ 75{
94 u32 i; 76 u32 i;
95 77
96 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) { 78 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++)
97 irq_desc[i].status = IRQ_DISABLED; 79 set_irq_chip_and_handler(i, &emma2rh_irq_controller,
98 irq_desc[i].action = NULL; 80 handle_level_irq);
99 irq_desc[i].depth = 1;
100 irq_desc[i].chip = &emma2rh_irq_controller;
101 }
102 81
103 emma2rh_irq_base = irq_base; 82 emma2rh_irq_base = irq_base;
104} 83}
diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c
index 0b36eb001e62..3ac4e405ecdc 100644
--- a/arch/mips/emma2rh/markeins/irq_markeins.c
+++ b/arch/mips/emma2rh/markeins/irq_markeins.c
@@ -48,19 +48,6 @@ static void emma2rh_sw_irq_disable(unsigned int irq)
48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base); 48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
49} 49}
50 50
51static unsigned int emma2rh_sw_irq_startup(unsigned int irq)
52{
53 emma2rh_sw_irq_enable(irq);
54 return 0;
55}
56
57#define emma2rh_sw_irq_shutdown emma2rh_sw_irq_disable
58
59static void emma2rh_sw_irq_ack(unsigned int irq)
60{
61 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
62}
63
64static void emma2rh_sw_irq_end(unsigned int irq) 51static void emma2rh_sw_irq_end(unsigned int irq)
65{ 52{
66 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 53 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -69,25 +56,20 @@ static void emma2rh_sw_irq_end(unsigned int irq)
69 56
70struct irq_chip emma2rh_sw_irq_controller = { 57struct irq_chip emma2rh_sw_irq_controller = {
71 .typename = "emma2rh_sw_irq", 58 .typename = "emma2rh_sw_irq",
72 .startup = emma2rh_sw_irq_startup, 59 .ack = emma2rh_sw_irq_disable,
73 .shutdown = emma2rh_sw_irq_shutdown, 60 .mask = emma2rh_sw_irq_disable,
74 .enable = emma2rh_sw_irq_enable, 61 .mask_ack = emma2rh_sw_irq_disable,
75 .disable = emma2rh_sw_irq_disable, 62 .unmask = emma2rh_sw_irq_enable,
76 .ack = emma2rh_sw_irq_ack,
77 .end = emma2rh_sw_irq_end, 63 .end = emma2rh_sw_irq_end,
78 .set_affinity = NULL,
79}; 64};
80 65
81void emma2rh_sw_irq_init(u32 irq_base) 66void emma2rh_sw_irq_init(u32 irq_base)
82{ 67{
83 u32 i; 68 u32 i;
84 69
85 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) { 70 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++)
86 irq_desc[i].status = IRQ_DISABLED; 71 set_irq_chip_and_handler(i, &emma2rh_sw_irq_controller,
87 irq_desc[i].action = NULL; 72 handle_level_irq);
88 irq_desc[i].depth = 2;
89 irq_desc[i].chip = &emma2rh_sw_irq_controller;
90 }
91 73
92 emma2rh_sw_irq_base = irq_base; 74 emma2rh_sw_irq_base = irq_base;
93} 75}
@@ -126,14 +108,6 @@ static void emma2rh_gpio_irq_disable(unsigned int irq)
126 ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base); 108 ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
127} 109}
128 110
129static unsigned int emma2rh_gpio_irq_startup(unsigned int irq)
130{
131 emma2rh_gpio_irq_enable(irq);
132 return 0;
133}
134
135#define emma2rh_gpio_irq_shutdown emma2rh_gpio_irq_disable
136
137static void emma2rh_gpio_irq_ack(unsigned int irq) 111static void emma2rh_gpio_irq_ack(unsigned int irq)
138{ 112{
139 irq -= emma2rh_gpio_irq_base; 113 irq -= emma2rh_gpio_irq_base;
@@ -149,25 +123,19 @@ static void emma2rh_gpio_irq_end(unsigned int irq)
149 123
150struct irq_chip emma2rh_gpio_irq_controller = { 124struct irq_chip emma2rh_gpio_irq_controller = {
151 .typename = "emma2rh_gpio_irq", 125 .typename = "emma2rh_gpio_irq",
152 .startup = emma2rh_gpio_irq_startup,
153 .shutdown = emma2rh_gpio_irq_shutdown,
154 .enable = emma2rh_gpio_irq_enable,
155 .disable = emma2rh_gpio_irq_disable,
156 .ack = emma2rh_gpio_irq_ack, 126 .ack = emma2rh_gpio_irq_ack,
127 .mask = emma2rh_gpio_irq_disable,
128 .mask_ack = emma2rh_gpio_irq_ack,
129 .unmask = emma2rh_gpio_irq_enable,
157 .end = emma2rh_gpio_irq_end, 130 .end = emma2rh_gpio_irq_end,
158 .set_affinity = NULL,
159}; 131};
160 132
161void emma2rh_gpio_irq_init(u32 irq_base) 133void emma2rh_gpio_irq_init(u32 irq_base)
162{ 134{
163 u32 i; 135 u32 i;
164 136
165 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) { 137 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++)
166 irq_desc[i].status = IRQ_DISABLED; 138 set_irq_chip(i, &emma2rh_gpio_irq_controller);
167 irq_desc[i].action = NULL;
168 irq_desc[i].depth = 2;
169 irq_desc[i].chip = &emma2rh_gpio_irq_controller;
170 }
171 139
172 emma2rh_gpio_irq_base = irq_base; 140 emma2rh_gpio_irq_base = irq_base;
173} 141}
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
index ed4d82b9a24a..b3e5796c81d7 100644
--- a/arch/mips/gt64120/ev64120/irq.c
+++ b/arch/mips/gt64120/ev64120/irq.c
@@ -66,38 +66,21 @@ asmlinkage void plat_irq_dispatch(void)
66 66
67static void disable_ev64120_irq(unsigned int irq_nr) 67static void disable_ev64120_irq(unsigned int irq_nr)
68{ 68{
69 unsigned long flags;
70
71 local_irq_save(flags);
72 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2 69 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2
73 clear_c0_status(9 << 10); 70 clear_c0_status(9 << 10);
74 } else { 71 } else {
75 clear_c0_status(1 << (irq_nr + 8)); 72 clear_c0_status(1 << (irq_nr + 8));
76 } 73 }
77 local_irq_restore(flags);
78} 74}
79 75
80static void enable_ev64120_irq(unsigned int irq_nr) 76static void enable_ev64120_irq(unsigned int irq_nr)
81{ 77{
82 unsigned long flags;
83
84 local_irq_save(flags);
85 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2 78 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2
86 set_c0_status(9 << 10); 79 set_c0_status(9 << 10);
87 else 80 else
88 set_c0_status(1 << (irq_nr + 8)); 81 set_c0_status(1 << (irq_nr + 8));
89 local_irq_restore(flags);
90}
91
92static unsigned int startup_ev64120_irq(unsigned int irq)
93{
94 enable_ev64120_irq(irq);
95 return 0; /* Never anything pending */
96} 82}
97 83
98#define shutdown_ev64120_irq disable_ev64120_irq
99#define mask_and_ack_ev64120_irq disable_ev64120_irq
100
101static void end_ev64120_irq(unsigned int irq) 84static void end_ev64120_irq(unsigned int irq)
102{ 85{
103 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 86 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -106,13 +89,11 @@ static void end_ev64120_irq(unsigned int irq)
106 89
107static struct irq_chip ev64120_irq_type = { 90static struct irq_chip ev64120_irq_type = {
108 .typename = "EV64120", 91 .typename = "EV64120",
109 .startup = startup_ev64120_irq, 92 .ack = disable_ev64120_irq,
110 .shutdown = shutdown_ev64120_irq, 93 .mask = disable_ev64120_irq,
111 .enable = enable_ev64120_irq, 94 .mask_ack = disable_ev64120_irq,
112 .disable = disable_ev64120_irq, 95 .unmask = enable_ev64120_irq,
113 .ack = mask_and_ack_ev64120_irq,
114 .end = end_ev64120_irq, 96 .end = end_ev64120_irq,
115 .set_affinity = NULL
116}; 97};
117 98
118void gt64120_irq_setup(void) 99void gt64120_irq_setup(void)
@@ -122,8 +103,6 @@ void gt64120_irq_setup(void)
122 */ 103 */
123 clear_c0_status(ST0_IM); 104 clear_c0_status(ST0_IM);
124 105
125 local_irq_disable();
126
127 /* 106 /*
128 * Enable timer. Other interrupts will be enabled as they are 107 * Enable timer. Other interrupts will be enabled as they are
129 * registered. 108 * registered.
@@ -133,16 +112,5 @@ void gt64120_irq_setup(void)
133 112
134void __init arch_init_irq(void) 113void __init arch_init_irq(void)
135{ 114{
136 int i;
137
138 /* Let's initialize our IRQ descriptors */
139 for (i = 0; i < NR_IRQS; i++) {
140 irq_desc[i].status = 0;
141 irq_desc[i].chip = &no_irq_chip;
142 irq_desc[i].action = NULL;
143 irq_desc[i].depth = 0;
144 spin_lock_init(&irq_desc[i].lock);
145 }
146
147 gt64120_irq_setup(); 115 gt64120_irq_setup();
148} 116}
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index d5bd6b3a0933..5c4f50cdf157 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -28,14 +28,6 @@ static void enable_r4030_irq(unsigned int irq)
28 spin_unlock_irqrestore(&r4030_lock, flags); 28 spin_unlock_irqrestore(&r4030_lock, flags);
29} 29}
30 30
31static unsigned int startup_r4030_irq(unsigned int irq)
32{
33 enable_r4030_irq(irq);
34 return 0; /* never anything pending */
35}
36
37#define shutdown_r4030_irq disable_r4030_irq
38
39void disable_r4030_irq(unsigned int irq) 31void disable_r4030_irq(unsigned int irq)
40{ 32{
41 unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ)); 33 unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ));
@@ -47,8 +39,6 @@ void disable_r4030_irq(unsigned int irq)
47 spin_unlock_irqrestore(&r4030_lock, flags); 39 spin_unlock_irqrestore(&r4030_lock, flags);
48} 40}
49 41
50#define mask_and_ack_r4030_irq disable_r4030_irq
51
52static void end_r4030_irq(unsigned int irq) 42static void end_r4030_irq(unsigned int irq)
53{ 43{
54 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 44 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -57,11 +47,10 @@ static void end_r4030_irq(unsigned int irq)
57 47
58static struct irq_chip r4030_irq_type = { 48static struct irq_chip r4030_irq_type = {
59 .typename = "R4030", 49 .typename = "R4030",
60 .startup = startup_r4030_irq, 50 .ack = disable_r4030_irq,
61 .shutdown = shutdown_r4030_irq, 51 .mask = disable_r4030_irq,
62 .enable = enable_r4030_irq, 52 .mask_ack = disable_r4030_irq,
63 .disable = disable_r4030_irq, 53 .unmask = enable_r4030_irq,
64 .ack = mask_and_ack_r4030_irq,
65 .end = end_r4030_irq, 54 .end = end_r4030_irq,
66}; 55};
67 56
@@ -69,12 +58,8 @@ void __init init_r4030_ints(void)
69{ 58{
70 int i; 59 int i;
71 60
72 for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) { 61 for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++)
73 irq_desc[i].status = IRQ_DISABLED; 62 set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
74 irq_desc[i].action = 0;
75 irq_desc[i].depth = 1;
76 irq_desc[i].chip = &r4030_irq_type;
77 }
78 63
79 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); 64 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
80 r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */ 65 r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index de4a238c28be..3da49c5aaf49 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -90,17 +90,6 @@ static unsigned char irc_level[TX3927_NUM_IR] = {
90static void jmr3927_irq_disable(unsigned int irq_nr); 90static void jmr3927_irq_disable(unsigned int irq_nr);
91static void jmr3927_irq_enable(unsigned int irq_nr); 91static void jmr3927_irq_enable(unsigned int irq_nr);
92 92
93static DEFINE_SPINLOCK(jmr3927_irq_lock);
94
95static unsigned int jmr3927_irq_startup(unsigned int irq)
96{
97 jmr3927_irq_enable(irq);
98
99 return 0;
100}
101
102#define jmr3927_irq_shutdown jmr3927_irq_disable
103
104static void jmr3927_irq_ack(unsigned int irq) 93static void jmr3927_irq_ack(unsigned int irq)
105{ 94{
106 if (irq == JMR3927_IRQ_IRC_TMR0) 95 if (irq == JMR3927_IRQ_IRC_TMR0)
@@ -118,9 +107,7 @@ static void jmr3927_irq_end(unsigned int irq)
118static void jmr3927_irq_disable(unsigned int irq_nr) 107static void jmr3927_irq_disable(unsigned int irq_nr)
119{ 108{
120 struct tb_irq_space* sp; 109 struct tb_irq_space* sp;
121 unsigned long flags;
122 110
123 spin_lock_irqsave(&jmr3927_irq_lock, flags);
124 for (sp = tb_irq_spaces; sp; sp = sp->next) { 111 for (sp = tb_irq_spaces; sp; sp = sp->next) {
125 if (sp->start_irqno <= irq_nr && 112 if (sp->start_irqno <= irq_nr &&
126 irq_nr < sp->start_irqno + sp->nr_irqs) { 113 irq_nr < sp->start_irqno + sp->nr_irqs) {
@@ -130,15 +117,12 @@ static void jmr3927_irq_disable(unsigned int irq_nr)
130 break; 117 break;
131 } 118 }
132 } 119 }
133 spin_unlock_irqrestore(&jmr3927_irq_lock, flags);
134} 120}
135 121
136static void jmr3927_irq_enable(unsigned int irq_nr) 122static void jmr3927_irq_enable(unsigned int irq_nr)
137{ 123{
138 struct tb_irq_space* sp; 124 struct tb_irq_space* sp;
139 unsigned long flags;
140 125
141 spin_lock_irqsave(&jmr3927_irq_lock, flags);
142 for (sp = tb_irq_spaces; sp; sp = sp->next) { 126 for (sp = tb_irq_spaces; sp; sp = sp->next) {
143 if (sp->start_irqno <= irq_nr && 127 if (sp->start_irqno <= irq_nr &&
144 irq_nr < sp->start_irqno + sp->nr_irqs) { 128 irq_nr < sp->start_irqno + sp->nr_irqs) {
@@ -148,7 +132,6 @@ static void jmr3927_irq_enable(unsigned int irq_nr)
148 break; 132 break;
149 } 133 }
150 } 134 }
151 spin_unlock_irqrestore(&jmr3927_irq_lock, flags);
152} 135}
153 136
154/* 137/*
@@ -457,11 +440,10 @@ void __init arch_init_irq(void)
457 440
458static struct irq_chip jmr3927_irq_controller = { 441static struct irq_chip jmr3927_irq_controller = {
459 .typename = "jmr3927_irq", 442 .typename = "jmr3927_irq",
460 .startup = jmr3927_irq_startup,
461 .shutdown = jmr3927_irq_shutdown,
462 .enable = jmr3927_irq_enable,
463 .disable = jmr3927_irq_disable,
464 .ack = jmr3927_irq_ack, 443 .ack = jmr3927_irq_ack,
444 .mask = jmr3927_irq_disable,
445 .mask_ack = jmr3927_irq_ack,
446 .unmask = jmr3927_irq_enable,
465 .end = jmr3927_irq_end, 447 .end = jmr3927_irq_end,
466}; 448};
467 449
@@ -469,12 +451,8 @@ void jmr3927_irq_init(u32 irq_base)
469{ 451{
470 u32 i; 452 u32 i;
471 453
472 for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) { 454 for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++)
473 irq_desc[i].status = IRQ_DISABLED; 455 set_irq_chip(i, &jmr3927_irq_controller);
474 irq_desc[i].action = NULL;
475 irq_desc[i].depth = 1;
476 irq_desc[i].chip = &jmr3927_irq_controller;
477 }
478 456
479 jmr3927_irq_base = irq_base; 457 jmr3927_irq_base = irq_base;
480} 458}
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index 16e5dfe7aa8a..138f25efe38a 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -170,7 +170,7 @@ static void jmr3927_machine_power_off(void)
170 while (1); 170 while (1);
171} 171}
172 172
173static unsigned int jmr3927_hpt_read(void) 173static cycle_t jmr3927_hpt_read(void)
174{ 174{
175 /* We assume this function is called xtime_lock held. */ 175 /* We assume this function is called xtime_lock held. */
176 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr; 176 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
@@ -182,7 +182,7 @@ extern void rtc_ds1742_init(unsigned long base);
182#endif 182#endif
183static void __init jmr3927_time_init(void) 183static void __init jmr3927_time_init(void)
184{ 184{
185 mips_hpt_read = jmr3927_hpt_read; 185 clocksource_mips.read = jmr3927_hpt_read;
186 mips_hpt_frequency = JMR3927_TIMER_CLK; 186 mips_hpt_frequency = JMR3927_TIMER_CLK;
187#ifdef USE_RTC_DS1742 187#ifdef USE_RTC_DS1742
188 if (jmr3927_have_nvram()) { 188 if (jmr3927_have_nvram()) {
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 6bfbbed0897e..bbbb8d7cb89b 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -45,7 +45,6 @@ obj-$(CONFIG_MIPS_APSP_KSPD) += kspd.o
45obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o 45obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
46obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o 46obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
47 47
48obj-$(CONFIG_NO_ISA) += dma-no-isa.o
49obj-$(CONFIG_I8259) += i8259.o 48obj-$(CONFIG_I8259) += i8259.o
50obj-$(CONFIG_IRQ_CPU) += irq_cpu.o 49obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
51obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o 50obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
@@ -67,6 +66,8 @@ obj-$(CONFIG_64BIT) += cpu-bugs64.o
67 66
68obj-$(CONFIG_I8253) += i8253.o 67obj-$(CONFIG_I8253) += i8253.o
69 68
69obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
70
70CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) 71CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
71 72
72EXTRA_AFLAGS := $(CFLAGS) 73EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 8485af340ee1..442839e9578c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -110,9 +110,8 @@ static inline void check_wait(void)
110{ 110{
111 struct cpuinfo_mips *c = &current_cpu_data; 111 struct cpuinfo_mips *c = &current_cpu_data;
112 112
113 printk("Checking for 'wait' instruction... ");
114 if (nowait) { 113 if (nowait) {
115 printk (" disabled.\n"); 114 printk("Wait instruction disabled.\n");
116 return; 115 return;
117 } 116 }
118 117
@@ -120,11 +119,9 @@ static inline void check_wait(void)
120 case CPU_R3081: 119 case CPU_R3081:
121 case CPU_R3081E: 120 case CPU_R3081E:
122 cpu_wait = r3081_wait; 121 cpu_wait = r3081_wait;
123 printk(" available.\n");
124 break; 122 break;
125 case CPU_TX3927: 123 case CPU_TX3927:
126 cpu_wait = r39xx_wait; 124 cpu_wait = r39xx_wait;
127 printk(" available.\n");
128 break; 125 break;
129 case CPU_R4200: 126 case CPU_R4200:
130/* case CPU_R4300: */ 127/* case CPU_R4300: */
@@ -146,33 +143,23 @@ static inline void check_wait(void)
146 case CPU_74K: 143 case CPU_74K:
147 case CPU_PR4450: 144 case CPU_PR4450:
148 cpu_wait = r4k_wait; 145 cpu_wait = r4k_wait;
149 printk(" available.\n");
150 break; 146 break;
151 case CPU_TX49XX: 147 case CPU_TX49XX:
152 cpu_wait = r4k_wait_irqoff; 148 cpu_wait = r4k_wait_irqoff;
153 printk(" available.\n");
154 break; 149 break;
155 case CPU_AU1000: 150 case CPU_AU1000:
156 case CPU_AU1100: 151 case CPU_AU1100:
157 case CPU_AU1500: 152 case CPU_AU1500:
158 case CPU_AU1550: 153 case CPU_AU1550:
159 case CPU_AU1200: 154 case CPU_AU1200:
160 if (allow_au1k_wait) { 155 if (allow_au1k_wait)
161 cpu_wait = au1k_wait; 156 cpu_wait = au1k_wait;
162 printk(" available.\n");
163 } else
164 printk(" unavailable.\n");
165 break; 157 break;
166 case CPU_RM9000: 158 case CPU_RM9000:
167 if ((c->processor_id & 0x00ff) >= 0x40) { 159 if ((c->processor_id & 0x00ff) >= 0x40)
168 cpu_wait = r4k_wait; 160 cpu_wait = r4k_wait;
169 printk(" available.\n");
170 } else {
171 printk(" unavailable.\n");
172 }
173 break; 161 break;
174 default: 162 default:
175 printk(" unavailable.\n");
176 break; 163 break;
177 } 164 }
178} 165}
diff --git a/arch/mips/kernel/dma-no-isa.c b/arch/mips/kernel/dma-no-isa.c
deleted file mode 100644
index 6df8b07741e3..000000000000
--- a/arch/mips/kernel/dma-no-isa.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 by Ralf Baechle
7 *
8 * Dummy ISA DMA functions for systems that don't have ISA but share drivers
9 * with ISA such as legacy free PCI.
10 */
11#include <linux/errno.h>
12#include <linux/module.h>
13#include <linux/spinlock.h>
14
15DEFINE_SPINLOCK(dma_spin_lock);
16
17int request_dma(unsigned int dmanr, const char * device_id)
18{
19 return -EINVAL;
20}
21
22void free_dma(unsigned int dmanr)
23{
24}
25
26EXPORT_SYMBOL(dma_spin_lock);
27EXPORT_SYMBOL(request_dma);
28EXPORT_SYMBOL(free_dma);
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 5baca16993d0..aacd4a005c5f 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -19,6 +19,7 @@
19#include <asm/mipsregs.h> 19#include <asm/mipsregs.h>
20#include <asm/stackframe.h> 20#include <asm/stackframe.h>
21#include <asm/war.h> 21#include <asm/war.h>
22#include <asm/page.h>
22 23
23#define PANIC_PIC(msg) \ 24#define PANIC_PIC(msg) \
24 .set push; \ 25 .set push; \
@@ -378,6 +379,68 @@ NESTED(nmi_handler, PT_SIZE, sp)
378 BUILD_HANDLER dsp dsp sti silent /* #26 */ 379 BUILD_HANDLER dsp dsp sti silent /* #26 */
379 BUILD_HANDLER reserved reserved sti verbose /* others */ 380 BUILD_HANDLER reserved reserved sti verbose /* others */
380 381
382 .align 5
383 LEAF(handle_ri_rdhwr_vivt)
384#ifdef CONFIG_MIPS_MT_SMTC
385 PANIC_PIC("handle_ri_rdhwr_vivt called")
386#else
387 .set push
388 .set noat
389 .set noreorder
390 /* check if TLB contains a entry for EPC */
391 MFC0 k1, CP0_ENTRYHI
392 andi k1, 0xff /* ASID_MASK */
393 MFC0 k0, CP0_EPC
394 PTR_SRL k0, PAGE_SHIFT + 1
395 PTR_SLL k0, PAGE_SHIFT + 1
396 or k1, k0
397 MTC0 k1, CP0_ENTRYHI
398 mtc0_tlbw_hazard
399 tlbp
400 tlb_probe_hazard
401 mfc0 k1, CP0_INDEX
402 .set pop
403 bltz k1, handle_ri /* slow path */
404 /* fall thru */
405#endif
406 END(handle_ri_rdhwr_vivt)
407
408 LEAF(handle_ri_rdhwr)
409 .set push
410 .set noat
411 .set noreorder
412 /* 0x7c03e83b: rdhwr v1,$29 */
413 MFC0 k1, CP0_EPC
414 lui k0, 0x7c03
415 lw k1, (k1)
416 ori k0, 0xe83b
417 .set reorder
418 bne k0, k1, handle_ri /* if not ours */
419 /* The insn is rdhwr. No need to check CAUSE.BD here. */
420 get_saved_sp /* k1 := current_thread_info */
421 .set noreorder
422 MFC0 k0, CP0_EPC
423#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
424 ori k1, _THREAD_MASK
425 xori k1, _THREAD_MASK
426 LONG_L v1, TI_TP_VALUE(k1)
427 LONG_ADDIU k0, 4
428 jr k0
429 rfe
430#else
431 LONG_ADDIU k0, 4 /* stall on $k0 */
432 MTC0 k0, CP0_EPC
433 /* I hope three instructions between MTC0 and ERET are enough... */
434 ori k1, _THREAD_MASK
435 xori k1, _THREAD_MASK
436 LONG_L v1, TI_TP_VALUE(k1)
437 .set mips3
438 eret
439 .set mips0
440#endif
441 .set pop
442 END(handle_ri_rdhwr)
443
381#ifdef CONFIG_64BIT 444#ifdef CONFIG_64BIT
382/* A temporary overflow handler used by check_daddi(). */ 445/* A temporary overflow handler used by check_daddi(). */
383 446
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index ddc1b71c9378..a2e095adaa3f 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -250,6 +250,9 @@ NESTED(smp_bootstrap, 16, sp)
250 */ 250 */
251 page swapper_pg_dir, _PGD_ORDER 251 page swapper_pg_dir, _PGD_ORDER
252#ifdef CONFIG_64BIT 252#ifdef CONFIG_64BIT
253#if defined(CONFIG_MODULES) && !defined(CONFIG_BUILD_ELF64)
254 page module_pg_dir, _PGD_ORDER
255#endif
253 page invalid_pmd_table, _PMD_ORDER 256 page invalid_pmd_table, _PMD_ORDER
254#endif 257#endif
255 page invalid_pte_table, _PTE_ORDER 258 page invalid_pte_table, _PTE_ORDER
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 48e3418c217b..2526c0ca4d81 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -40,21 +40,10 @@ static void end_8259A_irq (unsigned int irq)
40 enable_8259A_irq(irq); 40 enable_8259A_irq(irq);
41} 41}
42 42
43#define shutdown_8259A_irq disable_8259A_irq
44
45void mask_and_ack_8259A(unsigned int); 43void mask_and_ack_8259A(unsigned int);
46 44
47static unsigned int startup_8259A_irq(unsigned int irq)
48{
49 enable_8259A_irq(irq);
50
51 return 0; /* never anything pending */
52}
53
54static struct irq_chip i8259A_irq_type = { 45static struct irq_chip i8259A_irq_type = {
55 .typename = "XT-PIC", 46 .typename = "XT-PIC",
56 .startup = startup_8259A_irq,
57 .shutdown = shutdown_8259A_irq,
58 .enable = enable_8259A_irq, 47 .enable = enable_8259A_irq,
59 .disable = disable_8259A_irq, 48 .disable = disable_8259A_irq,
60 .ack = mask_and_ack_8259A, 49 .ack = mask_and_ack_8259A,
@@ -120,7 +109,7 @@ int i8259A_irq_pending(unsigned int irq)
120void make_8259A_irq(unsigned int irq) 109void make_8259A_irq(unsigned int irq)
121{ 110{
122 disable_irq_nosync(irq); 111 disable_irq_nosync(irq);
123 irq_desc[irq].chip = &i8259A_irq_type; 112 set_irq_chip(irq, &i8259A_irq_type);
124 enable_irq(irq); 113 enable_irq(irq);
125} 114}
126 115
@@ -323,12 +312,8 @@ void __init init_i8259_irqs (void)
323 312
324 init_8259A(0); 313 init_8259A(0);
325 314
326 for (i = 0; i < 16; i++) { 315 for (i = 0; i < 16; i++)
327 irq_desc[i].status = IRQ_DISABLED; 316 set_irq_chip(i, &i8259A_irq_type);
328 irq_desc[i].action = NULL;
329 irq_desc[i].depth = 1;
330 irq_desc[i].chip = &i8259A_irq_type;
331 }
332 317
333 setup_irq(2, &irq2); 318 setup_irq(2, &irq2);
334} 319}
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 650a80ca3741..bcaad6696082 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -45,31 +45,6 @@ static inline void unmask_msc_irq(unsigned int irq)
45} 45}
46 46
47/* 47/*
48 * Enables the IRQ on SOC-it
49 */
50static void enable_msc_irq(unsigned int irq)
51{
52 unmask_msc_irq(irq);
53}
54
55/*
56 * Initialize the IRQ on SOC-it
57 */
58static unsigned int startup_msc_irq(unsigned int irq)
59{
60 unmask_msc_irq(irq);
61 return 0;
62}
63
64/*
65 * Disables the IRQ on SOC-it
66 */
67static void disable_msc_irq(unsigned int irq)
68{
69 mask_msc_irq(irq);
70}
71
72/*
73 * Masks and ACKs an IRQ 48 * Masks and ACKs an IRQ
74 */ 49 */
75static void level_mask_and_ack_msc_irq(unsigned int irq) 50static void level_mask_and_ack_msc_irq(unsigned int irq)
@@ -136,25 +111,23 @@ msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
136 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); 111 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
137} 112}
138 113
139#define shutdown_msc_irq disable_msc_irq
140
141struct irq_chip msc_levelirq_type = { 114struct irq_chip msc_levelirq_type = {
142 .typename = "SOC-it-Level", 115 .typename = "SOC-it-Level",
143 .startup = startup_msc_irq,
144 .shutdown = shutdown_msc_irq,
145 .enable = enable_msc_irq,
146 .disable = disable_msc_irq,
147 .ack = level_mask_and_ack_msc_irq, 116 .ack = level_mask_and_ack_msc_irq,
117 .mask = mask_msc_irq,
118 .mask_ack = level_mask_and_ack_msc_irq,
119 .unmask = unmask_msc_irq,
120 .eoi = unmask_msc_irq,
148 .end = end_msc_irq, 121 .end = end_msc_irq,
149}; 122};
150 123
151struct irq_chip msc_edgeirq_type = { 124struct irq_chip msc_edgeirq_type = {
152 .typename = "SOC-it-Edge", 125 .typename = "SOC-it-Edge",
153 .startup =startup_msc_irq,
154 .shutdown = shutdown_msc_irq,
155 .enable = enable_msc_irq,
156 .disable = disable_msc_irq,
157 .ack = edge_mask_and_ack_msc_irq, 126 .ack = edge_mask_and_ack_msc_irq,
127 .mask = mask_msc_irq,
128 .mask_ack = edge_mask_and_ack_msc_irq,
129 .unmask = unmask_msc_irq,
130 .eoi = unmask_msc_irq,
158 .end = end_msc_irq, 131 .end = end_msc_irq,
159}; 132};
160 133
@@ -175,14 +148,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
175 148
176 switch (imp->im_type) { 149 switch (imp->im_type) {
177 case MSC01_IRQ_EDGE: 150 case MSC01_IRQ_EDGE:
178 irq_desc[base+n].chip = &msc_edgeirq_type; 151 set_irq_chip(base+n, &msc_edgeirq_type);
179 if (cpu_has_veic) 152 if (cpu_has_veic)
180 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 153 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
181 else 154 else
182 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 155 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
183 break; 156 break;
184 case MSC01_IRQ_LEVEL: 157 case MSC01_IRQ_LEVEL:
185 irq_desc[base+n].chip = &msc_levelirq_type; 158 set_irq_chip(base+n, &msc_levelirq_type);
186 if (cpu_has_veic) 159 if (cpu_has_veic)
187 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 160 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
188 else 161 else
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
index 37d106202b83..6cfb31cafde2 100644
--- a/arch/mips/kernel/irq-mv6434x.c
+++ b/arch/mips/kernel/irq-mv6434x.c
@@ -67,39 +67,6 @@ static inline void unmask_mv64340_irq(unsigned int irq)
67} 67}
68 68
69/* 69/*
70 * Enables the IRQ on Marvell Chip
71 */
72static void enable_mv64340_irq(unsigned int irq)
73{
74 unmask_mv64340_irq(irq);
75}
76
77/*
78 * Initialize the IRQ on Marvell Chip
79 */
80static unsigned int startup_mv64340_irq(unsigned int irq)
81{
82 unmask_mv64340_irq(irq);
83 return 0;
84}
85
86/*
87 * Disables the IRQ on Marvell Chip
88 */
89static void disable_mv64340_irq(unsigned int irq)
90{
91 mask_mv64340_irq(irq);
92}
93
94/*
95 * Masks and ACKs an IRQ
96 */
97static void mask_and_ack_mv64340_irq(unsigned int irq)
98{
99 mask_mv64340_irq(irq);
100}
101
102/*
103 * End IRQ processing 70 * End IRQ processing
104 */ 71 */
105static void end_mv64340_irq(unsigned int irq) 72static void end_mv64340_irq(unsigned int irq)
@@ -133,15 +100,12 @@ void ll_mv64340_irq(void)
133 do_IRQ(ls1bit32(irq_src_high) + irq_base + 32); 100 do_IRQ(ls1bit32(irq_src_high) + irq_base + 32);
134} 101}
135 102
136#define shutdown_mv64340_irq disable_mv64340_irq
137
138struct irq_chip mv64340_irq_type = { 103struct irq_chip mv64340_irq_type = {
139 .typename = "MV-64340", 104 .typename = "MV-64340",
140 .startup = startup_mv64340_irq, 105 .ack = mask_mv64340_irq,
141 .shutdown = shutdown_mv64340_irq, 106 .mask = mask_mv64340_irq,
142 .enable = enable_mv64340_irq, 107 .mask_ack = mask_mv64340_irq,
143 .disable = disable_mv64340_irq, 108 .unmask = unmask_mv64340_irq,
144 .ack = mask_and_ack_mv64340_irq,
145 .end = end_mv64340_irq, 109 .end = end_mv64340_irq,
146}; 110};
147 111
@@ -149,13 +113,9 @@ void __init mv64340_irq_init(unsigned int base)
149{ 113{
150 int i; 114 int i;
151 115
152 /* Reset irq handlers pointers to NULL */ 116 for (i = base; i < base + 64; i++)
153 for (i = base; i < base + 64; i++) { 117 set_irq_chip_and_handler(i, &mv64340_irq_type,
154 irq_desc[i].status = IRQ_DISABLED; 118 handle_level_irq);
155 irq_desc[i].action = 0;
156 irq_desc[i].depth = 2;
157 irq_desc[i].chip = &mv64340_irq_type;
158 }
159 119
160 irq_base = base; 120 irq_base = base;
161} 121}
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index 6b54c7109e2e..ddcc2a5f8a06 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -29,42 +29,6 @@ static inline void mask_rm7k_irq(unsigned int irq)
29 clear_c0_intcontrol(0x100 << (irq - irq_base)); 29 clear_c0_intcontrol(0x100 << (irq - irq_base));
30} 30}
31 31
32static inline void rm7k_cpu_irq_enable(unsigned int irq)
33{
34 unsigned long flags;
35
36 local_irq_save(flags);
37 unmask_rm7k_irq(irq);
38 local_irq_restore(flags);
39}
40
41static void rm7k_cpu_irq_disable(unsigned int irq)
42{
43 unsigned long flags;
44
45 local_irq_save(flags);
46 mask_rm7k_irq(irq);
47 local_irq_restore(flags);
48}
49
50static unsigned int rm7k_cpu_irq_startup(unsigned int irq)
51{
52 rm7k_cpu_irq_enable(irq);
53
54 return 0;
55}
56
57#define rm7k_cpu_irq_shutdown rm7k_cpu_irq_disable
58
59/*
60 * While we ack the interrupt interrupts are disabled and thus we don't need
61 * to deal with concurrency issues. Same for rm7k_cpu_irq_end.
62 */
63static void rm7k_cpu_irq_ack(unsigned int irq)
64{
65 mask_rm7k_irq(irq);
66}
67
68static void rm7k_cpu_irq_end(unsigned int irq) 32static void rm7k_cpu_irq_end(unsigned int irq)
69{ 33{
70 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 34 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -73,11 +37,10 @@ static void rm7k_cpu_irq_end(unsigned int irq)
73 37
74static struct irq_chip rm7k_irq_controller = { 38static struct irq_chip rm7k_irq_controller = {
75 .typename = "RM7000", 39 .typename = "RM7000",
76 .startup = rm7k_cpu_irq_startup, 40 .ack = mask_rm7k_irq,
77 .shutdown = rm7k_cpu_irq_shutdown, 41 .mask = mask_rm7k_irq,
78 .enable = rm7k_cpu_irq_enable, 42 .mask_ack = mask_rm7k_irq,
79 .disable = rm7k_cpu_irq_disable, 43 .unmask = unmask_rm7k_irq,
80 .ack = rm7k_cpu_irq_ack,
81 .end = rm7k_cpu_irq_end, 44 .end = rm7k_cpu_irq_end,
82}; 45};
83 46
@@ -87,12 +50,9 @@ void __init rm7k_cpu_irq_init(int base)
87 50
88 clear_c0_intcontrol(0x00000f00); /* Mask all */ 51 clear_c0_intcontrol(0x00000f00); /* Mask all */
89 52
90 for (i = base; i < base + 4; i++) { 53 for (i = base; i < base + 4; i++)
91 irq_desc[i].status = IRQ_DISABLED; 54 set_irq_chip_and_handler(i, &rm7k_irq_controller,
92 irq_desc[i].action = NULL; 55 handle_level_irq);
93 irq_desc[i].depth = 1;
94 irq_desc[i].chip = &rm7k_irq_controller;
95 }
96 56
97 irq_base = base; 57 irq_base = base;
98} 58}
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index 62f011ba97a2..ba6440c88abd 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -48,15 +48,6 @@ static void rm9k_cpu_irq_disable(unsigned int irq)
48 local_irq_restore(flags); 48 local_irq_restore(flags);
49} 49}
50 50
51static unsigned int rm9k_cpu_irq_startup(unsigned int irq)
52{
53 rm9k_cpu_irq_enable(irq);
54
55 return 0;
56}
57
58#define rm9k_cpu_irq_shutdown rm9k_cpu_irq_disable
59
60/* 51/*
61 * Performance counter interrupts are global on all processors. 52 * Performance counter interrupts are global on all processors.
62 */ 53 */
@@ -89,16 +80,6 @@ static void rm9k_perfcounter_irq_shutdown(unsigned int irq)
89 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1); 80 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1);
90} 81}
91 82
92
93/*
94 * While we ack the interrupt interrupts are disabled and thus we don't need
95 * to deal with concurrency issues. Same for rm9k_cpu_irq_end.
96 */
97static void rm9k_cpu_irq_ack(unsigned int irq)
98{
99 mask_rm9k_irq(irq);
100}
101
102static void rm9k_cpu_irq_end(unsigned int irq) 83static void rm9k_cpu_irq_end(unsigned int irq)
103{ 84{
104 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 85 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -107,11 +88,10 @@ static void rm9k_cpu_irq_end(unsigned int irq)
107 88
108static struct irq_chip rm9k_irq_controller = { 89static struct irq_chip rm9k_irq_controller = {
109 .typename = "RM9000", 90 .typename = "RM9000",
110 .startup = rm9k_cpu_irq_startup, 91 .ack = mask_rm9k_irq,
111 .shutdown = rm9k_cpu_irq_shutdown, 92 .mask = mask_rm9k_irq,
112 .enable = rm9k_cpu_irq_enable, 93 .mask_ack = mask_rm9k_irq,
113 .disable = rm9k_cpu_irq_disable, 94 .unmask = unmask_rm9k_irq,
114 .ack = rm9k_cpu_irq_ack,
115 .end = rm9k_cpu_irq_end, 95 .end = rm9k_cpu_irq_end,
116}; 96};
117 97
@@ -119,9 +99,10 @@ static struct irq_chip rm9k_perfcounter_irq = {
119 .typename = "RM9000", 99 .typename = "RM9000",
120 .startup = rm9k_perfcounter_irq_startup, 100 .startup = rm9k_perfcounter_irq_startup,
121 .shutdown = rm9k_perfcounter_irq_shutdown, 101 .shutdown = rm9k_perfcounter_irq_shutdown,
122 .enable = rm9k_cpu_irq_enable, 102 .ack = mask_rm9k_irq,
123 .disable = rm9k_cpu_irq_disable, 103 .mask = mask_rm9k_irq,
124 .ack = rm9k_cpu_irq_ack, 104 .mask_ack = mask_rm9k_irq,
105 .unmask = unmask_rm9k_irq,
125 .end = rm9k_cpu_irq_end, 106 .end = rm9k_cpu_irq_end,
126}; 107};
127 108
@@ -135,15 +116,13 @@ void __init rm9k_cpu_irq_init(int base)
135 116
136 clear_c0_intcontrol(0x0000f000); /* Mask all */ 117 clear_c0_intcontrol(0x0000f000); /* Mask all */
137 118
138 for (i = base; i < base + 4; i++) { 119 for (i = base; i < base + 4; i++)
139 irq_desc[i].status = IRQ_DISABLED; 120 set_irq_chip_and_handler(i, &rm9k_irq_controller,
140 irq_desc[i].action = NULL; 121 handle_level_irq);
141 irq_desc[i].depth = 1;
142 irq_desc[i].chip = &rm9k_irq_controller;
143 }
144 122
145 rm9000_perfcount_irq = base + 1; 123 rm9000_perfcount_irq = base + 1;
146 irq_desc[rm9000_perfcount_irq].chip = &rm9k_perfcounter_irq; 124 set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
125 handle_level_irq);
147 126
148 irq_base = base; 127 irq_base = base;
149} 128}
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 9b0e49d63d7b..b339798b3172 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -88,25 +88,6 @@ atomic_t irq_err_count;
88unsigned long irq_hwmask[NR_IRQS]; 88unsigned long irq_hwmask[NR_IRQS];
89#endif /* CONFIG_MIPS_MT_SMTC */ 89#endif /* CONFIG_MIPS_MT_SMTC */
90 90
91#undef do_IRQ
92
93/*
94 * do_IRQ handles all normal device IRQ's (the special
95 * SMP cross-CPU interrupts have their own specific
96 * handlers).
97 */
98asmlinkage unsigned int do_IRQ(unsigned int irq)
99{
100 irq_enter();
101
102 __DO_IRQ_SMTC_HOOK();
103 __do_IRQ(irq);
104
105 irq_exit();
106
107 return 1;
108}
109
110/* 91/*
111 * Generic, controller-independent functions: 92 * Generic, controller-independent functions:
112 */ 93 */
@@ -172,19 +153,6 @@ __setup("nokgdb", nokgdb);
172 153
173void __init init_IRQ(void) 154void __init init_IRQ(void)
174{ 155{
175 int i;
176
177 for (i = 0; i < NR_IRQS; i++) {
178 irq_desc[i].status = IRQ_DISABLED;
179 irq_desc[i].action = NULL;
180 irq_desc[i].depth = 1;
181 irq_desc[i].chip = &no_irq_chip;
182 spin_lock_init(&irq_desc[i].lock);
183#ifdef CONFIG_MIPS_MT_SMTC
184 irq_hwmask[i] = 0;
185#endif /* CONFIG_MIPS_MT_SMTC */
186 }
187
188 arch_init_irq(); 156 arch_init_irq();
189 157
190#ifdef CONFIG_KGDB 158#ifdef CONFIG_KGDB
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 9bb21c7f2149..be5ac23d3812 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -50,44 +50,6 @@ static inline void mask_mips_irq(unsigned int irq)
50 irq_disable_hazard(); 50 irq_disable_hazard();
51} 51}
52 52
53static inline void mips_cpu_irq_enable(unsigned int irq)
54{
55 unsigned long flags;
56
57 local_irq_save(flags);
58 unmask_mips_irq(irq);
59 back_to_back_c0_hazard();
60 local_irq_restore(flags);
61}
62
63static void mips_cpu_irq_disable(unsigned int irq)
64{
65 unsigned long flags;
66
67 local_irq_save(flags);
68 mask_mips_irq(irq);
69 back_to_back_c0_hazard();
70 local_irq_restore(flags);
71}
72
73static unsigned int mips_cpu_irq_startup(unsigned int irq)
74{
75 mips_cpu_irq_enable(irq);
76
77 return 0;
78}
79
80#define mips_cpu_irq_shutdown mips_cpu_irq_disable
81
82/*
83 * While we ack the interrupt interrupts are disabled and thus we don't need
84 * to deal with concurrency issues. Same for mips_cpu_irq_end.
85 */
86static void mips_cpu_irq_ack(unsigned int irq)
87{
88 mask_mips_irq(irq);
89}
90
91static void mips_cpu_irq_end(unsigned int irq) 53static void mips_cpu_irq_end(unsigned int irq)
92{ 54{
93 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 55 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -96,11 +58,11 @@ static void mips_cpu_irq_end(unsigned int irq)
96 58
97static struct irq_chip mips_cpu_irq_controller = { 59static struct irq_chip mips_cpu_irq_controller = {
98 .typename = "MIPS", 60 .typename = "MIPS",
99 .startup = mips_cpu_irq_startup, 61 .ack = mask_mips_irq,
100 .shutdown = mips_cpu_irq_shutdown, 62 .mask = mask_mips_irq,
101 .enable = mips_cpu_irq_enable, 63 .mask_ack = mask_mips_irq,
102 .disable = mips_cpu_irq_disable, 64 .unmask = unmask_mips_irq,
103 .ack = mips_cpu_irq_ack, 65 .eoi = unmask_mips_irq,
104 .end = mips_cpu_irq_end, 66 .end = mips_cpu_irq_end,
105}; 67};
106 68
@@ -110,8 +72,6 @@ static struct irq_chip mips_cpu_irq_controller = {
110 72
111#define unmask_mips_mt_irq unmask_mips_irq 73#define unmask_mips_mt_irq unmask_mips_irq
112#define mask_mips_mt_irq mask_mips_irq 74#define mask_mips_mt_irq mask_mips_irq
113#define mips_mt_cpu_irq_enable mips_cpu_irq_enable
114#define mips_mt_cpu_irq_disable mips_cpu_irq_disable
115 75
116static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) 76static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
117{ 77{
@@ -119,13 +79,11 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
119 79
120 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); 80 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
121 evpe(vpflags); 81 evpe(vpflags);
122 mips_mt_cpu_irq_enable(irq); 82 unmask_mips_mt_irq(irq);
123 83
124 return 0; 84 return 0;
125} 85}
126 86
127#define mips_mt_cpu_irq_shutdown mips_mt_cpu_irq_disable
128
129/* 87/*
130 * While we ack the interrupt interrupts are disabled and thus we don't need 88 * While we ack the interrupt interrupts are disabled and thus we don't need
131 * to deal with concurrency issues. Same for mips_cpu_irq_end. 89 * to deal with concurrency issues. Same for mips_cpu_irq_end.
@@ -143,10 +101,11 @@ static void mips_mt_cpu_irq_ack(unsigned int irq)
143static struct irq_chip mips_mt_cpu_irq_controller = { 101static struct irq_chip mips_mt_cpu_irq_controller = {
144 .typename = "MIPS", 102 .typename = "MIPS",
145 .startup = mips_mt_cpu_irq_startup, 103 .startup = mips_mt_cpu_irq_startup,
146 .shutdown = mips_mt_cpu_irq_shutdown,
147 .enable = mips_mt_cpu_irq_enable,
148 .disable = mips_mt_cpu_irq_disable,
149 .ack = mips_mt_cpu_irq_ack, 104 .ack = mips_mt_cpu_irq_ack,
105 .mask = mask_mips_mt_irq,
106 .mask_ack = mips_mt_cpu_irq_ack,
107 .unmask = unmask_mips_mt_irq,
108 .eoi = unmask_mips_mt_irq,
150 .end = mips_mt_cpu_irq_end, 109 .end = mips_mt_cpu_irq_end,
151}; 110};
152 111
@@ -163,19 +122,12 @@ void __init mips_cpu_irq_init(int irq_base)
163 * leave them uninitialized for other processors. 122 * leave them uninitialized for other processors.
164 */ 123 */
165 if (cpu_has_mipsmt) 124 if (cpu_has_mipsmt)
166 for (i = irq_base; i < irq_base + 2; i++) { 125 for (i = irq_base; i < irq_base + 2; i++)
167 irq_desc[i].status = IRQ_DISABLED; 126 set_irq_chip(i, &mips_mt_cpu_irq_controller);
168 irq_desc[i].action = NULL; 127
169 irq_desc[i].depth = 1; 128 for (i = irq_base + 2; i < irq_base + 8; i++)
170 irq_desc[i].chip = &mips_mt_cpu_irq_controller; 129 set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
171 } 130 handle_level_irq);
172
173 for (i = irq_base + 2; i < irq_base + 8; i++) {
174 irq_desc[i].status = IRQ_DISABLED;
175 irq_desc[i].action = NULL;
176 irq_desc[i].depth = 1;
177 irq_desc[i].chip = &mips_cpu_irq_controller;
178 }
179 131
180 mips_cpu_irq_base = irq_base; 132 mips_cpu_irq_base = irq_base;
181} 133}
diff --git a/arch/mips/kernel/machine_kexec.c b/arch/mips/kernel/machine_kexec.c
new file mode 100644
index 000000000000..e0ad754c7edd
--- /dev/null
+++ b/arch/mips/kernel/machine_kexec.c
@@ -0,0 +1,85 @@
1/*
2 * machine_kexec.c for kexec
3 * Created by <nschichan@corp.free.fr> on Thu Oct 12 15:15:06 2006
4 *
5 * This source code is licensed under the GNU General Public License,
6 * Version 2. See the file COPYING for more details.
7 */
8
9#include <linux/kexec.h>
10#include <linux/mm.h>
11#include <linux/delay.h>
12
13#include <asm/cacheflush.h>
14#include <asm/page.h>
15
16const extern unsigned char relocate_new_kernel[];
17const extern unsigned int relocate_new_kernel_size;
18
19extern unsigned long kexec_start_address;
20extern unsigned long kexec_indirection_page;
21
22int
23machine_kexec_prepare(struct kimage *kimage)
24{
25 return 0;
26}
27
28void
29machine_kexec_cleanup(struct kimage *kimage)
30{
31}
32
33void
34machine_shutdown(void)
35{
36}
37
38void
39machine_crash_shutdown(struct pt_regs *regs)
40{
41}
42
43void
44machine_kexec(struct kimage *image)
45{
46 unsigned long reboot_code_buffer;
47 unsigned long entry;
48 unsigned long *ptr;
49
50 reboot_code_buffer =
51 (unsigned long)page_address(image->control_code_page);
52
53 kexec_start_address = image->start;
54 kexec_indirection_page = phys_to_virt(image->head & PAGE_MASK);
55
56 memcpy((void*)reboot_code_buffer, relocate_new_kernel,
57 relocate_new_kernel_size);
58
59 /*
60 * The generic kexec code builds a page list with physical
61 * addresses. they are directly accessible through KSEG0 (or
62 * CKSEG0 or XPHYS if on 64bit system), hence the
63 * pys_to_virt() call.
64 */
65 for (ptr = &image->head; (entry = *ptr) && !(entry &IND_DONE);
66 ptr = (entry & IND_INDIRECTION) ?
67 phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
68 if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION ||
69 *ptr & IND_DESTINATION)
70 *ptr = phys_to_virt(*ptr);
71 }
72
73 /*
74 * we do not want to be bothered.
75 */
76 local_irq_disable();
77
78 flush_icache_range(reboot_code_buffer,
79 reboot_code_buffer + KEXEC_CONTROL_CODE_SIZE);
80
81 printk("Will call new kernel at %08x\n", image->start);
82 printk("Bye ...\n");
83 flush_cache_all();
84 ((void (*)(void))reboot_code_buffer)();
85}
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index d7bf0215bc1d..cb0801437b66 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -29,6 +29,7 @@
29#include <linux/kernel.h> 29#include <linux/kernel.h>
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/spinlock.h> 31#include <linux/spinlock.h>
32#include <asm/pgtable.h> /* MODULE_START */
32 33
33struct mips_hi16 { 34struct mips_hi16 {
34 struct mips_hi16 *next; 35 struct mips_hi16 *next;
@@ -43,9 +44,23 @@ static DEFINE_SPINLOCK(dbe_lock);
43 44
44void *module_alloc(unsigned long size) 45void *module_alloc(unsigned long size)
45{ 46{
47#ifdef MODULE_START
48 struct vm_struct *area;
49
50 size = PAGE_ALIGN(size);
51 if (!size)
52 return NULL;
53
54 area = __get_vm_area(size, VM_ALLOC, MODULE_START, MODULE_END);
55 if (!area)
56 return NULL;
57
58 return __vmalloc_area(area, GFP_KERNEL, PAGE_KERNEL);
59#else
46 if (size == 0) 60 if (size == 0)
47 return NULL; 61 return NULL;
48 return vmalloc(size); 62 return vmalloc(size);
63#endif
49} 64}
50 65
51/* Free memory returned from module_alloc */ 66/* Free memory returned from module_alloc */
diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S
new file mode 100644
index 000000000000..a3f0d00c1334
--- /dev/null
+++ b/arch/mips/kernel/relocate_kernel.S
@@ -0,0 +1,80 @@
1/*
2 * relocate_kernel.S for kexec
3 * Created by <nschichan@corp.free.fr> on Thu Oct 12 17:49:57 2006
4 *
5 * This source code is licensed under the GNU General Public License,
6 * Version 2. See the file COPYING for more details.
7 */
8
9#include <asm/asm.h>
10#include <asm/asmmacro.h>
11#include <asm/regdef.h>
12#include <asm/page.h>
13#include <asm/mipsregs.h>
14#include <asm/stackframe.h>
15#include <asm/addrspace.h>
16
17 .globl relocate_new_kernel
18relocate_new_kernel:
19
20 PTR_L s0, kexec_indirection_page
21 PTR_L s1, kexec_start_address
22
23process_entry:
24 PTR_L s2, (s0)
25 PTR_ADD s0, s0, SZREG
26
27 /* destination page */
28 and s3, s2, 0x1
29 beq s3, zero, 1f
30 and s4, s2, ~0x1 /* store destination addr in s4 */
31 move a0, s4
32 b process_entry
33
341:
35 /* indirection page, update s0 */
36 and s3, s2, 0x2
37 beq s3, zero, 1f
38 and s0, s2, ~0x2
39 b process_entry
40
411:
42 /* done page */
43 and s3, s2, 0x4
44 beq s3, zero, 1f
45 b done
461:
47 /* source page */
48 and s3, s2, 0x8
49 beq s3, zero, process_entry
50 and s2, s2, ~0x8
51 li s6, (1 << PAGE_SHIFT) / SZREG
52
53copy_word:
54 /* copy page word by word */
55 REG_L s5, (s2)
56 REG_S s5, (s4)
57 INT_ADD s4, s4, SZREG
58 INT_ADD s2, s2, SZREG
59 INT_SUB s6, s6, 1
60 beq s6, zero, process_entry
61 b copy_word
62 b process_entry
63
64done:
65 /* jump to kexec_start_address */
66 j s1
67
68 .globl kexec_start_address
69kexec_start_address:
70 .long 0x0
71
72 .globl kexec_indirection_page
73kexec_indirection_page:
74 .long 0x0
75
76relocate_new_kernel_end:
77
78 .globl relocate_new_kernel_size
79relocate_new_kernel_size:
80 .long relocate_new_kernel_end - relocate_new_kernel
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index a95f37de080e..7c0b3936ba44 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -653,7 +653,7 @@ einval: li v0, -EINVAL
653 sys sys_move_pages 6 653 sys sys_move_pages 6
654 sys sys_set_robust_list 2 654 sys sys_set_robust_list 2
655 sys sys_get_robust_list 3 /* 4310 */ 655 sys sys_get_robust_list 3 /* 4310 */
656 sys sys_ni_syscall 0 656 sys sys_kexec_load 4
657 sys sys_getcpu 3 657 sys sys_getcpu 3
658 sys sys_epoll_pwait 6 658 sys sys_epoll_pwait 6
659 .endm 659 .endm
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 8fb0f60f657b..e569b846e9a3 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -468,6 +468,6 @@ sys_call_table:
468 PTR sys_move_pages 468 PTR sys_move_pages
469 PTR sys_set_robust_list 469 PTR sys_set_robust_list
470 PTR sys_get_robust_list 470 PTR sys_get_robust_list
471 PTR sys_ni_syscall /* 5270 */ 471 PTR sys_kexec_load /* 5270 */
472 PTR sys_getcpu 472 PTR sys_getcpu
473 PTR sys_epoll_pwait 473 PTR sys_epoll_pwait
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 0da5ca2040ff..5b18f265d75b 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -394,6 +394,6 @@ EXPORT(sysn32_call_table)
394 PTR sys_move_pages 394 PTR sys_move_pages
395 PTR compat_sys_set_robust_list 395 PTR compat_sys_set_robust_list
396 PTR compat_sys_get_robust_list 396 PTR compat_sys_get_robust_list
397 PTR sys_ni_syscall 397 PTR compat_sys_kexec_load
398 PTR sys_getcpu 398 PTR sys_getcpu
399 PTR sys_epoll_pwait 399 PTR sys_epoll_pwait
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index b9d00cae8b5f..e91379c1be1d 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -516,7 +516,7 @@ sys_call_table:
516 PTR compat_sys_move_pages 516 PTR compat_sys_move_pages
517 PTR compat_sys_set_robust_list 517 PTR compat_sys_set_robust_list
518 PTR compat_sys_get_robust_list /* 4310 */ 518 PTR compat_sys_get_robust_list /* 4310 */
519 PTR sys_ni_syscall 519 PTR compat_sys_kexec_load
520 PTR sys_getcpu 520 PTR sys_getcpu
521 PTR sys_epoll_pwait 521 PTR sys_epoll_pwait
522 .size sys_call_table,.-sys_call_table 522 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8f6e89697ccf..89440a0d8528 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -145,13 +145,12 @@ static int __init rd_start_early(char *p)
145 unsigned long start = memparse(p, &p); 145 unsigned long start = memparse(p, &p);
146 146
147#ifdef CONFIG_64BIT 147#ifdef CONFIG_64BIT
148 /* HACK: Guess if the sign extension was forgotten */ 148 /* Guess if the sign extension was forgotten by bootloader */
149 if (start > 0x0000000080000000 && start < 0x00000000ffffffff) 149 if (start < XKPHYS)
150 start |= 0xffffffff00000000UL; 150 start = (int)start;
151#endif 151#endif
152 initrd_start = start; 152 initrd_start = start;
153 initrd_end += start; 153 initrd_end += start;
154
155 return 0; 154 return 0;
156} 155}
157early_param("rd_start", rd_start_early); 156early_param("rd_start", rd_start_early);
@@ -159,41 +158,64 @@ early_param("rd_start", rd_start_early);
159static int __init rd_size_early(char *p) 158static int __init rd_size_early(char *p)
160{ 159{
161 initrd_end += memparse(p, &p); 160 initrd_end += memparse(p, &p);
162
163 return 0; 161 return 0;
164} 162}
165early_param("rd_size", rd_size_early); 163early_param("rd_size", rd_size_early);
166 164
165/* it returns the next free pfn after initrd */
167static unsigned long __init init_initrd(void) 166static unsigned long __init init_initrd(void)
168{ 167{
169 unsigned long tmp, end, size; 168 unsigned long end;
170 u32 *initrd_header; 169 u32 *initrd_header;
171 170
172 ROOT_DEV = Root_RAM0;
173
174 /* 171 /*
175 * Board specific code or command line parser should have 172 * Board specific code or command line parser should have
176 * already set up initrd_start and initrd_end. In these cases 173 * already set up initrd_start and initrd_end. In these cases
177 * perfom sanity checks and use them if all looks good. 174 * perfom sanity checks and use them if all looks good.
178 */ 175 */
179 size = initrd_end - initrd_start; 176 if (initrd_start && initrd_end > initrd_start)
180 if (initrd_end == 0 || size == 0) { 177 goto sanitize;
181 initrd_start = 0; 178
182 initrd_end = 0; 179 /*
183 } else 180 * See if initrd has been added to the kernel image by
184 return initrd_end; 181 * arch/mips/boot/addinitrd.c. In that case a header is
185 182 * prepended to initrd and is made up by 8 bytes. The fisrt
186 end = (unsigned long)&_end; 183 * word is a magic number and the second one is the size of
187 tmp = PAGE_ALIGN(end) - sizeof(u32) * 2; 184 * initrd. Initrd start must be page aligned in any cases.
188 if (tmp < end) 185 */
189 tmp += PAGE_SIZE; 186 initrd_header = __va(PAGE_ALIGN(__pa_symbol(&_end) + 8)) - 8;
190 187 if (initrd_header[0] != 0x494E5244)
191 initrd_header = (u32 *)tmp; 188 goto disable;
192 if (initrd_header[0] == 0x494E5244) { 189 initrd_start = (unsigned long)(initrd_header + 2);
193 initrd_start = (unsigned long)&initrd_header[2]; 190 initrd_end = initrd_start + initrd_header[1];
194 initrd_end = initrd_start + initrd_header[1]; 191
192sanitize:
193 if (initrd_start & ~PAGE_MASK) {
194 printk(KERN_ERR "initrd start must be page aligned\n");
195 goto disable;
195 } 196 }
196 return initrd_end; 197 if (initrd_start < PAGE_OFFSET) {
198 printk(KERN_ERR "initrd start < PAGE_OFFSET\n");
199 goto disable;
200 }
201
202 /*
203 * Sanitize initrd addresses. For example firmware
204 * can't guess if they need to pass them through
205 * 64-bits values if the kernel has been built in pure
206 * 32-bit. We need also to switch from KSEG0 to XKPHYS
207 * addresses now, so the code can now safely use __pa().
208 */
209 end = __pa(initrd_end);
210 initrd_end = (unsigned long)__va(end);
211 initrd_start = (unsigned long)__va(__pa(initrd_start));
212
213 ROOT_DEV = Root_RAM0;
214 return PFN_UP(end);
215disable:
216 initrd_start = 0;
217 initrd_end = 0;
218 return 0;
197} 219}
198 220
199static void __init finalize_initrd(void) 221static void __init finalize_initrd(void)
@@ -204,12 +226,12 @@ static void __init finalize_initrd(void)
204 printk(KERN_INFO "Initrd not found or empty"); 226 printk(KERN_INFO "Initrd not found or empty");
205 goto disable; 227 goto disable;
206 } 228 }
207 if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { 229 if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) {
208 printk("Initrd extends beyond end of memory"); 230 printk("Initrd extends beyond end of memory");
209 goto disable; 231 goto disable;
210 } 232 }
211 233
212 reserve_bootmem(CPHYSADDR(initrd_start), size); 234 reserve_bootmem(__pa(initrd_start), size);
213 initrd_below_start_ok = 1; 235 initrd_below_start_ok = 1;
214 236
215 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 237 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
@@ -259,8 +281,7 @@ static void __init bootmem_init(void)
259 * not selected. Once that done we can determine the low bound 281 * not selected. Once that done we can determine the low bound
260 * of usable memory. 282 * of usable memory.
261 */ 283 */
262 reserved_end = init_initrd(); 284 reserved_end = max(init_initrd(), PFN_UP(__pa_symbol(&_end)));
263 reserved_end = PFN_UP(CPHYSADDR(max(reserved_end, (unsigned long)&_end)));
264 285
265 /* 286 /*
266 * Find the highest page frame number we have available. 287 * Find the highest page frame number we have available.
@@ -432,10 +453,10 @@ static void __init resource_init(void)
432 if (UNCAC_BASE != IO_BASE) 453 if (UNCAC_BASE != IO_BASE)
433 return; 454 return;
434 455
435 code_resource.start = virt_to_phys(&_text); 456 code_resource.start = __pa_symbol(&_text);
436 code_resource.end = virt_to_phys(&_etext) - 1; 457 code_resource.end = __pa_symbol(&_etext) - 1;
437 data_resource.start = virt_to_phys(&_etext); 458 data_resource.start = __pa_symbol(&_etext);
438 data_resource.end = virt_to_phys(&_edata) - 1; 459 data_resource.end = __pa_symbol(&_edata) - 1;
439 460
440 /* 461 /*
441 * Request address space for all standard RAM. 462 * Request address space for all standard RAM.
diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index 477c5334ec1b..a67c18555ed3 100644
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -17,7 +17,6 @@
17 */ 17 */
18#include <linux/cache.h> 18#include <linux/cache.h>
19#include <linux/sched.h> 19#include <linux/sched.h>
20#include <linux/sched.h>
21#include <linux/mm.h> 20#include <linux/mm.h>
22#include <linux/smp.h> 21#include <linux/smp.h>
23#include <linux/smp_lock.h> 22#include <linux/smp_lock.h>
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 2ac19a6cbf68..1ee689c0e0c9 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -278,7 +278,9 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
278 278
279 /* need to mark IPI's as IRQ_PER_CPU */ 279 /* need to mark IPI's as IRQ_PER_CPU */
280 irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU; 280 irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU;
281 set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
281 irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU; 282 irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU;
283 set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
282} 284}
283 285
284/* 286/*
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 3b78caf112f5..802febed7df5 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1009,6 +1009,7 @@ void setup_cross_vpe_interrupts(void)
1009 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); 1009 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
1010 1010
1011 irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU; 1011 irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU;
1012 set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
1012} 1013}
1013 1014
1014/* 1015/*
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index e535f86efa2f..11aab6d6bfe5 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -11,7 +11,6 @@
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14#include <linux/clocksource.h>
15#include <linux/types.h> 14#include <linux/types.h>
16#include <linux/kernel.h> 15#include <linux/kernel.h>
17#include <linux/init.h> 16#include <linux/init.h>
@@ -83,17 +82,11 @@ static void null_timer_ack(void) { /* nothing */ }
83/* 82/*
84 * Null high precision timer functions for systems lacking one. 83 * Null high precision timer functions for systems lacking one.
85 */ 84 */
86static unsigned int null_hpt_read(void) 85static cycle_t null_hpt_read(void)
87{ 86{
88 return 0; 87 return 0;
89} 88}
90 89
91static void __init null_hpt_init(void)
92{
93 /* nothing */
94}
95
96
97/* 90/*
98 * Timer ack for an R4k-compatible timer of a known frequency. 91 * Timer ack for an R4k-compatible timer of a known frequency.
99 */ 92 */
@@ -118,7 +111,7 @@ static void c0_timer_ack(void)
118/* 111/*
119 * High precision timer functions for a R4k-compatible timer. 112 * High precision timer functions for a R4k-compatible timer.
120 */ 113 */
121static unsigned int c0_hpt_read(void) 114static cycle_t c0_hpt_read(void)
122{ 115{
123 return read_c0_count(); 116 return read_c0_count();
124} 117}
@@ -132,9 +125,6 @@ static void __init c0_hpt_timer_init(void)
132 125
133int (*mips_timer_state)(void); 126int (*mips_timer_state)(void);
134void (*mips_timer_ack)(void); 127void (*mips_timer_ack)(void);
135unsigned int (*mips_hpt_read)(void);
136void (*mips_hpt_init)(void) __initdata = null_hpt_init;
137unsigned int mips_hpt_mask = 0xffffffff;
138 128
139/* last time when xtime and rtc are sync'ed up */ 129/* last time when xtime and rtc are sync'ed up */
140static long last_rtc_update; 130static long last_rtc_update;
@@ -276,8 +266,7 @@ static struct irqaction timer_irqaction = {
276 266
277static unsigned int __init calibrate_hpt(void) 267static unsigned int __init calibrate_hpt(void)
278{ 268{
279 u64 frequency; 269 cycle_t frequency, hpt_start, hpt_end, hpt_count, hz;
280 u32 hpt_start, hpt_end, hpt_count, hz;
281 270
282 const int loops = HZ / 10; 271 const int loops = HZ / 10;
283 int log_2_loops = 0; 272 int log_2_loops = 0;
@@ -303,28 +292,23 @@ static unsigned int __init calibrate_hpt(void)
303 * during the calculated number of periods between timer 292 * during the calculated number of periods between timer
304 * interrupts. 293 * interrupts.
305 */ 294 */
306 hpt_start = mips_hpt_read(); 295 hpt_start = clocksource_mips.read();
307 do { 296 do {
308 while (mips_timer_state()); 297 while (mips_timer_state());
309 while (!mips_timer_state()); 298 while (!mips_timer_state());
310 } while (--i); 299 } while (--i);
311 hpt_end = mips_hpt_read(); 300 hpt_end = clocksource_mips.read();
312 301
313 hpt_count = (hpt_end - hpt_start) & mips_hpt_mask; 302 hpt_count = (hpt_end - hpt_start) & clocksource_mips.mask;
314 hz = HZ; 303 hz = HZ;
315 frequency = (u64)hpt_count * (u64)hz; 304 frequency = hpt_count * hz;
316 305
317 return frequency >> log_2_loops; 306 return frequency >> log_2_loops;
318} 307}
319 308
320static cycle_t read_mips_hpt(void) 309struct clocksource clocksource_mips = {
321{
322 return (cycle_t)mips_hpt_read();
323}
324
325static struct clocksource clocksource_mips = {
326 .name = "MIPS", 310 .name = "MIPS",
327 .read = read_mips_hpt, 311 .mask = 0xffffffff,
328 .is_continuous = 1, 312 .is_continuous = 1,
329}; 313};
330 314
@@ -333,7 +317,7 @@ static void __init init_mips_clocksource(void)
333 u64 temp; 317 u64 temp;
334 u32 shift; 318 u32 shift;
335 319
336 if (!mips_hpt_frequency || mips_hpt_read == null_hpt_read) 320 if (!mips_hpt_frequency || clocksource_mips.read == null_hpt_read)
337 return; 321 return;
338 322
339 /* Calclate a somewhat reasonable rating value */ 323 /* Calclate a somewhat reasonable rating value */
@@ -347,7 +331,6 @@ static void __init init_mips_clocksource(void)
347 } 331 }
348 clocksource_mips.shift = shift; 332 clocksource_mips.shift = shift;
349 clocksource_mips.mult = (u32)temp; 333 clocksource_mips.mult = (u32)temp;
350 clocksource_mips.mask = mips_hpt_mask;
351 334
352 clocksource_register(&clocksource_mips); 335 clocksource_register(&clocksource_mips);
353} 336}
@@ -367,32 +350,36 @@ void __init time_init(void)
367 -xtime.tv_sec, -xtime.tv_nsec); 350 -xtime.tv_sec, -xtime.tv_nsec);
368 351
369 /* Choose appropriate high precision timer routines. */ 352 /* Choose appropriate high precision timer routines. */
370 if (!cpu_has_counter && !mips_hpt_read) 353 if (!cpu_has_counter && !clocksource_mips.read)
371 /* No high precision timer -- sorry. */ 354 /* No high precision timer -- sorry. */
372 mips_hpt_read = null_hpt_read; 355 clocksource_mips.read = null_hpt_read;
373 else if (!mips_hpt_frequency && !mips_timer_state) { 356 else if (!mips_hpt_frequency && !mips_timer_state) {
374 /* A high precision timer of unknown frequency. */ 357 /* A high precision timer of unknown frequency. */
375 if (!mips_hpt_read) 358 if (!clocksource_mips.read)
376 /* No external high precision timer -- use R4k. */ 359 /* No external high precision timer -- use R4k. */
377 mips_hpt_read = c0_hpt_read; 360 clocksource_mips.read = c0_hpt_read;
378 } else { 361 } else {
379 /* We know counter frequency. Or we can get it. */ 362 /* We know counter frequency. Or we can get it. */
380 if (!mips_hpt_read) { 363 if (!clocksource_mips.read) {
381 /* No external high precision timer -- use R4k. */ 364 /* No external high precision timer -- use R4k. */
382 mips_hpt_read = c0_hpt_read; 365 clocksource_mips.read = c0_hpt_read;
383 366
384 if (!mips_timer_state) { 367 if (!mips_timer_state) {
385 /* No external timer interrupt -- use R4k. */ 368 /* No external timer interrupt -- use R4k. */
386 mips_hpt_init = c0_hpt_timer_init;
387 mips_timer_ack = c0_timer_ack; 369 mips_timer_ack = c0_timer_ack;
370 /* Calculate cache parameters. */
371 cycles_per_jiffy =
372 (mips_hpt_frequency + HZ / 2) / HZ;
373 /*
374 * This sets up the high precision
375 * timer for the first interrupt.
376 */
377 c0_hpt_timer_init();
388 } 378 }
389 } 379 }
390 if (!mips_hpt_frequency) 380 if (!mips_hpt_frequency)
391 mips_hpt_frequency = calibrate_hpt(); 381 mips_hpt_frequency = calibrate_hpt();
392 382
393 /* Calculate cache parameters. */
394 cycles_per_jiffy = (mips_hpt_frequency + HZ / 2) / HZ;
395
396 /* Report the high precision timer rate for a reference. */ 383 /* Report the high precision timer rate for a reference. */
397 printk("Using %u.%03u MHz high precision timer.\n", 384 printk("Using %u.%03u MHz high precision timer.\n",
398 ((mips_hpt_frequency + 500) / 1000) / 1000, 385 ((mips_hpt_frequency + 500) / 1000) / 1000,
@@ -403,9 +390,6 @@ void __init time_init(void)
403 /* No timer interrupt ack (e.g. i8254). */ 390 /* No timer interrupt ack (e.g. i8254). */
404 mips_timer_ack = null_timer_ack; 391 mips_timer_ack = null_timer_ack;
405 392
406 /* This sets up the high precision timer for the first interrupt. */
407 mips_hpt_init();
408
409 /* 393 /*
410 * Call board specific timer interrupt setup. 394 * Call board specific timer interrupt setup.
411 * 395 *
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 9fda1b8be3a7..2a932cada244 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -54,6 +54,8 @@ extern asmlinkage void handle_dbe(void);
54extern asmlinkage void handle_sys(void); 54extern asmlinkage void handle_sys(void);
55extern asmlinkage void handle_bp(void); 55extern asmlinkage void handle_bp(void);
56extern asmlinkage void handle_ri(void); 56extern asmlinkage void handle_ri(void);
57extern asmlinkage void handle_ri_rdhwr_vivt(void);
58extern asmlinkage void handle_ri_rdhwr(void);
57extern asmlinkage void handle_cpu(void); 59extern asmlinkage void handle_cpu(void);
58extern asmlinkage void handle_ov(void); 60extern asmlinkage void handle_ov(void);
59extern asmlinkage void handle_tr(void); 61extern asmlinkage void handle_tr(void);
@@ -397,19 +399,6 @@ asmlinkage void do_be(struct pt_regs *regs)
397 force_sig(SIGBUS, current); 399 force_sig(SIGBUS, current);
398} 400}
399 401
400static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
401{
402 unsigned int __user *epc;
403
404 epc = (unsigned int __user *) regs->cp0_epc +
405 ((regs->cp0_cause & CAUSEF_BD) != 0);
406 if (!get_user(*opcode, epc))
407 return 0;
408
409 force_sig(SIGSEGV, current);
410 return 1;
411}
412
413/* 402/*
414 * ll/sc emulation 403 * ll/sc emulation
415 */ 404 */
@@ -544,8 +533,8 @@ static inline int simulate_llsc(struct pt_regs *regs)
544{ 533{
545 unsigned int opcode; 534 unsigned int opcode;
546 535
547 if (unlikely(get_insn_opcode(regs, &opcode))) 536 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
548 return -EFAULT; 537 goto out_sigsegv;
549 538
550 if ((opcode & OPCODE) == LL) { 539 if ((opcode & OPCODE) == LL) {
551 simulate_ll(regs, opcode); 540 simulate_ll(regs, opcode);
@@ -557,6 +546,10 @@ static inline int simulate_llsc(struct pt_regs *regs)
557 } 546 }
558 547
559 return -EFAULT; /* Strange things going on ... */ 548 return -EFAULT; /* Strange things going on ... */
549
550out_sigsegv:
551 force_sig(SIGSEGV, current);
552 return -EFAULT;
560} 553}
561 554
562/* 555/*
@@ -569,8 +562,8 @@ static inline int simulate_rdhwr(struct pt_regs *regs)
569 struct thread_info *ti = task_thread_info(current); 562 struct thread_info *ti = task_thread_info(current);
570 unsigned int opcode; 563 unsigned int opcode;
571 564
572 if (unlikely(get_insn_opcode(regs, &opcode))) 565 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
573 return -EFAULT; 566 goto out_sigsegv;
574 567
575 if (unlikely(compute_return_epc(regs))) 568 if (unlikely(compute_return_epc(regs)))
576 return -EFAULT; 569 return -EFAULT;
@@ -589,6 +582,10 @@ static inline int simulate_rdhwr(struct pt_regs *regs)
589 582
590 /* Not ours. */ 583 /* Not ours. */
591 return -EFAULT; 584 return -EFAULT;
585
586out_sigsegv:
587 force_sig(SIGSEGV, current);
588 return -EFAULT;
592} 589}
593 590
594asmlinkage void do_ov(struct pt_regs *regs) 591asmlinkage void do_ov(struct pt_regs *regs)
@@ -672,10 +669,8 @@ asmlinkage void do_bp(struct pt_regs *regs)
672 unsigned int opcode, bcode; 669 unsigned int opcode, bcode;
673 siginfo_t info; 670 siginfo_t info;
674 671
675 die_if_kernel("Break instruction in kernel code", regs); 672 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
676 673 goto out_sigsegv;
677 if (get_insn_opcode(regs, &opcode))
678 return;
679 674
680 /* 675 /*
681 * There is the ancient bug in the MIPS assemblers that the break 676 * There is the ancient bug in the MIPS assemblers that the break
@@ -696,6 +691,7 @@ asmlinkage void do_bp(struct pt_regs *regs)
696 switch (bcode) { 691 switch (bcode) {
697 case BRK_OVERFLOW << 10: 692 case BRK_OVERFLOW << 10:
698 case BRK_DIVZERO << 10: 693 case BRK_DIVZERO << 10:
694 die_if_kernel("Break instruction in kernel code", regs);
699 if (bcode == (BRK_DIVZERO << 10)) 695 if (bcode == (BRK_DIVZERO << 10))
700 info.si_code = FPE_INTDIV; 696 info.si_code = FPE_INTDIV;
701 else 697 else
@@ -705,9 +701,16 @@ asmlinkage void do_bp(struct pt_regs *regs)
705 info.si_addr = (void __user *) regs->cp0_epc; 701 info.si_addr = (void __user *) regs->cp0_epc;
706 force_sig_info(SIGFPE, &info, current); 702 force_sig_info(SIGFPE, &info, current);
707 break; 703 break;
704 case BRK_BUG:
705 die("Kernel bug detected", regs);
706 break;
708 default: 707 default:
708 die_if_kernel("Break instruction in kernel code", regs);
709 force_sig(SIGTRAP, current); 709 force_sig(SIGTRAP, current);
710 } 710 }
711
712out_sigsegv:
713 force_sig(SIGSEGV, current);
711} 714}
712 715
713asmlinkage void do_tr(struct pt_regs *regs) 716asmlinkage void do_tr(struct pt_regs *regs)
@@ -715,10 +718,8 @@ asmlinkage void do_tr(struct pt_regs *regs)
715 unsigned int opcode, tcode = 0; 718 unsigned int opcode, tcode = 0;
716 siginfo_t info; 719 siginfo_t info;
717 720
718 die_if_kernel("Trap instruction in kernel code", regs); 721 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
719 722 goto out_sigsegv;
720 if (get_insn_opcode(regs, &opcode))
721 return;
722 723
723 /* Immediate versions don't provide a code. */ 724 /* Immediate versions don't provide a code. */
724 if (!(opcode & OPCODE)) 725 if (!(opcode & OPCODE))
@@ -733,6 +734,7 @@ asmlinkage void do_tr(struct pt_regs *regs)
733 switch (tcode) { 734 switch (tcode) {
734 case BRK_OVERFLOW: 735 case BRK_OVERFLOW:
735 case BRK_DIVZERO: 736 case BRK_DIVZERO:
737 die_if_kernel("Trap instruction in kernel code", regs);
736 if (tcode == BRK_DIVZERO) 738 if (tcode == BRK_DIVZERO)
737 info.si_code = FPE_INTDIV; 739 info.si_code = FPE_INTDIV;
738 else 740 else
@@ -742,9 +744,16 @@ asmlinkage void do_tr(struct pt_regs *regs)
742 info.si_addr = (void __user *) regs->cp0_epc; 744 info.si_addr = (void __user *) regs->cp0_epc;
743 force_sig_info(SIGFPE, &info, current); 745 force_sig_info(SIGFPE, &info, current);
744 break; 746 break;
747 case BRK_BUG:
748 die("Kernel bug detected", regs);
749 break;
745 default: 750 default:
751 die_if_kernel("Trap instruction in kernel code", regs);
746 force_sig(SIGTRAP, current); 752 force_sig(SIGTRAP, current);
747 } 753 }
754
755out_sigsegv:
756 force_sig(SIGSEGV, current);
748} 757}
749 758
750asmlinkage void do_ri(struct pt_regs *regs) 759asmlinkage void do_ri(struct pt_regs *regs)
@@ -1423,6 +1432,15 @@ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned lon
1423 memcpy((void *)(uncached_ebase + offset), addr, size); 1432 memcpy((void *)(uncached_ebase + offset), addr, size);
1424} 1433}
1425 1434
1435static int __initdata rdhwr_noopt;
1436static int __init set_rdhwr_noopt(char *str)
1437{
1438 rdhwr_noopt = 1;
1439 return 1;
1440}
1441
1442__setup("rdhwr_noopt", set_rdhwr_noopt);
1443
1426void __init trap_init(void) 1444void __init trap_init(void)
1427{ 1445{
1428 extern char except_vec3_generic, except_vec3_r4000; 1446 extern char except_vec3_generic, except_vec3_r4000;
@@ -1502,7 +1520,9 @@ void __init trap_init(void)
1502 1520
1503 set_except_vector(8, handle_sys); 1521 set_except_vector(8, handle_sys);
1504 set_except_vector(9, handle_bp); 1522 set_except_vector(9, handle_bp);
1505 set_except_vector(10, handle_ri); 1523 set_except_vector(10, rdhwr_noopt ? handle_ri :
1524 (cpu_has_vtag_icache ?
1525 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1506 set_except_vector(11, handle_cpu); 1526 set_except_vector(11, handle_cpu);
1507 set_except_vector(12, handle_ov); 1527 set_except_vector(12, handle_ov);
1508 set_except_vector(13, handle_tr); 1528 set_except_vector(13, handle_tr);
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index a144a002dcc4..4a84a7beac53 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -36,33 +36,14 @@ static volatile int lasat_int_mask_shift;
36 36
37void disable_lasat_irq(unsigned int irq_nr) 37void disable_lasat_irq(unsigned int irq_nr)
38{ 38{
39 unsigned long flags;
40
41 local_irq_save(flags);
42 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift; 39 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift;
43 local_irq_restore(flags);
44} 40}
45 41
46void enable_lasat_irq(unsigned int irq_nr) 42void enable_lasat_irq(unsigned int irq_nr)
47{ 43{
48 unsigned long flags;
49
50 local_irq_save(flags);
51 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; 44 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
52 local_irq_restore(flags);
53} 45}
54 46
55static unsigned int startup_lasat_irq(unsigned int irq)
56{
57 enable_lasat_irq(irq);
58
59 return 0; /* never anything pending */
60}
61
62#define shutdown_lasat_irq disable_lasat_irq
63
64#define mask_and_ack_lasat_irq disable_lasat_irq
65
66static void end_lasat_irq(unsigned int irq) 47static void end_lasat_irq(unsigned int irq)
67{ 48{
68 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 49 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -71,11 +52,10 @@ static void end_lasat_irq(unsigned int irq)
71 52
72static struct irq_chip lasat_irq_type = { 53static struct irq_chip lasat_irq_type = {
73 .typename = "Lasat", 54 .typename = "Lasat",
74 .startup = startup_lasat_irq, 55 .ack = disable_lasat_irq,
75 .shutdown = shutdown_lasat_irq, 56 .mask = disable_lasat_irq,
76 .enable = enable_lasat_irq, 57 .mask_ack = disable_lasat_irq,
77 .disable = disable_lasat_irq, 58 .unmask = enable_lasat_irq,
78 .ack = mask_and_ack_lasat_irq,
79 .end = end_lasat_irq, 59 .end = end_lasat_irq,
80}; 60};
81 61
@@ -152,10 +132,6 @@ void __init arch_init_irq(void)
152 panic("arch_init_irq: mips_machtype incorrect"); 132 panic("arch_init_irq: mips_machtype incorrect");
153 } 133 }
154 134
155 for (i = 0; i <= LASATINT_END; i++) { 135 for (i = 0; i <= LASATINT_END; i++)
156 irq_desc[i].status = IRQ_DISABLED; 136 set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
157 irq_desc[i].action = 0;
158 irq_desc[i].depth = 1;
159 irq_desc[i].chip = &lasat_irq_type;
160 }
161} 137}
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index be624b8c3b0e..43dba6ce6603 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -62,16 +62,6 @@ void enable_atlas_irq(unsigned int irq_nr)
62 iob(); 62 iob();
63} 63}
64 64
65static unsigned int startup_atlas_irq(unsigned int irq)
66{
67 enable_atlas_irq(irq);
68 return 0; /* never anything pending */
69}
70
71#define shutdown_atlas_irq disable_atlas_irq
72
73#define mask_and_ack_atlas_irq disable_atlas_irq
74
75static void end_atlas_irq(unsigned int irq) 65static void end_atlas_irq(unsigned int irq)
76{ 66{
77 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 67 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -80,11 +70,11 @@ static void end_atlas_irq(unsigned int irq)
80 70
81static struct irq_chip atlas_irq_type = { 71static struct irq_chip atlas_irq_type = {
82 .typename = "Atlas", 72 .typename = "Atlas",
83 .startup = startup_atlas_irq, 73 .ack = disable_atlas_irq,
84 .shutdown = shutdown_atlas_irq, 74 .mask = disable_atlas_irq,
85 .enable = enable_atlas_irq, 75 .mask_ack = disable_atlas_irq,
86 .disable = disable_atlas_irq, 76 .unmask = enable_atlas_irq,
87 .ack = mask_and_ack_atlas_irq, 77 .eoi = enable_atlas_irq,
88 .end = end_atlas_irq, 78 .end = end_atlas_irq,
89}; 79};
90 80
@@ -217,13 +207,8 @@ static inline void init_atlas_irqs (int base)
217 */ 207 */
218 atlas_hw0_icregs->intrsten = 0xffffffff; 208 atlas_hw0_icregs->intrsten = 0xffffffff;
219 209
220 for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) { 210 for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++)
221 irq_desc[i].status = IRQ_DISABLED; 211 set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq);
222 irq_desc[i].action = 0;
223 irq_desc[i].depth = 1;
224 irq_desc[i].chip = &atlas_irq_type;
225 spin_lock_init(&irq_desc[i].lock);
226 }
227} 212}
228 213
229static struct irqaction atlasirq = { 214static struct irqaction atlasirq = {
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index d817c60c5ca5..e4604c73f02e 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -288,6 +288,7 @@ void __init plat_timer_setup(struct irqaction *irq)
288 The effect is that the int remains disabled on the second cpu. 288 The effect is that the int remains disabled on the second cpu.
289 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ 289 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
290 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; 290 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
291 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
291#endif 292#endif
292 293
293 /* to generate the first timer interrupt */ 294 /* to generate the first timer interrupt */
diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c
index 24a4ed00cc0a..30711d016fed 100644
--- a/arch/mips/mips-boards/sim/sim_time.c
+++ b/arch/mips/mips-boards/sim/sim_time.c
@@ -3,31 +3,24 @@
3#include <linux/kernel_stat.h> 3#include <linux/kernel_stat.h>
4#include <linux/sched.h> 4#include <linux/sched.h>
5#include <linux/spinlock.h> 5#include <linux/spinlock.h>
6
7#include <asm/mipsregs.h>
8#include <asm/ptrace.h>
9#include <asm/hardirq.h>
10#include <asm/div64.h>
11#include <asm/cpu.h>
12#include <asm/time.h>
13
14#include <linux/interrupt.h> 6#include <linux/interrupt.h>
15#include <linux/mc146818rtc.h> 7#include <linux/mc146818rtc.h>
16#include <linux/timex.h> 8#include <linux/timex.h>
9
17#include <asm/mipsregs.h> 10#include <asm/mipsregs.h>
11#include <asm/ptrace.h>
18#include <asm/hardirq.h> 12#include <asm/hardirq.h>
19#include <asm/irq.h>
20#include <asm/div64.h> 13#include <asm/div64.h>
21#include <asm/cpu.h> 14#include <asm/cpu.h>
22#include <asm/time.h> 15#include <asm/time.h>
16#include <asm/irq.h>
23#include <asm/mc146818-time.h> 17#include <asm/mc146818-time.h>
24#include <asm/msc01_ic.h> 18#include <asm/msc01_ic.h>
19#include <asm/smp.h>
25 20
26#include <asm/mips-boards/generic.h> 21#include <asm/mips-boards/generic.h>
27#include <asm/mips-boards/prom.h> 22#include <asm/mips-boards/prom.h>
28#include <asm/mips-boards/simint.h> 23#include <asm/mips-boards/simint.h>
29#include <asm/mc146818-time.h>
30#include <asm/smp.h>
31 24
32 25
33unsigned long cpu_khz; 26unsigned long cpu_khz;
@@ -203,7 +196,8 @@ void __init plat_timer_setup(struct irqaction *irq)
203 on seperate cpu's the first one tries to handle the second interrupt. 196 on seperate cpu's the first one tries to handle the second interrupt.
204 The effect is that the int remains disabled on the second cpu. 197 The effect is that the int remains disabled on the second cpu.
205 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ 198 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
206 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; 199 irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU;
200 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
207#endif 201#endif
208 202
209 /* to generate the first timer interrupt */ 203 /* to generate the first timer interrupt */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index cc895dad71d2..df04a315d830 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -323,7 +323,6 @@ static void __init r4k_blast_scache_setup(void)
323static inline void local_r4k_flush_cache_all(void * args) 323static inline void local_r4k_flush_cache_all(void * args)
324{ 324{
325 r4k_blast_dcache(); 325 r4k_blast_dcache();
326 r4k_blast_icache();
327} 326}
328 327
329static void r4k_flush_cache_all(void) 328static void r4k_flush_cache_all(void)
@@ -359,21 +358,19 @@ static void r4k___flush_cache_all(void)
359static inline void local_r4k_flush_cache_range(void * args) 358static inline void local_r4k_flush_cache_range(void * args)
360{ 359{
361 struct vm_area_struct *vma = args; 360 struct vm_area_struct *vma = args;
362 int exec;
363 361
364 if (!(cpu_context(smp_processor_id(), vma->vm_mm))) 362 if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
365 return; 363 return;
366 364
367 exec = vma->vm_flags & VM_EXEC; 365 r4k_blast_dcache();
368 if (cpu_has_dc_aliases || exec)
369 r4k_blast_dcache();
370 if (exec)
371 r4k_blast_icache();
372} 366}
373 367
374static void r4k_flush_cache_range(struct vm_area_struct *vma, 368static void r4k_flush_cache_range(struct vm_area_struct *vma,
375 unsigned long start, unsigned long end) 369 unsigned long start, unsigned long end)
376{ 370{
371 if (!cpu_has_dc_aliases)
372 return;
373
377 r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); 374 r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
378} 375}
379 376
@@ -384,18 +381,21 @@ static inline void local_r4k_flush_cache_mm(void * args)
384 if (!cpu_context(smp_processor_id(), mm)) 381 if (!cpu_context(smp_processor_id(), mm))
385 return; 382 return;
386 383
387 r4k_blast_dcache();
388 r4k_blast_icache();
389
390 /* 384 /*
391 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we 385 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
392 * only flush the primary caches but R10000 and R12000 behave sane ... 386 * only flush the primary caches but R10000 and R12000 behave sane ...
387 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
388 * caches, so we can bail out early.
393 */ 389 */
394 if (current_cpu_data.cputype == CPU_R4000SC || 390 if (current_cpu_data.cputype == CPU_R4000SC ||
395 current_cpu_data.cputype == CPU_R4000MC || 391 current_cpu_data.cputype == CPU_R4000MC ||
396 current_cpu_data.cputype == CPU_R4400SC || 392 current_cpu_data.cputype == CPU_R4400SC ||
397 current_cpu_data.cputype == CPU_R4400MC) 393 current_cpu_data.cputype == CPU_R4400MC) {
398 r4k_blast_scache(); 394 r4k_blast_scache();
395 return;
396 }
397
398 r4k_blast_dcache();
399} 399}
400 400
401static void r4k_flush_cache_mm(struct mm_struct *mm) 401static void r4k_flush_cache_mm(struct mm_struct *mm)
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 8423d8590779..6f90e7ef66ac 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -60,6 +60,10 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
60 */ 60 */
61 if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END)) 61 if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END))
62 goto vmalloc_fault; 62 goto vmalloc_fault;
63#ifdef MODULE_START
64 if (unlikely(address >= MODULE_START && address < MODULE_END))
65 goto vmalloc_fault;
66#endif
63 67
64 /* 68 /*
65 * If we're in an interrupt or have no user 69 * If we're in an interrupt or have no user
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 2de4d3c367a2..9e29ba9205f0 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -90,9 +90,9 @@ unsigned long setup_zero_pages(void)
90 if (!empty_zero_page) 90 if (!empty_zero_page)
91 panic("Oh boy, that early out of memory?"); 91 panic("Oh boy, that early out of memory?");
92 92
93 page = virt_to_page(empty_zero_page); 93 page = virt_to_page((void *)empty_zero_page);
94 split_page(page, order); 94 split_page(page, order);
95 while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) { 95 while (page < virt_to_page((void *)(empty_zero_page + (PAGE_SIZE << order)))) {
96 SetPageReserved(page); 96 SetPageReserved(page);
97 page++; 97 page++;
98 } 98 }
@@ -443,15 +443,18 @@ void __init mem_init(void)
443} 443}
444#endif /* !CONFIG_NEED_MULTIPLE_NODES */ 444#endif /* !CONFIG_NEED_MULTIPLE_NODES */
445 445
446void free_init_pages(char *what, unsigned long begin, unsigned long end) 446static void free_init_pages(char *what, unsigned long begin, unsigned long end)
447{ 447{
448 unsigned long addr; 448 unsigned long pfn;
449 449
450 for (addr = begin; addr < end; addr += PAGE_SIZE) { 450 for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
451 ClearPageReserved(virt_to_page(addr)); 451 struct page *page = pfn_to_page(pfn);
452 init_page_count(virt_to_page(addr)); 452 void *addr = phys_to_virt(PFN_PHYS(pfn));
453 memset((void *)addr, 0xcc, PAGE_SIZE); 453
454 free_page(addr); 454 ClearPageReserved(page);
455 init_page_count(page);
456 memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
457 __free_page(page);
455 totalram_pages++; 458 totalram_pages++;
456 } 459 }
457 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10); 460 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
@@ -460,12 +463,9 @@ void free_init_pages(char *what, unsigned long begin, unsigned long end)
460#ifdef CONFIG_BLK_DEV_INITRD 463#ifdef CONFIG_BLK_DEV_INITRD
461void free_initrd_mem(unsigned long start, unsigned long end) 464void free_initrd_mem(unsigned long start, unsigned long end)
462{ 465{
463#ifdef CONFIG_64BIT 466 free_init_pages("initrd memory",
464 /* Switch from KSEG0 to XKPHYS addresses */ 467 virt_to_phys((void *)start),
465 start = (unsigned long)phys_to_virt(CPHYSADDR(start)); 468 virt_to_phys((void *)end));
466 end = (unsigned long)phys_to_virt(CPHYSADDR(end));
467#endif
468 free_init_pages("initrd memory", start, end);
469} 469}
470#endif 470#endif
471 471
@@ -473,17 +473,13 @@ extern unsigned long prom_free_prom_memory(void);
473 473
474void free_initmem(void) 474void free_initmem(void)
475{ 475{
476 unsigned long start, end, freed; 476 unsigned long freed;
477 477
478 freed = prom_free_prom_memory(); 478 freed = prom_free_prom_memory();
479 if (freed) 479 if (freed)
480 printk(KERN_INFO "Freeing firmware memory: %ldk freed\n",freed); 480 printk(KERN_INFO "Freeing firmware memory: %ldk freed\n",freed);
481 481
482 start = (unsigned long)(&__init_begin); 482 free_init_pages("unused kernel memory",
483 end = (unsigned long)(&__init_end); 483 __pa_symbol(&__init_begin),
484#ifdef CONFIG_64BIT 484 __pa_symbol(&__init_end));
485 start = PAGE_OFFSET | CPHYSADDR(start);
486 end = PAGE_OFFSET | CPHYSADDR(end);
487#endif
488 free_init_pages("unused kernel memory", start, end);
489} 485}
diff --git a/arch/mips/mm/pgtable-64.c b/arch/mips/mm/pgtable-64.c
index 8d600d307d5d..c46eb651bf09 100644
--- a/arch/mips/mm/pgtable-64.c
+++ b/arch/mips/mm/pgtable-64.c
@@ -58,6 +58,9 @@ void __init pagetable_init(void)
58 58
59 /* Initialize the entire pgd. */ 59 /* Initialize the entire pgd. */
60 pgd_init((unsigned long)swapper_pg_dir); 60 pgd_init((unsigned long)swapper_pg_dir);
61#ifdef MODULE_START
62 pgd_init((unsigned long)module_pg_dir);
63#endif
61 pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table); 64 pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table);
62 65
63 pgd_base = swapper_pg_dir; 66 pgd_base = swapper_pg_dir;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index fec318a1c8c5..492c518e7ba5 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -423,6 +423,9 @@ enum label_id {
423 label_invalid, 423 label_invalid,
424 label_second_part, 424 label_second_part,
425 label_leave, 425 label_leave,
426#ifdef MODULE_START
427 label_module_alloc,
428#endif
426 label_vmalloc, 429 label_vmalloc,
427 label_vmalloc_done, 430 label_vmalloc_done,
428 label_tlbw_hazard, 431 label_tlbw_hazard,
@@ -455,6 +458,9 @@ static __init void build_label(struct label **lab, u32 *addr,
455 458
456L_LA(_second_part) 459L_LA(_second_part)
457L_LA(_leave) 460L_LA(_leave)
461#ifdef MODULE_START
462L_LA(_module_alloc)
463#endif
458L_LA(_vmalloc) 464L_LA(_vmalloc)
459L_LA(_vmalloc_done) 465L_LA(_vmalloc_done)
460L_LA(_tlbw_hazard) 466L_LA(_tlbw_hazard)
@@ -686,6 +692,13 @@ static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
686 i_bgezl(p, reg, 0); 692 i_bgezl(p, reg, 0);
687} 693}
688 694
695static void __init __attribute__((unused))
696il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
697{
698 r_mips_pc16(r, *p, l);
699 i_bgez(p, reg, 0);
700}
701
689/* The only general purpose registers allowed in TLB handlers. */ 702/* The only general purpose registers allowed in TLB handlers. */
690#define K0 26 703#define K0 26
691#define K1 27 704#define K1 27
@@ -970,7 +983,11 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
970 * The vmalloc handling is not in the hotpath. 983 * The vmalloc handling is not in the hotpath.
971 */ 984 */
972 i_dmfc0(p, tmp, C0_BADVADDR); 985 i_dmfc0(p, tmp, C0_BADVADDR);
986#ifdef MODULE_START
987 il_bltz(p, r, tmp, label_module_alloc);
988#else
973 il_bltz(p, r, tmp, label_vmalloc); 989 il_bltz(p, r, tmp, label_vmalloc);
990#endif
974 /* No i_nop needed here, since the next insn doesn't touch TMP. */ 991 /* No i_nop needed here, since the next insn doesn't touch TMP. */
975 992
976#ifdef CONFIG_SMP 993#ifdef CONFIG_SMP
@@ -1023,8 +1040,46 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1023{ 1040{
1024 long swpd = (long)swapper_pg_dir; 1041 long swpd = (long)swapper_pg_dir;
1025 1042
1043#ifdef MODULE_START
1044 long modd = (long)module_pg_dir;
1045
1046 l_module_alloc(l, *p);
1047 /*
1048 * Assumption:
1049 * VMALLOC_START >= 0xc000000000000000UL
1050 * MODULE_START >= 0xe000000000000000UL
1051 */
1052 i_SLL(p, ptr, bvaddr, 2);
1053 il_bgez(p, r, ptr, label_vmalloc);
1054
1055 if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START)) {
1056 i_lui(p, ptr, rel_hi(MODULE_START)); /* delay slot */
1057 } else {
1058 /* unlikely configuration */
1059 i_nop(p); /* delay slot */
1060 i_LA(p, ptr, MODULE_START);
1061 }
1062 i_dsubu(p, bvaddr, bvaddr, ptr);
1063
1064 if (in_compat_space_p(modd) && !rel_lo(modd)) {
1065 il_b(p, r, label_vmalloc_done);
1066 i_lui(p, ptr, rel_hi(modd));
1067 } else {
1068 i_LA_mostly(p, ptr, modd);
1069 il_b(p, r, label_vmalloc_done);
1070 i_daddiu(p, ptr, ptr, rel_lo(modd));
1071 }
1072
1073 l_vmalloc(l, *p);
1074 if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START) &&
1075 MODULE_START << 32 == VMALLOC_START)
1076 i_dsll32(p, ptr, ptr, 0); /* typical case */
1077 else
1078 i_LA(p, ptr, VMALLOC_START);
1079#else
1026 l_vmalloc(l, *p); 1080 l_vmalloc(l, *p);
1027 i_LA(p, ptr, VMALLOC_START); 1081 i_LA(p, ptr, VMALLOC_START);
1082#endif
1028 i_dsubu(p, bvaddr, bvaddr, ptr); 1083 i_dsubu(p, bvaddr, bvaddr, ptr);
1029 1084
1030 if (in_compat_space_p(swpd) && !rel_lo(swpd)) { 1085 if (in_compat_space_p(swpd) && !rel_lo(swpd)) {
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
index 47e3fa32b075..e5a4a0a8a7f0 100644
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -66,39 +66,6 @@ static inline void unmask_cpci_irq(unsigned int irq)
66} 66}
67 67
68/* 68/*
69 * Enables the IRQ in the FPGA
70 */
71static void enable_cpci_irq(unsigned int irq)
72{
73 unmask_cpci_irq(irq);
74}
75
76/*
77 * Initialize the IRQ in the FPGA
78 */
79static unsigned int startup_cpci_irq(unsigned int irq)
80{
81 unmask_cpci_irq(irq);
82 return 0;
83}
84
85/*
86 * Disables the IRQ in the FPGA
87 */
88static void disable_cpci_irq(unsigned int irq)
89{
90 mask_cpci_irq(irq);
91}
92
93/*
94 * Masks and ACKs an IRQ
95 */
96static void mask_and_ack_cpci_irq(unsigned int irq)
97{
98 mask_cpci_irq(irq);
99}
100
101/*
102 * End IRQ processing 69 * End IRQ processing
103 */ 70 */
104static void end_cpci_irq(unsigned int irq) 71static void end_cpci_irq(unsigned int irq)
@@ -125,15 +92,12 @@ void ll_cpci_irq(void)
125 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE); 92 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE);
126} 93}
127 94
128#define shutdown_cpci_irq disable_cpci_irq
129
130struct irq_chip cpci_irq_type = { 95struct irq_chip cpci_irq_type = {
131 .typename = "CPCI/FPGA", 96 .typename = "CPCI/FPGA",
132 .startup = startup_cpci_irq, 97 .ack = mask_cpci_irq,
133 .shutdown = shutdown_cpci_irq, 98 .mask = mask_cpci_irq,
134 .enable = enable_cpci_irq, 99 .mask_ack = mask_cpci_irq,
135 .disable = disable_cpci_irq, 100 .unmask = unmask_cpci_irq,
136 .ack = mask_and_ack_cpci_irq,
137 .end = end_cpci_irq, 101 .end = end_cpci_irq,
138}; 102};
139 103
@@ -141,11 +105,6 @@ void cpci_irq_init(void)
141{ 105{
142 int i; 106 int i;
143 107
144 /* Reset irq handlers pointers to NULL */ 108 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++)
145 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) { 109 set_irq_chip_and_handler(i, &cpci_irq_type, handle_level_irq);
146 irq_desc[i].status = IRQ_DISABLED;
147 irq_desc[i].action = 0;
148 irq_desc[i].depth = 2;
149 irq_desc[i].chip = &cpci_irq_type;
150 }
151} 110}
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
index 510257dc205a..0029f0008dea 100644
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -60,39 +60,6 @@ static inline void unmask_uart_irq(unsigned int irq)
60} 60}
61 61
62/* 62/*
63 * Enables the IRQ in the FPGA
64 */
65static void enable_uart_irq(unsigned int irq)
66{
67 unmask_uart_irq(irq);
68}
69
70/*
71 * Initialize the IRQ in the FPGA
72 */
73static unsigned int startup_uart_irq(unsigned int irq)
74{
75 unmask_uart_irq(irq);
76 return 0;
77}
78
79/*
80 * Disables the IRQ in the FPGA
81 */
82static void disable_uart_irq(unsigned int irq)
83{
84 mask_uart_irq(irq);
85}
86
87/*
88 * Masks and ACKs an IRQ
89 */
90static void mask_and_ack_uart_irq(unsigned int irq)
91{
92 mask_uart_irq(irq);
93}
94
95/*
96 * End IRQ processing 63 * End IRQ processing
97 */ 64 */
98static void end_uart_irq(unsigned int irq) 65static void end_uart_irq(unsigned int irq)
@@ -118,28 +85,17 @@ void ll_uart_irq(void)
118 do_IRQ(ls1bit8(irq_src) + 74); 85 do_IRQ(ls1bit8(irq_src) + 74);
119} 86}
120 87
121#define shutdown_uart_irq disable_uart_irq
122
123struct irq_chip uart_irq_type = { 88struct irq_chip uart_irq_type = {
124 .typename = "UART/FPGA", 89 .typename = "UART/FPGA",
125 .startup = startup_uart_irq, 90 .ack = mask_uart_irq,
126 .shutdown = shutdown_uart_irq, 91 .mask = mask_uart_irq,
127 .enable = enable_uart_irq, 92 .mask_ack = mask_uart_irq,
128 .disable = disable_uart_irq, 93 .unmask = unmask_uart_irq,
129 .ack = mask_and_ack_uart_irq,
130 .end = end_uart_irq, 94 .end = end_uart_irq,
131}; 95};
132 96
133void uart_irq_init(void) 97void uart_irq_init(void)
134{ 98{
135 /* Reset irq handlers pointers to NULL */ 99 set_irq_chip_and_handler(80, &uart_irq_type, handle_level_irq);
136 irq_desc[80].status = IRQ_DISABLED; 100 set_irq_chip_and_handler(81, &uart_irq_type, handle_level_irq);
137 irq_desc[80].action = 0;
138 irq_desc[80].depth = 2;
139 irq_desc[80].chip = &uart_irq_type;
140
141 irq_desc[81].status = IRQ_DISABLED;
142 irq_desc[81].action = 0;
143 irq_desc[81].depth = 2;
144 irq_desc[81].chip = &uart_irq_type;
145} 101}
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 0a50aad5bbe4..bf3be6fcf7ff 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -12,5 +12,6 @@ oprofile-y := $(DRIVER_OBJS) common.o
12 12
13oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o 13oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o
14oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o 14oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o
15oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o
15oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o 16oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o
16oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o 17oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 65eb55400d77..4e0a90b3916b 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -83,6 +83,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
83 case CPU_74K: 83 case CPU_74K:
84 case CPU_SB1: 84 case CPU_SB1:
85 case CPU_SB1A: 85 case CPU_SB1A:
86 case CPU_R10000:
87 case CPU_R12000:
88 case CPU_R14000:
86 lmodel = &op_model_mipsxx_ops; 89 lmodel = &op_model_mipsxx_ops;
87 break; 90 break;
88 91
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 1fb240c57bac..455d76ad06d8 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -18,7 +18,7 @@
18#define M_PERFCTL_SUPERVISOR (1UL << 2) 18#define M_PERFCTL_SUPERVISOR (1UL << 2)
19#define M_PERFCTL_USER (1UL << 3) 19#define M_PERFCTL_USER (1UL << 3)
20#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) 20#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
21#define M_PERFCTL_EVENT(event) ((event) << 5) 21#define M_PERFCTL_EVENT(event) (((event) & 0x3f) << 5)
22#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) 22#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
23#define M_PERFCTL_MT_EN(filter) ((filter) << 20) 23#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
24#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) 24#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
@@ -218,13 +218,23 @@ static inline int __n_counters(void)
218 218
219static inline int n_counters(void) 219static inline int n_counters(void)
220{ 220{
221 int counters = __n_counters(); 221 int counters;
222
223 switch (current_cpu_data.cputype) {
224 case CPU_R10000:
225 counters = 2;
226
227 case CPU_R12000:
228 case CPU_R14000:
229 counters = 4;
230
231 default:
232 counters = __n_counters();
233 }
222 234
223#ifdef CONFIG_MIPS_MT_SMP 235#ifdef CONFIG_MIPS_MT_SMP
224 if (current_cpu_data.cputype == CPU_34K) 236 counters >> 1;
225 return counters >> 1;
226#endif 237#endif
227
228 return counters; 238 return counters;
229} 239}
230 240
@@ -284,6 +294,18 @@ static int __init mipsxx_init(void)
284 op_model_mipsxx_ops.cpu_type = "mips/5K"; 294 op_model_mipsxx_ops.cpu_type = "mips/5K";
285 break; 295 break;
286 296
297 case CPU_R10000:
298 if ((current_cpu_data.processor_id & 0xff) == 0x20)
299 op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
300 else
301 op_model_mipsxx_ops.cpu_type = "mips/r10000";
302 break;
303
304 case CPU_R12000:
305 case CPU_R14000:
306 op_model_mipsxx_ops.cpu_type = "mips/r12000";
307 break;
308
287 case CPU_SB1: 309 case CPU_SB1:
288 case CPU_SB1A: 310 case CPU_SB1A:
289 op_model_mipsxx_ops.cpu_type = "mips/sb1"; 311 op_model_mipsxx_ops.cpu_type = "mips/sb1";
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 75a01e764898..7d5f6bbf7a9d 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -94,22 +94,21 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
94#if 0 94#if 0
95 if (galileo_id >= 0x10) { 95 if (galileo_id >= 0x10) {
96 /* New Galileo, assumes PCI stop line to VIA is connected. */ 96 /* New Galileo, assumes PCI stop line to VIA is connected. */
97 GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS); 97 GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
98 } else if (galileo_id == 0x1 || galileo_id == 0x2) 98 } else if (galileo_id == 0x1 || galileo_id == 0x2)
99#endif 99#endif
100 { 100 {
101 signed int timeo; 101 signed int timeo;
102 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ 102 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
103 timeo = GALILEO_INL(GT_PCI0_TOR_OFS); 103 timeo = GT_READ(GT_PCI0_TOR_OFS);
104 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ 104 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
105 GALILEO_OUTL( 105 GT_WRITE(GT_PCI0_TOR_OFS,
106 (0xff << 16) | /* retry count */ 106 (0xff << 16) | /* retry count */
107 (0xff << 8) | /* timeout 1 */ 107 (0xff << 8) | /* timeout 1 */
108 0xff, /* timeout 0 */ 108 0xff); /* timeout 0 */
109 GT_PCI0_TOR_OFS);
110 109
111 /* enable PCI retry exceeded interrupt */ 110 /* enable PCI retry exceeded interrupt */
112 GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); 111 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
113 } 112 }
114} 113}
115 114
diff --git a/arch/mips/pci/ops-gt64111.c b/arch/mips/pci/ops-gt64111.c
index 13de45940b19..ecd3991bd0e4 100644
--- a/arch/mips/pci/ops-gt64111.c
+++ b/arch/mips/pci/ops-gt64111.c
@@ -38,18 +38,18 @@ static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
38 switch (size) { 38 switch (size) {
39 case 4: 39 case 4:
40 PCI_CFG_SET(devfn, where); 40 PCI_CFG_SET(devfn, where);
41 *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 41 *val = GT_READ(GT_PCI0_CFGDATA_OFS);
42 return PCIBIOS_SUCCESSFUL; 42 return PCIBIOS_SUCCESSFUL;
43 43
44 case 2: 44 case 2:
45 PCI_CFG_SET(devfn, (where & ~0x3)); 45 PCI_CFG_SET(devfn, (where & ~0x3));
46 *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) 46 *val = GT_READ(GT_PCI0_CFGDATA_OFS)
47 >> ((where & 3) * 8); 47 >> ((where & 3) * 8);
48 return PCIBIOS_SUCCESSFUL; 48 return PCIBIOS_SUCCESSFUL;
49 49
50 case 1: 50 case 1:
51 PCI_CFG_SET(devfn, (where & ~0x3)); 51 PCI_CFG_SET(devfn, (where & ~0x3));
52 *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) 52 *val = GT_READ(GT_PCI0_CFGDATA_OFS)
53 >> ((where & 3) * 8); 53 >> ((where & 3) * 8);
54 return PCIBIOS_SUCCESSFUL; 54 return PCIBIOS_SUCCESSFUL;
55 } 55 }
@@ -68,25 +68,25 @@ static int gt64111_pci_write_config(struct pci_bus *bus, unsigned int devfn,
68 switch (size) { 68 switch (size) {
69 case 4: 69 case 4:
70 PCI_CFG_SET(devfn, where); 70 PCI_CFG_SET(devfn, where);
71 GALILEO_OUTL(val, GT_PCI0_CFGDATA_OFS); 71 GT_WRITE(GT_PCI0_CFGDATA_OFS, val);
72 72
73 return PCIBIOS_SUCCESSFUL; 73 return PCIBIOS_SUCCESSFUL;
74 74
75 case 2: 75 case 2:
76 PCI_CFG_SET(devfn, (where & ~0x3)); 76 PCI_CFG_SET(devfn, (where & ~0x3));
77 tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 77 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
78 tmp &= ~(0xffff << ((where & 0x3) * 8)); 78 tmp &= ~(0xffff << ((where & 0x3) * 8));
79 tmp |= (val << ((where & 0x3) * 8)); 79 tmp |= (val << ((where & 0x3) * 8));
80 GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS); 80 GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
81 81
82 return PCIBIOS_SUCCESSFUL; 82 return PCIBIOS_SUCCESSFUL;
83 83
84 case 1: 84 case 1:
85 PCI_CFG_SET(devfn, (where & ~0x3)); 85 PCI_CFG_SET(devfn, (where & ~0x3));
86 tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 86 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
87 tmp &= ~(0xff << ((where & 0x3) * 8)); 87 tmp &= ~(0xff << ((where & 0x3) * 8));
88 tmp |= (val << ((where & 0x3) * 8)); 88 tmp |= (val << ((where & 0x3) * 8));
89 GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS); 89 GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
90 90
91 return PCIBIOS_SUCCESSFUL; 91 return PCIBIOS_SUCCESSFUL;
92 } 92 }
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index 710611615ca2..0dc23930edbd 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -38,8 +38,6 @@
38#include <int.h> 38#include <int.h>
39#include <uart.h> 39#include <uart.h>
40 40
41static DEFINE_SPINLOCK(irq_lock);
42
43/* default prio for interrupts */ 41/* default prio for interrupts */
44/* first one is a no-no so therefore always prio 0 (disabled) */ 42/* first one is a no-no so therefore always prio 0 (disabled) */
45static char gic_prio[PNX8550_INT_GIC_TOTINT] = { 43static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
@@ -149,38 +147,6 @@ static inline void unmask_irq(unsigned int irq_nr)
149 } 147 }
150} 148}
151 149
152#define pnx8550_disable pnx8550_ack
153static void pnx8550_ack(unsigned int irq)
154{
155 unsigned long flags;
156
157 spin_lock_irqsave(&irq_lock, flags);
158 mask_irq(irq);
159 spin_unlock_irqrestore(&irq_lock, flags);
160}
161
162#define pnx8550_enable pnx8550_unmask
163static void pnx8550_unmask(unsigned int irq)
164{
165 unsigned long flags;
166
167 spin_lock_irqsave(&irq_lock, flags);
168 unmask_irq(irq);
169 spin_unlock_irqrestore(&irq_lock, flags);
170}
171
172static unsigned int startup_irq(unsigned int irq_nr)
173{
174 pnx8550_unmask(irq_nr);
175 return 0;
176}
177
178static void shutdown_irq(unsigned int irq_nr)
179{
180 pnx8550_ack(irq_nr);
181 return;
182}
183
184int pnx8550_set_gic_priority(int irq, int priority) 150int pnx8550_set_gic_priority(int irq, int priority)
185{ 151{
186 int gic_irq = irq-PNX8550_INT_GIC_MIN; 152 int gic_irq = irq-PNX8550_INT_GIC_MIN;
@@ -192,26 +158,19 @@ int pnx8550_set_gic_priority(int irq, int priority)
192 return prev_priority; 158 return prev_priority;
193} 159}
194 160
195static inline void mask_and_ack_level_irq(unsigned int irq)
196{
197 pnx8550_disable(irq);
198 return;
199}
200
201static void end_irq(unsigned int irq) 161static void end_irq(unsigned int irq)
202{ 162{
203 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { 163 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
204 pnx8550_enable(irq); 164 unmask_irq(irq);
205 } 165 }
206} 166}
207 167
208static struct irq_chip level_irq_type = { 168static struct irq_chip level_irq_type = {
209 .typename = "PNX Level IRQ", 169 .typename = "PNX Level IRQ",
210 .startup = startup_irq, 170 .ack = mask_irq,
211 .shutdown = shutdown_irq, 171 .mask = mask_irq,
212 .enable = pnx8550_enable, 172 .mask_ack = mask_irq,
213 .disable = pnx8550_disable, 173 .unmask = unmask_irq,
214 .ack = mask_and_ack_level_irq,
215 .end = end_irq, 174 .end = end_irq,
216}; 175};
217 176
@@ -233,8 +192,8 @@ void __init arch_init_irq(void)
233 int configPR; 192 int configPR;
234 193
235 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { 194 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
236 irq_desc[i].chip = &level_irq_type; 195 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
237 pnx8550_ack(i); /* mask the irq just in case */ 196 mask_irq(i); /* mask the irq just in case */
238 } 197 }
239 198
240 /* init of GIC/IPC interrupts */ 199 /* init of GIC/IPC interrupts */
@@ -270,7 +229,7 @@ void __init arch_init_irq(void)
270 /* mask/priority is still 0 so we will not get any 229 /* mask/priority is still 0 so we will not get any
271 * interrupts until it is unmasked */ 230 * interrupts until it is unmasked */
272 231
273 irq_desc[i].chip = &level_irq_type; 232 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
274 } 233 }
275 234
276 /* Priority level 0 */ 235 /* Priority level 0 */
@@ -279,20 +238,21 @@ void __init arch_init_irq(void)
279 /* Set int vector table address */ 238 /* Set int vector table address */
280 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; 239 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
281 240
282 irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type; 241 set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
242 handle_level_irq);
283 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); 243 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
284 244
285 /* init of Timer interrupts */ 245 /* init of Timer interrupts */
286 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) { 246 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
287 irq_desc[i].chip = &level_irq_type; 247 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
288 }
289 248
290 /* Stop Timer 1-3 */ 249 /* Stop Timer 1-3 */
291 configPR = read_c0_config7(); 250 configPR = read_c0_config7();
292 configPR |= 0x00000038; 251 configPR |= 0x00000038;
293 write_c0_config7(configPR); 252 write_c0_config7(configPR);
294 253
295 irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type; 254 set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
255 handle_level_irq);
296 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); 256 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
297} 257}
298 258
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index 3cc0436db6cf..305491e74dbe 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -99,8 +99,6 @@ void prom_cpus_done(void)
99 */ 99 */
100void prom_init_secondary(void) 100void prom_init_secondary(void)
101{ 101{
102 mips_hpt_init();
103
104 set_c0_status(ST0_CO | ST0_IE | ST0_IM); 102 set_c0_status(ST0_CO | ST0_IE | ST0_IM);
105} 103}
106 104
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 0d18ed47c47a..a1a9af6da7bf 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -95,16 +95,11 @@ static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
95 95
96static void enable_eisa1_irq(unsigned int irq) 96static void enable_eisa1_irq(unsigned int irq)
97{ 97{
98 unsigned long flags;
99 u8 mask; 98 u8 mask;
100 99
101 local_irq_save(flags);
102
103 mask = inb(EISA_INT1_MASK); 100 mask = inb(EISA_INT1_MASK);
104 mask &= ~((u8) (1 << irq)); 101 mask &= ~((u8) (1 << irq));
105 outb(mask, EISA_INT1_MASK); 102 outb(mask, EISA_INT1_MASK);
106
107 local_irq_restore(flags);
108} 103}
109 104
110static unsigned int startup_eisa1_irq(unsigned int irq) 105static unsigned int startup_eisa1_irq(unsigned int irq)
@@ -130,8 +125,6 @@ static void disable_eisa1_irq(unsigned int irq)
130 outb(mask, EISA_INT1_MASK); 125 outb(mask, EISA_INT1_MASK);
131} 126}
132 127
133#define shutdown_eisa1_irq disable_eisa1_irq
134
135static void mask_and_ack_eisa1_irq(unsigned int irq) 128static void mask_and_ack_eisa1_irq(unsigned int irq)
136{ 129{
137 disable_eisa1_irq(irq); 130 disable_eisa1_irq(irq);
@@ -148,25 +141,20 @@ static void end_eisa1_irq(unsigned int irq)
148static struct irq_chip ip22_eisa1_irq_type = { 141static struct irq_chip ip22_eisa1_irq_type = {
149 .typename = "IP22 EISA", 142 .typename = "IP22 EISA",
150 .startup = startup_eisa1_irq, 143 .startup = startup_eisa1_irq,
151 .shutdown = shutdown_eisa1_irq,
152 .enable = enable_eisa1_irq,
153 .disable = disable_eisa1_irq,
154 .ack = mask_and_ack_eisa1_irq, 144 .ack = mask_and_ack_eisa1_irq,
145 .mask = disable_eisa1_irq,
146 .mask_ack = mask_and_ack_eisa1_irq,
147 .unmask = enable_eisa1_irq,
155 .end = end_eisa1_irq, 148 .end = end_eisa1_irq,
156}; 149};
157 150
158static void enable_eisa2_irq(unsigned int irq) 151static void enable_eisa2_irq(unsigned int irq)
159{ 152{
160 unsigned long flags;
161 u8 mask; 153 u8 mask;
162 154
163 local_irq_save(flags);
164
165 mask = inb(EISA_INT2_MASK); 155 mask = inb(EISA_INT2_MASK);
166 mask &= ~((u8) (1 << (irq - 8))); 156 mask &= ~((u8) (1 << (irq - 8)));
167 outb(mask, EISA_INT2_MASK); 157 outb(mask, EISA_INT2_MASK);
168
169 local_irq_restore(flags);
170} 158}
171 159
172static unsigned int startup_eisa2_irq(unsigned int irq) 160static unsigned int startup_eisa2_irq(unsigned int irq)
@@ -192,8 +180,6 @@ static void disable_eisa2_irq(unsigned int irq)
192 outb(mask, EISA_INT2_MASK); 180 outb(mask, EISA_INT2_MASK);
193} 181}
194 182
195#define shutdown_eisa2_irq disable_eisa2_irq
196
197static void mask_and_ack_eisa2_irq(unsigned int irq) 183static void mask_and_ack_eisa2_irq(unsigned int irq)
198{ 184{
199 disable_eisa2_irq(irq); 185 disable_eisa2_irq(irq);
@@ -210,10 +196,10 @@ static void end_eisa2_irq(unsigned int irq)
210static struct irq_chip ip22_eisa2_irq_type = { 196static struct irq_chip ip22_eisa2_irq_type = {
211 .typename = "IP22 EISA", 197 .typename = "IP22 EISA",
212 .startup = startup_eisa2_irq, 198 .startup = startup_eisa2_irq,
213 .shutdown = shutdown_eisa2_irq,
214 .enable = enable_eisa2_irq,
215 .disable = disable_eisa2_irq,
216 .ack = mask_and_ack_eisa2_irq, 199 .ack = mask_and_ack_eisa2_irq,
200 .mask = disable_eisa2_irq,
201 .mask_ack = mask_and_ack_eisa2_irq,
202 .unmask = enable_eisa2_irq,
217 .end = end_eisa2_irq, 203 .end = end_eisa2_irq,
218}; 204};
219 205
@@ -275,13 +261,10 @@ int __init ip22_eisa_init(void)
275 outb(0, EISA_DMA2_WRITE_SINGLE); 261 outb(0, EISA_DMA2_WRITE_SINGLE);
276 262
277 for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) { 263 for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
278 irq_desc[i].status = IRQ_DISABLED;
279 irq_desc[i].action = 0;
280 irq_desc[i].depth = 1;
281 if (i < (SGINT_EISA + 8)) 264 if (i < (SGINT_EISA + 8))
282 irq_desc[i].chip = &ip22_eisa1_irq_type; 265 set_irq_chip(i, &ip22_eisa1_irq_type);
283 else 266 else
284 irq_desc[i].chip = &ip22_eisa2_irq_type; 267 set_irq_chip(i, &ip22_eisa2_irq_type);
285 } 268 }
286 269
287 /* Cannot use request_irq because of kmalloc not being ready at such 270 /* Cannot use request_irq because of kmalloc not being ready at such
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index af518898eaa1..c7b138053159 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -40,34 +40,17 @@ extern int ip22_eisa_init(void);
40 40
41static void enable_local0_irq(unsigned int irq) 41static void enable_local0_irq(unsigned int irq)
42{ 42{
43 unsigned long flags;
44
45 local_irq_save(flags);
46 /* don't allow mappable interrupt to be enabled from setup_irq, 43 /* don't allow mappable interrupt to be enabled from setup_irq,
47 * we have our own way to do so */ 44 * we have our own way to do so */
48 if (irq != SGI_MAP_0_IRQ) 45 if (irq != SGI_MAP_0_IRQ)
49 sgint->imask0 |= (1 << (irq - SGINT_LOCAL0)); 46 sgint->imask0 |= (1 << (irq - SGINT_LOCAL0));
50 local_irq_restore(flags);
51}
52
53static unsigned int startup_local0_irq(unsigned int irq)
54{
55 enable_local0_irq(irq);
56 return 0; /* Never anything pending */
57} 47}
58 48
59static void disable_local0_irq(unsigned int irq) 49static void disable_local0_irq(unsigned int irq)
60{ 50{
61 unsigned long flags;
62
63 local_irq_save(flags);
64 sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0)); 51 sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
65 local_irq_restore(flags);
66} 52}
67 53
68#define shutdown_local0_irq disable_local0_irq
69#define mask_and_ack_local0_irq disable_local0_irq
70
71static void end_local0_irq (unsigned int irq) 54static void end_local0_irq (unsigned int irq)
72{ 55{
73 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 56 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -76,44 +59,26 @@ static void end_local0_irq (unsigned int irq)
76 59
77static struct irq_chip ip22_local0_irq_type = { 60static struct irq_chip ip22_local0_irq_type = {
78 .typename = "IP22 local 0", 61 .typename = "IP22 local 0",
79 .startup = startup_local0_irq, 62 .ack = disable_local0_irq,
80 .shutdown = shutdown_local0_irq, 63 .mask = disable_local0_irq,
81 .enable = enable_local0_irq, 64 .mask_ack = disable_local0_irq,
82 .disable = disable_local0_irq, 65 .unmask = enable_local0_irq,
83 .ack = mask_and_ack_local0_irq,
84 .end = end_local0_irq, 66 .end = end_local0_irq,
85}; 67};
86 68
87static void enable_local1_irq(unsigned int irq) 69static void enable_local1_irq(unsigned int irq)
88{ 70{
89 unsigned long flags;
90
91 local_irq_save(flags);
92 /* don't allow mappable interrupt to be enabled from setup_irq, 71 /* don't allow mappable interrupt to be enabled from setup_irq,
93 * we have our own way to do so */ 72 * we have our own way to do so */
94 if (irq != SGI_MAP_1_IRQ) 73 if (irq != SGI_MAP_1_IRQ)
95 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1)); 74 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
96 local_irq_restore(flags);
97}
98
99static unsigned int startup_local1_irq(unsigned int irq)
100{
101 enable_local1_irq(irq);
102 return 0; /* Never anything pending */
103} 75}
104 76
105void disable_local1_irq(unsigned int irq) 77void disable_local1_irq(unsigned int irq)
106{ 78{
107 unsigned long flags;
108
109 local_irq_save(flags);
110 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1)); 79 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
111 local_irq_restore(flags);
112} 80}
113 81
114#define shutdown_local1_irq disable_local1_irq
115#define mask_and_ack_local1_irq disable_local1_irq
116
117static void end_local1_irq (unsigned int irq) 82static void end_local1_irq (unsigned int irq)
118{ 83{
119 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 84 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -122,44 +87,26 @@ static void end_local1_irq (unsigned int irq)
122 87
123static struct irq_chip ip22_local1_irq_type = { 88static struct irq_chip ip22_local1_irq_type = {
124 .typename = "IP22 local 1", 89 .typename = "IP22 local 1",
125 .startup = startup_local1_irq, 90 .ack = disable_local1_irq,
126 .shutdown = shutdown_local1_irq, 91 .mask = disable_local1_irq,
127 .enable = enable_local1_irq, 92 .mask_ack = disable_local1_irq,
128 .disable = disable_local1_irq, 93 .unmask = enable_local1_irq,
129 .ack = mask_and_ack_local1_irq,
130 .end = end_local1_irq, 94 .end = end_local1_irq,
131}; 95};
132 96
133static void enable_local2_irq(unsigned int irq) 97static void enable_local2_irq(unsigned int irq)
134{ 98{
135 unsigned long flags;
136
137 local_irq_save(flags);
138 sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); 99 sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
139 sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2)); 100 sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
140 local_irq_restore(flags);
141}
142
143static unsigned int startup_local2_irq(unsigned int irq)
144{
145 enable_local2_irq(irq);
146 return 0; /* Never anything pending */
147} 101}
148 102
149void disable_local2_irq(unsigned int irq) 103void disable_local2_irq(unsigned int irq)
150{ 104{
151 unsigned long flags;
152
153 local_irq_save(flags);
154 sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2)); 105 sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
155 if (!sgint->cmeimask0) 106 if (!sgint->cmeimask0)
156 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); 107 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
157 local_irq_restore(flags);
158} 108}
159 109
160#define shutdown_local2_irq disable_local2_irq
161#define mask_and_ack_local2_irq disable_local2_irq
162
163static void end_local2_irq (unsigned int irq) 110static void end_local2_irq (unsigned int irq)
164{ 111{
165 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 112 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -168,44 +115,26 @@ static void end_local2_irq (unsigned int irq)
168 115
169static struct irq_chip ip22_local2_irq_type = { 116static struct irq_chip ip22_local2_irq_type = {
170 .typename = "IP22 local 2", 117 .typename = "IP22 local 2",
171 .startup = startup_local2_irq, 118 .ack = disable_local2_irq,
172 .shutdown = shutdown_local2_irq, 119 .mask = disable_local2_irq,
173 .enable = enable_local2_irq, 120 .mask_ack = disable_local2_irq,
174 .disable = disable_local2_irq, 121 .unmask = enable_local2_irq,
175 .ack = mask_and_ack_local2_irq,
176 .end = end_local2_irq, 122 .end = end_local2_irq,
177}; 123};
178 124
179static void enable_local3_irq(unsigned int irq) 125static void enable_local3_irq(unsigned int irq)
180{ 126{
181 unsigned long flags;
182
183 local_irq_save(flags);
184 sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); 127 sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
185 sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3)); 128 sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
186 local_irq_restore(flags);
187}
188
189static unsigned int startup_local3_irq(unsigned int irq)
190{
191 enable_local3_irq(irq);
192 return 0; /* Never anything pending */
193} 129}
194 130
195void disable_local3_irq(unsigned int irq) 131void disable_local3_irq(unsigned int irq)
196{ 132{
197 unsigned long flags;
198
199 local_irq_save(flags);
200 sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3)); 133 sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
201 if (!sgint->cmeimask1) 134 if (!sgint->cmeimask1)
202 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); 135 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
203 local_irq_restore(flags);
204} 136}
205 137
206#define shutdown_local3_irq disable_local3_irq
207#define mask_and_ack_local3_irq disable_local3_irq
208
209static void end_local3_irq (unsigned int irq) 138static void end_local3_irq (unsigned int irq)
210{ 139{
211 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 140 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -214,11 +143,10 @@ static void end_local3_irq (unsigned int irq)
214 143
215static struct irq_chip ip22_local3_irq_type = { 144static struct irq_chip ip22_local3_irq_type = {
216 .typename = "IP22 local 3", 145 .typename = "IP22 local 3",
217 .startup = startup_local3_irq, 146 .ack = disable_local3_irq,
218 .shutdown = shutdown_local3_irq, 147 .mask = disable_local3_irq,
219 .enable = enable_local3_irq, 148 .mask_ack = disable_local3_irq,
220 .disable = disable_local3_irq, 149 .unmask = enable_local3_irq,
221 .ack = mask_and_ack_local3_irq,
222 .end = end_local3_irq, 150 .end = end_local3_irq,
223}; 151};
224 152
@@ -430,10 +358,7 @@ void __init arch_init_irq(void)
430 else 358 else
431 handler = &ip22_local3_irq_type; 359 handler = &ip22_local3_irq_type;
432 360
433 irq_desc[i].status = IRQ_DISABLED; 361 set_irq_chip_and_handler(i, handler, handle_level_irq);
434 irq_desc[i].action = 0;
435 irq_desc[i].depth = 1;
436 irq_desc[i].chip = handler;
437 } 362 }
438 363
439 /* vector handler. this register the IRQ as non-sharable */ 364 /* vector handler. this register the IRQ as non-sharable */
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 270ecd3e6b4a..5f8835b4e84a 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -332,11 +332,6 @@ static inline void disable_bridge_irq(unsigned int irq)
332 intr_disconnect_level(cpu, swlevel); 332 intr_disconnect_level(cpu, swlevel);
333} 333}
334 334
335static void mask_and_ack_bridge_irq(unsigned int irq)
336{
337 disable_bridge_irq(irq);
338}
339
340static void end_bridge_irq(unsigned int irq) 335static void end_bridge_irq(unsigned int irq)
341{ 336{
342 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) && 337 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
@@ -348,18 +343,16 @@ static struct irq_chip bridge_irq_type = {
348 .typename = "bridge", 343 .typename = "bridge",
349 .startup = startup_bridge_irq, 344 .startup = startup_bridge_irq,
350 .shutdown = shutdown_bridge_irq, 345 .shutdown = shutdown_bridge_irq,
351 .enable = enable_bridge_irq, 346 .ack = disable_bridge_irq,
352 .disable = disable_bridge_irq, 347 .mask = disable_bridge_irq,
353 .ack = mask_and_ack_bridge_irq, 348 .mask_ack = disable_bridge_irq,
349 .unmask = enable_bridge_irq,
354 .end = end_bridge_irq, 350 .end = end_bridge_irq,
355}; 351};
356 352
357void __devinit register_bridge_irq(unsigned int irq) 353void __devinit register_bridge_irq(unsigned int irq)
358{ 354{
359 irq_desc[irq].status = IRQ_DISABLED; 355 set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
360 irq_desc[irq].action = 0;
361 irq_desc[irq].depth = 1;
362 irq_desc[irq].chip = &bridge_irq_type;
363} 356}
364 357
365int __devinit request_bridge_irq(struct bridge_controller *bc) 358int __devinit request_bridge_irq(struct bridge_controller *bc)
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 5e82a268e3c9..7d361726bbfb 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -172,15 +172,6 @@ static __init unsigned long get_m48t35_time(void)
172 return mktime(year, month, date, hour, min, sec); 172 return mktime(year, month, date, hour, min, sec);
173} 173}
174 174
175static unsigned int startup_rt_irq(unsigned int irq)
176{
177 return 0;
178}
179
180static void shutdown_rt_irq(unsigned int irq)
181{
182}
183
184static void enable_rt_irq(unsigned int irq) 175static void enable_rt_irq(unsigned int irq)
185{ 176{
186} 177}
@@ -189,21 +180,17 @@ static void disable_rt_irq(unsigned int irq)
189{ 180{
190} 181}
191 182
192static void mask_and_ack_rt(unsigned int irq)
193{
194}
195
196static void end_rt_irq(unsigned int irq) 183static void end_rt_irq(unsigned int irq)
197{ 184{
198} 185}
199 186
200static struct irq_chip rt_irq_type = { 187static struct irq_chip rt_irq_type = {
201 .typename = "SN HUB RT timer", 188 .typename = "SN HUB RT timer",
202 .startup = startup_rt_irq, 189 .ack = disable_rt_irq,
203 .shutdown = shutdown_rt_irq, 190 .mask = disable_rt_irq,
204 .enable = enable_rt_irq, 191 .mask_ack = disable_rt_irq,
205 .disable = disable_rt_irq, 192 .unmask = enable_rt_irq,
206 .ack = mask_and_ack_rt, 193 .eoi = enable_rt_irq,
207 .end = end_rt_irq, 194 .end = end_rt_irq,
208}; 195};
209 196
@@ -221,10 +208,7 @@ void __init plat_timer_setup(struct irqaction *irq)
221 if (irqno < 0) 208 if (irqno < 0)
222 panic("Can't allocate interrupt number for timer interrupt"); 209 panic("Can't allocate interrupt number for timer interrupt");
223 210
224 irq_desc[irqno].status = IRQ_DISABLED; 211 set_irq_chip_and_handler(irqno, &rt_irq_type, handle_percpu_irq);
225 irq_desc[irqno].action = NULL;
226 irq_desc[irqno].depth = 1;
227 irq_desc[irqno].chip = &rt_irq_type;
228 212
229 /* over-write the handler, we use our own way */ 213 /* over-write the handler, we use our own way */
230 irq->handler = no_action; 214 irq->handler = no_action;
@@ -239,14 +223,14 @@ void __init plat_timer_setup(struct irqaction *irq)
239 setup_irq(irqno, &rt_irqaction); 223 setup_irq(irqno, &rt_irqaction);
240} 224}
241 225
242static unsigned int ip27_hpt_read(void) 226static cycle_t ip27_hpt_read(void)
243{ 227{
244 return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT); 228 return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT);
245} 229}
246 230
247void __init ip27_time_init(void) 231void __init ip27_time_init(void)
248{ 232{
249 mips_hpt_read = ip27_hpt_read; 233 clocksource_mips.read = ip27_hpt_read;
250 mips_hpt_frequency = CYCLES_PER_SEC; 234 mips_hpt_frequency = CYCLES_PER_SEC;
251 xtime.tv_sec = get_m48t35_time(); 235 xtime.tv_sec = get_m48t35_time();
252 xtime.tv_nsec = 0; 236 xtime.tv_nsec = 0;
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index c9acadd0846b..ae063864c026 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -113,12 +113,6 @@ static void inline flush_mace_bus(void)
113 * is quite different anyway. 113 * is quite different anyway.
114 */ 114 */
115 115
116/*
117 * IRQ spinlock - Ralf says not to disable CPU interrupts,
118 * and I think he knows better.
119 */
120static DEFINE_SPINLOCK(ip32_irq_lock);
121
122/* Some initial interrupts to set up */ 116/* Some initial interrupts to set up */
123extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); 117extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
124extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); 118extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
@@ -138,12 +132,6 @@ static void enable_cpu_irq(unsigned int irq)
138 set_c0_status(STATUSF_IP7); 132 set_c0_status(STATUSF_IP7);
139} 133}
140 134
141static unsigned int startup_cpu_irq(unsigned int irq)
142{
143 enable_cpu_irq(irq);
144 return 0;
145}
146
147static void disable_cpu_irq(unsigned int irq) 135static void disable_cpu_irq(unsigned int irq)
148{ 136{
149 clear_c0_status(STATUSF_IP7); 137 clear_c0_status(STATUSF_IP7);
@@ -155,16 +143,12 @@ static void end_cpu_irq(unsigned int irq)
155 enable_cpu_irq (irq); 143 enable_cpu_irq (irq);
156} 144}
157 145
158#define shutdown_cpu_irq disable_cpu_irq
159#define mask_and_ack_cpu_irq disable_cpu_irq
160
161static struct irq_chip ip32_cpu_interrupt = { 146static struct irq_chip ip32_cpu_interrupt = {
162 .typename = "IP32 CPU", 147 .typename = "IP32 CPU",
163 .startup = startup_cpu_irq, 148 .ack = disable_cpu_irq,
164 .shutdown = shutdown_cpu_irq, 149 .mask = disable_cpu_irq,
165 .enable = enable_cpu_irq, 150 .mask_ack = disable_cpu_irq,
166 .disable = disable_cpu_irq, 151 .unmask = enable_cpu_irq,
167 .ack = mask_and_ack_cpu_irq,
168 .end = end_cpu_irq, 152 .end = end_cpu_irq,
169}; 153};
170 154
@@ -177,45 +161,27 @@ static uint64_t crime_mask;
177 161
178static void enable_crime_irq(unsigned int irq) 162static void enable_crime_irq(unsigned int irq)
179{ 163{
180 unsigned long flags;
181
182 spin_lock_irqsave(&ip32_irq_lock, flags);
183 crime_mask |= 1 << (irq - 1); 164 crime_mask |= 1 << (irq - 1);
184 crime->imask = crime_mask; 165 crime->imask = crime_mask;
185 spin_unlock_irqrestore(&ip32_irq_lock, flags);
186}
187
188static unsigned int startup_crime_irq(unsigned int irq)
189{
190 enable_crime_irq(irq);
191 return 0; /* This is probably not right; we could have pending irqs */
192} 166}
193 167
194static void disable_crime_irq(unsigned int irq) 168static void disable_crime_irq(unsigned int irq)
195{ 169{
196 unsigned long flags;
197
198 spin_lock_irqsave(&ip32_irq_lock, flags);
199 crime_mask &= ~(1 << (irq - 1)); 170 crime_mask &= ~(1 << (irq - 1));
200 crime->imask = crime_mask; 171 crime->imask = crime_mask;
201 flush_crime_bus(); 172 flush_crime_bus();
202 spin_unlock_irqrestore(&ip32_irq_lock, flags);
203} 173}
204 174
205static void mask_and_ack_crime_irq(unsigned int irq) 175static void mask_and_ack_crime_irq(unsigned int irq)
206{ 176{
207 unsigned long flags;
208
209 /* Edge triggered interrupts must be cleared. */ 177 /* Edge triggered interrupts must be cleared. */
210 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ) 178 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
211 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ) 179 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
212 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) { 180 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
213 uint64_t crime_int; 181 uint64_t crime_int;
214 spin_lock_irqsave(&ip32_irq_lock, flags);
215 crime_int = crime->hard_int; 182 crime_int = crime->hard_int;
216 crime_int &= ~(1 << (irq - 1)); 183 crime_int &= ~(1 << (irq - 1));
217 crime->hard_int = crime_int; 184 crime->hard_int = crime_int;
218 spin_unlock_irqrestore(&ip32_irq_lock, flags);
219 } 185 }
220 disable_crime_irq(irq); 186 disable_crime_irq(irq);
221} 187}
@@ -226,15 +192,12 @@ static void end_crime_irq(unsigned int irq)
226 enable_crime_irq(irq); 192 enable_crime_irq(irq);
227} 193}
228 194
229#define shutdown_crime_irq disable_crime_irq
230
231static struct irq_chip ip32_crime_interrupt = { 195static struct irq_chip ip32_crime_interrupt = {
232 .typename = "IP32 CRIME", 196 .typename = "IP32 CRIME",
233 .startup = startup_crime_irq,
234 .shutdown = shutdown_crime_irq,
235 .enable = enable_crime_irq,
236 .disable = disable_crime_irq,
237 .ack = mask_and_ack_crime_irq, 197 .ack = mask_and_ack_crime_irq,
198 .mask = disable_crime_irq,
199 .mask_ack = mask_and_ack_crime_irq,
200 .unmask = enable_crime_irq,
238 .end = end_crime_irq, 201 .end = end_crime_irq,
239}; 202};
240 203
@@ -248,34 +211,20 @@ static unsigned long macepci_mask;
248 211
249static void enable_macepci_irq(unsigned int irq) 212static void enable_macepci_irq(unsigned int irq)
250{ 213{
251 unsigned long flags;
252
253 spin_lock_irqsave(&ip32_irq_lock, flags);
254 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9); 214 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
255 mace->pci.control = macepci_mask; 215 mace->pci.control = macepci_mask;
256 crime_mask |= 1 << (irq - 1); 216 crime_mask |= 1 << (irq - 1);
257 crime->imask = crime_mask; 217 crime->imask = crime_mask;
258 spin_unlock_irqrestore(&ip32_irq_lock, flags);
259}
260
261static unsigned int startup_macepci_irq(unsigned int irq)
262{
263 enable_macepci_irq (irq);
264 return 0;
265} 218}
266 219
267static void disable_macepci_irq(unsigned int irq) 220static void disable_macepci_irq(unsigned int irq)
268{ 221{
269 unsigned long flags;
270
271 spin_lock_irqsave(&ip32_irq_lock, flags);
272 crime_mask &= ~(1 << (irq - 1)); 222 crime_mask &= ~(1 << (irq - 1));
273 crime->imask = crime_mask; 223 crime->imask = crime_mask;
274 flush_crime_bus(); 224 flush_crime_bus();
275 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9); 225 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
276 mace->pci.control = macepci_mask; 226 mace->pci.control = macepci_mask;
277 flush_mace_bus(); 227 flush_mace_bus();
278 spin_unlock_irqrestore(&ip32_irq_lock, flags);
279} 228}
280 229
281static void end_macepci_irq(unsigned int irq) 230static void end_macepci_irq(unsigned int irq)
@@ -284,16 +233,12 @@ static void end_macepci_irq(unsigned int irq)
284 enable_macepci_irq(irq); 233 enable_macepci_irq(irq);
285} 234}
286 235
287#define shutdown_macepci_irq disable_macepci_irq
288#define mask_and_ack_macepci_irq disable_macepci_irq
289
290static struct irq_chip ip32_macepci_interrupt = { 236static struct irq_chip ip32_macepci_interrupt = {
291 .typename = "IP32 MACE PCI", 237 .typename = "IP32 MACE PCI",
292 .startup = startup_macepci_irq, 238 .ack = disable_macepci_irq,
293 .shutdown = shutdown_macepci_irq, 239 .mask = disable_macepci_irq,
294 .enable = enable_macepci_irq, 240 .mask_ack = disable_macepci_irq,
295 .disable = disable_macepci_irq, 241 .unmask = enable_macepci_irq,
296 .ack = mask_and_ack_macepci_irq,
297 .end = end_macepci_irq, 242 .end = end_macepci_irq,
298}; 243};
299 244
@@ -339,7 +284,6 @@ static unsigned long maceisa_mask;
339static void enable_maceisa_irq (unsigned int irq) 284static void enable_maceisa_irq (unsigned int irq)
340{ 285{
341 unsigned int crime_int = 0; 286 unsigned int crime_int = 0;
342 unsigned long flags;
343 287
344 DBG ("maceisa enable: %u\n", irq); 288 DBG ("maceisa enable: %u\n", irq);
345 289
@@ -355,26 +299,16 @@ static void enable_maceisa_irq (unsigned int irq)
355 break; 299 break;
356 } 300 }
357 DBG ("crime_int %08x enabled\n", crime_int); 301 DBG ("crime_int %08x enabled\n", crime_int);
358 spin_lock_irqsave(&ip32_irq_lock, flags);
359 crime_mask |= crime_int; 302 crime_mask |= crime_int;
360 crime->imask = crime_mask; 303 crime->imask = crime_mask;
361 maceisa_mask |= 1 << (irq - 33); 304 maceisa_mask |= 1 << (irq - 33);
362 mace->perif.ctrl.imask = maceisa_mask; 305 mace->perif.ctrl.imask = maceisa_mask;
363 spin_unlock_irqrestore(&ip32_irq_lock, flags);
364}
365
366static unsigned int startup_maceisa_irq(unsigned int irq)
367{
368 enable_maceisa_irq(irq);
369 return 0;
370} 306}
371 307
372static void disable_maceisa_irq(unsigned int irq) 308static void disable_maceisa_irq(unsigned int irq)
373{ 309{
374 unsigned int crime_int = 0; 310 unsigned int crime_int = 0;
375 unsigned long flags;
376 311
377 spin_lock_irqsave(&ip32_irq_lock, flags);
378 maceisa_mask &= ~(1 << (irq - 33)); 312 maceisa_mask &= ~(1 << (irq - 33));
379 if(!(maceisa_mask & MACEISA_AUDIO_INT)) 313 if(!(maceisa_mask & MACEISA_AUDIO_INT))
380 crime_int |= MACE_AUDIO_INT; 314 crime_int |= MACE_AUDIO_INT;
@@ -387,23 +321,20 @@ static void disable_maceisa_irq(unsigned int irq)
387 flush_crime_bus(); 321 flush_crime_bus();
388 mace->perif.ctrl.imask = maceisa_mask; 322 mace->perif.ctrl.imask = maceisa_mask;
389 flush_mace_bus(); 323 flush_mace_bus();
390 spin_unlock_irqrestore(&ip32_irq_lock, flags);
391} 324}
392 325
393static void mask_and_ack_maceisa_irq(unsigned int irq) 326static void mask_and_ack_maceisa_irq(unsigned int irq)
394{ 327{
395 unsigned long mace_int, flags; 328 unsigned long mace_int;
396 329
397 switch (irq) { 330 switch (irq) {
398 case MACEISA_PARALLEL_IRQ: 331 case MACEISA_PARALLEL_IRQ:
399 case MACEISA_SERIAL1_TDMAPR_IRQ: 332 case MACEISA_SERIAL1_TDMAPR_IRQ:
400 case MACEISA_SERIAL2_TDMAPR_IRQ: 333 case MACEISA_SERIAL2_TDMAPR_IRQ:
401 /* edge triggered */ 334 /* edge triggered */
402 spin_lock_irqsave(&ip32_irq_lock, flags);
403 mace_int = mace->perif.ctrl.istat; 335 mace_int = mace->perif.ctrl.istat;
404 mace_int &= ~(1 << (irq - 33)); 336 mace_int &= ~(1 << (irq - 33));
405 mace->perif.ctrl.istat = mace_int; 337 mace->perif.ctrl.istat = mace_int;
406 spin_unlock_irqrestore(&ip32_irq_lock, flags);
407 break; 338 break;
408 } 339 }
409 disable_maceisa_irq(irq); 340 disable_maceisa_irq(irq);
@@ -415,15 +346,12 @@ static void end_maceisa_irq(unsigned irq)
415 enable_maceisa_irq(irq); 346 enable_maceisa_irq(irq);
416} 347}
417 348
418#define shutdown_maceisa_irq disable_maceisa_irq
419
420static struct irq_chip ip32_maceisa_interrupt = { 349static struct irq_chip ip32_maceisa_interrupt = {
421 .typename = "IP32 MACE ISA", 350 .typename = "IP32 MACE ISA",
422 .startup = startup_maceisa_irq,
423 .shutdown = shutdown_maceisa_irq,
424 .enable = enable_maceisa_irq,
425 .disable = disable_maceisa_irq,
426 .ack = mask_and_ack_maceisa_irq, 351 .ack = mask_and_ack_maceisa_irq,
352 .mask = disable_maceisa_irq,
353 .mask_ack = mask_and_ack_maceisa_irq,
354 .unmask = enable_maceisa_irq,
427 .end = end_maceisa_irq, 355 .end = end_maceisa_irq,
428}; 356};
429 357
@@ -433,29 +361,15 @@ static struct irq_chip ip32_maceisa_interrupt = {
433 361
434static void enable_mace_irq(unsigned int irq) 362static void enable_mace_irq(unsigned int irq)
435{ 363{
436 unsigned long flags;
437
438 spin_lock_irqsave(&ip32_irq_lock, flags);
439 crime_mask |= 1 << (irq - 1); 364 crime_mask |= 1 << (irq - 1);
440 crime->imask = crime_mask; 365 crime->imask = crime_mask;
441 spin_unlock_irqrestore(&ip32_irq_lock, flags);
442}
443
444static unsigned int startup_mace_irq(unsigned int irq)
445{
446 enable_mace_irq(irq);
447 return 0;
448} 366}
449 367
450static void disable_mace_irq(unsigned int irq) 368static void disable_mace_irq(unsigned int irq)
451{ 369{
452 unsigned long flags;
453
454 spin_lock_irqsave(&ip32_irq_lock, flags);
455 crime_mask &= ~(1 << (irq - 1)); 370 crime_mask &= ~(1 << (irq - 1));
456 crime->imask = crime_mask; 371 crime->imask = crime_mask;
457 flush_crime_bus(); 372 flush_crime_bus();
458 spin_unlock_irqrestore(&ip32_irq_lock, flags);
459} 373}
460 374
461static void end_mace_irq(unsigned int irq) 375static void end_mace_irq(unsigned int irq)
@@ -464,16 +378,12 @@ static void end_mace_irq(unsigned int irq)
464 enable_mace_irq(irq); 378 enable_mace_irq(irq);
465} 379}
466 380
467#define shutdown_mace_irq disable_mace_irq
468#define mask_and_ack_mace_irq disable_mace_irq
469
470static struct irq_chip ip32_mace_interrupt = { 381static struct irq_chip ip32_mace_interrupt = {
471 .typename = "IP32 MACE", 382 .typename = "IP32 MACE",
472 .startup = startup_mace_irq, 383 .ack = disable_mace_irq,
473 .shutdown = shutdown_mace_irq, 384 .mask = disable_mace_irq,
474 .enable = enable_mace_irq, 385 .mask_ack = disable_mace_irq,
475 .disable = disable_mace_irq, 386 .unmask = enable_mace_irq,
476 .ack = mask_and_ack_mace_irq,
477 .end = end_mace_irq, 387 .end = end_mace_irq,
478}; 388};
479 389
@@ -586,10 +496,7 @@ void __init arch_init_irq(void)
586 else 496 else
587 controller = &ip32_maceisa_interrupt; 497 controller = &ip32_maceisa_interrupt;
588 498
589 irq_desc[irq].status = IRQ_DISABLED; 499 set_irq_chip(irq, controller);
590 irq_desc[irq].action = 0;
591 irq_desc[irq].depth = 0;
592 irq_desc[irq].chip = controller;
593 } 500 }
594 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); 501 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
595 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); 502 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 8b1f41484923..2e8f6b2e2420 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -45,11 +45,9 @@
45 */ 45 */
46 46
47 47
48#define shutdown_bcm1480_irq disable_bcm1480_irq
49static void end_bcm1480_irq(unsigned int irq); 48static void end_bcm1480_irq(unsigned int irq);
50static void enable_bcm1480_irq(unsigned int irq); 49static void enable_bcm1480_irq(unsigned int irq);
51static void disable_bcm1480_irq(unsigned int irq); 50static void disable_bcm1480_irq(unsigned int irq);
52static unsigned int startup_bcm1480_irq(unsigned int irq);
53static void ack_bcm1480_irq(unsigned int irq); 51static void ack_bcm1480_irq(unsigned int irq);
54#ifdef CONFIG_SMP 52#ifdef CONFIG_SMP
55static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask); 53static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
@@ -85,11 +83,10 @@ extern char sb1250_duart_present[];
85 83
86static struct irq_chip bcm1480_irq_type = { 84static struct irq_chip bcm1480_irq_type = {
87 .typename = "BCM1480-IMR", 85 .typename = "BCM1480-IMR",
88 .startup = startup_bcm1480_irq,
89 .shutdown = shutdown_bcm1480_irq,
90 .enable = enable_bcm1480_irq,
91 .disable = disable_bcm1480_irq,
92 .ack = ack_bcm1480_irq, 86 .ack = ack_bcm1480_irq,
87 .mask = disable_bcm1480_irq,
88 .mask_ack = ack_bcm1480_irq,
89 .unmask = enable_bcm1480_irq,
93 .end = end_bcm1480_irq, 90 .end = end_bcm1480_irq,
94#ifdef CONFIG_SMP 91#ifdef CONFIG_SMP
95 .set_affinity = bcm1480_set_affinity 92 .set_affinity = bcm1480_set_affinity
@@ -188,14 +185,6 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask)
188 185
189/*****************************************************************************/ 186/*****************************************************************************/
190 187
191static unsigned int startup_bcm1480_irq(unsigned int irq)
192{
193 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
194
195 return 0; /* never anything pending */
196}
197
198
199static void disable_bcm1480_irq(unsigned int irq) 188static void disable_bcm1480_irq(unsigned int irq)
200{ 189{
201 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 190 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
@@ -270,16 +259,9 @@ void __init init_bcm1480_irqs(void)
270{ 259{
271 int i; 260 int i;
272 261
273 for (i = 0; i < NR_IRQS; i++) { 262 for (i = 0; i < BCM1480_NR_IRQS; i++) {
274 irq_desc[i].status = IRQ_DISABLED; 263 set_irq_chip(i, &bcm1480_irq_type);
275 irq_desc[i].action = 0; 264 bcm1480_irq_owner[i] = 0;
276 irq_desc[i].depth = 1;
277 if (i < BCM1480_NR_IRQS) {
278 irq_desc[i].chip = &bcm1480_irq_type;
279 bcm1480_irq_owner[i] = 0;
280 } else {
281 irq_desc[i].chip = &no_irq_chip;
282 }
283 } 265 }
284} 266}
285 267
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index e136bde5248e..6f3f71bf4244 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -94,8 +94,6 @@ void bcm1480_time_init(void)
94 */ 94 */
95} 95}
96 96
97#include <asm/sibyte/sb1250.h>
98
99void bcm1480_timer_interrupt(void) 97void bcm1480_timer_interrupt(void)
100{ 98{
101 int cpu = smp_processor_id(); 99 int cpu = smp_processor_id();
@@ -119,7 +117,7 @@ void bcm1480_timer_interrupt(void)
119 } 117 }
120} 118}
121 119
122static unsigned int bcm1480_hpt_read(void) 120static cycle_t bcm1480_hpt_read(void)
123{ 121{
124 /* We assume this function is called xtime_lock held. */ 122 /* We assume this function is called xtime_lock held. */
125 unsigned long count = 123 unsigned long count =
@@ -129,6 +127,6 @@ static unsigned int bcm1480_hpt_read(void)
129 127
130void __init bcm1480_hpt_setup(void) 128void __init bcm1480_hpt_setup(void)
131{ 129{
132 mips_hpt_read = bcm1480_hpt_read; 130 clocksource_mips.read = bcm1480_hpt_read;
133 mips_hpt_frequency = BCM1480_HPT_VALUE; 131 mips_hpt_frequency = BCM1480_HPT_VALUE;
134} 132}
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index d5d26770daf6..82ce7533053f 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -44,11 +44,9 @@
44 */ 44 */
45 45
46 46
47#define shutdown_sb1250_irq disable_sb1250_irq
48static void end_sb1250_irq(unsigned int irq); 47static void end_sb1250_irq(unsigned int irq);
49static void enable_sb1250_irq(unsigned int irq); 48static void enable_sb1250_irq(unsigned int irq);
50static void disable_sb1250_irq(unsigned int irq); 49static void disable_sb1250_irq(unsigned int irq);
51static unsigned int startup_sb1250_irq(unsigned int irq);
52static void ack_sb1250_irq(unsigned int irq); 50static void ack_sb1250_irq(unsigned int irq);
53#ifdef CONFIG_SMP 51#ifdef CONFIG_SMP
54static void sb1250_set_affinity(unsigned int irq, cpumask_t mask); 52static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
@@ -70,11 +68,10 @@ extern char sb1250_duart_present[];
70 68
71static struct irq_chip sb1250_irq_type = { 69static struct irq_chip sb1250_irq_type = {
72 .typename = "SB1250-IMR", 70 .typename = "SB1250-IMR",
73 .startup = startup_sb1250_irq,
74 .shutdown = shutdown_sb1250_irq,
75 .enable = enable_sb1250_irq,
76 .disable = disable_sb1250_irq,
77 .ack = ack_sb1250_irq, 71 .ack = ack_sb1250_irq,
72 .mask = disable_sb1250_irq,
73 .mask_ack = ack_sb1250_irq,
74 .unmask = enable_sb1250_irq,
78 .end = end_sb1250_irq, 75 .end = end_sb1250_irq,
79#ifdef CONFIG_SMP 76#ifdef CONFIG_SMP
80 .set_affinity = sb1250_set_affinity 77 .set_affinity = sb1250_set_affinity
@@ -163,14 +160,6 @@ static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
163 160
164/*****************************************************************************/ 161/*****************************************************************************/
165 162
166static unsigned int startup_sb1250_irq(unsigned int irq)
167{
168 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
169
170 return 0; /* never anything pending */
171}
172
173
174static void disable_sb1250_irq(unsigned int irq) 163static void disable_sb1250_irq(unsigned int irq)
175{ 164{
176 sb1250_mask_irq(sb1250_irq_owner[irq], irq); 165 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
@@ -239,16 +228,9 @@ void __init init_sb1250_irqs(void)
239{ 228{
240 int i; 229 int i;
241 230
242 for (i = 0; i < NR_IRQS; i++) { 231 for (i = 0; i < SB1250_NR_IRQS; i++) {
243 irq_desc[i].status = IRQ_DISABLED; 232 set_irq_chip(i, &sb1250_irq_type);
244 irq_desc[i].action = 0; 233 sb1250_irq_owner[i] = 0;
245 irq_desc[i].depth = 1;
246 if (i < SB1250_NR_IRQS) {
247 irq_desc[i].chip = &sb1250_irq_type;
248 sb1250_irq_owner[i] = 0;
249 } else {
250 irq_desc[i].chip = &no_irq_chip;
251 }
252 } 234 }
253} 235}
254 236
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index bcb74f2c1948..2efffe15ff23 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -51,7 +51,7 @@
51 51
52extern int sb1250_steal_irq(int irq); 52extern int sb1250_steal_irq(int irq);
53 53
54static unsigned int sb1250_hpt_read(void); 54static cycle_t sb1250_hpt_read(void);
55 55
56void __init sb1250_hpt_setup(void) 56void __init sb1250_hpt_setup(void)
57{ 57{
@@ -66,8 +66,8 @@ void __init sb1250_hpt_setup(void)
66 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); 66 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
67 67
68 mips_hpt_frequency = V_SCD_TIMER_FREQ; 68 mips_hpt_frequency = V_SCD_TIMER_FREQ;
69 mips_hpt_read = sb1250_hpt_read; 69 clocksource_mips.read = sb1250_hpt_read;
70 mips_hpt_mask = M_SCD_TIMER_INIT; 70 clocksource_mips.mask = M_SCD_TIMER_INIT;
71 } 71 }
72} 72}
73 73
@@ -143,7 +143,7 @@ void sb1250_timer_interrupt(void)
143 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over 143 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
144 * again. 144 * again.
145 */ 145 */
146static unsigned int sb1250_hpt_read(void) 146static cycle_t sb1250_hpt_read(void)
147{ 147{
148 unsigned int count; 148 unsigned int count;
149 149
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 48fb74a7aaec..8511bcc6d99d 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -11,44 +11,25 @@
11#include <linux/interrupt.h> 11#include <linux/interrupt.h>
12#include <linux/irq.h> 12#include <linux/irq.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/spinlock.h>
15 14
16#include <asm/i8259.h> 15#include <asm/i8259.h>
17#include <asm/io.h> 16#include <asm/io.h>
18#include <asm/sni.h> 17#include <asm/sni.h>
19 18
20DEFINE_SPINLOCK(pciasic_lock);
21
22static void enable_pciasic_irq(unsigned int irq) 19static void enable_pciasic_irq(unsigned int irq)
23{ 20{
24 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2); 21 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
25 unsigned long flags;
26 22
27 spin_lock_irqsave(&pciasic_lock, flags);
28 *(volatile u8 *) PCIMT_IRQSEL |= mask; 23 *(volatile u8 *) PCIMT_IRQSEL |= mask;
29 spin_unlock_irqrestore(&pciasic_lock, flags);
30}
31
32static unsigned int startup_pciasic_irq(unsigned int irq)
33{
34 enable_pciasic_irq(irq);
35 return 0; /* never anything pending */
36} 24}
37 25
38#define shutdown_pciasic_irq disable_pciasic_irq
39
40void disable_pciasic_irq(unsigned int irq) 26void disable_pciasic_irq(unsigned int irq)
41{ 27{
42 unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2)); 28 unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
43 unsigned long flags;
44 29
45 spin_lock_irqsave(&pciasic_lock, flags);
46 *(volatile u8 *) PCIMT_IRQSEL &= mask; 30 *(volatile u8 *) PCIMT_IRQSEL &= mask;
47 spin_unlock_irqrestore(&pciasic_lock, flags);
48} 31}
49 32
50#define mask_and_ack_pciasic_irq disable_pciasic_irq
51
52static void end_pciasic_irq(unsigned int irq) 33static void end_pciasic_irq(unsigned int irq)
53{ 34{
54 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 35 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -57,11 +38,10 @@ static void end_pciasic_irq(unsigned int irq)
57 38
58static struct irq_chip pciasic_irq_type = { 39static struct irq_chip pciasic_irq_type = {
59 .typename = "ASIC-PCI", 40 .typename = "ASIC-PCI",
60 .startup = startup_pciasic_irq, 41 .ack = disable_pciasic_irq,
61 .shutdown = shutdown_pciasic_irq, 42 .mask = disable_pciasic_irq,
62 .enable = enable_pciasic_irq, 43 .mask_ack = disable_pciasic_irq,
63 .disable = disable_pciasic_irq, 44 .unmask = enable_pciasic_irq,
64 .ack = mask_and_ack_pciasic_irq,
65 .end = end_pciasic_irq, 45 .end = end_pciasic_irq,
66}; 46};
67 47
@@ -178,12 +158,8 @@ asmlinkage void plat_irq_dispatch(void)
178 158
179void __init init_pciasic(void) 159void __init init_pciasic(void)
180{ 160{
181 unsigned long flags;
182
183 spin_lock_irqsave(&pciasic_lock, flags);
184 * (volatile u8 *) PCIMT_IRQSEL = 161 * (volatile u8 *) PCIMT_IRQSEL =
185 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD; 162 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD;
186 spin_unlock_irqrestore(&pciasic_lock, flags);
187} 163}
188 164
189/* 165/*
@@ -199,12 +175,8 @@ void __init arch_init_irq(void)
199 init_pciasic(); 175 init_pciasic();
200 176
201 /* Actually we've got more interrupts to handle ... */ 177 /* Actually we've got more interrupts to handle ... */
202 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) { 178 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++)
203 irq_desc[i].status = IRQ_DISABLED; 179 set_irq_chip(i, &pciasic_irq_type);
204 irq_desc[i].action = 0;
205 irq_desc[i].depth = 1;
206 irq_desc[i].chip = &pciasic_irq_type;
207 }
208 180
209 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); 181 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
210} 182}
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
index 8266a88a3f88..21873de49aa8 100644
--- a/arch/mips/tx4927/common/tx4927_irq.c
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -64,19 +64,13 @@
64#define TX4927_IRQ_NEST4 ( 1 << 9 ) 64#define TX4927_IRQ_NEST4 ( 1 << 9 )
65 65
66#define TX4927_IRQ_CP0_INIT ( 1 << 10 ) 66#define TX4927_IRQ_CP0_INIT ( 1 << 10 )
67#define TX4927_IRQ_CP0_STARTUP ( 1 << 11 )
68#define TX4927_IRQ_CP0_SHUTDOWN ( 1 << 12 )
69#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 ) 67#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 )
70#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 ) 68#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 )
71#define TX4927_IRQ_CP0_MASK ( 1 << 15 )
72#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 ) 69#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 )
73 70
74#define TX4927_IRQ_PIC_INIT ( 1 << 20 ) 71#define TX4927_IRQ_PIC_INIT ( 1 << 20 )
75#define TX4927_IRQ_PIC_STARTUP ( 1 << 21 )
76#define TX4927_IRQ_PIC_SHUTDOWN ( 1 << 22 )
77#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 ) 72#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 )
78#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 ) 73#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 )
79#define TX4927_IRQ_PIC_MASK ( 1 << 25 )
80#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 ) 74#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 )
81 75
82#define TX4927_IRQ_ALL 0xffffffff 76#define TX4927_IRQ_ALL 0xffffffff
@@ -87,18 +81,12 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
87 | TX4927_IRQ_INFO 81 | TX4927_IRQ_INFO
88 | TX4927_IRQ_WARN | TX4927_IRQ_EROR 82 | TX4927_IRQ_WARN | TX4927_IRQ_EROR
89// | TX4927_IRQ_CP0_INIT 83// | TX4927_IRQ_CP0_INIT
90// | TX4927_IRQ_CP0_STARTUP
91// | TX4927_IRQ_CP0_SHUTDOWN
92// | TX4927_IRQ_CP0_ENABLE 84// | TX4927_IRQ_CP0_ENABLE
93// | TX4927_IRQ_CP0_DISABLE 85// | TX4927_IRQ_CP0_DISABLE
94// | TX4927_IRQ_CP0_MASK
95// | TX4927_IRQ_CP0_ENDIRQ 86// | TX4927_IRQ_CP0_ENDIRQ
96// | TX4927_IRQ_PIC_INIT 87// | TX4927_IRQ_PIC_INIT
97// | TX4927_IRQ_PIC_STARTUP
98// | TX4927_IRQ_PIC_SHUTDOWN
99// | TX4927_IRQ_PIC_ENABLE 88// | TX4927_IRQ_PIC_ENABLE
100// | TX4927_IRQ_PIC_DISABLE 89// | TX4927_IRQ_PIC_DISABLE
101// | TX4927_IRQ_PIC_MASK
102// | TX4927_IRQ_PIC_ENDIRQ 90// | TX4927_IRQ_PIC_ENDIRQ
103// | TX4927_IRQ_INIT 91// | TX4927_IRQ_INIT
104// | TX4927_IRQ_NEST1 92// | TX4927_IRQ_NEST1
@@ -124,49 +112,36 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
124 * Forwad definitions for all pic's 112 * Forwad definitions for all pic's
125 */ 113 */
126 114
127static unsigned int tx4927_irq_cp0_startup(unsigned int irq);
128static void tx4927_irq_cp0_shutdown(unsigned int irq);
129static void tx4927_irq_cp0_enable(unsigned int irq); 115static void tx4927_irq_cp0_enable(unsigned int irq);
130static void tx4927_irq_cp0_disable(unsigned int irq); 116static void tx4927_irq_cp0_disable(unsigned int irq);
131static void tx4927_irq_cp0_mask_and_ack(unsigned int irq);
132static void tx4927_irq_cp0_end(unsigned int irq); 117static void tx4927_irq_cp0_end(unsigned int irq);
133 118
134static unsigned int tx4927_irq_pic_startup(unsigned int irq);
135static void tx4927_irq_pic_shutdown(unsigned int irq);
136static void tx4927_irq_pic_enable(unsigned int irq); 119static void tx4927_irq_pic_enable(unsigned int irq);
137static void tx4927_irq_pic_disable(unsigned int irq); 120static void tx4927_irq_pic_disable(unsigned int irq);
138static void tx4927_irq_pic_mask_and_ack(unsigned int irq);
139static void tx4927_irq_pic_end(unsigned int irq); 121static void tx4927_irq_pic_end(unsigned int irq);
140 122
141/* 123/*
142 * Kernel structs for all pic's 124 * Kernel structs for all pic's
143 */ 125 */
144 126
145static DEFINE_SPINLOCK(tx4927_cp0_lock);
146static DEFINE_SPINLOCK(tx4927_pic_lock);
147
148#define TX4927_CP0_NAME "TX4927-CP0" 127#define TX4927_CP0_NAME "TX4927-CP0"
149static struct irq_chip tx4927_irq_cp0_type = { 128static struct irq_chip tx4927_irq_cp0_type = {
150 .typename = TX4927_CP0_NAME, 129 .typename = TX4927_CP0_NAME,
151 .startup = tx4927_irq_cp0_startup, 130 .ack = tx4927_irq_cp0_disable,
152 .shutdown = tx4927_irq_cp0_shutdown, 131 .mask = tx4927_irq_cp0_disable,
153 .enable = tx4927_irq_cp0_enable, 132 .mask_ack = tx4927_irq_cp0_disable,
154 .disable = tx4927_irq_cp0_disable, 133 .unmask = tx4927_irq_cp0_enable,
155 .ack = tx4927_irq_cp0_mask_and_ack,
156 .end = tx4927_irq_cp0_end, 134 .end = tx4927_irq_cp0_end,
157 .set_affinity = NULL
158}; 135};
159 136
160#define TX4927_PIC_NAME "TX4927-PIC" 137#define TX4927_PIC_NAME "TX4927-PIC"
161static struct irq_chip tx4927_irq_pic_type = { 138static struct irq_chip tx4927_irq_pic_type = {
162 .typename = TX4927_PIC_NAME, 139 .typename = TX4927_PIC_NAME,
163 .startup = tx4927_irq_pic_startup, 140 .ack = tx4927_irq_pic_disable,
164 .shutdown = tx4927_irq_pic_shutdown, 141 .mask = tx4927_irq_pic_disable,
165 .enable = tx4927_irq_pic_enable, 142 .mask_ack = tx4927_irq_pic_disable,
166 .disable = tx4927_irq_pic_disable, 143 .unmask = tx4927_irq_pic_enable,
167 .ack = tx4927_irq_pic_mask_and_ack,
168 .end = tx4927_irq_pic_end, 144 .end = tx4927_irq_pic_end,
169 .set_affinity = NULL
170}; 145};
171 146
172#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } 147#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
@@ -211,8 +186,6 @@ tx4927_irq_cp0_modify(unsigned cp0_reg, unsigned clr_bits, unsigned set_bits)
211 break; 186 break;
212 } 187 }
213 } 188 }
214
215 return;
216} 189}
217 190
218static void __init tx4927_irq_cp0_init(void) 191static void __init tx4927_irq_cp0_init(void)
@@ -222,71 +195,23 @@ static void __init tx4927_irq_cp0_init(void)
222 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n", 195 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n",
223 TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END); 196 TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END);
224 197
225 for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++) { 198 for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++)
226 irq_desc[i].status = IRQ_DISABLED; 199 set_irq_chip_and_handler(i, &tx4927_irq_cp0_type,
227 irq_desc[i].action = 0; 200 handle_level_irq);
228 irq_desc[i].depth = 1;
229 irq_desc[i].chip = &tx4927_irq_cp0_type;
230 }
231
232 return;
233}
234
235static unsigned int tx4927_irq_cp0_startup(unsigned int irq)
236{
237 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_STARTUP, "irq=%d \n", irq);
238
239 tx4927_irq_cp0_enable(irq);
240
241 return (0);
242}
243
244static void tx4927_irq_cp0_shutdown(unsigned int irq)
245{
246 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_SHUTDOWN, "irq=%d \n", irq);
247
248 tx4927_irq_cp0_disable(irq);
249
250 return;
251} 201}
252 202
253static void tx4927_irq_cp0_enable(unsigned int irq) 203static void tx4927_irq_cp0_enable(unsigned int irq)
254{ 204{
255 unsigned long flags;
256
257 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq); 205 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq);
258 206
259 spin_lock_irqsave(&tx4927_cp0_lock, flags);
260
261 tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq)); 207 tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq));
262
263 spin_unlock_irqrestore(&tx4927_cp0_lock, flags);
264
265 return;
266} 208}
267 209
268static void tx4927_irq_cp0_disable(unsigned int irq) 210static void tx4927_irq_cp0_disable(unsigned int irq)
269{ 211{
270 unsigned long flags;
271
272 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq); 212 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq);
273 213
274 spin_lock_irqsave(&tx4927_cp0_lock, flags);
275
276 tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0); 214 tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0);
277
278 spin_unlock_irqrestore(&tx4927_cp0_lock, flags);
279
280 return;
281}
282
283static void tx4927_irq_cp0_mask_and_ack(unsigned int irq)
284{
285 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_MASK, "irq=%d \n", irq);
286
287 tx4927_irq_cp0_disable(irq);
288
289 return;
290} 215}
291 216
292static void tx4927_irq_cp0_end(unsigned int irq) 217static void tx4927_irq_cp0_end(unsigned int irq)
@@ -296,8 +221,6 @@ static void tx4927_irq_cp0_end(unsigned int irq)
296 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 221 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
297 tx4927_irq_cp0_enable(irq); 222 tx4927_irq_cp0_enable(irq);
298 } 223 }
299
300 return;
301} 224}
302 225
303/* 226/*
@@ -418,94 +341,39 @@ static void tx4927_irq_pic_modify(unsigned pic_reg, unsigned clr_bits,
418 val &= (~clr_bits); 341 val &= (~clr_bits);
419 val |= (set_bits); 342 val |= (set_bits);
420 TX4927_WR(pic_reg, val); 343 TX4927_WR(pic_reg, val);
421
422 return;
423} 344}
424 345
425static void __init tx4927_irq_pic_init(void) 346static void __init tx4927_irq_pic_init(void)
426{ 347{
427 unsigned long flags;
428 int i; 348 int i;
429 349
430 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n", 350 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n",
431 TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END); 351 TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END);
432 352
433 for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) { 353 for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++)
434 irq_desc[i].status = IRQ_DISABLED; 354 set_irq_chip_and_handler(i, &tx4927_irq_pic_type,
435 irq_desc[i].action = 0; 355 handle_level_irq);
436 irq_desc[i].depth = 2;
437 irq_desc[i].chip = &tx4927_irq_pic_type;
438 }
439 356
440 setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); 357 setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action);
441 358
442 spin_lock_irqsave(&tx4927_pic_lock, flags);
443
444 TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ 359 TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
445 TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */ 360 TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */
446
447 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
448
449 return;
450}
451
452static unsigned int tx4927_irq_pic_startup(unsigned int irq)
453{
454 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_STARTUP, "irq=%d\n", irq);
455
456 tx4927_irq_pic_enable(irq);
457
458 return (0);
459}
460
461static void tx4927_irq_pic_shutdown(unsigned int irq)
462{
463 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_SHUTDOWN, "irq=%d\n", irq);
464
465 tx4927_irq_pic_disable(irq);
466
467 return;
468} 361}
469 362
470static void tx4927_irq_pic_enable(unsigned int irq) 363static void tx4927_irq_pic_enable(unsigned int irq)
471{ 364{
472 unsigned long flags;
473
474 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq); 365 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq);
475 366
476 spin_lock_irqsave(&tx4927_pic_lock, flags);
477
478 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0, 367 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0,
479 tx4927_irq_pic_mask(irq)); 368 tx4927_irq_pic_mask(irq));
480
481 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
482
483 return;
484} 369}
485 370
486static void tx4927_irq_pic_disable(unsigned int irq) 371static void tx4927_irq_pic_disable(unsigned int irq)
487{ 372{
488 unsigned long flags;
489
490 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq); 373 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq);
491 374
492 spin_lock_irqsave(&tx4927_pic_lock, flags);
493
494 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 375 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq),
495 tx4927_irq_pic_mask(irq), 0); 376 tx4927_irq_pic_mask(irq), 0);
496
497 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
498
499 return;
500}
501
502static void tx4927_irq_pic_mask_and_ack(unsigned int irq)
503{
504 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_MASK, "irq=%d\n", irq);
505
506 tx4927_irq_pic_disable(irq);
507
508 return;
509} 377}
510 378
511static void tx4927_irq_pic_end(unsigned int irq) 379static void tx4927_irq_pic_end(unsigned int irq)
@@ -515,8 +383,6 @@ static void tx4927_irq_pic_end(unsigned int irq)
515 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 383 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
516 tx4927_irq_pic_enable(irq); 384 tx4927_irq_pic_enable(irq);
517 } 385 }
518
519 return;
520} 386}
521 387
522/* 388/*
@@ -533,8 +399,6 @@ void __init tx4927_irq_init(void)
533 tx4927_irq_pic_init(); 399 tx4927_irq_pic_init();
534 400
535 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n"); 401 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n");
536
537 return;
538} 402}
539 403
540static int tx4927_irq_nested(void) 404static int tx4927_irq_nested(void)
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index 0c3c3f668230..34cdb2a240e9 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -151,16 +151,11 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
151#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 ) 151#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 )
152 152
153#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 ) 153#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
154#define TOSHIBA_RBTX4927_IRQ_IOC_STARTUP ( 1 << 11 )
155#define TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN ( 1 << 12 )
156#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 ) 154#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
157#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 ) 155#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
158#define TOSHIBA_RBTX4927_IRQ_IOC_MASK ( 1 << 15 )
159#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 ) 156#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 )
160 157
161#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 ) 158#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
162#define TOSHIBA_RBTX4927_IRQ_ISA_STARTUP ( 1 << 21 )
163#define TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN ( 1 << 22 )
164#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 ) 159#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
165#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 ) 160#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 )
166#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 ) 161#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 )
@@ -175,15 +170,10 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
175 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | 170 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
176 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR 171 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
177// | TOSHIBA_RBTX4927_IRQ_IOC_INIT 172// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
178// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP
179// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN
180// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE 173// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
181// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE 174// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
182// | TOSHIBA_RBTX4927_IRQ_IOC_MASK
183// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ 175// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
184// | TOSHIBA_RBTX4927_IRQ_ISA_INIT 176// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
185// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP
186// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN
187// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE 177// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
188// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE 178// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
189// | TOSHIBA_RBTX4927_IRQ_ISA_MASK 179// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
@@ -231,35 +221,25 @@ extern void disable_8259A_irq(unsigned int irq);
231extern void mask_and_ack_8259A(unsigned int irq); 221extern void mask_and_ack_8259A(unsigned int irq);
232#endif 222#endif
233 223
234static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq);
235static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq);
236static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); 224static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
237static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); 225static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
238static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq);
239static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq); 226static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
240 227
241#ifdef CONFIG_TOSHIBA_FPCIB0 228#ifdef CONFIG_TOSHIBA_FPCIB0
242static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq);
243static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq);
244static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq); 229static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
245static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq); 230static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
246static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq); 231static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
247static void toshiba_rbtx4927_irq_isa_end(unsigned int irq); 232static void toshiba_rbtx4927_irq_isa_end(unsigned int irq);
248#endif 233#endif
249 234
250static DEFINE_SPINLOCK(toshiba_rbtx4927_ioc_lock);
251
252
253#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" 235#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
254static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { 236static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
255 .typename = TOSHIBA_RBTX4927_IOC_NAME, 237 .typename = TOSHIBA_RBTX4927_IOC_NAME,
256 .startup = toshiba_rbtx4927_irq_ioc_startup, 238 .ack = toshiba_rbtx4927_irq_ioc_disable,
257 .shutdown = toshiba_rbtx4927_irq_ioc_shutdown, 239 .mask = toshiba_rbtx4927_irq_ioc_disable,
258 .enable = toshiba_rbtx4927_irq_ioc_enable, 240 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
259 .disable = toshiba_rbtx4927_irq_ioc_disable, 241 .unmask = toshiba_rbtx4927_irq_ioc_enable,
260 .ack = toshiba_rbtx4927_irq_ioc_mask_and_ack,
261 .end = toshiba_rbtx4927_irq_ioc_end, 242 .end = toshiba_rbtx4927_irq_ioc_end,
262 .set_affinity = NULL
263}; 243};
264#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 244#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
265#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 245#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
@@ -269,13 +249,11 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
269#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA" 249#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
270static struct irq_chip toshiba_rbtx4927_irq_isa_type = { 250static struct irq_chip toshiba_rbtx4927_irq_isa_type = {
271 .typename = TOSHIBA_RBTX4927_ISA_NAME, 251 .typename = TOSHIBA_RBTX4927_ISA_NAME,
272 .startup = toshiba_rbtx4927_irq_isa_startup,
273 .shutdown = toshiba_rbtx4927_irq_isa_shutdown,
274 .enable = toshiba_rbtx4927_irq_isa_enable,
275 .disable = toshiba_rbtx4927_irq_isa_disable,
276 .ack = toshiba_rbtx4927_irq_isa_mask_and_ack, 252 .ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
253 .mask = toshiba_rbtx4927_irq_isa_disable,
254 .mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
255 .unmask = toshiba_rbtx4927_irq_isa_enable,
277 .end = toshiba_rbtx4927_irq_isa_end, 256 .end = toshiba_rbtx4927_irq_isa_end,
278 .set_affinity = NULL
279}; 257};
280#endif 258#endif
281 259
@@ -363,58 +341,16 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void)
363 TOSHIBA_RBTX4927_IRQ_IOC_END); 341 TOSHIBA_RBTX4927_IRQ_IOC_END);
364 342
365 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; 343 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
366 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) { 344 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
367 irq_desc[i].status = IRQ_DISABLED; 345 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
368 irq_desc[i].action = 0; 346 handle_level_irq);
369 irq_desc[i].depth = 3;
370 irq_desc[i].chip = &toshiba_rbtx4927_irq_ioc_type;
371 }
372 347
373 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, 348 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
374 &toshiba_rbtx4927_irq_ioc_action); 349 &toshiba_rbtx4927_irq_ioc_action);
375
376 return;
377} 350}
378 351
379static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq)
380{
381 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_STARTUP,
382 "irq=%d\n", irq);
383
384 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
385 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
386 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
387 "bad irq=%d\n", irq);
388 panic("\n");
389 }
390
391 toshiba_rbtx4927_irq_ioc_enable(irq);
392
393 return (0);
394}
395
396
397static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq)
398{
399 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN,
400 "irq=%d\n", irq);
401
402 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
403 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
404 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
405 "bad irq=%d\n", irq);
406 panic("\n");
407 }
408
409 toshiba_rbtx4927_irq_ioc_disable(irq);
410
411 return;
412}
413
414
415static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) 352static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
416{ 353{
417 unsigned long flags;
418 volatile unsigned char v; 354 volatile unsigned char v;
419 355
420 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE, 356 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
@@ -427,21 +363,14 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
427 panic("\n"); 363 panic("\n");
428 } 364 }
429 365
430 spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
431
432 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 366 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
433 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 367 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
434 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 368 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
435
436 spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
437
438 return;
439} 369}
440 370
441 371
442static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) 372static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
443{ 373{
444 unsigned long flags;
445 volatile unsigned char v; 374 volatile unsigned char v;
446 375
447 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE, 376 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
@@ -454,36 +383,11 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
454 panic("\n"); 383 panic("\n");
455 } 384 }
456 385
457 spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
458
459 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 386 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
460 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 387 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
461 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 388 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
462
463 spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
464
465 return;
466} 389}
467 390
468
469static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq)
470{
471 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_MASK,
472 "irq=%d\n", irq);
473
474 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
475 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
476 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
477 "bad irq=%d\n", irq);
478 panic("\n");
479 }
480
481 toshiba_rbtx4927_irq_ioc_disable(irq);
482
483 return;
484}
485
486
487static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq) 391static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
488{ 392{
489 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ, 393 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
@@ -499,8 +403,6 @@ static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
499 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 403 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
500 toshiba_rbtx4927_irq_ioc_enable(irq); 404 toshiba_rbtx4927_irq_ioc_enable(irq);
501 } 405 }
502
503 return;
504} 406}
505 407
506 408
@@ -520,13 +422,8 @@ static void __init toshiba_rbtx4927_irq_isa_init(void)
520 TOSHIBA_RBTX4927_IRQ_ISA_END); 422 TOSHIBA_RBTX4927_IRQ_ISA_END);
521 423
522 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG; 424 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
523 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) { 425 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++)
524 irq_desc[i].status = IRQ_DISABLED; 426 set_irq_chip(i, &toshiba_rbtx4927_irq_isa_type);
525 irq_desc[i].action = 0;
526 irq_desc[i].depth =
527 ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5));
528 irq_desc[i].chip = &toshiba_rbtx4927_irq_isa_type;
529 }
530 427
531 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC, 428 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
532 &toshiba_rbtx4927_irq_isa_master); 429 &toshiba_rbtx4927_irq_isa_master);
@@ -536,48 +433,6 @@ static void __init toshiba_rbtx4927_irq_isa_init(void)
536 /* make sure we are looking at IRR (not ISR) */ 433 /* make sure we are looking at IRR (not ISR) */
537 outb(0x0A, 0x20); 434 outb(0x0A, 0x20);
538 outb(0x0A, 0xA0); 435 outb(0x0A, 0xA0);
539
540 return;
541}
542#endif
543
544
545#ifdef CONFIG_TOSHIBA_FPCIB0
546static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq)
547{
548 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_STARTUP,
549 "irq=%d\n", irq);
550
551 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
552 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
553 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
554 "bad irq=%d\n", irq);
555 panic("\n");
556 }
557
558 toshiba_rbtx4927_irq_isa_enable(irq);
559
560 return (0);
561}
562#endif
563
564
565#ifdef CONFIG_TOSHIBA_FPCIB0
566static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq)
567{
568 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN,
569 "irq=%d\n", irq);
570
571 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
572 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
573 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
574 "bad irq=%d\n", irq);
575 panic("\n");
576 }
577
578 toshiba_rbtx4927_irq_isa_disable(irq);
579
580 return;
581} 436}
582#endif 437#endif
583 438
@@ -596,8 +451,6 @@ static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
596 } 451 }
597 452
598 enable_8259A_irq(irq); 453 enable_8259A_irq(irq);
599
600 return;
601} 454}
602#endif 455#endif
603 456
@@ -616,8 +469,6 @@ static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
616 } 469 }
617 470
618 disable_8259A_irq(irq); 471 disable_8259A_irq(irq);
619
620 return;
621} 472}
622#endif 473#endif
623 474
@@ -636,8 +487,6 @@ static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
636 } 487 }
637 488
638 mask_and_ack_8259A(irq); 489 mask_and_ack_8259A(irq);
639
640 return;
641} 490}
642#endif 491#endif
643 492
@@ -658,8 +507,6 @@ static void toshiba_rbtx4927_irq_isa_end(unsigned int irq)
658 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 507 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
659 toshiba_rbtx4927_irq_isa_enable(irq); 508 toshiba_rbtx4927_irq_isa_enable(irq);
660 } 509 }
661
662 return;
663} 510}
664#endif 511#endif
665 512
@@ -668,8 +515,6 @@ void __init arch_init_irq(void)
668{ 515{
669 extern void tx4927_irq_init(void); 516 extern void tx4927_irq_init(void);
670 517
671 local_irq_disable();
672
673 tx4927_irq_init(); 518 tx4927_irq_init();
674 toshiba_rbtx4927_irq_ioc_init(); 519 toshiba_rbtx4927_irq_ioc_init();
675#ifdef CONFIG_TOSHIBA_FPCIB0 520#ifdef CONFIG_TOSHIBA_FPCIB0
@@ -681,8 +526,6 @@ void __init arch_init_irq(void)
681#endif 526#endif
682 527
683 wbflush(); 528 wbflush();
684
685 return;
686} 529}
687 530
688void toshiba_rbtx4927_irq_dump(char *key) 531void toshiba_rbtx4927_irq_dump(char *key)
@@ -715,7 +558,6 @@ void toshiba_rbtx4927_irq_dump(char *key)
715 } 558 }
716 } 559 }
717#endif 560#endif
718 return;
719} 561}
720 562
721void toshiba_rbtx4927_irq_dump_pics(char *s) 563void toshiba_rbtx4927_irq_dump_pics(char *s)
@@ -780,6 +622,4 @@ void toshiba_rbtx4927_irq_dump_pics(char *s)
780 level5_s); 622 level5_s);
781 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n", 623 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
782 s); 624 s);
783
784 return;
785} 625}
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
index 77fe2454f5b9..42e127683ae9 100644
--- a/arch/mips/tx4938/common/irq.c
+++ b/arch/mips/tx4938/common/irq.c
@@ -37,48 +37,36 @@
37/* Forwad definitions for all pic's */ 37/* Forwad definitions for all pic's */
38/**********************************************************************************/ 38/**********************************************************************************/
39 39
40static unsigned int tx4938_irq_cp0_startup(unsigned int irq);
41static void tx4938_irq_cp0_shutdown(unsigned int irq);
42static void tx4938_irq_cp0_enable(unsigned int irq); 40static void tx4938_irq_cp0_enable(unsigned int irq);
43static void tx4938_irq_cp0_disable(unsigned int irq); 41static void tx4938_irq_cp0_disable(unsigned int irq);
44static void tx4938_irq_cp0_mask_and_ack(unsigned int irq);
45static void tx4938_irq_cp0_end(unsigned int irq); 42static void tx4938_irq_cp0_end(unsigned int irq);
46 43
47static unsigned int tx4938_irq_pic_startup(unsigned int irq);
48static void tx4938_irq_pic_shutdown(unsigned int irq);
49static void tx4938_irq_pic_enable(unsigned int irq); 44static void tx4938_irq_pic_enable(unsigned int irq);
50static void tx4938_irq_pic_disable(unsigned int irq); 45static void tx4938_irq_pic_disable(unsigned int irq);
51static void tx4938_irq_pic_mask_and_ack(unsigned int irq);
52static void tx4938_irq_pic_end(unsigned int irq); 46static void tx4938_irq_pic_end(unsigned int irq);
53 47
54/**********************************************************************************/ 48/**********************************************************************************/
55/* Kernel structs for all pic's */ 49/* Kernel structs for all pic's */
56/**********************************************************************************/ 50/**********************************************************************************/
57DEFINE_SPINLOCK(tx4938_cp0_lock);
58DEFINE_SPINLOCK(tx4938_pic_lock);
59 51
60#define TX4938_CP0_NAME "TX4938-CP0" 52#define TX4938_CP0_NAME "TX4938-CP0"
61static struct irq_chip tx4938_irq_cp0_type = { 53static struct irq_chip tx4938_irq_cp0_type = {
62 .typename = TX4938_CP0_NAME, 54 .typename = TX4938_CP0_NAME,
63 .startup = tx4938_irq_cp0_startup, 55 .ack = tx4938_irq_cp0_disable,
64 .shutdown = tx4938_irq_cp0_shutdown, 56 .mask = tx4938_irq_cp0_disable,
65 .enable = tx4938_irq_cp0_enable, 57 .mask_ack = tx4938_irq_cp0_disable,
66 .disable = tx4938_irq_cp0_disable, 58 .unmask = tx4938_irq_cp0_enable,
67 .ack = tx4938_irq_cp0_mask_and_ack,
68 .end = tx4938_irq_cp0_end, 59 .end = tx4938_irq_cp0_end,
69 .set_affinity = NULL
70}; 60};
71 61
72#define TX4938_PIC_NAME "TX4938-PIC" 62#define TX4938_PIC_NAME "TX4938-PIC"
73static struct irq_chip tx4938_irq_pic_type = { 63static struct irq_chip tx4938_irq_pic_type = {
74 .typename = TX4938_PIC_NAME, 64 .typename = TX4938_PIC_NAME,
75 .startup = tx4938_irq_pic_startup, 65 .ack = tx4938_irq_pic_disable,
76 .shutdown = tx4938_irq_pic_shutdown, 66 .mask = tx4938_irq_pic_disable,
77 .enable = tx4938_irq_pic_enable, 67 .mask_ack = tx4938_irq_pic_disable,
78 .disable = tx4938_irq_pic_disable, 68 .unmask = tx4938_irq_pic_enable,
79 .ack = tx4938_irq_pic_mask_and_ack,
80 .end = tx4938_irq_pic_end, 69 .end = tx4938_irq_pic_end,
81 .set_affinity = NULL
82}; 70};
83 71
84static struct irqaction tx4938_irq_pic_action = { 72static struct irqaction tx4938_irq_pic_action = {
@@ -99,56 +87,21 @@ tx4938_irq_cp0_init(void)
99{ 87{
100 int i; 88 int i;
101 89
102 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) { 90 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++)
103 irq_desc[i].status = IRQ_DISABLED; 91 set_irq_chip_and_handler(i, &tx4938_irq_cp0_type,
104 irq_desc[i].action = 0; 92 handle_level_irq);
105 irq_desc[i].depth = 1;
106 irq_desc[i].chip = &tx4938_irq_cp0_type;
107 }
108}
109
110static unsigned int
111tx4938_irq_cp0_startup(unsigned int irq)
112{
113 tx4938_irq_cp0_enable(irq);
114
115 return 0;
116}
117
118static void
119tx4938_irq_cp0_shutdown(unsigned int irq)
120{
121 tx4938_irq_cp0_disable(irq);
122} 93}
123 94
124static void 95static void
125tx4938_irq_cp0_enable(unsigned int irq) 96tx4938_irq_cp0_enable(unsigned int irq)
126{ 97{
127 unsigned long flags;
128
129 spin_lock_irqsave(&tx4938_cp0_lock, flags);
130
131 set_c0_status(tx4938_irq_cp0_mask(irq)); 98 set_c0_status(tx4938_irq_cp0_mask(irq));
132
133 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
134} 99}
135 100
136static void 101static void
137tx4938_irq_cp0_disable(unsigned int irq) 102tx4938_irq_cp0_disable(unsigned int irq)
138{ 103{
139 unsigned long flags;
140
141 spin_lock_irqsave(&tx4938_cp0_lock, flags);
142
143 clear_c0_status(tx4938_irq_cp0_mask(irq)); 104 clear_c0_status(tx4938_irq_cp0_mask(irq));
144
145 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
146}
147
148static void
149tx4938_irq_cp0_mask_and_ack(unsigned int irq)
150{
151 tx4938_irq_cp0_disable(irq);
152} 105}
153 106
154static void 107static void
@@ -290,70 +243,30 @@ tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
290static void __init 243static void __init
291tx4938_irq_pic_init(void) 244tx4938_irq_pic_init(void)
292{ 245{
293 unsigned long flags;
294 int i; 246 int i;
295 247
296 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) { 248 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++)
297 irq_desc[i].status = IRQ_DISABLED; 249 set_irq_chip_and_handler(i, &tx4938_irq_pic_type,
298 irq_desc[i].action = 0; 250 handle_level_irq);
299 irq_desc[i].depth = 2;
300 irq_desc[i].chip = &tx4938_irq_pic_type;
301 }
302 251
303 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); 252 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
304 253
305 spin_lock_irqsave(&tx4938_pic_lock, flags);
306
307 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ 254 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
308 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */ 255 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
309
310 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
311}
312
313static unsigned int
314tx4938_irq_pic_startup(unsigned int irq)
315{
316 tx4938_irq_pic_enable(irq);
317
318 return 0;
319}
320
321static void
322tx4938_irq_pic_shutdown(unsigned int irq)
323{
324 tx4938_irq_pic_disable(irq);
325} 256}
326 257
327static void 258static void
328tx4938_irq_pic_enable(unsigned int irq) 259tx4938_irq_pic_enable(unsigned int irq)
329{ 260{
330 unsigned long flags;
331
332 spin_lock_irqsave(&tx4938_pic_lock, flags);
333
334 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0, 261 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
335 tx4938_irq_pic_mask(irq)); 262 tx4938_irq_pic_mask(irq));
336
337 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
338} 263}
339 264
340static void 265static void
341tx4938_irq_pic_disable(unsigned int irq) 266tx4938_irq_pic_disable(unsigned int irq)
342{ 267{
343 unsigned long flags;
344
345 spin_lock_irqsave(&tx4938_pic_lock, flags);
346
347 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 268 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
348 tx4938_irq_pic_mask(irq), 0); 269 tx4938_irq_pic_mask(irq), 0);
349
350 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
351}
352
353static void
354tx4938_irq_pic_mask_and_ack(unsigned int irq)
355{
356 tx4938_irq_pic_disable(irq);
357} 270}
358 271
359static void 272static void
diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c
index f415a1f18fba..dc87d92bb08d 100644
--- a/arch/mips/tx4938/common/setup.c
+++ b/arch/mips/tx4938/common/setup.c
@@ -31,7 +31,6 @@
31#include <asm/mipsregs.h> 31#include <asm/mipsregs.h>
32#include <asm/system.h> 32#include <asm/system.h>
33#include <asm/time.h> 33#include <asm/time.h>
34#include <asm/time.h>
35#include <asm/tx4938/rbtx4938.h> 34#include <asm/tx4938/rbtx4938.h>
36 35
37extern void toshiba_rbtx4938_setup(void); 36extern void toshiba_rbtx4938_setup(void);
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
index 102e473c10a2..8c87a35f3068 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -87,25 +87,18 @@ IRQ Device
87#include <linux/bootmem.h> 87#include <linux/bootmem.h>
88#include <asm/tx4938/rbtx4938.h> 88#include <asm/tx4938/rbtx4938.h>
89 89
90static unsigned int toshiba_rbtx4938_irq_ioc_startup(unsigned int irq);
91static void toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq);
92static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); 90static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
93static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); 91static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
94static void toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq);
95static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq); 92static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq);
96 93
97DEFINE_SPINLOCK(toshiba_rbtx4938_ioc_lock);
98
99#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" 94#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
100static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { 95static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
101 .typename = TOSHIBA_RBTX4938_IOC_NAME, 96 .typename = TOSHIBA_RBTX4938_IOC_NAME,
102 .startup = toshiba_rbtx4938_irq_ioc_startup, 97 .ack = toshiba_rbtx4938_irq_ioc_disable,
103 .shutdown = toshiba_rbtx4938_irq_ioc_shutdown, 98 .mask = toshiba_rbtx4938_irq_ioc_disable,
104 .enable = toshiba_rbtx4938_irq_ioc_enable, 99 .mask_ack = toshiba_rbtx4938_irq_ioc_disable,
105 .disable = toshiba_rbtx4938_irq_ioc_disable, 100 .unmask = toshiba_rbtx4938_irq_ioc_enable,
106 .ack = toshiba_rbtx4938_irq_ioc_mask_and_ack,
107 .end = toshiba_rbtx4938_irq_ioc_end, 101 .end = toshiba_rbtx4938_irq_ioc_end,
108 .set_affinity = NULL
109}; 102};
110 103
111#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000 104#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
@@ -142,69 +135,36 @@ toshiba_rbtx4938_irq_ioc_init(void)
142 int i; 135 int i;
143 136
144 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; 137 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
145 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) { 138 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++)
146 irq_desc[i].status = IRQ_DISABLED; 139 set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
147 irq_desc[i].action = 0; 140 handle_level_irq);
148 irq_desc[i].depth = 3;
149 irq_desc[i].chip = &toshiba_rbtx4938_irq_ioc_type;
150 }
151 141
152 setup_irq(RBTX4938_IRQ_IOCINT, 142 setup_irq(RBTX4938_IRQ_IOCINT,
153 &toshiba_rbtx4938_irq_ioc_action); 143 &toshiba_rbtx4938_irq_ioc_action);
154} 144}
155 145
156static unsigned int
157toshiba_rbtx4938_irq_ioc_startup(unsigned int irq)
158{
159 toshiba_rbtx4938_irq_ioc_enable(irq);
160
161 return 0;
162}
163
164static void
165toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq)
166{
167 toshiba_rbtx4938_irq_ioc_disable(irq);
168}
169
170static void 146static void
171toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) 147toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
172{ 148{
173 unsigned long flags;
174 volatile unsigned char v; 149 volatile unsigned char v;
175 150
176 spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
177
178 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 151 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
179 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); 152 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
180 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); 153 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
181 mmiowb(); 154 mmiowb();
182 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 155 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
183
184 spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
185} 156}
186 157
187static void 158static void
188toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) 159toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
189{ 160{
190 unsigned long flags;
191 volatile unsigned char v; 161 volatile unsigned char v;
192 162
193 spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
194
195 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 163 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
196 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); 164 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
197 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); 165 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
198 mmiowb(); 166 mmiowb();
199 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 167 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
200
201 spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
202}
203
204static void
205toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq)
206{
207 toshiba_rbtx4938_irq_ioc_disable(irq);
208} 168}
209 169
210static void 170static void
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index c215c0d39fae..54b92a74c7ac 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -417,14 +417,7 @@ void vr41xx_disable_bcuint(void)
417 417
418EXPORT_SYMBOL(vr41xx_disable_bcuint); 418EXPORT_SYMBOL(vr41xx_disable_bcuint);
419 419
420static unsigned int startup_sysint1_irq(unsigned int irq) 420static void disable_sysint1_irq(unsigned int irq)
421{
422 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
423
424 return 0; /* never anything pending */
425}
426
427static void shutdown_sysint1_irq(unsigned int irq)
428{ 421{
429 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); 422 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
430} 423}
@@ -434,9 +427,6 @@ static void enable_sysint1_irq(unsigned int irq)
434 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); 427 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
435} 428}
436 429
437#define disable_sysint1_irq shutdown_sysint1_irq
438#define ack_sysint1_irq shutdown_sysint1_irq
439
440static void end_sysint1_irq(unsigned int irq) 430static void end_sysint1_irq(unsigned int irq)
441{ 431{
442 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 432 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -445,22 +435,14 @@ static void end_sysint1_irq(unsigned int irq)
445 435
446static struct irq_chip sysint1_irq_type = { 436static struct irq_chip sysint1_irq_type = {
447 .typename = "SYSINT1", 437 .typename = "SYSINT1",
448 .startup = startup_sysint1_irq, 438 .ack = disable_sysint1_irq,
449 .shutdown = shutdown_sysint1_irq, 439 .mask = disable_sysint1_irq,
450 .enable = enable_sysint1_irq, 440 .mask_ack = disable_sysint1_irq,
451 .disable = disable_sysint1_irq, 441 .unmask = enable_sysint1_irq,
452 .ack = ack_sysint1_irq,
453 .end = end_sysint1_irq, 442 .end = end_sysint1_irq,
454}; 443};
455 444
456static unsigned int startup_sysint2_irq(unsigned int irq) 445static void disable_sysint2_irq(unsigned int irq)
457{
458 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
459
460 return 0; /* never anything pending */
461}
462
463static void shutdown_sysint2_irq(unsigned int irq)
464{ 446{
465 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); 447 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
466} 448}
@@ -470,9 +452,6 @@ static void enable_sysint2_irq(unsigned int irq)
470 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); 452 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
471} 453}
472 454
473#define disable_sysint2_irq shutdown_sysint2_irq
474#define ack_sysint2_irq shutdown_sysint2_irq
475
476static void end_sysint2_irq(unsigned int irq) 455static void end_sysint2_irq(unsigned int irq)
477{ 456{
478 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 457 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -481,11 +460,10 @@ static void end_sysint2_irq(unsigned int irq)
481 460
482static struct irq_chip sysint2_irq_type = { 461static struct irq_chip sysint2_irq_type = {
483 .typename = "SYSINT2", 462 .typename = "SYSINT2",
484 .startup = startup_sysint2_irq, 463 .ack = disable_sysint2_irq,
485 .shutdown = shutdown_sysint2_irq, 464 .mask = disable_sysint2_irq,
486 .enable = enable_sysint2_irq, 465 .mask_ack = disable_sysint2_irq,
487 .disable = disable_sysint2_irq, 466 .unmask = enable_sysint2_irq,
488 .ack = ack_sysint2_irq,
489 .end = end_sysint2_irq, 467 .end = end_sysint2_irq,
490}; 468};
491 469
@@ -723,10 +701,12 @@ static int __init vr41xx_icu_init(void)
723 icu2_write(MGIUINTHREG, 0xffff); 701 icu2_write(MGIUINTHREG, 0xffff);
724 702
725 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) 703 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
726 irq_desc[i].chip = &sysint1_irq_type; 704 set_irq_chip_and_handler(i, &sysint1_irq_type,
705 handle_level_irq);
727 706
728 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) 707 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
729 irq_desc[i].chip = &sysint2_irq_type; 708 set_irq_chip_and_handler(i, &sysint2_irq_type,
709 handle_level_irq);
730 710
731 cascade_irq(INT0_IRQ, icu_get_irq); 711 cascade_irq(INT0_IRQ, icu_get_irq);
732 cascade_irq(INT1_IRQ, icu_get_irq); 712 cascade_irq(INT1_IRQ, icu_get_irq);
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
index 2483487344c2..a039bb7251ff 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/irq.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
@@ -30,17 +30,6 @@ extern void init_8259A(int hoge);
30 30
31extern int vr4133_rockhopper; 31extern int vr4133_rockhopper;
32 32
33static unsigned int startup_i8259_irq(unsigned int irq)
34{
35 enable_8259A_irq(irq - I8259_IRQ_BASE);
36 return 0;
37}
38
39static void shutdown_i8259_irq(unsigned int irq)
40{
41 disable_8259A_irq(irq - I8259_IRQ_BASE);
42}
43
44static void enable_i8259_irq(unsigned int irq) 33static void enable_i8259_irq(unsigned int irq)
45{ 34{
46 enable_8259A_irq(irq - I8259_IRQ_BASE); 35 enable_8259A_irq(irq - I8259_IRQ_BASE);
@@ -64,11 +53,10 @@ static void end_i8259_irq(unsigned int irq)
64 53
65static struct irq_chip i8259_irq_type = { 54static struct irq_chip i8259_irq_type = {
66 .typename = "XT-PIC", 55 .typename = "XT-PIC",
67 .startup = startup_i8259_irq,
68 .shutdown = shutdown_i8259_irq,
69 .enable = enable_i8259_irq,
70 .disable = disable_i8259_irq,
71 .ack = ack_i8259_irq, 56 .ack = ack_i8259_irq,
57 .mask = disable_i8259_irq,
58 .mask_ack = ack_i8259_irq,
59 .unmask = enable_i8259_irq,
72 .end = end_i8259_irq, 60 .end = end_i8259_irq,
73}; 61};
74 62
@@ -104,7 +92,7 @@ void __init rockhopper_init_irq(void)
104 } 92 }
105 93
106 for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++) 94 for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++)
107 irq_desc[i].chip = &i8259_irq_type; 95 set_irq_chip(i, &i8259_irq_type);
108 96
109 setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade); 97 setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade);
110 98
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 45c706e34df1..c6275088cf65 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -19,12 +19,16 @@
19#define _ATYPE_ 19#define _ATYPE_
20#define _ATYPE32_ 20#define _ATYPE32_
21#define _ATYPE64_ 21#define _ATYPE64_
22#define _LLCONST_(x) x 22#define _CONST64_(x) x
23#else 23#else
24#define _ATYPE_ __PTRDIFF_TYPE__ 24#define _ATYPE_ __PTRDIFF_TYPE__
25#define _ATYPE32_ int 25#define _ATYPE32_ int
26#define _ATYPE64_ long long 26#define _ATYPE64_ __s64
27#define _LLCONST_(x) x ## LL 27#ifdef CONFIG_64BIT
28#define _CONST64_(x) x ## L
29#else
30#define _CONST64_(x) x ## LL
31#endif
28#endif 32#endif
29 33
30/* 34/*
@@ -48,7 +52,7 @@
48 */ 52 */
49#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) 53#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
50#define XPHYSADDR(a) ((_ACAST64_(a)) & \ 54#define XPHYSADDR(a) ((_ACAST64_(a)) & \
51 _LLCONST_(0x000000ffffffffff)) 55 _CONST64_(0x000000ffffffffff))
52 56
53#ifdef CONFIG_64BIT 57#ifdef CONFIG_64BIT
54 58
@@ -57,14 +61,14 @@
57 * The compatibility segments use the full 64-bit sign extended value. Note 61 * The compatibility segments use the full 64-bit sign extended value. Note
58 * the R8000 doesn't have them so don't reference these in generic MIPS code. 62 * the R8000 doesn't have them so don't reference these in generic MIPS code.
59 */ 63 */
60#define XKUSEG _LLCONST_(0x0000000000000000) 64#define XKUSEG _CONST64_(0x0000000000000000)
61#define XKSSEG _LLCONST_(0x4000000000000000) 65#define XKSSEG _CONST64_(0x4000000000000000)
62#define XKPHYS _LLCONST_(0x8000000000000000) 66#define XKPHYS _CONST64_(0x8000000000000000)
63#define XKSEG _LLCONST_(0xc000000000000000) 67#define XKSEG _CONST64_(0xc000000000000000)
64#define CKSEG0 _LLCONST_(0xffffffff80000000) 68#define CKSEG0 _CONST64_(0xffffffff80000000)
65#define CKSEG1 _LLCONST_(0xffffffffa0000000) 69#define CKSEG1 _CONST64_(0xffffffffa0000000)
66#define CKSSEG _LLCONST_(0xffffffffc0000000) 70#define CKSSEG _CONST64_(0xffffffffc0000000)
67#define CKSEG3 _LLCONST_(0xffffffffe0000000) 71#define CKSEG3 _CONST64_(0xffffffffe0000000)
68 72
69#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) 73#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
70#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) 74#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
@@ -122,7 +126,7 @@
122#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p)) 126#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p))
123#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p)) 127#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
124#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) 128#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
125#define PHYS_TO_XKPHYS(cm,a) (_LLCONST_(0x8000000000000000) | \ 129#define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \
126 ((cm)<<59) | (a)) 130 ((cm)<<59) | (a))
127 131
128#if defined (CONFIG_CPU_R4300) \ 132#if defined (CONFIG_CPU_R4300) \
@@ -132,20 +136,20 @@
132 || defined (CONFIG_CPU_NEVADA) \ 136 || defined (CONFIG_CPU_NEVADA) \
133 || defined (CONFIG_CPU_TX49XX) \ 137 || defined (CONFIG_CPU_TX49XX) \
134 || defined (CONFIG_CPU_MIPS64) 138 || defined (CONFIG_CPU_MIPS64)
135#define TO_PHYS_MASK _LLCONST_(0x0000000fffffffff) /* 2^^36 - 1 */ 139#define TO_PHYS_MASK _CONST64_(0x0000000fffffffff) /* 2^^36 - 1 */
136#endif 140#endif
137 141
138#if defined (CONFIG_CPU_R8000) 142#if defined (CONFIG_CPU_R8000)
139/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */ 143/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
140#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */ 144#define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */
141#endif 145#endif
142 146
143#if defined (CONFIG_CPU_R10000) 147#if defined (CONFIG_CPU_R10000)
144#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */ 148#define TO_PHYS_MASK _CONST64_(0x000000ffffffffff) /* 2^^40 - 1 */
145#endif 149#endif
146 150
147#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A) 151#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
148#define TO_PHYS_MASK _LLCONST_(0x00000fffffffffff) /* 2^^44 - 1 */ 152#define TO_PHYS_MASK _CONST64_(0x00000fffffffffff) /* 2^^44 - 1 */
149#endif 153#endif
150 154
151#ifndef CONFIG_CPU_R8000 155#ifndef CONFIG_CPU_R8000
@@ -155,7 +159,7 @@
155 * in order to catch bugs in the source code. 159 * in order to catch bugs in the source code.
156 */ 160 */
157 161
158#define COMPAT_K1BASE32 _LLCONST_(0xffffffffa0000000) 162#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
159#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ 163#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
160 164
161#endif 165#endif
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index e64abc0d8221..7978d8e11647 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -9,16 +9,8 @@
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details. 10 * for more details.
11 * 11 *
12 * Copyright (C) 1996, 97, 99, 2000, 03, 04 by Ralf Baechle 12 * Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
13 */ 13 */
14
15/*
16 * As workaround for the ATOMIC_DEC_AND_LOCK / atomic_dec_and_lock mess in
17 * <linux/spinlock.h> we have to include <linux/spinlock.h> outside the
18 * main big wrapper ...
19 */
20#include <linux/spinlock.h>
21
22#ifndef _ASM_ATOMIC_H 14#ifndef _ASM_ATOMIC_H
23#define _ASM_ATOMIC_H 15#define _ASM_ATOMIC_H
24 16
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 1bb89c5a10ee..b9007411b60f 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -10,31 +10,26 @@
10#define _ASM_BITOPS_H 10#define _ASM_BITOPS_H
11 11
12#include <linux/compiler.h> 12#include <linux/compiler.h>
13#include <linux/irqflags.h>
13#include <linux/types.h> 14#include <linux/types.h>
14#include <asm/bug.h> 15#include <asm/bug.h>
15#include <asm/byteorder.h> /* sigh ... */ 16#include <asm/byteorder.h> /* sigh ... */
16#include <asm/cpu-features.h> 17#include <asm/cpu-features.h>
18#include <asm/sgidefs.h>
19#include <asm/war.h>
17 20
18#if (_MIPS_SZLONG == 32) 21#if (_MIPS_SZLONG == 32)
19#define SZLONG_LOG 5 22#define SZLONG_LOG 5
20#define SZLONG_MASK 31UL 23#define SZLONG_MASK 31UL
21#define __LL "ll " 24#define __LL "ll "
22#define __SC "sc " 25#define __SC "sc "
23#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
24#elif (_MIPS_SZLONG == 64) 26#elif (_MIPS_SZLONG == 64)
25#define SZLONG_LOG 6 27#define SZLONG_LOG 6
26#define SZLONG_MASK 63UL 28#define SZLONG_MASK 63UL
27#define __LL "lld " 29#define __LL "lld "
28#define __SC "scd " 30#define __SC "scd "
29#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
30#endif 31#endif
31 32
32#ifdef __KERNEL__
33
34#include <linux/irqflags.h>
35#include <asm/sgidefs.h>
36#include <asm/war.h>
37
38/* 33/*
39 * clear_bit() doesn't provide any barrier for the compiler. 34 * clear_bit() doesn't provide any barrier for the compiler.
40 */ 35 */
@@ -42,20 +37,6 @@
42#define smp_mb__after_clear_bit() smp_mb() 37#define smp_mb__after_clear_bit() smp_mb()
43 38
44/* 39/*
45 * Only disable interrupt for kernel mode stuff to keep usermode stuff
46 * that dares to use kernel include files alive.
47 */
48
49#define __bi_flags unsigned long flags
50#define __bi_local_irq_save(x) local_irq_save(x)
51#define __bi_local_irq_restore(x) local_irq_restore(x)
52#else
53#define __bi_flags
54#define __bi_local_irq_save(x)
55#define __bi_local_irq_restore(x)
56#endif /* __KERNEL__ */
57
58/*
59 * set_bit - Atomically set a bit in memory 40 * set_bit - Atomically set a bit in memory
60 * @nr: the bit to set 41 * @nr: the bit to set
61 * @addr: the address to start counting from 42 * @addr: the address to start counting from
@@ -93,13 +74,13 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
93 } else { 74 } else {
94 volatile unsigned long *a = addr; 75 volatile unsigned long *a = addr;
95 unsigned long mask; 76 unsigned long mask;
96 __bi_flags; 77 unsigned long flags;
97 78
98 a += nr >> SZLONG_LOG; 79 a += nr >> SZLONG_LOG;
99 mask = 1UL << (nr & SZLONG_MASK); 80 mask = 1UL << (nr & SZLONG_MASK);
100 __bi_local_irq_save(flags); 81 local_irq_save(flags);
101 *a |= mask; 82 *a |= mask;
102 __bi_local_irq_restore(flags); 83 local_irq_restore(flags);
103 } 84 }
104} 85}
105 86
@@ -141,13 +122,13 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
141 } else { 122 } else {
142 volatile unsigned long *a = addr; 123 volatile unsigned long *a = addr;
143 unsigned long mask; 124 unsigned long mask;
144 __bi_flags; 125 unsigned long flags;
145 126
146 a += nr >> SZLONG_LOG; 127 a += nr >> SZLONG_LOG;
147 mask = 1UL << (nr & SZLONG_MASK); 128 mask = 1UL << (nr & SZLONG_MASK);
148 __bi_local_irq_save(flags); 129 local_irq_save(flags);
149 *a &= ~mask; 130 *a &= ~mask;
150 __bi_local_irq_restore(flags); 131 local_irq_restore(flags);
151 } 132 }
152} 133}
153 134
@@ -191,13 +172,13 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
191 } else { 172 } else {
192 volatile unsigned long *a = addr; 173 volatile unsigned long *a = addr;
193 unsigned long mask; 174 unsigned long mask;
194 __bi_flags; 175 unsigned long flags;
195 176
196 a += nr >> SZLONG_LOG; 177 a += nr >> SZLONG_LOG;
197 mask = 1UL << (nr & SZLONG_MASK); 178 mask = 1UL << (nr & SZLONG_MASK);
198 __bi_local_irq_save(flags); 179 local_irq_save(flags);
199 *a ^= mask; 180 *a ^= mask;
200 __bi_local_irq_restore(flags); 181 local_irq_restore(flags);
201 } 182 }
202} 183}
203 184
@@ -258,14 +239,14 @@ static inline int test_and_set_bit(unsigned long nr,
258 volatile unsigned long *a = addr; 239 volatile unsigned long *a = addr;
259 unsigned long mask; 240 unsigned long mask;
260 int retval; 241 int retval;
261 __bi_flags; 242 unsigned long flags;
262 243
263 a += nr >> SZLONG_LOG; 244 a += nr >> SZLONG_LOG;
264 mask = 1UL << (nr & SZLONG_MASK); 245 mask = 1UL << (nr & SZLONG_MASK);
265 __bi_local_irq_save(flags); 246 local_irq_save(flags);
266 retval = (mask & *a) != 0; 247 retval = (mask & *a) != 0;
267 *a |= mask; 248 *a |= mask;
268 __bi_local_irq_restore(flags); 249 local_irq_restore(flags);
269 250
270 return retval; 251 return retval;
271 } 252 }
@@ -330,14 +311,14 @@ static inline int test_and_clear_bit(unsigned long nr,
330 volatile unsigned long *a = addr; 311 volatile unsigned long *a = addr;
331 unsigned long mask; 312 unsigned long mask;
332 int retval; 313 int retval;
333 __bi_flags; 314 unsigned long flags;
334 315
335 a += nr >> SZLONG_LOG; 316 a += nr >> SZLONG_LOG;
336 mask = 1UL << (nr & SZLONG_MASK); 317 mask = 1UL << (nr & SZLONG_MASK);
337 __bi_local_irq_save(flags); 318 local_irq_save(flags);
338 retval = (mask & *a) != 0; 319 retval = (mask & *a) != 0;
339 *a &= ~mask; 320 *a &= ~mask;
340 __bi_local_irq_restore(flags); 321 local_irq_restore(flags);
341 322
342 return retval; 323 return retval;
343 } 324 }
@@ -399,23 +380,19 @@ static inline int test_and_change_bit(unsigned long nr,
399 } else { 380 } else {
400 volatile unsigned long *a = addr; 381 volatile unsigned long *a = addr;
401 unsigned long mask, retval; 382 unsigned long mask, retval;
402 __bi_flags; 383 unsigned long flags;
403 384
404 a += nr >> SZLONG_LOG; 385 a += nr >> SZLONG_LOG;
405 mask = 1UL << (nr & SZLONG_MASK); 386 mask = 1UL << (nr & SZLONG_MASK);
406 __bi_local_irq_save(flags); 387 local_irq_save(flags);
407 retval = (mask & *a) != 0; 388 retval = (mask & *a) != 0;
408 *a ^= mask; 389 *a ^= mask;
409 __bi_local_irq_restore(flags); 390 local_irq_restore(flags);
410 391
411 return retval; 392 return retval;
412 } 393 }
413} 394}
414 395
415#undef __bi_flags
416#undef __bi_local_irq_save
417#undef __bi_local_irq_restore
418
419#include <asm-generic/bitops/non-atomic.h> 396#include <asm-generic/bitops/non-atomic.h>
420 397
421/* 398/*
diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h
index 7b4739dc8f3f..4d560a533940 100644
--- a/include/asm-mips/bug.h
+++ b/include/asm-mips/bug.h
@@ -1,6 +1,7 @@
1#ifndef __ASM_BUG_H 1#ifndef __ASM_BUG_H
2#define __ASM_BUG_H 2#define __ASM_BUG_H
3 3
4#include <asm/sgidefs.h>
4 5
5#ifdef CONFIG_BUG 6#ifdef CONFIG_BUG
6 7
@@ -13,6 +14,17 @@ do { \
13 14
14#define HAVE_ARCH_BUG 15#define HAVE_ARCH_BUG
15 16
17#if (_MIPS_ISA > _MIPS_ISA_MIPS1)
18
19#define BUG_ON(condition) \
20do { \
21 __asm__ __volatile__("tne $0, %0" : : "r" (condition)); \
22} while (0)
23
24#define HAVE_ARCH_BUG_ON
25
26#endif /* _MIPS_ISA > _MIPS_ISA_MIPS1 */
27
16#endif 28#endif
17 29
18#include <asm-generic/bug.h> 30#include <asm-generic/bug.h>
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index a2f0c8ea9160..610d0cdeaa9e 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -22,12 +22,12 @@
22 * Descriptor for a cache 22 * Descriptor for a cache
23 */ 23 */
24struct cache_desc { 24struct cache_desc {
25 unsigned short linesz; /* Size of line in bytes */
26 unsigned short ways; /* Number of ways */
27 unsigned short sets; /* Number of lines per set */
28 unsigned int waysize; /* Bytes per way */ 25 unsigned int waysize; /* Bytes per way */
29 unsigned int waybit; /* Bits to select in a cache set */ 26 unsigned short sets; /* Number of lines per set */
30 unsigned int flags; /* Flags describing cache properties */ 27 unsigned char ways; /* Number of ways */
28 unsigned char linesz; /* Size of line in bytes */
29 unsigned char waybit; /* Bits to select in a cache set */
30 unsigned char flags; /* Flags describing cache properties */
31}; 31};
32 32
33/* 33/*
diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h
index 8319ad77b250..93430b5f4724 100644
--- a/include/asm-mips/dec/kn02.h
+++ b/include/asm-mips/dec/kn02.h
@@ -82,11 +82,9 @@
82 82
83#ifndef __ASSEMBLY__ 83#ifndef __ASSEMBLY__
84 84
85#include <linux/spinlock.h>
86#include <linux/types.h> 85#include <linux/types.h>
87 86
88extern u32 cached_kn02_csr; 87extern u32 cached_kn02_csr;
89extern spinlock_t kn02_lock;
90extern void init_kn02_irqs(int base); 88extern void init_kn02_irqs(int base);
91#endif 89#endif
92 90
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h
index e85849ac165f..23f789c80845 100644
--- a/include/asm-mips/dma.h
+++ b/include/asm-mips/dma.h
@@ -74,7 +74,9 @@
74 * 74 *
75 */ 75 */
76 76
77#ifndef GENERIC_ISA_DMA_SUPPORT_BROKEN
77#define MAX_DMA_CHANNELS 8 78#define MAX_DMA_CHANNELS 8
79#endif
78 80
79/* 81/*
80 * The maximum address in KSEG0 that we can perform a DMA transfer to on this 82 * The maximum address in KSEG0 that we can perform a DMA transfer to on this
diff --git a/include/asm-mips/gt64120.h b/include/asm-mips/gt64120.h
index 2edd171bb6cd..4bf8e28f8850 100644
--- a/include/asm-mips/gt64120.h
+++ b/include/asm-mips/gt64120.h
@@ -451,6 +451,13 @@
451#define GT_SDRAM_OPMODE_OP_MODE 3 451#define GT_SDRAM_OPMODE_OP_MODE 3
452#define GT_SDRAM_OPMODE_OP_CBR 4 452#define GT_SDRAM_OPMODE_OP_CBR 4
453 453
454#define GT_TC_CONTROL_ENTC0_SHF 0
455#define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
456#define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK
457#define GT_TC_CONTROL_SELTC0_SHF 1
458#define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
459#define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK
460
454 461
455#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 462#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
456#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) 463#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
@@ -523,6 +530,13 @@
523#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) 530#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
524#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK 531#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
525 532
533#define GT_INTR_T0EXP_SHF 8
534#define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF)
535#define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK
536#define GT_INTR_RETRYCTR0_SHF 20
537#define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF)
538#define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK
539
526/* 540/*
527 * Misc 541 * Misc
528 */ 542 */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index bc5f3c53155f..d77b657c09c7 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -113,7 +113,7 @@ static inline void set_io_port_base(unsigned long base)
113 * almost all conceivable cases a device driver should not be using 113 * almost all conceivable cases a device driver should not be using
114 * this function 114 * this function
115 */ 115 */
116static inline unsigned long virt_to_phys(volatile void * address) 116static inline unsigned long virt_to_phys(volatile const void *address)
117{ 117{
118 return (unsigned long)address - PAGE_OFFSET; 118 return (unsigned long)address - PAGE_OFFSET;
119} 119}
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 35a05ca5560c..67657089efa7 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -24,8 +24,6 @@ static inline int irq_canonicalize(int irq)
24#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ 24#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
25#endif 25#endif
26 26
27extern asmlinkage unsigned int do_IRQ(unsigned int irq);
28
29#ifdef CONFIG_MIPS_MT_SMTC 27#ifdef CONFIG_MIPS_MT_SMTC
30/* 28/*
31 * Clear interrupt mask handling "backstop" if irq_hwmask 29 * Clear interrupt mask handling "backstop" if irq_hwmask
@@ -43,8 +41,6 @@ do { \
43#define __DO_IRQ_SMTC_HOOK() do { } while (0) 41#define __DO_IRQ_SMTC_HOOK() do { } while (0)
44#endif 42#endif
45 43
46#ifdef CONFIG_PREEMPT
47
48/* 44/*
49 * do_IRQ handles all normal device IRQ's (the special 45 * do_IRQ handles all normal device IRQ's (the special
50 * SMP cross-CPU interrupts have their own specific 46 * SMP cross-CPU interrupts have their own specific
@@ -57,12 +53,10 @@ do { \
57do { \ 53do { \
58 irq_enter(); \ 54 irq_enter(); \
59 __DO_IRQ_SMTC_HOOK(); \ 55 __DO_IRQ_SMTC_HOOK(); \
60 __do_IRQ((irq)); \ 56 generic_handle_irq(irq); \
61 irq_exit(); \ 57 irq_exit(); \
62} while (0) 58} while (0)
63 59
64#endif
65
66extern void arch_init_irq(void); 60extern void arch_init_irq(void);
67extern void spurious_interrupt(void); 61extern void spurious_interrupt(void);
68 62
diff --git a/include/asm-mips/kexec.h b/include/asm-mips/kexec.h
new file mode 100644
index 000000000000..b25267ebcb09
--- /dev/null
+++ b/include/asm-mips/kexec.h
@@ -0,0 +1,32 @@
1/*
2 * kexec.h for kexec
3 * Created by <nschichan@corp.free.fr> on Thu Oct 12 14:59:34 2006
4 *
5 * This source code is licensed under the GNU General Public License,
6 * Version 2. See the file COPYING for more details.
7 */
8
9#ifndef _MIPS_KEXEC
10# define _MIPS_KEXEC
11
12/* Maximum physical address we can use pages from */
13#define KEXEC_SOURCE_MEMORY_LIMIT (0x20000000)
14/* Maximum address we can reach in physical address mode */
15#define KEXEC_DESTINATION_MEMORY_LIMIT (0x20000000)
16 /* Maximum address we can use for the control code buffer */
17#define KEXEC_CONTROL_MEMORY_LIMIT (0x20000000)
18
19#define KEXEC_CONTROL_CODE_SIZE 4096
20
21/* The native architecture */
22#define KEXEC_ARCH KEXEC_ARCH_MIPS
23
24#define MAX_NOTE_BYTES 1024
25
26static inline void crash_setup_regs(struct pt_regs *newregs,
27 struct pt_regs *oldregs)
28{
29 /* Dummy implementation for now */
30}
31
32#endif /* !_MIPS_KEXEC */
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index b3c5ecbec03c..00b0fc68d5cb 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -67,34 +67,9 @@
67#define COBALT_BRD_ID_QUBE2 0x5 67#define COBALT_BRD_ID_QUBE2 0x5
68#define COBALT_BRD_ID_RAQ2 0x6 68#define COBALT_BRD_ID_RAQ2 0x6
69 69
70/*
71 * Galileo chipset access macros for the Cobalt. The base address for
72 * the GT64111 chip is 0x14000000
73 *
74 * Most of this really should go into a separate GT64111 header file.
75 */
76#define GT64111_IO_BASE 0x10000000UL
77#define GT64111_IO_END 0x11ffffffUL
78#define GT64111_MEM_BASE 0x12000000UL
79#define GT64111_MEM_END 0x13ffffffUL
80#define GT64111_BASE 0x14000000UL
81#define GALILEO_REG(ofs) CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs))
82
83#define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port))
84#define GALILEO_OUTL(val, port) \
85do { \
86 *(volatile unsigned int *) GALILEO_REG(port) = (val); \
87} while (0)
88
89#define GALILEO_INTR_T0EXP (1 << 8)
90#define GALILEO_INTR_RETRY_CTR (1 << 20)
91
92#define GALILEO_ENTC0 0x01
93#define GALILEO_SELTC0 0x02
94
95#define PCI_CFG_SET(devfn,where) \ 70#define PCI_CFG_SET(devfn,where) \
96 GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \ 71 GT_WRITE(GT_PCI0_CFGADDR_OFS, (0x80000000 | (PCI_SLOT (devfn) << 11) | \
97 (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS) 72 (PCI_FUNC (devfn) << 8) | (where)))
98 73
99#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000)) 74#define COBALT_LED_PORT (*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
100# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */ 75# define COBALT_LED_BAR_LEFT (1 << 0) /* Qube */
diff --git a/include/asm-mips/mach-cobalt/mach-gt64120.h b/include/asm-mips/mach-cobalt/mach-gt64120.h
index 587fc4378f44..ae9c5523c7ef 100644
--- a/include/asm-mips/mach-cobalt/mach-gt64120.h
+++ b/include/asm-mips/mach-cobalt/mach-gt64120.h
@@ -1 +1,27 @@
1/* there's something here ... in the dark */ 1/*
2 * Copyright (C) 2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef _COBALT_MACH_GT64120_H
19#define _COBALT_MACH_GT64120_H
20
21/*
22 * Cobalt uses GT64111. GT64111 is almost the same as GT64120.
23 */
24
25#define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE)
26
27#endif /* _COBALT_MACH_GT64120_H */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 1f318d707998..9985cb7c16e7 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -545,62 +545,6 @@
545#define MIPS_FPIR_L (_ULCAST_(1) << 21) 545#define MIPS_FPIR_L (_ULCAST_(1) << 21)
546#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 546#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
547 547
548/*
549 * R10000 performance counter definitions.
550 *
551 * FIXME: The R10000 performance counter opens a nice way to implement CPU
552 * time accounting with a precission of one cycle. I don't have
553 * R10000 silicon but just a manual, so ...
554 */
555
556/*
557 * Events counted by counter #0
558 */
559#define CE0_CYCLES 0
560#define CE0_INSN_ISSUED 1
561#define CE0_LPSC_ISSUED 2
562#define CE0_S_ISSUED 3
563#define CE0_SC_ISSUED 4
564#define CE0_SC_FAILED 5
565#define CE0_BRANCH_DECODED 6
566#define CE0_QW_WB_SECONDARY 7
567#define CE0_CORRECTED_ECC_ERRORS 8
568#define CE0_ICACHE_MISSES 9
569#define CE0_SCACHE_I_MISSES 10
570#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
571#define CE0_EXT_INTERVENTIONS_REQ 12
572#define CE0_EXT_INVALIDATE_REQ 13
573#define CE0_VIRTUAL_COHERENCY_COND 14
574#define CE0_INSN_GRADUATED 15
575
576/*
577 * Events counted by counter #1
578 */
579#define CE1_CYCLES 0
580#define CE1_INSN_GRADUATED 1
581#define CE1_LPSC_GRADUATED 2
582#define CE1_S_GRADUATED 3
583#define CE1_SC_GRADUATED 4
584#define CE1_FP_INSN_GRADUATED 5
585#define CE1_QW_WB_PRIMARY 6
586#define CE1_TLB_REFILL 7
587#define CE1_BRANCH_MISSPREDICTED 8
588#define CE1_DCACHE_MISS 9
589#define CE1_SCACHE_D_MISSES 10
590#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
591#define CE1_EXT_INTERVENTION_HITS 12
592#define CE1_EXT_INVALIDATE_REQ 13
593#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
594#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
595
596/*
597 * These flags define in which privilege mode the counters count events
598 */
599#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
600#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
601#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
602#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
603
604#ifndef __ASSEMBLY__ 548#ifndef __ASSEMBLY__
605 549
606/* 550/*
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 85b258ee7090..0dc1a45c27ed 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -34,7 +34,9 @@
34 34
35#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
36 36
37#include <linux/pfn.h>
37#include <asm/cpu-features.h> 38#include <asm/cpu-features.h>
39#include <asm/io.h>
38 40
39extern void clear_page(void * page); 41extern void clear_page(void * page);
40extern void copy_page(void * to, void * from); 42extern void copy_page(void * to, void * from);
@@ -134,8 +136,14 @@ typedef struct { unsigned long pgprot; } pgprot_t;
134/* to align the pointer to the (next) page boundary */ 136/* to align the pointer to the (next) page boundary */
135#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) 137#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
136 138
137#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) 139#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
138#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) 140#define __pa_page_offset(x) ((unsigned long)(x) < CKSEG0 ? PAGE_OFFSET : CKSEG0)
141#else
142#define __pa_page_offset(x) PAGE_OFFSET
143#endif
144#define __pa(x) ((unsigned long)(x) - __pa_page_offset(x))
145#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0))
146#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET))
139 147
140#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) 148#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
141 149
@@ -160,8 +168,8 @@ typedef struct { unsigned long pgprot; } pgprot_t;
160 168
161#endif 169#endif
162 170
163#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) 171#define virt_to_page(kaddr) pfn_to_page(PFN_DOWN(virt_to_phys(kaddr)))
164#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) 172#define virt_addr_valid(kaddr) pfn_valid(PFN_DOWN(virt_to_phys(kaddr)))
165 173
166#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ 174#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
167 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) 175 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index 7e7320300aa3..b9b1e86493ee 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -14,6 +14,7 @@
14#include <asm/addrspace.h> 14#include <asm/addrspace.h>
15#include <asm/page.h> 15#include <asm/page.h>
16#include <asm/cachectl.h> 16#include <asm/cachectl.h>
17#include <asm/fixmap.h>
17 18
18#include <asm-generic/pgtable-nopud.h> 19#include <asm-generic/pgtable-nopud.h>
19 20
@@ -103,6 +104,13 @@
103#define VMALLOC_START MAP_BASE 104#define VMALLOC_START MAP_BASE
104#define VMALLOC_END \ 105#define VMALLOC_END \
105 (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE) 106 (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
107#if defined(CONFIG_MODULES) && !defined(CONFIG_BUILD_ELF64) && \
108 VMALLOC_START != CKSSEG
109/* Load modules into 32bit-compatible segment. */
110#define MODULE_START CKSSEG
111#define MODULE_END (FIXADDR_START-2*PAGE_SIZE)
112extern pgd_t module_pg_dir[PTRS_PER_PGD];
113#endif
106 114
107#define pte_ERROR(e) \ 115#define pte_ERROR(e) \
108 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) 116 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
@@ -174,7 +182,12 @@ static inline void pud_clear(pud_t *pudp)
174#define __pmd_offset(address) pmd_index(address) 182#define __pmd_offset(address) pmd_index(address)
175 183
176/* to find an entry in a kernel page-table-directory */ 184/* to find an entry in a kernel page-table-directory */
185#ifdef MODULE_START
186#define pgd_offset_k(address) \
187 ((address) >= MODULE_START ? module_pg_dir : pgd_offset(&init_mm, 0UL))
188#else
177#define pgd_offset_k(address) pgd_offset(&init_mm, 0UL) 189#define pgd_offset_k(address) pgd_offset(&init_mm, 0UL)
190#endif
178 191
179#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 192#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
180#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) 193#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 1ca4d1e185c7..f2e1325fec6c 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -67,7 +67,7 @@ extern unsigned long empty_zero_page;
67extern unsigned long zero_page_mask; 67extern unsigned long zero_page_mask;
68 68
69#define ZERO_PAGE(vaddr) \ 69#define ZERO_PAGE(vaddr) \
70 (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))) 70 (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))))
71 71
72#define __HAVE_ARCH_MOVE_PTE 72#define __HAVE_ARCH_MOVE_PTE
73#define move_pte(pte, prot, old_addr, new_addr) \ 73#define move_pte(pte, prot, old_addr, new_addr) \
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 5f3a9075cd28..30bf555faeaa 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -80,8 +80,6 @@ struct pt_regs {
80#define instruction_pointer(regs) ((regs)->cp0_epc) 80#define instruction_pointer(regs) ((regs)->cp0_epc)
81#define profile_pc(regs) instruction_pointer(regs) 81#define profile_pc(regs) instruction_pointer(regs)
82 82
83extern void show_regs(struct pt_regs *);
84
85extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit); 83extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
86 84
87#endif 85#endif
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
index 625acd337bc3..a632cef830a2 100644
--- a/include/asm-mips/time.h
+++ b/include/asm-mips/time.h
@@ -21,6 +21,7 @@
21#include <linux/ptrace.h> 21#include <linux/ptrace.h>
22#include <linux/rtc.h> 22#include <linux/rtc.h>
23#include <linux/spinlock.h> 23#include <linux/spinlock.h>
24#include <linux/clocksource.h>
24 25
25extern spinlock_t rtc_lock; 26extern spinlock_t rtc_lock;
26 27
@@ -44,12 +45,10 @@ extern int (*mips_timer_state)(void);
44extern void (*mips_timer_ack)(void); 45extern void (*mips_timer_ack)(void);
45 46
46/* 47/*
47 * High precision timer functions. 48 * High precision timer clocksource.
48 * If mips_hpt_read is NULL, an R4k-compatible timer setup is attempted. 49 * If .read is NULL, an R4k-compatible timer setup is attempted.
49 */ 50 */
50extern unsigned int (*mips_hpt_read)(void); 51extern struct clocksource clocksource_mips;
51extern void (*mips_hpt_init)(void);
52extern unsigned int mips_hpt_mask;
53 52
54/* 53/*
55 * to_tm() converts system time back to (year, mon, day, hour, min, sec). 54 * to_tm() converts system time back to (year, mon, day, hour, min, sec).
diff --git a/include/linux/kexec.h b/include/linux/kexec.h
index 6427949ddf99..a4ede62b339d 100644
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -122,6 +122,8 @@ extern struct kimage *kexec_crash_image;
122#define KEXEC_ARCH_IA_64 (50 << 16) 122#define KEXEC_ARCH_IA_64 (50 << 16)
123#define KEXEC_ARCH_S390 (22 << 16) 123#define KEXEC_ARCH_S390 (22 << 16)
124#define KEXEC_ARCH_SH (42 << 16) 124#define KEXEC_ARCH_SH (42 << 16)
125#define KEXEC_ARCH_MIPS_LE (10 << 16)
126#define KEXEC_ARCH_MIPS ( 8 << 16)
125 127
126#define KEXEC_FLAGS (KEXEC_ON_CRASH) /* List of defined/legal kexec flags */ 128#define KEXEC_FLAGS (KEXEC_ON_CRASH) /* List of defined/legal kexec flags */
127 129
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 15:13:27 -0500