diff options
-rw-r--r-- | drivers/net/tg3.c | 36 | ||||
-rw-r--r-- | drivers/net/tg3.h | 8 |
2 files changed, 38 insertions, 6 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index b865c5d44837..ef849b1eb110 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -8701,7 +8701,9 @@ static void tg3_get_ethtool_stats (struct net_device *dev, | |||
8701 | } | 8701 | } |
8702 | 8702 | ||
8703 | #define NVRAM_TEST_SIZE 0x100 | 8703 | #define NVRAM_TEST_SIZE 0x100 |
8704 | #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14 | 8704 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
8705 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | ||
8706 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | ||
8705 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 | 8707 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
8706 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | 8708 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c |
8707 | 8709 | ||
@@ -8716,9 +8718,22 @@ static int tg3_test_nvram(struct tg3 *tp) | |||
8716 | if (magic == TG3_EEPROM_MAGIC) | 8718 | if (magic == TG3_EEPROM_MAGIC) |
8717 | size = NVRAM_TEST_SIZE; | 8719 | size = NVRAM_TEST_SIZE; |
8718 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { | 8720 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
8719 | if ((magic & 0xe00000) == 0x200000) | 8721 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
8720 | size = NVRAM_SELFBOOT_FORMAT1_SIZE; | 8722 | TG3_EEPROM_SB_FORMAT_1) { |
8721 | else | 8723 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { |
8724 | case TG3_EEPROM_SB_REVISION_0: | ||
8725 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | ||
8726 | break; | ||
8727 | case TG3_EEPROM_SB_REVISION_2: | ||
8728 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | ||
8729 | break; | ||
8730 | case TG3_EEPROM_SB_REVISION_3: | ||
8731 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | ||
8732 | break; | ||
8733 | default: | ||
8734 | return 0; | ||
8735 | } | ||
8736 | } else | ||
8722 | return 0; | 8737 | return 0; |
8723 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) | 8738 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
8724 | size = NVRAM_SELFBOOT_HW_SIZE; | 8739 | size = NVRAM_SELFBOOT_HW_SIZE; |
@@ -8745,8 +8760,17 @@ static int tg3_test_nvram(struct tg3 *tp) | |||
8745 | TG3_EEPROM_MAGIC_FW) { | 8760 | TG3_EEPROM_MAGIC_FW) { |
8746 | u8 *buf8 = (u8 *) buf, csum8 = 0; | 8761 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
8747 | 8762 | ||
8748 | for (i = 0; i < size; i++) | 8763 | if ((cpu_to_be32(buf[0]) & TG3_EEPROM_SB_REVISION_MASK) == |
8749 | csum8 += buf8[i]; | 8764 | TG3_EEPROM_SB_REVISION_2) { |
8765 | /* For rev 2, the csum doesn't include the MBA. */ | ||
8766 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | ||
8767 | csum8 += buf8[i]; | ||
8768 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | ||
8769 | csum8 += buf8[i]; | ||
8770 | } else { | ||
8771 | for (i = 0; i < size; i++) | ||
8772 | csum8 += buf8[i]; | ||
8773 | } | ||
8750 | 8774 | ||
8751 | if (csum8 == 0) { | 8775 | if (csum8 == 0) { |
8752 | err = 0; | 8776 | err = 0; |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index c6aad49a375d..f715b35dfd54 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -1555,6 +1555,12 @@ | |||
1555 | #define TG3_EEPROM_MAGIC 0x669955aa | 1555 | #define TG3_EEPROM_MAGIC 0x669955aa |
1556 | #define TG3_EEPROM_MAGIC_FW 0xa5000000 | 1556 | #define TG3_EEPROM_MAGIC_FW 0xa5000000 |
1557 | #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000 | 1557 | #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000 |
1558 | #define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000 | ||
1559 | #define TG3_EEPROM_SB_FORMAT_1 0x00200000 | ||
1560 | #define TG3_EEPROM_SB_REVISION_MASK 0x001f0000 | ||
1561 | #define TG3_EEPROM_SB_REVISION_0 0x00000000 | ||
1562 | #define TG3_EEPROM_SB_REVISION_2 0x00020000 | ||
1563 | #define TG3_EEPROM_SB_REVISION_3 0x00030000 | ||
1558 | #define TG3_EEPROM_MAGIC_HW 0xabcd | 1564 | #define TG3_EEPROM_MAGIC_HW 0xabcd |
1559 | #define TG3_EEPROM_MAGIC_HW_MSK 0xffff | 1565 | #define TG3_EEPROM_MAGIC_HW_MSK 0xffff |
1560 | 1566 | ||
@@ -1765,6 +1771,8 @@ | |||
1765 | /* APE convenience enumerations. */ | 1771 | /* APE convenience enumerations. */ |
1766 | #define TG3_APE_LOCK_MEM 4 | 1772 | #define TG3_APE_LOCK_MEM 4 |
1767 | 1773 | ||
1774 | #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 | ||
1775 | |||
1768 | 1776 | ||
1769 | /* There are two ways to manage the TX descriptors on the tigon3. | 1777 | /* There are two ways to manage the TX descriptors on the tigon3. |
1770 | * Either the descriptors are in host DMA'able memory, or they | 1778 | * Either the descriptors are in host DMA'able memory, or they |