diff options
-rw-r--r-- | drivers/video/omap2/dss/dss.h | 18 | ||||
-rw-r--r-- | drivers/video/omap2/dss/hdmi.c | 1 | ||||
-rw-r--r-- | drivers/video/omap2/dss/hdmi.h | 53 | ||||
-rw-r--r-- | drivers/video/omap2/dss/ti_hdmi.h | 94 |
4 files changed, 95 insertions, 71 deletions
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h index 6aeb1f5505d0..d790580a6a3b 100644 --- a/drivers/video/omap2/dss/dss.h +++ b/drivers/video/omap2/dss/dss.h | |||
@@ -155,24 +155,6 @@ struct dsi_clock_info { | |||
155 | bool use_sys_clk; | 155 | bool use_sys_clk; |
156 | }; | 156 | }; |
157 | 157 | ||
158 | enum hdmi_clk_refsel { | ||
159 | HDMI_REFSEL_PCLK = 0, | ||
160 | HDMI_REFSEL_REF1 = 1, | ||
161 | HDMI_REFSEL_REF2 = 2, | ||
162 | HDMI_REFSEL_SYSCLK = 3 | ||
163 | }; | ||
164 | |||
165 | /* HDMI PLL structure */ | ||
166 | struct hdmi_pll_info { | ||
167 | u16 regn; | ||
168 | u16 regm; | ||
169 | u32 regmf; | ||
170 | u16 regm2; | ||
171 | u16 regsd; | ||
172 | u16 dcofreq; | ||
173 | enum hdmi_clk_refsel refsel; | ||
174 | }; | ||
175 | |||
176 | struct seq_file; | 158 | struct seq_file; |
177 | struct platform_device; | 159 | struct platform_device; |
178 | 160 | ||
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c index c387bf47ee0e..bf76c87024b2 100644 --- a/drivers/video/omap2/dss/hdmi.c +++ b/drivers/video/omap2/dss/hdmi.c | |||
@@ -39,6 +39,7 @@ | |||
39 | #include <sound/pcm_params.h> | 39 | #include <sound/pcm_params.h> |
40 | #endif | 40 | #endif |
41 | 41 | ||
42 | #include "ti_hdmi.h" | ||
42 | #include "dss.h" | 43 | #include "dss.h" |
43 | #include "hdmi.h" | 44 | #include "hdmi.h" |
44 | #include "dss_features.h" | 45 | #include "dss_features.h" |
diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h index 02342f6395c2..cb50f6a3ad09 100644 --- a/drivers/video/omap2/dss/hdmi.h +++ b/drivers/video/omap2/dss/hdmi.h | |||
@@ -198,39 +198,12 @@ struct hdmi_reg { u16 idx; }; | |||
198 | #define REG_GET(base, idx, start, end) \ | 198 | #define REG_GET(base, idx, start, end) \ |
199 | FLD_GET(hdmi_read_reg(base, idx), start, end) | 199 | FLD_GET(hdmi_read_reg(base, idx), start, end) |
200 | 200 | ||
201 | struct hdmi_video_timings { | ||
202 | u16 x_res; | ||
203 | u16 y_res; | ||
204 | /* Unit: KHz */ | ||
205 | u32 pixel_clock; | ||
206 | u16 hsw; | ||
207 | u16 hfp; | ||
208 | u16 hbp; | ||
209 | u16 vsw; | ||
210 | u16 vfp; | ||
211 | u16 vbp; | ||
212 | }; | ||
213 | |||
214 | /* HDMI timing structure */ | ||
215 | struct hdmi_timings { | ||
216 | struct hdmi_video_timings timings; | ||
217 | int vsync_pol; | ||
218 | int hsync_pol; | ||
219 | }; | ||
220 | |||
221 | enum hdmi_phy_pwr { | 201 | enum hdmi_phy_pwr { |
222 | HDMI_PHYPWRCMD_OFF = 0, | 202 | HDMI_PHYPWRCMD_OFF = 0, |
223 | HDMI_PHYPWRCMD_LDOON = 1, | 203 | HDMI_PHYPWRCMD_LDOON = 1, |
224 | HDMI_PHYPWRCMD_TXON = 2 | 204 | HDMI_PHYPWRCMD_TXON = 2 |
225 | }; | 205 | }; |
226 | 206 | ||
227 | enum hdmi_pll_pwr { | ||
228 | HDMI_PLLPWRCMD_ALLOFF = 0, | ||
229 | HDMI_PLLPWRCMD_PLLONLY = 1, | ||
230 | HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, | ||
231 | HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 | ||
232 | }; | ||
233 | |||
234 | enum hdmi_core_inputbus_width { | 207 | enum hdmi_core_inputbus_width { |
235 | HDMI_INPUT_8BIT = 0, | 208 | HDMI_INPUT_8BIT = 0, |
236 | HDMI_INPUT_10BIT = 1, | 209 | HDMI_INPUT_10BIT = 1, |
@@ -259,11 +232,6 @@ enum hdmi_core_packet_mode { | |||
259 | HDMI_PACKETMODE48BITPERPIXEL = 7 | 232 | HDMI_PACKETMODE48BITPERPIXEL = 7 |
260 | }; | 233 | }; |
261 | 234 | ||
262 | enum hdmi_core_hdmi_dvi { | ||
263 | HDMI_DVI = 0, | ||
264 | HDMI_HDMI = 1 | ||
265 | }; | ||
266 | |||
267 | enum hdmi_core_tclkselclkmult { | 235 | enum hdmi_core_tclkselclkmult { |
268 | HDMI_FPLL05IDCK = 0, | 236 | HDMI_FPLL05IDCK = 0, |
269 | HDMI_FPLL10IDCK = 1, | 237 | HDMI_FPLL10IDCK = 1, |
@@ -564,27 +532,6 @@ struct hdmi_video_interface { | |||
564 | int tm; /* Timing mode */ | 532 | int tm; /* Timing mode */ |
565 | }; | 533 | }; |
566 | 534 | ||
567 | struct hdmi_cm { | ||
568 | int code; | ||
569 | int mode; | ||
570 | }; | ||
571 | |||
572 | struct hdmi_config { | ||
573 | struct hdmi_timings timings; | ||
574 | u16 interlace; | ||
575 | struct hdmi_cm cm; | ||
576 | }; | ||
577 | |||
578 | struct hdmi_ip_data { | ||
579 | void __iomem *base_wp; /* HDMI wrapper */ | ||
580 | unsigned long core_sys_offset; | ||
581 | unsigned long core_av_offset; | ||
582 | unsigned long pll_offset; | ||
583 | unsigned long phy_offset; | ||
584 | struct hdmi_config cfg; | ||
585 | struct hdmi_pll_info pll_data; | ||
586 | }; | ||
587 | |||
588 | struct hdmi_audio_format { | 535 | struct hdmi_audio_format { |
589 | enum hdmi_stereo_channels stereo_channels; | 536 | enum hdmi_stereo_channels stereo_channels; |
590 | u8 active_chnnls_msk; | 537 | u8 active_chnnls_msk; |
diff --git a/drivers/video/omap2/dss/ti_hdmi.h b/drivers/video/omap2/dss/ti_hdmi.h new file mode 100644 index 000000000000..f0e508ec28d1 --- /dev/null +++ b/drivers/video/omap2/dss/ti_hdmi.h | |||
@@ -0,0 +1,94 @@ | |||
1 | /* | ||
2 | * ti_hdmi.h | ||
3 | * | ||
4 | * HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor. | ||
5 | * | ||
6 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License version 2 as published by | ||
10 | * the Free Software Foundation. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License along with | ||
18 | * this program. If not, see <http://www.gnu.org/licenses/>. | ||
19 | */ | ||
20 | |||
21 | #ifndef _TI_HDMI_H | ||
22 | #define _TI_HDMI_H | ||
23 | |||
24 | enum hdmi_pll_pwr { | ||
25 | HDMI_PLLPWRCMD_ALLOFF = 0, | ||
26 | HDMI_PLLPWRCMD_PLLONLY = 1, | ||
27 | HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, | ||
28 | HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 | ||
29 | }; | ||
30 | |||
31 | enum hdmi_core_hdmi_dvi { | ||
32 | HDMI_DVI = 0, | ||
33 | HDMI_HDMI = 1 | ||
34 | }; | ||
35 | |||
36 | enum hdmi_clk_refsel { | ||
37 | HDMI_REFSEL_PCLK = 0, | ||
38 | HDMI_REFSEL_REF1 = 1, | ||
39 | HDMI_REFSEL_REF2 = 2, | ||
40 | HDMI_REFSEL_SYSCLK = 3 | ||
41 | }; | ||
42 | |||
43 | struct hdmi_video_timings { | ||
44 | u16 x_res; | ||
45 | u16 y_res; | ||
46 | /* Unit: KHz */ | ||
47 | u32 pixel_clock; | ||
48 | u16 hsw; | ||
49 | u16 hfp; | ||
50 | u16 hbp; | ||
51 | u16 vsw; | ||
52 | u16 vfp; | ||
53 | u16 vbp; | ||
54 | }; | ||
55 | |||
56 | /* HDMI timing structure */ | ||
57 | struct hdmi_timings { | ||
58 | struct hdmi_video_timings timings; | ||
59 | int vsync_pol; | ||
60 | int hsync_pol; | ||
61 | }; | ||
62 | |||
63 | struct hdmi_cm { | ||
64 | int code; | ||
65 | int mode; | ||
66 | }; | ||
67 | |||
68 | struct hdmi_config { | ||
69 | struct hdmi_timings timings; | ||
70 | u16 interlace; | ||
71 | struct hdmi_cm cm; | ||
72 | }; | ||
73 | |||
74 | /* HDMI PLL structure */ | ||
75 | struct hdmi_pll_info { | ||
76 | u16 regn; | ||
77 | u16 regm; | ||
78 | u32 regmf; | ||
79 | u16 regm2; | ||
80 | u16 regsd; | ||
81 | u16 dcofreq; | ||
82 | enum hdmi_clk_refsel refsel; | ||
83 | }; | ||
84 | |||
85 | struct hdmi_ip_data { | ||
86 | void __iomem *base_wp; /* HDMI wrapper */ | ||
87 | unsigned long core_sys_offset; | ||
88 | unsigned long core_av_offset; | ||
89 | unsigned long pll_offset; | ||
90 | unsigned long phy_offset; | ||
91 | struct hdmi_config cfg; | ||
92 | struct hdmi_pll_info pll_data; | ||
93 | }; | ||
94 | #endif | ||