34 files changed, 499 insertions, 288 deletions

diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 5cfade235bb4..6f58cad5bf74 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -34,9 +34,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "gpmc-smsc911x.h"
-#include "gpmc.h"
-#include <plat/sdrc.h>
 #include <plat/usb.h>
 
 #include "common.h"
@@ -44,6 +41,8 @@
 #include "hsmmc.h"
 #include "control.h"
 #include "common-board-devices.h"
+#include "gpmc.h"
+#include "gpmc-smsc911x.h"
 
 #define OMAP3LOGIC_SMSC911X_CS                  1
 
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 4ae439222085..35076592189e 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -27,13 +27,13 @@
 
 #include <plat/clock.h>
 #include <plat/sram.h>
-#include <plat/sdrc.h>
 
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
+#include "sdrc.h"
 
 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
 
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 3524f0e7b6d5..0cf63e7c6102 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -35,7 +35,6 @@
 
 #include <plat/clock.h>
 #include <plat/sram.h>
-#include <plat/sdrc.h>
 
 #include "soc.h"
 #include "clock.h"
@@ -43,6 +42,7 @@
 #include "opp2xxx.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
+#include "sdrc.h"
 
 const struct prcm_config *curr_prcm_set;
 const struct prcm_config *rate_table;
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 7c6da2f731dc..aff6ca4fd3a4 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -23,7 +23,6 @@
 
 #include <plat/clock.h>
 #include <plat/sram.h>
-#include <plat/sdrc.h>
 
 #include "clock.h"
 #include "clock3xxx.h"
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index d1ff8399a222..bf2be5c5468d 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -1,7 +1,7 @@
 /*
  * OMAP2/3 System Control Module register access
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
+ * Copyright (C) 2007, 2012 Texas Instruments, Inc.
  * Copyright (C) 2007 Nokia Corporation
  *
  * Written by Paul Walmsley
@@ -15,8 +15,6 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 
-#include <plat/sdrc.h>
-
 #include "soc.h"
 #include "iomap.h"
 #include "common.h"
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 1011995f150a..28f508724a56 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -284,6 +284,35 @@ err:
         return ERR_PTR(r);
 }
 
+static enum omapdss_version __init omap_display_get_version(void)
+{
+        if (cpu_is_omap24xx())
+                return OMAPDSS_VER_OMAP24xx;
+        else if (cpu_is_omap3630())
+                return OMAPDSS_VER_OMAP3630;
+        else if (cpu_is_omap34xx()) {
+                if (soc_is_am35xx()) {
+                        return OMAPDSS_VER_AM35xx;
+                } else {
+                        if (omap_rev() < OMAP3430_REV_ES3_0)
+                                return OMAPDSS_VER_OMAP34xx_ES1;
+                        else
+                                return OMAPDSS_VER_OMAP34xx_ES3;
+                }
+        } else if (omap_rev() == OMAP4430_REV_ES1_0)
+                return OMAPDSS_VER_OMAP4430_ES1;
+        else if (omap_rev() == OMAP4430_REV_ES2_0 ||
+                        omap_rev() == OMAP4430_REV_ES2_1 ||
+                        omap_rev() == OMAP4430_REV_ES2_2)
+                return OMAPDSS_VER_OMAP4430_ES2;
+        else if (cpu_is_omap44xx())
+                return OMAPDSS_VER_OMAP4;
+        else if (soc_is_omap54xx())
+                return OMAPDSS_VER_OMAP5;
+        else
+                return OMAPDSS_VER_UNKNOWN;
+}
+
 int __init omap_display_init(struct omap_dss_board_info *board_data)
 {
         int r = 0;
@@ -291,9 +320,18 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
         int i, oh_count;
         const struct omap_dss_hwmod_data *curr_dss_hwmod;
         struct platform_device *dss_pdev;
+        enum omapdss_version ver;
 
         /* create omapdss device */
 
+        ver = omap_display_get_version();
+
+        if (ver == OMAPDSS_VER_UNKNOWN) {
+                pr_err("DSS not supported on this SoC\n");
+                return -ENODEV;
+        }
+
+        board_data->version = ver;
         board_data->dsi_enable_pads = omap_dsi_enable_pads;
         board_data->dsi_disable_pads = omap_dsi_disable_pads;
         board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index f14bd3f55218..9472541a4d8d 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -31,7 +31,6 @@
 #include <asm/mach-types.h>
 
 #include <plat/cpu.h>
-#include <plat/sdrc.h>
 #include <plat/omap_device.h>
 
 #include "soc.h"
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 42a4b9c08aaa..f71e51bfbe2a 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -26,7 +26,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/sram.h>
-#include <plat/sdrc.h>
 #include <plat/serial.h>
 #include <plat/omap-pm.h>
 #include <plat/omap_hwmod.h>
@@ -43,6 +42,7 @@
 #include "clock2xxx.h"
 #include "clock3xxx.h"
 #include "clock44xx.h"
+#include "sdrc.h"
 
 /*
  * The machine specific code may provide the extra mapping besides the
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 001eff290cdb..bbe15cb1b874 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -38,7 +38,6 @@
 #include <plat/sram.h>
 #include "clockdomain.h"
 #include "powerdomain.h"
-#include <plat/sdrc.h>
 #include <plat/prcm.h>
 #include <plat-omap/dma-omap.h>
 
diff --git a/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h b/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
index 8bfaf342a028..1ee58c281a31 100644
--- a/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
+++ b/arch/arm/mach-omap2/sdram-hynix-h8mbx00u0mer-0em.h
@@ -11,7 +11,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
 #define __ARCH_ARM_MACH_OMAP2_SDRAM_HYNIX_H8MBX00U0MER0EM
 
-#include <plat/sdrc.h>
+#include "sdrc.h"
 
 /* Hynix H8MBX00U0MER-0EM */
 static struct omap_sdrc_params h8mbx00u0mer0em_sdrc_params[] = {
diff --git a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
index a391b4939f74..85cccc004c06 100644
--- a/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
+++ b/arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h
@@ -14,7 +14,7 @@
 #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
 #define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
 
-#include <plat/sdrc.h>
+#include "sdrc.h"
 
 /* Micron MT46H32M32LF-6 */
 /* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c
index 845c4fd2b125..5e5702cd410d 100644
--- a/arch/arm/mach-omap2/sdram-nokia.c
+++ b/arch/arm/mach-omap2/sdram-nokia.c
@@ -19,9 +19,9 @@
 
 #include "common.h"
 #include <plat/clock.h>
-#include <plat/sdrc.h>
 
 #include "sdram-nokia.h"
+#include "sdrc.h"
 
 /* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
 struct sdram_timings {
diff --git a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
index cd4352917022..003f7bf4e2e3 100644
--- a/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
+++ b/arch/arm/mach-omap2/sdram-numonyx-m65kxxxxam.h
@@ -11,7 +11,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
 #define __ARCH_ARM_MACH_OMAP2_SDRAM_NUMONYX_M65KXXXXAM
 
-#include <plat/sdrc.h>
+#include "sdrc.h"
 
 /* Numonyx  M65KXXXXAM */
 static struct omap_sdrc_params m65kxxxxam_sdrc_params[] = {
diff --git a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
index 0e518a72831f..8dc3de5ebb5b 100644
--- a/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
+++ b/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h
@@ -14,7 +14,7 @@
 #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
 #define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
 
-#include <plat/sdrc.h>
+#include "sdrc.h"
 
 /* Qimonda HYB18M512160AF-6 */
 static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index e3d345f46409..761a781a99c5 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -27,7 +27,6 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 
-#include <plat/sdrc.h>
 #include "sdrc.h"
 
 static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
@@ -160,19 +159,3 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
         sdrc_write_reg(l, SDRC_POWER);
         omap2_sms_save_context();
 }
-
-void omap2_sms_write_rot_control(u32 val, unsigned ctx)
-{
-        sms_write_reg(val, SMS_ROT_CONTROL(ctx));
-}
-
-void omap2_sms_write_rot_size(u32 val, unsigned ctx)
-{
-        sms_write_reg(val, SMS_ROT_SIZE(ctx));
-}
-
-void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx)
-{
-        sms_write_reg(val, SMS_ROT_PHYSICAL_BA(ctx));
-}
-
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index b3f83799e6cf..69c4b329452e 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -2,12 +2,14 @@
 #define __ARCH_ARM_MACH_OMAP2_SDRC_H
 
 /*
- * OMAP2 SDRC register definitions
+ * OMAP2/3 SDRC/SMS macros and prototypes
  *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Copyright (C) 2007 Nokia Corporation
+ * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
+ * Copyright (C) 2007-2008 Nokia Corporation
  *
- * Written by Paul Walmsley
+ * Paul Walmsley
+ * Tony Lindgren
+ * Richard Woodruff
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -15,8 +17,6 @@
  */
 #undef DEBUG
 
-#include <plat/sdrc.h>
-
 #ifndef __ASSEMBLER__
 
 #include <linux/io.h>
@@ -50,6 +50,58 @@ static inline u32 sms_read_reg(u16 reg)
 {
         return __raw_readl(OMAP_SMS_REGADDR(reg));
 }
+
+
+/**
+ * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
+ * @rate: SDRC clock rate (in Hz)
+ * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
+ * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
+ * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
+ * @mr: Value to program to SDRC_MR for this rate
+ *
+ * This structure holds a pre-computed set of register values for the
+ * SDRC for a given SDRC clock rate and SDRAM chip.  These are
+ * intended to be pre-computed and specified in an array in the board-*.c
+ * files.  The structure is keyed off the 'rate' field.
+ */
+struct omap_sdrc_params {
+        unsigned long rate;
+        u32 actim_ctrla;
+        u32 actim_ctrlb;
+        u32 rfr_ctrl;
+        u32 mr;
+};
+
+#ifdef CONFIG_SOC_HAS_OMAP2_SDRC
+void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                            struct omap_sdrc_params *sdrc_cs1);
+#else
+static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                                          struct omap_sdrc_params *sdrc_cs1) {};
+#endif
+
+int omap2_sdrc_get_params(unsigned long r,
+                          struct omap_sdrc_params **sdrc_cs0,
+                          struct omap_sdrc_params **sdrc_cs1);
+void omap2_sms_save_context(void);
+void omap2_sms_restore_context(void);
+
+struct memory_timings {
+        u32 m_type;             /* ddr = 1, sdr = 0 */
+        u32 dll_mode;           /* use lock mode = 1, unlock mode = 0 */
+        u32 slow_dll_ctrl;      /* unlock mode, dll value for slow speed */
+        u32 fast_dll_ctrl;      /* unlock mode, dll value for fast speed */
+        u32 base_cs;            /* base chip select to use for calculations */
+};
+
+extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
+struct omap_sdrc_params *rx51_get_sdram_timings(void);
+
+u32 omap2xxx_sdrc_dll_is_unlocked(void);
+u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
+
+
 #else
 #define OMAP242X_SDRC_REGADDR(reg)                                      \
                         OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
@@ -57,6 +109,7 @@ static inline u32 sms_read_reg(u16 reg)
                         OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
 #define OMAP34XX_SDRC_REGADDR(reg)                                      \
                         OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
+
 #endif  /* __ASSEMBLER__ */
 
 /* Minimum frequency that the SDRC DLL can lock at */
@@ -74,4 +127,85 @@ static inline u32 sms_read_reg(u16 reg)
  */
 #define SDRC_MPURATE_LOOPS              96
 
+/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
+
+#define SDRC_SYSCONFIG          0x010
+#define SDRC_CS_CFG             0x040
+#define SDRC_SHARING            0x044
+#define SDRC_ERR_TYPE           0x04C
+#define SDRC_DLLA_CTRL          0x060
+#define SDRC_DLLA_STATUS        0x064
+#define SDRC_DLLB_CTRL          0x068
+#define SDRC_DLLB_STATUS        0x06C
+#define SDRC_POWER              0x070
+#define SDRC_MCFG_0             0x080
+#define SDRC_MR_0               0x084
+#define SDRC_EMR2_0             0x08c
+#define SDRC_ACTIM_CTRL_A_0     0x09c
+#define SDRC_ACTIM_CTRL_B_0     0x0a0
+#define SDRC_RFR_CTRL_0         0x0a4
+#define SDRC_MANUAL_0           0x0a8
+#define SDRC_MCFG_1             0x0B0
+#define SDRC_MR_1               0x0B4
+#define SDRC_EMR2_1             0x0BC
+#define SDRC_ACTIM_CTRL_A_1     0x0C4
+#define SDRC_ACTIM_CTRL_B_1     0x0C8
+#define SDRC_RFR_CTRL_1         0x0D4
+#define SDRC_MANUAL_1           0x0D8
+
+#define SDRC_POWER_AUTOCOUNT_SHIFT      8
+#define SDRC_POWER_AUTOCOUNT_MASK       (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
+#define SDRC_POWER_CLKCTRL_SHIFT        4
+#define SDRC_POWER_CLKCTRL_MASK         (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
+#define SDRC_SELF_REFRESH_ON_AUTOCOUNT  (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
+
+/*
+ * These values represent the number of memory clock cycles between
+ * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
+ * rows per device, and include a subtraction of a 50 cycle window in the
+ * event that the autorefresh command is delayed due to other SDRC activity.
+ * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
+ * counter reaches 0.
+ *
+ * These represent optimal values for common parts, it won't work for all.
+ * As long as you scale down, most parameters are still work, they just
+ * become sub-optimal. The RFR value goes in the opposite direction. If you
+ * don't adjust it down as your clock period increases the refresh interval
+ * will not be met. Setting all parameters for complete worst case may work,
+ * but may cut memory performance by 2x. Due to errata the DLLs need to be
+ * unlocked and their value needs run time calibration. A dynamic call is
+ * need for that as no single right value exists acorss production samples.
+ *
+ * Only the FULL speed values are given. Current code is such that rate
+ * changes must be made at DPLLoutx2. The actual value adjustment for low
+ * frequency operation will be handled by omap_set_performance()
+ *
+ * By having the boot loader boot up in the fastest L4 speed available likely
+ * will result in something which you can switch between.
+ */
+#define SDRC_RFR_CTRL_165MHz    (0x00044c00 | 1)
+#define SDRC_RFR_CTRL_133MHz    (0x0003de00 | 1)
+#define SDRC_RFR_CTRL_100MHz    (0x0002da01 | 1)
+#define SDRC_RFR_CTRL_110MHz    (0x0002da01 | 1) /* Need to calc */
+#define SDRC_RFR_CTRL_BYPASS    (0x00005000 | 1) /* Need to calc */
+
+
+/*
+ * SMS register access
+ */
+
+#define OMAP242X_SMS_REGADDR(reg)                                       \
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
+#define OMAP243X_SMS_REGADDR(reg)                                       \
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
+#define OMAP343X_SMS_REGADDR(reg)                                       \
+                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
+
+/* SMS register offsets - read/write with sms_{read,write}_reg() */
+
+#define SMS_SYSCONFIG                   0x010
+/* REVISIT: fill in other SMS registers here */
+
+
+
 #endif
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 73e55e485329..f7074ff1d084 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -26,7 +26,6 @@
 
 #include <plat/clock.h>
 #include <plat/sram.h>
-#include <plat/sdrc.h>
 
 #include "soc.h"
 #include "iomap.h"
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index bcbb9d5dc293..f868caeedfd6 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -33,6 +33,67 @@
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 
+#include <plat/cpu.h>
+
+#ifdef CONFIG_OMAP2_VRFB
+
+/*
+ * The first memory resource is the register region for VRFB,
+ * the rest are VRFB virtual memory areas for each VRFB context.
+ */
+
+static const struct resource omap2_vrfb_resources[] = {
+        DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
+        DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
+        DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
+        DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
+        DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
+};
+
+static const struct resource omap3_vrfb_resources[] = {
+        DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
+        DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
+        DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
+        DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
+        DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
+        DEFINE_RES_MEM_NAMED(0xe0000000u, 0x4000000, "vrfb-area-4"),
+        DEFINE_RES_MEM_NAMED(0xe4000000u, 0x4000000, "vrfb-area-5"),
+        DEFINE_RES_MEM_NAMED(0xe8000000u, 0x4000000, "vrfb-area-6"),
+        DEFINE_RES_MEM_NAMED(0xec000000u, 0x4000000, "vrfb-area-7"),
+        DEFINE_RES_MEM_NAMED(0xf0000000u, 0x4000000, "vrfb-area-8"),
+        DEFINE_RES_MEM_NAMED(0xf4000000u, 0x4000000, "vrfb-area-9"),
+        DEFINE_RES_MEM_NAMED(0xf8000000u, 0x4000000, "vrfb-area-10"),
+        DEFINE_RES_MEM_NAMED(0xfc000000u, 0x4000000, "vrfb-area-11"),
+};
+
+static int __init omap_init_vrfb(void)
+{
+        struct platform_device *pdev;
+        const struct resource *res;
+        unsigned int num_res;
+
+        if (cpu_is_omap24xx()) {
+                res = omap2_vrfb_resources;
+                num_res = ARRAY_SIZE(omap2_vrfb_resources);
+        } else if (cpu_is_omap34xx()) {
+                res = omap3_vrfb_resources;
+                num_res = ARRAY_SIZE(omap3_vrfb_resources);
+        } else {
+                return 0;
+        }
+
+        pdev = platform_device_register_resndata(NULL, "omapvrfb", -1,
+                        res, num_res, NULL, 0);
+
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+        else
+                return 0;
+}
+
+arch_initcall(omap_init_vrfb);
+#endif
+
 #if defined(CONFIG_FB_OMAP) || defined(CONFIG_FB_OMAP_MODULE)
 
 static bool omapfb_lcd_configured;
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
deleted file mode 100644
index 36d6a7666216..000000000000
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ /dev/null
@@ -1,164 +0,0 @@
-#ifndef ____ASM_ARCH_SDRC_H
-#define ____ASM_ARCH_SDRC_H
-
-/*
- * OMAP2/3 SDRC/SMS register definitions
- *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
- *
- * Tony Lindgren
- * Paul Walmsley
- * Richard Woodruff
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-
-/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
-
-#define SDRC_SYSCONFIG          0x010
-#define SDRC_CS_CFG             0x040
-#define SDRC_SHARING            0x044
-#define SDRC_ERR_TYPE           0x04C
-#define SDRC_DLLA_CTRL          0x060
-#define SDRC_DLLA_STATUS        0x064
-#define SDRC_DLLB_CTRL          0x068
-#define SDRC_DLLB_STATUS        0x06C
-#define SDRC_POWER              0x070
-#define SDRC_MCFG_0             0x080
-#define SDRC_MR_0               0x084
-#define SDRC_EMR2_0             0x08c
-#define SDRC_ACTIM_CTRL_A_0     0x09c
-#define SDRC_ACTIM_CTRL_B_0     0x0a0
-#define SDRC_RFR_CTRL_0         0x0a4
-#define SDRC_MANUAL_0           0x0a8
-#define SDRC_MCFG_1             0x0B0
-#define SDRC_MR_1               0x0B4
-#define SDRC_EMR2_1             0x0BC
-#define SDRC_ACTIM_CTRL_A_1     0x0C4
-#define SDRC_ACTIM_CTRL_B_1     0x0C8
-#define SDRC_RFR_CTRL_1         0x0D4
-#define SDRC_MANUAL_1           0x0D8
-
-#define SDRC_POWER_AUTOCOUNT_SHIFT      8
-#define SDRC_POWER_AUTOCOUNT_MASK       (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
-#define SDRC_POWER_CLKCTRL_SHIFT        4
-#define SDRC_POWER_CLKCTRL_MASK         (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
-#define SDRC_SELF_REFRESH_ON_AUTOCOUNT  (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
-
-/*
- * These values represent the number of memory clock cycles between
- * autorefresh initiation.  They assume 1 refresh per 64 ms (JEDEC), 8192
- * rows per device, and include a subtraction of a 50 cycle window in the
- * event that the autorefresh command is delayed due to other SDRC activity.
- * The '| 1' sets the ARE field to send one autorefresh when the autorefresh
- * counter reaches 0.
- *
- * These represent optimal values for common parts, it won't work for all.
- * As long as you scale down, most parameters are still work, they just
- * become sub-optimal. The RFR value goes in the opposite direction. If you
- * don't adjust it down as your clock period increases the refresh interval
- * will not be met. Setting all parameters for complete worst case may work,
- * but may cut memory performance by 2x. Due to errata the DLLs need to be
- * unlocked and their value needs run time calibration. A dynamic call is
- * need for that as no single right value exists acorss production samples.
- *
- * Only the FULL speed values are given. Current code is such that rate
- * changes must be made at DPLLoutx2. The actual value adjustment for low
- * frequency operation will be handled by omap_set_performance()
- *
- * By having the boot loader boot up in the fastest L4 speed available likely
- * will result in something which you can switch between.
- */
-#define SDRC_RFR_CTRL_165MHz    (0x00044c00 | 1)
-#define SDRC_RFR_CTRL_133MHz    (0x0003de00 | 1)
-#define SDRC_RFR_CTRL_100MHz    (0x0002da01 | 1)
-#define SDRC_RFR_CTRL_110MHz    (0x0002da01 | 1) /* Need to calc */
-#define SDRC_RFR_CTRL_BYPASS    (0x00005000 | 1) /* Need to calc */
-
-
-/*
- * SMS register access
- */
-
-#define OMAP242X_SMS_REGADDR(reg)                                       \
-                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
-#define OMAP243X_SMS_REGADDR(reg)                                       \
-                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
-#define OMAP343X_SMS_REGADDR(reg)                                       \
-                (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
-
-/* SMS register offsets - read/write with sms_{read,write}_reg() */
-
-#define SMS_SYSCONFIG                   0x010
-#define SMS_ROT_CONTROL(context)        (0x180 + 0x10 * context)
-#define SMS_ROT_SIZE(context)           (0x184 + 0x10 * context)
-#define SMS_ROT_PHYSICAL_BA(context)    (0x188 + 0x10 * context)
-/* REVISIT: fill in other SMS registers here */
-
-
-#ifndef __ASSEMBLER__
-
-/**
- * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
- * @rate: SDRC clock rate (in Hz)
- * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
- * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
- * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
- * @mr: Value to program to SDRC_MR for this rate
- *
- * This structure holds a pre-computed set of register values for the
- * SDRC for a given SDRC clock rate and SDRAM chip.  These are
- * intended to be pre-computed and specified in an array in the board-*.c
- * files.  The structure is keyed off the 'rate' field.
- */
-struct omap_sdrc_params {
-        unsigned long rate;
-        u32 actim_ctrla;
-        u32 actim_ctrlb;
-        u32 rfr_ctrl;
-        u32 mr;
-};
-
-#ifdef CONFIG_SOC_HAS_OMAP2_SDRC
-void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
-                            struct omap_sdrc_params *sdrc_cs1);
-#else
-static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
-                                          struct omap_sdrc_params *sdrc_cs1) {};
-#endif
-
-int omap2_sdrc_get_params(unsigned long r,
-                          struct omap_sdrc_params **sdrc_cs0,
-                          struct omap_sdrc_params **sdrc_cs1);
-void omap2_sms_save_context(void);
-void omap2_sms_restore_context(void);
-
-void omap2_sms_write_rot_control(u32 val, unsigned ctx);
-void omap2_sms_write_rot_size(u32 val, unsigned ctx);
-void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx);
-
-#ifdef CONFIG_ARCH_OMAP2
-
-struct memory_timings {
-        u32 m_type;             /* ddr = 1, sdr = 0 */
-        u32 dll_mode;           /* use lock mode = 1, unlock mode = 0 */
-        u32 slow_dll_ctrl;      /* unlock mode, dll value for slow speed */
-        u32 fast_dll_ctrl;      /* unlock mode, dll value for fast speed */
-        u32 base_cs;            /* base chip select to use for calculations */
-};
-
-extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode);
-struct omap_sdrc_params *rx51_get_sdram_timings(void);
-
-u32 omap2xxx_sdrc_dll_is_unlocked(void);
-u32 omap2xxx_sdrc_reprogram(u32 level, u32 force);
-
-#endif  /* CONFIG_ARCH_OMAP2 */
-
-#endif  /* __ASSEMBLER__ */
-
-#endif
diff --git a/drivers/media/platform/omap/omap_vout.c b/drivers/media/platform/omap/omap_vout.c
index 1bd6a2ec95a3..4b1becc86e54 100644
--- a/drivers/media/platform/omap/omap_vout.c
+++ b/drivers/media/platform/omap/omap_vout.c
@@ -46,7 +46,7 @@
 
 #include <plat/cpu.h>
 #include <plat-omap/dma-omap.h>
-#include <plat/vrfb.h>
+#include <video/omapvrfb.h>
 #include <video/omapdss.h>
 
 #include "omap_voutlib.h"
diff --git a/drivers/media/platform/omap/omap_vout_vrfb.c b/drivers/media/platform/omap/omap_vout_vrfb.c
index bed4cbb18ef5..8340445a0ee5 100644
--- a/drivers/media/platform/omap/omap_vout_vrfb.c
+++ b/drivers/media/platform/omap/omap_vout_vrfb.c
@@ -17,7 +17,7 @@
 #include <media/v4l2-device.h>
 
 #include <plat-omap/dma-omap.h>
-#include <plat/vrfb.h>
+#include <video/omapvrfb.h>
 
 #include "omap_voutdef.h"
 #include "omap_voutlib.h"
diff --git a/drivers/media/platform/omap/omap_voutdef.h b/drivers/media/platform/omap/omap_voutdef.h
index 27a95d23b913..9ccfe1f475a4 100644
--- a/drivers/media/platform/omap/omap_voutdef.h
+++ b/drivers/media/platform/omap/omap_voutdef.h
@@ -12,7 +12,7 @@
 #define OMAP_VOUTDEF_H
 
 #include <video/omapdss.h>
-#include <plat/vrfb.h>
+#include <video/omapvrfb.h>
 
 #define YUYV_BPP        2
 #define RGB565_BPP      2
diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
index b2af72dc20bd..d94ef9e31a35 100644
--- a/drivers/video/omap2/dss/core.c
+++ b/drivers/video/omap2/dss/core.c
@@ -237,7 +237,7 @@ static int __init omap_dss_probe(struct platform_device *pdev)
 
         core.pdev = pdev;
 
-        dss_features_init();
+        dss_features_init(pdata->version);
 
         dss_apply_init();
 
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index b43477a5fae8..a5ab354f267a 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -37,8 +37,6 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 
-#include <plat/cpu.h>
-
 #include <video/omapdss.h>
 
 #include "dss.h"
@@ -4042,29 +4040,44 @@ static const struct dispc_features omap44xx_dispc_feats __initconst = {
         .gfx_fifo_workaround    =       true,
 };
 
-static int __init dispc_init_features(struct device *dev)
+static int __init dispc_init_features(struct platform_device *pdev)
 {
+        struct omap_dss_board_info *pdata = pdev->dev.platform_data;
         const struct dispc_features *src;
         struct dispc_features *dst;
 
-        dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL);
+        dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
         if (!dst) {
-                dev_err(dev, "Failed to allocate DISPC Features\n");
+                dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
                 return -ENOMEM;
         }
 
-        if (cpu_is_omap24xx()) {
+        switch (pdata->version) {
+        case OMAPDSS_VER_OMAP24xx:
                 src = &omap24xx_dispc_feats;
-        } else if (cpu_is_omap34xx()) {
-                if (omap_rev() < OMAP3430_REV_ES3_0)
-                        src = &omap34xx_rev1_0_dispc_feats;
-                else
-                        src = &omap34xx_rev3_0_dispc_feats;
-        } else if (cpu_is_omap44xx()) {
+                break;
+
+        case OMAPDSS_VER_OMAP34xx_ES1:
+                src = &omap34xx_rev1_0_dispc_feats;
+                break;
+
+        case OMAPDSS_VER_OMAP34xx_ES3:
+        case OMAPDSS_VER_OMAP3630:
+        case OMAPDSS_VER_AM35xx:
+                src = &omap34xx_rev3_0_dispc_feats;
+                break;
+
+        case OMAPDSS_VER_OMAP4430_ES1:
+        case OMAPDSS_VER_OMAP4430_ES2:
+        case OMAPDSS_VER_OMAP4:
                 src = &omap44xx_dispc_feats;
-        } else if (soc_is_omap54xx()) {
+                break;
+
+        case OMAPDSS_VER_OMAP5:
                 src = &omap44xx_dispc_feats;
-        } else {
+                break;
+
+        default:
                 return -ENODEV;
         }
 
@@ -4084,7 +4097,7 @@ static int __init omap_dispchw_probe(struct platform_device *pdev)
 
         dispc.pdev = pdev;
 
-        r = dispc_init_features(&dispc.pdev->dev);
+        r = dispc_init_features(dispc.pdev);
         if (r)
                 return r;
 
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 2ab1c3e96553..363852a0f764 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -35,8 +35,6 @@
 
 #include <video/omapdss.h>
 
-#include <plat/cpu.h>
-
 #include "dss.h"
 #include "dss_features.h"
 
@@ -792,29 +790,46 @@ static const struct dss_features omap54xx_dss_feats __initconst = {
         .dpi_select_source      =       &dss_dpi_select_source_omap5,
 };
 
-static int __init dss_init_features(struct device *dev)
+static int __init dss_init_features(struct platform_device *pdev)
 {
+        struct omap_dss_board_info *pdata = pdev->dev.platform_data;
         const struct dss_features *src;
         struct dss_features *dst;
 
-        dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL);
+        dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
         if (!dst) {
-                dev_err(dev, "Failed to allocate local DSS Features\n");
+                dev_err(&pdev->dev, "Failed to allocate local DSS Features\n");
                 return -ENOMEM;
         }
 
-        if (cpu_is_omap24xx())
+        switch (pdata->version) {
+        case OMAPDSS_VER_OMAP24xx:
                 src = &omap24xx_dss_feats;
-        else if (cpu_is_omap34xx())
+                break;
+
+        case OMAPDSS_VER_OMAP34xx_ES1:
+        case OMAPDSS_VER_OMAP34xx_ES3:
+        case OMAPDSS_VER_AM35xx:
                 src = &omap34xx_dss_feats;
-        else if (cpu_is_omap3630())
+                break;
+
+        case OMAPDSS_VER_OMAP3630:
                 src = &omap3630_dss_feats;
-        else if (cpu_is_omap44xx())
+                break;
+
+        case OMAPDSS_VER_OMAP4430_ES1:
+        case OMAPDSS_VER_OMAP4430_ES2:
+        case OMAPDSS_VER_OMAP4:
                 src = &omap44xx_dss_feats;
-        else if (soc_is_omap54xx())
+                break;
+
+        case OMAPDSS_VER_OMAP5:
                 src = &omap54xx_dss_feats;
-        else
+                break;
+
+        default:
                 return -ENODEV;
+        }
 
         memcpy(dst, src, sizeof(*dst));
         dss.feat = dst;
@@ -831,7 +846,7 @@ static int __init omap_dsshw_probe(struct platform_device *pdev)
 
         dss.pdev = pdev;
 
-        r = dss_init_features(&dss.pdev->dev);
+        r = dss_init_features(dss.pdev);
         if (r)
                 return r;
 
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index acbc1e1efba3..3e8287c8709d 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -23,7 +23,6 @@
 #include <linux/slab.h>
 
 #include <video/omapdss.h>
-#include <plat/cpu.h>
 
 #include "dss.h"
 #include "dss_features.h"
@@ -825,10 +824,20 @@ static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
 
 };
 
-void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data)
+void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data,
+                enum omapdss_version version)
 {
-        if (cpu_is_omap44xx())
+        switch (version) {
+        case OMAPDSS_VER_OMAP4430_ES1:
+        case OMAPDSS_VER_OMAP4430_ES2:
+        case OMAPDSS_VER_OMAP4:
                 ip_data->ops = &omap4_hdmi_functions;
+                break;
+        default:
+                ip_data->ops = NULL;
+        }
+
+        WARN_ON(ip_data->ops == NULL);
 }
 #endif
 
@@ -929,29 +938,44 @@ bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type)
         return omap_current_dss_features->supported_rotation_types & rot_type;
 }
 
-void dss_features_init(void)
+void dss_features_init(enum omapdss_version version)
 {
-        if (cpu_is_omap24xx())
+        switch (version) {
+        case OMAPDSS_VER_OMAP24xx:
                 omap_current_dss_features = &omap2_dss_features;
-        else if (cpu_is_omap3630())
+                break;
+
+        case OMAPDSS_VER_OMAP34xx_ES1:
+        case OMAPDSS_VER_OMAP34xx_ES3:
+                omap_current_dss_features = &omap3430_dss_features;
+                break;
+
+        case OMAPDSS_VER_OMAP3630:
                 omap_current_dss_features = &omap3630_dss_features;
-        else if (cpu_is_omap34xx()) {
-                if (soc_is_am35xx()) {
-                        omap_current_dss_features = &am35xx_dss_features;
-                } else {
-                        omap_current_dss_features = &omap3430_dss_features;
-                }
-        }
-        else if (omap_rev() == OMAP4430_REV_ES1_0)
+                break;
+
+        case OMAPDSS_VER_OMAP4430_ES1:
                 omap_current_dss_features = &omap4430_es1_0_dss_features;
-        else if (omap_rev() == OMAP4430_REV_ES2_0 ||
-                omap_rev() == OMAP4430_REV_ES2_1 ||
-                omap_rev() == OMAP4430_REV_ES2_2)
+                break;
+
+        case OMAPDSS_VER_OMAP4430_ES2:
                 omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
-        else if (cpu_is_omap44xx())
+                break;
+
+        case OMAPDSS_VER_OMAP4:
                 omap_current_dss_features = &omap4_dss_features;
-        else if (soc_is_omap54xx())
+                break;
+
+        case OMAPDSS_VER_OMAP5:
                 omap_current_dss_features = &omap5_dss_features;
-        else
+                break;
+
+        case OMAPDSS_VER_AM35xx:
+                omap_current_dss_features = &am35xx_dss_features;
+                break;
+
+        default:
                 DSSWARN("Unsupported OMAP version");
+                break;
+        }
 }
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index 9218113b5e88..fc492ef72a51 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -123,8 +123,9 @@ bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type);
 
 bool dss_has_feature(enum dss_feat_id id);
 void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end);
-void dss_features_init(void);
+void dss_features_init(enum omapdss_version version);
 #if defined(CONFIG_OMAP4_DSS_HDMI)
-void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data);
+void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data,
+                enum omapdss_version version);
 #endif
 #endif
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index a48a7dd75b33..adcc906d12f8 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -323,6 +323,7 @@ static void hdmi_runtime_put(void)
 
 static int __init hdmi_init_display(struct omap_dss_device *dssdev)
 {
+        struct omap_dss_board_info *pdata = hdmi.pdev->dev.platform_data;
         int r;
 
         struct gpio gpios[] = {
@@ -333,7 +334,7 @@ static int __init hdmi_init_display(struct omap_dss_device *dssdev)
 
         DSSDBG("init_display\n");
 
-        dss_init_hdmi_ip_ops(&hdmi.ip_data);
+        dss_init_hdmi_ip_ops(&hdmi.ip_data, pdata->version);
 
         if (hdmi.vdda_hdmi_dac_reg == NULL) {
                 struct regulator *reg;
diff --git a/drivers/video/omap2/omapfb/omapfb-ioctl.c b/drivers/video/omap2/omapfb/omapfb-ioctl.c
index 606b89f12351..55a39be694a5 100644
--- a/drivers/video/omap2/omapfb/omapfb-ioctl.c
+++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c
@@ -30,7 +30,7 @@
 #include <linux/export.h>
 
 #include <video/omapdss.h>
-#include <plat/vrfb.h>
+#include <video/omapvrfb.h>
 #include <plat/vram.h>
 
 #include "omapfb.h"
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
index 16db1589bd91..bc225e46fdd2 100644
--- a/drivers/video/omap2/omapfb/omapfb-main.c
+++ b/drivers/video/omap2/omapfb/omapfb-main.c
@@ -31,9 +31,8 @@
 #include <linux/omapfb.h>
 
 #include <video/omapdss.h>
-#include <plat/cpu.h>
 #include <plat/vram.h>
-#include <plat/vrfb.h>
+#include <video/omapvrfb.h>
 
 #include "omapfb.h"
 
@@ -2396,10 +2395,7 @@ static int __init omapfb_probe(struct platform_device *pdev)
                 goto err0;
         }
 
-        /* TODO : Replace cpu check with omap_has_vrfb once HAS_FEATURE
-        *        available for OMAP2 and OMAP3
-        */
-        if (def_vrfb && !cpu_is_omap24xx() && !cpu_is_omap34xx()) {
+        if (def_vrfb && !omap_vrfb_supported()) {
                 def_vrfb = 0;
                 dev_warn(&pdev->dev, "VRFB is not supported on this hardware, "
                                 "ignoring the module parameter vrfb=y\n");
diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
index e8d8cc76a435..17aa174e187c 100644
--- a/drivers/video/omap2/omapfb/omapfb-sysfs.c
+++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
@@ -30,7 +30,7 @@
 #include <linux/omapfb.h>
 
 #include <video/omapdss.h>
-#include <plat/vrfb.h>
+#include <video/omapvrfb.h>
 
 #include "omapfb.h"
 
diff --git a/drivers/video/omap2/vrfb.c b/drivers/video/omap2/vrfb.c
index 7e990220ad2a..5d8fdac3b800 100644
--- a/drivers/video/omap2/vrfb.c
+++ b/drivers/video/omap2/vrfb.c
@@ -26,9 +26,9 @@
 #include <linux/io.h>
 #include <linux/bitops.h>
 #include <linux/mutex.h>
+#include <linux/platform_device.h>
 
-#include <plat/vrfb.h>
-#include <plat/sdrc.h>
+#include <video/omapvrfb.h>
 
 #ifdef DEBUG
 #define DBG(format, ...) pr_debug("VRFB: " format, ## __VA_ARGS__)
@@ -36,10 +36,10 @@
 #define DBG(format, ...)
 #endif
 
-#define SMS_ROT_VIRT_BASE(context, rot) \
-        (((context >= 4) ? 0xD0000000 : 0x70000000) \
-         + (0x4000000 * (context)) \
-         + (0x1000000 * (rot)))
+#define SMS_ROT_CONTROL(context)        (0x0 + 0x10 * context)
+#define SMS_ROT_SIZE(context)           (0x4 + 0x10 * context)
+#define SMS_ROT_PHYSICAL_BA(context)    (0x8 + 0x10 * context)
+#define SMS_ROT_VIRT_BASE(rot)          (0x1000000 * (rot))
 
 #define OMAP_VRFB_SIZE                  (2048 * 2048 * 4)
 
@@ -53,10 +53,16 @@
 #define SMS_PW_OFFSET           4
 #define SMS_PS_OFFSET           0
 
-#define VRFB_NUM_CTXS 12
 /* bitmap of reserved contexts */
 static unsigned long ctx_map;
 
+struct vrfb_ctx {
+        u32 base;
+        u32 physical_ba;
+        u32 control;
+        u32 size;
+};
+
 static DEFINE_MUTEX(ctx_lock);
 
 /*
@@ -65,17 +71,34 @@ static DEFINE_MUTEX(ctx_lock);
  * we don't need locking, since no drivers will run until after the wake-up
  * has finished.
  */
-static struct {
-        u32 physical_ba;
-        u32 control;
-        u32 size;
-} vrfb_hw_context[VRFB_NUM_CTXS];
+
+static void __iomem *vrfb_base;
+
+static int num_ctxs;
+static struct vrfb_ctx *ctxs;
+
+static bool vrfb_loaded;
+
+static void omap2_sms_write_rot_control(u32 val, unsigned ctx)
+{
+        __raw_writel(val, vrfb_base + SMS_ROT_CONTROL(ctx));
+}
+
+static void omap2_sms_write_rot_size(u32 val, unsigned ctx)
+{
+        __raw_writel(val, vrfb_base + SMS_ROT_SIZE(ctx));
+}
+
+static void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx)
+{
+        __raw_writel(val, vrfb_base + SMS_ROT_PHYSICAL_BA(ctx));
+}
 
 static inline void restore_hw_context(int ctx)
 {
-        omap2_sms_write_rot_control(vrfb_hw_context[ctx].control, ctx);
-        omap2_sms_write_rot_size(vrfb_hw_context[ctx].size, ctx);
-        omap2_sms_write_rot_physical_ba(vrfb_hw_context[ctx].physical_ba, ctx);
+        omap2_sms_write_rot_control(ctxs[ctx].control, ctx);
+        omap2_sms_write_rot_size(ctxs[ctx].size, ctx);
+        omap2_sms_write_rot_physical_ba(ctxs[ctx].physical_ba, ctx);
 }
 
 static u32 get_image_width_roundup(u16 width, u8 bytespp)
@@ -196,9 +219,9 @@ void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
         control |= VRFB_PAGE_WIDTH_EXP  << SMS_PW_OFFSET;
         control |= VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET;
 
-        vrfb_hw_context[ctx].physical_ba = paddr;
-        vrfb_hw_context[ctx].size = size;
-        vrfb_hw_context[ctx].control = control;
+        ctxs[ctx].physical_ba = paddr;
+        ctxs[ctx].size = size;
+        ctxs[ctx].control = control;
 
         omap2_sms_write_rot_physical_ba(paddr, ctx);
         omap2_sms_write_rot_size(size, ctx);
@@ -274,11 +297,11 @@ int omap_vrfb_request_ctx(struct vrfb *vrfb)
 
         mutex_lock(&ctx_lock);
 
-        for (ctx = 0; ctx < VRFB_NUM_CTXS; ++ctx)
+        for (ctx = 0; ctx < num_ctxs; ++ctx)
                 if ((ctx_map & (1 << ctx)) == 0)
                         break;
 
-        if (ctx == VRFB_NUM_CTXS) {
+        if (ctx == num_ctxs) {
                 pr_err("vrfb: no free contexts\n");
                 r = -EBUSY;
                 goto out;
@@ -293,7 +316,7 @@ int omap_vrfb_request_ctx(struct vrfb *vrfb)
         vrfb->context = ctx;
 
         for (rot = 0; rot < 4; ++rot) {
-                paddr = SMS_ROT_VIRT_BASE(ctx, rot);
+                paddr = ctxs[ctx].base + SMS_ROT_VIRT_BASE(rot);
                 if (!request_mem_region(paddr, OMAP_VRFB_SIZE, "vrfb")) {
                         pr_err("vrfb: failed to reserve VRFB "
                                         "area for ctx %d, rotation %d\n",
@@ -314,3 +337,80 @@ out:
         return r;
 }
 EXPORT_SYMBOL(omap_vrfb_request_ctx);
+
+bool omap_vrfb_supported(void)
+{
+        return vrfb_loaded;
+}
+EXPORT_SYMBOL(omap_vrfb_supported);
+
+static int __init vrfb_probe(struct platform_device *pdev)
+{
+        struct resource *mem;
+        int i;
+
+        /* first resource is the register res, the rest are vrfb contexts */
+
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!mem) {
+                dev_err(&pdev->dev, "can't get vrfb base address\n");
+                return -EINVAL;
+        }
+
+        vrfb_base = devm_request_and_ioremap(&pdev->dev, mem);
+        if (!vrfb_base) {
+                dev_err(&pdev->dev, "can't ioremap vrfb memory\n");
+                return -ENOMEM;
+        }
+
+        num_ctxs = pdev->num_resources - 1;
+
+        ctxs = devm_kzalloc(&pdev->dev,
+                        sizeof(struct vrfb_ctx) * num_ctxs,
+                        GFP_KERNEL);
+
+        if (!ctxs)
+                return -ENOMEM;
+
+        for (i = 0; i < num_ctxs; ++i) {
+                mem = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i);
+                if (!mem) {
+                        dev_err(&pdev->dev, "can't get vrfb ctx %d address\n",
+                                        i);
+                        return -EINVAL;
+                }
+
+                ctxs[i].base = mem->start;
+        }
+
+        vrfb_loaded = true;
+
+        return 0;
+}
+
+static void __exit vrfb_remove(struct platform_device *pdev)
+{
+        vrfb_loaded = false;
+}
+
+static struct platform_driver vrfb_driver = {
+        .driver.name    = "omapvrfb",
+        .remove         = __exit_p(vrfb_remove),
+};
+
+static int __init vrfb_init(void)
+{
+        return platform_driver_probe(&vrfb_driver, &vrfb_probe);
+}
+
+static void __exit vrfb_exit(void)
+{
+        platform_driver_unregister(&vrfb_driver);
+}
+
+module_init(vrfb_init);
+module_exit(vrfb_exit);
+
+MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ti.com>");
+MODULE_DESCRIPTION("OMAP VRFB");
+MODULE_LICENSE("GPL v2");
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index 3729173b7fbc..88c829466fc1 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -314,6 +314,19 @@ int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
 
+enum omapdss_version {
+        OMAPDSS_VER_UNKNOWN = 0,
+        OMAPDSS_VER_OMAP24xx,
+        OMAPDSS_VER_OMAP34xx_ES1,       /* OMAP3430 ES1.0, 2.0 */
+        OMAPDSS_VER_OMAP34xx_ES3,       /* OMAP3430 ES3.0+ */
+        OMAPDSS_VER_OMAP3630,
+        OMAPDSS_VER_AM35xx,
+        OMAPDSS_VER_OMAP4430_ES1,       /* OMAP4430 ES1.0 */
+        OMAPDSS_VER_OMAP4430_ES2,       /* OMAP4430 ES2.0, 2.1, 2.2 */
+        OMAPDSS_VER_OMAP4,              /* All other OMAP4s */
+        OMAPDSS_VER_OMAP5,
+};
+
 /* Board specific data */
 struct omap_dss_board_info {
         int (*get_context_loss_count)(struct device *dev);
@@ -323,6 +336,7 @@ struct omap_dss_board_info {
         int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
         void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
         int (*set_min_bus_tput)(struct device *dev, unsigned long r);
+        enum omapdss_version version;
 };
 
 /* Init with the board info */
diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/include/video/omapvrfb.h
index 3792bdea2f6d..bb0bd89f8bc6 100644
--- a/arch/arm/plat-omap/include/plat/vrfb.h
+++ b/include/video/omapvrfb.h
@@ -36,6 +36,7 @@ struct vrfb {
 };
 
 #ifdef CONFIG_OMAP2_VRFB
+extern bool omap_vrfb_supported(void);
 extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
 extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
 extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
@@ -49,6 +50,7 @@ extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
 extern void omap_vrfb_restore_context(void);
 
 #else
+static inline bool omap_vrfb_supported(void) { return false; }
 static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; }
 static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {}
 static inline void omap_vrfb_adjust_size(u16 *width, u16 *height,