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-rw-r--r--drivers/net/bna/bfa_defs.h4
-rw-r--r--drivers/net/bna/bfa_defs_mfg_comm.h20
-rw-r--r--drivers/net/bna/bfa_defs_status.h134
-rw-r--r--drivers/net/bna/bfa_ioc.c2
-rw-r--r--drivers/net/bna/bfa_ioc.h16
-rw-r--r--drivers/net/bna/bfi.h14
-rw-r--r--drivers/net/bna/bna.h16
-rw-r--r--drivers/net/bna/bna_hw.h92
-rw-r--r--drivers/net/bna/bna_txrx.c4
-rw-r--r--drivers/net/bna/bna_types.h58
-rw-r--r--drivers/net/bna/bnad.c44
-rw-r--r--drivers/net/bna/bnad.h24
-rw-r--r--drivers/net/bna/bnad_ethtool.c2
13 files changed, 215 insertions, 215 deletions
diff --git a/drivers/net/bna/bfa_defs.h b/drivers/net/bna/bfa_defs.h
index 2ea0dfe1cedc..fa81f3c4b332 100644
--- a/drivers/net/bna/bfa_defs.h
+++ b/drivers/net/bna/bfa_defs.h
@@ -80,7 +80,7 @@ struct bfa_adapter_attr {
80 80
81enum { 81enum {
82 BFA_IOC_DRIVER_LEN = 16, 82 BFA_IOC_DRIVER_LEN = 16,
83 BFA_IOC_CHIP_REV_LEN = 8, 83 BFA_IOC_CHIP_REV_LEN = 8,
84}; 84};
85 85
86/** 86/**
@@ -174,7 +174,7 @@ enum bfa_ioc_type {
174 */ 174 */
175struct bfa_ioc_attr { 175struct bfa_ioc_attr {
176 enum bfa_ioc_type ioc_type; 176 enum bfa_ioc_type ioc_type;
177 enum bfa_ioc_state state; /*!< IOC state */ 177 enum bfa_ioc_state state; /*!< IOC state */
178 struct bfa_adapter_attr adapter_attr; /*!< HBA attributes */ 178 struct bfa_adapter_attr adapter_attr; /*!< HBA attributes */
179 struct bfa_ioc_driver_attr driver_attr; /*!< driver attr */ 179 struct bfa_ioc_driver_attr driver_attr; /*!< driver attr */
180 struct bfa_ioc_pci_attr pci_attr; 180 struct bfa_ioc_pci_attr pci_attr;
diff --git a/drivers/net/bna/bfa_defs_mfg_comm.h b/drivers/net/bna/bfa_defs_mfg_comm.h
index fdd677618361..885ef3afdd4e 100644
--- a/drivers/net/bna/bfa_defs_mfg_comm.h
+++ b/drivers/net/bna/bfa_defs_mfg_comm.h
@@ -192,14 +192,14 @@ do { \
192 * VPD vendor tag 192 * VPD vendor tag
193 */ 193 */
194enum { 194enum {
195 BFA_MFG_VPD_UNKNOWN = 0, /*!< vendor unknown */ 195 BFA_MFG_VPD_UNKNOWN = 0, /*!< vendor unknown */
196 BFA_MFG_VPD_IBM = 1, /*!< vendor IBM */ 196 BFA_MFG_VPD_IBM = 1, /*!< vendor IBM */
197 BFA_MFG_VPD_HP = 2, /*!< vendor HP */ 197 BFA_MFG_VPD_HP = 2, /*!< vendor HP */
198 BFA_MFG_VPD_DELL = 3, /*!< vendor DELL */ 198 BFA_MFG_VPD_DELL = 3, /*!< vendor DELL */
199 BFA_MFG_VPD_PCI_IBM = 0x08, /*!< PCI VPD IBM */ 199 BFA_MFG_VPD_PCI_IBM = 0x08, /*!< PCI VPD IBM */
200 BFA_MFG_VPD_PCI_HP = 0x10, /*!< PCI VPD HP */ 200 BFA_MFG_VPD_PCI_HP = 0x10, /*!< PCI VPD HP */
201 BFA_MFG_VPD_PCI_DELL = 0x20, /*!< PCI VPD DELL */ 201 BFA_MFG_VPD_PCI_DELL = 0x20, /*!< PCI VPD DELL */
202 BFA_MFG_VPD_PCI_BRCD = 0xf8, /*!< PCI VPD Brocade */ 202 BFA_MFG_VPD_PCI_BRCD = 0xf8, /*!< PCI VPD Brocade */
203}; 203};
204 204
205/** 205/**
@@ -212,8 +212,8 @@ struct bfa_mfg_vpd {
212 u8 vpd_sig[3]; /*!< characters 'V', 'P', 'D' */ 212 u8 vpd_sig[3]; /*!< characters 'V', 'P', 'D' */
213 u8 chksum; /*!< u8 checksum */ 213 u8 chksum; /*!< u8 checksum */
214 u8 vendor; /*!< vendor */ 214 u8 vendor; /*!< vendor */
215 u8 len; /*!< vpd data length excluding header */ 215 u8 len; /*!< vpd data length excluding header */
216 u8 rsv; 216 u8 rsv;
217 u8 data[BFA_MFG_VPD_LEN]; /*!< vpd data */ 217 u8 data[BFA_MFG_VPD_LEN]; /*!< vpd data */
218}; 218};
219 219
diff --git a/drivers/net/bna/bfa_defs_status.h b/drivers/net/bna/bfa_defs_status.h
index af951126375c..7c5fe6c2e80e 100644
--- a/drivers/net/bna/bfa_defs_status.h
+++ b/drivers/net/bna/bfa_defs_status.h
@@ -25,95 +25,95 @@
25 * comments are supported 25 * comments are supported
26 */ 26 */
27enum bfa_status { 27enum bfa_status {
28 BFA_STATUS_OK = 0, 28 BFA_STATUS_OK = 0,
29 BFA_STATUS_FAILED = 1, 29 BFA_STATUS_FAILED = 1,
30 BFA_STATUS_EINVAL = 2, 30 BFA_STATUS_EINVAL = 2,
31 BFA_STATUS_ENOMEM = 3, 31 BFA_STATUS_ENOMEM = 3,
32 BFA_STATUS_ENOSYS = 4, 32 BFA_STATUS_ENOSYS = 4,
33 BFA_STATUS_ETIMER = 5, 33 BFA_STATUS_ETIMER = 5,
34 BFA_STATUS_EPROTOCOL = 6, 34 BFA_STATUS_EPROTOCOL = 6,
35 BFA_STATUS_ENOFCPORTS = 7, 35 BFA_STATUS_ENOFCPORTS = 7,
36 BFA_STATUS_NOFLASH = 8, 36 BFA_STATUS_NOFLASH = 8,
37 BFA_STATUS_BADFLASH = 9, 37 BFA_STATUS_BADFLASH = 9,
38 BFA_STATUS_SFP_UNSUPP = 10, 38 BFA_STATUS_SFP_UNSUPP = 10,
39 BFA_STATUS_UNKNOWN_VFID = 11, 39 BFA_STATUS_UNKNOWN_VFID = 11,
40 BFA_STATUS_DATACORRUPTED = 12, 40 BFA_STATUS_DATACORRUPTED = 12,
41 BFA_STATUS_DEVBUSY = 13, 41 BFA_STATUS_DEVBUSY = 13,
42 BFA_STATUS_ABORTED = 14, 42 BFA_STATUS_ABORTED = 14,
43 BFA_STATUS_NODEV = 15, 43 BFA_STATUS_NODEV = 15,
44 BFA_STATUS_HDMA_FAILED = 16, 44 BFA_STATUS_HDMA_FAILED = 16,
45 BFA_STATUS_FLASH_BAD_LEN = 17, 45 BFA_STATUS_FLASH_BAD_LEN = 17,
46 BFA_STATUS_UNKNOWN_LWWN = 18, 46 BFA_STATUS_UNKNOWN_LWWN = 18,
47 BFA_STATUS_UNKNOWN_RWWN = 19, 47 BFA_STATUS_UNKNOWN_RWWN = 19,
48 BFA_STATUS_FCPT_LS_RJT = 20, 48 BFA_STATUS_FCPT_LS_RJT = 20,
49 BFA_STATUS_VPORT_EXISTS = 21, 49 BFA_STATUS_VPORT_EXISTS = 21,
50 BFA_STATUS_VPORT_MAX = 22, 50 BFA_STATUS_VPORT_MAX = 22,
51 BFA_STATUS_UNSUPP_SPEED = 23, 51 BFA_STATUS_UNSUPP_SPEED = 23,
52 BFA_STATUS_INVLD_DFSZ = 24, 52 BFA_STATUS_INVLD_DFSZ = 24,
53 BFA_STATUS_CNFG_FAILED = 25, 53 BFA_STATUS_CNFG_FAILED = 25,
54 BFA_STATUS_CMD_NOTSUPP = 26, 54 BFA_STATUS_CMD_NOTSUPP = 26,
55 BFA_STATUS_NO_ADAPTER = 27, 55 BFA_STATUS_NO_ADAPTER = 27,
56 BFA_STATUS_LINKDOWN = 28, 56 BFA_STATUS_LINKDOWN = 28,
57 BFA_STATUS_FABRIC_RJT = 29, 57 BFA_STATUS_FABRIC_RJT = 29,
58 BFA_STATUS_UNKNOWN_VWWN = 30, 58 BFA_STATUS_UNKNOWN_VWWN = 30,
59 BFA_STATUS_NSLOGIN_FAILED = 31, 59 BFA_STATUS_NSLOGIN_FAILED = 31,
60 BFA_STATUS_NO_RPORTS = 32, 60 BFA_STATUS_NO_RPORTS = 32,
61 BFA_STATUS_NSQUERY_FAILED = 33, 61 BFA_STATUS_NSQUERY_FAILED = 33,
62 BFA_STATUS_PORT_OFFLINE = 34, 62 BFA_STATUS_PORT_OFFLINE = 34,
63 BFA_STATUS_RPORT_OFFLINE = 35, 63 BFA_STATUS_RPORT_OFFLINE = 35,
64 BFA_STATUS_TGTOPEN_FAILED = 36, 64 BFA_STATUS_TGTOPEN_FAILED = 36,
65 BFA_STATUS_BAD_LUNS = 37, 65 BFA_STATUS_BAD_LUNS = 37,
66 BFA_STATUS_IO_FAILURE = 38, 66 BFA_STATUS_IO_FAILURE = 38,
67 BFA_STATUS_NO_FABRIC = 39, 67 BFA_STATUS_NO_FABRIC = 39,
68 BFA_STATUS_EBADF = 40, 68 BFA_STATUS_EBADF = 40,
69 BFA_STATUS_EINTR = 41, 69 BFA_STATUS_EINTR = 41,
70 BFA_STATUS_EIO = 42, 70 BFA_STATUS_EIO = 42,
71 BFA_STATUS_ENOTTY = 43, 71 BFA_STATUS_ENOTTY = 43,
72 BFA_STATUS_ENXIO = 44, 72 BFA_STATUS_ENXIO = 44,
73 BFA_STATUS_EFOPEN = 45, 73 BFA_STATUS_EFOPEN = 45,
74 BFA_STATUS_VPORT_WWN_BP = 46, 74 BFA_STATUS_VPORT_WWN_BP = 46,
75 BFA_STATUS_PORT_NOT_DISABLED = 47, 75 BFA_STATUS_PORT_NOT_DISABLED = 47,
76 BFA_STATUS_BADFRMHDR = 48, 76 BFA_STATUS_BADFRMHDR = 48,
77 BFA_STATUS_BADFRMSZ = 49, 77 BFA_STATUS_BADFRMSZ = 49,
78 BFA_STATUS_MISSINGFRM = 50, 78 BFA_STATUS_MISSINGFRM = 50,
79 BFA_STATUS_LINKTIMEOUT = 51, 79 BFA_STATUS_LINKTIMEOUT = 51,
80 BFA_STATUS_NO_FCPIM_NEXUS = 52, 80 BFA_STATUS_NO_FCPIM_NEXUS = 52,
81 BFA_STATUS_CHECKSUM_FAIL = 53, 81 BFA_STATUS_CHECKSUM_FAIL = 53,
82 BFA_STATUS_GZME_FAILED = 54, 82 BFA_STATUS_GZME_FAILED = 54,
83 BFA_STATUS_SCSISTART_REQD = 55, 83 BFA_STATUS_SCSISTART_REQD = 55,
84 BFA_STATUS_IOC_FAILURE = 56, 84 BFA_STATUS_IOC_FAILURE = 56,
85 BFA_STATUS_INVALID_WWN = 57, 85 BFA_STATUS_INVALID_WWN = 57,
86 BFA_STATUS_MISMATCH = 58, 86 BFA_STATUS_MISMATCH = 58,
87 BFA_STATUS_IOC_ENABLED = 59, 87 BFA_STATUS_IOC_ENABLED = 59,
88 BFA_STATUS_ADAPTER_ENABLED = 60, 88 BFA_STATUS_ADAPTER_ENABLED = 60,
89 BFA_STATUS_IOC_NON_OP = 61, 89 BFA_STATUS_IOC_NON_OP = 61,
90 BFA_STATUS_ADDR_MAP_FAILURE = 62, 90 BFA_STATUS_ADDR_MAP_FAILURE = 62,
91 BFA_STATUS_SAME_NAME = 63, 91 BFA_STATUS_SAME_NAME = 63,
92 BFA_STATUS_PENDING = 64, 92 BFA_STATUS_PENDING = 64,
93 BFA_STATUS_8G_SPD = 65, 93 BFA_STATUS_8G_SPD = 65,
94 BFA_STATUS_4G_SPD = 66, 94 BFA_STATUS_4G_SPD = 66,
95 BFA_STATUS_AD_IS_ENABLE = 67, 95 BFA_STATUS_AD_IS_ENABLE = 67,
96 BFA_STATUS_EINVAL_TOV = 68, 96 BFA_STATUS_EINVAL_TOV = 68,
97 BFA_STATUS_EINVAL_QDEPTH = 69, 97 BFA_STATUS_EINVAL_QDEPTH = 69,
98 BFA_STATUS_VERSION_FAIL = 70, 98 BFA_STATUS_VERSION_FAIL = 70,
99 BFA_STATUS_DIAG_BUSY = 71, 99 BFA_STATUS_DIAG_BUSY = 71,
100 BFA_STATUS_BEACON_ON = 72, 100 BFA_STATUS_BEACON_ON = 72,
101 BFA_STATUS_BEACON_OFF = 73, 101 BFA_STATUS_BEACON_OFF = 73,
102 BFA_STATUS_LBEACON_ON = 74, 102 BFA_STATUS_LBEACON_ON = 74,
103 BFA_STATUS_LBEACON_OFF = 75, 103 BFA_STATUS_LBEACON_OFF = 75,
104 BFA_STATUS_PORT_NOT_INITED = 76, 104 BFA_STATUS_PORT_NOT_INITED = 76,
105 BFA_STATUS_RPSC_ENABLED = 77, 105 BFA_STATUS_RPSC_ENABLED = 77,
106 BFA_STATUS_ENOFSAVE = 78, 106 BFA_STATUS_ENOFSAVE = 78,
107 BFA_STATUS_BAD_FILE = 79, 107 BFA_STATUS_BAD_FILE = 79,
108 BFA_STATUS_RLIM_EN = 80, 108 BFA_STATUS_RLIM_EN = 80,
109 BFA_STATUS_RLIM_DIS = 81, 109 BFA_STATUS_RLIM_DIS = 81,
110 BFA_STATUS_IOC_DISABLED = 82, 110 BFA_STATUS_IOC_DISABLED = 82,
111 BFA_STATUS_ADAPTER_DISABLED = 83, 111 BFA_STATUS_ADAPTER_DISABLED = 83,
112 BFA_STATUS_BIOS_DISABLED = 84, 112 BFA_STATUS_BIOS_DISABLED = 84,
113 BFA_STATUS_AUTH_ENABLED = 85, 113 BFA_STATUS_AUTH_ENABLED = 85,
114 BFA_STATUS_AUTH_DISABLED = 86, 114 BFA_STATUS_AUTH_DISABLED = 86,
115 BFA_STATUS_ERROR_TRL_ENABLED = 87, 115 BFA_STATUS_ERROR_TRL_ENABLED = 87,
116 BFA_STATUS_ERROR_QOS_ENABLED = 88, 116 BFA_STATUS_ERROR_QOS_ENABLED = 88,
117 BFA_STATUS_NO_SFP_DEV = 89, 117 BFA_STATUS_NO_SFP_DEV = 89,
118 BFA_STATUS_MEMTEST_FAILED = 90, 118 BFA_STATUS_MEMTEST_FAILED = 90,
119 BFA_STATUS_INVALID_DEVID = 91, 119 BFA_STATUS_INVALID_DEVID = 91,
@@ -190,7 +190,7 @@ enum bfa_status {
190 BFA_STATUS_FLASH_CKFAIL = 162, 190 BFA_STATUS_FLASH_CKFAIL = 162,
191 BFA_STATUS_TRUNK_UNSUPP = 163, 191 BFA_STATUS_TRUNK_UNSUPP = 163,
192 BFA_STATUS_TRUNK_ENABLED = 164, 192 BFA_STATUS_TRUNK_ENABLED = 164,
193 BFA_STATUS_TRUNK_DISABLED = 165, 193 BFA_STATUS_TRUNK_DISABLED = 165,
194 BFA_STATUS_TRUNK_ERROR_TRL_ENABLED = 166, 194 BFA_STATUS_TRUNK_ERROR_TRL_ENABLED = 166,
195 BFA_STATUS_BOOT_CODE_UPDATED = 167, 195 BFA_STATUS_BOOT_CODE_UPDATED = 167,
196 BFA_STATUS_BOOT_VERSION = 168, 196 BFA_STATUS_BOOT_VERSION = 168,
@@ -198,8 +198,8 @@ enum bfa_status {
198 BFA_STATUS_INVALID_CARDTYPE = 170, 198 BFA_STATUS_INVALID_CARDTYPE = 170,
199 BFA_STATUS_NO_TOPOLOGY_FOR_CNA = 171, 199 BFA_STATUS_NO_TOPOLOGY_FOR_CNA = 171,
200 BFA_STATUS_IM_VLAN_OVER_TEAM_DELETE_FAILED = 172, 200 BFA_STATUS_IM_VLAN_OVER_TEAM_DELETE_FAILED = 172,
201 BFA_STATUS_ETHBOOT_ENABLED = 173, 201 BFA_STATUS_ETHBOOT_ENABLED = 173,
202 BFA_STATUS_ETHBOOT_DISABLED = 174, 202 BFA_STATUS_ETHBOOT_DISABLED = 174,
203 BFA_STATUS_IOPROFILE_OFF = 175, 203 BFA_STATUS_IOPROFILE_OFF = 175,
204 BFA_STATUS_NO_PORT_INSTANCE = 176, 204 BFA_STATUS_NO_PORT_INSTANCE = 176,
205 BFA_STATUS_BOOT_CODE_TIMEDOUT = 177, 205 BFA_STATUS_BOOT_CODE_TIMEDOUT = 177,
diff --git a/drivers/net/bna/bfa_ioc.c b/drivers/net/bna/bfa_ioc.c
index fcb9bb3169e0..04bfb29bdc93 100644
--- a/drivers/net/bna/bfa_ioc.c
+++ b/drivers/net/bna/bfa_ioc.c
@@ -156,7 +156,7 @@ enum iocpf_event {
156 IOCPF_E_ENABLE = 1, /*!< IOCPF enable request */ 156 IOCPF_E_ENABLE = 1, /*!< IOCPF enable request */
157 IOCPF_E_DISABLE = 2, /*!< IOCPF disable request */ 157 IOCPF_E_DISABLE = 2, /*!< IOCPF disable request */
158 IOCPF_E_STOP = 3, /*!< stop on driver detach */ 158 IOCPF_E_STOP = 3, /*!< stop on driver detach */
159 IOCPF_E_FWREADY = 4, /*!< f/w initialization done */ 159 IOCPF_E_FWREADY = 4, /*!< f/w initialization done */
160 IOCPF_E_FWRSP_ENABLE = 5, /*!< enable f/w response */ 160 IOCPF_E_FWRSP_ENABLE = 5, /*!< enable f/w response */
161 IOCPF_E_FWRSP_DISABLE = 6, /*!< disable f/w response */ 161 IOCPF_E_FWRSP_DISABLE = 6, /*!< disable f/w response */
162 IOCPF_E_FAIL = 7, /*!< failure notice by ioc sm */ 162 IOCPF_E_FAIL = 7, /*!< failure notice by ioc sm */
diff --git a/drivers/net/bna/bfa_ioc.h b/drivers/net/bna/bfa_ioc.h
index bd48abee781f..8473c00b9427 100644
--- a/drivers/net/bna/bfa_ioc.h
+++ b/drivers/net/bna/bfa_ioc.h
@@ -155,11 +155,11 @@ struct bfa_iocpf {
155 155
156struct bfa_ioc { 156struct bfa_ioc {
157 bfa_fsm_t fsm; 157 bfa_fsm_t fsm;
158 struct bfa *bfa; 158 struct bfa *bfa;
159 struct bfa_pcidev pcidev; 159 struct bfa_pcidev pcidev;
160 struct timer_list ioc_timer; 160 struct timer_list ioc_timer;
161 struct timer_list iocpf_timer; 161 struct timer_list iocpf_timer;
162 struct timer_list sem_timer; 162 struct timer_list sem_timer;
163 struct timer_list hb_timer; 163 struct timer_list hb_timer;
164 u32 hb_count; 164 u32 hb_count;
165 struct list_head hb_notify_q; 165 struct list_head hb_notify_q;
@@ -167,13 +167,13 @@ struct bfa_ioc {
167 int dbg_fwsave_len; 167 int dbg_fwsave_len;
168 bool dbg_fwsave_once; 168 bool dbg_fwsave_once;
169 enum bfi_mclass ioc_mc; 169 enum bfi_mclass ioc_mc;
170 struct bfa_ioc_regs ioc_regs; 170 struct bfa_ioc_regs ioc_regs;
171 struct bfa_ioc_drv_stats stats; 171 struct bfa_ioc_drv_stats stats;
172 bool fcmode; 172 bool fcmode;
173 bool ctdev; 173 bool ctdev;
174 bool cna; 174 bool cna;
175 bool pllinit; 175 bool pllinit;
176 bool stats_busy; /*!< outstanding stats */ 176 bool stats_busy; /*!< outstanding stats */
177 u8 port_id; 177 u8 port_id;
178 178
179 struct bfa_dma attr_dma; 179 struct bfa_dma attr_dma;
@@ -219,7 +219,7 @@ struct bfa_ioc_hwif {
219#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++) 219#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++)
220#define BFA_IOC_FWIMG_MINSZ (16 * 1024) 220#define BFA_IOC_FWIMG_MINSZ (16 * 1024)
221#define BFA_IOC_FWIMG_TYPE(__ioc) \ 221#define BFA_IOC_FWIMG_TYPE(__ioc) \
222 (((__ioc)->ctdev) ? \ 222 (((__ioc)->ctdev) ? \
223 (((__ioc)->fcmode) ? BFI_IMAGE_CT_FC : BFI_IMAGE_CT_CNA) : \ 223 (((__ioc)->fcmode) ? BFI_IMAGE_CT_FC : BFI_IMAGE_CT_CNA) : \
224 BFI_IMAGE_CB_FC) 224 BFI_IMAGE_CB_FC)
225#define BFA_IOC_FW_SMEM_SIZE(__ioc) \ 225#define BFA_IOC_FW_SMEM_SIZE(__ioc) \
diff --git a/drivers/net/bna/bfi.h b/drivers/net/bna/bfi.h
index 6050379526f7..683a7d7acc38 100644
--- a/drivers/net/bna/bfi.h
+++ b/drivers/net/bna/bfi.h
@@ -51,13 +51,13 @@ struct bfi_mhdr {
51}; 51};
52 52
53#define bfi_h2i_set(_mh, _mc, _op, _lpuid) do { \ 53#define bfi_h2i_set(_mh, _mc, _op, _lpuid) do { \
54 (_mh).msg_class = (_mc); \ 54 (_mh).msg_class = (_mc); \
55 (_mh).msg_id = (_op); \ 55 (_mh).msg_id = (_op); \
56 (_mh).mtag.h2i.lpu_id = (_lpuid); \ 56 (_mh).mtag.h2i.lpu_id = (_lpuid); \
57} while (0) 57} while (0)
58 58
59#define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \ 59#define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \
60 (_mh).msg_class = (_mc); \ 60 (_mh).msg_class = (_mc); \
61 (_mh).msg_id = (_op); \ 61 (_mh).msg_id = (_op); \
62 (_mh).mtag.i2htok = (_i2htok); \ 62 (_mh).mtag.i2htok = (_i2htok); \
63} while (0) 63} while (0)
@@ -66,7 +66,7 @@ struct bfi_mhdr {
66 * Message opcodes: 0-127 to firmware, 128-255 to host 66 * Message opcodes: 0-127 to firmware, 128-255 to host
67 */ 67 */
68#define BFI_I2H_OPCODE_BASE 128 68#define BFI_I2H_OPCODE_BASE 128
69#define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE) 69#define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE)
70 70
71/** 71/**
72 **************************************************************************** 72 ****************************************************************************
@@ -186,7 +186,7 @@ enum bfi_mclass {
186#define BFI_BOOT_TYPE_OFF 8 186#define BFI_BOOT_TYPE_OFF 8
187#define BFI_BOOT_LOADER_OFF 12 187#define BFI_BOOT_LOADER_OFF 12
188 188
189#define BFI_BOOT_TYPE_NORMAL 0 189#define BFI_BOOT_TYPE_NORMAL 0
190#define BFI_BOOT_TYPE_FLASH 1 190#define BFI_BOOT_TYPE_FLASH 1
191#define BFI_BOOT_TYPE_MEMTEST 2 191#define BFI_BOOT_TYPE_MEMTEST 2
192 192
@@ -211,9 +211,9 @@ enum bfi_ioc_h2i_msgs {
211 211
212enum bfi_ioc_i2h_msgs { 212enum bfi_ioc_i2h_msgs {
213 BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1), 213 BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1),
214 BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2), 214 BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
215 BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3), 215 BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
216 BFI_IOC_I2H_READY_EVENT = BFA_I2HM(4), 216 BFI_IOC_I2H_READY_EVENT = BFA_I2HM(4),
217 BFI_IOC_I2H_HBEAT = BFA_I2HM(5), 217 BFI_IOC_I2H_HBEAT = BFA_I2HM(5),
218}; 218};
219 219
diff --git a/drivers/net/bna/bna.h b/drivers/net/bna/bna.h
index a287f89b0289..6b14c1d92871 100644
--- a/drivers/net/bna/bna.h
+++ b/drivers/net/bna/bna.h
@@ -88,7 +88,7 @@ do { \
88} while (0) 88} while (0)
89 89
90#define containing_rec(addr, type, field) \ 90#define containing_rec(addr, type, field) \
91 ((type *)((unsigned char *)(addr) - \ 91 ((type *)((unsigned char *)(addr) - \
92 (unsigned char *)(&((type *)0)->field))) 92 (unsigned char *)(&((type *)0)->field)))
93 93
94#define BNA_TXQ_WI_NEEDED(_vectors) (((_vectors) + 3) >> 2) 94#define BNA_TXQ_WI_NEEDED(_vectors) (((_vectors) + 3) >> 2)
@@ -101,8 +101,8 @@ do { \
101{ \ 101{ \
102 unsigned int page_index; /* index within a page */ \ 102 unsigned int page_index; /* index within a page */ \
103 void *page_addr; \ 103 void *page_addr; \
104 page_index = (_qe_idx) & (BNA_TXQ_PAGE_INDEX_MAX - 1); \ 104 page_index = (_qe_idx) & (BNA_TXQ_PAGE_INDEX_MAX - 1); \
105 (_qe_ptr_range) = (BNA_TXQ_PAGE_INDEX_MAX - page_index); \ 105 (_qe_ptr_range) = (BNA_TXQ_PAGE_INDEX_MAX - page_index); \
106 page_addr = (_qpt_ptr)[((_qe_idx) >> BNA_TXQ_PAGE_INDEX_MAX_SHIFT)];\ 106 page_addr = (_qpt_ptr)[((_qe_idx) >> BNA_TXQ_PAGE_INDEX_MAX_SHIFT)];\
107 (_qe_ptr) = &((struct bna_txq_entry *)(page_addr))[page_index]; \ 107 (_qe_ptr) = &((struct bna_txq_entry *)(page_addr))[page_index]; \
108} 108}
@@ -166,25 +166,25 @@ do { \
166 (((_q_ptr)->q.producer_index + (_num)) & \ 166 (((_q_ptr)->q.producer_index + (_num)) & \
167 ((_q_ptr)->q.q_depth - 1)) 167 ((_q_ptr)->q.q_depth - 1))
168 168
169#define BNA_Q_CI_ADD(_q_ptr, _num) \ 169#define BNA_Q_CI_ADD(_q_ptr, _num) \
170 (_q_ptr)->q.consumer_index = \ 170 (_q_ptr)->q.consumer_index = \
171 (((_q_ptr)->q.consumer_index + (_num)) \ 171 (((_q_ptr)->q.consumer_index + (_num)) \
172 & ((_q_ptr)->q.q_depth - 1)) 172 & ((_q_ptr)->q.q_depth - 1))
173 173
174#define BNA_Q_FREE_COUNT(_q_ptr) \ 174#define BNA_Q_FREE_COUNT(_q_ptr) \
175 (BNA_QE_FREE_CNT(&((_q_ptr)->q), (_q_ptr)->q.q_depth)) 175 (BNA_QE_FREE_CNT(&((_q_ptr)->q), (_q_ptr)->q.q_depth))
176 176
177#define BNA_Q_IN_USE_COUNT(_q_ptr) \ 177#define BNA_Q_IN_USE_COUNT(_q_ptr) \
178 (BNA_QE_IN_USE_CNT(&(_q_ptr)->q, (_q_ptr)->q.q_depth)) 178 (BNA_QE_IN_USE_CNT(&(_q_ptr)->q, (_q_ptr)->q.q_depth))
179 179
180/* These macros build the data portion of the TxQ/RxQ doorbell */ 180/* These macros build the data portion of the TxQ/RxQ doorbell */
181#define BNA_DOORBELL_Q_PRD_IDX(_pi) (0x80000000 | (_pi)) 181#define BNA_DOORBELL_Q_PRD_IDX(_pi) (0x80000000 | (_pi))
182#define BNA_DOORBELL_Q_STOP (0x40000000) 182#define BNA_DOORBELL_Q_STOP (0x40000000)
183 183
184/* These macros build the data portion of the IB doorbell */ 184/* These macros build the data portion of the IB doorbell */
185#define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) \ 185#define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) \
186 (0x80000000 | ((_timeout) << 16) | (_events)) 186 (0x80000000 | ((_timeout) << 16) | (_events))
187#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000) 187#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000)
188 188
189/* Set the coalescing timer for the given ib */ 189/* Set the coalescing timer for the given ib */
190#define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer) \ 190#define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer) \
diff --git a/drivers/net/bna/bna_hw.h b/drivers/net/bna/bna_hw.h
index 6cb89692f5c1..cad233da843a 100644
--- a/drivers/net/bna/bna_hw.h
+++ b/drivers/net/bna/bna_hw.h
@@ -67,7 +67,7 @@ static struct bna_ibidx_pool name[BFI_IBIDX_TOTAL_POOLS] = \
67 67
68/** 68/**
69 * There are 2 free RIT segment pools: 69 * There are 2 free RIT segment pools:
70 * Pool1: 192 segments of 1 RIT entry each 70 * Pool1: 192 segments of 1 RIT entry each
71 * Pool2: 1 segment of 64 RIT entry 71 * Pool2: 1 segment of 64 RIT entry
72 */ 72 */
73#define BFI_RIT_SEG_POOL1_SIZE 192 73#define BFI_RIT_SEG_POOL1_SIZE 192
@@ -357,14 +357,14 @@ static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \
357 * To clear set the value to 0. 357 * To clear set the value to 0.
358 * Range : 0x20 to 0x5c 358 * Range : 0x20 to 0x5c
359 */ 359 */
360#define PSS_SEM_LOCK_REG(_num) \ 360#define PSS_SEM_LOCK_REG(_num) \
361 (PSS_BLK_REG_ADDR + 0x020 + ((_num) << 2)) 361 (PSS_BLK_REG_ADDR + 0x020 + ((_num) << 2))
362 362
363/** 363/**
364 * PSS Semaphore Status Registers, 364 * PSS Semaphore Status Registers,
365 * corresponding to the lock registers above 365 * corresponding to the lock registers above
366 */ 366 */
367#define PSS_SEM_STATUS_REG(_num) \ 367#define PSS_SEM_STATUS_REG(_num) \
368 (PSS_BLK_REG_ADDR + 0x060 + ((_num) << 2)) 368 (PSS_BLK_REG_ADDR + 0x060 + ((_num) << 2))
369 369
370/** 370/**
@@ -1044,7 +1044,7 @@ static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \
1044 __LPU12HOST_MBOX1_STATUS_BITS)) 1044 __LPU12HOST_MBOX1_STATUS_BITS))
1045 1045
1046#define BNA_IS_MBOX_INTR(_intr_status) \ 1046#define BNA_IS_MBOX_INTR(_intr_status) \
1047 ((_intr_status) & \ 1047 ((_intr_status) & \
1048 (__LPU02HOST_MBOX0_STATUS_BITS | \ 1048 (__LPU02HOST_MBOX0_STATUS_BITS | \
1049 __LPU02HOST_MBOX1_STATUS_BITS | \ 1049 __LPU02HOST_MBOX1_STATUS_BITS | \
1050 __LPU12HOST_MBOX0_STATUS_BITS | \ 1050 __LPU12HOST_MBOX0_STATUS_BITS | \
@@ -1070,11 +1070,11 @@ static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \
1070 __HALT_MASK_BITS) 1070 __HALT_MASK_BITS)
1071 1071
1072#define BNA_IS_ERR_INTR(_intr_status) \ 1072#define BNA_IS_ERR_INTR(_intr_status) \
1073 ((_intr_status) & \ 1073 ((_intr_status) & \
1074 (__EMC_ERROR_STATUS_BITS | \ 1074 (__EMC_ERROR_STATUS_BITS | \
1075 __LPU0_ERROR_STATUS_BITS | \ 1075 __LPU0_ERROR_STATUS_BITS | \
1076 __LPU1_ERROR_STATUS_BITS | \ 1076 __LPU1_ERROR_STATUS_BITS | \
1077 __PSS_ERROR_STATUS_BITS | \ 1077 __PSS_ERROR_STATUS_BITS | \
1078 __HALT_STATUS_BITS)) 1078 __HALT_STATUS_BITS))
1079 1079
1080#define BNA_IS_MBOX_ERR_INTR(_intr_status) \ 1080#define BNA_IS_MBOX_ERR_INTR(_intr_status) \
@@ -1087,9 +1087,9 @@ static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \
1087#define BNA_INTR_STATUS_MBOX_CLR(_intr_status) \ 1087#define BNA_INTR_STATUS_MBOX_CLR(_intr_status) \
1088do { \ 1088do { \
1089 (_intr_status) &= ~(__LPU02HOST_MBOX0_STATUS_BITS | \ 1089 (_intr_status) &= ~(__LPU02HOST_MBOX0_STATUS_BITS | \
1090 __LPU02HOST_MBOX1_STATUS_BITS | \ 1090 __LPU02HOST_MBOX1_STATUS_BITS | \
1091 __LPU12HOST_MBOX0_STATUS_BITS | \ 1091 __LPU12HOST_MBOX0_STATUS_BITS | \
1092 __LPU12HOST_MBOX1_STATUS_BITS); \ 1092 __LPU12HOST_MBOX1_STATUS_BITS); \
1093} while (0) 1093} while (0)
1094 1094
1095#define BNA_INTR_STATUS_ERR_CLR(_intr_status) \ 1095#define BNA_INTR_STATUS_ERR_CLR(_intr_status) \
@@ -1107,7 +1107,7 @@ do { \
1107 writel(0xffffffff, (_bna)->regs.fn_int_mask);\ 1107 writel(0xffffffff, (_bna)->regs.fn_int_mask);\
1108} 1108}
1109 1109
1110#define bna_intx_enable(bna, new_mask) \ 1110#define bna_intx_enable(bna, new_mask) \
1111 writel((new_mask), (bna)->regs.fn_int_mask) 1111 writel((new_mask), (bna)->regs.fn_int_mask)
1112 1112
1113#define bna_mbox_intr_disable(bna) \ 1113#define bna_mbox_intr_disable(bna) \
@@ -1179,18 +1179,18 @@ do {\
1179#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000) 1179#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000)
1180 1180
1181/* TxQ Entry Opcodes */ 1181/* TxQ Entry Opcodes */
1182#define BNA_TXQ_WI_SEND (0x402) /* Single Frame Transmission */ 1182#define BNA_TXQ_WI_SEND (0x402) /* Single Frame Transmission */
1183#define BNA_TXQ_WI_SEND_LSO (0x403) /* Multi-Frame Transmission */ 1183#define BNA_TXQ_WI_SEND_LSO (0x403) /* Multi-Frame Transmission */
1184#define BNA_TXQ_WI_EXTENSION (0x104) /* Extension WI */ 1184#define BNA_TXQ_WI_EXTENSION (0x104) /* Extension WI */
1185 1185
1186/* TxQ Entry Control Flags */ 1186/* TxQ Entry Control Flags */
1187#define BNA_TXQ_WI_CF_FCOE_CRC (1 << 8) 1187#define BNA_TXQ_WI_CF_FCOE_CRC (1 << 8)
1188#define BNA_TXQ_WI_CF_IPID_MODE (1 << 5) 1188#define BNA_TXQ_WI_CF_IPID_MODE (1 << 5)
1189#define BNA_TXQ_WI_CF_INS_PRIO (1 << 4) 1189#define BNA_TXQ_WI_CF_INS_PRIO (1 << 4)
1190#define BNA_TXQ_WI_CF_INS_VLAN (1 << 3) 1190#define BNA_TXQ_WI_CF_INS_VLAN (1 << 3)
1191#define BNA_TXQ_WI_CF_UDP_CKSUM (1 << 2) 1191#define BNA_TXQ_WI_CF_UDP_CKSUM (1 << 2)
1192#define BNA_TXQ_WI_CF_TCP_CKSUM (1 << 1) 1192#define BNA_TXQ_WI_CF_TCP_CKSUM (1 << 1)
1193#define BNA_TXQ_WI_CF_IP_CKSUM (1 << 0) 1193#define BNA_TXQ_WI_CF_IP_CKSUM (1 << 0)
1194 1194
1195#define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \ 1195#define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \
1196 (((_hdr_size) << 10) | ((_offset) & 0x3FF)) 1196 (((_hdr_size) << 10) | ((_offset) & 0x3FF))
@@ -1199,30 +1199,30 @@ do {\
1199 * Completion Q defines 1199 * Completion Q defines
1200 */ 1200 */
1201/* CQ Entry Flags */ 1201/* CQ Entry Flags */
1202#define BNA_CQ_EF_MAC_ERROR (1 << 0) 1202#define BNA_CQ_EF_MAC_ERROR (1 << 0)
1203#define BNA_CQ_EF_FCS_ERROR (1 << 1) 1203#define BNA_CQ_EF_FCS_ERROR (1 << 1)
1204#define BNA_CQ_EF_TOO_LONG (1 << 2) 1204#define BNA_CQ_EF_TOO_LONG (1 << 2)
1205#define BNA_CQ_EF_FC_CRC_OK (1 << 3) 1205#define BNA_CQ_EF_FC_CRC_OK (1 << 3)
1206 1206
1207#define BNA_CQ_EF_RSVD1 (1 << 4) 1207#define BNA_CQ_EF_RSVD1 (1 << 4)
1208#define BNA_CQ_EF_L4_CKSUM_OK (1 << 5) 1208#define BNA_CQ_EF_L4_CKSUM_OK (1 << 5)
1209#define BNA_CQ_EF_L3_CKSUM_OK (1 << 6) 1209#define BNA_CQ_EF_L3_CKSUM_OK (1 << 6)
1210#define BNA_CQ_EF_HDS_HEADER (1 << 7) 1210#define BNA_CQ_EF_HDS_HEADER (1 << 7)
1211 1211
1212#define BNA_CQ_EF_UDP (1 << 8) 1212#define BNA_CQ_EF_UDP (1 << 8)
1213#define BNA_CQ_EF_TCP (1 << 9) 1213#define BNA_CQ_EF_TCP (1 << 9)
1214#define BNA_CQ_EF_IP_OPTIONS (1 << 10) 1214#define BNA_CQ_EF_IP_OPTIONS (1 << 10)
1215#define BNA_CQ_EF_IPV6 (1 << 11) 1215#define BNA_CQ_EF_IPV6 (1 << 11)
1216 1216
1217#define BNA_CQ_EF_IPV4 (1 << 12) 1217#define BNA_CQ_EF_IPV4 (1 << 12)
1218#define BNA_CQ_EF_VLAN (1 << 13) 1218#define BNA_CQ_EF_VLAN (1 << 13)
1219#define BNA_CQ_EF_RSS (1 << 14) 1219#define BNA_CQ_EF_RSS (1 << 14)
1220#define BNA_CQ_EF_RSVD2 (1 << 15) 1220#define BNA_CQ_EF_RSVD2 (1 << 15)
1221 1221
1222#define BNA_CQ_EF_MCAST_MATCH (1 << 16) 1222#define BNA_CQ_EF_MCAST_MATCH (1 << 16)
1223#define BNA_CQ_EF_MCAST (1 << 17) 1223#define BNA_CQ_EF_MCAST (1 << 17)
1224#define BNA_CQ_EF_BCAST (1 << 18) 1224#define BNA_CQ_EF_BCAST (1 << 18)
1225#define BNA_CQ_EF_REMOTE (1 << 19) 1225#define BNA_CQ_EF_REMOTE (1 << 19)
1226 1226
1227#define BNA_CQ_EF_LOCAL (1 << 20) 1227#define BNA_CQ_EF_LOCAL (1 << 20)
1228 1228
@@ -1257,10 +1257,10 @@ enum ib_flags {
1257}; 1257};
1258 1258
1259enum rss_hash_type { 1259enum rss_hash_type {
1260 BFI_RSS_T_V4_TCP = (1 << 11), 1260 BFI_RSS_T_V4_TCP = (1 << 11),
1261 BFI_RSS_T_V4_IP = (1 << 10), 1261 BFI_RSS_T_V4_IP = (1 << 10),
1262 BFI_RSS_T_V6_TCP = (1 << 9), 1262 BFI_RSS_T_V6_TCP = (1 << 9),
1263 BFI_RSS_T_V6_IP = (1 << 8) 1263 BFI_RSS_T_V6_IP = (1 << 8)
1264}; 1264};
1265enum hds_header_type { 1265enum hds_header_type {
1266 BNA_HDS_T_V4_TCP = (1 << 11), 1266 BNA_HDS_T_V4_TCP = (1 << 11),
@@ -1298,7 +1298,7 @@ struct bna_txq_mem {
1298 u32 reserved2; 1298 u32 reserved2;
1299 u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */ 1299 u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */
1300 /* 15:0 ->producer pointer (index?) */ 1300 /* 15:0 ->producer pointer (index?) */
1301 u32 entry_n_pg_size; /* 31:16->entry size */ 1301 u32 entry_n_pg_size; /* 31:16->entry size */
1302 /* 15:0 ->page size */ 1302 /* 15:0 ->page size */
1303 u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */ 1303 u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */
1304 /* 23:16->Int Blk Offset */ 1304 /* 23:16->Int Blk Offset */
@@ -1326,7 +1326,7 @@ struct bna_rxq_mem {
1326 u32 sg_n_cq_n_cns_ptr; /* 31:28->reserved; 27:24->sg count */ 1326 u32 sg_n_cq_n_cns_ptr; /* 31:28->reserved; 27:24->sg count */
1327 /* 23:16->CQ; */ 1327 /* 23:16->CQ; */
1328 /* 15:0->consumer pointer(index?) */ 1328 /* 15:0->consumer pointer(index?) */
1329 u32 buf_sz_n_q_state; /* 31:16->buffer size; 15:0-> Q state */ 1329 u32 buf_sz_n_q_state; /* 31:16->buffer size; 15:0-> Q state */
1330 u32 next_qid; /* 17:10->next QId */ 1330 u32 next_qid; /* 17:10->next QId */
1331 u32 reserved3; 1331 u32 reserved3;
1332 u32 reserved4[4]; 1332 u32 reserved4[4];
@@ -1426,8 +1426,8 @@ struct bna_dma_addr {
1426}; 1426};
1427 1427
1428struct bna_txq_wi_vector { 1428struct bna_txq_wi_vector {
1429 u16 reserved; 1429 u16 reserved;
1430 u16 length; /* Only 14 LSB are valid */ 1430 u16 length; /* Only 14 LSB are valid */
1431 struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */ 1431 struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */
1432}; 1432};
1433 1433
@@ -1465,7 +1465,7 @@ struct bna_txq_entry {
1465 } hdr; 1465 } hdr;
1466 struct bna_txq_wi_vector vector[4]; 1466 struct bna_txq_wi_vector vector[4];
1467}; 1467};
1468#define wi_hdr hdr.wi 1468#define wi_hdr hdr.wi
1469#define wi_ext_hdr hdr.wi_ext 1469#define wi_ext_hdr hdr.wi_ext
1470 1470
1471/* RxQ Entry Structure */ 1471/* RxQ Entry Structure */
diff --git a/drivers/net/bna/bna_txrx.c b/drivers/net/bna/bna_txrx.c
index 380085cc3088..2c06e089bb8e 100644
--- a/drivers/net/bna/bna_txrx.c
+++ b/drivers/net/bna/bna_txrx.c
@@ -734,7 +734,7 @@ bna_rxf_sm_cam_fltr_clr_wait_entry(struct bna_rxf *rxf)
734 /** 734 /**
735 * Note: Do not add rxf_clear_packet_filter here. 735 * Note: Do not add rxf_clear_packet_filter here.
736 * It will overstep mbox when this transition happens: 736 * It will overstep mbox when this transition happens:
737 * cam_fltr_mod_wait -> cam_fltr_clr_wait on RXF_E_STOP event 737 * cam_fltr_mod_wait -> cam_fltr_clr_wait on RXF_E_STOP event
738 */ 738 */
739} 739}
740 740
@@ -771,7 +771,7 @@ bna_rxf_sm_stop_wait_entry(struct bna_rxf *rxf)
771 /** 771 /**
772 * NOTE: Do not add rxf_disable here. 772 * NOTE: Do not add rxf_disable here.
773 * It will overstep mbox when this transition happens: 773 * It will overstep mbox when this transition happens:
774 * start_wait -> stop_wait on RXF_E_STOP event 774 * start_wait -> stop_wait on RXF_E_STOP event
775 */ 775 */
776} 776}
777 777
diff --git a/drivers/net/bna/bna_types.h b/drivers/net/bna/bna_types.h
index b9c134f7ad31..2f89cb235248 100644
--- a/drivers/net/bna/bna_types.h
+++ b/drivers/net/bna/bna_types.h
@@ -50,12 +50,12 @@ enum bna_status {
50}; 50};
51 51
52enum bna_cleanup_type { 52enum bna_cleanup_type {
53 BNA_HARD_CLEANUP = 0, 53 BNA_HARD_CLEANUP = 0,
54 BNA_SOFT_CLEANUP = 1 54 BNA_SOFT_CLEANUP = 1
55}; 55};
56 56
57enum bna_cb_status { 57enum bna_cb_status {
58 BNA_CB_SUCCESS = 0, 58 BNA_CB_SUCCESS = 0,
59 BNA_CB_FAIL = 1, 59 BNA_CB_FAIL = 1,
60 BNA_CB_INTERRUPT = 2, 60 BNA_CB_INTERRUPT = 2,
61 BNA_CB_BUSY = 3, 61 BNA_CB_BUSY = 3,
@@ -72,8 +72,8 @@ enum bna_res_type {
72}; 72};
73 73
74enum bna_mem_type { 74enum bna_mem_type {
75 BNA_MEM_T_KVA = 1, 75 BNA_MEM_T_KVA = 1,
76 BNA_MEM_T_DMA = 2 76 BNA_MEM_T_DMA = 2
77}; 77};
78 78
79enum bna_intr_type { 79enum bna_intr_type {
@@ -82,10 +82,10 @@ enum bna_intr_type {
82}; 82};
83 83
84enum bna_res_req_type { 84enum bna_res_req_type {
85 BNA_RES_MEM_T_COM = 0, 85 BNA_RES_MEM_T_COM = 0,
86 BNA_RES_MEM_T_ATTR = 1, 86 BNA_RES_MEM_T_ATTR = 1,
87 BNA_RES_MEM_T_FWTRC = 2, 87 BNA_RES_MEM_T_FWTRC = 2,
88 BNA_RES_MEM_T_STATS = 3, 88 BNA_RES_MEM_T_STATS = 3,
89 BNA_RES_MEM_T_SWSTATS = 4, 89 BNA_RES_MEM_T_SWSTATS = 4,
90 BNA_RES_MEM_T_IBIDX = 5, 90 BNA_RES_MEM_T_IBIDX = 5,
91 BNA_RES_MEM_T_IB_ARRAY = 6, 91 BNA_RES_MEM_T_IB_ARRAY = 6,
@@ -107,9 +107,9 @@ enum bna_res_req_type {
107enum bna_tx_res_req_type { 107enum bna_tx_res_req_type {
108 BNA_TX_RES_MEM_T_TCB = 0, 108 BNA_TX_RES_MEM_T_TCB = 0,
109 BNA_TX_RES_MEM_T_UNMAPQ = 1, 109 BNA_TX_RES_MEM_T_UNMAPQ = 1,
110 BNA_TX_RES_MEM_T_QPT = 2, 110 BNA_TX_RES_MEM_T_QPT = 2,
111 BNA_TX_RES_MEM_T_SWQPT = 3, 111 BNA_TX_RES_MEM_T_SWQPT = 3,
112 BNA_TX_RES_MEM_T_PAGE = 4, 112 BNA_TX_RES_MEM_T_PAGE = 4,
113 BNA_TX_RES_INTR_T_TXCMPL = 5, 113 BNA_TX_RES_INTR_T_TXCMPL = 5,
114 BNA_TX_RES_T_MAX, 114 BNA_TX_RES_T_MAX,
115}; 115};
@@ -158,14 +158,14 @@ enum bna_rx_type {
158}; 158};
159 159
160enum bna_rxp_type { 160enum bna_rxp_type {
161 BNA_RXP_SINGLE = 1, 161 BNA_RXP_SINGLE = 1,
162 BNA_RXP_SLR = 2, 162 BNA_RXP_SLR = 2,
163 BNA_RXP_HDS = 3 163 BNA_RXP_HDS = 3
164}; 164};
165 165
166enum bna_rxmode { 166enum bna_rxmode {
167 BNA_RXMODE_PROMISC = 1, 167 BNA_RXMODE_PROMISC = 1,
168 BNA_RXMODE_ALLMULTI = 2 168 BNA_RXMODE_ALLMULTI = 2
169}; 169};
170 170
171enum bna_rx_event { 171enum bna_rx_event {
@@ -202,7 +202,7 @@ enum bna_rxf_oper_state {
202}; 202};
203 203
204enum bna_rxf_flags { 204enum bna_rxf_flags {
205 BNA_RXF_FL_STOP_PENDING = 0x01, 205 BNA_RXF_FL_STOP_PENDING = 0x01,
206 BNA_RXF_FL_FAILED = 0x02, 206 BNA_RXF_FL_FAILED = 0x02,
207 BNA_RXF_FL_RSS_CONFIG_PENDING = 0x04, 207 BNA_RXF_FL_RSS_CONFIG_PENDING = 0x04,
208 BNA_RXF_FL_OPERSTATE_CHANGED = 0x08, 208 BNA_RXF_FL_OPERSTATE_CHANGED = 0x08,
@@ -244,11 +244,11 @@ enum bna_port_type {
244enum bna_link_status { 244enum bna_link_status {
245 BNA_LINK_DOWN = 0, 245 BNA_LINK_DOWN = 0,
246 BNA_LINK_UP = 1, 246 BNA_LINK_UP = 1,
247 BNA_CEE_UP = 2 247 BNA_CEE_UP = 2
248}; 248};
249 249
250enum bna_llport_flags { 250enum bna_llport_flags {
251 BNA_LLPORT_F_ADMIN_UP = 1, 251 BNA_LLPORT_F_ADMIN_UP = 1,
252 BNA_LLPORT_F_PORT_ENABLED = 2, 252 BNA_LLPORT_F_PORT_ENABLED = 2,
253 BNA_LLPORT_F_RX_STARTED = 4 253 BNA_LLPORT_F_RX_STARTED = 4
254}; 254};
@@ -304,7 +304,7 @@ struct bna_mem_descr {
304struct bna_mem_info { 304struct bna_mem_info {
305 enum bna_mem_type mem_type; 305 enum bna_mem_type mem_type;
306 u32 len; 306 u32 len;
307 u32 num; 307 u32 num;
308 u32 align_sz; /* 0/1 = no alignment */ 308 u32 align_sz; /* 0/1 = no alignment */
309 struct bna_mem_descr *mdl; 309 struct bna_mem_descr *mdl;
310 void *cookie; /* For bnad to unmap dma later */ 310 void *cookie; /* For bnad to unmap dma later */
@@ -371,10 +371,10 @@ struct bna_mbox_qe {
371 struct list_head qe; 371 struct list_head qe;
372 372
373 struct bfa_mbox_cmd cmd; 373 struct bfa_mbox_cmd cmd;
374 u32 cmd_len; 374 u32 cmd_len;
375 /* Callback for port, tx, rx, rxf */ 375 /* Callback for port, tx, rx, rxf */
376 void (*cbfn)(void *arg, int status); 376 void (*cbfn)(void *arg, int status);
377 void *cbarg; 377 void *cbarg;
378}; 378};
379 379
380struct bna_mbox_mod { 380struct bna_mbox_mod {
@@ -480,7 +480,7 @@ struct bna_ib_dbell {
480 480
481/* Interrupt timer configuration */ 481/* Interrupt timer configuration */
482struct bna_ib_config { 482struct bna_ib_config {
483 u8 coalescing_timeo; /* Unit is 5usec. */ 483 u8 coalescing_timeo; /* Unit is 5usec. */
484 484
485 int interpkt_count; 485 int interpkt_count;
486 int interpkt_timeo; 486 int interpkt_timeo;
@@ -576,8 +576,8 @@ struct bna_txq {
576 576
577 struct bna_tx *tx; 577 struct bna_tx *tx;
578 578
579 u64 tx_packets; 579 u64 tx_packets;
580 u64 tx_bytes; 580 u64 tx_bytes;
581}; 581};
582 582
583/* TxF structure (hardware Tx Function) */ 583/* TxF structure (hardware Tx Function) */
@@ -739,10 +739,10 @@ struct bna_rxq {
739 struct bna_rxp *rxp; 739 struct bna_rxp *rxp;
740 struct bna_rx *rx; 740 struct bna_rx *rx;
741 741
742 u64 rx_packets; 742 u64 rx_packets;
743 u64 rx_bytes; 743 u64 rx_bytes;
744 u64 rx_packets_with_error; 744 u64 rx_packets_with_error;
745 u64 rxbuf_alloc_failed; 745 u64 rxbuf_alloc_failed;
746}; 746};
747 747
748/* RxQ pair */ 748/* RxQ pair */
@@ -902,7 +902,7 @@ struct bna_rxf {
902 * callback for: 902 * callback for:
903 * bna_rxf_ucast_set() 903 * bna_rxf_ucast_set()
904 * bna_rxf_{ucast/mcast}_add(), 904 * bna_rxf_{ucast/mcast}_add(),
905 * bna_rxf_{ucast/mcast}_del(), 905 * bna_rxf_{ucast/mcast}_del(),
906 * bna_rxf_mode_set() 906 * bna_rxf_mode_set()
907 */ 907 */
908 void (*cam_fltr_cbfn)(struct bnad *bnad, struct bna_rx *rx, 908 void (*cam_fltr_cbfn)(struct bnad *bnad, struct bna_rx *rx,
diff --git a/drivers/net/bna/bnad.c b/drivers/net/bna/bnad.c
index 3e7a90f3e5be..dd771562e31e 100644
--- a/drivers/net/bna/bnad.c
+++ b/drivers/net/bna/bnad.c
@@ -60,7 +60,7 @@ static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
60 60
61#define BNAD_GET_MBOX_IRQ(_bnad) \ 61#define BNAD_GET_MBOX_IRQ(_bnad) \
62 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \ 62 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
63 ((_bnad)->msix_table[(_bnad)->msix_num - 1].vector) : \ 63 ((_bnad)->msix_table[(_bnad)->msix_num - 1].vector) : \
64 ((_bnad)->pcidev->irq)) 64 ((_bnad)->pcidev->irq))
65 65
66#define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \ 66#define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
@@ -112,10 +112,10 @@ static void
112bnad_free_all_txbufs(struct bnad *bnad, 112bnad_free_all_txbufs(struct bnad *bnad,
113 struct bna_tcb *tcb) 113 struct bna_tcb *tcb)
114{ 114{
115 u32 unmap_cons; 115 u32 unmap_cons;
116 struct bnad_unmap_q *unmap_q = tcb->unmap_q; 116 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
117 struct bnad_skb_unmap *unmap_array; 117 struct bnad_skb_unmap *unmap_array;
118 struct sk_buff *skb = NULL; 118 struct sk_buff *skb = NULL;
119 int i; 119 int i;
120 120
121 unmap_array = unmap_q->unmap_array; 121 unmap_array = unmap_q->unmap_array;
@@ -165,11 +165,11 @@ static u32
165bnad_free_txbufs(struct bnad *bnad, 165bnad_free_txbufs(struct bnad *bnad,
166 struct bna_tcb *tcb) 166 struct bna_tcb *tcb)
167{ 167{
168 u32 sent_packets = 0, sent_bytes = 0; 168 u32 sent_packets = 0, sent_bytes = 0;
169 u16 wis, unmap_cons, updated_hw_cons; 169 u16 wis, unmap_cons, updated_hw_cons;
170 struct bnad_unmap_q *unmap_q = tcb->unmap_q; 170 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
171 struct bnad_skb_unmap *unmap_array; 171 struct bnad_skb_unmap *unmap_array;
172 struct sk_buff *skb; 172 struct sk_buff *skb;
173 int i; 173 int i;
174 174
175 /* 175 /*
@@ -247,7 +247,7 @@ bnad_tx_free_tasklet(unsigned long bnad_ptr)
247{ 247{
248 struct bnad *bnad = (struct bnad *)bnad_ptr; 248 struct bnad *bnad = (struct bnad *)bnad_ptr;
249 struct bna_tcb *tcb; 249 struct bna_tcb *tcb;
250 u32 acked = 0; 250 u32 acked = 0;
251 int i, j; 251 int i, j;
252 252
253 for (i = 0; i < bnad->num_tx; i++) { 253 for (i = 0; i < bnad->num_tx; i++) {
@@ -1102,10 +1102,10 @@ static int
1102bnad_mbox_irq_alloc(struct bnad *bnad, 1102bnad_mbox_irq_alloc(struct bnad *bnad,
1103 struct bna_intr_info *intr_info) 1103 struct bna_intr_info *intr_info)
1104{ 1104{
1105 int err = 0; 1105 int err = 0;
1106 unsigned long irq_flags, flags; 1106 unsigned long irq_flags, flags;
1107 u32 irq; 1107 u32 irq;
1108 irq_handler_t irq_handler; 1108 irq_handler_t irq_handler;
1109 1109
1110 /* Mbox should use only 1 vector */ 1110 /* Mbox should use only 1 vector */
1111 1111
@@ -1447,7 +1447,7 @@ bnad_iocpf_sem_timeout(unsigned long data)
1447/* 1447/*
1448 * All timer routines use bnad->bna_lock to protect against 1448 * All timer routines use bnad->bna_lock to protect against
1449 * the following race, which may occur in case of no locking: 1449 * the following race, which may occur in case of no locking:
1450 * Time CPU m CPU n 1450 * Time CPU m CPU n
1451 * 0 1 = test_bit 1451 * 0 1 = test_bit
1452 * 1 clear_bit 1452 * 1 clear_bit
1453 * 2 del_timer_sync 1453 * 2 del_timer_sync
@@ -1912,7 +1912,7 @@ void
1912bnad_rx_coalescing_timeo_set(struct bnad *bnad) 1912bnad_rx_coalescing_timeo_set(struct bnad *bnad)
1913{ 1913{
1914 struct bnad_rx_info *rx_info; 1914 struct bnad_rx_info *rx_info;
1915 int i; 1915 int i;
1916 1916
1917 for (i = 0; i < bnad->num_rx; i++) { 1917 for (i = 0; i < bnad->num_rx; i++) {
1918 rx_info = &bnad->rx_info[i]; 1918 rx_info = &bnad->rx_info[i];
@@ -2426,18 +2426,18 @@ bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2426{ 2426{
2427 struct bnad *bnad = netdev_priv(netdev); 2427 struct bnad *bnad = netdev_priv(netdev);
2428 2428
2429 u16 txq_prod, vlan_tag = 0; 2429 u16 txq_prod, vlan_tag = 0;
2430 u32 unmap_prod, wis, wis_used, wi_range; 2430 u32 unmap_prod, wis, wis_used, wi_range;
2431 u32 vectors, vect_id, i, acked; 2431 u32 vectors, vect_id, i, acked;
2432 u32 tx_id; 2432 u32 tx_id;
2433 int err; 2433 int err;
2434 2434
2435 struct bnad_tx_info *tx_info; 2435 struct bnad_tx_info *tx_info;
2436 struct bna_tcb *tcb; 2436 struct bna_tcb *tcb;
2437 struct bnad_unmap_q *unmap_q; 2437 struct bnad_unmap_q *unmap_q;
2438 dma_addr_t dma_addr; 2438 dma_addr_t dma_addr;
2439 struct bna_txq_entry *txqent; 2439 struct bna_txq_entry *txqent;
2440 bna_txq_wi_ctrl_flag_t flags; 2440 bna_txq_wi_ctrl_flag_t flags;
2441 2441
2442 if (unlikely 2442 if (unlikely
2443 (skb->len <= ETH_HLEN || skb->len > BFI_TX_MAX_DATA_PER_PKT)) { 2443 (skb->len <= ETH_HLEN || skb->len > BFI_TX_MAX_DATA_PER_PKT)) {
@@ -3033,8 +3033,8 @@ static int __devinit
3033bnad_pci_probe(struct pci_dev *pdev, 3033bnad_pci_probe(struct pci_dev *pdev,
3034 const struct pci_device_id *pcidev_id) 3034 const struct pci_device_id *pcidev_id)
3035{ 3035{
3036 bool using_dac = false; 3036 bool using_dac = false;
3037 int err; 3037 int err;
3038 struct bnad *bnad; 3038 struct bnad *bnad;
3039 struct bna *bna; 3039 struct bna *bna;
3040 struct net_device *netdev; 3040 struct net_device *netdev;
@@ -3066,7 +3066,7 @@ bnad_pci_probe(struct pci_dev *pdev,
3066 3066
3067 /* 3067 /*
3068 * PCI initialization 3068 * PCI initialization
3069 * Output : using_dac = 1 for 64 bit DMA 3069 * Output : using_dac = 1 for 64 bit DMA
3070 * = 0 for 32 bit DMA 3070 * = 0 for 32 bit DMA
3071 */ 3071 */
3072 err = bnad_pci_init(bnad, pdev, &using_dac); 3072 err = bnad_pci_init(bnad, pdev, &using_dac);
@@ -3209,7 +3209,7 @@ bnad_pci_remove(struct pci_dev *pdev)
3209 free_netdev(netdev); 3209 free_netdev(netdev);
3210} 3210}
3211 3211
3212static const struct pci_device_id bnad_pci_id_table[] = { 3212static DEFINE_PCI_DEVICE_TABLE(bnad_pci_id_table) = {
3213 { 3213 {
3214 PCI_DEVICE(PCI_VENDOR_ID_BROCADE, 3214 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3215 PCI_DEVICE_ID_BROCADE_CT), 3215 PCI_DEVICE_ID_BROCADE_CT),
diff --git a/drivers/net/bna/bnad.h b/drivers/net/bna/bnad.h
index 7aa550b6182d..ea97060f9e95 100644
--- a/drivers/net/bna/bnad.h
+++ b/drivers/net/bna/bnad.h
@@ -70,8 +70,8 @@ struct bnad_rx_ctrl {
70 70
71#define BNAD_MAILBOX_MSIX_VECTORS 1 71#define BNAD_MAILBOX_MSIX_VECTORS 1
72 72
73#define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */ 73#define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */
74#define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */ 74#define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */
75 75
76#define BNAD_MAX_Q_DEPTH 0x10000 76#define BNAD_MAX_Q_DEPTH 0x10000
77#define BNAD_MIN_Q_DEPTH 0x200 77#define BNAD_MIN_Q_DEPTH 0x200
@@ -102,12 +102,12 @@ enum bnad_intr_source {
102 102
103enum bnad_link_state { 103enum bnad_link_state {
104 BNAD_LS_DOWN = 0, 104 BNAD_LS_DOWN = 0,
105 BNAD_LS_UP = 1 105 BNAD_LS_UP = 1
106}; 106};
107 107
108struct bnad_completion { 108struct bnad_completion {
109 struct completion ioc_comp; 109 struct completion ioc_comp;
110 struct completion ucast_comp; 110 struct completion ucast_comp;
111 struct completion mcast_comp; 111 struct completion mcast_comp;
112 struct completion tx_comp; 112 struct completion tx_comp;
113 struct completion rx_comp; 113 struct completion rx_comp;
@@ -125,7 +125,7 @@ struct bnad_completion {
125 125
126/* Tx Rx Control Stats */ 126/* Tx Rx Control Stats */
127struct bnad_drv_stats { 127struct bnad_drv_stats {
128 u64 netif_queue_stop; 128 u64 netif_queue_stop;
129 u64 netif_queue_wakeup; 129 u64 netif_queue_wakeup;
130 u64 netif_queue_stopped; 130 u64 netif_queue_stopped;
131 u64 tso4; 131 u64 tso4;
@@ -188,7 +188,7 @@ struct bnad_skb_unmap {
188struct bnad_unmap_q { 188struct bnad_unmap_q {
189 u32 producer_index; 189 u32 producer_index;
190 u32 consumer_index; 190 u32 consumer_index;
191 u32 q_depth; 191 u32 q_depth;
192 /* This should be the last one */ 192 /* This should be the last one */
193 struct bnad_skb_unmap unmap_array[1]; 193 struct bnad_skb_unmap unmap_array[1];
194}; 194};
@@ -211,7 +211,7 @@ struct bnad_unmap_q {
211#define BNAD_RF_RX_SHUTDOWN_DELAYED 7 211#define BNAD_RF_RX_SHUTDOWN_DELAYED 7
212 212
213struct bnad { 213struct bnad {
214 struct net_device *netdev; 214 struct net_device *netdev;
215 215
216 /* Data path */ 216 /* Data path */
217 struct bnad_tx_info tx_info[BNAD_MAX_TXS]; 217 struct bnad_tx_info tx_info[BNAD_MAX_TXS];
@@ -245,7 +245,7 @@ struct bnad {
245 u32 cfg_flags; 245 u32 cfg_flags;
246 unsigned long run_flags; 246 unsigned long run_flags;
247 247
248 struct pci_dev *pcidev; 248 struct pci_dev *pcidev;
249 u64 mmio_start; 249 u64 mmio_start;
250 u64 mmio_len; 250 u64 mmio_len;
251 251
@@ -278,7 +278,7 @@ struct bnad {
278 struct bnad_diag *diag; 278 struct bnad_diag *diag;
279 279
280 char adapter_name[BNAD_NAME_LEN]; 280 char adapter_name[BNAD_NAME_LEN];
281 char port_name[BNAD_NAME_LEN]; 281 char port_name[BNAD_NAME_LEN];
282 char mbox_irq_name[BNAD_NAME_LEN]; 282 char mbox_irq_name[BNAD_NAME_LEN];
283}; 283};
284 284
@@ -286,7 +286,7 @@ struct bnad {
286 * EXTERN VARIABLES 286 * EXTERN VARIABLES
287 */ 287 */
288extern struct firmware *bfi_fw; 288extern struct firmware *bfi_fw;
289extern u32 bnad_rxqs_per_cq; 289extern u32 bnad_rxqs_per_cq;
290 290
291/* 291/*
292 * EXTERN PROTOTYPES 292 * EXTERN PROTOTYPES
@@ -332,7 +332,7 @@ extern void bnad_netdev_hwstats_fill(struct bnad *bnad,
332} 332}
333 333
334#define bnad_dim_timer_running(_bnad) \ 334#define bnad_dim_timer_running(_bnad) \
335 (((_bnad)->cfg_flags & BNAD_CF_DIM_ENABLED) && \ 335 (((_bnad)->cfg_flags & BNAD_CF_DIM_ENABLED) && \
336 (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &((_bnad)->run_flags)))) 336 (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &((_bnad)->run_flags))))
337 337
338#endif /* __BNAD_H__ */ 338#endif /* __BNAD_H__ */
diff --git a/drivers/net/bna/bnad_ethtool.c b/drivers/net/bna/bnad_ethtool.c
index 3330cd78da2c..fea07f19a5db 100644
--- a/drivers/net/bna/bnad_ethtool.c
+++ b/drivers/net/bna/bnad_ethtool.c
@@ -295,7 +295,7 @@ get_regs(struct bnad *bnad, u32 * regs)
295 u32 reg_addr; 295 u32 reg_addr;
296 unsigned long flags; 296 unsigned long flags;
297 297
298#define BNAD_GET_REG(addr) \ 298#define BNAD_GET_REG(addr) \
299do { \ 299do { \
300 if (regs) \ 300 if (regs) \
301 regs[num++] = readl(bnad->bar0 + (addr)); \ 301 regs[num++] = readl(bnad->bar0 + (addr)); \
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 06:38:13 -0500