diff options
-rw-r--r-- | arch/mips/ddb5xxx/ddb5477/irq.c | 5 | ||||
-rw-r--r-- | arch/mips/kernel/i8259.c | 20 | ||||
-rw-r--r-- | arch/mips/pci/fixup-vr4133.c | 13 | ||||
-rw-r--r-- | arch/mips/vr41xx/nec-cmbvr4133/irq.c | 53 | ||||
-rw-r--r-- | include/asm-mips/ddb5xxx/ddb5477.h | 36 | ||||
-rw-r--r-- | include/asm-mips/i8259.h | 3 | ||||
-rw-r--r-- | include/asm-mips/irq.h | 2 | ||||
-rw-r--r-- | include/asm-mips/mach-generic/irq.h | 6 | ||||
-rw-r--r-- | include/asm-mips/mach-vr41xx/irq.h | 3 | ||||
-rw-r--r-- | include/asm-mips/vr41xx/cmbvr4133.h | 5 |
10 files changed, 49 insertions, 97 deletions
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c index bd7cd7c5f485..2b23234a5b95 100644 --- a/arch/mips/ddb5xxx/ddb5477/irq.c +++ b/arch/mips/ddb5xxx/ddb5477/irq.c | |||
@@ -146,8 +146,7 @@ u8 i8259_interrupt_ack(void) | |||
146 | irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); | 146 | irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); |
147 | ddb_out32(DDB_PCIINIT10, reg); | 147 | ddb_out32(DDB_PCIINIT10, reg); |
148 | 148 | ||
149 | /* i8259.c set the base vector to be 0x0 */ | 149 | return irq; |
150 | return irq + I8259_IRQ_BASE; | ||
151 | } | 150 | } |
152 | /* | 151 | /* |
153 | * the first level int-handler will jump here if it is a vrc5477 irq | 152 | * the first level int-handler will jump here if it is a vrc5477 irq |
@@ -177,7 +176,7 @@ static void vrc5477_irq_dispatch(void) | |||
177 | /* check for i8259 interrupts */ | 176 | /* check for i8259 interrupts */ |
178 | if (intStatus & (1 << VRC5477_I8259_CASCADE)) { | 177 | if (intStatus & (1 << VRC5477_I8259_CASCADE)) { |
179 | int i8259_irq = i8259_interrupt_ack(); | 178 | int i8259_irq = i8259_interrupt_ack(); |
180 | do_IRQ(I8259_IRQ_BASE + i8259_irq); | 179 | do_IRQ(i8259_irq); |
181 | return; | 180 | return; |
182 | } | 181 | } |
183 | } | 182 | } |
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index b59a676c6d0e..91de4223d638 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c | |||
@@ -54,9 +54,11 @@ static unsigned int cached_irq_mask = 0xffff; | |||
54 | 54 | ||
55 | void disable_8259A_irq(unsigned int irq) | 55 | void disable_8259A_irq(unsigned int irq) |
56 | { | 56 | { |
57 | unsigned int mask = 1 << irq; | 57 | unsigned int mask; |
58 | unsigned long flags; | 58 | unsigned long flags; |
59 | 59 | ||
60 | irq -= I8259A_IRQ_BASE; | ||
61 | mask = 1 << irq; | ||
60 | spin_lock_irqsave(&i8259A_lock, flags); | 62 | spin_lock_irqsave(&i8259A_lock, flags); |
61 | cached_irq_mask |= mask; | 63 | cached_irq_mask |= mask; |
62 | if (irq & 8) | 64 | if (irq & 8) |
@@ -68,9 +70,11 @@ void disable_8259A_irq(unsigned int irq) | |||
68 | 70 | ||
69 | void enable_8259A_irq(unsigned int irq) | 71 | void enable_8259A_irq(unsigned int irq) |
70 | { | 72 | { |
71 | unsigned int mask = ~(1 << irq); | 73 | unsigned int mask; |
72 | unsigned long flags; | 74 | unsigned long flags; |
73 | 75 | ||
76 | irq -= I8259A_IRQ_BASE; | ||
77 | mask = ~(1 << irq); | ||
74 | spin_lock_irqsave(&i8259A_lock, flags); | 78 | spin_lock_irqsave(&i8259A_lock, flags); |
75 | cached_irq_mask &= mask; | 79 | cached_irq_mask &= mask; |
76 | if (irq & 8) | 80 | if (irq & 8) |
@@ -82,10 +86,12 @@ void enable_8259A_irq(unsigned int irq) | |||
82 | 86 | ||
83 | int i8259A_irq_pending(unsigned int irq) | 87 | int i8259A_irq_pending(unsigned int irq) |
84 | { | 88 | { |
85 | unsigned int mask = 1 << irq; | 89 | unsigned int mask; |
86 | unsigned long flags; | 90 | unsigned long flags; |
87 | int ret; | 91 | int ret; |
88 | 92 | ||
93 | irq -= I8259A_IRQ_BASE; | ||
94 | mask = 1 << irq; | ||
89 | spin_lock_irqsave(&i8259A_lock, flags); | 95 | spin_lock_irqsave(&i8259A_lock, flags); |
90 | if (irq < 8) | 96 | if (irq < 8) |
91 | ret = inb(PIC_MASTER_CMD) & mask; | 97 | ret = inb(PIC_MASTER_CMD) & mask; |
@@ -134,9 +140,11 @@ static inline int i8259A_irq_real(unsigned int irq) | |||
134 | */ | 140 | */ |
135 | void mask_and_ack_8259A(unsigned int irq) | 141 | void mask_and_ack_8259A(unsigned int irq) |
136 | { | 142 | { |
137 | unsigned int irqmask = 1 << irq; | 143 | unsigned int irqmask; |
138 | unsigned long flags; | 144 | unsigned long flags; |
139 | 145 | ||
146 | irq -= I8259A_IRQ_BASE; | ||
147 | irqmask = 1 << irq; | ||
140 | spin_lock_irqsave(&i8259A_lock, flags); | 148 | spin_lock_irqsave(&i8259A_lock, flags); |
141 | /* | 149 | /* |
142 | * Lightweight spurious IRQ detection. We do not want | 150 | * Lightweight spurious IRQ detection. We do not want |
@@ -322,8 +330,8 @@ void __init init_i8259_irqs (void) | |||
322 | 330 | ||
323 | init_8259A(0); | 331 | init_8259A(0); |
324 | 332 | ||
325 | for (i = 0; i < 16; i++) | 333 | for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) |
326 | set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq); | 334 | set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq); |
327 | 335 | ||
328 | setup_irq(PIC_CASCADE_IR, &irq2); | 336 | setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2); |
329 | } | 337 | } |
diff --git a/arch/mips/pci/fixup-vr4133.c b/arch/mips/pci/fixup-vr4133.c index 597b89764ba1..b1a5b318f26f 100644 --- a/arch/mips/pci/fixup-vr4133.c +++ b/arch/mips/pci/fixup-vr4133.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/pci.h> | 19 | #include <linux/pci.h> |
20 | 20 | ||
21 | #include <asm/io.h> | 21 | #include <asm/io.h> |
22 | #include <asm/i8259.h> | ||
22 | #include <asm/vr41xx/cmbvr4133.h> | 23 | #include <asm/vr41xx/cmbvr4133.h> |
23 | 24 | ||
24 | extern int vr4133_rockhopper; | 25 | extern int vr4133_rockhopper; |
@@ -160,17 +161,7 @@ int rockhopper_get_irq(struct pci_dev *dev, u8 pin, u8 slot) | |||
160 | #ifdef CONFIG_ROCKHOPPER | 161 | #ifdef CONFIG_ROCKHOPPER |
161 | void i8259_init(void) | 162 | void i8259_init(void) |
162 | { | 163 | { |
163 | outb(0x11, 0x20); /* Master ICW1 */ | 164 | init_i8259_irqs(); |
164 | outb(I8259_IRQ_BASE, 0x21); /* Master ICW2 */ | ||
165 | outb(0x04, 0x21); /* Master ICW3 */ | ||
166 | outb(0x01, 0x21); /* Master ICW4 */ | ||
167 | outb(0xff, 0x21); /* Master IMW */ | ||
168 | |||
169 | outb(0x11, 0xa0); /* Slave ICW1 */ | ||
170 | outb(I8259_IRQ_BASE + 8, 0xa1); /* Slave ICW2 */ | ||
171 | outb(0x02, 0xa1); /* Slave ICW3 */ | ||
172 | outb(0x01, 0xa1); /* Slave ICW4 */ | ||
173 | outb(0xff, 0xa1); /* Slave IMW */ | ||
174 | 165 | ||
175 | outb(0x00, 0x4d0); | 166 | outb(0x00, 0x4d0); |
176 | outb(0x02, 0x4d1); /* USB IRQ9 is level */ | 167 | outb(0x02, 0x4d1); /* USB IRQ9 is level */ |
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c index 128ed8d6f111..7d2d076b0f54 100644 --- a/arch/mips/vr41xx/nec-cmbvr4133/irq.c +++ b/arch/mips/vr41xx/nec-cmbvr4133/irq.c | |||
@@ -21,60 +21,16 @@ | |||
21 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
22 | 22 | ||
23 | #include <asm/io.h> | 23 | #include <asm/io.h> |
24 | #include <asm/i8259.h> | ||
24 | #include <asm/vr41xx/cmbvr4133.h> | 25 | #include <asm/vr41xx/cmbvr4133.h> |
25 | 26 | ||
26 | extern void enable_8259A_irq(unsigned int irq); | ||
27 | extern void disable_8259A_irq(unsigned int irq); | ||
28 | extern void mask_and_ack_8259A(unsigned int irq); | ||
29 | extern void init_8259A(int hoge); | ||
30 | |||
31 | extern int vr4133_rockhopper; | 27 | extern int vr4133_rockhopper; |
32 | 28 | ||
33 | static void enable_i8259_irq(unsigned int irq) | ||
34 | { | ||
35 | enable_8259A_irq(irq - I8259_IRQ_BASE); | ||
36 | } | ||
37 | |||
38 | static void disable_i8259_irq(unsigned int irq) | ||
39 | { | ||
40 | disable_8259A_irq(irq - I8259_IRQ_BASE); | ||
41 | } | ||
42 | |||
43 | static void ack_i8259_irq(unsigned int irq) | ||
44 | { | ||
45 | mask_and_ack_8259A(irq - I8259_IRQ_BASE); | ||
46 | } | ||
47 | |||
48 | static struct irq_chip i8259_irq_type = { | ||
49 | .typename = "XT-PIC", | ||
50 | .ack = ack_i8259_irq, | ||
51 | .mask = disable_i8259_irq, | ||
52 | .mask_ack = ack_i8259_irq, | ||
53 | .unmask = enable_i8259_irq, | ||
54 | }; | ||
55 | |||
56 | static int i8259_get_irq_number(int irq) | 29 | static int i8259_get_irq_number(int irq) |
57 | { | 30 | { |
58 | unsigned long isr; | 31 | return i8259_irq(); |
59 | |||
60 | isr = inb(0x20); | ||
61 | irq = ffz(~isr); | ||
62 | if (irq == 2) { | ||
63 | isr = inb(0xa0); | ||
64 | irq = 8 + ffz(~isr); | ||
65 | } | ||
66 | |||
67 | if (irq < 0 || irq > 15) | ||
68 | return -EINVAL; | ||
69 | |||
70 | return I8259_IRQ_BASE + irq; | ||
71 | } | 32 | } |
72 | 33 | ||
73 | static struct irqaction i8259_slave_cascade = { | ||
74 | .handler = &no_action, | ||
75 | .name = "cascade", | ||
76 | }; | ||
77 | |||
78 | void __init rockhopper_init_irq(void) | 34 | void __init rockhopper_init_irq(void) |
79 | { | 35 | { |
80 | int i; | 36 | int i; |
@@ -84,11 +40,6 @@ void __init rockhopper_init_irq(void) | |||
84 | return; | 40 | return; |
85 | } | 41 | } |
86 | 42 | ||
87 | for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++) | ||
88 | set_irq_chip_and_handler(i, &i8259_irq_type, handle_level_irq); | ||
89 | |||
90 | setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade); | ||
91 | |||
92 | vr41xx_set_irq_trigger(CMBVR41XX_INTC_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH); | 43 | vr41xx_set_irq_trigger(CMBVR41XX_INTC_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH); |
93 | vr41xx_set_irq_level(CMBVR41XX_INTC_PIN, LEVEL_HIGH); | 44 | vr41xx_set_irq_level(CMBVR41XX_INTC_PIN, LEVEL_HIGH); |
94 | vr41xx_cascade_irq(CMBVR41XX_INTC_IRQ, i8259_get_irq_number); | 45 | vr41xx_cascade_irq(CMBVR41XX_INTC_IRQ, i8259_get_irq_number); |
diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h index 27655dbd23f3..6cf177caf6d5 100644 --- a/include/asm-mips/ddb5xxx/ddb5477.h +++ b/include/asm-mips/ddb5xxx/ddb5477.h | |||
@@ -252,12 +252,8 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); | |||
252 | */ | 252 | */ |
253 | 253 | ||
254 | #define NUM_CPU_IRQ 8 | 254 | #define NUM_CPU_IRQ 8 |
255 | #define NUM_I8259_IRQ 16 | ||
256 | #define NUM_VRC5477_IRQ 32 | 255 | #define NUM_VRC5477_IRQ 32 |
257 | 256 | ||
258 | #define DDB_IRQ_BASE 0 | ||
259 | |||
260 | #define I8259_IRQ_BASE DDB_IRQ_BASE | ||
261 | #define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE | 257 | #define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE |
262 | #define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) | 258 | #define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) |
263 | 259 | ||
@@ -301,22 +297,22 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); | |||
301 | /* | 297 | /* |
302 | * i2859 irq assignment | 298 | * i2859 irq assignment |
303 | */ | 299 | */ |
304 | #define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE) | 300 | #define I8259_IRQ_RESERVED_0 (0 + I8259A_IRQ_BASE) |
305 | #define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */ | 301 | #define I8259_IRQ_KEYBOARD (1 + I8259A_IRQ_BASE) /* M1543 default */ |
306 | #define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE) | 302 | #define I8259_IRQ_CASCADE (2 + I8259A_IRQ_BASE) |
307 | #define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ | 303 | #define I8259_IRQ_UART_B (3 + I8259A_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ |
308 | #define I8259_IRQ_UART_A (4 + I8259_IRQ_BASE) /* M1543 default */ | 304 | #define I8259_IRQ_UART_A (4 + I8259A_IRQ_BASE) /* M1543 default */ |
309 | #define I8259_IRQ_PARALLEL (5 + I8259_IRQ_BASE) /* M1543 default */ | 305 | #define I8259_IRQ_PARALLEL (5 + I8259A_IRQ_BASE) /* M1543 default */ |
310 | #define I8259_IRQ_RESERVED_6 (6 + I8259_IRQ_BASE) | 306 | #define I8259_IRQ_RESERVED_6 (6 + I8259A_IRQ_BASE) |
311 | #define I8259_IRQ_RESERVED_7 (7 + I8259_IRQ_BASE) | 307 | #define I8259_IRQ_RESERVED_7 (7 + I8259A_IRQ_BASE) |
312 | #define I8259_IRQ_RTC (8 + I8259_IRQ_BASE) /* who set this? */ | 308 | #define I8259_IRQ_RTC (8 + I8259A_IRQ_BASE) /* who set this? */ |
313 | #define I8259_IRQ_USB (9 + I8259_IRQ_BASE) /* ddb_setup */ | 309 | #define I8259_IRQ_USB (9 + I8259A_IRQ_BASE) /* ddb_setup */ |
314 | #define I8259_IRQ_PMU (10 + I8259_IRQ_BASE) /* ddb_setup */ | 310 | #define I8259_IRQ_PMU (10 + I8259A_IRQ_BASE) /* ddb_setup */ |
315 | #define I8259_IRQ_RESERVED_11 (11 + I8259_IRQ_BASE) | 311 | #define I8259_IRQ_RESERVED_11 (11 + I8259A_IRQ_BASE) |
316 | #define I8259_IRQ_RESERVED_12 (12 + I8259_IRQ_BASE) /* m1543_irq_setup */ | 312 | #define I8259_IRQ_RESERVED_12 (12 + I8259A_IRQ_BASE) /* m1543_irq_setup */ |
317 | #define I8259_IRQ_RESERVED_13 (13 + I8259_IRQ_BASE) | 313 | #define I8259_IRQ_RESERVED_13 (13 + I8259A_IRQ_BASE) |
318 | #define I8259_IRQ_HDC1 (14 + I8259_IRQ_BASE) /* default and ddb_setup */ | 314 | #define I8259_IRQ_HDC1 (14 + I8259A_IRQ_BASE) /* default and ddb_setup */ |
319 | #define I8259_IRQ_HDC2 (15 + I8259_IRQ_BASE) /* default */ | 315 | #define I8259_IRQ_HDC2 (15 + I8259A_IRQ_BASE) /* default */ |
320 | 316 | ||
321 | 317 | ||
322 | /* | 318 | /* |
diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h index 4df8d8b118c0..e88a01607fea 100644 --- a/include/asm-mips/i8259.h +++ b/include/asm-mips/i8259.h | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/spinlock.h> | 18 | #include <linux/spinlock.h> |
19 | 19 | ||
20 | #include <asm/io.h> | 20 | #include <asm/io.h> |
21 | #include <irq.h> | ||
21 | 22 | ||
22 | /* i8259A PIC registers */ | 23 | /* i8259A PIC registers */ |
23 | #define PIC_MASTER_CMD 0x20 | 24 | #define PIC_MASTER_CMD 0x20 |
@@ -42,8 +43,6 @@ extern void disable_8259A_irq(unsigned int irq); | |||
42 | 43 | ||
43 | extern void init_i8259_irqs(void); | 44 | extern void init_i8259_irqs(void); |
44 | 45 | ||
45 | #define I8259A_IRQ_BASE 0 | ||
46 | |||
47 | /* | 46 | /* |
48 | * Do the traditional i8259 interrupt polling thing. This is for the few | 47 | * Do the traditional i8259 interrupt polling thing. This is for the few |
49 | * cases where no better interrupt acknowledge method is available and we | 48 | * cases where no better interrupt acknowledge method is available and we |
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 386da82e5774..91803ba30ff2 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h | |||
@@ -18,7 +18,7 @@ | |||
18 | #ifdef CONFIG_I8259 | 18 | #ifdef CONFIG_I8259 |
19 | static inline int irq_canonicalize(int irq) | 19 | static inline int irq_canonicalize(int irq) |
20 | { | 20 | { |
21 | return ((irq == 2) ? 9 : irq); | 21 | return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq); |
22 | } | 22 | } |
23 | #else | 23 | #else |
24 | #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ | 24 | #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ |
diff --git a/include/asm-mips/mach-generic/irq.h b/include/asm-mips/mach-generic/irq.h index 91e6778907fe..70d9a25132c5 100644 --- a/include/asm-mips/mach-generic/irq.h +++ b/include/asm-mips/mach-generic/irq.h | |||
@@ -12,6 +12,12 @@ | |||
12 | #define NR_IRQS 128 | 12 | #define NR_IRQS 128 |
13 | #endif | 13 | #endif |
14 | 14 | ||
15 | #ifdef CONFIG_I8259 | ||
16 | #ifndef I8259A_IRQ_BASE | ||
17 | #define I8259A_IRQ_BASE 0 | ||
18 | #endif | ||
19 | #endif | ||
20 | |||
15 | #ifdef CONFIG_IRQ_CPU | 21 | #ifdef CONFIG_IRQ_CPU |
16 | 22 | ||
17 | #ifndef MIPS_CPU_IRQ_BASE | 23 | #ifndef MIPS_CPU_IRQ_BASE |
diff --git a/include/asm-mips/mach-vr41xx/irq.h b/include/asm-mips/mach-vr41xx/irq.h index 862058d3f81b..848812296052 100644 --- a/include/asm-mips/mach-vr41xx/irq.h +++ b/include/asm-mips/mach-vr41xx/irq.h | |||
@@ -2,6 +2,9 @@ | |||
2 | #define __ASM_MACH_VR41XX_IRQ_H | 2 | #define __ASM_MACH_VR41XX_IRQ_H |
3 | 3 | ||
4 | #include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */ | 4 | #include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */ |
5 | #ifdef CONFIG_NEC_CMBVR4133 | ||
6 | #include <asm/vr41xx/cmbvr4133.h> /* for I8259A_IRQ_BASE */ | ||
7 | #endif | ||
5 | 8 | ||
6 | #include_next <irq.h> | 9 | #include_next <irq.h> |
7 | 10 | ||
diff --git a/include/asm-mips/vr41xx/cmbvr4133.h b/include/asm-mips/vr41xx/cmbvr4133.h index 9490ade58b46..42300037d593 100644 --- a/include/asm-mips/vr41xx/cmbvr4133.h +++ b/include/asm-mips/vr41xx/cmbvr4133.h | |||
@@ -35,8 +35,8 @@ | |||
35 | #define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN) | 35 | #define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN) |
36 | #define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN) | 36 | #define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN) |
37 | 37 | ||
38 | #define I8259_IRQ_BASE 72 | 38 | #define I8259A_IRQ_BASE 72 |
39 | #define I8259_IRQ(x) (I8259_IRQ_BASE + (x)) | 39 | #define I8259_IRQ(x) (I8259A_IRQ_BASE + (x)) |
40 | #define TIMER_IRQ I8259_IRQ(0) | 40 | #define TIMER_IRQ I8259_IRQ(0) |
41 | #define KEYBOARD_IRQ I8259_IRQ(1) | 41 | #define KEYBOARD_IRQ I8259_IRQ(1) |
42 | #define I8259_SLAVE_IRQ I8259_IRQ(2) | 42 | #define I8259_SLAVE_IRQ I8259_IRQ(2) |
@@ -52,6 +52,5 @@ | |||
52 | #define AUX_IRQ I8259_IRQ(12) | 52 | #define AUX_IRQ I8259_IRQ(12) |
53 | #define IDE_PRIMARY_IRQ I8259_IRQ(14) | 53 | #define IDE_PRIMARY_IRQ I8259_IRQ(14) |
54 | #define IDE_SECONDARY_IRQ I8259_IRQ(15) | 54 | #define IDE_SECONDARY_IRQ I8259_IRQ(15) |
55 | #define I8259_IRQ_LAST IDE_SECONDARY_IRQ | ||
56 | 55 | ||
57 | #endif /* __NEC_CMBVR4133_H */ | 56 | #endif /* __NEC_CMBVR4133_H */ |