123 files changed, 1150 insertions, 3647 deletions
diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt
index 611acc32fdf5..bf56b20652b0 100644
--- a/Documentation/feature-removal-schedule.txt
+++ b/Documentation/feature-removal-schedule.txt
@@ -217,14 +217,6 @@ Who:	Nick Piggin <npiggin@suse.de>
 ---------------------------
-What:   Support for the MIPS EV96100 evaluation board
-When:   September 2006
-Why:    Does no longer build since at least November 15, 2003, apparently
-        no userbase left.
-Who:    Ralf Baechle <ralf@linux-mips.org>
---------------------------
 What:   Support for the Momentum / PMC-Sierra Jaguar ATX evaluation board
 When:   September 2006
 Why:    Does no longer build since quite some time, and was never popular,
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index c918cc3f65fb..255ec535bba8 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -573,8 +573,6 @@ running once the system is up.
        gscd=           [HW,CD]
                        Format: <io>
-        gt96100eth=     [NET] MIPS GT96100 Advanced Communication Controller
        gus=            [HW,OSS]
                        Format: <io>,<irq>,<dma>,<dma16>
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 330f6abc7703..30750c54bdf5 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -126,7 +126,7 @@ config BASLER_EXCITE
        select IRQ_CPU
        select IRQ_CPU_RM7K
        select IRQ_CPU_RM9K
-        select SERIAL_RM9000
+        select MIPS_RM9122
        select SYS_HAS_CPU_RM9000
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_64BIT_KERNEL
@@ -203,26 +203,6 @@ config MIPS_EV64120
          <http://www.marvell.com/>.  Say Y here if you wish to build a
          kernel for this platform.
-config MIPS_EV96100
-        bool "Galileo EV96100 Evaluation board (EXPERIMENTAL)"
-        depends on EXPERIMENTAL
-        select DMA_NONCOHERENT
-        select HW_HAS_PCI
-        select IRQ_CPU
-        select MIPS_GT96100
-        select RM7000_CPU_SCACHE
-        select SWAP_IO_SPACE
-        select SYS_HAS_CPU_R5000
-        select SYS_HAS_CPU_RM7000
-        select SYS_SUPPORTS_32BIT_KERNEL
-        select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
-        select SYS_SUPPORTS_BIG_ENDIAN
-        help
-          This is an evaluation board based on the Galileo GT-96100 LAN/WAN
-          communications controllers containing a MIPS R5000 compatible core
-          running at 83MHz. Their website is <http://www.marvell.com/>. Say Y
-          here if you wish to build a kernel for this platform.
 config MIPS_IVR
        bool "Globespan IVR board"
        select DMA_NONCOHERENT
@@ -974,6 +954,12 @@ config MIPS_TX3927
        bool
        select HAS_TXX9_SERIAL
+config MIPS_RM9122
+        bool
+        select SERIAL_RM9000
+        select GPI_RM9000
+        select WDT_RM9000
 config PCI_MARVELL
        bool
@@ -1024,6 +1010,15 @@ config EMMA2RH
        depends on MARKEINS
        default y
+config SERIAL_RM9000
+        bool
+config GPI_RM9000
+        bool
+config WDT_RM9000
+        bool
 #
 # Unfortunately not all GT64120 systems run the chip at the same clock.
 # As the user for the clock rate and try to minimize the available options.
@@ -1054,10 +1049,6 @@ config AU1X00_USB_DEVICE
        depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000
        default n
-config MIPS_GT96100
-        bool
-        select MIPS_GT64120
 config IT8172_CIR
        bool
        depends on MIPS_ITE8172 || MIPS_IVR
@@ -1527,6 +1518,7 @@ config MIPS_MT_SMTC
        select CPU_MIPSR2_SRS
        select MIPS_MT
        select SMP
+        select SYS_SUPPORTS_SMP
        help
          This is a kernel model which is known a SMTC or lately has been
          marketesed into SMVP.
@@ -1538,6 +1530,7 @@ config MIPS_MT_SMP
        select CPU_MIPSR2_SRS
        select MIPS_MT
        select SMP
+        select SYS_SUPPORTS_SMP
        help
          This is a kernel model which is also known a VSMP or lately
          has been marketesed into SMVP.
@@ -1649,9 +1642,7 @@ config GENERIC_IRQ_PROBE
        default y
 config IRQ_PER_CPU
-        depends on SMP
        bool
-        default y
 #
 # - Highmem only makes sense for the 32-bit kernel.
@@ -1719,6 +1710,7 @@ source "mm/Kconfig"
 config SMP
        bool "Multi-Processing support"
        depends on SYS_SUPPORTS_SMP
+        select IRQ_PER_CPU
        help
          This enables support for systems with more than one CPU. If you have
          a system with only one CPU, like most personal computers, say N. If
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index d333ce4ba26b..e521826b4234 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -280,13 +280,6 @@ cflags-$(CONFIG_MIPS_EV64120)	+= -Iinclude/asm-mips/mach-ev64120
 load-$(CONFIG_MIPS_EV64120)     += 0xffffffff80100000
 #
-# Galileo EV96100 Board
-#
-core-$(CONFIG_MIPS_EV96100)     += arch/mips/galileo-boards/ev96100/
-cflags-$(CONFIG_MIPS_EV96100)   += -Iinclude/asm-mips/mach-ev96100
-load-$(CONFIG_MIPS_EV96100)     += 0xffffffff80100000
-#
 # Wind River PPMC Board (4KC + GT64120)
 #
 core-$(CONFIG_WR_PPMC)          += arch/mips/gt64120/wrppmc/
@@ -330,6 +323,7 @@ load-$(CONFIG_MIPS_MALTA)	+= 0xffffffff80100000
 # MIPS SEAD board
 #
 core-$(CONFIG_MIPS_SEAD)        += arch/mips/mips-boards/sead/
+cflags-$(CONFIG_MIPS_SEAD)      += -Iinclude/asm-mips/mach-mips
 load-$(CONFIG_MIPS_SEAD)        += 0xffffffff80100000
 #
diff --git a/arch/mips/au1000/db1x00/Makefile b/arch/mips/au1000/db1x00/Makefile
index 4c7d763f2113..51d62bd5d900 100644
--- a/arch/mips/au1000/db1x00/Makefile
+++ b/arch/mips/au1000/db1x00/Makefile
@@ -6,4 +6,3 @@
 # Makefile for the Alchemy Semiconductor Db1x00 board.
 lib-y := init.o board_setup.o irqmap.o
-obj-$(CONFIG_WM97XX_COMODULE) += mirage_ts.o
diff --git a/arch/mips/au1000/db1x00/mirage_ts.c b/arch/mips/au1000/db1x00/mirage_ts.c
deleted file mode 100644
index 0942dcf69518..000000000000
--- a/arch/mips/au1000/db1x00/mirage_ts.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * linux/arch/mips/au1000/db1x00/mirage_ts.c
- *
- * BRIEF MODULE DESCRIPTION
- *      Glue between Mirage board-specific touchscreen pieces
- *      and generic Wolfson Codec touchscreen support.
- *
- *      Based on pb1100_ts.c used in Hydrogen II.
- *
- * Copyright (c) 2003 Embedded Edge, LLC
- *              dan@embeddededge.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/fs.h>
-#include <linux/poll.h>
-#include <linux/proc_fs.h>
-#include <linux/smp.h>
-#include <linux/smp_lock.h>
-#include <linux/wait.h>
-#include <asm/segment.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <asm/delay.h>
-#include <asm/au1000.h>
-/*
- *  Imported interface to Wolfson Codec driver.
- */
-extern void *wm97xx_ts_get_handle(int which);
-extern int wm97xx_ts_ready(void* ts_handle);
-extern void wm97xx_ts_set_cal(void* ts_handle, int xscale, int xtrans, int yscale, int ytrans);
-extern u16 wm97xx_ts_get_ac97(void* ts_handle, u8 reg);
-extern void wm97xx_ts_set_ac97(void* ts_handle, u8 reg, u16 val);
-extern int wm97xx_ts_read_data(void* ts_handle, long* x, long* y, long* pressure);
-extern void wm97xx_ts_send_data(void* ts_handle, long x, long y, long z);
-int wm97xx_comodule_present = 1;
-#define TS_NAME "mirage_ts"
-#define err(format, arg...) printk(KERN_ERR TS_NAME ": " format "\n" , ## arg)
-#define info(format, arg...) printk(KERN_INFO TS_NAME ": " format "\n" , ## arg)
-#define warn(format, arg...) printk(KERN_WARNING TS_NAME ": " format "\n" , ## arg)
-#define DPRINTK(format, arg...) printk("%s: " format "\n", __FUNCTION__ , ## arg)
-#define PEN_DOWN_IRQ    AU1000_GPIO_7
-static struct task_struct *ts_task = 0;
-static DECLARE_COMPLETION(ts_complete);
-static DECLARE_WAIT_QUEUE_HEAD(pendown_wait);
-#ifdef CONFIG_WM97XX_FIVEWIRETS
-static int release_pressure = 1;
-#else
-static int release_pressure = 50;
-#endif
-typedef struct {
-   long x;
-   long y;
-} DOWN_EVENT;
-#define SAMPLE_RATE     50      /* samples per second */
-#define PEN_DEBOUNCE    5       /* samples for settling - fn of SAMPLE_RATE */
-#define PEN_UP_TIMEOUT  10      /* in seconds */
-#define PEN_UP_SETTLE   5       /* samples per second */
-static struct {
-        int xscale;
-        int xtrans;
-        int yscale;
-        int ytrans;
-} mirage_ts_cal =
-{
-#if 0
-        .xscale   = 84,
-        .xtrans = -157,
-        .yscale   = 66,
-        .ytrans = -150,
-#else
-        .xscale   = 84,
-        .xtrans = -150,
-        .yscale   = 66,
-        .ytrans = -146,
-#endif
-};
-static void pendown_irq(int irqnr, void *devid, struct pt_regs *regs)
-{
-//DPRINTK("got one 0x%x", au_readl(SYS_PINSTATERD));
-        wake_up(&pendown_wait);
-}
-static int ts_thread(void *id)
-{
-        static int pen_was_down = 0;
-        static DOWN_EVENT pen_xy;
-        long x, y, z;
-        void *ts;       /* handle */
-        struct task_struct *tsk = current;
-        int timeout = HZ / SAMPLE_RATE;
-        ts_task = tsk;
-        daemonize();
-        tsk->tty = NULL;
-        tsk->policy = SCHED_FIFO;
-        tsk->rt_priority = 1;
-        strcpy(tsk->comm, "touchscreen");
-        /* only want to receive SIGKILL */
-        spin_lock_irq(&tsk->sigmask_lock);
-        siginitsetinv(&tsk->blocked, sigmask(SIGKILL));
-        recalc_sigpending(tsk);
-        spin_unlock_irq(&tsk->sigmask_lock);
-        /* get handle for codec */
-        ts = wm97xx_ts_get_handle(0);
-        /* proceed only after everybody is ready */
-        wait_event_timeout(pendown_wait, wm97xx_ts_ready(ts), HZ/4);
-        /* board-specific calibration */
-        wm97xx_ts_set_cal(ts,
-                        mirage_ts_cal.xscale,
-                        mirage_ts_cal.xtrans,
-                        mirage_ts_cal.yscale,
-                        mirage_ts_cal.ytrans);
-        /* route Wolfson pendown interrupts to our GPIO */
-        au_sync();
-        wm97xx_ts_set_ac97(ts, 0x4c, wm97xx_ts_get_ac97(ts, 0x4c) & ~0x0008);
-        au_sync();
-        wm97xx_ts_set_ac97(ts, 0x56, wm97xx_ts_get_ac97(ts, 0x56) & ~0x0008);
-        au_sync();
-        wm97xx_ts_set_ac97(ts, 0x52, wm97xx_ts_get_ac97(ts, 0x52) | 0x2008);
-        au_sync();
-        for (;;) {
-                interruptible_sleep_on_timeout(&pendown_wait, timeout);
-                disable_irq(PEN_DOWN_IRQ);
-                if (signal_pending(tsk)) {
-                        break;
-                }
-                /* read codec */
-                if (!wm97xx_ts_read_data(ts, &x, &y, &z))
-                        z = 0;  /* treat no-data and pen-up the same */
-                if (signal_pending(tsk)) {
-                        break;
-                }
-                if (z >= release_pressure) {
-                        y = ~y; /* top to bottom */
-                        if (pen_was_down > 1 /*&& pen_was_down < PEN_DEBOUNCE*/) {//THXXX
-                                /* bounce ? */
-                                x = pen_xy.x;
-                                y = pen_xy.y;
-                                --pen_was_down;
-                        } else if (pen_was_down <= 1) {
-                                pen_xy.x = x;
-                                pen_xy.y = y;
-                                if (pen_was_down)
-                                        wm97xx_ts_send_data(ts, x, y, z);
-                                pen_was_down = PEN_DEBOUNCE;
-                        }
-                        //wm97xx_ts_send_data(ts, x, y, z);
-                        timeout = HZ / SAMPLE_RATE;
-                } else {
-                        if (pen_was_down) {
-                                if (--pen_was_down)
-                                        z = release_pressure;
-                                else //THXXX
-                                wm97xx_ts_send_data(ts, pen_xy.x, pen_xy.y, z);
-                        }
-                        /* The pendown signal takes some time to settle after
-                         * reading the pen pressure so wait a little
-                         * before enabling the pen.
-                         */
-                        if (! pen_was_down) {
-//                              interruptible_sleep_on_timeout(&pendown_wait, HZ / PEN_UP_SETTLE);
-                                timeout = HZ * PEN_UP_TIMEOUT;
-                        }
-                }
-                enable_irq(PEN_DOWN_IRQ);
-        }
-        enable_irq(PEN_DOWN_IRQ);
-        ts_task = NULL;
-        complete(&ts_complete);
-        return 0;
-}
-static int __init ts_mirage_init(void)
-{
-        int ret;
-        /* pen down signal is connected to GPIO 7 */
-        ret = request_irq(PEN_DOWN_IRQ, pendown_irq, 0, "ts-pendown", NULL);
-        if (ret) {
-                err("unable to get pendown irq%d: [%d]", PEN_DOWN_IRQ, ret);
-                return ret;
-        }
-        lock_kernel();
-        ret = kernel_thread(ts_thread, NULL, CLONE_FS | CLONE_FILES);
-        if (ret < 0) {
-                unlock_kernel();
-                return ret;
-        }
-        unlock_kernel();
-        info("Mirage touchscreen IRQ initialized.");
-        return 0;
-}
-static void __exit ts_mirage_exit(void)
-{
-        if (ts_task) {
-                send_sig(SIGKILL, ts_task, 1);
-                wait_for_completion(&ts_complete);
-        }
-        free_irq(PEN_DOWN_IRQ, NULL);
-}
-module_init(ts_mirage_init);
-module_exit(ts_mirage_exit);
diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c
index bbb4ea43da88..cc1ce77eab4a 100644
--- a/arch/mips/basler/excite/excite_device.c
+++ b/arch/mips/basler/excite/excite_device.c
@@ -68,7 +68,7 @@ enum {
 static struct resource
-        excite_ctr_resource = {
+        excite_ctr_resource __attribute__((unused)) = {
                .name           = "GPI counters",
                .start          = 0,
                .end            = 5,
@@ -77,7 +77,7 @@ static struct resource
                .sibling        = NULL,
                .child          = NULL
        },
-        excite_gpislice_resource = {
+        excite_gpislice_resource __attribute__((unused)) = {
                .name           = "GPI slices",
                .start          = 0,
                .end            = 1,
@@ -86,7 +86,7 @@ static struct resource
                .sibling        = NULL,
                .child          = NULL
        },
-        excite_mdio_channel_resource = {
+        excite_mdio_channel_resource __attribute__((unused)) = {
                .name           = "MDIO channels",
                .start          = 0,
                .end            = 1,
@@ -95,7 +95,7 @@ static struct resource
                .sibling        = NULL,
                .child          = NULL
        },
-        excite_fifomem_resource = {
+        excite_fifomem_resource __attribute__((unused)) = {
                .name           = "FIFO memory",
                .start          = 0,
                .end            = 767,
@@ -104,7 +104,7 @@ static struct resource
                .sibling        = NULL,
                .child          = NULL
        },
-        excite_scram_resource = {
+        excite_scram_resource __attribute__((unused)) = {
                .name           = "Scratch RAM",
                .start          = EXCITE_PHYS_SCRAM,
                .end            = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
@@ -113,7 +113,7 @@ static struct resource
                .sibling        = NULL,
                .child          = NULL
        },
-        excite_fpga_resource = {
+        excite_fpga_resource __attribute__((unused)) = {
                .name           = "System FPGA",
                .start          = EXCITE_PHYS_FPGA,
                .end            = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
@@ -122,7 +122,7 @@ static struct resource
                .sibling        = NULL,
                .child          = NULL
        },
-        excite_nand_resource = {
+        excite_nand_resource __attribute__((unused)) = {
                .name           = "NAND flash control",
                .start          = EXCITE_PHYS_NAND,
                .end            = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
@@ -131,7 +131,7 @@ static struct resource
                .sibling        = NULL,
                .child          = NULL
        },
-        excite_titan_resource = {
+        excite_titan_resource __attribute__((unused)) = {
                .name           = "TITAN registers",
                .start          = EXCITE_PHYS_TITAN,
                .end            = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig
index 54274065e9a5..d3705284de39 100644
--- a/arch/mips/configs/atlas_defconfig
+++ b/arch/mips/configs/atlas_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1193,7 +1192,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 887fd959482a..e12a475dcbf4 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index a01344f3a4c2..bfade9abb767 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index c95682445a28..4baf2ff1128a 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 CONFIG_MIPS_COBALT=y
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -828,7 +827,7 @@ CONFIG_FUSE_FS=y
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index c2f33d3af62c..93cca1585bc3 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS_DB1000=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index 8c44d16ae9a2..ffd99252a837 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS_DB1100=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index c13768e75ac5..63eac5e89b9c 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS_DB1200=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 8aea73fae7fb..25a095f7dc4e 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS_DB1500=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 90ccb7359630..dda469c842b3 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS_DB1550=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig
index b598cf08f156..fcd3dd19bc74 100644
--- a/arch/mips/configs/ddb5477_defconfig
+++ b/arch/mips/configs/ddb5477_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 597150b14077..8683e0df12e0 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 CONFIG_MACH_DECSTATION=y
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index fa2996bb4b7c..4ace61c95778 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.18-rc1
+# Linux kernel version: 2.6.18-rc2
-# Thu Jul  6 10:04:02 2006
+# Tue Jul 25 23:15:03 2006
 #
 CONFIG_MIPS=y
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -227,7 +226,6 @@ CONFIG_MMU=y
 #
 # PCCARD (PCMCIA/CardBus) support
 #
-# CONFIG_PCCARD is not set
 #
 # PCI Hotplug Support
@@ -254,7 +252,6 @@ CONFIG_TRAD_SIGNALS=y
 #
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
 # CONFIG_SYS_HYPERVISOR is not set
 #
@@ -284,6 +281,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_BLK_DEV_RAM=m
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CDROM_PKTCDVD is not set
@@ -643,6 +641,7 @@ CONFIG_MSDOS_PARTITION=y
 #
 # Kernel hacking
 #
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
@@ -650,7 +649,7 @@ CONFIG_MSDOS_PARTITION=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DEBUG_FS is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE="console=ttyVR0,19200 mem=8M"
+CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x1f0,0x3f6,40 mem=8M"
 #
 # Security options
diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig
index 375b2ac24a49..5847c916c130 100644
--- a/arch/mips/configs/emma2rh_defconfig
+++ b/arch/mips/configs/emma2rh_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig
index b0afc118bd5c..bc4c4f125c48 100644
--- a/arch/mips/configs/ev64120_defconfig
+++ b/arch/mips/configs/ev64120_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 CONFIG_MIPS_EV64120=y
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/ev96100_defconfig b/arch/mips/configs/ev96100_defconfig
deleted file mode 100644
index 0bdc10f11610..000000000000
--- a/arch/mips/configs/ev96100_defconfig
+++ /dev/null
@@ -1,850 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.18-rc1
-# Thu Jul  6 10:04:05 2006
-#
-CONFIG_MIPS=y
-#
-# Machine selection
-#
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
-# CONFIG_BASLER_EXCITE is not set
-# CONFIG_MIPS_COBALT is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MIPS_EV64120 is not set
-CONFIG_MIPS_EV96100=y
-# CONFIG_MIPS_IVR is not set
-# CONFIG_MIPS_ITE8172 is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_LASAT is not set
-# CONFIG_MIPS_ATLAS is not set
-# CONFIG_MIPS_MALTA is not set
-# CONFIG_MIPS_SEAD is not set
-# CONFIG_WR_PPMC is not set
-# CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MOMENCO_OCELOT is not set
-# CONFIG_MOMENCO_OCELOT_3 is not set
-# CONFIG_MOMENCO_OCELOT_C is not set
-# CONFIG_MOMENCO_OCELOT_G is not set
-# CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_DDB5477 is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_QEMU is not set
-# CONFIG_MARKEINS is not set
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_PTSWARM is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SNI_RM200_PCI is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_CPU_BIG_ENDIAN=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_IRQ_CPU=y
-CONFIG_MIPS_GT64120=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_MIPS_GT96100=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-#
-# CPU selection
-#
-# CONFIG_CPU_MIPS32_R1 is not set
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_VR41XX is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_R10000 is not set
-CONFIG_CPU_RM7000=y
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_SYS_HAS_CPU_R5000=y
-CONFIG_SYS_HAS_CPU_RM7000=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-#
-# Kernel type
-#
-CONFIG_32BIT=y
-# CONFIG_64BIT is not set
-CONFIG_PAGE_SIZE_4KB=y
-# CONFIG_PAGE_SIZE_8KB is not set
-# CONFIG_PAGE_SIZE_16KB is not set
-# CONFIG_PAGE_SIZE_64KB is not set
-CONFIG_BOARD_SCACHE=y
-CONFIG_RM7000_CPU_SCACHE=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_VPE_LOADER is not set
-# CONFIG_64BIT_PHYS_ADDR is not set
-CONFIG_CPU_HAS_LLSC=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
-# CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
-# CONFIG_HZ_128 is not set
-# CONFIG_HZ_250 is not set
-# CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
-# CONFIG_HZ_1024 is not set
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_RELAY=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EMBEDDED=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-# CONFIG_HOTPLUG is not set
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_RT_MUTEXES=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_KMOD is not set
-#
-# Block layer
-#
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-#
-# Bus options (PCI, PCMCIA, EISA, ISA, TC)
-#
-CONFIG_HW_HAS_PCI=y
-# CONFIG_PCI is not set
-CONFIG_MMU=y
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-#
-# PCI Hotplug Support
-#
-#
-# Executable file formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
-CONFIG_TRAD_SIGNALS=y
-#
-# Networking
-#
-CONFIG_NET=y
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-# CONFIG_PACKET is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_BIC=y
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-# CONFIG_NETFILTER is not set
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_SOFTMAC=m
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-CONFIG_WIRELESS_EXT=y
-#
-# Device Drivers
-#
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_SYS_HYPERVISOR is not set
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=m
-#
-# Memory Technology Devices (MTD)
-#
-# CONFIG_MTD is not set
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-#
-# Plug and Play support
-#
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=m
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-#
-# SCSI device support
-#
-CONFIG_RAID_ATTRS=m
-# CONFIG_SCSI is not set
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-#
-# IEEE 1394 (FireWire) support
-#
-#
-# I2O device support
-#
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-#
-# PHY device support
-#
-CONFIG_PHYLIB=m
-#
-# MII PHY device drivers
-#
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-# CONFIG_MII is not set
-CONFIG_MIPS_GT96100ETH=y
-# CONFIG_DM9000 is not set
-#
-# Ethernet (1000 Mbit)
-#
-#
-# Ethernet (10000 Mbit)
-#
-#
-# Token Ring devices
-#
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
-#
-# Input device support
-#
-CONFIG_INPUT=y
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_LIBPS2 is not set
-CONFIG_SERIO_RAW=m
-# CONFIG_GAMEPORT is not set
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SERIAL_8250_EXTENDED is not set
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_RAW_DRIVER is not set
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-# CONFIG_TELCLOCK is not set
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-#
-# Hardware Monitoring support
-#
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
-#
-# Misc devices
-#
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-CONFIG_VIDEO_V4L2=y
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-#
-# Graphics support
-#
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-#
-# USB support
-#
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-#
-# LED drivers
-#
-#
-# LED Triggers
-#
-#
-# InfiniBand support
-#
-#
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-#
-# Real Time Clock
-#
-# CONFIG_RTC_CLASS is not set
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-#
-# DMA Clients
-#
-#
-# DMA Devices
-#
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-CONFIG_FUSE_FS=m
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
-CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_CONFIGFS_FS is not set
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-#
-# Native Language Support
-#
-# CONFIG_NLS is not set
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_DEBUG_FS is not set
-CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE=""
-#
-# Security options
-#
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-# CONFIG_SECURITY is not set
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=m
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_CRC32C=m
-# CONFIG_CRYPTO_TEST is not set
-#
-# Hardware crypto devices
-#
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-CONFIG_CRC16=m
-CONFIG_CRC32=m
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=m
-CONFIG_ZLIB_DEFLATE=m
-CONFIG_PLIST=y
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
index 045ebd089893..eb87cbbfd037 100644
--- a/arch/mips/configs/excite_defconfig
+++ b/arch/mips/configs/excite_defconfig
@@ -26,7 +26,6 @@ CONFIG_BASLER_EXCITE=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index ef16d1fb5071..cc9b24eda9e8 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1013,7 +1012,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 4bf1ee7f5f00..50092ba8aa71 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -900,7 +899,7 @@ CONFIG_FUSE_FS=m
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index f83dc09c3ca9..dec2ba6ba03f 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/it8172_defconfig b/arch/mips/configs/it8172_defconfig
index a91d72a9ca86..37f9dd7187b1 100644
--- a/arch/mips/configs/it8172_defconfig
+++ b/arch/mips/configs/it8172_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 CONFIG_MIPS_ITE8172=y
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/ivr_defconfig b/arch/mips/configs/ivr_defconfig
index cebc67212d06..18874a4c24fe 100644
--- a/arch/mips/configs/ivr_defconfig
+++ b/arch/mips/configs/ivr_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 CONFIG_MIPS_IVR=y
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig
index 5d9eb11aba3d..9f1e3048d623 100644
--- a/arch/mips/configs/jaguar-atx_defconfig
+++ b/arch/mips/configs/jaguar-atx_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -731,7 +730,7 @@ CONFIG_FUSE_FS=m
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index be45a9044d06..fded3f73815f 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig
index 64dc9f45a19c..320b8cdd6e58 100644
--- a/arch/mips/configs/lasat200_defconfig
+++ b/arch/mips/configs/lasat200_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -905,7 +904,7 @@ CONFIG_FUSE_FS=m
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 2690baf15a85..0ba1ef5048fb 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1230,7 +1229,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index c298979c18ae..adbeeadddb8f 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 938b38ab5239..79fd544fcb2a 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.18-rc1
+# Linux kernel version: 2.6.18-rc2
-# Thu Jul  6 10:04:15 2006
+# Tue Jul 25 23:16:46 2006
 #
 CONFIG_MIPS=y
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -71,7 +70,6 @@ CONFIG_MACH_VR41XX=y
 CONFIG_VICTOR_MPC30X=y
 # CONFIG_ZAO_CAPCELLA is not set
 CONFIG_PCI_VR41XX=y
-CONFIG_VRC4173=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
@@ -168,6 +166,7 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
 CONFIG_SYSCTL=y
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
@@ -841,7 +840,7 @@ CONFIG_USB_PEGASUS=m
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
 # CONFIG_USB_LED is not set
-# CONFIG_USB_CY7C63 is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
 # CONFIG_USB_PHIDGETKIT is not set
 # CONFIG_USB_PHIDGETSERVO is not set
@@ -982,7 +981,6 @@ CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
-# CONFIG_CIFS_DEBUG2 is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
@@ -1007,6 +1005,7 @@ CONFIG_MSDOS_PARTITION=y
 #
 # Kernel hacking
 #
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
@@ -1014,7 +1013,7 @@ CONFIG_MSDOS_PARTITION=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DEBUG_FS is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE="mem=32M console=ttyVR0,19200"
+CONFIG_CMDLINE="mem=32M console=ttyVR0,19200 ide0=0x170,0x376,73"
 #
 # Security options
diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig
index ec5758f22676..4d87da2b99fd 100644
--- a/arch/mips/configs/ocelot_3_defconfig
+++ b/arch/mips/configs/ocelot_3_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig
index 0d33d87de1a1..a7ac2b0a8273 100644
--- a/arch/mips/configs/ocelot_c_defconfig
+++ b/arch/mips/configs/ocelot_c_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -774,7 +773,7 @@ CONFIG_FUSE_FS=y
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig
index 4b999102715e..853e7bba5122 100644
--- a/arch/mips/configs/ocelot_defconfig
+++ b/arch/mips/configs/ocelot_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -723,7 +722,7 @@ CONFIG_FUSE_FS=y
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig
index 827b344f6010..8524efa23a49 100644
--- a/arch/mips/configs/ocelot_g_defconfig
+++ b/arch/mips/configs/ocelot_g_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -777,7 +776,7 @@ CONFIG_FUSE_FS=y
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 9ed60fef69e0..1a16e92900cb 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS_PB1100=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 6774254b1be6..9ea8edea6f29 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS_PB1500=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 1afe5bf6e765..c4a158976f8f 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS_PB1550=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index ac616c82d348..1cbf270c301c 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/pnx8550-v2pci_defconfig b/arch/mips/configs/pnx8550-v2pci_defconfig
index a8eb51bae3f3..bec30b15b9bd 100644
--- a/arch/mips/configs/pnx8550-v2pci_defconfig
+++ b/arch/mips/configs/pnx8550-v2pci_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig
index 6a63a113b7ea..f5f799e93707 100644
--- a/arch/mips/configs/qemu_defconfig
+++ b/arch/mips/configs/qemu_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -687,7 +686,7 @@ CONFIG_FUSE_FS=y
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig
index 6779f449bd2d..2f5650227ba3 100644
--- a/arch/mips/configs/rbhma4500_defconfig
+++ b/arch/mips/configs/rbhma4500_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index b7826d3a2b77..4fee90b2b100 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1442,7 +1441,7 @@ CONFIG_NTFS_FS=m
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 625c1c619b6b..9041f095f96f 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig
index 4401b602118f..02abb2f1bfaf 100644
--- a/arch/mips/configs/sead_defconfig
+++ b/arch/mips/configs/sead_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index 2ba4e25e8c34..ca3d0c4ba15b 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig
index fc8a407c1add..4e2009ace278 100644
--- a/arch/mips/configs/tb0229_defconfig
+++ b/arch/mips/configs/tb0229_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index effcb63b81a3..535a813d01a9 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index 4891d02ef8ca..3a3ef20b21cc 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.18-rc1
+# Linux kernel version: 2.6.18-rc2
-# Thu Jul  6 10:04:21 2006
+# Tue Jul 25 23:13:04 2006
 #
 CONFIG_MIPS=y
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -166,6 +165,7 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
 CONFIG_SYSCTL=y
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
@@ -379,6 +379,7 @@ CONFIG_CONNECTOR=m
 CONFIG_BLK_DEV_RAM=m
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
@@ -855,7 +856,6 @@ CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
-# CONFIG_CIFS_DEBUG2 is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
@@ -880,6 +880,7 @@ CONFIG_MSDOS_PARTITION=y
 #
 # Kernel hacking
 #
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
@@ -887,7 +888,7 @@ CONFIG_MSDOS_PARTITION=y
 CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DEBUG_FS is not set
 CONFIG_CROSSCOMPILE=y
-CONFIG_CMDLINE="console=ttyVR0,19200 mem=16M"
+CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x170,0x376,49 mem=16M"
 #
 # Security options
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index 3e4b16b39827..e6b1dea55842 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 3a68d8a25b66..06a072b77b1c 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
diff --git a/arch/mips/defconfig b/arch/mips/defconfig
index fff6fcc96212..cc9b24eda9e8 100644
--- a/arch/mips/defconfig
+++ b/arch/mips/defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.18-rc1
-# Thu Jul  6 09:49:33 2006
+# Thu Jul  6 10:04:10 2006
 #
 CONFIG_MIPS=y
@@ -25,7 +25,6 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MIPS_EV64120 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_IVR is not set
 # CONFIG_MIPS_ITE8172 is not set
 # CONFIG_MACH_JAZZ is not set
@@ -1013,7 +1012,7 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 CONFIG_PROC_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
 # CONFIG_HUGETLB_PAGE is not set
 CONFIG_RAMFS=y
 # CONFIG_CONFIGFS_FS is not set
diff --git a/arch/mips/galileo-boards/ev96100/Makefile b/arch/mips/galileo-boards/ev96100/Makefile
deleted file mode 100644
index cd868ec78cbc..000000000000
--- a/arch/mips/galileo-boards/ev96100/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-#  Copyright 2000 MontaVista Software Inc.
-#  Author: MontaVista Software, Inc.
-#       ppopov@mvista.com or source@mvista.com
-#
-# Makefile for the Galileo EV96100 board.
-#
-obj-y           += init.o irq.o puts.o reset.o time.o setup.o
diff --git a/arch/mips/galileo-boards/ev96100/init.c b/arch/mips/galileo-boards/ev96100/init.c
deleted file mode 100644
index a01fe9b36f2c..000000000000
--- a/arch/mips/galileo-boards/ev96100/init.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@mvista.com or source@mvista.com
- *
- * This file was derived from Carsten Langgaard's
- * arch/mips/mips-boards/generic/generic.c
- *
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/bootmem.h>
-#include <linux/string.h>
-#include <linux/kernel.h>
-#include <asm/addrspace.h>
-#include <asm/bootinfo.h>
-#include <asm/gt64120.h>
-/* Environment variable */
-typedef struct {
-        char *name;
-        char *val;
-} t_env_var;
-int prom_argc;
-char **prom_argv, **prom_envp;
-int init_debug = 0;
-char * __init prom_getcmdline(void)
-{
-        return &(arcs_cmdline[0]);
-}
-unsigned long __init prom_free_prom_memory(void)
-{
-        return 0;
-}
-void  __init prom_init_cmdline(void)
-{
-        char *cp;
-        int actr;
-        actr = 1; /* Always ignore argv[0] */
-        cp = &(arcs_cmdline[0]);
-        while(actr < prom_argc) {
-                strcpy(cp, prom_argv[actr]);
-                cp += strlen(prom_argv[actr]);
-                *cp++ = ' ';
-                actr++;
-        }
-        if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
-                --cp;
-        *cp = '\0';
-}
-char *prom_getenv(char *envname)
-{
-        /*
-         * Return a pointer to the given environment variable.
-         */
-        t_env_var *env = (t_env_var *) prom_envp;
-        int i;
-        i = strlen(envname);
-        while (env->name) {
-                if (strncmp(envname, env->name, i) == 0) {
-                        return (env->val);
-                }
-                env++;
-        }
-        return (NULL);
-}
-static inline unsigned char str2hexnum(unsigned char c)
-{
-        if (c >= '0' && c <= '9')
-                return c - '0';
-        if (c >= 'a' && c <= 'f')
-                return c - 'a' + 10;
-        return 0;               /* foo */
-}
-static inline void str2eaddr(unsigned char *ea, unsigned char *str)
-{
-        int i;
-        for (i = 0; i < 6; i++) {
-                unsigned char num;
-                if ((*str == '.') || (*str == ':'))
-                        str++;
-                num = str2hexnum(*str++) << 4;
-                num |= (str2hexnum(*str++));
-                ea[i] = num;
-        }
-}
-int get_ethernet_addr(char *ethernet_addr)
-{
-        char *ethaddr_str;
-        ethaddr_str = prom_getenv("ethaddr");
-        if (!ethaddr_str) {
-                printk("ethaddr not set in boot prom\n");
-                return -1;
-        }
-        str2eaddr(ethernet_addr, ethaddr_str);
-        if (init_debug > 1) {
-                int i;
-                printk("get_ethernet_addr: ");
-                for (i = 0; i < 5; i++)
-                        printk("%02x:",
-                               (unsigned char) *(ethernet_addr + i));
-                printk("%02x\n", *(ethernet_addr + i));
-        }
-        return 0;
-}
-const char *get_system_type(void)
-{
-        return "Galileo EV96100";
-}
-void __init prom_init(void)
-{
-        volatile unsigned char *uart;
-        char ppbuf[8];
-        prom_argc = fw_arg0;
-        prom_argv = (char **) fw_arg1;
-        prom_envp = (char **) fw_arg2;
-        mips_machgroup = MACH_GROUP_GALILEO;
-        mips_machtype = MACH_EV96100;
-        prom_init_cmdline();
-        /* 32 MB upgradable */
-        add_memory_region(0, 32 << 20, BOOT_MEM_RAM);
-}
diff --git a/arch/mips/galileo-boards/ev96100/irq.c b/arch/mips/galileo-boards/ev96100/irq.c
deleted file mode 100644
index ee5d6720f23b..000000000000
--- a/arch/mips/galileo-boards/ev96100/irq.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@mvista.com or source@mvista.com
- *
- * This file was derived from Carsten Langgaard's
- * arch/mips/mips-boards/atlas/atlas_int.c.
- *
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/irq.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <asm/irq_cpu.h>
-static inline unsigned int ffz8(unsigned int word)
-{
-        unsigned long k;
-        k = 7;
-        if (word & 0x0fUL) { k -= 4;  word <<= 4;  }
-        if (word & 0x30UL) { k -= 2;  word <<= 2;  }
-        if (word & 0x40UL) { k -= 1; }
-        return k;
-}
-extern void mips_timer_interrupt(struct pt_regs *regs);
-asmlinkage void ev96100_cpu_irq(unsigned int pending, struct pt_regs *regs)
-{
-        do_IRQ(ffz8(pending >> 8), regs);
-}
-asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
-{
-        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
-        if (pending & CAUSEF_IP7)
-                mips_timer_interrupt(regs);
-        else if (pending)
-                ev96100_cpu_irq(pending, regs);
-        else
-                spurious_interrupt(regs);
-}
-void __init arch_init_irq(void)
-{
-        mips_cpu_irq_init(0);
-}
diff --git a/arch/mips/galileo-boards/ev96100/puts.c b/arch/mips/galileo-boards/ev96100/puts.c
deleted file mode 100644
index 49dc6d137b9c..000000000000
--- a/arch/mips/galileo-boards/ev96100/puts.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Debug routines which directly access the uart.
- */
-#include <linux/types.h>
-#include <asm/gt64120.h>
-//#define SERIAL_BASE    EV96100_UART0_REGS_BASE
-#define SERIAL_BASE    0xBD000020
-#define NS16550_BASE   SERIAL_BASE
-#define SERA_CMD       0x0D
-#define SERA_DATA      0x08
-//#define SERB_CMD       0x05
-#define SERB_CMD       20
-#define SERB_DATA      0x00
-#define TX_BUSY        0x20
-#define TIMEOUT    0xffff
-#undef SLOW_DOWN
-static const char digits[16] = "0123456789abcdef";
-static volatile unsigned char *const com1 = (unsigned char *) SERIAL_BASE;
-#ifdef SLOW_DOWN
-static inline void slow_down()
-{
-        int k;
-        for (k = 0; k < 10000; k++);
-}
-#else
-#define slow_down()
-#endif
-void putch(const unsigned char c)
-{
-        unsigned char ch;
-        int i = 0;
-        do {
-                ch = com1[SERB_CMD];
-                slow_down();
-                i++;
-                if (i > TIMEOUT) {
-                        break;
-                }
-        } while (0 == (ch & TX_BUSY));
-        com1[SERB_DATA] = c;
-}
-void putchar(const unsigned char c)
-{
-        unsigned char ch;
-        int i = 0;
-        do {
-                ch = com1[SERB_CMD];
-                slow_down();
-                i++;
-                if (i > TIMEOUT) {
-                        break;
-                }
-        } while (0 == (ch & TX_BUSY));
-        com1[SERB_DATA] = c;
-}
-void puts(unsigned char *cp)
-{
-        unsigned char ch;
-        int i = 0;
-        while (*cp) {
-                do {
-                        ch = com1[SERB_CMD];
-                        slow_down();
-                        i++;
-                        if (i > TIMEOUT) {
-                                break;
-                        }
-                } while (0 == (ch & TX_BUSY));
-                com1[SERB_DATA] = *cp++;
-        }
-        putch('\r');
-        putch('\n');
-}
-void fputs(unsigned char *cp)
-{
-        unsigned char ch;
-        int i = 0;
-        while (*cp) {
-                do {
-                        ch = com1[SERB_CMD];
-                        slow_down();
-                        i++;
-                        if (i > TIMEOUT) {
-                                break;
-                        }
-                } while (0 == (ch & TX_BUSY));
-                com1[SERB_DATA] = *cp++;
-        }
-}
-void put64(uint64_t ul)
-{
-        int cnt;
-        unsigned ch;
-        cnt = 16;               /* 16 nibbles in a 64 bit long */
-        putch('0');
-        putch('x');
-        do {
-                cnt--;
-                ch = (unsigned char) (ul >> cnt * 4) & 0x0F;
-                putch(digits[ch]);
-        } while (cnt > 0);
-}
-void put32(unsigned u)
-{
-        int cnt;
-        unsigned ch;
-        cnt = 8;                /* 8 nibbles in a 32 bit long */
-        putch('0');
-        putch('x');
-        do {
-                cnt--;
-                ch = (unsigned char) (u >> cnt * 4) & 0x0F;
-                putch(digits[ch]);
-        } while (cnt > 0);
-}
diff --git a/arch/mips/galileo-boards/ev96100/reset.c b/arch/mips/galileo-boards/ev96100/reset.c
deleted file mode 100644
index 5ef9b7f896e6..000000000000
--- a/arch/mips/galileo-boards/ev96100/reset.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *      Galileo EV96100 reset routines.
- *
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@mvista.com or source@mvista.com
- *
- * This file was derived from Carsten Langgaard's
- * arch/mips/mips-boards/generic/reset.c
- *
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/processor.h>
-#include <asm/reboot.h>
-#include <asm/system.h>
-#include <asm/gt64120.h>
-static void mips_machine_restart(char *command);
-static void mips_machine_halt(void);
-static void mips_machine_restart(char *command)
-{
-        set_c0_status(ST0_BEV | ST0_ERL);
-        change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
-        flush_cache_all();
-        write_c0_wired(0);
-        __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
-        while (1);
-}
-static void mips_machine_halt(void)
-{
-        printk(KERN_NOTICE "You can safely turn off the power\n");
-        while (1)
-                __asm__(".set\tmips3\n\t"
-                        "wait\n\t"
-                        ".set\tmips0");
-}
-void mips_reboot_setup(void)
-{
-        _machine_restart = mips_machine_restart;
-        _machine_halt = mips_machine_halt;
-}
diff --git a/arch/mips/galileo-boards/ev96100/setup.c b/arch/mips/galileo-boards/ev96100/setup.c
deleted file mode 100644
index 639ad5562c63..000000000000
--- a/arch/mips/galileo-boards/ev96100/setup.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *      Galileo EV96100 setup.
- *
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@mvista.com or source@mvista.com
- *
- * This file was derived from Carsten Langgaard's
- * arch/mips/mips-boards/atlas/atlas_setup.c.
- *
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/string.h>
-#include <linux/ctype.h>
-#include <linux/pci.h>
-#include <asm/cpu.h>
-#include <asm/bootinfo.h>
-#include <asm/mipsregs.h>
-#include <asm/irq.h>
-#include <asm/delay.h>
-#include <asm/gt64120.h>
-#include <asm/galileo-boards/ev96100int.h>
-extern char *__init prom_getcmdline(void);
-extern void mips_reboot_setup(void);
-unsigned char mac_0_1[12];
-void __init plat_mem_setup(void)
-{
-        unsigned int config = read_c0_config();
-        unsigned int status = read_c0_status();
-        unsigned int info = read_c0_info();
-        u32 tmp;
-        char *argptr;
-        clear_c0_status(ST0_FR);
-        if (config & 0x8)
-                printk("Secondary cache is enabled\n");
-        else
-                printk("Secondary cache is disabled\n");
-        if (status & (1 << 27))
-                printk("User-mode cache ops enabled\n");
-        else
-                printk("User-mode cache ops disabled\n");
-        printk("CP0 info reg: %x\n", (unsigned) info);
-        if (info & (1 << 28))
-                printk("burst mode Scache RAMS\n");
-        else
-                printk("pipelined Scache RAMS\n");
-        if (info & 0x1)
-                printk("Atomic Enable is set\n");
-        argptr = prom_getcmdline();
-#ifdef CONFIG_SERIAL_CONSOLE
-        if (strstr(argptr, "console=") == NULL) {
-                argptr = prom_getcmdline();
-                strcat(argptr, " console=ttyS0,115200");
-        }
-#endif
-        mips_reboot_setup();
-        set_io_port_base(KSEG1);
-        ioport_resource.start = GT_PCI_IO_BASE;
-        ioport_resource.end = GT_PCI_IO_BASE + 0x01ffffff;
-#ifdef CONFIG_BLK_DEV_INITRD
-        ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
-#endif
-        /*
-         * Setup GT controller master bit so we can do config cycles
-         */
-        /* Clear cause register bits */
-        GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
-                                     GT_INTRCAUSE_TARABORT0_BIT));
-        /* Setup address */
-        GT_WRITE(GT_PCI0_CFGADDR_OFS,
-                 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
-                 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
-                 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
-                 GT_PCI0_CFGADDR_CONFIGEN_BIT);
-        udelay(2);
-        tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
-        tmp |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
-                PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
-        GT_WRITE(GT_PCI0_CFGADDR_OFS,
-                 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
-                 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
-                 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
-                 GT_PCI0_CFGADDR_CONFIGEN_BIT);
-        udelay(2);
-        GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
-        /* Setup address */
-        GT_WRITE(GT_PCI0_CFGADDR_OFS,
-                 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
-                 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
-                 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
-                 GT_PCI0_CFGADDR_CONFIGEN_BIT);
-        udelay(2);
-        tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
-}
-unsigned short get_gt_devid(void)
-{
-        u32 gt_devid;
-        /* Figure out if this is a gt96100 or gt96100A */
-        GT_WRITE(GT_PCI0_CFGADDR_OFS,
-                 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
-                 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
-                 ((PCI_VENDOR_ID / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
-                 GT_PCI0_CFGADDR_CONFIGEN_BIT);
-        udelay(4);
-        gt_devid = GT_READ(GT_PCI0_CFGDATA_OFS);
-        return gt_devid >> 16;
-}
diff --git a/arch/mips/galileo-boards/ev96100/time.c b/arch/mips/galileo-boards/ev96100/time.c
deleted file mode 100644
index 8cbe8426491a..000000000000
--- a/arch/mips/galileo-boards/ev96100/time.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *      Galileo EV96100 rtc routines.
- *
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@mvista.com or source@mvista.com
- *
- * This file was derived from Carsten Langgaard's
- * arch/mips/mips-boards/atlas/atlas_rtc.c.
- *
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/init.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/timex.h>
-#include <asm/mipsregs.h>
-#include <asm/ptrace.h>
-#include <asm/time.h>
-#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
-extern volatile unsigned long wall_jiffies;
-unsigned long missed_heart_beats = 0;
-static unsigned long r4k_offset; /* Amount to increment compare reg each time */
-static unsigned long r4k_cur;    /* What counter should be at next timer irq */
-static inline void ack_r4ktimer(unsigned long newval)
-{
-        write_c0_compare(newval);
-}
-/*
- * There are a lot of conceptually broken versions of the MIPS timer interrupt
- * handler floating around.  This one is rather different, but the algorithm
- * is probably more robust.
- */
-void mips_timer_interrupt(struct pt_regs *regs)
-{
-        int irq = 7; /* FIX ME */
-        if (r4k_offset == 0) {
-            goto null;
-        }
-        do {
-                kstat_this_cpu.irqs[irq]++;
-                do_timer(regs);
-#ifndef CONFIG_SMP
-                update_process_times(user_mode(regs));
-#endif
-                r4k_cur += r4k_offset;
-                ack_r4ktimer(r4k_cur);
-        } while (((unsigned long)read_c0_count()
-                    - r4k_cur) < 0x7fffffff);
-        return;
-null:
-        ack_r4ktimer(0);
-}
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index aa2caa67299a..9fbf8430c849 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -38,15 +38,40 @@ static void r3081_wait(void)
 static void r39xx_wait(void)
 {
-        unsigned long cfg = read_c0_conf();
+        local_irq_disable();
-        write_c0_conf(cfg | TX39_CONF_HALT);
+        if (!need_resched())
+                write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
+        local_irq_enable();
 }
+/*
+ * There is a race when WAIT instruction executed with interrupt
+ * enabled.
+ * But it is implementation-dependent wheter the pipelie restarts when
+ * a non-enabled interrupt is requested.
+ */
 static void r4k_wait(void)
 {
-        __asm__(".set\tmips3\n\t"
+        __asm__("       .set    mips3                   \n"
-                "wait\n\t"
+                "       wait                            \n"
-                ".set\tmips0");
+                "       .set    mips0                   \n");
+}
+/*
+ * This variant is preferable as it allows testing need_resched and going to
+ * sleep depending on the outcome atomically.  Unfortunately the "It is
+ * implementation-dependent whether the pipeline restarts when a non-enabled
+ * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
+ * using this version a gamble.
+ */
+static void r4k_wait_irqoff(void)
+{
+        local_irq_disable();
+        if (!need_resched())
+                __asm__("       .set    mips3           \n"
+                        "       wait                    \n"
+                        "       .set    mips0           \n");
+        local_irq_enable();
 }
 /* The Au1xxx wait is available only if using 32khz counter or
@@ -56,17 +81,17 @@ int allow_au1k_wait;
 static void au1k_wait(void)
 {
        /* using the wait instruction makes CP0 counter unusable */
-        __asm__(".set mips3\n\t"
+        __asm__("       .set    mips3                   \n"
-                "cache 0x14, 0(%0)\n\t"
+                "       cache   0x14, 0(%0)             \n"
-                "cache 0x14, 32(%0)\n\t"
+                "       cache   0x14, 32(%0)            \n"
-                "sync\n\t"
+                "       sync                            \n"
-                "nop\n\t"
+                "       nop                             \n"
-                "wait\n\t"
+                "       wait                            \n"
-                "nop\n\t"
+                "       nop                             \n"
-                "nop\n\t"
+                "       nop                             \n"
-                "nop\n\t"
+                "       nop                             \n"
-                "nop\n\t"
+                "       nop                             \n"
-                ".set mips0\n\t"
+                "       .set    mips0                   \n"
                : : "r" (au1k_wait));
 }
@@ -111,7 +136,6 @@ static inline void check_wait(void)
        case CPU_NEVADA:
        case CPU_RM7000:
        case CPU_RM9000:
-        case CPU_TX49XX:
        case CPU_4KC:
        case CPU_4KEC:
        case CPU_4KSC:
@@ -125,6 +149,10 @@ static inline void check_wait(void)
                cpu_wait = r4k_wait;
                printk(" available.\n");
                break;
+        case CPU_TX49XX:
+                cpu_wait = r4k_wait_irqoff;
+                printk(" available.\n");
+                break;
        case CPU_AU1000:
        case CPU_AU1100:
        case CPU_AU1500:
diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c
index 676e868d26fb..2132485caa74 100644
--- a/arch/mips/kernel/irixsig.c
+++ b/arch/mips/kernel/irixsig.c
@@ -17,6 +17,7 @@
 #include <asm/ptrace.h>
 #include <asm/uaccess.h>
+#include <asm/unistd.h>
 #undef DEBUG_SIG
@@ -172,11 +173,12 @@ static inline int handle_signal(unsigned long sig, siginfo_t *info,
        return ret;
 }
-asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs)
+void do_irix_signal(struct pt_regs *regs)
 {
        struct k_sigaction ka;
        siginfo_t info;
        int signr;
+        sigset_t *oldset;
        /*
         * We want the common case to go fast, which is why we may in certain
@@ -184,19 +186,28 @@ asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs)
         * if so.
         */
        if (!user_mode(regs))
-                return 1;
+                return;
-        if (try_to_freeze())
+        if (test_thread_flag(TIF_RESTORE_SIGMASK))
-                goto no_signal;
+                oldset = &current->saved_sigmask;
+        else
-        if (!oldset)
                oldset = &current->blocked;
        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
-        if (signr > 0)
+        if (signr > 0) {
-                return handle_signal(signr, &info, &ka, oldset, regs);
+                /* Whee!  Actually deliver the signal.  */
+                if (handle_signal(signr, &info, &ka, oldset, regs) == 0) {
+                        /* a signal was successfully delivered; the saved
+                         * sigmask will have been stored in the signal frame,
+                         * and will be restored by sigreturn, so we can simply
+                         * clear the TIF_RESTORE_SIGMASK flag */
+                        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                }
+                return;
+        }
-no_signal:
        /*
         * Who's code doesn't conform to the restartable syscall convention
         * dies here!!!  The li instruction, a single machine instruction,
@@ -208,8 +219,22 @@ no_signal:
                    regs->regs[2] == ERESTARTNOINTR) {
                        regs->cp0_epc -= 8;
                }
+                if (regs->regs[2] == ERESTART_RESTARTBLOCK) {
+                        regs->regs[2] = __NR_restart_syscall;
+                        regs->regs[7] = regs->regs[26];
+                        regs->cp0_epc -= 4;
+                }
+                regs->regs[0] = 0;      /* Don't deal with this again.  */
+        }
+        /*
+        * If there's no signal to deliver, we just put the saved sigmask
+        * back
+        */
+        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
        }
-        return 0;
 }
 asmlinkage void
@@ -298,6 +323,9 @@ struct sigact_irix5 {
        int _unused0[2];
 };
+#define SIG_SETMASK32   256     /* Goodie from SGI for BSD compatibility:
+                                   set only the low 32 bit of the sigset.  */
 #ifdef DEBUG_SIG
 static inline void dump_sigact_irix5(struct sigact_irix5 *p)
 {
@@ -413,7 +441,7 @@ asmlinkage int irix_sigprocmask(int how, irix_sigset_t __user *new,
 asmlinkage int irix_sigsuspend(struct pt_regs *regs)
 {
-        sigset_t saveset, newset;
+        sigset_t newset;
        sigset_t __user *uset;
        uset = (sigset_t __user *) regs->regs[4];
@@ -422,18 +450,15 @@ asmlinkage int irix_sigsuspend(struct pt_regs *regs)
        sigdelsetmask(&newset, ~_BLOCKABLE);
        spin_lock_irq(&current->sighand->siglock);
-        saveset = current->blocked;
+        current->saved_sigmask = current->blocked;
        current->blocked = newset;
        recalc_sigpending();
        spin_unlock_irq(&current->sighand->siglock);
-        regs->regs[2] = -EINTR;
+        current->state = TASK_INTERRUPTIBLE;
-        while (1) {
+        schedule();
-                current->state = TASK_INTERRUPTIBLE;
+        set_thread_flag(TIF_RESTORE_SIGMASK);
-                schedule();
+        return -ERESTARTNOHAND;
-                if (do_irix_signal(&saveset, regs))
-                        return -EINTR;
-        }
 }
 /* hate hate hate... */
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 450ac592da57..dc500e20cf14 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -1296,9 +1296,3 @@ _sys32_clone(nabi_no_regargs struct pt_regs regs)
        return do_fork(clone_flags, newsp, &regs, 0,
                       parent_tidptr, child_tidptr);
 }
-extern asmlinkage void sys_set_thread_area(u32 addr);
-asmlinkage void sys32_set_thread_area(u32 addr)
-{
-        sys_set_thread_area(AA(addr));
-}
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 7ab67f786bfe..2613a0dd4b82 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -273,104 +273,107 @@ long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
        return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 }
-static struct mips_frame_info {
+/*
-        void *func;
+ *
-        unsigned long func_size;
+ */
-        int frame_size;
+struct mips_frame_info {
-        int pc_offset;
+        void            *func;
-} *schedule_frame, mfinfo[64];
+        unsigned long   func_size;
-static int mfinfo_num;
+        int             frame_size;
+        int             pc_offset;
-static int __init get_frame_info(struct mips_frame_info *info)
+};
+static inline int is_ra_save_ins(union mips_instruction *ip)
 {
-        int i;
+        /* sw / sd $ra, offset($sp) */
-        void *func = info->func;
+        return (ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) &&
-        union mips_instruction *ip = (union mips_instruction *)func;
+                ip->i_format.rs == 29 &&
+                ip->i_format.rt == 31;
+}
+static inline int is_jal_jalr_jr_ins(union mips_instruction *ip)
+{
+        if (ip->j_format.opcode == jal_op)
+                return 1;
+        if (ip->r_format.opcode != spec_op)
+                return 0;
+        return ip->r_format.func == jalr_op || ip->r_format.func == jr_op;
+}
+static inline int is_sp_move_ins(union mips_instruction *ip)
+{
+        /* addiu/daddiu sp,sp,-imm */
+        if (ip->i_format.rs != 29 || ip->i_format.rt != 29)
+                return 0;
+        if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op)
+                return 1;
+        return 0;
+}
+static int get_frame_info(struct mips_frame_info *info)
+{
+        union mips_instruction *ip = info->func;
+        unsigned max_insns = info->func_size / sizeof(union mips_instruction);
+        unsigned i;
        info->pc_offset = -1;
        info->frame_size = 0;
-        for (i = 0; i < 128; i++, ip++) {
-                /* if jal, jalr, jr, stop. */
-                if (ip->j_format.opcode == jal_op ||
-                    (ip->r_format.opcode == spec_op &&
-                     (ip->r_format.func == jalr_op ||
-                      ip->r_format.func == jr_op)))
-                        break;
-                if (info->func_size && i >= info->func_size / 4)
+        if (!ip)
+                goto err;
+        if (max_insns == 0)
+                max_insns = 128U;       /* unknown function size */
+        max_insns = min(128U, max_insns);
+        for (i = 0; i < max_insns; i++, ip++) {
+                if (is_jal_jalr_jr_ins(ip))
                        break;
-                if (
+                if (!info->frame_size) {
-#ifdef CONFIG_32BIT
+                        if (is_sp_move_ins(ip))
-                    ip->i_format.opcode == addiu_op &&
+                                info->frame_size = - ip->i_format.simmediate;
-#endif
+                        continue;
-#ifdef CONFIG_64BIT
-                    ip->i_format.opcode == daddiu_op &&
-#endif
-                    ip->i_format.rs == 29 &&
-                    ip->i_format.rt == 29) {
-                        /* addiu/daddiu sp,sp,-imm */
-                        if (info->frame_size)
-                                continue;
-                        info->frame_size = - ip->i_format.simmediate;
                }
+                if (info->pc_offset == -1 && is_ra_save_ins(ip)) {
-                if (
-#ifdef CONFIG_32BIT
-                    ip->i_format.opcode == sw_op &&
-#endif
-#ifdef CONFIG_64BIT
-                    ip->i_format.opcode == sd_op &&
-#endif
-                    ip->i_format.rs == 29 &&
-                    ip->i_format.rt == 31) {
-                        /* sw / sd $ra, offset($sp) */
-                        if (info->pc_offset != -1)
-                                continue;
                        info->pc_offset =
                                ip->i_format.simmediate / sizeof(long);
+                        break;
                }
        }
-        if (info->pc_offset == -1 || info->frame_size == 0) {
+        if (info->frame_size && info->pc_offset >= 0) /* nested */
-                if (func == schedule)
+                return 0;
-                        printk("Can't analyze prologue code at %p\n", func);
+        if (info->pc_offset < 0) /* leaf */
-                info->pc_offset = -1;
+                return 1;
-                info->frame_size = 0;
+        /* prologue seems boggus... */
-        }
+err:
+        return -1;
-        return 0;
 }
+static struct mips_frame_info schedule_mfi __read_mostly;
 static int __init frame_info_init(void)
 {
-        int i;
+        unsigned long size = 0;
 #ifdef CONFIG_KALLSYMS
+        unsigned long ofs;
        char *modname;
        char namebuf[KSYM_NAME_LEN + 1];
-        unsigned long start, size, ofs;
-        extern char __sched_text_start[], __sched_text_end[];
+        kallsyms_lookup((unsigned long)schedule, &size, &ofs, &modname, namebuf);
-        extern char __lock_text_start[], __lock_text_end[];
-        start = (unsigned long)__sched_text_start;
-        for (i = 0; i < ARRAY_SIZE(mfinfo); i++) {
-                if (start == (unsigned long)schedule)
-                        schedule_frame = &mfinfo[i];
-                if (!kallsyms_lookup(start, &size, &ofs, &modname, namebuf))
-                        break;
-                mfinfo[i].func = (void *)(start + ofs);
-                mfinfo[i].func_size = size;
-                start += size - ofs;
-                if (start >= (unsigned long)__lock_text_end)
-                        break;
-                if (start == (unsigned long)__sched_text_end)
-                        start = (unsigned long)__lock_text_start;
-        }
-#else
-        mfinfo[0].func = schedule;
-        schedule_frame = &mfinfo[0];
 #endif
-        for (i = 0; i < ARRAY_SIZE(mfinfo) && mfinfo[i].func; i++)
+        schedule_mfi.func = schedule;
-                get_frame_info(&mfinfo[i]);
+        schedule_mfi.func_size = size;
+        get_frame_info(&schedule_mfi);
+        /*
+         * Without schedule() frame info, result given by
+         * thread_saved_pc() and get_wchan() are not reliable.
+         */
+        if (schedule_mfi.pc_offset < 0)
+                printk("Can't analyze schedule() prologue at %p\n", schedule);
-        mfinfo_num = i;
        return 0;
 }
@@ -386,54 +389,86 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
        /* New born processes are a special case */
        if (t->reg31 == (unsigned long) ret_from_fork)
                return t->reg31;
+        if (schedule_mfi.pc_offset < 0)
-        if (!schedule_frame || schedule_frame->pc_offset < 0)
                return 0;
-        return ((unsigned long *)t->reg29)[schedule_frame->pc_offset];
+        return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset];
 }
-/* get_wchan - a maintenance nightmare^W^Wpain in the ass ...  */
-unsigned long get_wchan(struct task_struct *p)
+#ifdef CONFIG_KALLSYMS
+/* used by show_backtrace() */
+unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
+                           unsigned long pc, unsigned long ra)
 {
        unsigned long stack_page;
-        unsigned long pc;
+        struct mips_frame_info info;
-#ifdef CONFIG_KALLSYMS
+        char *modname;
-        unsigned long frame;
+        char namebuf[KSYM_NAME_LEN + 1];
-#endif
+        unsigned long size, ofs;
+        int leaf;
-        if (!p || p == current || p->state == TASK_RUNNING)
+        stack_page = (unsigned long)task_stack_page(task);
+        if (!stack_page)
                return 0;
-        stack_page = (unsigned long)task_stack_page(p);
+        if (!kallsyms_lookup(pc, &size, &ofs, &modname, namebuf))
-        if (!stack_page || !mfinfo_num)
+                return 0;
+        /*
+         * Return ra if an exception occured at the first instruction
+         */
+        if (unlikely(ofs == 0))
+                return ra;
+        info.func = (void *)(pc - ofs);
+        info.func_size = ofs;   /* analyze from start to ofs */
+        leaf = get_frame_info(&info);
+        if (leaf < 0)
+                return 0;
+        if (*sp < stack_page ||
+            *sp + info.frame_size > stack_page + THREAD_SIZE - 32)
                return 0;
-        pc = thread_saved_pc(p);
+        if (leaf)
+                /*
+                 * For some extreme cases, get_frame_info() can
+                 * consider wrongly a nested function as a leaf
+                 * one. In that cases avoid to return always the
+                 * same value.
+                 */
+                pc = pc != ra ? ra : 0;
+        else
+                pc = ((unsigned long *)(*sp))[info.pc_offset];
+        *sp += info.frame_size;
+        return __kernel_text_address(pc) ? pc : 0;
+}
+#endif
+/*
+ * get_wchan - a maintenance nightmare^W^Wpain in the ass ...
+ */
+unsigned long get_wchan(struct task_struct *task)
+{
+        unsigned long pc = 0;
 #ifdef CONFIG_KALLSYMS
-        if (!in_sched_functions(pc))
+        unsigned long sp;
-                return pc;
+#endif
-        frame = p->thread.reg29 + schedule_frame->frame_size;
+        if (!task || task == current || task->state == TASK_RUNNING)
-        do {
+                goto out;
-                int i;
+        if (!task_stack_page(task))
+                goto out;
-                if (frame < stack_page || frame > stack_page + THREAD_SIZE - 32)
+        pc = thread_saved_pc(task);
-                        return 0;
-                for (i = mfinfo_num - 1; i >= 0; i--) {
+#ifdef CONFIG_KALLSYMS
-                        if (pc >= (unsigned long) mfinfo[i].func)
+        sp = task->thread.reg29 + schedule_mfi.frame_size;
-                                break;
-                }
-                if (i < 0)
-                        break;
-                pc = ((unsigned long *)frame)[mfinfo[i].pc_offset];
+        while (in_sched_functions(pc))
-                if (!mfinfo[i].frame_size)
+                pc = unwind_stack(task, &sp, pc, 0);
-                        break;
-                frame += mfinfo[i].frame_size;
-        } while (in_sched_functions(pc));
 #endif
+out:
        return pc;
 }
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index ba1bcd83c7d3..e71785102206 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -662,6 +662,8 @@ einval:	li	v0, -EINVAL
        sys     sys_tee                 4
        sys     sys_vmsplice            4
        sys     sys_move_pages          6
+        sys     sys_set_robust_list     2
+        sys     sys_get_robust_list     3
        .endm
        /* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 939e172db953..4c22d0b4825d 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -466,3 +466,5 @@ sys_call_table:
        PTR     sys_tee                         /* 5265 */
        PTR     sys_vmsplice
        PTR     sys_move_pages
+        PTR     sys_set_robust_list
+        PTR     sys_get_robust_list
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 98abbc5a9f13..f25c2a2f1038 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -247,7 +247,7 @@ EXPORT(sysn32_call_table)
        PTR     sys_capset
        PTR     sys32_rt_sigpending             /* 6125 */
        PTR     compat_sys_rt_sigtimedwait
-        PTR     sys_rt_sigqueueinfo
+        PTR     sys32_rt_sigqueueinfo
        PTR     sysn32_rt_sigsuspend
        PTR     sys32_sigaltstack
        PTR     compat_sys_utime                /* 6130 */
@@ -390,5 +390,7 @@ EXPORT(sysn32_call_table)
        PTR     sys_splice
        PTR     sys_sync_file_range
        PTR     sys_tee
-        PTR     sys_vmsplice                    /* 6271 */
+        PTR     sys_vmsplice                    /* 6270 */
        PTR     sys_move_pages
+        PTR     compat_sys_set_robust_list
+        PTR     compat_sys_get_robust_list
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 505c9ee54009..288ee4ac4dbb 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -498,7 +498,7 @@ sys_call_table:
        PTR     sys_mknodat                     /* 4290 */
        PTR     sys_fchownat
        PTR     compat_sys_futimesat
-        PTR     compat_sys_newfstatat
+        PTR     sys_newfstatat
        PTR     sys_unlinkat
        PTR     sys_renameat                    /* 4295 */
        PTR     sys_linkat
@@ -514,4 +514,6 @@ sys_call_table:
        PTR     sys_tee
        PTR     sys_vmsplice
        PTR     compat_sys_move_pages
+        PTR     compat_sys_set_robust_list
+        PTR     compat_sys_get_robust_list      /* 4310 */
        .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8c2b596a136f..fdbb508661c5 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -10,29 +10,15 @@
 * Copyright (C) 1999 Silicon Graphics, Inc.
 * Copyright (C) 2000 2001, 2002  Maciej W. Rozycki
 */
-#include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
 #include <linux/module.h>
-#include <linux/stddef.h>
-#include <linux/string.h>
-#include <linux/unistd.h>
-#include <linux/slab.h>
-#include <linux/user.h>
-#include <linux/utsname.h>
-#include <linux/a.out.h>
 #include <linux/screen_info.h>
 #include <linux/bootmem.h>
 #include <linux/initrd.h>
-#include <linux/major.h>
-#include <linux/kdev_t.h>
 #include <linux/root_dev.h>
 #include <linux/highmem.h>
 #include <linux/console.h>
-#include <linux/mmzone.h>
 #include <linux/pfn.h>
 #include <asm/addrspace.h>
@@ -96,6 +82,12 @@ void __init add_memory_region(phys_t start, phys_t size, long type)
        int x = boot_mem_map.nr_map;
        struct boot_mem_map_entry *prev = boot_mem_map.map + x - 1;
+        /* Sanity check */
+        if (start + size < start) {
+                printk("Trying to add an invalid memory region, skipped\n");
+                return;
+        }
        /*
         * Try to merge with previous entry if any.  This is far less than
         * perfect but is sufficient for most real world cases.
@@ -143,167 +135,132 @@ static void __init print_memory_map(void)
        }
 }
-static inline void parse_cmdline_early(void)
+/*
+ * Manage initrd
+ */
+#ifdef CONFIG_BLK_DEV_INITRD
+static int __init rd_start_early(char *p)
 {
-        char c = ' ', *to = command_line, *from = saved_command_line;
+        unsigned long start = memparse(p, &p);
-        unsigned long start_at, mem_size;
-        int len = 0;
-        int usermem = 0;
-        printk("Determined physical RAM map:\n");
+#ifdef CONFIG_64BIT
-        print_memory_map();
+        /* HACK: Guess if the sign extension was forgotten */
+        if (start > 0x0000000080000000 && start < 0x00000000ffffffff)
+                start |= 0xffffffff00000000UL;
+#endif
+        initrd_start = start;
+        initrd_end += start;
-        for (;;) {
+        return 0;
-                /*
+}
-                 * "mem=XXX[kKmM]" defines a memory region from
+early_param("rd_start", rd_start_early);
-                 * 0 to <XXX>, overriding the determined size.
-                 * "mem=XXX[KkmM]@YYY[KkmM]" defines a memory region from
-                 * <YYY> to <YYY>+<XXX>, overriding the determined size.
-                 */
-                if (c == ' ' && !memcmp(from, "mem=", 4)) {
-                        if (to != command_line)
-                                to--;
-                        /*
-                         * If a user specifies memory size, we
-                         * blow away any automatically generated
-                         * size.
-                         */
-                        if (usermem == 0) {
-                                boot_mem_map.nr_map = 0;
-                                usermem = 1;
-                        }
-                        mem_size = memparse(from + 4, &from);
-                        if (*from == '@')
-                                start_at = memparse(from + 1, &from);
-                        else
-                                start_at = 0;
-                        add_memory_region(start_at, mem_size, BOOT_MEM_RAM);
-                }
-                c = *(from++);
-                if (!c)
-                        break;
-                if (CL_SIZE <= ++len)
-                        break;
-                *(to++) = c;
-        }
-        *to = '\0';
-        if (usermem) {
+static int __init rd_size_early(char *p)
-                printk("User-defined physical RAM map:\n");
+{
-                print_memory_map();
+        initrd_end += memparse(p, &p);
-        }
+        return 0;
 }
+early_param("rd_size", rd_size_early);
-static inline int parse_rd_cmdline(unsigned long* rd_start, unsigned long* rd_end)
+static unsigned long __init init_initrd(void)
 {
+        unsigned long tmp, end, size;
+        u32 *initrd_header;
+        ROOT_DEV = Root_RAM0;
        /*
-         * "rd_start=0xNNNNNNNN" defines the memory address of an initrd
+         * Board specific code or command line parser should have
-         * "rd_size=0xNN" it's size
+         * already set up initrd_start and initrd_end. In these cases
+         * perfom sanity checks and use them if all looks good.
         */
-        unsigned long start = 0;
+        size = initrd_end - initrd_start;
-        unsigned long size = 0;
+        if (initrd_end == 0 || size == 0) {
-        unsigned long end;
+                initrd_start = 0;
-        char cmd_line[CL_SIZE];
+                initrd_end = 0;
-        char *start_str;
+        } else
-        char *size_str;
+                return initrd_end;
-        char *tmp;
+        end = (unsigned long)&_end;
-        strcpy(cmd_line, command_line);
+        tmp = PAGE_ALIGN(end) - sizeof(u32) * 2;
-        *command_line = 0;
+        if (tmp < end)
-        tmp = cmd_line;
+                tmp += PAGE_SIZE;
-        /* Ignore "rd_start=" strings in other parameters. */
-        start_str = strstr(cmd_line, "rd_start=");
+        initrd_header = (u32 *)tmp;
-        if (start_str && start_str != cmd_line && *(start_str - 1) != ' ')
+        if (initrd_header[0] == 0x494E5244) {
-                start_str = strstr(start_str, " rd_start=");
+                initrd_start = (unsigned long)&initrd_header[2];
-        while (start_str) {
+                initrd_end = initrd_start + initrd_header[1];
-                if (start_str != cmd_line)
-                        strncat(command_line, tmp, start_str - tmp);
-                start = memparse(start_str + 9, &start_str);
-                tmp = start_str + 1;
-                start_str = strstr(start_str, " rd_start=");
        }
-        if (*tmp)
+        return initrd_end;
-                strcat(command_line, tmp);
+}
-        strcpy(cmd_line, command_line);
+static void __init finalize_initrd(void)
-        *command_line = 0;
+{
-        tmp = cmd_line;
+        unsigned long size = initrd_end - initrd_start;
-        /* Ignore "rd_size" strings in other parameters. */
-        size_str = strstr(cmd_line, "rd_size=");
+        if (size == 0) {
-        if (size_str && size_str != cmd_line && *(size_str - 1) != ' ')
+                printk(KERN_INFO "Initrd not found or empty");
-                size_str = strstr(size_str, " rd_size=");
+                goto disable;
-        while (size_str) {
+        }
-                if (size_str != cmd_line)
+        if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) {
-                        strncat(command_line, tmp, size_str - tmp);
+                printk("Initrd extends beyond end of memory");
-                size = memparse(size_str + 8, &size_str);
+                goto disable;
-                tmp = size_str + 1;
-                size_str = strstr(size_str, " rd_size=");
        }
-        if (*tmp)
-                strcat(command_line, tmp);
-#ifdef CONFIG_64BIT
+        reserve_bootmem(CPHYSADDR(initrd_start), size);
-        /* HACK: Guess if the sign extension was forgotten */
+        initrd_below_start_ok = 1;
-        if (start > 0x0000000080000000 && start < 0x00000000ffffffff)
-                start |= 0xffffffff00000000UL;
+        printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
+               initrd_start, size);
+        return;
+disable:
+        printk(" - disabling initrd\n");
+        initrd_start = 0;
+        initrd_end = 0;
+}
+#else  /* !CONFIG_BLK_DEV_INITRD */
+#define init_initrd()           0
+#define finalize_initrd()       do {} while (0)
 #endif
-        end = start + size;
+/*
-        if (start && end) {
+ * Initialize the bootmem allocator. It also setup initrd related data
-                *rd_start = start;
+ * if needed.
-                *rd_end = end;
+ */
-                return 1;
+#ifdef CONFIG_SGI_IP27
-        }
-        return 0;
+static void __init bootmem_init(void)
+{
+        init_initrd();
+        finalize_initrd();
 }
-#define MAXMEM          HIGHMEM_START
+#else  /* !CONFIG_SGI_IP27 */
-#define MAXMEM_PFN      PFN_DOWN(MAXMEM)
-static inline void bootmem_init(void)
+static void __init bootmem_init(void)
 {
-        unsigned long start_pfn;
+        unsigned long reserved_end;
-        unsigned long reserved_end = (unsigned long)&_end;
+        unsigned long highest = 0;
-#ifndef CONFIG_SGI_IP27
+        unsigned long mapstart = -1UL;
-        unsigned long first_usable_pfn;
        unsigned long bootmap_size;
        int i;
-#endif
-#ifdef CONFIG_BLK_DEV_INITRD
-        int initrd_reserve_bootmem = 0;
-        /* Board specific code should have set up initrd_start and initrd_end */
-        ROOT_DEV = Root_RAM0;
-        if (parse_rd_cmdline(&initrd_start, &initrd_end)) {
-                reserved_end = max(reserved_end, initrd_end);
-                initrd_reserve_bootmem = 1;
-        } else {
-                unsigned long tmp;
-                u32 *initrd_header;
-                tmp = ((reserved_end + PAGE_SIZE-1) & PAGE_MASK) - sizeof(u32) * 2;
-                if (tmp < reserved_end)
-                        tmp += PAGE_SIZE;
-                initrd_header = (u32 *)tmp;
-                if (initrd_header[0] == 0x494E5244) {
-                        initrd_start = (unsigned long)&initrd_header[2];
-                        initrd_end = initrd_start + initrd_header[1];
-                        reserved_end = max(reserved_end, initrd_end);
-                        initrd_reserve_bootmem = 1;
-                }
-        }
-#endif  /* CONFIG_BLK_DEV_INITRD */
        /*
-         * Partially used pages are not usable - thus
+         * Init any data related to initrd. It's a nop if INITRD is
-         * we are rounding upwards.
+         * not selected. Once that done we can determine the low bound
+         * of usable memory.
         */
-        start_pfn = PFN_UP(CPHYSADDR(reserved_end));
+        reserved_end = init_initrd();
+        reserved_end = PFN_UP(CPHYSADDR(max(reserved_end, (unsigned long)&_end)));
-#ifndef CONFIG_SGI_IP27
+        /*
-        /* Find the highest page frame number we have available.  */
+         * Find the highest page frame number we have available.
-        max_pfn = 0;
+         */
-        first_usable_pfn = -1UL;
        for (i = 0; i < boot_mem_map.nr_map; i++) {
                unsigned long start, end;
@@ -312,56 +269,38 @@ static inline void bootmem_init(void)
                start = PFN_UP(boot_mem_map.map[i].addr);
                end = PFN_DOWN(boot_mem_map.map[i].addr
-                      + boot_mem_map.map[i].size);
+                                + boot_mem_map.map[i].size);
-                if (start >= end)
+                if (end > highest)
+                        highest = end;
+                if (end <= reserved_end)
                        continue;
-                if (end > max_pfn)
+                if (start >= mapstart)
-                        max_pfn = end;
+                        continue;
-                if (start < first_usable_pfn) {
+                mapstart = max(reserved_end, start);
-                        if (start > start_pfn) {
-                                first_usable_pfn = start;
-                        } else if (end > start_pfn) {
-                                first_usable_pfn = start_pfn;
-                        }
-                }
        }
        /*
         * Determine low and high memory ranges
         */
-        max_low_pfn = max_pfn;
+        if (highest > PFN_DOWN(HIGHMEM_START)) {
-        if (max_low_pfn > MAXMEM_PFN) {
+#ifdef CONFIG_HIGHMEM
-                max_low_pfn = MAXMEM_PFN;
+                highstart_pfn = PFN_DOWN(HIGHMEM_START);
-#ifndef CONFIG_HIGHMEM
+                highend_pfn = highest;
-                /* Maximum memory usable is what is directly addressable */
-                printk(KERN_WARNING "Warning only %ldMB will be used.\n",
-                       MAXMEM >> 20);
-                printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n");
 #endif
+                highest = PFN_DOWN(HIGHMEM_START);
        }
-#ifdef CONFIG_HIGHMEM
        /*
-         * Crude, we really should make a better attempt at detecting
+         * Initialize the boot-time allocator with low memory only.
-         * highstart_pfn
         */
-        highstart_pfn = highend_pfn = max_pfn;
+        bootmap_size = init_bootmem(mapstart, highest);
-        if (max_pfn > MAXMEM_PFN) {
-                highstart_pfn = MAXMEM_PFN;
-                printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
-                       (highend_pfn - highstart_pfn) >> (20 - PAGE_SHIFT));
-        }
-#endif
-        /* Initialize the boot-time allocator with low memory only.  */
-        bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
        /*
         * Register fully available low RAM pages with the bootmem allocator.
         */
        for (i = 0; i < boot_mem_map.nr_map; i++) {
-                unsigned long curr_pfn, last_pfn, size;
+                unsigned long start, end, size;
                /*
                 * Reserve usable memory.
@@ -369,85 +308,50 @@ static inline void bootmem_init(void)
                if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
                        continue;
-                /*
+                start = PFN_UP(boot_mem_map.map[i].addr);
-                 * We are rounding up the start address of usable memory:
+                end   = PFN_DOWN(boot_mem_map.map[i].addr
-                 */
-                curr_pfn = PFN_UP(boot_mem_map.map[i].addr);
-                if (curr_pfn >= max_low_pfn)
-                        continue;
-                if (curr_pfn < start_pfn)
-                        curr_pfn = start_pfn;
-                /*
-                 * ... and at the end of the usable range downwards:
-                 */
-                last_pfn = PFN_DOWN(boot_mem_map.map[i].addr
                                    + boot_mem_map.map[i].size);
-                if (last_pfn > max_low_pfn)
-                        last_pfn = max_low_pfn;
                /*
-                 * Only register lowmem part of lowmem segment with bootmem.
+                 * We are rounding up the start address of usable memory
+                 * and at the end of the usable range downwards.
                 */
-                size = last_pfn - curr_pfn;
+                if (start >= max_low_pfn)
-                if (curr_pfn > PFN_DOWN(HIGHMEM_START))
-                        continue;
-                if (curr_pfn + size - 1 > PFN_DOWN(HIGHMEM_START))
-                        size = PFN_DOWN(HIGHMEM_START) - curr_pfn;
-                if (!size)
                        continue;
+                if (start < reserved_end)
+                        start = reserved_end;
+                if (end > max_low_pfn)
+                        end = max_low_pfn;
                /*
-                 * ... finally, did all the rounding and playing
+                 * ... finally, is the area going away?
-                 * around just make the area go away?
                 */
-                if (last_pfn <= curr_pfn)
+                if (end <= start)
                        continue;
+                size = end - start;
                /* Register lowmem ranges */
-                free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
+                free_bootmem(PFN_PHYS(start), size << PAGE_SHIFT);
-                memory_present(0, curr_pfn, curr_pfn + size - 1);
+                memory_present(0, start, end);
        }
-        /* Reserve the bootmap memory.  */
+        /*
-        reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
+         * Reserve the bootmap memory.
-#endif /* CONFIG_SGI_IP27 */
+         */
+        reserve_bootmem(PFN_PHYS(mapstart), bootmap_size);
-#ifdef CONFIG_BLK_DEV_INITRD
-        initrd_below_start_ok = 1;
-        if (initrd_start) {
-                unsigned long initrd_size = ((unsigned char *)initrd_end) -
-                        ((unsigned char *)initrd_start);
-                const int width = sizeof(long) * 2;
-                printk("Initial ramdisk at: 0x%p (%lu bytes)\n",
-                       (void *)initrd_start, initrd_size);
-                if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) {
-                        printk("initrd extends beyond end of memory "
-                               "(0x%0*Lx > 0x%0*Lx)\ndisabling initrd\n",
-                               width,
-                               (unsigned long long) CPHYSADDR(initrd_end),
-                               width,
-                               (unsigned long long) PFN_PHYS(max_low_pfn));
-                        initrd_start = initrd_end = 0;
-                        initrd_reserve_bootmem = 0;
-                }
-                if (initrd_reserve_bootmem)
+        /*
-                        reserve_bootmem(CPHYSADDR(initrd_start), initrd_size);
+         * Reserve initrd memory if needed.
-        }
+         */
-#endif /* CONFIG_BLK_DEV_INITRD  */
+        finalize_initrd();
 }
+#endif  /* CONFIG_SGI_IP27 */
 /*
 * arch_mem_init - initialize memory managment subsystem
 *
 *  o plat_mem_setup() detects the memory configuration and will record detected
 *    memory areas using add_memory_region.
- *  o parse_cmdline_early() parses the command line for mem= options which,
- *    iff detected, will override the results of the automatic detection.
 *
 * At this stage the memory configuration of the system is known to the
 * kernel but generic memory managment system is still entirely uninitialized.
@@ -465,25 +369,59 @@ static inline void bootmem_init(void)
 * initialization hook for anything else was introduced.
 */
-extern void plat_mem_setup(void);
+static int usermem __initdata = 0;
+static int __init early_parse_mem(char *p)
+{
+        unsigned long start, size;
+        /*
+         * If a user specifies memory size, we
+         * blow away any automatically generated
+         * size.
+         */
+        if (usermem == 0) {
+                boot_mem_map.nr_map = 0;
+                usermem = 1;
+        }
+        start = 0;
+        size = memparse(p, &p);
+        if (*p == '@')
+                start = memparse(p + 1, &p);
+        add_memory_region(start, size, BOOT_MEM_RAM);
+        return 0;
+}
+early_param("mem", early_parse_mem);
 static void __init arch_mem_init(char **cmdline_p)
 {
+        extern void plat_mem_setup(void);
        /* call board setup routine */
        plat_mem_setup();
+        printk("Determined physical RAM map:\n");
+        print_memory_map();
        strlcpy(command_line, arcs_cmdline, sizeof(command_line));
        strlcpy(saved_command_line, command_line, COMMAND_LINE_SIZE);
        *cmdline_p = command_line;
-        parse_cmdline_early();
+        parse_early_param();
+        if (usermem) {
+                printk("User-defined physical RAM map:\n");
+                print_memory_map();
+        }
        bootmem_init();
        sparse_init();
        paging_init();
 }
-static inline void resource_init(void)
+static void __init resource_init(void)
 {
        int i;
@@ -504,10 +442,10 @@ static inline void resource_init(void)
                start = boot_mem_map.map[i].addr;
                end = boot_mem_map.map[i].addr + boot_mem_map.map[i].size - 1;
-                if (start >= MAXMEM)
+                if (start >= HIGHMEM_START)
                        continue;
-                if (end >= MAXMEM)
+                if (end >= HIGHMEM_START)
-                        end = MAXMEM - 1;
+                        end = HIGHMEM_START - 1;
                res = alloc_bootmem(sizeof(struct resource));
                switch (boot_mem_map.map[i].type) {
@@ -536,9 +474,6 @@ static inline void resource_init(void)
        }
 }
-#undef MAXMEM
-#undef MAXMEM_PFN
 void __init setup_arch(char **cmdline_p)
 {
        cpu_probe();
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 6b4d9be31615..b9d358e05214 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -424,15 +424,11 @@ void do_signal(struct pt_regs *regs)
        if (!user_mode(regs))
                return;
-        if (try_to_freeze())
-                goto no_signal;
        if (test_thread_flag(TIF_RESTORE_SIGMASK))
                oldset = &current->saved_sigmask;
        else
                oldset = &current->blocked;
        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
        if (signr > 0) {
                /* Whee!  Actually deliver the signal.  */
@@ -446,9 +442,10 @@ void do_signal(struct pt_regs *regs)
                        if (test_thread_flag(TIF_RESTORE_SIGMASK))
                                clear_thread_flag(TIF_RESTORE_SIGMASK);
                }
+                return;
        }
-no_signal:
        /*
         * Who's code doesn't conform to the restartable syscall convention
         * dies here!!!  The li instruction, a single machine instruction,
@@ -466,6 +463,7 @@ no_signal:
                        regs->regs[7] = regs->regs[26];
                        regs->cp0_epc -= 4;
                }
+                regs->regs[0] = 0;      /* Don't deal with this again.  */
        }
        /*
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index f32a22997c3d..c86a5ddff050 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -815,9 +815,6 @@ void do_signal32(struct pt_regs *regs)
        if (!user_mode(regs))
                return;
-        if (try_to_freeze())
-                goto no_signal;
        if (test_thread_flag(TIF_RESTORE_SIGMASK))
                oldset = &current->saved_sigmask;
        else
@@ -836,9 +833,10 @@ void do_signal32(struct pt_regs *regs)
                        if (test_thread_flag(TIF_RESTORE_SIGMASK))
                                clear_thread_flag(TIF_RESTORE_SIGMASK);
                }
+                return;
        }
-no_signal:
        /*
         * Who's code doesn't conform to the restartable syscall convention
         * dies here!!!  The li instruction, a single machine instruction,
@@ -856,6 +854,7 @@ no_signal:
                        regs->regs[7] = regs->regs[26];
                        regs->cp0_epc -= 4;
                }
+                regs->regs[0] = 0;      /* Don't deal with this again.  */
        }
        /*
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 93429a4d3012..766253c44f3f 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -203,7 +203,7 @@ void plat_smp_setup(void)
                                write_vpe_c0_config( read_c0_config());
                                /* make sure there are no software interrupts pending */
-                                write_vpe_c0_cause(read_vpe_c0_cause() & ~(C_SW1|C_SW0));
+                                write_vpe_c0_cause(0);
                                /* Propagate Config7 */
                                write_vpe_c0_config7(read_c0_config7());
diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S
index 4cc3dea36612..76cb31d57482 100644
--- a/arch/mips/kernel/smtc-asm.S
+++ b/arch/mips/kernel/smtc-asm.S
@@ -8,7 +8,7 @@
 #include <asm/regdef.h>
 #include <asm/asmmacro.h>
 #include <asm/stackframe.h>
-#include <asm/stackframe.h>
+#include <asm/irqflags.h>
 /*
 * "Software Interrupt" linkage.
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 0721314db657..9951240cc3fd 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -263,7 +263,7 @@ asmlinkage int sys_olduname(struct oldold_utsname __user * name)
        return error;
 }
-void sys_set_thread_area(unsigned long addr)
+asmlinkage int sys_set_thread_area(unsigned long addr)
 {
        struct thread_info *ti = task_thread_info(current);
@@ -271,6 +271,8 @@ void sys_set_thread_area(unsigned long addr)
        /* If some future MIPS implementation has this register in hardware,
         * we will need to update it here (and in context switches).  */
+        return 0;
 }
 asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 954a198494ef..e51d8fd9a152 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -20,6 +20,7 @@
 #include <linux/spinlock.h>
 #include <linux/kallsyms.h>
 #include <linux/bootmem.h>
+#include <linux/interrupt.h>
 #include <asm/bootinfo.h>
 #include <asm/branch.h>
@@ -72,28 +73,68 @@ void (*board_nmi_handler_setup)(void);
 void (*board_ejtag_handler_setup)(void);
 void (*board_bind_eic_interrupt)(int irq, int regset);
-/*
- * These constant is for searching for possible module text segments.
+static void show_raw_backtrace(unsigned long reg29)
- * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
+{
- */
+        unsigned long *sp = (unsigned long *)reg29;
-#define MODULE_RANGE (8*1024*1024)
+        unsigned long addr;
+        printk("Call Trace:");
+#ifdef CONFIG_KALLSYMS
+        printk("\n");
+#endif
+        while (!kstack_end(sp)) {
+                addr = *sp++;
+                if (__kernel_text_address(addr))
+                        print_ip_sym(addr);
+        }
+        printk("\n");
+}
+#ifdef CONFIG_KALLSYMS
+static int raw_show_trace;
+static int __init set_raw_show_trace(char *str)
+{
+        raw_show_trace = 1;
+        return 1;
+}
+__setup("raw_show_trace", set_raw_show_trace);
+extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
+                                  unsigned long pc, unsigned long ra);
+static void show_backtrace(struct task_struct *task, struct pt_regs *regs)
+{
+        unsigned long sp = regs->regs[29];
+        unsigned long ra = regs->regs[31];
+        unsigned long pc = regs->cp0_epc;
+        if (raw_show_trace || !__kernel_text_address(pc)) {
+                show_raw_backtrace(sp);
+                return;
+        }
+        printk("Call Trace:\n");
+        do {
+                print_ip_sym(pc);
+                pc = unwind_stack(task, &sp, pc, ra);
+                ra = 0;
+        } while (pc);
+        printk("\n");
+}
+#else
+#define show_backtrace(task, r) show_raw_backtrace((r)->regs[29]);
+#endif
 /*
 * This routine abuses get_user()/put_user() to reference pointers
 * with at least a bit of error checking ...
 */
-void show_stack(struct task_struct *task, unsigned long *sp)
+static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
 {
        const int field = 2 * sizeof(unsigned long);
        long stackdata;
        int i;
+        unsigned long *sp = (unsigned long *)regs->regs[29];
-        if (!sp) {
-                if (task && task != current)
-                        sp = (unsigned long *) task->thread.reg29;
-                else
-                        sp = (unsigned long *) &sp;
-        }
        printk("Stack :");
        i = 0;
@@ -114,32 +155,48 @@ void show_stack(struct task_struct *task, unsigned long *sp)
                i++;
        }
        printk("\n");
+        show_backtrace(task, regs);
 }
-void show_trace(struct task_struct *task, unsigned long *stack)
+static __always_inline void prepare_frametrace(struct pt_regs *regs)
 {
-        const int field = 2 * sizeof(unsigned long);
+        __asm__ __volatile__(
-        unsigned long addr;
+                ".set push\n\t"
+                ".set noat\n\t"
-        if (!stack) {
+#ifdef CONFIG_64BIT
-                if (task && task != current)
+                "1: dla $1, 1b\n\t"
-                        stack = (unsigned long *) task->thread.reg29;
+                "sd $1, %0\n\t"
-                else
+                "sd $29, %1\n\t"
-                        stack = (unsigned long *) &stack;
+                "sd $31, %2\n\t"
-        }
+#else
+                "1: la $1, 1b\n\t"
-        printk("Call Trace:");
+                "sw $1, %0\n\t"
-#ifdef CONFIG_KALLSYMS
+                "sw $29, %1\n\t"
-        printk("\n");
+                "sw $31, %2\n\t"
 #endif
-        while (!kstack_end(stack)) {
+                ".set pop\n\t"
-                addr = *stack++;
+                : "=m" (regs->cp0_epc),
-                if (__kernel_text_address(addr)) {
+                "=m" (regs->regs[29]), "=m" (regs->regs[31])
-                        printk(" [<%0*lx>] ", field, addr);
+                : : "memory");
-                        print_symbol("%s\n", addr);
+}
+void show_stack(struct task_struct *task, unsigned long *sp)
+{
+        struct pt_regs regs;
+        if (sp) {
+                regs.regs[29] = (unsigned long)sp;
+                regs.regs[31] = 0;
+                regs.cp0_epc = 0;
+        } else {
+                if (task && task != current) {
+                        regs.regs[29] = task->thread.reg29;
+                        regs.regs[31] = 0;
+                        regs.cp0_epc = task->thread.reg31;
+                } else {
+                        prepare_frametrace(&regs);
                }
        }
-        printk("\n");
+        show_stacktrace(task, &regs);
 }
 /*
@@ -147,9 +204,15 @@ void show_trace(struct task_struct *task, unsigned long *stack)
 */
 void dump_stack(void)
 {
-        unsigned long stack;
+        struct pt_regs regs;
-        show_trace(current, &stack);
+        /*
+         * Remove any garbage that may be in regs (specially func
+         * addresses) to avoid show_raw_backtrace() to report them
+         */
+        memset(&regs, 0, sizeof(regs));
+        prepare_frametrace(&regs);
+        show_backtrace(current, &regs);
 }
 EXPORT_SYMBOL(dump_stack);
@@ -268,8 +331,7 @@ void show_registers(struct pt_regs *regs)
        print_modules();
        printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
                current->comm, current->pid, current_thread_info(), current);
-        show_stack(current, (long *) regs->regs[29]);
+        show_stacktrace(current, regs);
-        show_trace(current, (long *) regs->regs[29]);
        show_code((unsigned int *) regs->cp0_epc);
        printk("\n");
 }
@@ -292,6 +354,16 @@ NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
        printk("%s[#%d]:\n", str, ++die_counter);
        show_registers(regs);
        spin_unlock_irq(&die_lock);
+        if (in_interrupt())
+                panic("Fatal exception in interrupt");
+        if (panic_on_oops) {
+                printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
+                ssleep(5);
+                panic("Fatal exception");
+        }
        do_exit(SIGSEGV);
 }
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 9ee0ec2cd067..51ddd2166898 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -768,10 +768,16 @@ int vpe_run(struct vpe * v)
         */
        write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | v->minor);
+        write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA));
+        back_to_back_c0_hazard();
        /* Set up the XTC bit in vpeconf0 to point at our tc */
        write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC))
                               | (t->index << VPECONF0_XTC_SHIFT));
+        back_to_back_c0_hazard();
        /* enable this VPE */
        write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index fb25e0377f11..a020a3cb4f4b 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -1,6 +1,8 @@
 /*
- * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999, 2000, 2006  MIPS Technologies, Inc.
- * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ *      All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
 *
 * ########################################################################
 *
@@ -25,17 +27,20 @@
 */
 #include <linux/compiler.h>
 #include <linux/init.h>
+#include <linux/irq.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
-#include <asm/irq.h>
+#include <asm/gdb-stub.h>
 #include <asm/io.h>
+#include <asm/irq_cpu.h>
+#include <asm/msc01_ic.h>
 #include <asm/mips-boards/atlas.h>
 #include <asm/mips-boards/atlasint.h>
-#include <asm/gdb-stub.h>
+#include <asm/mips-boards/generic.h>
 static struct atlas_ictrl_regs *atlas_hw0_icregs;
@@ -47,13 +52,13 @@ static struct atlas_ictrl_regs *atlas_hw0_icregs;
 void disable_atlas_irq(unsigned int irq_nr)
 {
-        atlas_hw0_icregs->intrsten = (1 << (irq_nr-ATLASINT_BASE));
+        atlas_hw0_icregs->intrsten = 1 << (irq_nr - ATLAS_INT_BASE);
        iob();
 }
 void enable_atlas_irq(unsigned int irq_nr)
 {
-        atlas_hw0_icregs->intseten = (1 << (irq_nr-ATLASINT_BASE));
+        atlas_hw0_icregs->intseten = 1 << (irq_nr - ATLAS_INT_BASE);
        iob();
 }
@@ -107,7 +112,7 @@ static inline void atlas_hw0_irqdispatch(struct pt_regs *regs)
        if (unlikely(int_status == 0))
                return;
-        irq = ATLASINT_BASE + ls1bit32(int_status);
+        irq = ATLAS_INT_BASE + ls1bit32(int_status);
        DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
@@ -161,15 +166,14 @@ static inline unsigned int irq_ffs(unsigned int pending)
 }
 /*
- * IRQs on the Atlas board look basically (barring software IRQs which we
+ * IRQs on the Atlas board look basically like (all external interrupt
- * don't use at all and all external interrupt sources are combined together
+ * sources are combined together on hardware interrupt 0 (MIPS IRQ 2)):
- * on hardware interrupt 0 (MIPS IRQ 2)) like:
 *
- *      MIPS IRQ        Source
+ *      MIPS IRQ        Source
 *      --------        ------
- *             0        Software (ignored)
+ *             0        Software 0 (reschedule IPI on MT)
- *             1        Software (ignored)
+ *             1        Software 1 (remote call IPI on MT)
- *             2        Combined hardware interrupt (hw0)
+ *             2        Combined Atlas hardware interrupt (hw0)
 *             3        Hardware (ignored)
 *             4        Hardware (ignored)
 *             5        Hardware (ignored)
@@ -179,7 +183,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
 * We handle the IRQ according to _our_ priority which is:
 *
 * Highest ----     R4k Timer
- * Lowest  ----     Combined hardware interrupt
+ * Lowest  ----     Software 0
 *
 * then we just return, if multiple IRQs are pending then we will just take
 * another exception, big deal.
@@ -193,17 +197,19 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
        if (irq == MIPSCPU_INT_ATLAS)
                atlas_hw0_irqdispatch(regs);
-        else if (irq > 0)
+        else if (irq >= 0)
                do_IRQ(MIPSCPU_INT_BASE + irq, regs);
        else
                spurious_interrupt(regs);
 }
-void __init arch_init_irq(void)
+static inline void init_atlas_irqs (int base)
 {
        int i;
-        atlas_hw0_icregs = (struct atlas_ictrl_regs *)ioremap (ATLAS_ICTRL_REGS_BASE, sizeof(struct atlas_ictrl_regs *));
+        atlas_hw0_icregs = (struct atlas_ictrl_regs *)
+                           ioremap(ATLAS_ICTRL_REGS_BASE,
+                                   sizeof(struct atlas_ictrl_regs *));
        /*
         * Mask out all interrupt by writing "1" to all bit position in
@@ -211,7 +217,7 @@ void __init arch_init_irq(void)
         */
        atlas_hw0_icregs->intrsten = 0xffffffff;
-        for (i = ATLASINT_BASE; i <= ATLASINT_END; i++) {
+        for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) {
                irq_desc[i].status      = IRQ_DISABLED;
                irq_desc[i].action      = 0;
                irq_desc[i].depth       = 1;
@@ -219,3 +225,62 @@ void __init arch_init_irq(void)
                spin_lock_init(&irq_desc[i].lock);
        }
 }
+static struct irqaction atlasirq = {
+        .handler = no_action,
+        .name = "Atlas cascade"
+};
+msc_irqmap_t __initdata msc_irqmap[] = {
+        {MSC01C_INT_TMR,                MSC01_IRQ_EDGE, 0},
+        {MSC01C_INT_PCI,                MSC01_IRQ_LEVEL, 0},
+};
+int __initdata msc_nr_irqs = sizeof(msc_irqmap) / sizeof(*msc_irqmap);
+msc_irqmap_t __initdata msc_eicirqmap[] = {
+        {MSC01E_INT_SW0,                MSC01_IRQ_LEVEL, 0},
+        {MSC01E_INT_SW1,                MSC01_IRQ_LEVEL, 0},
+        {MSC01E_INT_ATLAS,              MSC01_IRQ_LEVEL, 0},
+        {MSC01E_INT_TMR,                MSC01_IRQ_EDGE, 0},
+        {MSC01E_INT_PCI,                MSC01_IRQ_LEVEL, 0},
+        {MSC01E_INT_PERFCTR,            MSC01_IRQ_LEVEL, 0},
+        {MSC01E_INT_CPUCTR,             MSC01_IRQ_LEVEL, 0}
+};
+int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap) / sizeof(*msc_eicirqmap);
+void __init arch_init_irq(void)
+{
+        init_atlas_irqs(ATLAS_INT_BASE);
+        if (!cpu_has_veic)
+                mips_cpu_irq_init(MIPSCPU_INT_BASE);
+        switch(mips_revision_corid) {
+        case MIPS_REVISION_CORID_CORE_MSC:
+        case MIPS_REVISION_CORID_CORE_FPGA2:
+        case MIPS_REVISION_CORID_CORE_FPGA3:
+        case MIPS_REVISION_CORID_CORE_24K:
+        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
+                if (cpu_has_veic)
+                        init_msc_irqs (MSC01E_INT_BASE,
+                                       msc_eicirqmap, msc_nr_eicirqs);
+                else
+                        init_msc_irqs (MSC01C_INT_BASE,
+                                       msc_irqmap, msc_nr_irqs);
+        }
+        if (cpu_has_veic) {
+                set_vi_handler (MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
+                setup_irq (MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
+        } else if (cpu_has_vint) {
+                set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
+#ifdef CONFIG_MIPS_MT_SMTC
+                setup_irq_smtc (MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS,
+                                &atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
+#else /* Not SMTC */
+                setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
+#endif /* CONFIG_MIPS_MT_SMTC */
+        } else
+                setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
+}
diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c
index 9871a91fdb07..0c6b0ce15028 100644
--- a/arch/mips/mips-boards/atlas/atlas_setup.c
+++ b/arch/mips/mips-boards/atlas/atlas_setup.c
@@ -77,7 +77,7 @@ static void __init serial_init(void)
 #else
        s.iobase = ATLAS_UART_REGS_BASE+3;
 #endif
-        s.irq = ATLASINT_UART;
+        s.irq = ATLAS_INT_UART;
        s.uartclk = ATLAS_BASE_BAUD * 16;
        s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ;
        s.iotype = UPIO_PORT;
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 557bf961f36a..8d15861fce61 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -41,8 +41,13 @@
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/prom.h>
+#ifdef CONFIG_MIPS_ATLAS
+#include <asm/mips-boards/atlasint.h>
+#endif
+#ifdef CONFIG_MIPS_MALTA
 #include <asm/mips-boards/maltaint.h>
-#include <asm/mc146818-time.h>
+#endif
 unsigned long cpu_khz;
@@ -92,10 +97,9 @@ extern int (*perf_irq)(struct pt_regs *regs);
 irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
        int cpu = smp_processor_id();
-        int r2 = cpu_has_mips_r2;
 #ifdef CONFIG_MIPS_MT_SMTC
-        /*
+        /*
         *  In an SMTC system, one Count/Compare set exists per VPE.
         *  Which TC within a VPE gets the interrupt is essentially
         *  random - we only know that it shouldn't be one with
@@ -108,29 +112,46 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
         *  the general MIPS timer_interrupt routine.
         */
+        int vpflags;
        /*
-         * DVPE is necessary so long as cross-VPE interrupts
+         * We could be here due to timer interrupt,
-         * are done via read-modify-write of Cause register.
+         * perf counter overflow, or both.
         */
-        int vpflags = dvpe();
+        if (read_c0_cause() & (1 << 26))
-        write_c0_compare (read_c0_count() - 1);
+                perf_irq(regs);
-        clear_c0_cause(CPUCTR_IMASKBIT);
-        evpe(vpflags);
-        if (cpu_data[cpu].vpe_id == 0) {
+        if (read_c0_cause() & (1 << 30)) {
-                timer_interrupt(irq, dev_id, regs);
+                /* If timer interrupt, make it de-assert */
-                scroll_display_message();
+                write_c0_compare (read_c0_count() - 1);
-        } else
-                write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
-        smtc_timer_broadcast(cpu_data[cpu].vpe_id);
-        if (cpu != 0)
                /*
-                 * Other CPUs should do profiling and process accounting
+                 * DVPE is necessary so long as cross-VPE interrupts
+                 * are done via read-modify-write of Cause register.
                 */
-                local_timer_interrupt(irq, dev_id, regs);
+                vpflags = dvpe();
+                clear_c0_cause(CPUCTR_IMASKBIT);
+                evpe(vpflags);
+                /*
+                 * There are things we only want to do once per tick
+                 * in an "MP" system.   One TC of each VPE will take
+                 * the actual timer interrupt.  The others will get
+                 * timer broadcast IPIs. We use whoever it is that takes
+                 * the tick on VPE 0 to run the full timer_interrupt().
+                 */
+                if (cpu_data[cpu].vpe_id == 0) {
+                                timer_interrupt(irq, NULL, regs);
+                                smtc_timer_broadcast(cpu_data[cpu].vpe_id);
+                                scroll_display_message();
+                } else {
+                        write_c0_compare(read_c0_count() +
+                                         (mips_hpt_frequency/HZ));
+                        local_timer_interrupt(irq, dev_id, regs);
+                        smtc_timer_broadcast(cpu_data[cpu].vpe_id);
+                }
+        }
 #else /* CONFIG_MIPS_MT_SMTC */
+        int r2 = cpu_has_mips_r2;
        if (cpu == 0) {
                /*
                 * CPU 0 handles the global timer interrupt job and process
@@ -161,9 +182,8 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
                 */
                local_timer_interrupt(irq, dev_id, regs);
        }
-#endif /* CONFIG_MIPS_MT_SMTC */
 out:
+#endif /* CONFIG_MIPS_MT_SMTC */
        return IRQ_HANDLED;
 }
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index bb041a22f20a..e1f35ef81145 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -335,7 +335,7 @@ void __init r3k_cache_init(void)
        flush_cache_mm = r3k_flush_cache_mm;
        flush_cache_range = r3k_flush_cache_range;
        flush_cache_page = r3k_flush_cache_page;
-        flush_icache_page = r3k_flush_icache_page;
+        __flush_icache_page = r3k_flush_icache_page;
        flush_icache_range = r3k_flush_icache_range;
        flush_cache_sigtramp = r3k_flush_cache_sigtramp;
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 069803f58f3b..0b2da53750bd 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -89,7 +89,7 @@ static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
        blast_dcache32_page(addr);
 }
-static inline void r4k_blast_dcache_page_setup(void)
+static void __init r4k_blast_dcache_page_setup(void)
 {
        unsigned long  dc_lsize = cpu_dcache_line_size();
@@ -103,7 +103,7 @@ static inline void r4k_blast_dcache_page_setup(void)
 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
-static inline void r4k_blast_dcache_page_indexed_setup(void)
+static void __init r4k_blast_dcache_page_indexed_setup(void)
 {
        unsigned long dc_lsize = cpu_dcache_line_size();
@@ -117,7 +117,7 @@ static inline void r4k_blast_dcache_page_indexed_setup(void)
 static void (* r4k_blast_dcache)(void);
-static inline void r4k_blast_dcache_setup(void)
+static void __init r4k_blast_dcache_setup(void)
 {
        unsigned long dc_lsize = cpu_dcache_line_size();
@@ -202,7 +202,7 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 static void (* r4k_blast_icache_page)(unsigned long addr);
-static inline void r4k_blast_icache_page_setup(void)
+static void __init r4k_blast_icache_page_setup(void)
 {
        unsigned long ic_lsize = cpu_icache_line_size();
@@ -219,7 +219,7 @@ static inline void r4k_blast_icache_page_setup(void)
 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
-static inline void r4k_blast_icache_page_indexed_setup(void)
+static void __init r4k_blast_icache_page_indexed_setup(void)
 {
        unsigned long ic_lsize = cpu_icache_line_size();
@@ -243,7 +243,7 @@ static inline void r4k_blast_icache_page_indexed_setup(void)
 static void (* r4k_blast_icache)(void);
-static inline void r4k_blast_icache_setup(void)
+static void __init r4k_blast_icache_setup(void)
 {
        unsigned long ic_lsize = cpu_icache_line_size();
@@ -264,7 +264,7 @@ static inline void r4k_blast_icache_setup(void)
 static void (* r4k_blast_scache_page)(unsigned long addr);
-static inline void r4k_blast_scache_page_setup(void)
+static void __init r4k_blast_scache_page_setup(void)
 {
        unsigned long sc_lsize = cpu_scache_line_size();
@@ -282,7 +282,7 @@ static inline void r4k_blast_scache_page_setup(void)
 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
-static inline void r4k_blast_scache_page_indexed_setup(void)
+static void __init r4k_blast_scache_page_indexed_setup(void)
 {
        unsigned long sc_lsize = cpu_scache_line_size();
@@ -300,7 +300,7 @@ static inline void r4k_blast_scache_page_indexed_setup(void)
 static void (* r4k_blast_scache)(void);
-static inline void r4k_blast_scache_setup(void)
+static void __init r4k_blast_scache_setup(void)
 {
        unsigned long sc_lsize = cpu_scache_line_size();
@@ -475,7 +475,7 @@ static inline void local_r4k_flush_cache_page(void *args)
                }
        }
        if (exec) {
-                if (cpu_has_vtag_icache) {
+                if (cpu_has_vtag_icache && mm == current->active_mm) {
                        int cpu = smp_processor_id();
                        if (cpu_context(cpu, mm) != 0)
@@ -599,7 +599,7 @@ static inline void local_r4k_flush_icache_page(void *args)
         * We're not sure of the virtual address(es) involved here, so
         * we have to flush the entire I-cache.
         */
-        if (cpu_has_vtag_icache) {
+        if (cpu_has_vtag_icache && vma->vm_mm == current->active_mm) {
                int cpu = smp_processor_id();
                if (cpu_context(cpu, vma->vm_mm) != 0)
@@ -1221,7 +1221,7 @@ void au1x00_fixup_config_od(void)
        }
 }
-static inline void coherency_setup(void)
+static void __init coherency_setup(void)
 {
        change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
@@ -1242,7 +1242,7 @@ static inline void coherency_setup(void)
                clear_c0_config(CONF_CU);
                break;
        /*
-         * We need to catch the ealry Alchemy SOCs with
+         * We need to catch the early Alchemy SOCs with
         * the write-only co_config.od bit and set it back to one...
         */
        case CPU_AU1000: /* rev. DA, HA, HB */
@@ -1291,7 +1291,7 @@ void __init r4k_cache_init(void)
        __flush_cache_all       = r4k___flush_cache_all;
        flush_cache_mm          = r4k_flush_cache_mm;
        flush_cache_page        = r4k_flush_cache_page;
-        flush_icache_page       = r4k_flush_icache_page;
+        __flush_icache_page     = r4k_flush_icache_page;
        flush_cache_range       = r4k_flush_cache_range;
        flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
index 2d71efb82ac5..16bad7c0a63f 100644
--- a/arch/mips/mm/c-sb1.c
+++ b/arch/mips/mm/c-sb1.c
@@ -155,6 +155,26 @@ static inline void __sb1_flush_icache_all(void)
 }
 /*
+ * Invalidate a range of the icache.  The addresses are virtual, and
+ * the cache is virtually indexed and tagged.  However, we don't
+ * necessarily have the right ASID context, so use index ops instead
+ * of hit ops.
+ */
+static inline void __sb1_flush_icache_range(unsigned long start,
+        unsigned long end)
+{
+        start &= ~(icache_line_size - 1);
+        end = (end + icache_line_size - 1) & ~(icache_line_size - 1);
+        while (start != end) {
+                cache_set_op(Index_Invalidate_I, start & icache_index_mask);
+                start += icache_line_size;
+        }
+        mispredict();
+        sync();
+}
+/*
 * Flush the icache for a given physical page.  Need to writeback the
 * dcache first, then invalidate the icache.  If the page isn't
 * executable, nothing is required.
@@ -173,8 +193,11 @@ static void local_sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long
        /*
         * Bumping the ASID is probably cheaper than the flush ...
         */
-        if (cpu_context(cpu, vma->vm_mm) != 0)
+        if (vma->vm_mm == current->active_mm) {
-                drop_mmu_context(vma->vm_mm, cpu);
+                if (cpu_context(cpu, vma->vm_mm) != 0)
+                        drop_mmu_context(vma->vm_mm, cpu);
+        } else
+                __sb1_flush_icache_range(addr, addr + PAGE_SIZE);
 }
 #ifdef CONFIG_SMP
@@ -210,26 +233,6 @@ void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsign
        __attribute__((alias("local_sb1_flush_cache_page")));
 #endif
-/*
- * Invalidate a range of the icache.  The addresses are virtual, and
- * the cache is virtually indexed and tagged.  However, we don't
- * necessarily have the right ASID context, so use index ops instead
- * of hit ops.
- */
-static inline void __sb1_flush_icache_range(unsigned long start,
-        unsigned long end)
-{
-        start &= ~(icache_line_size - 1);
-        end = (end + icache_line_size - 1) & ~(icache_line_size - 1);
-        while (start != end) {
-                cache_set_op(Index_Invalidate_I, start & icache_index_mask);
-                start += icache_line_size;
-        }
-        mispredict();
-        sync();
-}
 /*
 * Invalidate all caches on this CPU
@@ -326,9 +329,12 @@ static void local_sb1_flush_icache_page(struct vm_area_struct *vma,
         * If there's a context, bump the ASID (cheaper than a flush,
         * since we don't know VAs!)
         */
-        if (cpu_context(cpu, vma->vm_mm) != 0) {
+        if (vma->vm_mm == current->active_mm) {
-                drop_mmu_context(vma->vm_mm, cpu);
+                if (cpu_context(cpu, vma->vm_mm) != 0)
-        }
+                        drop_mmu_context(vma->vm_mm, cpu);
+        } else
+                __sb1_flush_icache_range(start, start + PAGE_SIZE);
 }
 #ifdef CONFIG_SMP
@@ -520,7 +526,7 @@ void sb1_cache_init(void)
        /* These routines are for Icache coherence with the Dcache */
        flush_icache_range = sb1_flush_icache_range;
-        flush_icache_page = sb1_flush_icache_page;
+        __flush_icache_page = sb1_flush_icache_page;
        flush_icache_all = __sb1_flush_icache_all; /* local only */
        /* This implies an Icache flush too, so can't be nop'ed */
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 5dfc9b1901f6..932a09d7ef84 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -382,7 +382,7 @@ void __init tx39_cache_init(void)
                flush_cache_mm          = (void *) tx39h_flush_icache_all;
                flush_cache_range       = (void *) tx39h_flush_icache_all;
                flush_cache_page        = (void *) tx39h_flush_icache_all;
-                flush_icache_page       = (void *) tx39h_flush_icache_all;
+                __flush_icache_page     = (void *) tx39h_flush_icache_all;
                flush_icache_range      = (void *) tx39h_flush_icache_all;
                flush_cache_sigtramp    = (void *) tx39h_flush_icache_all;
@@ -408,7 +408,7 @@ void __init tx39_cache_init(void)
                flush_cache_mm = tx39_flush_cache_mm;
                flush_cache_range = tx39_flush_cache_range;
                flush_cache_page = tx39_flush_cache_page;
-                flush_icache_page = tx39_flush_icache_page;
+                __flush_icache_page = tx39_flush_icache_page;
                flush_icache_range = tx39_flush_icache_range;
                flush_cache_sigtramp = tx39_flush_cache_sigtramp;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index ddd3a2de1d73..40c8b0235183 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -25,7 +25,7 @@ void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
 void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
        unsigned long pfn);
 void (*flush_icache_range)(unsigned long start, unsigned long end);
-void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page);
+void (*__flush_icache_page)(struct vm_area_struct *vma, struct page *page);
 /* MIPS specific cache operations */
 void (*flush_cache_sigtramp)(unsigned long addr);
@@ -70,6 +70,8 @@ void __flush_dcache_page(struct page *page)
        struct address_space *mapping = page_mapping(page);
        unsigned long addr;
+        if (PageHighMem(page))
+                return;
        if (mapping && !mapping_mapped(mapping)) {
                SetPageDcacheDirty(page);
                return;
@@ -91,16 +93,16 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address,
 {
        struct page *page;
        unsigned long pfn, addr;
+        int exec = (vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc;
        pfn = pte_pfn(pte);
-        if (pfn_valid(pfn) && (page = pfn_to_page(pfn), page_mapping(page)) &&
+        if (unlikely(!pfn_valid(pfn)))
-            Page_dcache_dirty(page)) {
+                return;
-                if (pages_do_alias((unsigned long)page_address(page),
+        page = pfn_to_page(pfn);
-                                   address & PAGE_MASK)) {
+        if (page_mapping(page) && Page_dcache_dirty(page)) {
-                        addr = (unsigned long) page_address(page);
+                addr = (unsigned long) page_address(page);
+                if (exec || pages_do_alias(addr, address & PAGE_MASK))
                        flush_data_cache_page(addr);
-                }
                ClearPageDcacheDirty(page);
        }
 }
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index e3a617224868..a4f8c45c4e8e 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -89,7 +89,7 @@ good_area:
                if (!(vma->vm_flags & VM_WRITE))
                        goto bad_area;
        } else {
-                if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
+                if (!(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC)))
                        goto bad_area;
        }
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 2cde1b772443..2e0e21ef433e 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -26,11 +26,6 @@ extern void build_tlb_refill_handler(void);
 */
 #define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
-/* CP0 hazard avoidance. */
-#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
-                                     "nop; nop; nop; nop; nop; nop;\n\t" \
-                                     ".set reorder\n\t")
 /* Atomicity and interruptability */
 #ifdef CONFIG_MIPS_MT_SMTC
@@ -126,7 +121,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
                                start += (PAGE_SIZE << 1);
                                mtc0_tlbw_hazard();
                                tlb_probe();
-                                BARRIER;
+                                tlb_probe_hazard();
                                idx = read_c0_index();
                                write_c0_entrylo0(0);
                                write_c0_entrylo1(0);
@@ -168,7 +163,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
                        start += (PAGE_SIZE << 1);
                        mtc0_tlbw_hazard();
                        tlb_probe();
-                        BARRIER;
+                        tlb_probe_hazard();
                        idx = read_c0_index();
                        write_c0_entrylo0(0);
                        write_c0_entrylo1(0);
@@ -202,7 +197,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
                write_c0_entryhi(page | newpid);
                mtc0_tlbw_hazard();
                tlb_probe();
-                BARRIER;
+                tlb_probe_hazard();
                idx = read_c0_index();
                write_c0_entrylo0(0);
                write_c0_entrylo1(0);
@@ -235,7 +230,7 @@ void local_flush_tlb_one(unsigned long page)
        write_c0_entryhi(page);
        mtc0_tlbw_hazard();
        tlb_probe();
-        BARRIER;
+        tlb_probe_hazard();
        idx = read_c0_index();
        write_c0_entrylo0(0);
        write_c0_entrylo1(0);
@@ -279,7 +274,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
        pgdp = pgd_offset(vma->vm_mm, address);
        mtc0_tlbw_hazard();
        tlb_probe();
-        BARRIER;
+        tlb_probe_hazard();
        pudp = pud_offset(pgdp, address);
        pmdp = pmd_offset(pudp, address);
        idx = read_c0_index();
@@ -320,7 +315,7 @@ static void r4k_update_mmu_cache_hwbug(struct vm_area_struct * vma,
        pgdp = pgd_offset(vma->vm_mm, address);
        mtc0_tlbw_hazard();
        tlb_probe();
-        BARRIER;
+        tlb_probe_hazard();
        pmdp = pmd_offset(pgdp, address);
        idx = read_c0_index();
        ptep = pte_offset_map(pmdp, address);
@@ -351,7 +346,7 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
        wired = read_c0_wired();
        write_c0_wired(wired + 1);
        write_c0_index(wired);
-        BARRIER;
+        tlbw_use_hazard();      /* What is the hazard here? */
        write_c0_pagemask(pagemask);
        write_c0_entryhi(entryhi);
        write_c0_entrylo0(entrylo0);
@@ -361,7 +356,7 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
        tlbw_use_hazard();
        write_c0_entryhi(old_ctx);
-        BARRIER;
+        tlbw_use_hazard();      /* What is the hazard here? */
        write_c0_pagemask(old_pagemask);
        local_flush_tlb_all();
        EXIT_CRITICAL(flags);
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 35d5927706ea..edefa97b2330 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -11,7 +11,6 @@ obj-$(CONFIG_ITE_BOARD_GEN)	+= ops-it8172.o
 obj-$(CONFIG_MIPS_BONITO64)     += ops-bonito64.o
 obj-$(CONFIG_MIPS_GT64111)      += ops-gt64111.o
 obj-$(CONFIG_MIPS_GT64120)      += ops-gt64120.o
-obj-$(CONFIG_MIPS_GT96100)      += ops-gt96100.o
 obj-$(CONFIG_PCI_MARVELL)       += ops-marvell.o
 obj-$(CONFIG_MIPS_MSC)          += ops-msc.o
 obj-$(CONFIG_MIPS_NILE4)        += ops-nile4.o
@@ -28,8 +27,7 @@ obj-$(CONFIG_DDB5477)		+= fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
 obj-$(CONFIG_LASAT)             += pci-lasat.o
 obj-$(CONFIG_MIPS_ATLAS)        += fixup-atlas.o
 obj-$(CONFIG_MIPS_COBALT)       += fixup-cobalt.o
-obj-$(CONFIG_MIPS_EV96100)      += fixup-ev64120.o
+obj-$(CONFIG_MIPS_EV64120)      += fixup-ev64120.o
-obj-$(CONFIG_MIPS_EV96100)      += fixup-ev96100.o pci-ev96100.o
 obj-$(CONFIG_MIPS_ITE8172)      += fixup-ite8172g.o
 obj-$(CONFIG_MIPS_IVR)          += fixup-ivr.o
 obj-$(CONFIG_SOC_AU1500)        += fixup-au1000.o ops-au1000.o
diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c
index 439510af3037..c6cd6e9cdfbc 100644
--- a/arch/mips/pci/fixup-atlas.c
+++ b/arch/mips/pci/fixup-atlas.c
@@ -21,16 +21,16 @@
 #include <asm/mips-boards/atlasint.h>
-#define PCIA            ATLASINT_PCIA
+#define PCIA            ATLAS_INT_PCIA
-#define PCIB            ATLASINT_PCIB
+#define PCIB            ATLAS_INT_PCIB
-#define PCIC            ATLASINT_PCIC
+#define PCIC            ATLAS_INT_PCIC
-#define PCID            ATLASINT_PCID
+#define PCID            ATLAS_INT_PCID
-#define INTA            ATLASINT_INTA
+#define INTA            ATLAS_INT_INTA
-#define INTB            ATLASINT_INTB
+#define INTB            ATLAS_INT_INTB
-#define ETH             ATLASINT_ETH
+#define ETH             ATLAS_INT_ETH
-#define INTC            ATLASINT_INTC
+#define INTC            ATLAS_INT_INTC
-#define SCSI            ATLASINT_SCSI
+#define SCSI            ATLAS_INT_SCSI
-#define INTD            ATLASINT_INTD
+#define INTD            ATLAS_INT_INTD
 static char irq_tab[][5] __initdata = {
        /*      INTA    INTB    INTC    INTD */
diff --git a/arch/mips/pci/fixup-ev96100.c b/arch/mips/pci/fixup-ev96100.c
deleted file mode 100644
index e2bc977b6d58..000000000000
--- a/arch/mips/pci/fixup-ev96100.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      EV96100 Board specific pci fixups.
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@mvista.com or source@mvista.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-static char irq_tab_ev96100[][5] __initdata = {
- [8] = { 0, 5, 5, 5, 5 },
- [9] = { 0, 2, 2, 2, 2 }
-};
-int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-{
-        return irq_tab_ev96100[slot][pin];
-}
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-        return 0;
-}
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
index 0c0c1e6519f9..8ae46481fcb7 100644
--- a/arch/mips/pci/ops-au1000.c
+++ b/arch/mips/pci/ops-au1000.c
@@ -110,7 +110,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
        if (first_cfg) {
                /* reserve a wired entry for pci config accesses */
                first_cfg = 0;
-                pci_cfg_vm = get_vm_area(0x2000, 0);
+                pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
                if (!pci_cfg_vm)
                        panic (KERN_ERR "PCI unable to get vm area\n");
                pci_cfg_wired_entry = read_c0_wired();
diff --git a/arch/mips/pci/ops-gt96100.c b/arch/mips/pci/ops-gt96100.c
deleted file mode 100644
index 9e4ea6627e21..000000000000
--- a/arch/mips/pci/ops-gt96100.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      Galileo EV96100 board specific pci support.
- *
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@mvista.com or source@mvista.com
- *
- * This file was derived from Carsten Langgaard's
- * arch/mips/mips-boards/generic/pci.c
- *
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/delay.h>
-#include <asm/gt64120.h>
-#include <asm/galileo-boards/ev96100.h>
-#define PCI_ACCESS_READ  0
-#define PCI_ACCESS_WRITE 1
-static int static gt96100_config_access(unsigned char access_type,
-        struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
-{
-        unsigned char bus = bus->number;
-        u32 intr;
-        /*
-         * Because of a bug in the galileo (for slot 31).
-         */
-        if (bus == 0 && devfn >= PCI_DEVFN(31, 0))
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        /* Clear cause register bits */
-        GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
-                                     GT_INTRCAUSE_TARABORT0_BIT));
-        /* Setup address */
-        GT_WRITE(GT_PCI0_CFGADDR_OFS,
-                 (bus << GT_PCI0_CFGADDR_BUSNUM_SHF) |
-                 (devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
-                 ((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
-                 GT_PCI0_CFGADDR_CONFIGEN_BIT);
-        udelay(2);
-        if (access_type == PCI_ACCESS_WRITE) {
-                if (devfn != 0)
-                        *data = le32_to_cpu(*data);
-                GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
-        } else {
-                *data = GT_READ(GT_PCI0_CFGDATA_OFS);
-                if (devfn != 0)
-                        *data = le32_to_cpu(*data);
-        }
-        udelay(2);
-        /* Check for master or target abort */
-        intr = GT_READ(GT_INTRCAUSE_OFS);
-        if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {
-                /* Error occured */
-                /* Clear bits */
-                GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
-                                             GT_INTRCAUSE_TARABORT0_BIT));
-                return -1;
-        }
-        return 0;
-}
-/*
- * We can't address 8 and 16 bit words directly.  Instead we have to
- * read/write a 32bit word and mask/modify the data we actually want.
- */
-static int gt96100_pcibios_read(struct pci_bus *bus, unsigned int devfn,
-        int where, int size, u32 * val)
-{
-        u32 data = 0;
-        if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        switch (size) {
-        case 1:
-                *val = (data >> ((where & 3) << 3)) & 0xff;
-                break;
-        case 2:
-                *val = (data >> ((where & 3) << 3)) & 0xffff;
-                break;
-        case 4:
-                *val = data;
-                break;
-        }
-        return PCIBIOS_SUCCESSFUL;
-}
-static int gt96100_pcibios_write(struct pci_bus *bus, unsigned int devfn,
-        int where, int size, u32 val)
-{
-        u32 data = 0;
-        switch (size) {
-        case 1:
-                if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
-                        return -1;
-                data = (data & ~(0xff << ((where & 3) << 3))) |
-                       (val << ((where & 3) << 3));
-                if (gt96100_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
-                        return -1;
-                return PCIBIOS_SUCCESSFUL;
-        case 2:
-                if (gt96100_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
-                        return -1;
-                data = (data & ~(0xffff << ((where & 3) << 3))) |
-                       (val << ((where & 3) << 3));
-                if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &data))
-                        return -1;
-                return PCIBIOS_SUCCESSFUL;
-        case 4:
-                if (gt96100_config_access(PCI_ACCESS_WRITE, dev, where, &val))
-                        return -1;
-                return PCIBIOS_SUCCESSFUL;
-        }
-}
-struct pci_ops gt96100_pci_ops = {
-        .read   = gt96100_pcibios_read,
-        .write  = gt96100_pcibios_write
-};
diff --git a/arch/mips/pci/pci-ev96100.c b/arch/mips/pci/pci-ev96100.c
deleted file mode 100644
index f9457ea00def..000000000000
--- a/arch/mips/pci/pci-ev96100.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              ppopov@mvista.com or source@mvista.com
- *
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-static struct resource pci_io_resource = {
-        .name   = "io pci IO space",
-        .start  = 0x10000000,
-        .end    = 0x11ffffff,
-        .flags  = IORESOURCE_IO
-};
-static struct resource pci_mem_resource = {
-        .name   = "ext pci memory space",
-        .start  = 0x12000000,
-        .end    = 0x13ffffff,
-        .flags  = IORESOURCE_MEM
-};
-extern struct pci_ops gt96100_pci_ops;
-struct pci_controller ev96100_controller = {
-        .pci_ops        = &gt96100_pci_ops,
-        .io_resource    = &pci_io_resource,
-        .mem_resource   = &pci_mem_resource,
-};
-static void ev96100_pci_init(void)
-{
-        register_pci_controller(&ev96100_controller);
-}
-arch_initcall(ev96100_pci_init);
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 80eb9af9ecdf..405ce0152739 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -16,8 +16,6 @@
 #include <asm/sn/intr.h>
 #include <asm/sn/sn0/hub.h>
-extern unsigned int allocate_irqno(void);
 /*
 * Max #PCI busses we can handle; ie, max #PCI bridges.
 */
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index ed325f0ab28a..a0222fa4416c 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -469,21 +469,6 @@ void bcm1480_kgdb_interrupt(struct pt_regs *regs)
 #endif  /* CONFIG_KGDB */
-static inline int dclz(unsigned long long x)
-{
-        int lz;
-        __asm__ (
-        "       .set    push                                            \n"
-        "       .set    mips64                                          \n"
-        "       dclz    %0, %1                                          \n"
-        "       .set    pop                                             \n"
-        : "=r" (lz)
-        : "r" (x));
-        return lz;
-}
 extern void bcm1480_timer_interrupt(struct pt_regs *regs);
 extern void bcm1480_mailbox_interrupt(struct pt_regs *regs);
 extern void bcm1480_kgdb_interrupt(struct pt_regs *regs);
@@ -536,9 +521,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
                if (mask_h) {
                        if (mask_h ^ 1)
-                                do_IRQ(63 - dclz(mask_h), regs);
+                                do_IRQ(fls64(mask_h) - 1, regs);
                        else
-                                do_IRQ(127 - dclz(mask_l), regs);
+                                do_IRQ(63 + fls64(mask_l), regs);
                }
        }
 }
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 1de71adec6c6..a451b4c7732d 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -419,21 +419,6 @@ static void sb1250_kgdb_interrupt(struct pt_regs *regs)
 #endif  /* CONFIG_KGDB */
-static inline int dclz(unsigned long long x)
-{
-        int lz;
-        __asm__ (
-        "       .set    push                                            \n"
-        "       .set    mips64                                          \n"
-        "       dclz    %0, %1                                          \n"
-        "       .set    pop                                             \n"
-        : "=r" (lz)
-        : "r" (x));
-        return lz;
-}
 extern void sb1250_timer_interrupt(struct pt_regs *regs);
 extern void sb1250_mailbox_interrupt(struct pt_regs *regs);
 extern void sb1250_kgdb_interrupt(struct pt_regs *regs);
@@ -490,6 +475,6 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
                mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
                                              R_IMR_INTERRUPT_STATUS_BASE)));
                if (mask)
-                        do_IRQ(63 - dclz(mask), regs);
+                        do_IRQ(fls64(mask) - 1, regs);
        }
 }
diff --git a/include/asm-mips/Kbuild b/include/asm-mips/Kbuild
index c68e1680da01..7897f05e3165 100644
--- a/include/asm-mips/Kbuild
+++ b/include/asm-mips/Kbuild
@@ -1 +1,3 @@
 include include/asm-generic/Kbuild.asm
+header-y += cachectl.h sgidefs.h sysmips.h
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 3b745e76f429..78c35ec46362 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -112,8 +112,7 @@
 * Valid machtype for group GALILEO
 */
 #define MACH_GROUP_GALILEO     11       /* Galileo Eval Boards          */
-#define  MACH_EV96100           0       /* EV96100 */
+#define  MACH_EV64120A          0       /* EV64120A */
-#define  MACH_EV64120A          1       /* EV64120A */
 /*
 * Valid machtype for group MOMENCO
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
index 47bc8f6c20d2..36416fdfcf68 100644
--- a/include/asm-mips/cacheflush.h
+++ b/include/asm-mips/cacheflush.h
@@ -21,7 +21,6 @@
 *  - flush_cache_range(vma, start, end) flushes a range of pages
 *  - flush_icache_range(start, end) flush a range of instructions
 *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
- *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
 *
 * MIPS specific flush operations:
 *
@@ -39,7 +38,7 @@ extern void __flush_dcache_page(struct page *page);
 static inline void flush_dcache_page(struct page *page)
 {
-        if (cpu_has_dc_aliases)
+        if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
                __flush_dcache_page(page);
 }
@@ -47,8 +46,13 @@ static inline void flush_dcache_page(struct page *page)
 #define flush_dcache_mmap_lock(mapping)         do { } while (0)
 #define flush_dcache_mmap_unlock(mapping)       do { } while (0)
-extern void (*flush_icache_page)(struct vm_area_struct *vma,
+extern void (*__flush_icache_page)(struct vm_area_struct *vma,
        struct page *page);
+static inline void flush_icache_page(struct vm_area_struct *vma,
+        struct page *page)
+{
+}
 extern void (*flush_icache_range)(unsigned long start, unsigned long end);
 #define flush_cache_vmap(start, end)            flush_cache_all()
 #define flush_cache_vunmap(start, end)          flush_cache_all()
@@ -60,7 +64,7 @@ static inline void copy_to_user_page(struct vm_area_struct *vma,
        if (cpu_has_dc_aliases)
                flush_cache_page(vma, vaddr, page_to_pfn(page));
        memcpy(dst, src, len);
-        flush_icache_page(vma, page);
+        __flush_icache_page(vma, page);
 }
 static inline void copy_from_user_page(struct vm_area_struct *vma,
diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h
index 787220e6c1fc..00a50ec1c19f 100644
--- a/include/asm-mips/fcntl.h
+++ b/include/asm-mips/fcntl.h
@@ -25,8 +25,6 @@
 #define F_SETOWN        24      /*  for sockets. */
 #define F_GETOWN        23      /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
 #ifndef __mips64
 #define F_GETLK64       33      /*  using 'struct flock64' */
diff --git a/include/asm-mips/galileo-boards/gt96100.h b/include/asm-mips/galileo-boards/gt96100.h
deleted file mode 100644
index aabd1b629c19..000000000000
--- a/include/asm-mips/galileo-boards/gt96100.h
+++ /dev/null
@@ -1,427 +0,0 @@
-/*
- * Copyright 2000 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *              stevel@mvista.com or source@mvista.com
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Register offsets of the MIPS GT96100 Advanced Communication Controller.
- */
-#ifndef _GT96100_H
-#define _GT96100_H
-/*
- * Galileo GT96100 internal register base.
- */
-#define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000))
-#define GT96100_WRITE(ofs, data) \
-    *(volatile u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data)
-#define GT96100_READ(ofs) \
-    le32_to_cpu(*(volatile u32 *)(MIPS_GT96100_BASE+ofs))
-#define GT96100_ETH_IO_SIZE 0x4000
-/************************************************************************
- *  Register offset addresses follow
- ************************************************************************/
-/* CPU Interface Control Registers */
-#define GT96100_CPU_INTERF_CONFIG 0x000000
-/* Ethernet Ports */
-#define GT96100_ETH_PHY_ADDR_REG             0x080800
-#define GT96100_ETH_SMI_REG                  0x080810
-/*
-  These are offsets to port 0 registers. Add GT96100_ETH_IO_SIZE to
-  get offsets to port 1 registers.
-*/
-#define GT96100_ETH_PORT_CONFIG          0x084800
-#define GT96100_ETH_PORT_CONFIG_EXT      0x084808
-#define GT96100_ETH_PORT_COMM            0x084810
-#define GT96100_ETH_PORT_STATUS          0x084818
-#define GT96100_ETH_SER_PARAM            0x084820
-#define GT96100_ETH_HASH_TBL_PTR         0x084828
-#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_L    0x084830
-#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_H    0x084838
-#define GT96100_ETH_SDMA_CONFIG          0x084840
-#define GT96100_ETH_SDMA_COMM            0x084848
-#define GT96100_ETH_INT_CAUSE            0x084850
-#define GT96100_ETH_INT_MASK             0x084858
-#define GT96100_ETH_1ST_RX_DESC_PTR0         0x084880
-#define GT96100_ETH_1ST_RX_DESC_PTR1         0x084884
-#define GT96100_ETH_1ST_RX_DESC_PTR2         0x084888
-#define GT96100_ETH_1ST_RX_DESC_PTR3         0x08488C
-#define GT96100_ETH_CURR_RX_DESC_PTR0        0x0848A0
-#define GT96100_ETH_CURR_RX_DESC_PTR1        0x0848A4
-#define GT96100_ETH_CURR_RX_DESC_PTR2        0x0848A8
-#define GT96100_ETH_CURR_RX_DESC_PTR3        0x0848AC
-#define GT96100_ETH_CURR_TX_DESC_PTR0        0x0848E0
-#define GT96100_ETH_CURR_TX_DESC_PTR1        0x0848E4
-#define GT96100_ETH_MIB_COUNT_BASE           0x085800
-/* SDMAs */
-#define GT96100_SDMA_GROUP_CONFIG           0x101AF0
-/* SDMA Group 0 */
-#define GT96100_SDMA_G0_CHAN0_CONFIG        0x000900
-#define GT96100_SDMA_G0_CHAN0_COMM          0x000908
-#define GT96100_SDMA_G0_CHAN0_RX_DESC_BASE      0x008900
-#define GT96100_SDMA_G0_CHAN0_CURR_RX_DESC_PTR  0x008910
-#define GT96100_SDMA_G0_CHAN0_TX_DESC_BASE      0x00C900
-#define GT96100_SDMA_G0_CHAN0_CURR_TX_DESC_PTR  0x00C910
-#define GT96100_SDMA_G0_CHAN0_1ST_TX_DESC_PTR   0x00C914
-#define GT96100_SDMA_G0_CHAN1_CONFIG        0x010900
-#define GT96100_SDMA_G0_CHAN1_COMM          0x010908
-#define GT96100_SDMA_G0_CHAN1_RX_DESC_BASE      0x018900
-#define GT96100_SDMA_G0_CHAN1_CURR_RX_DESC_PTR  0x018910
-#define GT96100_SDMA_G0_CHAN1_TX_DESC_BASE      0x01C900
-#define GT96100_SDMA_G0_CHAN1_CURR_TX_DESC_PTR  0x01C910
-#define GT96100_SDMA_G0_CHAN1_1ST_TX_DESC_PTR   0x01C914
-#define GT96100_SDMA_G0_CHAN2_CONFIG        0x020900
-#define GT96100_SDMA_G0_CHAN2_COMM          0x020908
-#define GT96100_SDMA_G0_CHAN2_RX_DESC_BASE      0x028900
-#define GT96100_SDMA_G0_CHAN2_CURR_RX_DESC_PTR  0x028910
-#define GT96100_SDMA_G0_CHAN2_TX_DESC_BASE      0x02C900
-#define GT96100_SDMA_G0_CHAN2_CURR_TX_DESC_PTR  0x02C910
-#define GT96100_SDMA_G0_CHAN2_1ST_TX_DESC_PTR   0x02C914
-#define GT96100_SDMA_G0_CHAN3_CONFIG        0x030900
-#define GT96100_SDMA_G0_CHAN3_COMM          0x030908
-#define GT96100_SDMA_G0_CHAN3_RX_DESC_BASE      0x038900
-#define GT96100_SDMA_G0_CHAN3_CURR_RX_DESC_PTR  0x038910
-#define GT96100_SDMA_G0_CHAN3_TX_DESC_BASE      0x03C900
-#define GT96100_SDMA_G0_CHAN3_CURR_TX_DESC_PTR  0x03C910
-#define GT96100_SDMA_G0_CHAN3_1ST_TX_DESC_PTR   0x03C914
-#define GT96100_SDMA_G0_CHAN4_CONFIG        0x040900
-#define GT96100_SDMA_G0_CHAN4_COMM          0x040908
-#define GT96100_SDMA_G0_CHAN4_RX_DESC_BASE      0x048900
-#define GT96100_SDMA_G0_CHAN4_CURR_RX_DESC_PTR  0x048910
-#define GT96100_SDMA_G0_CHAN4_TX_DESC_BASE      0x04C900
-#define GT96100_SDMA_G0_CHAN4_CURR_TX_DESC_PTR  0x04C910
-#define GT96100_SDMA_G0_CHAN4_1ST_TX_DESC_PTR   0x04C914
-#define GT96100_SDMA_G0_CHAN5_CONFIG        0x050900
-#define GT96100_SDMA_G0_CHAN5_COMM          0x050908
-#define GT96100_SDMA_G0_CHAN5_RX_DESC_BASE      0x058900
-#define GT96100_SDMA_G0_CHAN5_CURR_RX_DESC_PTR  0x058910
-#define GT96100_SDMA_G0_CHAN5_TX_DESC_BASE      0x05C900
-#define GT96100_SDMA_G0_CHAN5_CURR_TX_DESC_PTR  0x05C910
-#define GT96100_SDMA_G0_CHAN5_1ST_TX_DESC_PTR   0x05C914
-#define GT96100_SDMA_G0_CHAN6_CONFIG        0x060900
-#define GT96100_SDMA_G0_CHAN6_COMM          0x060908
-#define GT96100_SDMA_G0_CHAN6_RX_DESC_BASE      0x068900
-#define GT96100_SDMA_G0_CHAN6_CURR_RX_DESC_PTR  0x068910
-#define GT96100_SDMA_G0_CHAN6_TX_DESC_BASE      0x06C900
-#define GT96100_SDMA_G0_CHAN6_CURR_TX_DESC_PTR  0x06C910
-#define GT96100_SDMA_G0_CHAN6_1ST_TX_DESC_PTR   0x06C914
-#define GT96100_SDMA_G0_CHAN7_CONFIG        0x070900
-#define GT96100_SDMA_G0_CHAN7_COMM          0x070908
-#define GT96100_SDMA_G0_CHAN7_RX_DESC_BASE      0x078900
-#define GT96100_SDMA_G0_CHAN7_CURR_RX_DESC_PTR  0x078910
-#define GT96100_SDMA_G0_CHAN7_TX_DESC_BASE      0x07C900
-#define GT96100_SDMA_G0_CHAN7_CURR_TX_DESC_PTR  0x07C910
-#define GT96100_SDMA_G0_CHAN7_1ST_TX_DESC_PTR   0x07C914
-/* SDMA Group 1 */
-#define GT96100_SDMA_G1_CHAN0_CONFIG        0x100900
-#define GT96100_SDMA_G1_CHAN0_COMM          0x100908
-#define GT96100_SDMA_G1_CHAN0_RX_DESC_BASE      0x108900
-#define GT96100_SDMA_G1_CHAN0_CURR_RX_DESC_PTR  0x108910
-#define GT96100_SDMA_G1_CHAN0_TX_DESC_BASE      0x10C900
-#define GT96100_SDMA_G1_CHAN0_CURR_TX_DESC_PTR  0x10C910
-#define GT96100_SDMA_G1_CHAN0_1ST_TX_DESC_PTR   0x10C914
-#define GT96100_SDMA_G1_CHAN1_CONFIG        0x110900
-#define GT96100_SDMA_G1_CHAN1_COMM          0x110908
-#define GT96100_SDMA_G1_CHAN1_RX_DESC_BASE      0x118900
-#define GT96100_SDMA_G1_CHAN1_CURR_RX_DESC_PTR  0x118910
-#define GT96100_SDMA_G1_CHAN1_TX_DESC_BASE      0x11C900
-#define GT96100_SDMA_G1_CHAN1_CURR_TX_DESC_PTR  0x11C910
-#define GT96100_SDMA_G1_CHAN1_1ST_TX_DESC_PTR   0x11C914
-#define GT96100_SDMA_G1_CHAN2_CONFIG        0x120900
-#define GT96100_SDMA_G1_CHAN2_COMM          0x120908
-#define GT96100_SDMA_G1_CHAN2_RX_DESC_BASE      0x128900
-#define GT96100_SDMA_G1_CHAN2_CURR_RX_DESC_PTR  0x128910
-#define GT96100_SDMA_G1_CHAN2_TX_DESC_BASE      0x12C900
-#define GT96100_SDMA_G1_CHAN2_CURR_TX_DESC_PTR  0x12C910
-#define GT96100_SDMA_G1_CHAN2_1ST_TX_DESC_PTR   0x12C914
-#define GT96100_SDMA_G1_CHAN3_CONFIG        0x130900
-#define GT96100_SDMA_G1_CHAN3_COMM          0x130908
-#define GT96100_SDMA_G1_CHAN3_RX_DESC_BASE      0x138900
-#define GT96100_SDMA_G1_CHAN3_CURR_RX_DESC_PTR  0x138910
-#define GT96100_SDMA_G1_CHAN3_TX_DESC_BASE      0x13C900
-#define GT96100_SDMA_G1_CHAN3_CURR_TX_DESC_PTR  0x13C910
-#define GT96100_SDMA_G1_CHAN3_1ST_TX_DESC_PTR   0x13C914
-#define GT96100_SDMA_G1_CHAN4_CONFIG        0x140900
-#define GT96100_SDMA_G1_CHAN4_COMM          0x140908
-#define GT96100_SDMA_G1_CHAN4_RX_DESC_BASE      0x148900
-#define GT96100_SDMA_G1_CHAN4_CURR_RX_DESC_PTR  0x148910
-#define GT96100_SDMA_G1_CHAN4_TX_DESC_BASE      0x14C900
-#define GT96100_SDMA_G1_CHAN4_CURR_TX_DESC_PTR  0x14C910
-#define GT96100_SDMA_G1_CHAN4_1ST_TX_DESC_PTR   0x14C914
-#define GT96100_SDMA_G1_CHAN5_CONFIG        0x150900
-#define GT96100_SDMA_G1_CHAN5_COMM          0x150908
-#define GT96100_SDMA_G1_CHAN5_RX_DESC_BASE      0x158900
-#define GT96100_SDMA_G1_CHAN5_CURR_RX_DESC_PTR  0x158910
-#define GT96100_SDMA_G1_CHAN5_TX_DESC_BASE      0x15C900
-#define GT96100_SDMA_G1_CHAN5_CURR_TX_DESC_PTR  0x15C910
-#define GT96100_SDMA_G1_CHAN5_1ST_TX_DESC_PTR   0x15C914
-#define GT96100_SDMA_G1_CHAN6_CONFIG        0x160900
-#define GT96100_SDMA_G1_CHAN6_COMM          0x160908
-#define GT96100_SDMA_G1_CHAN6_RX_DESC_BASE      0x168900
-#define GT96100_SDMA_G1_CHAN6_CURR_RX_DESC_PTR  0x168910
-#define GT96100_SDMA_G1_CHAN6_TX_DESC_BASE      0x16C900
-#define GT96100_SDMA_G1_CHAN6_CURR_TX_DESC_PTR  0x16C910
-#define GT96100_SDMA_G1_CHAN6_1ST_TX_DESC_PTR   0x16C914
-#define GT96100_SDMA_G1_CHAN7_CONFIG        0x170900
-#define GT96100_SDMA_G1_CHAN7_COMM          0x170908
-#define GT96100_SDMA_G1_CHAN7_RX_DESC_BASE      0x178900
-#define GT96100_SDMA_G1_CHAN7_CURR_RX_DESC_PTR  0x178910
-#define GT96100_SDMA_G1_CHAN7_TX_DESC_BASE      0x17C900
-#define GT96100_SDMA_G1_CHAN7_CURR_TX_DESC_PTR  0x17C910
-#define GT96100_SDMA_G1_CHAN7_1ST_TX_DESC_PTR   0x17C914
-/*  MPSCs  */
-#define GT96100_MPSC0_MAIN_CONFIG_LOW   0x000A00
-#define GT96100_MPSC0_MAIN_CONFIG_HIGH  0x000A04
-#define GT96100_MPSC0_PROTOCOL_CONFIG   0x000A08
-#define GT96100_MPSC_CHAN0_REG1         0x000A0C
-#define GT96100_MPSC_CHAN0_REG2         0x000A10
-#define GT96100_MPSC_CHAN0_REG3         0x000A14
-#define GT96100_MPSC_CHAN0_REG4         0x000A18
-#define GT96100_MPSC_CHAN0_REG5         0x000A1C
-#define GT96100_MPSC_CHAN0_REG6         0x000A20
-#define GT96100_MPSC_CHAN0_REG7         0x000A24
-#define GT96100_MPSC_CHAN0_REG8         0x000A28
-#define GT96100_MPSC_CHAN0_REG9         0x000A2C
-#define GT96100_MPSC_CHAN0_REG10        0x000A30
-#define GT96100_MPSC_CHAN0_REG11        0x000A34
-#define GT96100_MPSC1_MAIN_CONFIG_LOW   0x008A00
-#define GT96100_MPSC1_MAIN_CONFIG_HIGH  0x008A04
-#define GT96100_MPSC1_PROTOCOL_CONFIG   0x008A08
-#define GT96100_MPSC_CHAN1_REG1         0x008A0C
-#define GT96100_MPSC_CHAN1_REG2         0x008A10
-#define GT96100_MPSC_CHAN1_REG3         0x008A14
-#define GT96100_MPSC_CHAN1_REG4         0x008A18
-#define GT96100_MPSC_CHAN1_REG5         0x008A1C
-#define GT96100_MPSC_CHAN1_REG6         0x008A20
-#define GT96100_MPSC_CHAN1_REG7         0x008A24
-#define GT96100_MPSC_CHAN1_REG8         0x008A28
-#define GT96100_MPSC_CHAN1_REG9         0x008A2C
-#define GT96100_MPSC_CHAN1_REG10        0x008A30
-#define GT96100_MPSC_CHAN1_REG11        0x008A34
-#define GT96100_MPSC2_MAIN_CONFIG_LOW   0x010A00
-#define GT96100_MPSC2_MAIN_CONFIG_HIGH  0x010A04
-#define GT96100_MPSC2_PROTOCOL_CONFIG   0x010A08
-#define GT96100_MPSC_CHAN2_REG1         0x010A0C
-#define GT96100_MPSC_CHAN2_REG2         0x010A10
-#define GT96100_MPSC_CHAN2_REG3         0x010A14
-#define GT96100_MPSC_CHAN2_REG4         0x010A18
-#define GT96100_MPSC_CHAN2_REG5         0x010A1C
-#define GT96100_MPSC_CHAN2_REG6         0x010A20
-#define GT96100_MPSC_CHAN2_REG7         0x010A24
-#define GT96100_MPSC_CHAN2_REG8         0x010A28
-#define GT96100_MPSC_CHAN2_REG9         0x010A2C
-#define GT96100_MPSC_CHAN2_REG10        0x010A30
-#define GT96100_MPSC_CHAN2_REG11        0x010A34
-#define GT96100_MPSC3_MAIN_CONFIG_LOW   0x018A00
-#define GT96100_MPSC3_MAIN_CONFIG_HIGH  0x018A04
-#define GT96100_MPSC3_PROTOCOL_CONFIG   0x018A08
-#define GT96100_MPSC_CHAN3_REG1         0x018A0C
-#define GT96100_MPSC_CHAN3_REG2         0x018A10
-#define GT96100_MPSC_CHAN3_REG3         0x018A14
-#define GT96100_MPSC_CHAN3_REG4         0x018A18
-#define GT96100_MPSC_CHAN3_REG5         0x018A1C
-#define GT96100_MPSC_CHAN3_REG6         0x018A20
-#define GT96100_MPSC_CHAN3_REG7         0x018A24
-#define GT96100_MPSC_CHAN3_REG8         0x018A28
-#define GT96100_MPSC_CHAN3_REG9         0x018A2C
-#define GT96100_MPSC_CHAN3_REG10        0x018A30
-#define GT96100_MPSC_CHAN3_REG11        0x018A34
-#define GT96100_MPSC4_MAIN_CONFIG_LOW   0x020A00
-#define GT96100_MPSC4_MAIN_CONFIG_HIGH  0x020A04
-#define GT96100_MPSC4_PROTOCOL_CONFIG   0x020A08
-#define GT96100_MPSC_CHAN4_REG1         0x020A0C
-#define GT96100_MPSC_CHAN4_REG2         0x020A10
-#define GT96100_MPSC_CHAN4_REG3         0x020A14
-#define GT96100_MPSC_CHAN4_REG4         0x020A18
-#define GT96100_MPSC_CHAN4_REG5         0x020A1C
-#define GT96100_MPSC_CHAN4_REG6         0x020A20
-#define GT96100_MPSC_CHAN4_REG7         0x020A24
-#define GT96100_MPSC_CHAN4_REG8         0x020A28
-#define GT96100_MPSC_CHAN4_REG9         0x020A2C
-#define GT96100_MPSC_CHAN4_REG10        0x020A30
-#define GT96100_MPSC_CHAN4_REG11        0x020A34
-#define GT96100_MPSC5_MAIN_CONFIG_LOW   0x028A00
-#define GT96100_MPSC5_MAIN_CONFIG_HIGH  0x028A04
-#define GT96100_MPSC5_PROTOCOL_CONFIG   0x028A08
-#define GT96100_MPSC_CHAN5_REG1         0x028A0C
-#define GT96100_MPSC_CHAN5_REG2         0x028A10
-#define GT96100_MPSC_CHAN5_REG3         0x028A14
-#define GT96100_MPSC_CHAN5_REG4         0x028A18
-#define GT96100_MPSC_CHAN5_REG5         0x028A1C
-#define GT96100_MPSC_CHAN5_REG6         0x028A20
-#define GT96100_MPSC_CHAN5_REG7         0x028A24
-#define GT96100_MPSC_CHAN5_REG8         0x028A28
-#define GT96100_MPSC_CHAN5_REG9         0x028A2C
-#define GT96100_MPSC_CHAN5_REG10        0x028A30
-#define GT96100_MPSC_CHAN5_REG11        0x028A34
-#define GT96100_MPSC6_MAIN_CONFIG_LOW   0x030A00
-#define GT96100_MPSC6_MAIN_CONFIG_HIGH  0x030A04
-#define GT96100_MPSC6_PROTOCOL_CONFIG   0x030A08
-#define GT96100_MPSC_CHAN6_REG1         0x030A0C
-#define GT96100_MPSC_CHAN6_REG2         0x030A10
-#define GT96100_MPSC_CHAN6_REG3         0x030A14
-#define GT96100_MPSC_CHAN6_REG4         0x030A18
-#define GT96100_MPSC_CHAN6_REG5         0x030A1C
-#define GT96100_MPSC_CHAN6_REG6         0x030A20
-#define GT96100_MPSC_CHAN6_REG7         0x030A24
-#define GT96100_MPSC_CHAN6_REG8         0x030A28
-#define GT96100_MPSC_CHAN6_REG9         0x030A2C
-#define GT96100_MPSC_CHAN6_REG10        0x030A30
-#define GT96100_MPSC_CHAN6_REG11        0x030A34
-#define GT96100_MPSC7_MAIN_CONFIG_LOW   0x038A00
-#define GT96100_MPSC7_MAIN_CONFIG_HIGH  0x038A04
-#define GT96100_MPSC7_PROTOCOL_CONFIG   0x038A08
-#define GT96100_MPSC_CHAN7_REG1         0x038A0C
-#define GT96100_MPSC_CHAN7_REG2         0x038A10
-#define GT96100_MPSC_CHAN7_REG3         0x038A14
-#define GT96100_MPSC_CHAN7_REG4         0x038A18
-#define GT96100_MPSC_CHAN7_REG5         0x038A1C
-#define GT96100_MPSC_CHAN7_REG6         0x038A20
-#define GT96100_MPSC_CHAN7_REG7         0x038A24
-#define GT96100_MPSC_CHAN7_REG8         0x038A28
-#define GT96100_MPSC_CHAN7_REG9         0x038A2C
-#define GT96100_MPSC_CHAN7_REG10        0x038A30
-#define GT96100_MPSC_CHAN7_REG11        0x038A34
-/*  FlexTDMs  */
-/* TDPR0 - Transmit Dual Port RAM. block size 0xff */
-#define GT96100_FXTDM0_TDPR0_BLK0_BASE  0x000B00
-#define GT96100_FXTDM0_TDPR0_BLK1_BASE  0x001B00
-#define GT96100_FXTDM0_TDPR0_BLK2_BASE  0x002B00
-#define GT96100_FXTDM0_TDPR0_BLK3_BASE  0x003B00
-/* RDPR0 - Receive Dual Port RAM. block size 0xff */
-#define GT96100_FXTDM0_RDPR0_BLK0_BASE  0x004B00
-#define GT96100_FXTDM0_RDPR0_BLK1_BASE  0x005B00
-#define GT96100_FXTDM0_RDPR0_BLK2_BASE  0x006B00
-#define GT96100_FXTDM0_RDPR0_BLK3_BASE  0x007B00
-#define GT96100_FXTDM0_TX_READ_PTR      0x008B00
-#define GT96100_FXTDM0_RX_READ_PTR      0x008B04
-#define GT96100_FXTDM0_CONFIG       0x008B08
-#define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C
-#define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10
-#define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14
-#define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18
-#define GT96100_FXTDM1_TDPR1_BLK0_BASE  0x010B00
-#define GT96100_FXTDM1_TDPR1_BLK1_BASE  0x011B00
-#define GT96100_FXTDM1_TDPR1_BLK2_BASE  0x012B00
-#define GT96100_FXTDM1_TDPR1_BLK3_BASE  0x013B00
-#define GT96100_FXTDM1_RDPR1_BLK0_BASE  0x014B00
-#define GT96100_FXTDM1_RDPR1_BLK1_BASE  0x015B00
-#define GT96100_FXTDM1_RDPR1_BLK2_BASE  0x016B00
-#define GT96100_FXTDM1_RDPR1_BLK3_BASE  0x017B00
-#define GT96100_FXTDM1_TX_READ_PTR      0x018B00
-#define GT96100_FXTDM1_RX_READ_PTR      0x018B04
-#define GT96100_FXTDM1_CONFIG       0x018B08
-#define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C
-#define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10
-#define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14
-#define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18
-#define GT96100_FLTDM2_TDPR2_BLK0_BASE  0x020B00
-#define GT96100_FLTDM2_TDPR2_BLK1_BASE  0x021B00
-#define GT96100_FLTDM2_TDPR2_BLK2_BASE  0x022B00
-#define GT96100_FLTDM2_TDPR2_BLK3_BASE  0x023B00
-#define GT96100_FLTDM2_RDPR2_BLK0_BASE  0x024B00
-#define GT96100_FLTDM2_RDPR2_BLK1_BASE  0x025B00
-#define GT96100_FLTDM2_RDPR2_BLK2_BASE  0x026B00
-#define GT96100_FLTDM2_RDPR2_BLK3_BASE  0x027B00
-#define GT96100_FLTDM2_TX_READ_PTR      0x028B00
-#define GT96100_FLTDM2_RX_READ_PTR      0x028B04
-#define GT96100_FLTDM2_CONFIG       0x028B08
-#define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C
-#define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10
-#define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14
-#define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18
-#define GT96100_FLTDM3_TDPR3_BLK0_BASE  0x030B00
-#define GT96100_FLTDM3_TDPR3_BLK1_BASE  0x031B00
-#define GT96100_FLTDM3_TDPR3_BLK2_BASE  0x032B00
-#define GT96100_FLTDM3_TDPR3_BLK3_BASE  0x033B00
-#define GT96100_FXTDM3_RDPR3_BLK0_BASE  0x034B00
-#define GT96100_FXTDM3_RDPR3_BLK1_BASE  0x035B00
-#define GT96100_FXTDM3_RDPR3_BLK2_BASE  0x036B00
-#define GT96100_FXTDM3_RDPR3_BLK3_BASE  0x037B00
-#define GT96100_FXTDM3_TX_READ_PTR      0x038B00
-#define GT96100_FXTDM3_RX_READ_PTR      0x038B04
-#define GT96100_FXTDM3_CONFIG       0x038B08
-#define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C
-#define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10
-#define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14
-#define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18
-/*  Baud Rate Generators  */
-#define GT96100_BRG0_CONFIG     0x102A00
-#define GT96100_BRG0_BAUD_TUNE  0x102A04
-#define GT96100_BRG1_CONFIG     0x102A08
-#define GT96100_BRG1_BAUD_TUNE  0x102A0C
-#define GT96100_BRG2_CONFIG     0x102A10
-#define GT96100_BRG2_BAUD_TUNE  0x102A14
-#define GT96100_BRG3_CONFIG     0x102A18
-#define GT96100_BRG3_BAUD_TUNE  0x102A1C
-#define GT96100_BRG4_CONFIG     0x102A20
-#define GT96100_BRG4_BAUD_TUNE  0x102A24
-#define GT96100_BRG5_CONFIG     0x102A28
-#define GT96100_BRG5_BAUD_TUNE  0x102A2C
-#define GT96100_BRG6_CONFIG     0x102A30
-#define GT96100_BRG6_BAUD_TUNE  0x102A34
-#define GT96100_BRG7_CONFIG     0x102A38
-#define GT96100_BRG7_BAUD_TUNE  0x102A3C
-/*  Routing Registers  */
-#define GT96100_ROUTE_MAIN      0x101A00
-#define GT96100_ROUTE_RX_CLOCK  0x101A10
-#define GT96100_ROUTE_TX_CLOCK  0x101A20
-/*  General Purpose Ports  */
-#define GT96100_GPP_CONFIG0     0x100A00
-#define GT96100_GPP_CONFIG1     0x100A04
-#define GT96100_GPP_CONFIG2     0x100A08
-#define GT96100_GPP_CONFIG3     0x100A0C
-#define GT96100_GPP_IO0         0x100A20
-#define GT96100_GPP_IO1         0x100A24
-#define GT96100_GPP_IO2         0x100A28
-#define GT96100_GPP_IO3         0x100A2C
-#define GT96100_GPP_DATA0       0x100A40
-#define GT96100_GPP_DATA1       0x100A44
-#define GT96100_GPP_DATA2       0x100A48
-#define GT96100_GPP_DATA3       0x100A4C
-#define GT96100_GPP_LEVEL0      0x100A60
-#define GT96100_GPP_LEVEL1      0x100A64
-#define GT96100_GPP_LEVEL2      0x100A68
-#define GT96100_GPP_LEVEL3      0x100A6C
-/*  Watchdog  */
-#define GT96100_WD_CONFIG   0x101A80
-#define GT96100_WD_VALUE    0x101A84
-/* Communication Unit Arbiter  */
-#define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0
-/*  PCI Arbiters  */
-#define GT96100_PCI0_ARBTR_CONFIG 0x101AE0
-#define GT96100_PCI1_ARBTR_CONFIG 0x101AE4
-/* CIU Arbiter */
-#define GT96100_CIU_ARBITER_CONFIG 0x101AC0
-/* Interrupt Controller */
-#define GT96100_MAIN_CAUSE     0x000C18
-#define GT96100_INT0_MAIN_MASK 0x000C1C
-#define GT96100_INT1_MAIN_MASK 0x000C24
-#define GT96100_HIGH_CAUSE     0x000C98
-#define GT96100_INT0_HIGH_MASK 0x000C9C
-#define GT96100_INT1_HIGH_MASK 0x000CA4
-#define GT96100_INT0_SELECT    0x000C70
-#define GT96100_INT1_SELECT    0x000C74
-#define GT96100_SERIAL_CAUSE   0x103A00
-#define GT96100_SERINT0_MASK   0x103A80
-#define GT96100_SERINT1_MASK   0x103A88
-#endif /*  _GT96100_H */
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 25f5e8a4177d..0fe02945feba 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -12,102 +12,95 @@
 #ifdef __ASSEMBLY__
+#define ASMMACRO(name, code...) .macro name; code; .endm
-        .macro  _ssnop
-        sll     $0, $0, 1
-        .endm
-        .macro  _ehb
-        sll     $0, $0, 3
-        .endm
-/*
- * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
- * use of the JTLB for instructions should not occur for 4 cpu cycles and use
- * for data translations should not occur for 3 cpu cycles.
- */
-#ifdef CONFIG_CPU_RM9000
-        .macro  mtc0_tlbw_hazard
-        .set    push
-        .set    mips32
-        _ssnop; _ssnop; _ssnop; _ssnop
-        .set    pop
-        .endm
-        .macro  tlbw_eret_hazard
-        .set    push
-        .set    mips32
-        _ssnop; _ssnop; _ssnop; _ssnop
-        .set    pop
-        .endm
 #else
-/*
+#define ASMMACRO(name, code...)                                         \
- * The taken branch will result in a two cycle penalty for the two killed
+__asm__(".macro " #name "; " #code "; .endm");                          \
- * instructions on R4000 / R4400.  Other processors only have a single cycle
+                                                                        \
- * hazard so this is nice trick to have an optimal code for a range of
+static inline void name(void)                                           \
- * processors.
+{                                                                       \
- */
+        __asm__ __volatile__ (#name);                                   \
-        .macro  mtc0_tlbw_hazard
+}
-        b       . + 8
-        .endm
-        .macro  tlbw_eret_hazard
-        .endm
 #endif
+ASMMACRO(_ssnop,
+         sll    $0, $0, 1
+        )
+ASMMACRO(_ehb,
+         sll    $0, $0, 3
+        )
 /*
- * mtc0->mfc0 hazard
+ * TLB hazards
- * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
- * It is a MIPS32R2 processor so ehb will clear the hazard.
 */
+#if defined(CONFIG_CPU_MIPSR2)
-#ifdef CONFIG_CPU_MIPSR2
 /*
- * Use a macro for ehb unless explicit support for MIPSR2 is enabled
+ * MIPSR2 defines ehb for hazard avoidance
 */
-#define irq_enable_hazard                                               \
+ASMMACRO(mtc0_tlbw_hazard,
+         _ehb
+        )
+ASMMACRO(tlbw_use_hazard,
+         _ehb
+        )
+ASMMACRO(tlb_probe_hazard,
+         _ehb
+        )
+ASMMACRO(irq_enable_hazard,
+        )
+ASMMACRO(irq_disable_hazard,
        _ehb
+        )
-#define irq_disable_hazard                                              \
+ASMMACRO(back_to_back_c0_hazard,
-        _ehb
+         _ehb
+        )
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
 /*
- * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
+ * gcc has a tradition of misscompiling the previous construct using the
+ * address of a label as argument to inline assembler.  Gas otoh has the
+ * annoying difference between la and dla which are only usable for 32-bit
+ * rsp. 64-bit code, so can't be used without conditional compilation.
+ * The alterantive is switching the assembler to 64-bit code which happens
+ * to work right even for 32-bit code ...
 */
+#define instruction_hazard()                                            \
+do {                                                                    \
+        unsigned long tmp;                                              \
+                                                                        \
+        __asm__ __volatile__(                                           \
+        "       .set    mips64r2                                \n"     \
+        "       dla     %0, 1f                                  \n"     \
+        "       jr.hb   %0                                      \n"     \
+        "       .set    mips0                                   \n"     \
+        "1:                                                     \n"     \
+        : "=r" (tmp));                                                  \
+} while (0)
-#define irq_enable_hazard
+#elif defined(CONFIG_CPU_R10000)
-#define irq_disable_hazard
-#else
 /*
- * Classic MIPS needs 1 - 3 nops or ssnops
+ * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
 */
-#define irq_enable_hazard
-#define irq_disable_hazard                                              \
-        _ssnop; _ssnop; _ssnop
-#endif
+ASMMACRO(mtc0_tlbw_hazard,
+        )
-#else /* __ASSEMBLY__ */
+ASMMACRO(tlbw_use_hazard,
+        )
-__asm__(
+ASMMACRO(tlb_probe_hazard,
-        "       .macro  _ssnop                                  \n"
+        )
-        "       sll     $0, $0, 1                               \n"
+ASMMACRO(irq_enable_hazard,
-        "       .endm                                           \n"
+        )
-        "                                                       \n"
+ASMMACRO(irq_disable_hazard,
-        "       .macro  _ehb                                    \n"
+        )
-        "       sll     $0, $0, 3                               \n"
+ASMMACRO(back_to_back_c0_hazard,
-        "       .endm                                           \n");
+        )
+#define instruction_hazard() do { } while (0)
-#ifdef CONFIG_CPU_RM9000
+#elif defined(CONFIG_CPU_RM9000)
 /*
 * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
@@ -115,176 +108,73 @@ __asm__(
 * for data translations should not occur for 3 cpu cycles.
 */
-#define mtc0_tlbw_hazard()                                              \
+ASMMACRO(mtc0_tlbw_hazard,
-        __asm__ __volatile__(                                           \
+         _ssnop; _ssnop; _ssnop; _ssnop
-        "       .set    mips32                                  \n"     \
+        )
-        "       _ssnop                                          \n"     \
+ASMMACRO(tlbw_use_hazard,
-        "       _ssnop                                          \n"     \
+         _ssnop; _ssnop; _ssnop; _ssnop
-        "       _ssnop                                          \n"     \
+        )
-        "       _ssnop                                          \n"     \
+ASMMACRO(tlb_probe_hazard,
-        "       .set    mips0                                   \n")
+         _ssnop; _ssnop; _ssnop; _ssnop
+        )
-#define tlbw_use_hazard()                                               \
+ASMMACRO(irq_enable_hazard,
-        __asm__ __volatile__(                                           \
+        )
-        "       .set    mips32                                  \n"     \
+ASMMACRO(irq_disable_hazard,
-        "       _ssnop                                          \n"     \
+        )
-        "       _ssnop                                          \n"     \
+ASMMACRO(back_to_back_c0_hazard,
-        "       _ssnop                                          \n"     \
+        )
-        "       _ssnop                                          \n"     \
+#define instruction_hazard() do { } while (0)
-        "       .set    mips0                                   \n")
-#else
-/*
- * Overkill warning ...
- */
-#define mtc0_tlbw_hazard()                                              \
-        __asm__ __volatile__(                                           \
-        "       .set    noreorder                               \n"     \
-        "       nop                                             \n"     \
-        "       nop                                             \n"     \
-        "       nop                                             \n"     \
-        "       nop                                             \n"     \
-        "       nop                                             \n"     \
-        "       nop                                             \n"     \
-        "       .set    reorder                                 \n")
-#define tlbw_use_hazard()                                               \
-        __asm__ __volatile__(                                           \
-        "       .set    noreorder                               \n"     \
-        "       nop                                             \n"     \
-        "       nop                                             \n"     \
-        "       nop                                             \n"     \
-        "       nop                                             \n"     \
-        "       nop                                             \n"     \
-        "       nop                                             \n"     \
-        "       .set    reorder                                 \n")
-#endif
-/*
- * Interrupt enable/disable hazards
- * Some processors have hazards when modifying
- * the status register to change the interrupt state
- */
-#ifdef CONFIG_CPU_MIPSR2
-__asm__("       .macro  irq_enable_hazard                       \n"
-        "       _ehb                                            \n"
-        "       .endm                                           \n"
-        "                                                       \n"
-        "       .macro  irq_disable_hazard                      \n"
-        "       _ehb                                            \n"
-        "       .endm                                           \n");
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
+#elif defined(CONFIG_CPU_SB1)
 /*
- * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
+ * Mostly like R4000 for historic reasons
 */
+ASMMACRO(mtc0_tlbw_hazard,
-__asm__(
+        )
-        "       .macro  irq_enable_hazard                       \n"
+ASMMACRO(tlbw_use_hazard,
-        "       .endm                                           \n"
+        )
-        "                                                       \n"
+ASMMACRO(tlb_probe_hazard,
-        "       .macro  irq_disable_hazard                      \n"
+        )
-        "       .endm                                           \n");
+ASMMACRO(irq_enable_hazard,
+        )
+ASMMACRO(irq_disable_hazard,
+         _ssnop; _ssnop; _ssnop
+        )
+ASMMACRO(back_to_back_c0_hazard,
+        )
+#define instruction_hazard() do { } while (0)
 #else
 /*
- * Default for classic MIPS processors.  Assume worst case hazards but don't
+ * Finally the catchall case for all other processors including R4000, R4400,
- * care about the irq_enable_hazard - sooner or later the hardware will
+ * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
- * enable it and we don't care when exactly.
- */
-__asm__(
-        "       #                                               \n"
-        "       # There is a hazard but we do not care          \n"
-        "       #                                               \n"
-        "       .macro\tirq_enable_hazard                       \n"
-        "       .endm                                           \n"
-        "                                                       \n"
-        "       .macro\tirq_disable_hazard                      \n"
-        "       _ssnop                                          \n"
-        "       _ssnop                                          \n"
-        "       _ssnop                                          \n"
-        "       .endm                                           \n");
-#endif
-#define irq_enable_hazard()                                             \
-        __asm__ __volatile__("irq_enable_hazard")
-#define irq_disable_hazard()                                            \
-        __asm__ __volatile__("irq_disable_hazard")
-/*
- * Back-to-back hazards -
 *
- * What is needed to separate a move to cp0 from a subsequent read from the
+ * The taken branch will result in a two cycle penalty for the two killed
- * same cp0 register?
+ * instructions on R4000 / R4400.  Other processors only have a single cycle
- */
+ * hazard so this is nice trick to have an optimal code for a range of
-#ifdef CONFIG_CPU_MIPSR2
+ * processors.
-__asm__("       .macro  back_to_back_c0_hazard                  \n"
-        "       _ehb                                            \n"
-        "       .endm                                           \n");
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
-      defined(CONFIG_CPU_SB1)
-__asm__("       .macro  back_to_back_c0_hazard                  \n"
-        "       .endm                                           \n");
-#else
-__asm__("       .macro  back_to_back_c0_hazard                  \n"
-        "       .set    noreorder                               \n"
-        "       _ssnop                                          \n"
-        "       _ssnop                                          \n"
-        "       _ssnop                                          \n"
-        "       .set    reorder                                 \n"
-        "       .endm");
-#endif
-#define back_to_back_c0_hazard()                                        \
-        __asm__ __volatile__("back_to_back_c0_hazard")
-/*
- * Instruction execution hazard
- */
-#ifdef CONFIG_CPU_MIPSR2
-/*
- * gcc has a tradition of misscompiling the previous construct using the
- * address of a label as argument to inline assembler.  Gas otoh has the
- * annoying difference between la and dla which are only usable for 32-bit
- * rsp. 64-bit code, so can't be used without conditional compilation.
- * The alterantive is switching the assembler to 64-bit code which happens
- * to work right even for 32-bit code ...
 */
-#define instruction_hazard()                                            \
+ASMMACRO(mtc0_tlbw_hazard,
-do {                                                                    \
+        nop
-        unsigned long tmp;                                              \
+        )
-                                                                        \
+ASMMACRO(tlbw_use_hazard,
-        __asm__ __volatile__(                                           \
+        nop; nop; nop
-        "       .set    mips64r2                                \n"     \
+        )
-        "       dla     %0, 1f                                  \n"     \
+ASMMACRO(tlb_probe_hazard,
-        "       jr.hb   %0                                      \n"     \
+         nop; nop; nop
-        "       .set    mips0                                   \n"     \
+        )
-        "1:                                                     \n"     \
+ASMMACRO(irq_enable_hazard,
-        : "=r" (tmp));                                                  \
+        )
-} while (0)
+ASMMACRO(irq_disable_hazard,
+        nop; nop; nop
-#else
+        )
+ASMMACRO(back_to_back_c0_hazard,
+         _ssnop; _ssnop; _ssnop;
+        )
 #define instruction_hazard() do { } while (0)
-#endif
-extern void mips_ihb(void);
-#endif /* __ASSEMBLY__ */
+#endif
 #endif /* _ASM_HAZARDS_H */
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index 896550bad322..d35c61776a02 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -76,8 +76,4 @@ extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
                          unsigned long hwmask);
 #endif /* CONFIG_MIPS_MT_SMTC */
-#ifdef CONFIG_SMP
-#define ARCH_HAS_IRQ_PER_CPU
-#endif
 #endif /* _ASM_IRQ_H */
diff --git a/include/asm-mips/mach-atlas/mc146818rtc.h b/include/asm-mips/mach-atlas/mc146818rtc.h
index 397522ea5565..a73a5698420c 100644
--- a/include/asm-mips/mach-atlas/mc146818rtc.h
+++ b/include/asm-mips/mach-atlas/mc146818rtc.h
@@ -28,10 +28,12 @@
 #include <asm/mips-boards/atlas.h>
 #include <asm/mips-boards/atlasint.h>
+#define ARCH_RTC_LOCATION
 #define RTC_PORT(x)     (ATLAS_RTC_ADR_REG + (x) * 8)
 #define RTC_IO_EXTENT   0x100
 #define RTC_IOMAPPED    0
-#define RTC_IRQ         ATLASINT_RTC
+#define RTC_IRQ         ATLAS_INT_RTC
 static inline unsigned char CMOS_READ(unsigned long addr)
 {
diff --git a/include/asm-mips/mach-ev96100/mach-gt64120.h b/include/asm-mips/mach-ev96100/mach-gt64120.h
deleted file mode 100644
index 0ef1e6c25acf..000000000000
--- a/include/asm-mips/mach-ev96100/mach-gt64120.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *  This is a direct copy of the ev96100.h file, with a global
- * search and replace.  The numbers are the same.
- *
- *  The reason I'm duplicating this is so that the 64120/96100
- * defines won't be confusing in the source code.
- */
-#ifndef _ASM_GT64120_EV96100_GT64120_DEP_H
-#define _ASM_GT64120_EV96100_GT64120_DEP_H
-/*
- *   GT96100 config space base address
- */
-#define GT64120_BASE    (KSEG1ADDR(0x14000000))
-/*
- *   PCI Bus allocation
- *
- *   (Guessing ...)
- */
-#define GT_PCI_MEM_BASE 0x12000000UL
-#define GT_PCI_MEM_SIZE 0x02000000UL
-#define GT_PCI_IO_BASE  0x10000000UL
-#define GT_PCI_IO_SIZE  0x02000000UL
-#define GT_ISA_IO_BASE  PCI_IO_BASE
-/*
- *   Duart I/O ports.
- */
-#define EV96100_COM1_BASE_ADDR  (0xBD000000 + 0x20)
-#define EV96100_COM2_BASE_ADDR  (0xBD000000 + 0x00)
-/*
- *   EV96100 interrupt controller register base.
- */
-#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
-/*
- *   EV96100 UART register base.
- */
-#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR
-#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR
-#define EV96100_BASE_BAUD       ( 3686400 / 16 )
-#endif /* _ASM_GT64120_EV96100_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-excite/excite.h b/include/asm-mips/mach-excite/excite.h
index 130bd4b8edce..4c29ba44992c 100644
--- a/include/asm-mips/mach-excite/excite.h
+++ b/include/asm-mips/mach-excite/excite.h
@@ -7,7 +7,7 @@
 #define EXCITE_CPU_EXT_CLOCK 100000000
-#if !defined(__ASSEMBLER__)
+#if !defined(__ASSEMBLY__)
 void __init excite_kgdb_init(void);
 void excite_procfs_init(void);
 extern unsigned long memsize;
diff --git a/arch/mips/basler/excite/excite_fpga.h b/include/asm-mips/mach-excite/excite_fpga.h
index 38fcda703a0b..38fcda703a0b 100644
--- a/arch/mips/basler/excite/excite_fpga.h
+++ b/include/asm-mips/mach-excite/excite_fpga.h
diff --git a/include/asm-mips/mach-qemu/cpu-feature-overrides.h b/include/asm-mips/mach-qemu/cpu-feature-overrides.h
index f4e370e27168..529445dacedb 100644
--- a/include/asm-mips/mach-qemu/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-qemu/cpu-feature-overrides.h
@@ -20,7 +20,7 @@
 #define cpu_has_llsc            1
 #define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
+#define cpu_has_dc_aliases      0
 #define cpu_has_ic_fills_f_dc   0
 #define cpu_has_dsp             0
diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h
index fd7ebc54fa90..b15e4ea0b091 100644
--- a/include/asm-mips/mips-boards/atlasint.h
+++ b/include/asm-mips/mips-boards/atlasint.h
@@ -1,6 +1,7 @@
 /*
- * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999, 2006  MIPS Technologies, Inc.  All rights reserved.
- * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
 *
 * ########################################################################
 *
@@ -25,41 +26,88 @@
 #ifndef _MIPS_ATLASINT_H
 #define _MIPS_ATLASINT_H
-#define ATLASINT_BASE           1
+/*
-#define ATLASINT_UART           (ATLASINT_BASE+0)
+ * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode)
-#define ATLASINT_TIM0           (ATLASINT_BASE+1)
+ */
-#define ATLASINT_RES2           (ATLASINT_BASE+2)
+#define MIPSCPU_INT_BASE        0
-#define ATLASINT_RES3           (ATLASINT_BASE+3)
-#define ATLASINT_RTC            (ATLASINT_BASE+4)
+/* CPU interrupt offsets */
-#define ATLASINT_COREHI         (ATLASINT_BASE+5)
+#define MIPSCPU_INT_SW0         0
-#define ATLASINT_CORELO         (ATLASINT_BASE+6)
+#define MIPSCPU_INT_SW1         1
-#define ATLASINT_RES7           (ATLASINT_BASE+7)
+#define MIPSCPU_INT_MB0         2
-#define ATLASINT_PCIA           (ATLASINT_BASE+8)
+#define MIPSCPU_INT_ATLAS       MIPSCPU_INT_MB0
-#define ATLASINT_PCIB           (ATLASINT_BASE+9)
+#define MIPSCPU_INT_MB1         3
-#define ATLASINT_PCIC           (ATLASINT_BASE+10)
+#define MIPSCPU_INT_MB2         4
-#define ATLASINT_PCID           (ATLASINT_BASE+11)
+#define MIPSCPU_INT_MB3         5
-#define ATLASINT_ENUM           (ATLASINT_BASE+12)
+#define MIPSCPU_INT_MB4         6
-#define ATLASINT_DEG            (ATLASINT_BASE+13)
+#define MIPSCPU_INT_CPUCTR      7
-#define ATLASINT_ATXFAIL        (ATLASINT_BASE+14)
-#define ATLASINT_INTA           (ATLASINT_BASE+15)
+/*
-#define ATLASINT_INTB           (ATLASINT_BASE+16)
+ * Interrupts 8..39 are used for Atlas interrupt controller interrupts
-#define ATLASINT_ETH            ATLASINT_INTB
+ */
-#define ATLASINT_INTC           (ATLASINT_BASE+17)
+#define ATLAS_INT_BASE          8
-#define ATLASINT_SCSI           ATLASINT_INTC
+#define ATLAS_INT_UART          (ATLAS_INT_BASE + 0)
-#define ATLASINT_INTD           (ATLASINT_BASE+18)
+#define ATLAS_INT_TIM0          (ATLAS_INT_BASE + 1)
-#define ATLASINT_SERR           (ATLASINT_BASE+19)
+#define ATLAS_INT_RES2          (ATLAS_INT_BASE + 2)
-#define ATLASINT_RES20          (ATLASINT_BASE+20)
+#define ATLAS_INT_RES3          (ATLAS_INT_BASE + 3)
-#define ATLASINT_RES21          (ATLASINT_BASE+21)
+#define ATLAS_INT_RTC           (ATLAS_INT_BASE + 4)
-#define ATLASINT_RES22          (ATLASINT_BASE+22)
+#define ATLAS_INT_COREHI        (ATLAS_INT_BASE + 5)
-#define ATLASINT_RES23          (ATLASINT_BASE+23)
+#define ATLAS_INT_CORELO        (ATLAS_INT_BASE + 6)
-#define ATLASINT_RES24          (ATLASINT_BASE+24)
+#define ATLAS_INT_RES7          (ATLAS_INT_BASE + 7)
-#define ATLASINT_RES25          (ATLASINT_BASE+25)
+#define ATLAS_INT_PCIA          (ATLAS_INT_BASE + 8)
-#define ATLASINT_RES26          (ATLASINT_BASE+26)
+#define ATLAS_INT_PCIB          (ATLAS_INT_BASE + 9)
-#define ATLASINT_RES27          (ATLASINT_BASE+27)
+#define ATLAS_INT_PCIC          (ATLAS_INT_BASE + 10)
-#define ATLASINT_RES28          (ATLASINT_BASE+28)
+#define ATLAS_INT_PCID          (ATLAS_INT_BASE + 11)
-#define ATLASINT_RES29          (ATLASINT_BASE+29)
+#define ATLAS_INT_ENUM          (ATLAS_INT_BASE + 12)
-#define ATLASINT_RES30          (ATLASINT_BASE+30)
+#define ATLAS_INT_DEG           (ATLAS_INT_BASE + 13)
-#define ATLASINT_RES31          (ATLASINT_BASE+31)
+#define ATLAS_INT_ATXFAIL       (ATLAS_INT_BASE + 14)
-#define ATLASINT_END            (ATLASINT_BASE+31)
+#define ATLAS_INT_INTA          (ATLAS_INT_BASE + 15)
+#define ATLAS_INT_INTB          (ATLAS_INT_BASE + 16)
+#define ATLAS_INT_ETH           ATLAS_INT_INTB
+#define ATLAS_INT_INTC          (ATLAS_INT_BASE + 17)
+#define ATLAS_INT_SCSI          ATLAS_INT_INTC
+#define ATLAS_INT_INTD          (ATLAS_INT_BASE + 18)
+#define ATLAS_INT_SERR          (ATLAS_INT_BASE + 19)
+#define ATLAS_INT_RES20         (ATLAS_INT_BASE + 20)
+#define ATLAS_INT_RES21         (ATLAS_INT_BASE + 21)
+#define ATLAS_INT_RES22         (ATLAS_INT_BASE + 22)
+#define ATLAS_INT_RES23         (ATLAS_INT_BASE + 23)
+#define ATLAS_INT_RES24         (ATLAS_INT_BASE + 24)
+#define ATLAS_INT_RES25         (ATLAS_INT_BASE + 25)
+#define ATLAS_INT_RES26         (ATLAS_INT_BASE + 26)
+#define ATLAS_INT_RES27         (ATLAS_INT_BASE + 27)
+#define ATLAS_INT_RES28         (ATLAS_INT_BASE + 28)
+#define ATLAS_INT_RES29         (ATLAS_INT_BASE + 29)
+#define ATLAS_INT_RES30         (ATLAS_INT_BASE + 30)
+#define ATLAS_INT_RES31         (ATLAS_INT_BASE + 31)
+#define ATLAS_INT_END           (ATLAS_INT_BASE + 31)
+/*
+ * Interrupts 64..127 are used for Soc-it Classic interrupts
+ */
+#define MSC01C_INT_BASE         64
+/* SOC-it Classic interrupt offsets */
+#define MSC01C_INT_TMR          0
+#define MSC01C_INT_PCI          1
+/*
+ * Interrupts 64..127 are used for Soc-it EIC interrupts
+ */
+#define MSC01E_INT_BASE         64
+/* SOC-it EIC interrupt offsets */
+#define MSC01E_INT_SW0          1
+#define MSC01E_INT_SW1          2
+#define MSC01E_INT_MB0          3
+#define MSC01E_INT_ATLAS        MSC01E_INT_MB0
+#define MSC01E_INT_MB1          4
+#define MSC01E_INT_MB2          5
+#define MSC01E_INT_MB3          6
+#define MSC01E_INT_MB4          7
+#define MSC01E_INT_TMR          8
+#define MSC01E_INT_PCI          9
+#define MSC01E_INT_PERFCTR      10
+#define MSC01E_INT_CPUCTR       11
 #endif /* !(_MIPS_ATLASINT_H) */
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
index 18b69de87daa..fe065d6070ca 100644
--- a/include/asm-mips/mmu_context.h
+++ b/include/asm-mips/mmu_context.h
@@ -262,10 +262,10 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu)
                /* See comments for similar code above */
                prevvpe = dvpe();
                oldasid = (read_c0_entryhi() & ASID_MASK);
-                if(smtc_live_asid[mytlb][oldasid]) {
+                if (smtc_live_asid[mytlb][oldasid]) {
-                  smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
+                        smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
-                  if(smtc_live_asid[mytlb][oldasid] == 0)
+                        if(smtc_live_asid[mytlb][oldasid] == 0)
-                        smtc_flush_tlb_asid(oldasid);
+                                smtc_flush_tlb_asid(oldasid);
                }
                /* See comments for similar code above */
                write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 219d359861f3..85b258ee7090 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -34,6 +34,8 @@
 #ifndef __ASSEMBLY__
+#include <asm/cpu-features.h>
 extern void clear_page(void * page);
 extern void copy_page(void * to, void * from);
@@ -53,7 +55,7 @@ static inline void clear_user_page(void *addr, unsigned long vaddr,
        extern void (*flush_data_cache_page)(unsigned long addr);
        clear_page(addr);
-        if (pages_do_alias((unsigned long) addr, vaddr))
+        if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK))
                flush_data_cache_page((unsigned long)addr);
 }
@@ -63,7 +65,8 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
        extern void (*flush_data_cache_page)(unsigned long addr);
        copy_page(vto, vfrom);
-        if (pages_do_alias((unsigned long)vto, vaddr))
+        if (!cpu_has_ic_fills_f_dc ||
+            pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
                flush_data_cache_page((unsigned long)vto);
 }
@@ -74,15 +77,17 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
  #ifdef CONFIG_CPU_MIPS32
    typedef struct { unsigned long pte_low, pte_high; } pte_t;
    #define pte_val(x)    ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+    #define __pte(x)      ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
  #else
     typedef struct { unsigned long long pte; } pte_t;
     #define pte_val(x) ((x).pte)
+     #define __pte(x)   ((pte_t) { (x) } )
  #endif
 #else
 typedef struct { unsigned long pte; } pte_t;
 #define pte_val(x)      ((x).pte)
-#endif
 #define __pte(x)        ((pte_t) { (x) } )
+#endif
 /*
 * For 3-level pagetables we defines these ourselves, for 2-level the
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index c59a1e21f5b0..d05fb6f38aa7 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -93,8 +93,12 @@
 #define PTRS_PER_PMD    ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
 #define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
+#if PGDIR_SIZE >= TASK_SIZE
+#define USER_PTRS_PER_PGD       (1)
+#else
 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
-#define FIRST_USER_ADDRESS      0
+#endif
+#define FIRST_USER_ADDRESS      0UL
 #define VMALLOC_START           MAP_BASE
 #define VMALLOC_END     \
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 4113316ee0da..4fb0fc43ffd7 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -10,8 +10,6 @@
 #define _ASM_PTRACE_H
-#include <asm/isadep.h>
 /* 0 - 31 are integer registers, 32 - 63 are fp registers.  */
 #define FPR_BASE        32
 #define PC              64
@@ -73,6 +71,7 @@ struct pt_regs {
 #ifdef __KERNEL__
 #include <linux/linkage.h>
+#include <asm/isadep.h>
 /*
 * Does the process account for user or for system time?
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 584bd9c0ab2e..035637c67e7c 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -52,9 +52,9 @@
 #endif
 /*
- * Both Galileo boards have the same UART mappings.
+ * Galileo EV64120 evaluation board
 */
-#if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120)
+#ifdef CONFIG_MIPS_EV64120
 #include <asm/galileo-boards/ev96100.h>
 #include <asm/galileo-boards/ev96100int.h>
 #define EV96100_SERIAL_PORT_DEFNS                                  \
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
index 335dbaf1d831..a885491217c1 100644
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -212,7 +212,7 @@
 * Note: you'll need to define uint32_t and uint64_t in your headers.
 */
-#if !defined(__ASSEMBLER__)
+#if !defined(__ASSEMBLY__)
 #define _SB_MAKE64(x) ((uint64_t)(x))
 #define _SB_MAKE32(x) ((uint32_t)(x))
 #else
@@ -251,9 +251,9 @@
 */
-#if defined(__mips64) && !defined(__ASSEMBLER__)
+#if defined(__mips64) && !defined(__ASSEMBLY__)
 #define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
 #define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
-#endif /* __ASSEMBLER__ */
+#endif /* __ASSEMBLY__ */
 #endif
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index f4178bdcfcb0..7ed0bb611e56 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -149,7 +149,7 @@
 * (For the assembler version, sysrev and dest may be the same register.
 * Also, it clobbers AT.)
 */
-#ifdef __ASSEMBLER__
+#ifdef __ASSEMBLY__
 #define SYS_SOC_TYPE(dest, sysrev)                                      \
        .set push ;                                                     \
        .set reorder ;                                                  \
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
index 87a1dff95199..8b391a2f0814 100644
--- a/include/asm-mips/signal.h
+++ b/include/asm-mips/signal.h
@@ -108,17 +108,8 @@ typedef unsigned long old_sigset_t;		/* at least 32 bits */
 #define SIG_BLOCK       1       /* for blocking signals */
 #define SIG_UNBLOCK     2       /* for unblocking signals */
 #define SIG_SETMASK     3       /* for setting the signal mask */
-#define SIG_SETMASK32   256     /* Goodie from SGI for BSD compatibility:
-                                   set only the low 32 bit of the sigset.  */
-/* Type of a signal handler.  */
+#include <asm-generic/signal.h>
-typedef void __signalfn_t(int);
-typedef __signalfn_t __user *__sighandler_t;
-/* Fake signal functions */
-#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
-#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
-#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
 struct sigaction {
        unsigned int    sa_flags;
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
index 669b8e349ff2..4c1a1b53aeaf 100644
--- a/include/asm-mips/spinlock.h
+++ b/include/asm-mips/spinlock.h
@@ -239,7 +239,51 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
        : "memory");
 }
-#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
+{
+        unsigned int tmp;
+        int ret;
+        if (R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    noreorder       # __raw_read_trylock    \n"
+                "       li      %2, 0                                   \n"
+                "1:     ll      %1, %3                                  \n"
+                "       bnez    %1, 2f                                  \n"
+                "        addu   %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqzl   %1, 1b                                  \n"
+                "       .set    reorder                                 \n"
+#ifdef CONFIG_SMP
+                "        sync                                           \n"
+#endif
+                "       li      %2, 1                                   \n"
+                "2:                                                     \n"
+                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
+                : "m" (rw->lock)
+                : "memory");
+        } else {
+                __asm__ __volatile__(
+                "       .set    noreorder       # __raw_read_trylock    \n"
+                "       li      %2, 0                                   \n"
+                "1:     ll      %1, %3                                  \n"
+                "       bnez    %1, 2f                                  \n"
+                "        addu   %1, 1                                   \n"
+                "       sc      %1, %0                                  \n"
+                "       beqz    %1, 1b                                  \n"
+                "       .set    reorder                                 \n"
+#ifdef CONFIG_SMP
+                "        sync                                           \n"
+#endif
+                "       li      %2, 1                                   \n"
+                "2:                                                     \n"
+                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
+                : "m" (rw->lock)
+                : "memory");
+        }
+        return ret;
+}
 static inline int __raw_write_trylock(raw_rwlock_t *rw)
 {
@@ -283,4 +327,5 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
        return ret;
 }
 #endif /* _ASM_SPINLOCK_H */
diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h
index 98aa737b34aa..b80de8e0fbbd 100644
--- a/include/asm-mips/timex.h
+++ b/include/asm-mips/timex.h
@@ -8,6 +8,8 @@
 #ifndef _ASM_TIMEX_H
 #define _ASM_TIMEX_H
+#ifdef __KERNEL__
 #include <asm/mipsregs.h>
 /*
@@ -51,4 +53,6 @@ static inline cycles_t get_cycles (void)
        return read_c0_count();
 }
+#endif /* __KERNEL__ */
 #endif /*  _ASM_TIMEX_H */
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index 610ccb8a50b3..c39142920fe6 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -313,7 +313,7 @@
 #define __NR_mknodat                    (__NR_Linux + 290)
 #define __NR_fchownat                   (__NR_Linux + 291)
 #define __NR_futimesat                  (__NR_Linux + 292)
-#define __NR_fstatat                    (__NR_Linux + 293)
+#define __NR_fstatat64                  (__NR_Linux + 293)
 #define __NR_unlinkat                   (__NR_Linux + 294)
 #define __NR_renameat                   (__NR_Linux + 295)
 #define __NR_linkat                     (__NR_Linux + 296)
@@ -329,16 +329,18 @@
 #define __NR_tee                        (__NR_Linux + 306)
 #define __NR_vmsplice                   (__NR_Linux + 307)
 #define __NR_move_pages                 (__NR_Linux + 308)
+#define __NR_set_robust_list            (__NR_Linux + 309)
+#define __NR_get_robust_list            (__NR_Linux + 310)
 /*
 * Offset of the last Linux o32 flavoured syscall
 */
-#define __NR_Linux_syscalls             308
+#define __NR_Linux_syscalls             310
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 #define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         308
+#define __NR_O32_Linux_syscalls         310
 #if _MIPS_SIM == _MIPS_SIM_ABI64
@@ -598,7 +600,7 @@
 #define __NR_mknodat                    (__NR_Linux + 249)
 #define __NR_fchownat                   (__NR_Linux + 250)
 #define __NR_futimesat                  (__NR_Linux + 251)
-#define __NR_fstatat                    (__NR_Linux + 252)
+#define __NR_newfstatat                 (__NR_Linux + 252)
 #define __NR_unlinkat                   (__NR_Linux + 253)
 #define __NR_renameat                   (__NR_Linux + 254)
 #define __NR_linkat                     (__NR_Linux + 255)
@@ -614,16 +616,18 @@
 #define __NR_tee                        (__NR_Linux + 265)
 #define __NR_vmsplice                   (__NR_Linux + 266)
 #define __NR_move_pages                 (__NR_Linux + 267)
+#define __NR_set_robust_list            (__NR_Linux + 268)
+#define __NR_get_robust_list            (__NR_Linux + 269)
 /*
 * Offset of the last Linux 64-bit flavoured syscall
 */
-#define __NR_Linux_syscalls             267
+#define __NR_Linux_syscalls             269
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 #define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          267
+#define __NR_64_Linux_syscalls          269
 #if _MIPS_SIM == _MIPS_SIM_NABI32
@@ -887,7 +891,7 @@
 #define __NR_mknodat                    (__NR_Linux + 253)
 #define __NR_fchownat                   (__NR_Linux + 254)
 #define __NR_futimesat                  (__NR_Linux + 255)
-#define __NR_fstatat                    (__NR_Linux + 256)
+#define __NR_newfstatat                 (__NR_Linux + 256)
 #define __NR_unlinkat                   (__NR_Linux + 257)
 #define __NR_renameat                   (__NR_Linux + 258)
 #define __NR_linkat                     (__NR_Linux + 259)
@@ -903,16 +907,18 @@
 #define __NR_tee                        (__NR_Linux + 269)
 #define __NR_vmsplice                   (__NR_Linux + 270)
 #define __NR_move_pages                 (__NR_Linux + 271)
+#define __NR_set_robust_list            (__NR_Linux + 272)
+#define __NR_get_robust_list            (__NR_Linux + 273)
 /*
 * Offset of the last N32 flavoured syscall
 */
-#define __NR_Linux_syscalls             271
+#define __NR_Linux_syscalls             273
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 #define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         271
+#define __NR_N32_Linux_syscalls         273
 #ifdef __KERNEL__
diff --git a/include/asm-mips/user.h b/include/asm-mips/user.h
index 89bf8b4cab3c..61f2a093b91b 100644
--- a/include/asm-mips/user.h
+++ b/include/asm-mips/user.h
@@ -8,6 +8,8 @@
 #ifndef _ASM_USER_H
 #define _ASM_USER_H
+#ifdef __KERNEL__
 #include <asm/page.h>
 #include <asm/reg.h>
@@ -55,4 +57,6 @@ struct user {
 #define HOST_DATA_START_ADDR    (u.start_data)
 #define HOST_STACK_END_ADDR     (u.start_stack + u.u_ssize * NBPG)
+#endif /* __KERNEL__ */
 #endif /* _ASM_USER_H */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index b9e263adebab..ab032ceafa84 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1483,9 +1483,6 @@
 #define PCI_DEVICE_ID_MARVELL_GT64260   0x6430
 #define PCI_DEVICE_ID_MARVELL_MV64360   0x6460
 #define PCI_DEVICE_ID_MARVELL_MV64460   0x6480
-#define PCI_DEVICE_ID_MARVELL_GT96100   0x9652
-#define PCI_DEVICE_ID_MARVELL_GT96100A  0x9653
 #define PCI_VENDOR_ID_V3                0x11b0
 #define PCI_DEVICE_ID_V3_V960           0x0001