diff options
| -rw-r--r-- | arch/ppc/platforms/83xx/mpc834x_sys.h | 6 | ||||
| -rw-r--r-- | arch/ppc/syslib/ppc83xx_setup.c | 28 |
2 files changed, 34 insertions, 0 deletions
diff --git a/arch/ppc/platforms/83xx/mpc834x_sys.h b/arch/ppc/platforms/83xx/mpc834x_sys.h index 49db0f4c847e..a2f6e49d7151 100644 --- a/arch/ppc/platforms/83xx/mpc834x_sys.h +++ b/arch/ppc/platforms/83xx/mpc834x_sys.h | |||
| @@ -28,6 +28,12 @@ | |||
| 28 | #define BCSR_PHYS_ADDR ((uint)0xf8000000) | 28 | #define BCSR_PHYS_ADDR ((uint)0xf8000000) |
| 29 | #define BCSR_SIZE ((uint)(32 * 1024)) | 29 | #define BCSR_SIZE ((uint)(32 * 1024)) |
| 30 | 30 | ||
| 31 | #define BCSR_MISC_REG2_OFF 0x07 | ||
| 32 | #define BCSR_MISC_REG2_PORESET 0x01 | ||
| 33 | |||
| 34 | #define BCSR_MISC_REG3_OFF 0x08 | ||
| 35 | #define BCSR_MISC_REG3_CNFLOCK 0x80 | ||
| 36 | |||
| 31 | #ifdef CONFIG_PCI | 37 | #ifdef CONFIG_PCI |
| 32 | /* PCI interrupt controller */ | 38 | /* PCI interrupt controller */ |
| 33 | #define PIRQA MPC83xx_IRQ_IRQ4 | 39 | #define PIRQA MPC83xx_IRQ_IRQ4 |
diff --git a/arch/ppc/syslib/ppc83xx_setup.c b/arch/ppc/syslib/ppc83xx_setup.c index c28f9d679484..843cf8873e60 100644 --- a/arch/ppc/syslib/ppc83xx_setup.c +++ b/arch/ppc/syslib/ppc83xx_setup.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #include <asm/mmu.h> | 29 | #include <asm/mmu.h> |
| 30 | #include <asm/ppc_sys.h> | 30 | #include <asm/ppc_sys.h> |
| 31 | #include <asm/kgdb.h> | 31 | #include <asm/kgdb.h> |
| 32 | #include <asm/delay.h> | ||
| 32 | 33 | ||
| 33 | #include <syslib/ppc83xx_setup.h> | 34 | #include <syslib/ppc83xx_setup.h> |
| 34 | 35 | ||
| @@ -117,7 +118,34 @@ mpc83xx_early_serial_map(void) | |||
| 117 | void | 118 | void |
| 118 | mpc83xx_restart(char *cmd) | 119 | mpc83xx_restart(char *cmd) |
| 119 | { | 120 | { |
| 121 | volatile unsigned char __iomem *reg; | ||
| 122 | unsigned char tmp; | ||
| 123 | |||
| 124 | reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE); | ||
| 125 | |||
| 120 | local_irq_disable(); | 126 | local_irq_disable(); |
| 127 | |||
| 128 | /* | ||
| 129 | * Unlock the BCSR bits so a PRST will update the contents. | ||
| 130 | * Otherwise the reset asserts but doesn't clear. | ||
| 131 | */ | ||
| 132 | tmp = in_8(reg + BCSR_MISC_REG3_OFF); | ||
| 133 | tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */ | ||
| 134 | out_8(reg + BCSR_MISC_REG3_OFF, tmp); | ||
| 135 | |||
| 136 | /* | ||
| 137 | * Trigger a reset via a low->high transition of the | ||
| 138 | * PORESET bit. | ||
| 139 | */ | ||
| 140 | tmp = in_8(reg + BCSR_MISC_REG2_OFF); | ||
| 141 | tmp &= ~BCSR_MISC_REG2_PORESET; | ||
| 142 | out_8(reg + BCSR_MISC_REG2_OFF, tmp); | ||
| 143 | |||
| 144 | udelay(1); | ||
| 145 | |||
| 146 | tmp |= BCSR_MISC_REG2_PORESET; | ||
| 147 | out_8(reg + BCSR_MISC_REG2_OFF, tmp); | ||
| 148 | |||
| 121 | for(;;); | 149 | for(;;); |
| 122 | } | 150 | } |
| 123 | 151 | ||
