diff options
| -rw-r--r-- | drivers/media/dvb/frontends/qt1010.c | 69 |
1 files changed, 44 insertions, 25 deletions
diff --git a/drivers/media/dvb/frontends/qt1010.c b/drivers/media/dvb/frontends/qt1010.c index 827cb0c625f9..825aa1412e6f 100644 --- a/drivers/media/dvb/frontends/qt1010.c +++ b/drivers/media/dvb/frontends/qt1010.c | |||
| @@ -25,14 +25,19 @@ static int debug; | |||
| 25 | module_param(debug, int, 0644); | 25 | module_param(debug, int, 0644); |
| 26 | MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off)."); | 26 | MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off)."); |
| 27 | 27 | ||
| 28 | #define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "QT1010: " args); printk("\n"); }} while (0) | 28 | #define dprintk(args...) \ |
| 29 | do { \ | ||
| 30 | if (debug) printk(KERN_DEBUG "QT1010: " args); \ | ||
| 31 | } while (0) | ||
| 29 | 32 | ||
| 30 | /* read single register */ | 33 | /* read single register */ |
| 31 | static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val) | 34 | static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val) |
| 32 | { | 35 | { |
| 33 | struct i2c_msg msg[2] = { | 36 | struct i2c_msg msg[2] = { |
| 34 | { .addr = priv->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 }, | 37 | { .addr = priv->cfg->i2c_address, |
| 35 | { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .buf = val, .len = 1 }, | 38 | .flags = 0, .buf = ®, .len = 1 }, |
| 39 | { .addr = priv->cfg->i2c_address, | ||
| 40 | .flags = I2C_M_RD, .buf = val, .len = 1 }, | ||
| 36 | }; | 41 | }; |
| 37 | 42 | ||
| 38 | if (i2c_transfer(priv->i2c, msg, 2) != 2) { | 43 | if (i2c_transfer(priv->i2c, msg, 2) != 2) { |
| @@ -46,9 +51,8 @@ static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val) | |||
| 46 | static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val) | 51 | static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val) |
| 47 | { | 52 | { |
| 48 | u8 buf[2] = { reg, val }; | 53 | u8 buf[2] = { reg, val }; |
| 49 | struct i2c_msg msg = { | 54 | struct i2c_msg msg = { .addr = priv->cfg->i2c_address, |
| 50 | .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2 | 55 | .flags = 0, .buf = buf, .len = 2 }; |
| 51 | }; | ||
| 52 | 56 | ||
| 53 | if (i2c_transfer(priv->i2c, &msg, 1) != 1) { | 57 | if (i2c_transfer(priv->i2c, &msg, 1) != 1) { |
| 54 | printk(KERN_WARNING "qt1010 I2C write failed\n"); | 58 | printk(KERN_WARNING "qt1010 I2C write failed\n"); |
| @@ -80,7 +84,8 @@ static void qt1010_dump_regs(struct qt1010_priv *priv) | |||
| 80 | printk("%s\n", buf); | 84 | printk("%s\n", buf); |
| 81 | } | 85 | } |
| 82 | 86 | ||
| 83 | static int qt1010_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) | 87 | static int qt1010_set_params(struct dvb_frontend *fe, |
| 88 | struct dvb_frontend_parameters *params) | ||
| 84 | { | 89 | { |
| 85 | struct qt1010_priv *priv; | 90 | struct qt1010_priv *priv; |
| 86 | int err; | 91 | int err; |
| @@ -146,7 +151,8 @@ static int qt1010_set_params(struct dvb_frontend *fe, struct dvb_frontend_parame | |||
| 146 | freq = (div * QT1010_STEP) - QT1010_OFFSET; | 151 | freq = (div * QT1010_STEP) - QT1010_OFFSET; |
| 147 | mod1 = (freq + QT1010_OFFSET) % FREQ1; | 152 | mod1 = (freq + QT1010_OFFSET) % FREQ1; |
| 148 | mod2 = (freq + QT1010_OFFSET) % FREQ2; | 153 | mod2 = (freq + QT1010_OFFSET) % FREQ2; |
| 149 | priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0; | 154 | priv->bandwidth = |
| 155 | (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0; | ||
| 150 | priv->frequency = freq; | 156 | priv->frequency = freq; |
| 151 | 157 | ||
| 152 | if (fe->ops.i2c_gate_ctrl) | 158 | if (fe->ops.i2c_gate_ctrl) |
| @@ -227,8 +233,9 @@ static int qt1010_set_params(struct dvb_frontend *fe, struct dvb_frontend_parame | |||
| 227 | /* 00 */ | 233 | /* 00 */ |
| 228 | rd[45].val = 0x92; /* TODO: correct value calculation */ | 234 | rd[45].val = 0x92; /* TODO: correct value calculation */ |
| 229 | 235 | ||
| 230 | dprintk("freq:%u 05:%02x 07:%02x 09:%02x 0a:%02x 0b:%02x 1a:%02x 11:%02x " \ | 236 | dprintk("freq:%u 05:%02x 07:%02x 09:%02x 0a:%02x 0b:%02x " \ |
| 231 | "12:%02x 22:%02x 05:%02x 1f:%02x 20:%02x 25:%02x 00:%02x", \ | 237 | "1a:%02x 11:%02x 12:%02x 22:%02x 05:%02x 1f:%02x " \ |
| 238 | "20:%02x 25:%02x 00:%02x", \ | ||
| 232 | freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, rd[8].val, \ | 239 | freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, rd[8].val, \ |
| 233 | rd[10].val, rd[13].val, rd[14].val, rd[15].val, rd[35].val, \ | 240 | rd[10].val, rd[13].val, rd[14].val, rd[15].val, rd[35].val, \ |
| 234 | rd[40].val, rd[41].val, rd[43].val, rd[45].val); | 241 | rd[40].val, rd[41].val, rd[43].val, rd[45].val); |
| @@ -251,7 +258,8 @@ static int qt1010_set_params(struct dvb_frontend *fe, struct dvb_frontend_parame | |||
| 251 | return 0; | 258 | return 0; |
| 252 | } | 259 | } |
| 253 | 260 | ||
| 254 | static int qt1010_init_meas1(struct qt1010_priv *priv, u8 oper, u8 reg, u8 reg_init_val, u8 *retval) | 261 | static int qt1010_init_meas1(struct qt1010_priv *priv, |
| 262 | u8 oper, u8 reg, u8 reg_init_val, u8 *retval) | ||
| 255 | { | 263 | { |
| 256 | u8 i, val1, val2; | 264 | u8 i, val1, val2; |
| 257 | int err; | 265 | int err; |
| @@ -265,7 +273,8 @@ static int qt1010_init_meas1(struct qt1010_priv *priv, u8 oper, u8 reg, u8 reg_i | |||
| 265 | 273 | ||
| 266 | for (i = 0; i < ARRAY_SIZE(i2c_data); i++) { | 274 | for (i = 0; i < ARRAY_SIZE(i2c_data); i++) { |
| 267 | if (i2c_data[i].oper == QT1010_WR) { | 275 | if (i2c_data[i].oper == QT1010_WR) { |
| 268 | err = qt1010_writereg(priv, i2c_data[i].reg, i2c_data[i].val); | 276 | err = qt1010_writereg(priv, i2c_data[i].reg, |
| 277 | i2c_data[i].val); | ||
| 269 | } else { | 278 | } else { |
| 270 | err = qt1010_readreg(priv, i2c_data[i].reg, &val2); | 279 | err = qt1010_readreg(priv, i2c_data[i].reg, &val2); |
| 271 | } | 280 | } |
| @@ -283,7 +292,8 @@ static int qt1010_init_meas1(struct qt1010_priv *priv, u8 oper, u8 reg, u8 reg_i | |||
| 283 | return qt1010_writereg(priv, 0x1e, 0x00); | 292 | return qt1010_writereg(priv, 0x1e, 0x00); |
| 284 | } | 293 | } |
| 285 | 294 | ||
| 286 | static u8 qt1010_init_meas2(struct qt1010_priv *priv, u8 reg_init_val, u8 *retval) | 295 | static u8 qt1010_init_meas2(struct qt1010_priv *priv, |
| 296 | u8 reg_init_val, u8 *retval) | ||
| 287 | { | 297 | { |
| 288 | u8 i, val; | 298 | u8 i, val; |
| 289 | int err; | 299 | int err; |
| @@ -298,7 +308,8 @@ static u8 qt1010_init_meas2(struct qt1010_priv *priv, u8 reg_init_val, u8 *retva | |||
| 298 | }; | 308 | }; |
| 299 | for (i = 0; i < ARRAY_SIZE(i2c_data); i++) { | 309 | for (i = 0; i < ARRAY_SIZE(i2c_data); i++) { |
| 300 | if (i2c_data[i].oper == QT1010_WR) { | 310 | if (i2c_data[i].oper == QT1010_WR) { |
| 301 | err = qt1010_writereg(priv, i2c_data[i].reg, i2c_data[i].val); | 311 | err = qt1010_writereg(priv, i2c_data[i].reg, |
| 312 | i2c_data[i].val); | ||
| 302 | } else { | 313 | } else { |
| 303 | err = qt1010_readreg(priv, i2c_data[i].reg, &val); | 314 | err = qt1010_readreg(priv, i2c_data[i].reg, &val); |
| 304 | } | 315 | } |
| @@ -358,19 +369,26 @@ static int qt1010_init(struct dvb_frontend *fe) | |||
| 358 | for (i = 0; i < ARRAY_SIZE(i2c_data); i++) { | 369 | for (i = 0; i < ARRAY_SIZE(i2c_data); i++) { |
| 359 | switch (i2c_data[i].oper) { | 370 | switch (i2c_data[i].oper) { |
| 360 | case QT1010_WR: | 371 | case QT1010_WR: |
| 361 | err = qt1010_writereg(priv, i2c_data[i].reg, i2c_data[i].val); | 372 | err = qt1010_writereg(priv, i2c_data[i].reg, |
| 373 | i2c_data[i].val); | ||
| 362 | break; | 374 | break; |
| 363 | case QT1010_RD: | 375 | case QT1010_RD: |
| 364 | if (i2c_data[i].val == 0x20) valptr = &priv->reg20_init_val; | 376 | if (i2c_data[i].val == 0x20) |
| 365 | else valptr = &tmpval; | 377 | valptr = &priv->reg20_init_val; |
| 378 | else | ||
| 379 | valptr = &tmpval; | ||
| 366 | err = qt1010_readreg(priv, i2c_data[i].reg, valptr); | 380 | err = qt1010_readreg(priv, i2c_data[i].reg, valptr); |
| 367 | break; | 381 | break; |
| 368 | case QT1010_M1: | 382 | case QT1010_M1: |
| 369 | if (i2c_data[i].val == 0x25) valptr = &priv->reg25_init_val; | 383 | if (i2c_data[i].val == 0x25) |
| 370 | else if (i2c_data[i].val == 0x1f) valptr = &priv->reg1f_init_val; | 384 | valptr = &priv->reg25_init_val; |
| 371 | else valptr = &tmpval; | 385 | else if (i2c_data[i].val == 0x1f) |
| 372 | err = qt1010_init_meas1(priv, i2c_data[i+1].reg, i2c_data[i].reg, | 386 | valptr = &priv->reg1f_init_val; |
| 373 | i2c_data[i].val, valptr); | 387 | else |
| 388 | valptr = &tmpval; | ||
| 389 | err = qt1010_init_meas1(priv, i2c_data[i+1].reg, | ||
| 390 | i2c_data[i].reg, | ||
| 391 | i2c_data[i].val, valptr); | ||
| 374 | i++; | 392 | i++; |
| 375 | break; | 393 | break; |
| 376 | } | 394 | } |
| @@ -435,8 +453,8 @@ struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe, | |||
| 435 | if (priv == NULL) | 453 | if (priv == NULL) |
| 436 | return NULL; | 454 | return NULL; |
| 437 | 455 | ||
| 438 | priv->cfg = cfg; | 456 | priv->cfg = cfg; |
| 439 | priv->i2c = i2c; | 457 | priv->i2c = i2c; |
| 440 | 458 | ||
| 441 | if (fe->ops.i2c_gate_ctrl) | 459 | if (fe->ops.i2c_gate_ctrl) |
| 442 | fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ | 460 | fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ |
| @@ -452,7 +470,8 @@ struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe, | |||
| 452 | fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */ | 470 | fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */ |
| 453 | 471 | ||
| 454 | printk(KERN_INFO "Quantek QT1010 successfully identified.\n"); | 472 | printk(KERN_INFO "Quantek QT1010 successfully identified.\n"); |
| 455 | memcpy(&fe->ops.tuner_ops, &qt1010_tuner_ops, sizeof(struct dvb_tuner_ops)); | 473 | memcpy(&fe->ops.tuner_ops, &qt1010_tuner_ops, |
| 474 | sizeof(struct dvb_tuner_ops)); | ||
| 456 | 475 | ||
| 457 | fe->tuner_priv = priv; | 476 | fe->tuner_priv = priv; |
| 458 | return fe; | 477 | return fe; |
