diff options
| -rw-r--r-- | arch/arm/include/asm/smp_twd.h | 17 | ||||
| -rw-r--r-- | arch/arm/kernel/smp_twd.c | 17 |
2 files changed, 17 insertions, 17 deletions
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h index 7be0978b2625..634f357be6bb 100644 --- a/arch/arm/include/asm/smp_twd.h +++ b/arch/arm/include/asm/smp_twd.h | |||
| @@ -1,6 +1,23 @@ | |||
| 1 | #ifndef __ASMARM_SMP_TWD_H | 1 | #ifndef __ASMARM_SMP_TWD_H |
| 2 | #define __ASMARM_SMP_TWD_H | 2 | #define __ASMARM_SMP_TWD_H |
| 3 | 3 | ||
| 4 | #define TWD_TIMER_LOAD 0x00 | ||
| 5 | #define TWD_TIMER_COUNTER 0x04 | ||
| 6 | #define TWD_TIMER_CONTROL 0x08 | ||
| 7 | #define TWD_TIMER_INTSTAT 0x0C | ||
| 8 | |||
| 9 | #define TWD_WDOG_LOAD 0x20 | ||
| 10 | #define TWD_WDOG_COUNTER 0x24 | ||
| 11 | #define TWD_WDOG_CONTROL 0x28 | ||
| 12 | #define TWD_WDOG_INTSTAT 0x2C | ||
| 13 | #define TWD_WDOG_RESETSTAT 0x30 | ||
| 14 | #define TWD_WDOG_DISABLE 0x34 | ||
| 15 | |||
| 16 | #define TWD_TIMER_CONTROL_ENABLE (1 << 0) | ||
| 17 | #define TWD_TIMER_CONTROL_ONESHOT (0 << 1) | ||
| 18 | #define TWD_TIMER_CONTROL_PERIODIC (1 << 1) | ||
| 19 | #define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) | ||
| 20 | |||
| 4 | struct clock_event_device; | 21 | struct clock_event_device; |
| 5 | 22 | ||
| 6 | extern void __iomem *twd_base; | 23 | extern void __iomem *twd_base; |
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index ea02a7b1c244..7c5f0c024db7 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c | |||
| @@ -21,23 +21,6 @@ | |||
| 21 | #include <asm/smp_twd.h> | 21 | #include <asm/smp_twd.h> |
| 22 | #include <asm/hardware/gic.h> | 22 | #include <asm/hardware/gic.h> |
| 23 | 23 | ||
| 24 | #define TWD_TIMER_LOAD 0x00 | ||
| 25 | #define TWD_TIMER_COUNTER 0x04 | ||
| 26 | #define TWD_TIMER_CONTROL 0x08 | ||
| 27 | #define TWD_TIMER_INTSTAT 0x0C | ||
| 28 | |||
| 29 | #define TWD_WDOG_LOAD 0x20 | ||
| 30 | #define TWD_WDOG_COUNTER 0x24 | ||
| 31 | #define TWD_WDOG_CONTROL 0x28 | ||
| 32 | #define TWD_WDOG_INTSTAT 0x2C | ||
| 33 | #define TWD_WDOG_RESETSTAT 0x30 | ||
| 34 | #define TWD_WDOG_DISABLE 0x34 | ||
| 35 | |||
| 36 | #define TWD_TIMER_CONTROL_ENABLE (1 << 0) | ||
| 37 | #define TWD_TIMER_CONTROL_ONESHOT (0 << 1) | ||
| 38 | #define TWD_TIMER_CONTROL_PERIODIC (1 << 1) | ||
| 39 | #define TWD_TIMER_CONTROL_IT_ENABLE (1 << 2) | ||
| 40 | |||
| 41 | /* set up by the platform code */ | 24 | /* set up by the platform code */ |
| 42 | void __iomem *twd_base; | 25 | void __iomem *twd_base; |
| 43 | 26 | ||
