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-rw-r--r--arch/arm/mach-davinci/Makefile1
-rw-r--r--arch/arm/mach-davinci/include/mach/memory.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/pm.h54
-rw-r--r--arch/arm/mach-davinci/pm.c158
-rw-r--r--arch/arm/mach-davinci/sleep.S224
5 files changed, 438 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index eeb9230d8844..d0fed3a67100 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -34,3 +34,4 @@ obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
34# Power Management 34# Power Management
35obj-$(CONFIG_CPU_FREQ) += cpufreq.o 35obj-$(CONFIG_CPU_FREQ) += cpufreq.o
36obj-$(CONFIG_CPU_IDLE) += cpuidle.o 36obj-$(CONFIG_CPU_IDLE) += cpuidle.o
37obj-$(CONFIG_SUSPEND) += pm.o sleep.o
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 7aeaf46cade0..a91edfb8beea 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -33,6 +33,7 @@
33 33
34#define DDR2_SDRCR_OFFSET 0xc 34#define DDR2_SDRCR_OFFSET 0xc
35#define DDR2_SRPD_BIT BIT(23) 35#define DDR2_SRPD_BIT BIT(23)
36#define DDR2_MCLKSTOPEN_BIT BIT(30)
36#define DDR2_LPMODEN_BIT BIT(31) 37#define DDR2_LPMODEN_BIT BIT(31)
37 38
38/* 39/*
diff --git a/arch/arm/mach-davinci/include/mach/pm.h b/arch/arm/mach-davinci/include/mach/pm.h
new file mode 100644
index 000000000000..37b19bf35a85
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/pm.h
@@ -0,0 +1,54 @@
1/*
2 * TI DaVinci platform support for power management.
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef _MACH_DAVINCI_PM_H
16#define _MACH_DAVINCI_PM_H
17
18/*
19 * Caution: Assembly code in sleep.S makes assumtion on the order
20 * of the members of this structure.
21 */
22struct davinci_pm_config {
23 void __iomem *ddr2_ctlr_base;
24 void __iomem *ddrpsc_reg_base;
25 int ddrpsc_num;
26 void __iomem *ddrpll_reg_base;
27 void __iomem *deepsleep_reg;
28 void __iomem *cpupll_reg_base;
29 /*
30 * Note on SLEEPCOUNT:
31 * The SLEEPCOUNT feature is mainly intended for cases in which
32 * the internal oscillator is used. The internal oscillator is
33 * fully disabled in deep sleep mode. When you exist deep sleep
34 * mode, the oscillator will be turned on and will generate very
35 * small oscillations which will not be detected by the deep sleep
36 * counter. Eventually those oscillations will grow to an amplitude
37 * large enough to start incrementing the deep sleep counter.
38 * In this case recommendation from hardware engineers is that the
39 * SLEEPCOUNT be set to 4096. This means that 4096 valid clock cycles
40 * must be detected before the clock is passed to the rest of the
41 * system.
42 * In the case that the internal oscillator is not used and the
43 * clock is generated externally, the SLEEPCOUNT value can be very
44 * small since the clock input is assumed to be stable before SoC
45 * is taken out of deepsleep mode. A value of 128 would be more than
46 * adequate.
47 */
48 int sleepcount;
49};
50
51extern unsigned int davinci_cpu_suspend_sz;
52extern void davinci_cpu_suspend(struct davinci_pm_config *);
53
54#endif
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
new file mode 100644
index 000000000000..fab953b43dea
--- /dev/null
+++ b/arch/arm/mach-davinci/pm.c
@@ -0,0 +1,158 @@
1/*
2 * DaVinci Power Management Routines
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/pm.h>
12#include <linux/suspend.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/spinlock.h>
17
18#include <asm/cacheflush.h>
19#include <asm/delay.h>
20
21#include <mach/da8xx.h>
22#include <mach/sram.h>
23#include <mach/pm.h>
24
25#include "clock.h"
26
27#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
28
29static void (*davinci_sram_suspend) (struct davinci_pm_config *);
30static struct davinci_pm_config *pdata;
31
32static void davinci_sram_push(void *dest, void *src, unsigned int size)
33{
34 memcpy(dest, src, size);
35 flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
36}
37
38static void davinci_pm_suspend(void)
39{
40 unsigned val;
41
42 if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
43
44 /* Switch CPU PLL to bypass mode */
45 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
46 val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
47 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
48
49 udelay(PLL_BYPASS_TIME);
50
51 /* Powerdown CPU PLL */
52 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
53 val |= PLLCTL_PLLPWRDN;
54 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
55 }
56
57 /* Configure sleep count in deep sleep register */
58 val = __raw_readl(pdata->deepsleep_reg);
59 val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
60 val |= pdata->sleepcount;
61 __raw_writel(val, pdata->deepsleep_reg);
62
63 /* System goes to sleep in this call */
64 davinci_sram_suspend(pdata);
65
66 if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
67
68 /* put CPU PLL in reset */
69 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
70 val &= ~PLLCTL_PLLRST;
71 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
72
73 /* put CPU PLL in power down */
74 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
75 val &= ~PLLCTL_PLLPWRDN;
76 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
77
78 /* wait for CPU PLL reset */
79 udelay(PLL_RESET_TIME);
80
81 /* bring CPU PLL out of reset */
82 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
83 val |= PLLCTL_PLLRST;
84 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
85
86 /* Wait for CPU PLL to lock */
87 udelay(PLL_LOCK_TIME);
88
89 /* Remove CPU PLL from bypass mode */
90 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
91 val &= ~PLLCTL_PLLENSRC;
92 val |= PLLCTL_PLLEN;
93 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
94 }
95}
96
97static int davinci_pm_enter(suspend_state_t state)
98{
99 int ret = 0;
100
101 switch (state) {
102 case PM_SUSPEND_STANDBY:
103 case PM_SUSPEND_MEM:
104 davinci_pm_suspend();
105 break;
106 default:
107 ret = -EINVAL;
108 }
109
110 return ret;
111}
112
113static struct platform_suspend_ops davinci_pm_ops = {
114 .enter = davinci_pm_enter,
115 .valid = suspend_valid_only_mem,
116};
117
118static int __init davinci_pm_probe(struct platform_device *pdev)
119{
120 pdata = pdev->dev.platform_data;
121 if (!pdata) {
122 dev_err(&pdev->dev, "cannot get platform data\n");
123 return -ENOENT;
124 }
125
126 davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
127 if (!davinci_sram_suspend) {
128 dev_err(&pdev->dev, "cannot allocate SRAM memory\n");
129 return -ENOMEM;
130 }
131
132 davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
133 davinci_cpu_suspend_sz);
134
135 suspend_set_ops(&davinci_pm_ops);
136
137 return 0;
138}
139
140static int __exit davinci_pm_remove(struct platform_device *pdev)
141{
142 sram_free(davinci_sram_suspend, davinci_cpu_suspend_sz);
143 return 0;
144}
145
146static struct platform_driver davinci_pm_driver = {
147 .driver = {
148 .name = "pm-davinci",
149 .owner = THIS_MODULE,
150 },
151 .remove = __exit_p(davinci_pm_remove),
152};
153
154static int __init davinci_pm_init(void)
155{
156 return platform_driver_probe(&davinci_pm_driver, davinci_pm_probe);
157}
158late_initcall(davinci_pm_init);
diff --git a/arch/arm/mach-davinci/sleep.S b/arch/arm/mach-davinci/sleep.S
new file mode 100644
index 000000000000..fb5e72b532b0
--- /dev/null
+++ b/arch/arm/mach-davinci/sleep.S
@@ -0,0 +1,224 @@
1/*
2 * (C) Copyright 2009, Texas Instruments, Inc. http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
16 * MA 02111-1307 USA
17 */
18
19/* replicated define because linux/bitops.h cannot be included in assembly */
20#define BIT(nr) (1 << (nr))
21
22#include <linux/linkage.h>
23#include <asm/assembler.h>
24#include <mach/psc.h>
25#include <mach/memory.h>
26
27#include "clock.h"
28
29/* Arbitrary, hardware currently does not update PHYRDY correctly */
30#define PHYRDY_CYCLES 0x1000
31
32/* Assume 25 MHz speed for the cycle conversions since PLLs are bypassed */
33#define PLL_BYPASS_CYCLES (PLL_BYPASS_TIME * 25)
34#define PLL_RESET_CYCLES (PLL_RESET_TIME * 25)
35#define PLL_LOCK_CYCLES (PLL_LOCK_TIME * 25)
36
37#define DEEPSLEEP_SLEEPENABLE_BIT BIT(31)
38
39 .text
40/*
41 * Move DaVinci into deep sleep state
42 *
43 * Note: This code is copied to internal SRAM by PM code. When the DaVinci
44 * wakes up it continues execution at the point it went to sleep.
45 * Register Usage:
46 * r0: contains virtual base for DDR2 controller
47 * r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
48 * r2: contains PSC number for DDR2
49 * r3: contains virtual base DDR2 PLL controller
50 * r4: contains virtual address of the DEEPSLEEP register
51 */
52ENTRY(davinci_cpu_suspend)
53 stmfd sp!, {r0-r12, lr} @ save registers on stack
54
55 ldr ip, CACHE_FLUSH
56 blx ip
57
58 ldmia r0, {r0-r4}
59
60 /*
61 * Switch DDR to self-refresh mode.
62 */
63
64 /* calculate SDRCR address */
65 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
66 bic ip, ip, #DDR2_SRPD_BIT
67 orr ip, ip, #DDR2_LPMODEN_BIT
68 str ip, [r0, #DDR2_SDRCR_OFFSET]
69
70 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
71 orr ip, ip, #DDR2_MCLKSTOPEN_BIT
72 str ip, [r0, #DDR2_SDRCR_OFFSET]
73
74 mov ip, #PHYRDY_CYCLES
751: subs ip, ip, #0x1
76 bne 1b
77
78 /* Disable DDR2 LPSC */
79 mov r7, r0
80 mov r0, #0x2
81 bl davinci_ddr_psc_config
82 mov r0, r7
83
84 /* Disable clock to DDR PHY */
85 ldr ip, [r3, #PLLDIV1]
86 bic ip, ip, #PLLDIV_EN
87 str ip, [r3, #PLLDIV1]
88
89 /* Put the DDR PLL in bypass and power down */
90 ldr ip, [r3, #PLLCTL]
91 bic ip, ip, #PLLCTL_PLLENSRC
92 bic ip, ip, #PLLCTL_PLLEN
93 str ip, [r3, #PLLCTL]
94
95 /* Wait for PLL to switch to bypass */
96 mov ip, #PLL_BYPASS_CYCLES
972: subs ip, ip, #0x1
98 bne 2b
99
100 /* Power down the PLL */
101 ldr ip, [r3, #PLLCTL]
102 orr ip, ip, #PLLCTL_PLLPWRDN
103 str ip, [r3, #PLLCTL]
104
105 /* Go to deep sleep */
106 ldr ip, [r4]
107 orr ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
108 /* System goes to sleep beyond after this instruction */
109 str ip, [r4]
110
111 /* Wake up from sleep */
112
113 /* Clear sleep enable */
114 ldr ip, [r4]
115 bic ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
116 str ip, [r4]
117
118 /* initialize the DDR PLL controller */
119
120 /* Put PLL in reset */
121 ldr ip, [r3, #PLLCTL]
122 bic ip, ip, #PLLCTL_PLLRST
123 str ip, [r3, #PLLCTL]
124
125 /* Clear PLL power down */
126 ldr ip, [r3, #PLLCTL]
127 bic ip, ip, #PLLCTL_PLLPWRDN
128 str ip, [r3, #PLLCTL]
129
130 mov ip, #PLL_RESET_CYCLES
1313: subs ip, ip, #0x1
132 bne 3b
133
134 /* Bring PLL out of reset */
135 ldr ip, [r3, #PLLCTL]
136 orr ip, ip, #PLLCTL_PLLRST
137 str ip, [r3, #PLLCTL]
138
139 /* Wait for PLL to lock (assume prediv = 1, 25MHz OSCIN) */
140 mov ip, #PLL_LOCK_CYCLES
1414: subs ip, ip, #0x1
142 bne 4b
143
144 /* Remove PLL from bypass mode */
145 ldr ip, [r3, #PLLCTL]
146 bic ip, ip, #PLLCTL_PLLENSRC
147 orr ip, ip, #PLLCTL_PLLEN
148 str ip, [r3, #PLLCTL]
149
150 /* Start 2x clock to DDR2 */
151
152 ldr ip, [r3, #PLLDIV1]
153 orr ip, ip, #PLLDIV_EN
154 str ip, [r3, #PLLDIV1]
155
156 /* Enable VCLK */
157
158 /* Enable DDR2 LPSC */
159 mov r7, r0
160 mov r0, #0x3
161 bl davinci_ddr_psc_config
162 mov r0, r7
163
164 /* clear MCLKSTOPEN */
165
166 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
167 bic ip, ip, #DDR2_MCLKSTOPEN_BIT
168 str ip, [r0, #DDR2_SDRCR_OFFSET]
169
170 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
171 bic ip, ip, #DDR2_LPMODEN_BIT
172 str ip, [r0, #DDR2_SDRCR_OFFSET]
173
174 /* Restore registers and return */
175 ldmfd sp!, {r0-r12, pc}
176
177ENDPROC(davinci_cpu_suspend)
178
179/*
180 * Disables or Enables DDR2 LPSC
181 * Register Usage:
182 * r0: Enable or Disable LPSC r0 = 0x3 => Enable, r0 = 0x2 => Disable LPSC
183 * r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
184 * r2: contains PSC number for DDR2
185 */
186ENTRY(davinci_ddr_psc_config)
187 /* Set next state in mdctl for DDR2 */
188 mov r6, #MDCTL
189 add r6, r6, r2, lsl #2
190 ldr ip, [r1, r6]
191 bic ip, ip, #MDSTAT_STATE_MASK
192 orr ip, ip, r0
193 str ip, [r1, r6]
194
195 /* Enable the Power Domain Transition Command */
196 ldr ip, [r1, #PTCMD]
197 orr ip, ip, #0x1
198 str ip, [r1, #PTCMD]
199
200 /* Check for Transition Complete (PTSTAT) */
201ptstat_done:
202 ldr ip, [r1, #PTSTAT]
203 and ip, ip, #0x1
204 cmp ip, #0x0
205 bne ptstat_done
206
207 /* Check for DDR2 clock disable completion; */
208 mov r6, #MDSTAT
209 add r6, r6, r2, lsl #2
210ddr2clk_stop_done:
211 ldr ip, [r1, r6]
212 and ip, ip, #MDSTAT_STATE_MASK
213 cmp ip, r0
214 bne ddr2clk_stop_done
215
216 mov pc, lr
217ENDPROC(davinci_ddr_psc_config)
218
219CACHE_FLUSH:
220 .word arm926_flush_kern_cache_all
221
222ENTRY(davinci_cpu_suspend_sz)
223 .word . - davinci_cpu_suspend
224ENDPROC(davinci_cpu_suspend_sz)
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