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-rw-r--r--arch/sparc/kernel/sun4m_smp.c2
-rw-r--r--arch/sparc64/defconfig71
-rw-r--r--arch/sparc64/kernel/Makefile2
-rw-r--r--arch/sparc64/kernel/central.c6
-rw-r--r--arch/sparc64/kernel/irq.c16
-rw-r--r--arch/sparc64/kernel/pci.c37
-rw-r--r--arch/sparc64/kernel/pci_fire.c418
-rw-r--r--arch/sparc64/kernel/pci_iommu.c22
-rw-r--r--arch/sparc64/kernel/prom.c112
-rw-r--r--drivers/scsi/sun_esp.c1
-rw-r--r--drivers/serial/sunsu.c8
-rw-r--r--drivers/video/Kconfig26
-rw-r--r--drivers/video/Makefile2
-rw-r--r--drivers/video/sunxvr2500.c277
-rw-r--r--drivers/video/sunxvr500.c443
-rw-r--r--include/asm-sparc64/iommu.h1
-rw-r--r--mm/sparse.c2
17 files changed, 1365 insertions, 81 deletions
diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c
index e2d9c018bd56..4e07bdbbfb5d 100644
--- a/arch/sparc/kernel/sun4m_smp.c
+++ b/arch/sparc/kernel/sun4m_smp.c
@@ -405,7 +405,7 @@ void __init smp4m_blackbox_current(unsigned *addr)
405 405
406 addr[0] = 0x81580000 | rd; /* rd %tbr, reg */ 406 addr[0] = 0x81580000 | rd; /* rd %tbr, reg */
407 addr[2] = 0x8130200a | rd | rs1; /* srl reg, 0xa, reg */ 407 addr[2] = 0x8130200a | rd | rs1; /* srl reg, 0xa, reg */
408 addr[4] = 0x8008200c | rd | rs1; /* and reg, 3, reg */ 408 addr[4] = 0x8008200c | rd | rs1; /* and reg, 0xc, reg */
409} 409}
410 410
411void __init sun4m_init_smp(void) 411void __init sun4m_init_smp(void)
diff --git a/arch/sparc64/defconfig b/arch/sparc64/defconfig
index 120c9c33b7a6..37c2d3695658 100644
--- a/arch/sparc64/defconfig
+++ b/arch/sparc64/defconfig
@@ -1,15 +1,16 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.21-rc4 3# Linux kernel version: 2.6.21
4# Sat Mar 17 14:18:44 2007 4# Sun May 6 22:46:54 2007
5# 5#
6CONFIG_SPARC=y 6CONFIG_SPARC=y
7CONFIG_SPARC64=y 7CONFIG_SPARC64=y
8CONFIG_GENERIC_TIME=y
9CONFIG_GENERIC_CLOCKEVENTS=y
8CONFIG_64BIT=y 10CONFIG_64BIT=y
9CONFIG_MMU=y 11CONFIG_MMU=y
10CONFIG_STACKTRACE_SUPPORT=y 12CONFIG_STACKTRACE_SUPPORT=y
11CONFIG_LOCKDEP_SUPPORT=y 13CONFIG_LOCKDEP_SUPPORT=y
12CONFIG_TIME_INTERPOLATION=y
13CONFIG_ARCH_MAY_HAVE_PC_FDC=y 14CONFIG_ARCH_MAY_HAVE_PC_FDC=y
14# CONFIG_ARCH_HAS_ILOG2_U32 is not set 15# CONFIG_ARCH_HAS_ILOG2_U32 is not set
15# CONFIG_ARCH_HAS_ILOG2_U64 is not set 16# CONFIG_ARCH_HAS_ILOG2_U64 is not set
@@ -108,6 +109,9 @@ CONFIG_GENERIC_HARDIRQS=y
108# 109#
109# General machine setup 110# General machine setup
110# 111#
112CONFIG_TICK_ONESHOT=y
113CONFIG_NO_HZ=y
114CONFIG_HIGH_RES_TIMERS=y
111# CONFIG_SMP is not set 115# CONFIG_SMP is not set
112CONFIG_CPU_FREQ=y 116CONFIG_CPU_FREQ=y
113CONFIG_CPU_FREQ_TABLE=m 117CONFIG_CPU_FREQ_TABLE=m
@@ -140,8 +144,7 @@ CONFIG_SELECT_MEMORY_MODEL=y
140CONFIG_SPARSEMEM_MANUAL=y 144CONFIG_SPARSEMEM_MANUAL=y
141CONFIG_SPARSEMEM=y 145CONFIG_SPARSEMEM=y
142CONFIG_HAVE_MEMORY_PRESENT=y 146CONFIG_HAVE_MEMORY_PRESENT=y
143# CONFIG_SPARSEMEM_STATIC is not set 147CONFIG_SPARSEMEM_STATIC=y
144CONFIG_SPARSEMEM_EXTREME=y
145CONFIG_SPLIT_PTLOCK_CPUS=4 148CONFIG_SPLIT_PTLOCK_CPUS=4
146CONFIG_RESOURCES_64BIT=y 149CONFIG_RESOURCES_64BIT=y
147CONFIG_ZONE_DMA_FLAG=0 150CONFIG_ZONE_DMA_FLAG=0
@@ -151,6 +154,7 @@ CONFIG_SUN_AUXIO=y
151CONFIG_SUN_IO=y 154CONFIG_SUN_IO=y
152CONFIG_PCI=y 155CONFIG_PCI=y
153CONFIG_PCI_DOMAINS=y 156CONFIG_PCI_DOMAINS=y
157CONFIG_ARCH_SUPPORTS_MSI=y
154CONFIG_PCI_MSI=y 158CONFIG_PCI_MSI=y
155# CONFIG_PCI_DEBUG is not set 159# CONFIG_PCI_DEBUG is not set
156CONFIG_SUN_OPENPROMFS=m 160CONFIG_SUN_OPENPROMFS=m
@@ -178,7 +182,6 @@ CONFIG_NET=y
178# 182#
179# Networking options 183# Networking options
180# 184#
181# CONFIG_NETDEBUG is not set
182CONFIG_PACKET=y 185CONFIG_PACKET=y
183CONFIG_PACKET_MMAP=y 186CONFIG_PACKET_MMAP=y
184CONFIG_UNIX=y 187CONFIG_UNIX=y
@@ -219,6 +222,7 @@ CONFIG_IPV6=m
219CONFIG_IPV6_PRIVACY=y 222CONFIG_IPV6_PRIVACY=y
220CONFIG_IPV6_ROUTER_PREF=y 223CONFIG_IPV6_ROUTER_PREF=y
221CONFIG_IPV6_ROUTE_INFO=y 224CONFIG_IPV6_ROUTE_INFO=y
225CONFIG_IPV6_OPTIMISTIC_DAD=y
222CONFIG_INET6_AH=m 226CONFIG_INET6_AH=m
223CONFIG_INET6_ESP=m 227CONFIG_INET6_ESP=m
224CONFIG_INET6_IPCOMP=m 228CONFIG_INET6_IPCOMP=m
@@ -292,6 +296,14 @@ CONFIG_NET_TCPPROBE=m
292# CONFIG_HAMRADIO is not set 296# CONFIG_HAMRADIO is not set
293# CONFIG_IRDA is not set 297# CONFIG_IRDA is not set
294# CONFIG_BT is not set 298# CONFIG_BT is not set
299# CONFIG_AF_RXRPC is not set
300
301#
302# Wireless
303#
304# CONFIG_CFG80211 is not set
305# CONFIG_WIRELESS_EXT is not set
306# CONFIG_MAC80211 is not set
295# CONFIG_IEEE80211 is not set 307# CONFIG_IEEE80211 is not set
296 308
297# 309#
@@ -312,10 +324,6 @@ CONFIG_FW_LOADER=y
312# Connector - unified userspace <-> kernelspace linker 324# Connector - unified userspace <-> kernelspace linker
313# 325#
314CONFIG_CONNECTOR=m 326CONFIG_CONNECTOR=m
315
316#
317# Memory Technology Devices (MTD)
318#
319# CONFIG_MTD is not set 327# CONFIG_MTD is not set
320 328
321# 329#
@@ -383,7 +391,6 @@ CONFIG_BLK_DEV_IDEPCI=y
383# CONFIG_BLK_DEV_OPTI621 is not set 391# CONFIG_BLK_DEV_OPTI621 is not set
384CONFIG_BLK_DEV_IDEDMA_PCI=y 392CONFIG_BLK_DEV_IDEDMA_PCI=y
385# CONFIG_BLK_DEV_IDEDMA_FORCED is not set 393# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
386CONFIG_IDEDMA_PCI_AUTO=y
387CONFIG_IDEDMA_ONLYDISK=y 394CONFIG_IDEDMA_ONLYDISK=y
388# CONFIG_BLK_DEV_AEC62XX is not set 395# CONFIG_BLK_DEV_AEC62XX is not set
389CONFIG_BLK_DEV_ALI15X3=y 396CONFIG_BLK_DEV_ALI15X3=y
@@ -413,7 +420,6 @@ CONFIG_BLK_DEV_ALI15X3=y
413# CONFIG_IDE_ARM is not set 420# CONFIG_IDE_ARM is not set
414CONFIG_BLK_DEV_IDEDMA=y 421CONFIG_BLK_DEV_IDEDMA=y
415# CONFIG_IDEDMA_IVB is not set 422# CONFIG_IDEDMA_IVB is not set
416CONFIG_IDEDMA_AUTO=y
417# CONFIG_BLK_DEV_HD is not set 423# CONFIG_BLK_DEV_HD is not set
418 424
419# 425#
@@ -443,6 +449,7 @@ CONFIG_SCSI_MULTI_LUN=y
443CONFIG_SCSI_CONSTANTS=y 449CONFIG_SCSI_CONSTANTS=y
444# CONFIG_SCSI_LOGGING is not set 450# CONFIG_SCSI_LOGGING is not set
445# CONFIG_SCSI_SCAN_ASYNC is not set 451# CONFIG_SCSI_SCAN_ASYNC is not set
452CONFIG_SCSI_WAIT_SCAN=m
446 453
447# 454#
448# SCSI Transports 455# SCSI Transports
@@ -485,6 +492,7 @@ CONFIG_ISCSI_TCP=m
485# CONFIG_SCSI_DC395x is not set 492# CONFIG_SCSI_DC395x is not set
486# CONFIG_SCSI_DC390T is not set 493# CONFIG_SCSI_DC390T is not set
487# CONFIG_SCSI_DEBUG is not set 494# CONFIG_SCSI_DEBUG is not set
495# CONFIG_SCSI_ESP_CORE is not set
488# CONFIG_SCSI_SUNESP is not set 496# CONFIG_SCSI_SUNESP is not set
489# CONFIG_SCSI_SRP is not set 497# CONFIG_SCSI_SRP is not set
490 498
@@ -628,9 +636,10 @@ CONFIG_BNX2=m
628# CONFIG_TR is not set 636# CONFIG_TR is not set
629 637
630# 638#
631# Wireless LAN (non-hamradio) 639# Wireless LAN
632# 640#
633# CONFIG_NET_RADIO is not set 641# CONFIG_WLAN_PRE80211 is not set
642# CONFIG_WLAN_80211 is not set
634 643
635# 644#
636# Wan interfaces 645# Wan interfaces
@@ -695,6 +704,12 @@ CONFIG_KEYBOARD_LKKBD=m
695# CONFIG_KEYBOARD_STOWAWAY is not set 704# CONFIG_KEYBOARD_STOWAWAY is not set
696CONFIG_INPUT_MOUSE=y 705CONFIG_INPUT_MOUSE=y
697CONFIG_MOUSE_PS2=y 706CONFIG_MOUSE_PS2=y
707CONFIG_MOUSE_PS2_ALPS=y
708CONFIG_MOUSE_PS2_LOGIPS2PP=y
709CONFIG_MOUSE_PS2_SYNAPTICS=y
710CONFIG_MOUSE_PS2_LIFEBOOK=y
711CONFIG_MOUSE_PS2_TRACKPOINT=y
712# CONFIG_MOUSE_PS2_TOUCHKIT is not set
698CONFIG_MOUSE_SERIAL=y 713CONFIG_MOUSE_SERIAL=y
699# CONFIG_MOUSE_VSXXXAA is not set 714# CONFIG_MOUSE_VSXXXAA is not set
700# CONFIG_INPUT_JOYSTICK is not set 715# CONFIG_INPUT_JOYSTICK is not set
@@ -702,6 +717,7 @@ CONFIG_MOUSE_SERIAL=y
702CONFIG_INPUT_MISC=y 717CONFIG_INPUT_MISC=y
703CONFIG_INPUT_SPARCSPKR=y 718CONFIG_INPUT_SPARCSPKR=y
704# CONFIG_INPUT_UINPUT is not set 719# CONFIG_INPUT_UINPUT is not set
720# CONFIG_INPUT_POLLDEV is not set
705 721
706# 722#
707# Hardware I/O ports 723# Hardware I/O ports
@@ -763,11 +779,8 @@ CONFIG_RTC=y
763# TPM devices 779# TPM devices
764# 780#
765# CONFIG_TCG_TPM is not set 781# CONFIG_TCG_TPM is not set
766
767#
768# I2C support
769#
770CONFIG_I2C=y 782CONFIG_I2C=y
783CONFIG_I2C_BOARDINFO=y
771# CONFIG_I2C_CHARDEV is not set 784# CONFIG_I2C_CHARDEV is not set
772 785
773# 786#
@@ -791,17 +804,17 @@ CONFIG_I2C_ALGOBIT=y
791# CONFIG_I2C_NFORCE2 is not set 804# CONFIG_I2C_NFORCE2 is not set
792# CONFIG_I2C_OCORES is not set 805# CONFIG_I2C_OCORES is not set
793# CONFIG_I2C_PARPORT_LIGHT is not set 806# CONFIG_I2C_PARPORT_LIGHT is not set
794# CONFIG_I2C_PASEMI is not set
795# CONFIG_I2C_PROSAVAGE is not set 807# CONFIG_I2C_PROSAVAGE is not set
796# CONFIG_I2C_SAVAGE4 is not set 808# CONFIG_I2C_SAVAGE4 is not set
809# CONFIG_I2C_SIMTEC is not set
797# CONFIG_I2C_SIS5595 is not set 810# CONFIG_I2C_SIS5595 is not set
798# CONFIG_I2C_SIS630 is not set 811# CONFIG_I2C_SIS630 is not set
799# CONFIG_I2C_SIS96X is not set 812# CONFIG_I2C_SIS96X is not set
800# CONFIG_I2C_STUB is not set 813# CONFIG_I2C_STUB is not set
814# CONFIG_I2C_TINY_USB is not set
801# CONFIG_I2C_VIA is not set 815# CONFIG_I2C_VIA is not set
802# CONFIG_I2C_VIAPRO is not set 816# CONFIG_I2C_VIAPRO is not set
803# CONFIG_I2C_VOODOO3 is not set 817# CONFIG_I2C_VOODOO3 is not set
804# CONFIG_I2C_PCA_ISA is not set
805 818
806# 819#
807# Miscellaneous I2C Chip support 820# Miscellaneous I2C Chip support
@@ -912,7 +925,7 @@ CONFIG_FB_MODE_HELPERS=y
912CONFIG_FB_TILEBLITTING=y 925CONFIG_FB_TILEBLITTING=y
913 926
914# 927#
915# Frambuffer hardware drivers 928# Frame buffer hardware drivers
916# 929#
917# CONFIG_FB_CIRRUS is not set 930# CONFIG_FB_CIRRUS is not set
918# CONFIG_FB_PM2 is not set 931# CONFIG_FB_PM2 is not set
@@ -937,6 +950,8 @@ CONFIG_FB_RADEON_I2C=y
937# CONFIG_FB_3DFX is not set 950# CONFIG_FB_3DFX is not set
938# CONFIG_FB_VOODOO1 is not set 951# CONFIG_FB_VOODOO1 is not set
939# CONFIG_FB_TRIDENT is not set 952# CONFIG_FB_TRIDENT is not set
953# CONFIG_FB_XVR500 is not set
954# CONFIG_FB_XVR2500 is not set
940# CONFIG_FB_PCI is not set 955# CONFIG_FB_PCI is not set
941# CONFIG_FB_VIRTUAL is not set 956# CONFIG_FB_VIRTUAL is not set
942 957
@@ -1094,6 +1109,14 @@ CONFIG_HID=y
1094# CONFIG_HID_DEBUG is not set 1109# CONFIG_HID_DEBUG is not set
1095 1110
1096# 1111#
1112# USB Input Devices
1113#
1114CONFIG_USB_HID=y
1115# CONFIG_USB_HIDINPUT_POWERBOOK is not set
1116# CONFIG_HID_FF is not set
1117CONFIG_USB_HIDDEV=y
1118
1119#
1097# USB support 1120# USB support
1098# 1121#
1099CONFIG_USB_ARCH_HAS_HCD=y 1122CONFIG_USB_ARCH_HAS_HCD=y
@@ -1106,6 +1129,7 @@ CONFIG_USB=y
1106# Miscellaneous USB options 1129# Miscellaneous USB options
1107# 1130#
1108CONFIG_USB_DEVICEFS=y 1131CONFIG_USB_DEVICEFS=y
1132# CONFIG_USB_DEVICE_CLASS is not set
1109# CONFIG_USB_DYNAMIC_MINORS is not set 1133# CONFIG_USB_DYNAMIC_MINORS is not set
1110# CONFIG_USB_OTG is not set 1134# CONFIG_USB_OTG is not set
1111 1135
@@ -1156,10 +1180,6 @@ CONFIG_USB_STORAGE=m
1156# 1180#
1157# USB Input Devices 1181# USB Input Devices
1158# 1182#
1159CONFIG_USB_HID=y
1160# CONFIG_USB_HIDINPUT_POWERBOOK is not set
1161# CONFIG_HID_FF is not set
1162CONFIG_USB_HIDDEV=y
1163# CONFIG_USB_AIPTEK is not set 1183# CONFIG_USB_AIPTEK is not set
1164# CONFIG_USB_WACOM is not set 1184# CONFIG_USB_WACOM is not set
1165# CONFIG_USB_ACECAD is not set 1185# CONFIG_USB_ACECAD is not set
@@ -1524,6 +1544,7 @@ CONFIG_CRYPTO_ECB=m
1524CONFIG_CRYPTO_CBC=y 1544CONFIG_CRYPTO_CBC=y
1525CONFIG_CRYPTO_PCBC=m 1545CONFIG_CRYPTO_PCBC=m
1526CONFIG_CRYPTO_LRW=m 1546CONFIG_CRYPTO_LRW=m
1547# CONFIG_CRYPTO_CRYPTD is not set
1527CONFIG_CRYPTO_DES=y 1548CONFIG_CRYPTO_DES=y
1528CONFIG_CRYPTO_FCRYPT=m 1549CONFIG_CRYPTO_FCRYPT=m
1529CONFIG_CRYPTO_BLOWFISH=m 1550CONFIG_CRYPTO_BLOWFISH=m
diff --git a/arch/sparc64/kernel/Makefile b/arch/sparc64/kernel/Makefile
index eff0c01d3579..6bf6fb65bc20 100644
--- a/arch/sparc64/kernel/Makefile
+++ b/arch/sparc64/kernel/Makefile
@@ -17,7 +17,7 @@ obj-y := process.o setup.o cpu.o idprom.o \
17obj-$(CONFIG_STACKTRACE) += stacktrace.o 17obj-$(CONFIG_STACKTRACE) += stacktrace.o
18obj-$(CONFIG_PCI) += ebus.o isa.o pci_common.o pci_iommu.o \ 18obj-$(CONFIG_PCI) += ebus.o isa.o pci_common.o pci_iommu.o \
19 pci_psycho.o pci_sabre.o pci_schizo.o \ 19 pci_psycho.o pci_sabre.o pci_schizo.o \
20 pci_sun4v.o pci_sun4v_asm.o 20 pci_sun4v.o pci_sun4v_asm.o pci_fire.o
21obj-$(CONFIG_SMP) += smp.o trampoline.o 21obj-$(CONFIG_SMP) += smp.o trampoline.o
22obj-$(CONFIG_SPARC32_COMPAT) += sys32.o sys_sparc32.o signal32.o 22obj-$(CONFIG_SPARC32_COMPAT) += sys32.o sys_sparc32.o signal32.o
23obj-$(CONFIG_BINFMT_ELF32) += binfmt_elf32.o 23obj-$(CONFIG_BINFMT_ELF32) += binfmt_elf32.o
diff --git a/arch/sparc64/kernel/central.c b/arch/sparc64/kernel/central.c
index c65b2f9c98d8..8230099f0d8a 100644
--- a/arch/sparc64/kernel/central.c
+++ b/arch/sparc64/kernel/central.c
@@ -98,7 +98,7 @@ void apply_central_ranges(struct linux_central *central,
98 central->num_central_ranges); 98 central->num_central_ranges);
99} 99}
100 100
101void * __init central_alloc_bootmem(unsigned long size) 101static void * __init central_alloc_bootmem(unsigned long size)
102{ 102{
103 void *ret; 103 void *ret;
104 104
@@ -116,7 +116,7 @@ static unsigned long prom_reg_to_paddr(struct linux_prom_registers *r)
116 return ret | (unsigned long) r->phys_addr; 116 return ret | (unsigned long) r->phys_addr;
117} 117}
118 118
119static void probe_other_fhcs(void) 119static void __init probe_other_fhcs(void)
120{ 120{
121 struct device_node *dp; 121 struct device_node *dp;
122 const struct linux_prom64_registers *fpregs; 122 const struct linux_prom64_registers *fpregs;
@@ -298,7 +298,7 @@ static void init_all_fhc_hw(void)
298 298
299} 299}
300 300
301void central_probe(void) 301void __init central_probe(void)
302{ 302{
303 struct linux_prom_registers fpregs[6]; 303 struct linux_prom_registers fpregs[6];
304 const struct linux_prom_registers *pr; 304 const struct linux_prom_registers *pr;
diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c
index 6241e3dbbd57..3edc18e1b818 100644
--- a/arch/sparc64/kernel/irq.c
+++ b/arch/sparc64/kernel/irq.c
@@ -279,7 +279,7 @@ static void sun4u_irq_enable(unsigned int virt_irq)
279 struct irq_handler_data *data = get_irq_chip_data(virt_irq); 279 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
280 280
281 if (likely(data)) { 281 if (likely(data)) {
282 unsigned long cpuid, imap; 282 unsigned long cpuid, imap, val;
283 unsigned int tid; 283 unsigned int tid;
284 284
285 cpuid = irq_choose_cpu(virt_irq); 285 cpuid = irq_choose_cpu(virt_irq);
@@ -287,7 +287,11 @@ static void sun4u_irq_enable(unsigned int virt_irq)
287 287
288 tid = sun4u_compute_tid(imap, cpuid); 288 tid = sun4u_compute_tid(imap, cpuid);
289 289
290 upa_writel(tid | IMAP_VALID, imap); 290 val = upa_readq(imap);
291 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
292 IMAP_AID_SAFARI | IMAP_NID_SAFARI);
293 val |= tid | IMAP_VALID;
294 upa_writeq(val, imap);
291 } 295 }
292} 296}
293 297
@@ -297,10 +301,10 @@ static void sun4u_irq_disable(unsigned int virt_irq)
297 301
298 if (likely(data)) { 302 if (likely(data)) {
299 unsigned long imap = data->imap; 303 unsigned long imap = data->imap;
300 u32 tmp = upa_readl(imap); 304 u32 tmp = upa_readq(imap);
301 305
302 tmp &= ~IMAP_VALID; 306 tmp &= ~IMAP_VALID;
303 upa_writel(tmp, imap); 307 upa_writeq(tmp, imap);
304 } 308 }
305} 309}
306 310
@@ -309,7 +313,7 @@ static void sun4u_irq_end(unsigned int virt_irq)
309 struct irq_handler_data *data = get_irq_chip_data(virt_irq); 313 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
310 314
311 if (likely(data)) 315 if (likely(data))
312 upa_writel(ICLR_IDLE, data->iclr); 316 upa_writeq(ICLR_IDLE, data->iclr);
313} 317}
314 318
315static void sun4v_irq_enable(unsigned int virt_irq) 319static void sun4v_irq_enable(unsigned int virt_irq)
@@ -465,7 +469,7 @@ unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
465 469
466 BUG_ON(tlb_type == hypervisor); 470 BUG_ON(tlb_type == hypervisor);
467 471
468 ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; 472 ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
469 bucket = &ivector_table[ino]; 473 bucket = &ivector_table[ino];
470 if (!bucket->virt_irq) { 474 if (!bucket->virt_irq) {
471 bucket->virt_irq = virt_irq_alloc(__irq(bucket)); 475 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
diff --git a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
index 9a549547cb2b..af2c7ff01eeb 100644
--- a/arch/sparc64/kernel/pci.c
+++ b/arch/sparc64/kernel/pci.c
@@ -190,6 +190,7 @@ extern void schizo_init(struct device_node *, const char *);
190extern void schizo_plus_init(struct device_node *, const char *); 190extern void schizo_plus_init(struct device_node *, const char *);
191extern void tomatillo_init(struct device_node *, const char *); 191extern void tomatillo_init(struct device_node *, const char *);
192extern void sun4v_pci_init(struct device_node *, const char *); 192extern void sun4v_pci_init(struct device_node *, const char *);
193extern void fire_pci_init(struct device_node *, const char *);
193 194
194static struct { 195static struct {
195 char *model_name; 196 char *model_name;
@@ -207,6 +208,7 @@ static struct {
207 { "SUNW,tomatillo", tomatillo_init }, 208 { "SUNW,tomatillo", tomatillo_init },
208 { "pci108e,a801", tomatillo_init }, 209 { "pci108e,a801", tomatillo_init },
209 { "SUNW,sun4v-pci", sun4v_pci_init }, 210 { "SUNW,sun4v-pci", sun4v_pci_init },
211 { "pciex108e,80f0", fire_pci_init },
210}; 212};
211#define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \ 213#define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
212 sizeof(pci_controller_table[0])) 214 sizeof(pci_controller_table[0]))
@@ -436,6 +438,13 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
436 printk(" class: 0x%x device name: %s\n", 438 printk(" class: 0x%x device name: %s\n",
437 dev->class, pci_name(dev)); 439 dev->class, pci_name(dev));
438 440
441 /* I have seen IDE devices which will not respond to
442 * the bmdma simplex check reads if bus mastering is
443 * disabled.
444 */
445 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
446 pci_set_master(dev);
447
439 dev->current_state = 4; /* unknown power state */ 448 dev->current_state = 4; /* unknown power state */
440 dev->error_state = pci_channel_io_normal; 449 dev->error_state = pci_channel_io_normal;
441 450
@@ -468,7 +477,7 @@ struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
468 return dev; 477 return dev;
469} 478}
470 479
471static void __init apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) 480static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
472{ 481{
473 u32 idx, first, last; 482 u32 idx, first, last;
474 483
@@ -497,9 +506,9 @@ static void __init pci_resource_adjust(struct resource *res,
497/* Cook up fake bus resources for SUNW,simba PCI bridges which lack 506/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
498 * a proper 'ranges' property. 507 * a proper 'ranges' property.
499 */ 508 */
500static void __init apb_fake_ranges(struct pci_dev *dev, 509static void __devinit apb_fake_ranges(struct pci_dev *dev,
501 struct pci_bus *bus, 510 struct pci_bus *bus,
502 struct pci_pbm_info *pbm) 511 struct pci_pbm_info *pbm)
503{ 512{
504 struct resource *res; 513 struct resource *res;
505 u32 first, last; 514 u32 first, last;
@@ -522,15 +531,15 @@ static void __init apb_fake_ranges(struct pci_dev *dev,
522 pci_resource_adjust(res, &pbm->mem_space); 531 pci_resource_adjust(res, &pbm->mem_space);
523} 532}
524 533
525static void __init pci_of_scan_bus(struct pci_pbm_info *pbm, 534static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
526 struct device_node *node, 535 struct device_node *node,
527 struct pci_bus *bus); 536 struct pci_bus *bus);
528 537
529#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) 538#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
530 539
531void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, 540static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
532 struct device_node *node, 541 struct device_node *node,
533 struct pci_dev *dev) 542 struct pci_dev *dev)
534{ 543{
535 struct pci_bus *bus; 544 struct pci_bus *bus;
536 const u32 *busrange, *ranges; 545 const u32 *busrange, *ranges;
@@ -629,9 +638,9 @@ simba_cont:
629 pci_of_scan_bus(pbm, node, bus); 638 pci_of_scan_bus(pbm, node, bus);
630} 639}
631 640
632static void __init pci_of_scan_bus(struct pci_pbm_info *pbm, 641static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
633 struct device_node *node, 642 struct device_node *node,
634 struct pci_bus *bus) 643 struct pci_bus *bus)
635{ 644{
636 struct device_node *child; 645 struct device_node *child;
637 const u32 *reg; 646 const u32 *reg;
@@ -733,7 +742,7 @@ int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
733 return PCIBIOS_SUCCESSFUL; 742 return PCIBIOS_SUCCESSFUL;
734} 743}
735 744
736struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm) 745struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
737{ 746{
738 struct pci_controller_info *p = pbm->parent; 747 struct pci_controller_info *p = pbm->parent;
739 struct device_node *node = pbm->prom_node; 748 struct device_node *node = pbm->prom_node;
diff --git a/arch/sparc64/kernel/pci_fire.c b/arch/sparc64/kernel/pci_fire.c
new file mode 100644
index 000000000000..0fe626631e12
--- /dev/null
+++ b/arch/sparc64/kernel/pci_fire.c
@@ -0,0 +1,418 @@
1/* pci_fire.c: Sun4u platform PCI-E controller support.
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5#include <linux/kernel.h>
6#include <linux/pci.h>
7#include <linux/slab.h>
8#include <linux/init.h>
9
10#include <asm/pbm.h>
11#include <asm/oplib.h>
12#include <asm/prom.h>
13
14#include "pci_impl.h"
15
16#define fire_read(__reg) \
17({ u64 __ret; \
18 __asm__ __volatile__("ldxa [%1] %2, %0" \
19 : "=r" (__ret) \
20 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
21 : "memory"); \
22 __ret; \
23})
24#define fire_write(__reg, __val) \
25 __asm__ __volatile__("stxa %0, [%1] %2" \
26 : /* no outputs */ \
27 : "r" (__val), "r" (__reg), \
28 "i" (ASI_PHYS_BYPASS_EC_E) \
29 : "memory")
30
31/* Fire config space address format is nearly identical to
32 * that of SCHIZO and PSYCHO, except that in order to accomodate
33 * PCI-E extended config space the encoding can handle 12 bits
34 * of register address:
35 *
36 * 32 28 27 20 19 15 14 12 11 2 1 0
37 * -------------------------------------------------
38 * |0 0 0 0 0| bus | device | function | reg | 0 0 |
39 * -------------------------------------------------
40 */
41#define FIRE_CONFIG_BASE(PBM) ((PBM)->config_space)
42#define FIRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
43 (((unsigned long)(BUS) << 20) | \
44 ((unsigned long)(DEVFN) << 12) | \
45 ((unsigned long)(REG)))
46
47static void *fire_pci_config_mkaddr(struct pci_pbm_info *pbm,
48 unsigned char bus,
49 unsigned int devfn,
50 int where)
51{
52 if (!pbm)
53 return NULL;
54 return (void *)
55 (FIRE_CONFIG_BASE(pbm) |
56 FIRE_CONFIG_ENCODE(bus, devfn, where));
57}
58
59/* FIRE PCI configuration space accessors. */
60
61static int fire_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
62 int where, int size, u32 *value)
63{
64 struct pci_pbm_info *pbm = bus_dev->sysdata;
65 unsigned char bus = bus_dev->number;
66 u32 *addr;
67 u16 tmp16;
68 u8 tmp8;
69
70 if (bus_dev == pbm->pci_bus && devfn == 0x00)
71 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
72 size, value);
73 switch (size) {
74 case 1:
75 *value = 0xff;
76 break;
77 case 2:
78 *value = 0xffff;
79 break;
80 case 4:
81 *value = 0xffffffff;
82 break;
83 }
84
85 addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
86 if (!addr)
87 return PCIBIOS_SUCCESSFUL;
88
89 switch (size) {
90 case 1:
91 pci_config_read8((u8 *)addr, &tmp8);
92 *value = tmp8;
93 break;
94
95 case 2:
96 if (where & 0x01) {
97 printk("pci_read_config_word: misaligned reg [%x]\n",
98 where);
99 return PCIBIOS_SUCCESSFUL;
100 }
101 pci_config_read16((u16 *)addr, &tmp16);
102 *value = tmp16;
103 break;
104
105 case 4:
106 if (where & 0x03) {
107 printk("pci_read_config_dword: misaligned reg [%x]\n",
108 where);
109 return PCIBIOS_SUCCESSFUL;
110 }
111
112 pci_config_read32(addr, value);
113 break;
114 }
115 return PCIBIOS_SUCCESSFUL;
116}
117
118static int fire_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
119 int where, int size, u32 value)
120{
121 struct pci_pbm_info *pbm = bus_dev->sysdata;
122 unsigned char bus = bus_dev->number;
123 u32 *addr;
124
125 if (bus_dev == pbm->pci_bus && devfn == 0x00)
126 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
127 size, value);
128 addr = fire_pci_config_mkaddr(pbm, bus, devfn, where);
129 if (!addr)
130 return PCIBIOS_SUCCESSFUL;
131
132 switch (size) {
133 case 1:
134 pci_config_write8((u8 *)addr, value);
135 break;
136
137 case 2:
138 if (where & 0x01) {
139 printk("pci_write_config_word: misaligned reg [%x]\n",
140 where);
141 return PCIBIOS_SUCCESSFUL;
142 }
143 pci_config_write16((u16 *)addr, value);
144 break;
145
146 case 4:
147 if (where & 0x03) {
148 printk("pci_write_config_dword: misaligned reg [%x]\n",
149 where);
150 return PCIBIOS_SUCCESSFUL;
151 }
152
153 pci_config_write32(addr, value);
154 }
155 return PCIBIOS_SUCCESSFUL;
156}
157
158static struct pci_ops pci_fire_ops = {
159 .read = fire_read_pci_cfg,
160 .write = fire_write_pci_cfg,
161};
162
163static void pbm_scan_bus(struct pci_controller_info *p,
164 struct pci_pbm_info *pbm)
165{
166 pbm->pci_bus = pci_scan_one_pbm(pbm);
167}
168
169static void pci_fire_scan_bus(struct pci_controller_info *p)
170{
171 struct device_node *dp;
172
173 if ((dp = p->pbm_A.prom_node) != NULL)
174 pbm_scan_bus(p, &p->pbm_A);
175
176 if ((dp = p->pbm_B.prom_node) != NULL)
177 pbm_scan_bus(p, &p->pbm_B);
178
179 /* XXX register error interrupt handlers XXX */
180}
181
182#define FIRE_IOMMU_CONTROL 0x40000UL
183#define FIRE_IOMMU_TSBBASE 0x40008UL
184#define FIRE_IOMMU_FLUSH 0x40100UL
185#define FIRE_IOMMU_FLUSHINV 0x40100UL
186
187static void pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
188{
189 struct iommu *iommu = pbm->iommu;
190 u32 vdma[2], dma_mask;
191 u64 control;
192 int tsbsize;
193
194 /* No virtual-dma property on these guys, use largest size. */
195 vdma[0] = 0xc0000000; /* base */
196 vdma[1] = 0x40000000; /* size */
197 dma_mask = 0xffffffff;
198 tsbsize = 128;
199
200 /* Register addresses. */
201 iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL;
202 iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE;
203 iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH;
204 iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV;
205
206 /* We use the main control/status register of FIRE as the write
207 * completion register.
208 */
209 iommu->write_complete_reg = pbm->controller_regs + 0x410000UL;
210
211 /*
212 * Invalidate TLB Entries.
213 */
214 fire_write(iommu->iommu_flushinv, ~(u64)0);
215
216 pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
217
218 fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL);
219
220 control = fire_read(iommu->iommu_control);
221 control |= (0x00000400 /* TSB cache snoop enable */ |
222 0x00000300 /* Cache mode */ |
223 0x00000002 /* Bypass enable */ |
224 0x00000001 /* Translation enable */);
225 fire_write(iommu->iommu_control, control);
226}
227
228/* Based at pbm->controller_regs */
229#define FIRE_PARITY_CONTROL 0x470010UL
230#define FIRE_PARITY_ENAB 0x8000000000000000UL
231#define FIRE_FATAL_RESET_CTL 0x471028UL
232#define FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
233#define FIRE_FATAL_RESET_MB 0x0000000002000000UL
234#define FIRE_FATAL_RESET_CPE 0x0000000000008000UL
235#define FIRE_FATAL_RESET_APE 0x0000000000004000UL
236#define FIRE_FATAL_RESET_PIO 0x0000000000000040UL
237#define FIRE_FATAL_RESET_JW 0x0000000000000004UL
238#define FIRE_FATAL_RESET_JI 0x0000000000000002UL
239#define FIRE_FATAL_RESET_JR 0x0000000000000001UL
240#define FIRE_CORE_INTR_ENABLE 0x471800UL
241
242/* Based at pbm->pbm_regs */
243#define FIRE_TLU_CTRL 0x80000UL
244#define FIRE_TLU_CTRL_TIM 0x00000000da000000UL
245#define FIRE_TLU_CTRL_QDET 0x0000000000000100UL
246#define FIRE_TLU_CTRL_CFG 0x0000000000000001UL
247#define FIRE_TLU_DEV_CTRL 0x90008UL
248#define FIRE_TLU_LINK_CTRL 0x90020UL
249#define FIRE_TLU_LINK_CTRL_CLK 0x0000000000000040UL
250#define FIRE_LPU_RESET 0xe2008UL
251#define FIRE_LPU_LLCFG 0xe2200UL
252#define FIRE_LPU_LLCFG_VC0 0x0000000000000100UL
253#define FIRE_LPU_FCTRL_UCTRL 0xe2240UL
254#define FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
255#define FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
256#define FIRE_LPU_TXL_FIFOP 0xe2430UL
257#define FIRE_LPU_LTSSM_CFG2 0xe2788UL
258#define FIRE_LPU_LTSSM_CFG3 0xe2790UL
259#define FIRE_LPU_LTSSM_CFG4 0xe2798UL
260#define FIRE_LPU_LTSSM_CFG5 0xe27a0UL
261#define FIRE_DMC_IENAB 0x31800UL
262#define FIRE_DMC_DBG_SEL_A 0x53000UL
263#define FIRE_DMC_DBG_SEL_B 0x53008UL
264#define FIRE_PEC_IENAB 0x51800UL
265
266static void pci_fire_hw_init(struct pci_pbm_info *pbm)
267{
268 u64 val;
269
270 fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL,
271 FIRE_PARITY_ENAB);
272
273 fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL,
274 (FIRE_FATAL_RESET_SPARE |
275 FIRE_FATAL_RESET_MB |
276 FIRE_FATAL_RESET_CPE |
277 FIRE_FATAL_RESET_APE |
278 FIRE_FATAL_RESET_PIO |
279 FIRE_FATAL_RESET_JW |
280 FIRE_FATAL_RESET_JI |
281 FIRE_FATAL_RESET_JR));
282
283 fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0);
284
285 val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL);
286 val |= (FIRE_TLU_CTRL_TIM |
287 FIRE_TLU_CTRL_QDET |
288 FIRE_TLU_CTRL_CFG);
289 fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val);
290 fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0);
291 fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL,
292 FIRE_TLU_LINK_CTRL_CLK);
293
294 fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0);
295 fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG,
296 FIRE_LPU_LLCFG_VC0);
297 fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL,
298 (FIRE_LPU_FCTRL_UCTRL_N |
299 FIRE_LPU_FCTRL_UCTRL_P));
300 fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP,
301 ((0xffff << 16) | (0x0000 << 0)));
302 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000);
303 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000);
304 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4,
305 (2 << 16) | (140 << 8));
306 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0);
307
308 fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0);
309 fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0);
310 fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0);
311
312 fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
313}
314
315static void pci_fire_pbm_init(struct pci_controller_info *p,
316 struct device_node *dp, u32 portid)
317{
318 const struct linux_prom64_registers *regs;
319 struct pci_pbm_info *pbm;
320 const u32 *ino_bitmap;
321 const unsigned int *busrange;
322
323 if ((portid & 1) == 0)
324 pbm = &p->pbm_A;
325 else
326 pbm = &p->pbm_B;
327
328 pbm->portid = portid;
329 pbm->parent = p;
330 pbm->prom_node = dp;
331 pbm->name = dp->full_name;
332
333 regs = of_get_property(dp, "reg", NULL);
334 pbm->pbm_regs = regs[0].phys_addr;
335 pbm->controller_regs = regs[1].phys_addr - 0x410000UL;
336
337 printk("%s: SUN4U PCIE Bus Module\n", pbm->name);
338
339 pci_determine_mem_io_space(pbm);
340
341 ino_bitmap = of_get_property(dp, "ino-bitmap", NULL);
342 pbm->ino_bitmap = (((u64)ino_bitmap[1] << 32UL) |
343 ((u64)ino_bitmap[0] << 0UL));
344
345 busrange = of_get_property(dp, "bus-range", NULL);
346 pbm->pci_first_busno = busrange[0];
347 pbm->pci_last_busno = busrange[1];
348
349 pci_fire_hw_init(pbm);
350 pci_fire_pbm_iommu_init(pbm);
351}
352
353static inline int portid_compare(u32 x, u32 y)
354{
355 if (x == (y ^ 1))
356 return 1;
357 return 0;
358}
359
360void fire_pci_init(struct device_node *dp, const char *model_name)
361{
362 struct pci_controller_info *p;
363 u32 portid = of_getintprop_default(dp, "portid", 0xff);
364 struct iommu *iommu;
365
366 for (p = pci_controller_root; p; p = p->next) {
367 struct pci_pbm_info *pbm;
368
369 if (p->pbm_A.prom_node && p->pbm_B.prom_node)
370 continue;
371
372 pbm = (p->pbm_A.prom_node ?
373 &p->pbm_A :
374 &p->pbm_B);
375
376 if (portid_compare(pbm->portid, portid)) {
377 pci_fire_pbm_init(p, dp, portid);
378 return;
379 }
380 }
381
382 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
383 if (!p)
384 goto fatal_memory_error;
385
386 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
387 if (!iommu)
388 goto fatal_memory_error;
389
390 p->pbm_A.iommu = iommu;
391
392 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
393 if (!iommu)
394 goto fatal_memory_error;
395
396 p->pbm_B.iommu = iommu;
397
398 p->next = pci_controller_root;
399 pci_controller_root = p;
400
401 p->index = pci_num_controllers++;
402
403 p->scan_bus = pci_fire_scan_bus;
404 /* XXX MSI support XXX */
405 p->pci_ops = &pci_fire_ops;
406
407 /* Like PSYCHO and SCHIZO we have a 2GB aligned area
408 * for memory space.
409 */
410 pci_memspace_mask = 0x7fffffffUL;
411
412 pci_fire_pbm_init(p, dp, portid);
413 return;
414
415fatal_memory_error:
416 prom_printf("PCI_FIRE: Fatal memory allocation error.\n");
417 prom_halt();
418}
diff --git a/arch/sparc64/kernel/pci_iommu.c b/arch/sparc64/kernel/pci_iommu.c
index 66712772f494..9e405cbbcb0d 100644
--- a/arch/sparc64/kernel/pci_iommu.c
+++ b/arch/sparc64/kernel/pci_iommu.c
@@ -37,17 +37,21 @@
37/* Must be invoked under the IOMMU lock. */ 37/* Must be invoked under the IOMMU lock. */
38static void __iommu_flushall(struct iommu *iommu) 38static void __iommu_flushall(struct iommu *iommu)
39{ 39{
40 unsigned long tag; 40 if (iommu->iommu_flushinv) {
41 int entry; 41 pci_iommu_write(iommu->iommu_flushinv, ~(u64)0);
42 } else {
43 unsigned long tag;
44 int entry;
42 45
43 tag = iommu->iommu_flush + (0xa580UL - 0x0210UL); 46 tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
44 for (entry = 0; entry < 16; entry++) { 47 for (entry = 0; entry < 16; entry++) {
45 pci_iommu_write(tag, 0); 48 pci_iommu_write(tag, 0);
46 tag += 8; 49 tag += 8;
47 } 50 }
48 51
49 /* Ensure completion of previous PIO writes. */ 52 /* Ensure completion of previous PIO writes. */
50 (void) pci_iommu_read(iommu->write_complete_reg); 53 (void) pci_iommu_read(iommu->write_complete_reg);
54 }
51} 55}
52 56
53#define IOPTE_CONSISTENT(CTX) \ 57#define IOPTE_CONSISTENT(CTX) \
diff --git a/arch/sparc64/kernel/prom.c b/arch/sparc64/kernel/prom.c
index 5e1fcd05160d..c54d4d8af014 100644
--- a/arch/sparc64/kernel/prom.c
+++ b/arch/sparc64/kernel/prom.c
@@ -386,11 +386,9 @@ static unsigned int psycho_irq_build(struct device_node *dp,
386 386
387 /* Now build the IRQ bucket. */ 387 /* Now build the IRQ bucket. */
388 imap = controller_regs + imap_off; 388 imap = controller_regs + imap_off;
389 imap += 4;
390 389
391 iclr_off = psycho_iclr_offset(ino); 390 iclr_off = psycho_iclr_offset(ino);
392 iclr = controller_regs + iclr_off; 391 iclr = controller_regs + iclr_off;
393 iclr += 4;
394 392
395 if ((ino & 0x20) == 0) 393 if ((ino & 0x20) == 0)
396 inofixup = ino & 0x03; 394 inofixup = ino & 0x03;
@@ -398,7 +396,7 @@ static unsigned int psycho_irq_build(struct device_node *dp,
398 return build_irq(inofixup, iclr, imap); 396 return build_irq(inofixup, iclr, imap);
399} 397}
400 398
401static void psycho_irq_trans_init(struct device_node *dp) 399static void __init psycho_irq_trans_init(struct device_node *dp)
402{ 400{
403 const struct linux_prom64_registers *regs; 401 const struct linux_prom64_registers *regs;
404 402
@@ -613,11 +611,9 @@ static unsigned int sabre_irq_build(struct device_node *dp,
613 611
614 /* Now build the IRQ bucket. */ 612 /* Now build the IRQ bucket. */
615 imap = controller_regs + imap_off; 613 imap = controller_regs + imap_off;
616 imap += 4;
617 614
618 iclr_off = sabre_iclr_offset(ino); 615 iclr_off = sabre_iclr_offset(ino);
619 iclr = controller_regs + iclr_off; 616 iclr = controller_regs + iclr_off;
620 iclr += 4;
621 617
622 if ((ino & 0x20) == 0) 618 if ((ino & 0x20) == 0)
623 inofixup = ino & 0x03; 619 inofixup = ino & 0x03;
@@ -640,7 +636,7 @@ static unsigned int sabre_irq_build(struct device_node *dp,
640 return virt_irq; 636 return virt_irq;
641} 637}
642 638
643static void sabre_irq_trans_init(struct device_node *dp) 639static void __init sabre_irq_trans_init(struct device_node *dp)
644{ 640{
645 const struct linux_prom64_registers *regs; 641 const struct linux_prom64_registers *regs;
646 struct sabre_irq_data *irq_data; 642 struct sabre_irq_data *irq_data;
@@ -679,13 +675,14 @@ static unsigned long schizo_iclr_offset(unsigned long ino)
679static unsigned long schizo_ino_to_iclr(unsigned long pbm_regs, 675static unsigned long schizo_ino_to_iclr(unsigned long pbm_regs,
680 unsigned int ino) 676 unsigned int ino)
681{ 677{
682 return pbm_regs + schizo_iclr_offset(ino) + 4; 678
679 return pbm_regs + schizo_iclr_offset(ino);
683} 680}
684 681
685static unsigned long schizo_ino_to_imap(unsigned long pbm_regs, 682static unsigned long schizo_ino_to_imap(unsigned long pbm_regs,
686 unsigned int ino) 683 unsigned int ino)
687{ 684{
688 return pbm_regs + schizo_imap_offset(ino) + 4; 685 return pbm_regs + schizo_imap_offset(ino);
689} 686}
690 687
691#define schizo_read(__reg) \ 688#define schizo_read(__reg) \
@@ -796,7 +793,8 @@ static unsigned int schizo_irq_build(struct device_node *dp,
796 return virt_irq; 793 return virt_irq;
797} 794}
798 795
799static void __schizo_irq_trans_init(struct device_node *dp, int is_tomatillo) 796static void __init __schizo_irq_trans_init(struct device_node *dp,
797 int is_tomatillo)
800{ 798{
801 const struct linux_prom64_registers *regs; 799 const struct linux_prom64_registers *regs;
802 struct schizo_irq_data *irq_data; 800 struct schizo_irq_data *irq_data;
@@ -818,12 +816,12 @@ static void __schizo_irq_trans_init(struct device_node *dp, int is_tomatillo)
818 irq_data->chip_version = of_getintprop_default(dp, "version#", 0); 816 irq_data->chip_version = of_getintprop_default(dp, "version#", 0);
819} 817}
820 818
821static void schizo_irq_trans_init(struct device_node *dp) 819static void __init schizo_irq_trans_init(struct device_node *dp)
822{ 820{
823 __schizo_irq_trans_init(dp, 0); 821 __schizo_irq_trans_init(dp, 0);
824} 822}
825 823
826static void tomatillo_irq_trans_init(struct device_node *dp) 824static void __init tomatillo_irq_trans_init(struct device_node *dp)
827{ 825{
828 __schizo_irq_trans_init(dp, 1); 826 __schizo_irq_trans_init(dp, 1);
829} 827}
@@ -837,7 +835,7 @@ static unsigned int pci_sun4v_irq_build(struct device_node *dp,
837 return sun4v_build_irq(devhandle, devino); 835 return sun4v_build_irq(devhandle, devino);
838} 836}
839 837
840static void pci_sun4v_irq_trans_init(struct device_node *dp) 838static void __init pci_sun4v_irq_trans_init(struct device_node *dp)
841{ 839{
842 const struct linux_prom64_registers *regs; 840 const struct linux_prom64_registers *regs;
843 841
@@ -848,6 +846,85 @@ static void pci_sun4v_irq_trans_init(struct device_node *dp)
848 dp->irq_trans->data = (void *) (unsigned long) 846 dp->irq_trans->data = (void *) (unsigned long)
849 ((regs->phys_addr >> 32UL) & 0x0fffffff); 847 ((regs->phys_addr >> 32UL) & 0x0fffffff);
850} 848}
849
850struct fire_irq_data {
851 unsigned long pbm_regs;
852 u32 portid;
853};
854
855#define FIRE_IMAP_BASE 0x001000
856#define FIRE_ICLR_BASE 0x001400
857
858static unsigned long fire_imap_offset(unsigned long ino)
859{
860 return FIRE_IMAP_BASE + (ino * 8UL);
861}
862
863static unsigned long fire_iclr_offset(unsigned long ino)
864{
865 return FIRE_ICLR_BASE + (ino * 8UL);
866}
867
868static unsigned long fire_ino_to_iclr(unsigned long pbm_regs,
869 unsigned int ino)
870{
871 return pbm_regs + fire_iclr_offset(ino);
872}
873
874static unsigned long fire_ino_to_imap(unsigned long pbm_regs,
875 unsigned int ino)
876{
877 return pbm_regs + fire_imap_offset(ino);
878}
879
880static unsigned int fire_irq_build(struct device_node *dp,
881 unsigned int ino,
882 void *_data)
883{
884 struct fire_irq_data *irq_data = _data;
885 unsigned long pbm_regs = irq_data->pbm_regs;
886 unsigned long imap, iclr;
887 unsigned long int_ctrlr;
888
889 ino &= 0x3f;
890
891 /* Now build the IRQ bucket. */
892 imap = fire_ino_to_imap(pbm_regs, ino);
893 iclr = fire_ino_to_iclr(pbm_regs, ino);
894
895 /* Set the interrupt controller number. */
896 int_ctrlr = 1 << 6;
897 upa_writeq(int_ctrlr, imap);
898
899 /* The interrupt map registers do not have an INO field
900 * like other chips do. They return zero in the INO
901 * field, and the interrupt controller number is controlled
902 * in bits 6 thru 9. So in order for build_irq() to get
903 * the INO right we pass it in as part of the fixup
904 * which will get added to the map register zero value
905 * read by build_irq().
906 */
907 ino |= (irq_data->portid << 6);
908 ino -= int_ctrlr;
909 return build_irq(ino, iclr, imap);
910}
911
912static void __init fire_irq_trans_init(struct device_node *dp)
913{
914 const struct linux_prom64_registers *regs;
915 struct fire_irq_data *irq_data;
916
917 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
918 dp->irq_trans->irq_build = fire_irq_build;
919
920 irq_data = prom_early_alloc(sizeof(struct fire_irq_data));
921
922 regs = of_get_property(dp, "reg", NULL);
923 dp->irq_trans->data = irq_data;
924
925 irq_data->pbm_regs = regs[0].phys_addr;
926 irq_data->portid = of_getintprop_default(dp, "portid", 0);
927}
851#endif /* CONFIG_PCI */ 928#endif /* CONFIG_PCI */
852 929
853#ifdef CONFIG_SBUS 930#ifdef CONFIG_SBUS
@@ -995,7 +1072,7 @@ static unsigned int sbus_of_build_irq(struct device_node *dp,
995 return build_irq(sbus_level, iclr, imap); 1072 return build_irq(sbus_level, iclr, imap);
996} 1073}
997 1074
998static void sbus_irq_trans_init(struct device_node *dp) 1075static void __init sbus_irq_trans_init(struct device_node *dp)
999{ 1076{
1000 const struct linux_prom64_registers *regs; 1077 const struct linux_prom64_registers *regs;
1001 1078
@@ -1042,7 +1119,7 @@ static unsigned int central_build_irq(struct device_node *dp,
1042 return build_irq(0, iclr, imap); 1119 return build_irq(0, iclr, imap);
1043} 1120}
1044 1121
1045static void central_irq_trans_init(struct device_node *dp) 1122static void __init central_irq_trans_init(struct device_node *dp)
1046{ 1123{
1047 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller)); 1124 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
1048 dp->irq_trans->irq_build = central_build_irq; 1125 dp->irq_trans->irq_build = central_build_irq;
@@ -1056,7 +1133,7 @@ struct irq_trans {
1056}; 1133};
1057 1134
1058#ifdef CONFIG_PCI 1135#ifdef CONFIG_PCI
1059static struct irq_trans pci_irq_trans_table[] = { 1136static struct irq_trans __initdata pci_irq_trans_table[] = {
1060 { "SUNW,sabre", sabre_irq_trans_init }, 1137 { "SUNW,sabre", sabre_irq_trans_init },
1061 { "pci108e,a000", sabre_irq_trans_init }, 1138 { "pci108e,a000", sabre_irq_trans_init },
1062 { "pci108e,a001", sabre_irq_trans_init }, 1139 { "pci108e,a001", sabre_irq_trans_init },
@@ -1069,6 +1146,7 @@ static struct irq_trans pci_irq_trans_table[] = {
1069 { "SUNW,tomatillo", tomatillo_irq_trans_init }, 1146 { "SUNW,tomatillo", tomatillo_irq_trans_init },
1070 { "pci108e,a801", tomatillo_irq_trans_init }, 1147 { "pci108e,a801", tomatillo_irq_trans_init },
1071 { "SUNW,sun4v-pci", pci_sun4v_irq_trans_init }, 1148 { "SUNW,sun4v-pci", pci_sun4v_irq_trans_init },
1149 { "pciex108e,80f0", fire_irq_trans_init },
1072}; 1150};
1073#endif 1151#endif
1074 1152
@@ -1081,7 +1159,7 @@ static unsigned int sun4v_vdev_irq_build(struct device_node *dp,
1081 return sun4v_build_irq(devhandle, devino); 1159 return sun4v_build_irq(devhandle, devino);
1082} 1160}
1083 1161
1084static void sun4v_vdev_irq_trans_init(struct device_node *dp) 1162static void __init sun4v_vdev_irq_trans_init(struct device_node *dp)
1085{ 1163{
1086 const struct linux_prom64_registers *regs; 1164 const struct linux_prom64_registers *regs;
1087 1165
@@ -1093,7 +1171,7 @@ static void sun4v_vdev_irq_trans_init(struct device_node *dp)
1093 ((regs->phys_addr >> 32UL) & 0x0fffffff); 1171 ((regs->phys_addr >> 32UL) & 0x0fffffff);
1094} 1172}
1095 1173
1096static void irq_trans_init(struct device_node *dp) 1174static void __init irq_trans_init(struct device_node *dp)
1097{ 1175{
1098#ifdef CONFIG_PCI 1176#ifdef CONFIG_PCI
1099 const char *model; 1177 const char *model;
diff --git a/drivers/scsi/sun_esp.c b/drivers/scsi/sun_esp.c
index 8c766bcd1095..bbeb2451d32f 100644
--- a/drivers/scsi/sun_esp.c
+++ b/drivers/scsi/sun_esp.c
@@ -5,6 +5,7 @@
5 5
6#include <linux/kernel.h> 6#include <linux/kernel.h>
7#include <linux/types.h> 7#include <linux/types.h>
8#include <linux/delay.h>
8#include <linux/module.h> 9#include <linux/module.h>
9#include <linux/init.h> 10#include <linux/init.h>
10 11
diff --git a/drivers/serial/sunsu.c b/drivers/serial/sunsu.c
index bfd44177a215..2a63cdba3208 100644
--- a/drivers/serial/sunsu.c
+++ b/drivers/serial/sunsu.c
@@ -1312,7 +1312,7 @@ static void sunsu_console_write(struct console *co, const char *s,
1312 * - initialize the serial port 1312 * - initialize the serial port
1313 * Return non-zero if we didn't find a serial port. 1313 * Return non-zero if we didn't find a serial port.
1314 */ 1314 */
1315static int sunsu_console_setup(struct console *co, char *options) 1315static int __init sunsu_console_setup(struct console *co, char *options)
1316{ 1316{
1317 struct uart_port *port; 1317 struct uart_port *port;
1318 int baud = 9600; 1318 int baud = 9600;
@@ -1343,7 +1343,7 @@ static int sunsu_console_setup(struct console *co, char *options)
1343 return uart_set_options(port, co, baud, parity, bits, flow); 1343 return uart_set_options(port, co, baud, parity, bits, flow);
1344} 1344}
1345 1345
1346static struct console sunsu_cons = { 1346static struct console sunsu_console = {
1347 .name = "ttyS", 1347 .name = "ttyS",
1348 .write = sunsu_console_write, 1348 .write = sunsu_console_write,
1349 .device = uart_console_device, 1349 .device = uart_console_device,
@@ -1373,9 +1373,9 @@ static inline struct console *SUNSU_CONSOLE(int num_uart)
1373 if (i == num_uart) 1373 if (i == num_uart)
1374 return NULL; 1374 return NULL;
1375 1375
1376 sunsu_cons.index = i; 1376 sunsu_console.index = i;
1377 1377
1378 return &sunsu_cons; 1378 return &sunsu_console;
1379} 1379}
1380#else 1380#else
1381#define SUNSU_CONSOLE(num_uart) (NULL) 1381#define SUNSU_CONSOLE(num_uart) (NULL)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2d89d0e9bcf4..344c37595305 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1383,6 +1383,32 @@ config FB_LEO
1383 This is the frame buffer device driver for the SBUS-based Sun ZX 1383 This is the frame buffer device driver for the SBUS-based Sun ZX
1384 (leo) frame buffer cards. 1384 (leo) frame buffer cards.
1385 1385
1386config FB_XVR500
1387 bool "Sun XVR-500 3DLABS Wildcat support"
1388 depends on FB && PCI && SPARC64
1389 select FB_CFB_FILLRECT
1390 select FB_CFB_COPYAREA
1391 select FB_CFB_IMAGEBLIT
1392 help
1393 This is the framebuffer device for the Sun XVR-500 and similar
1394 graphics cards based upon the 3DLABS Wildcat chipset. The driver
1395 only works on sparc64 systems where the system firwmare has
1396 mostly initialized the card already. It is treated as a
1397 completely dumb framebuffer device.
1398
1399config FB_XVR2500
1400 bool "Sun XVR-2500 3DLABS Wildcat support"
1401 depends on FB && PCI && SPARC64
1402 select FB_CFB_FILLRECT
1403 select FB_CFB_COPYAREA
1404 select FB_CFB_IMAGEBLIT
1405 help
1406 This is the framebuffer device for the Sun XVR-2500 and similar
1407 graphics cards based upon the 3DLABS Wildcat chipset. The driver
1408 only works on sparc64 systems where the system firwmare has
1409 mostly initialized the card already. It is treated as a
1410 completely dumb framebuffer device.
1411
1386config FB_PCI 1412config FB_PCI
1387 bool "PCI framebuffers" 1413 bool "PCI framebuffers"
1388 depends on (FB = y) && PCI && SPARC 1414 depends on (FB = y) && PCI && SPARC
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 869351785ee8..558473d040d6 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -67,6 +67,8 @@ obj-$(CONFIG_FB_ATARI) += atafb.o c2p.o atafb_mfb.o \
67 atafb_iplan2p2.o atafb_iplan2p4.o atafb_iplan2p8.o 67 atafb_iplan2p2.o atafb_iplan2p4.o atafb_iplan2p8.o
68obj-$(CONFIG_FB_MAC) += macfb.o 68obj-$(CONFIG_FB_MAC) += macfb.o
69obj-$(CONFIG_FB_HGA) += hgafb.o 69obj-$(CONFIG_FB_HGA) += hgafb.o
70obj-$(CONFIG_FB_XVR500) += sunxvr500.o
71obj-$(CONFIG_FB_XVR2500) += sunxvr2500.o
70obj-$(CONFIG_FB_IGA) += igafb.o 72obj-$(CONFIG_FB_IGA) += igafb.o
71obj-$(CONFIG_FB_APOLLO) += dnfb.o 73obj-$(CONFIG_FB_APOLLO) += dnfb.o
72obj-$(CONFIG_FB_Q40) += q40fb.o 74obj-$(CONFIG_FB_Q40) += q40fb.o
diff --git a/drivers/video/sunxvr2500.c b/drivers/video/sunxvr2500.c
new file mode 100644
index 000000000000..4010492c6920
--- /dev/null
+++ b/drivers/video/sunxvr2500.c
@@ -0,0 +1,277 @@
1/* s3d.c: Sun 3DLABS XVR-2500 et al. driver for sparc64 systems
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/module.h>
7#include <linux/kernel.h>
8#include <linux/slab.h>
9#include <linux/fb.h>
10#include <linux/pci.h>
11#include <linux/init.h>
12
13#include <asm/io.h>
14#include <asm/prom.h>
15#include <asm/of_device.h>
16
17struct s3d_info {
18 struct fb_info *info;
19 struct pci_dev *pdev;
20
21 char __iomem *fb_base;
22 unsigned long fb_base_phys;
23
24 struct device_node *of_node;
25
26 unsigned int width;
27 unsigned int height;
28 unsigned int depth;
29 unsigned int fb_size;
30
31 u32 pseudo_palette[256];
32};
33
34static int __devinit s3d_get_props(struct s3d_info *sp)
35{
36 sp->width = of_getintprop_default(sp->of_node, "width", 0);
37 sp->height = of_getintprop_default(sp->of_node, "height", 0);
38 sp->depth = of_getintprop_default(sp->of_node, "depth", 8);
39
40 if (!sp->width || !sp->height) {
41 printk(KERN_ERR "s3d: Critical properties missing for %s\n",
42 pci_name(sp->pdev));
43 return -EINVAL;
44 }
45
46 return 0;
47}
48
49static int s3d_setcolreg(unsigned regno,
50 unsigned red, unsigned green, unsigned blue,
51 unsigned transp, struct fb_info *info)
52{
53 u32 value;
54
55 if (regno >= 256)
56 return 1;
57
58 red >>= 8;
59 green >>= 8;
60 blue >>= 8;
61
62 value = (blue << 24) | (green << 16) | (red << 8);
63 ((u32 *)info->pseudo_palette)[regno] = value;
64
65 return 0;
66}
67
68static struct fb_ops s3d_ops = {
69 .owner = THIS_MODULE,
70 .fb_setcolreg = s3d_setcolreg,
71 .fb_fillrect = cfb_fillrect,
72 .fb_copyarea = cfb_copyarea,
73 .fb_imageblit = cfb_imageblit,
74};
75
76static int __devinit s3d_set_fbinfo(struct s3d_info *sp)
77{
78 struct fb_info *info = sp->info;
79 struct fb_var_screeninfo *var = &info->var;
80
81 info->flags = FBINFO_DEFAULT;
82 info->fbops = &s3d_ops;
83 info->screen_base = sp->fb_base;
84 info->screen_size = sp->fb_size;
85
86 info->pseudo_palette = sp->pseudo_palette;
87
88 /* Fill fix common fields */
89 strlcpy(info->fix.id, "s3d", sizeof(info->fix.id));
90 info->fix.smem_start = sp->fb_base_phys;
91 info->fix.smem_len = sp->fb_size;
92 info->fix.type = FB_TYPE_PACKED_PIXELS;
93 if (sp->depth == 32 || sp->depth == 24)
94 info->fix.visual = FB_VISUAL_TRUECOLOR;
95 else
96 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
97
98 var->xres = sp->width;
99 var->yres = sp->height;
100 var->xres_virtual = var->xres;
101 var->yres_virtual = var->yres;
102 var->bits_per_pixel = sp->depth;
103
104 var->red.offset = 8;
105 var->red.length = 8;
106 var->green.offset = 16;
107 var->green.length = 8;
108 var->blue.offset = 24;
109 var->blue.length = 8;
110 var->transp.offset = 0;
111 var->transp.length = 0;
112
113 if (fb_alloc_cmap(&info->cmap, 256, 0)) {
114 printk(KERN_ERR "s3d: Cannot allocate color map.\n");
115 return -ENOMEM;
116 }
117
118 return 0;
119}
120
121static int __devinit s3d_pci_register(struct pci_dev *pdev,
122 const struct pci_device_id *ent)
123{
124 struct fb_info *info;
125 struct s3d_info *sp;
126 int err;
127
128 err = pci_enable_device(pdev);
129 if (err < 0) {
130 printk(KERN_ERR "s3d: Cannot enable PCI device %s\n",
131 pci_name(pdev));
132 goto err_out;
133 }
134
135 info = framebuffer_alloc(sizeof(struct s3d_info), &pdev->dev);
136 if (!info) {
137 printk(KERN_ERR "s3d: Cannot allocate fb_info\n");
138 err = -ENOMEM;
139 goto err_disable;
140 }
141
142 sp = info->par;
143 sp->info = info;
144 sp->pdev = pdev;
145 sp->of_node = pci_device_to_OF_node(pdev);
146 if (!sp->of_node) {
147 printk(KERN_ERR "s3d: Cannot find OF node of %s\n",
148 pci_name(pdev));
149 err = -ENODEV;
150 goto err_release_fb;
151 }
152
153 sp->fb_base_phys = pci_resource_start (pdev, 1);
154
155 err = pci_request_region(pdev, 1, "s3d framebuffer");
156 if (err < 0) {
157 printk("s3d: Cannot request region 1 for %s\n",
158 pci_name(pdev));
159 goto err_release_fb;
160 }
161
162 err = s3d_get_props(sp);
163 if (err)
164 goto err_release_pci;
165
166 /* XXX 'linebytes' is often wrong, it is equal to the width
167 * XXX with depth of 32 on my XVR-2500 which is clearly not
168 * XXX right. So we don't try to use it.
169 */
170 switch (sp->depth) {
171 case 8:
172 info->fix.line_length = sp->width;
173 break;
174 case 16:
175 info->fix.line_length = sp->width * 2;
176 break;
177 case 24:
178 info->fix.line_length = sp->width * 3;
179 break;
180 case 32:
181 info->fix.line_length = sp->width * 4;
182 break;
183 }
184 sp->fb_size = info->fix.line_length * sp->height;
185
186 sp->fb_base = ioremap(sp->fb_base_phys, sp->fb_size);
187 if (!sp->fb_base)
188 goto err_release_pci;
189
190 err = s3d_set_fbinfo(sp);
191 if (err)
192 goto err_unmap_fb;
193
194 pci_set_drvdata(pdev, info);
195
196 printk("s3d: Found device at %s\n", pci_name(pdev));
197
198 err = register_framebuffer(info);
199 if (err < 0) {
200 printk(KERN_ERR "s3d: Could not register framebuffer %s\n",
201 pci_name(pdev));
202 goto err_unmap_fb;
203 }
204
205 return 0;
206
207err_unmap_fb:
208 iounmap(sp->fb_base);
209
210err_release_pci:
211 pci_release_region(pdev, 1);
212
213err_release_fb:
214 framebuffer_release(info);
215
216err_disable:
217 pci_disable_device(pdev);
218
219err_out:
220 return err;
221}
222
223static void __devexit s3d_pci_unregister(struct pci_dev *pdev)
224{
225 struct fb_info *info = pci_get_drvdata(pdev);
226 struct s3d_info *sp = info->par;
227
228 unregister_framebuffer(info);
229
230 iounmap(sp->fb_base);
231
232 pci_release_region(pdev, 1);
233
234 framebuffer_release(info);
235
236 pci_disable_device(pdev);
237}
238
239static struct pci_device_id s3d_pci_table[] = {
240 { /* XVR-2500 */
241 PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x0032),
242 .driver_data = 1,
243 },
244 { /* XVR-500 */
245 PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x07a2),
246 .driver_data = 0,
247 },
248 { 0, }
249};
250
251static struct pci_driver s3d_driver = {
252 .name = "s3d",
253 .id_table = s3d_pci_table,
254 .probe = s3d_pci_register,
255 .remove = __devexit_p(s3d_pci_unregister),
256};
257
258static int __init s3d_init(void)
259{
260 if (fb_get_options("s3d", NULL))
261 return -ENODEV;
262
263 return pci_register_driver(&s3d_driver);
264}
265
266static void __exit s3d_exit(void)
267{
268 pci_unregister_driver(&s3d_driver);
269}
270
271module_init(s3d_init);
272module_exit(s3d_exit);
273
274MODULE_DESCRIPTION("framebuffer driver for Sun XVR-2500 graphics");
275MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
276MODULE_VERSION("1.0");
277MODULE_LICENSE("GPL");
diff --git a/drivers/video/sunxvr500.c b/drivers/video/sunxvr500.c
new file mode 100644
index 000000000000..08880a62bfa3
--- /dev/null
+++ b/drivers/video/sunxvr500.c
@@ -0,0 +1,443 @@
1/* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D driver for sparc64 systems
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/module.h>
7#include <linux/kernel.h>
8#include <linux/slab.h>
9#include <linux/fb.h>
10#include <linux/pci.h>
11#include <linux/init.h>
12
13#include <asm/io.h>
14#include <asm/prom.h>
15#include <asm/of_device.h>
16
17/* XXX This device has a 'dev-comm' property which aparently is
18 * XXX a pointer into the openfirmware's address space which is
19 * XXX a shared area the kernel driver can use to keep OBP
20 * XXX informed about the current resolution setting. The idea
21 * XXX is that the kernel can change resolutions, and as long
22 * XXX as the values in the 'dev-comm' area are accurate then
23 * XXX OBP can still render text properly to the console.
24 * XXX
25 * XXX I'm still working out the layout of this and whether there
26 * XXX are any signatures we need to look for etc.
27 */
28struct e3d_info {
29 struct fb_info *info;
30 struct pci_dev *pdev;
31
32 spinlock_t lock;
33
34 char __iomem *fb_base;
35 unsigned long fb_base_phys;
36
37 unsigned long fb8_buf_diff;
38 unsigned long regs_base_phys;
39
40 void __iomem *ramdac;
41
42 struct device_node *of_node;
43
44 unsigned int width;
45 unsigned int height;
46 unsigned int depth;
47 unsigned int fb_size;
48
49 u32 fb_base_reg;
50 u32 fb8_0_off;
51 u32 fb8_1_off;
52
53 u32 pseudo_palette[256];
54};
55
56static int __devinit e3d_get_props(struct e3d_info *ep)
57{
58 ep->width = of_getintprop_default(ep->of_node, "width", 0);
59 ep->height = of_getintprop_default(ep->of_node, "height", 0);
60 ep->depth = of_getintprop_default(ep->of_node, "depth", 8);
61
62 if (!ep->width || !ep->height) {
63 printk(KERN_ERR "e3d: Critical properties missing for %s\n",
64 pci_name(ep->pdev));
65 return -EINVAL;
66 }
67
68 return 0;
69}
70
71/* My XVR-500 comes up, at 1280x768 and a FB base register value of
72 * 0x04000000, the following video layout register values:
73 *
74 * RAMDAC_VID_WH 0x03ff04ff
75 * RAMDAC_VID_CFG 0x1a0b0088
76 * RAMDAC_VID_32FB_0 0x04000000
77 * RAMDAC_VID_32FB_1 0x04800000
78 * RAMDAC_VID_8FB_0 0x05000000
79 * RAMDAC_VID_8FB_1 0x05200000
80 * RAMDAC_VID_XXXFB 0x05400000
81 * RAMDAC_VID_YYYFB 0x05c00000
82 * RAMDAC_VID_ZZZFB 0x05e00000
83 */
84/* Video layout registers */
85#define RAMDAC_VID_WH 0x00000070UL /* (height-1)<<16 | (width-1) */
86#define RAMDAC_VID_CFG 0x00000074UL /* 0x1a000088|(linesz_log2<<16) */
87#define RAMDAC_VID_32FB_0 0x00000078UL /* PCI base 32bpp FB buffer 0 */
88#define RAMDAC_VID_32FB_1 0x0000007cUL /* PCI base 32bpp FB buffer 1 */
89#define RAMDAC_VID_8FB_0 0x00000080UL /* PCI base 8bpp FB buffer 0 */
90#define RAMDAC_VID_8FB_1 0x00000084UL /* PCI base 8bpp FB buffer 1 */
91#define RAMDAC_VID_XXXFB 0x00000088UL /* PCI base of XXX FB */
92#define RAMDAC_VID_YYYFB 0x0000008cUL /* PCI base of YYY FB */
93#define RAMDAC_VID_ZZZFB 0x00000090UL /* PCI base of ZZZ FB */
94
95/* CLUT registers */
96#define RAMDAC_INDEX 0x000000bcUL
97#define RAMDAC_DATA 0x000000c0UL
98
99static void e3d_clut_write(struct e3d_info *ep, int index, u32 val)
100{
101 void __iomem *ramdac = ep->ramdac;
102 unsigned long flags;
103
104 spin_lock_irqsave(&ep->lock, flags);
105
106 writel(index, ramdac + RAMDAC_INDEX);
107 writel(val, ramdac + RAMDAC_DATA);
108
109 spin_unlock_irqrestore(&ep->lock, flags);
110}
111
112static int e3d_setcolreg(unsigned regno,
113 unsigned red, unsigned green, unsigned blue,
114 unsigned transp, struct fb_info *info)
115{
116 struct e3d_info *ep = info->par;
117 u32 red_8, green_8, blue_8;
118 u32 red_10, green_10, blue_10;
119 u32 value;
120
121 if (regno >= 256)
122 return 1;
123
124 red_8 = red >> 8;
125 green_8 = green >> 8;
126 blue_8 = blue >> 8;
127
128 value = (blue_8 << 24) | (green_8 << 16) | (red_8 << 8);
129 ((u32 *)info->pseudo_palette)[regno] = value;
130
131
132 red_10 = red >> 6;
133 green_10 = green >> 6;
134 blue_10 = blue >> 6;
135
136 value = (blue_10 << 20) | (green_10 << 10) | (red_10 << 0);
137 e3d_clut_write(ep, regno, value);
138
139 return 0;
140}
141
142/* XXX This is a bit of a hack. I can't figure out exactly how the
143 * XXX two 8bpp areas of the framebuffer work. I imagine there is
144 * XXX a WID attribute somewhere else in the framebuffer which tells
145 * XXX the ramdac which of the two 8bpp framebuffer regions to take
146 * XXX the pixel from. So, for now, render into both regions to make
147 * XXX sure the pixel shows up.
148 */
149static void e3d_imageblit(struct fb_info *info, const struct fb_image *image)
150{
151 struct e3d_info *ep = info->par;
152 unsigned long flags;
153
154 spin_lock_irqsave(&ep->lock, flags);
155 cfb_imageblit(info, image);
156 info->screen_base += ep->fb8_buf_diff;
157 cfb_imageblit(info, image);
158 info->screen_base -= ep->fb8_buf_diff;
159 spin_unlock_irqrestore(&ep->lock, flags);
160}
161
162static void e3d_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
163{
164 struct e3d_info *ep = info->par;
165 unsigned long flags;
166
167 spin_lock_irqsave(&ep->lock, flags);
168 cfb_fillrect(info, rect);
169 info->screen_base += ep->fb8_buf_diff;
170 cfb_fillrect(info, rect);
171 info->screen_base -= ep->fb8_buf_diff;
172 spin_unlock_irqrestore(&ep->lock, flags);
173}
174
175static void e3d_copyarea(struct fb_info *info, const struct fb_copyarea *area)
176{
177 struct e3d_info *ep = info->par;
178 unsigned long flags;
179
180 spin_lock_irqsave(&ep->lock, flags);
181 cfb_copyarea(info, area);
182 info->screen_base += ep->fb8_buf_diff;
183 cfb_copyarea(info, area);
184 info->screen_base -= ep->fb8_buf_diff;
185 spin_unlock_irqrestore(&ep->lock, flags);
186}
187
188static struct fb_ops e3d_ops = {
189 .owner = THIS_MODULE,
190 .fb_setcolreg = e3d_setcolreg,
191 .fb_fillrect = e3d_fillrect,
192 .fb_copyarea = e3d_copyarea,
193 .fb_imageblit = e3d_imageblit,
194};
195
196static int __devinit e3d_set_fbinfo(struct e3d_info *ep)
197{
198 struct fb_info *info = ep->info;
199 struct fb_var_screeninfo *var = &info->var;
200
201 info->flags = FBINFO_DEFAULT;
202 info->fbops = &e3d_ops;
203 info->screen_base = ep->fb_base;
204 info->screen_size = ep->fb_size;
205
206 info->pseudo_palette = ep->pseudo_palette;
207
208 /* Fill fix common fields */
209 strlcpy(info->fix.id, "e3d", sizeof(info->fix.id));
210 info->fix.smem_start = ep->fb_base_phys;
211 info->fix.smem_len = ep->fb_size;
212 info->fix.type = FB_TYPE_PACKED_PIXELS;
213 if (ep->depth == 32 || ep->depth == 24)
214 info->fix.visual = FB_VISUAL_TRUECOLOR;
215 else
216 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
217
218 var->xres = ep->width;
219 var->yres = ep->height;
220 var->xres_virtual = var->xres;
221 var->yres_virtual = var->yres;
222 var->bits_per_pixel = ep->depth;
223
224 var->red.offset = 8;
225 var->red.length = 8;
226 var->green.offset = 16;
227 var->green.length = 8;
228 var->blue.offset = 24;
229 var->blue.length = 8;
230 var->transp.offset = 0;
231 var->transp.length = 0;
232
233 if (fb_alloc_cmap(&info->cmap, 256, 0)) {
234 printk(KERN_ERR "e3d: Cannot allocate color map.\n");
235 return -ENOMEM;
236 }
237
238 return 0;
239}
240
241static int __devinit e3d_pci_register(struct pci_dev *pdev,
242 const struct pci_device_id *ent)
243{
244 struct fb_info *info;
245 struct e3d_info *ep;
246 unsigned int line_length;
247 int err;
248
249 err = pci_enable_device(pdev);
250 if (err < 0) {
251 printk(KERN_ERR "e3d: Cannot enable PCI device %s\n",
252 pci_name(pdev));
253 goto err_out;
254 }
255
256 info = framebuffer_alloc(sizeof(struct e3d_info), &pdev->dev);
257 if (!info) {
258 printk(KERN_ERR "e3d: Cannot allocate fb_info\n");
259 err = -ENOMEM;
260 goto err_disable;
261 }
262
263 ep = info->par;
264 ep->info = info;
265 ep->pdev = pdev;
266 spin_lock_init(&ep->lock);
267 ep->of_node = pci_device_to_OF_node(pdev);
268 if (!ep->of_node) {
269 printk(KERN_ERR "e3d: Cannot find OF node of %s\n",
270 pci_name(pdev));
271 err = -ENODEV;
272 goto err_release_fb;
273 }
274
275 /* Read the PCI base register of the frame buffer, which we
276 * need in order to interpret the RAMDAC_VID_*FB* values in
277 * the ramdac correctly.
278 */
279 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
280 &ep->fb_base_reg);
281 ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK;
282
283 ep->regs_base_phys = pci_resource_start (pdev, 1);
284 err = pci_request_region(pdev, 1, "e3d regs");
285 if (err < 0) {
286 printk("e3d: Cannot request region 1 for %s\n",
287 pci_name(pdev));
288 goto err_release_fb;
289 }
290 ep->ramdac = ioremap(ep->regs_base_phys + 0x8000, 0x1000);
291 if (!ep->ramdac)
292 goto err_release_pci1;
293
294 ep->fb8_0_off = readl(ep->ramdac + RAMDAC_VID_8FB_0);
295 ep->fb8_0_off -= ep->fb_base_reg;
296
297 ep->fb8_1_off = readl(ep->ramdac + RAMDAC_VID_8FB_1);
298 ep->fb8_1_off -= ep->fb_base_reg;
299
300 ep->fb8_buf_diff = ep->fb8_1_off - ep->fb8_0_off;
301
302 ep->fb_base_phys = pci_resource_start (pdev, 0);
303 ep->fb_base_phys += ep->fb8_0_off;
304
305 err = pci_request_region(pdev, 0, "e3d framebuffer");
306 if (err < 0) {
307 printk("e3d: Cannot request region 0 for %s\n",
308 pci_name(pdev));
309 goto err_unmap_ramdac;
310 }
311
312 err = e3d_get_props(ep);
313 if (err)
314 goto err_release_pci0;
315
316 line_length = (readl(ep->ramdac + RAMDAC_VID_CFG) >> 16) & 0xff;
317 line_length = 1 << line_length;
318
319 switch (ep->depth) {
320 case 8:
321 info->fix.line_length = line_length;
322 break;
323 case 16:
324 info->fix.line_length = line_length * 2;
325 break;
326 case 24:
327 info->fix.line_length = line_length * 3;
328 break;
329 case 32:
330 info->fix.line_length = line_length * 4;
331 break;
332 }
333 ep->fb_size = info->fix.line_length * ep->height;
334
335 ep->fb_base = ioremap(ep->fb_base_phys, ep->fb_size);
336 if (!ep->fb_base)
337 goto err_release_pci0;
338
339 err = e3d_set_fbinfo(ep);
340 if (err)
341 goto err_unmap_fb;
342
343 pci_set_drvdata(pdev, info);
344
345 printk("e3d: Found device at %s\n", pci_name(pdev));
346
347 err = register_framebuffer(info);
348 if (err < 0) {
349 printk(KERN_ERR "e3d: Could not register framebuffer %s\n",
350 pci_name(pdev));
351 goto err_unmap_fb;
352 }
353
354 return 0;
355
356err_unmap_fb:
357 iounmap(ep->fb_base);
358
359err_release_pci0:
360 pci_release_region(pdev, 0);
361
362err_unmap_ramdac:
363 iounmap(ep->ramdac);
364
365err_release_pci1:
366 pci_release_region(pdev, 1);
367
368err_release_fb:
369 framebuffer_release(info);
370
371err_disable:
372 pci_disable_device(pdev);
373
374err_out:
375 return err;
376}
377
378static void __devexit e3d_pci_unregister(struct pci_dev *pdev)
379{
380 struct fb_info *info = pci_get_drvdata(pdev);
381 struct e3d_info *ep = info->par;
382
383 unregister_framebuffer(info);
384
385 iounmap(ep->ramdac);
386 iounmap(ep->fb_base);
387
388 pci_release_region(pdev, 0);
389 pci_release_region(pdev, 1);
390
391 framebuffer_release(info);
392
393 pci_disable_device(pdev);
394}
395
396static struct pci_device_id e3d_pci_table[] = {
397 { PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a0), },
398 { PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a2), },
399 { .vendor = PCI_VENDOR_ID_3DLABS,
400 .device = PCI_ANY_ID,
401 .subvendor = PCI_VENDOR_ID_3DLABS,
402 .subdevice = 0x0108,
403 },
404 { .vendor = PCI_VENDOR_ID_3DLABS,
405 .device = PCI_ANY_ID,
406 .subvendor = PCI_VENDOR_ID_3DLABS,
407 .subdevice = 0x0140,
408 },
409 { .vendor = PCI_VENDOR_ID_3DLABS,
410 .device = PCI_ANY_ID,
411 .subvendor = PCI_VENDOR_ID_3DLABS,
412 .subdevice = 0x1024,
413 },
414 { 0, }
415};
416
417static struct pci_driver e3d_driver = {
418 .name = "e3d",
419 .id_table = e3d_pci_table,
420 .probe = e3d_pci_register,
421 .remove = __devexit_p(e3d_pci_unregister),
422};
423
424static int __init e3d_init(void)
425{
426 if (fb_get_options("e3d", NULL))
427 return -ENODEV;
428
429 return pci_register_driver(&e3d_driver);
430}
431
432static void __exit e3d_exit(void)
433{
434 pci_unregister_driver(&e3d_driver);
435}
436
437module_init(e3d_init);
438module_exit(e3d_exit);
439
440MODULE_DESCRIPTION("framebuffer driver for Sun XVR-500 graphics");
441MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
442MODULE_VERSION("1.0");
443MODULE_LICENSE("GPL");
diff --git a/include/asm-sparc64/iommu.h b/include/asm-sparc64/iommu.h
index e199594a1e9b..0b1813f41045 100644
--- a/include/asm-sparc64/iommu.h
+++ b/include/asm-sparc64/iommu.h
@@ -32,6 +32,7 @@ struct iommu {
32 unsigned long iommu_control; 32 unsigned long iommu_control;
33 unsigned long iommu_tsbbase; 33 unsigned long iommu_tsbbase;
34 unsigned long iommu_flush; 34 unsigned long iommu_flush;
35 unsigned long iommu_flushinv;
35 unsigned long iommu_ctxflush; 36 unsigned long iommu_ctxflush;
36 unsigned long write_complete_reg; 37 unsigned long write_complete_reg;
37 unsigned long dummy_page; 38 unsigned long dummy_page;
diff --git a/mm/sparse.c b/mm/sparse.c
index ac26eb0d73cd..893e5621c247 100644
--- a/mm/sparse.c
+++ b/mm/sparse.c
@@ -272,7 +272,7 @@ static void __kfree_section_memmap(struct page *memmap, unsigned long nr_pages)
272 * Allocate the accumulated non-linear sections, allocate a mem_map 272 * Allocate the accumulated non-linear sections, allocate a mem_map
273 * for each and record the physical to section mapping. 273 * for each and record the physical to section mapping.
274 */ 274 */
275void sparse_init(void) 275void __init sparse_init(void)
276{ 276{
277 unsigned long pnum; 277 unsigned long pnum;
278 struct page *map; 278 struct page *map;
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-28 21:16:45 -0400