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-rw-r--r--drivers/spi/Kconfig8
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi_topcliff_pch.c1529
3 files changed, 1538 insertions, 0 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 91c2f4f3af10..b32167a686bb 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -298,6 +298,14 @@ config SPI_STMP3XXX
298 help 298 help
299 SPI driver for Freescale STMP37xx/378x SoC SSP interface 299 SPI driver for Freescale STMP37xx/378x SoC SSP interface
300 300
301config SPI_TOPCLIFF_PCH
302 tristate "PCH SPI Controller"
303 depends on PCI
304 help
305 This driver is for PCH(Platform controller Hub) SPI of Topcliff which
306 is an IOH(Input/Output Hub) for x86 embedded processor.
307 This driver can access PCH SPI bus device.
308
301config SPI_TXX9 309config SPI_TXX9
302 tristate "Toshiba TXx9 SPI controller" 310 tristate "Toshiba TXx9 SPI controller"
303 depends on GENERIC_GPIO && CPU_TX49XX 311 depends on GENERIC_GPIO && CPU_TX49XX
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index e9cbd18217a0..65a232d50bc8 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
39obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o 39obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
40obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx_hw.o 40obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx_hw.o
41obj-$(CONFIG_SPI_S3C64XX) += spi_s3c64xx.o 41obj-$(CONFIG_SPI_S3C64XX) += spi_s3c64xx.o
42obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi_topcliff_pch.o
42obj-$(CONFIG_SPI_TXX9) += spi_txx9.o 43obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
43obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o 44obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
44obj-$(CONFIG_SPI_XILINX_OF) += xilinx_spi_of.o 45obj-$(CONFIG_SPI_XILINX_OF) += xilinx_spi_of.o
diff --git a/drivers/spi/spi_topcliff_pch.c b/drivers/spi/spi_topcliff_pch.c
new file mode 100644
index 000000000000..58b183f6eec0
--- /dev/null
+++ b/drivers/spi/spi_topcliff_pch.c
@@ -0,0 +1,1529 @@
1/*
2 * SPI bus driver for the Topcliff PCH used by Intel SoCs
3 */
4
5/*
6 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include <linux/pci.h>
23#include <linux/wait.h>
24#include <linux/spi/spi.h>
25#include <linux/interrupt.h>
26#include <linux/sched.h>
27#include <linux/spi/spidev.h>
28#include <linux/module.h>
29#include <linux/device.h>
30
31/* Register offsets */
32#define PCH_SPCR 0x00 /* SPI control register */
33#define PCH_SPBRR 0x04 /* SPI baud rate register */
34#define PCH_SPSR 0x08 /* SPI status register */
35#define PCH_SPDWR 0x0C /* SPI write data register */
36#define PCH_SPDRR 0x10 /* SPI read data register */
37#define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
38#define PCH_SRST 0x1C /* SPI reset register */
39
40#define PCH_SPSR_TFD 0x000007C0
41#define PCH_SPSR_RFD 0x0000F800
42
43#define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
44#define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
45
46#define PCH_RX_THOLD 7
47#define PCH_RX_THOLD_MAX 15
48#define PCH_RX 1
49#define PCH_TX 2
50
51/* various interrupts */
52#define PCH_TFI 0x1
53#define PCH_RFI 0x2
54#define PCH_FI 0x4
55#define PCH_ORI 0x8
56#define PCH_MDFI 0x10
57
58#define PCH_ALL (PCH_TFI|PCH_RFI|PCH_FI|PCH_ORI|PCH_MDFI)
59#define PCH_MAX_BAUDRATE 5000000
60#define PCH_MAX_FIFO_DEPTH 16
61
62#define STATUS_RUNNING 1
63#define STATUS_EXITING 2
64#define PCH_SLEEP_TIME 10
65
66#define PCH_ADDRESS_SIZE 0x20
67
68#define SSN_LOW 0x02U
69#define SSN_NO_CONTROL 0x00U
70#define PCH_MAX_CS 0xFF
71#define PCI_DEVICE_ID_GE_SPI 0x8816
72
73#define SPCR_SPE_BIT (1 << 0)
74#define SPCR_MSTR_BIT (1 << 1)
75#define SPCR_LSBF_BIT (1 << 4)
76#define SPCR_CPHA_BIT (1 << 5)
77#define SPCR_CPOL_BIT (1 << 6)
78#define SPCR_TFIE_BIT (1 << 8)
79#define SPCR_RFIE_BIT (1 << 9)
80#define SPCR_FIE_BIT (1 << 10)
81#define SPCR_ORIE_BIT (1 << 11)
82#define SPCR_MDFIE_BIT (1 << 12)
83#define SPCR_FICLR_BIT (1 << 24)
84#define SPSR_TFI_BIT (1 << 0)
85#define SPSR_RFI_BIT (1 << 1)
86#define SPSR_FI_BIT (1 << 2)
87#define SPBRR_SIZE_BIT (1 << 10)
88
89#define SPCR_RFIC_FIELD 20
90#define SPCR_TFIC_FIELD 16
91
92#define SPSR_INT_BITS 0x1F
93#define MASK_SPBRR_SPBR_BITS (~((1 << 10) - 1))
94#define MASK_RFIC_SPCR_BITS (~(0xf << 20))
95#define MASK_TFIC_SPCR_BITS (~(0xf000f << 12))
96
97#define PCH_CLOCK_HZ 50000000
98#define PCH_MAX_SPBR 1023
99
100
101/**
102 * struct pch_spi_data - Holds the SPI channel specific details
103 * @io_remap_addr: The remapped PCI base address
104 * @master: Pointer to the SPI master structure
105 * @work: Reference to work queue handler
106 * @wk: Workqueue for carrying out execution of the
107 * requests
108 * @wait: Wait queue for waking up upon receiving an
109 * interrupt.
110 * @transfer_complete: Status of SPI Transfer
111 * @bcurrent_msg_processing: Status flag for message processing
112 * @lock: Lock for protecting this structure
113 * @queue: SPI Message queue
114 * @status: Status of the SPI driver
115 * @bpw_len: Length of data to be transferred in bits per
116 * word
117 * @transfer_active: Flag showing active transfer
118 * @tx_index: Transmit data count; for bookkeeping during
119 * transfer
120 * @rx_index: Receive data count; for bookkeeping during
121 * transfer
122 * @tx_buff: Buffer for data to be transmitted
123 * @rx_index: Buffer for Received data
124 * @n_curnt_chip: The chip number that this SPI driver currently
125 * operates on
126 * @current_chip: Reference to the current chip that this SPI
127 * driver currently operates on
128 * @current_msg: The current message that this SPI driver is
129 * handling
130 * @cur_trans: The current transfer that this SPI driver is
131 * handling
132 * @board_dat: Reference to the SPI device data structure
133 */
134struct pch_spi_data {
135 void __iomem *io_remap_addr;
136 struct spi_master *master;
137 struct work_struct work;
138 struct workqueue_struct *wk;
139 wait_queue_head_t wait;
140 u8 transfer_complete;
141 u8 bcurrent_msg_processing;
142 spinlock_t lock;
143 struct list_head queue;
144 u8 status;
145 u32 bpw_len;
146 u8 transfer_active;
147 u32 tx_index;
148 u32 rx_index;
149 u16 *pkt_tx_buff;
150 u16 *pkt_rx_buff;
151 u8 n_curnt_chip;
152 struct spi_device *current_chip;
153 struct spi_message *current_msg;
154 struct spi_transfer *cur_trans;
155 struct pch_spi_board_data *board_dat;
156};
157
158/**
159 * struct pch_spi_board_data - Holds the SPI device specific details
160 * @pdev: Pointer to the PCI device
161 * @irq_reg_sts: Status of IRQ registration
162 * @pci_req_sts: Status of pci_request_regions
163 * @suspend_sts: Status of suspend
164 * @data: Pointer to SPI channel data structure
165 */
166struct pch_spi_board_data {
167 struct pci_dev *pdev;
168 u8 irq_reg_sts;
169 u8 pci_req_sts;
170 u8 suspend_sts;
171 struct pch_spi_data *data;
172};
173
174static struct pci_device_id pch_spi_pcidev_id[] = {
175 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_GE_SPI)},
176 {0,}
177};
178
179static inline void pch_set_bitmsk(u32 *var, u32 bitmask)
180{
181 *var |= bitmask;
182}
183
184static inline void pch_clr_bitmsk(u32 *var, u32 bitmask)
185{
186 *var &= (~(bitmask));
187}
188
189/**
190 * pch_spi_writereg() - Performs register writes
191 * @master: Pointer to struct spi_master.
192 * @idx: Register offset.
193 * @val: Value to be written to register.
194 */
195static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
196{
197
198 struct pch_spi_data *data = spi_master_get_devdata(master);
199
200 iowrite32(val, (data->io_remap_addr + idx));
201}
202
203/**
204 * pch_spi_readreg() - Performs register reads
205 * @master: Pointer to struct spi_master.
206 * @idx: Register offset.
207 */
208static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
209{
210 struct pch_spi_data *data = spi_master_get_devdata(master);
211
212 return ioread32(data->io_remap_addr + idx);
213}
214
215/* ope==true:Set bit, ope==false:Clear bit */
216static inline void pch_spi_setclr_bit(u32 *val, u32 pos, bool ope)
217{
218 if (ope)
219 *val |= pos;
220 else
221 *val &= (~(pos));
222}
223
224static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
225 u32 set, u32 clr)
226{
227 u32 tmp = pch_spi_readreg(master, idx);
228 tmp = (tmp & ~clr) | set;
229 pch_spi_writereg(master, idx, tmp);
230}
231
232
233static void pch_spi_set_master_mode(struct spi_master *master)
234{
235 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
236}
237
238/**
239 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
240 * @master: Pointer to struct spi_master.
241 */
242static void pch_spi_clear_fifo(struct spi_master *master)
243{
244 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
245 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
246}
247
248/**
249 * ch_spi_disable_interrupts() - Disables specified interrupts
250 * @master: Pointer to struct spi_master.
251 * @interrupt: Interrups to be enabled.
252 */
253static void pch_spi_disable_interrupts(struct spi_master *master, u8 interrupt)
254{
255 u32 clr_flags = 0;
256
257 if (interrupt & PCH_RFI)
258 clr_flags |= SPCR_RFIE_BIT;
259
260 if (interrupt & PCH_TFI)
261 clr_flags |= SPCR_TFIE_BIT;
262
263 if (interrupt & PCH_FI)
264 clr_flags |= SPCR_FIE_BIT;
265
266 if (interrupt & PCH_ORI)
267 clr_flags |= SPCR_ORIE_BIT;
268
269 if (interrupt & PCH_MDFI)
270 clr_flags |= SPCR_MDFIE_BIT;
271
272 pch_spi_setclr_reg(master, PCH_SPCR, 0, clr_flags);
273
274 dev_dbg(&master->dev, "%s clearing bits =%x\n", __func__, clr_flags);
275}
276
277static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
278 void __iomem *io_remap_addr)
279{
280 u32 n_read, tx_index, rx_index, bpw_len;
281 u16 *pkt_rx_buffer, *pkt_tx_buff;
282 int read_cnt;
283 u32 reg_spcr_val;
284 void __iomem *spsr;
285 void __iomem *spdrr;
286 void __iomem *spdwr;
287
288 spsr = io_remap_addr + PCH_SPSR;
289 iowrite32(reg_spsr_val, spsr);
290
291 if (data->transfer_active) {
292 rx_index = data->rx_index;
293 tx_index = data->tx_index;
294 bpw_len = data->bpw_len;
295 pkt_rx_buffer = data->pkt_rx_buff;
296 pkt_tx_buff = data->pkt_tx_buff;
297
298 spdrr = io_remap_addr + PCH_SPDRR;
299 spdwr = io_remap_addr + PCH_SPDWR;
300
301 n_read = PCH_READABLE(reg_spsr_val);
302
303 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
304 pkt_rx_buffer[rx_index++] = ioread32(spdrr);
305 if (tx_index < bpw_len)
306 iowrite32(pkt_tx_buff[tx_index++], spdwr);
307 }
308
309 /* disable RFI if not needed */
310 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
311 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
312
313 /* disable RFI */
314 pch_clr_bitmsk(&reg_spcr_val, SPCR_RFIE_BIT);
315
316 /* reset rx threshold */
317 reg_spcr_val &= MASK_RFIC_SPCR_BITS;
318 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
319 iowrite32(((reg_spcr_val) &= (~(SPCR_RFIE_BIT))),
320 (io_remap_addr + PCH_SPCR));
321 }
322
323 /* update counts */
324 data->tx_index = tx_index;
325 data->rx_index = rx_index;
326
327 }
328
329 /* if transfer complete interrupt */
330 if (reg_spsr_val & SPSR_FI_BIT) {
331 /* disable FI & RFI interrupts */
332 pch_spi_disable_interrupts(data->master, PCH_FI | PCH_RFI);
333
334 /* transfer is completed;inform pch_spi_process_messages */
335 data->transfer_complete = true;
336 wake_up(&data->wait);
337 }
338}
339
340
341/**
342 * pch_spi_handler() - Interrupt handler
343 * @irq: The interrupt number.
344 * @dev_id: Pointer to struct pch_spi_board_data.
345 */
346static irqreturn_t pch_spi_handler(int irq, void *dev_id)
347{
348 u32 reg_spsr_val;
349 struct pch_spi_data *data;
350 void __iomem *spsr;
351 void __iomem *io_remap_addr;
352 irqreturn_t ret = IRQ_NONE;
353
354 struct pch_spi_board_data *board_dat = dev_id;
355
356 if (board_dat->suspend_sts) {
357 dev_dbg(&board_dat->pdev->dev,
358 "%s returning due to suspend\n", __func__);
359 return IRQ_NONE;
360 }
361
362 data = board_dat->data;
363 io_remap_addr = data->io_remap_addr;
364 spsr = io_remap_addr + PCH_SPSR;
365
366 reg_spsr_val = ioread32(spsr);
367
368 /* Check if the interrupt is for SPI device */
369
370 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
371 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
372 ret = IRQ_HANDLED;
373 }
374
375 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
376 __func__, ret);
377
378 return ret;
379}
380
381/**
382 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
383 * @master: Pointer to struct spi_master.
384 * @speed_hz: Baud rate.
385 */
386static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
387{
388 u32 n_spbr;
389
390 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
391
392 /* if baud rate is less than we can support limit it */
393
394 if (n_spbr > PCH_MAX_SPBR)
395 n_spbr = PCH_MAX_SPBR;
396
397 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, ~MASK_SPBRR_SPBR_BITS);
398}
399
400/**
401 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
402 * @master: Pointer to struct spi_master.
403 * @bits_per_word: Bits per word for SPI transfer.
404 */
405static void pch_spi_set_bits_per_word(struct spi_master *master,
406 u8 bits_per_word)
407{
408 if (bits_per_word == 8)
409 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
410 else
411 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
412}
413
414/**
415 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
416 * @spi: Pointer to struct spi_device.
417 */
418static void pch_spi_setup_transfer(struct spi_device *spi)
419{
420 u32 reg_spcr_val;
421
422 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
423 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
424 spi->max_speed_hz);
425
426 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
427
428 /* set bits per word */
429 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
430
431 if (spi->mode & SPI_LSB_FIRST)
432 pch_spi_setclr_reg(spi->master, PCH_SPCR, 0, SPCR_LSBF_BIT);
433 else
434 pch_spi_setclr_reg(spi->master, PCH_SPCR, SPCR_LSBF_BIT, 0);
435
436 if (spi->mode & SPI_CPOL)
437 pch_spi_setclr_reg(spi->master, PCH_SPCR, SPCR_CPOL_BIT, 0);
438 else
439 pch_spi_setclr_reg(spi->master, PCH_SPCR, 0, SPCR_CPOL_BIT);
440
441 if (spi->mode & SPI_CPHA)
442 pch_spi_setclr_reg(spi->master, PCH_SPCR, SPCR_CPHA_BIT, 0);
443 else
444 pch_spi_setclr_reg(spi->master, PCH_SPCR, 0, SPCR_CPHA_BIT);
445
446 dev_dbg(&spi->dev,
447 "%s SPCR content after setting LSB/MSB and MODE= %x\n",
448 __func__, reg_spcr_val);
449
450 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
451 pch_spi_clear_fifo(spi->master);
452}
453
454/**
455 * pch_spi_enable_interrupts() - Enables specified interrupts
456 * @master: Pointer to struct spi_master.
457 * @interrupt: Interrups to be enabled.
458 */
459static void pch_spi_enable_interrupts(struct spi_master *master, u8 interrupt)
460{
461 u32 reg_val_spcr;
462
463 dev_dbg(&master->dev, "%s SPCR content=%x\n", __func__, reg_val_spcr);
464
465 if (interrupt & PCH_RFI) {
466 /* set RFIE bit in SPCR */
467 dev_dbg(&master->dev, "setting RFI in %s\n", __func__);
468 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_RFIE_BIT, 0);
469 }
470
471 if (interrupt & PCH_TFI) {
472 /* set TFIE bit in SPCR */
473 dev_dbg(&master->dev, "setting TFI in %s\n", __func__);
474 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_TFIE_BIT, 0);
475 }
476
477 if (interrupt & PCH_FI) {
478 /* set FIE bit in SPCR */
479 dev_dbg(&master->dev, "setting FI in %s\n", __func__);
480 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FIE_BIT, 0);
481 }
482
483 if (interrupt & PCH_ORI) {
484 /* set ORIE bit in SPCR */
485 dev_dbg(&master->dev, "setting ORI in %s\n", __func__);
486 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_ORIE_BIT, 0);
487 }
488
489 if (interrupt & PCH_MDFI) {
490 /* set MODFIE bit in SPCR */
491 dev_dbg(&master->dev, "setting MDFI in %s\n", __func__);
492 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MDFIE_BIT, 0);
493 }
494}
495
496/**
497 * pch_spi_set_threshold() - Sets Tx/Rx FIFO thresholds
498 * @spi: Pointer to struct spi_device.
499 * @threshold: Threshold value to be set.
500 * @dir: Rx or Tx threshold to be set.
501 */
502static void pch_spi_set_threshold(struct spi_device *spi, u32 threshold, u8 dir)
503{
504
505 if (dir == PCH_RX) {
506 dev_dbg(&spi->dev, "%s setting Rx threshold\n", __func__);
507 pch_spi_setclr_reg(spi->master, PCH_SPCR,
508 threshold << SPCR_RFIC_FIELD,
509 ~MASK_RFIC_SPCR_BITS);
510
511 } else if (dir == PCH_TX) {
512 dev_dbg(&spi->dev, "%s setting Tx threshold\n", __func__);
513 pch_spi_setclr_reg(spi->master, PCH_SPCR,
514 (threshold << SPCR_TFIC_FIELD) ,
515 ~MASK_TFIC_SPCR_BITS);
516 }
517}
518
519/**
520 * pch_spi_reset() - Clears SPI registers
521 * @master: Pointer to struct spi_master.
522 */
523static void pch_spi_reset(struct spi_master *master)
524{
525 /* write 1 to reset SPI */
526 pch_spi_writereg(master, PCH_SRST, 0x1);
527
528 /* clear reset */
529 pch_spi_writereg(master, PCH_SRST, 0x0);
530}
531
532static int pch_spi_setup(struct spi_device *pspi)
533{
534 /* check bits per word */
535 if ((pspi->bits_per_word) == 0) {
536 pspi->bits_per_word = 8;
537 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
538 }
539
540 if (((pspi->bits_per_word) != 8) &&
541 ((pspi->bits_per_word != 16))) {
542 dev_err(&pspi->dev, "%s Invalid bits per word\n", __func__);
543 return -EINVAL;
544 }
545
546 /* Check baud rate setting */
547 /* if baud rate of chip is greater than
548 max we can support,return error */
549 if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE)
550 pspi->max_speed_hz = PCH_MAX_BAUDRATE;
551
552 dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__,
553 ((pspi->mode) & (SPI_CPOL | SPI_CPHA)));
554
555 return 0;
556}
557
558static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
559{
560
561 struct spi_transfer *transfer;
562 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
563 int retval;
564 unsigned long flags;
565
566 /* validate spi message and baud rate */
567 if (unlikely((list_empty(&pmsg->transfers) == 1) ||
568 (pspi->max_speed_hz == 0))) {
569 if (list_empty(&pmsg->transfers) == 1)
570 dev_err(&pspi->dev, "%s list empty\n", __func__);
571
572 if ((pspi->max_speed_hz) == 0) {
573 dev_err(&pspi->dev, "%s pch_spi_tranfer maxspeed=%d\n",
574 __func__, pspi->max_speed_hz);
575 }
576 dev_err(&pspi->dev, "%s returning EINVAL\n", __func__);
577
578 retval = -EINVAL;
579 goto err_out;
580 }
581
582 dev_dbg(&pspi->dev, "%s Transfer List not empty. "
583 "Transfer Speed is set.\n", __func__);
584
585 spin_lock_irqsave(&data->lock, flags);
586
587 /* validate Tx/Rx buffers and Transfer length */
588 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
589 if ((!(transfer->tx_buf)) && (!(transfer->rx_buf))) {
590 dev_err(&pspi->dev,
591 "%s Tx and Rx buffer NULL\n", __func__);
592 retval = -EINVAL;
593 goto err_return_spinlock;
594 }
595
596 if (!(transfer->len)) {
597 dev_err(&pspi->dev, "%s Transfer length invalid\n",
598 __func__);
599 retval = -EINVAL;
600 goto err_return_spinlock;
601 }
602
603 dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length"
604 " valid\n", __func__);
605
606 /* if baud rate hs been specified validate the same */
607 if (transfer->speed_hz) {
608 if ((transfer->speed_hz) > PCH_MAX_BAUDRATE)
609 transfer->speed_hz = PCH_MAX_BAUDRATE;
610 }
611
612 /* if bits per word has been specified validate the same */
613 if (transfer->bits_per_word) {
614 if ((transfer->bits_per_word != 8)
615 && (transfer->bits_per_word != 16)) {
616 retval = -EINVAL;
617 dev_err(&pspi->dev,
618 "%s Invalid bits per word\n", __func__);
619 goto err_return_spinlock;
620 }
621 }
622 }
623
624 /* We won't process any messages if we have been asked to terminate */
625
626 if (STATUS_EXITING == (data->status)) {
627 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
628 retval = -ESHUTDOWN;
629 goto err_return_spinlock;
630 }
631
632 /* If suspended ,return -EINVAL */
633 if (data->board_dat->suspend_sts) {
634 dev_err(&pspi->dev,
635 "%s bSuspending= true returning EINVAL\n", __func__);
636 retval = -EINVAL;
637 goto err_return_spinlock;
638 }
639
640 /* set status of message */
641 pmsg->actual_length = 0;
642
643 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
644
645 pmsg->status = -EINPROGRESS;
646
647 /* add message to queue */
648 list_add_tail(&pmsg->queue, &data->queue);
649
650 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
651
652 /* schedule work queue to run */
653 queue_work(data->wk, &data->work);
654
655 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
656
657 retval = 0;
658
659err_return_spinlock:
660 spin_unlock_irqrestore(&data->lock, flags);
661err_out:
662 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
663 return retval;
664}
665
666static inline void pch_spi_select_chip(struct pch_spi_data *data,
667 struct spi_device *pspi)
668{
669 if ((data->current_chip) != NULL) {
670 if ((pspi->chip_select) != (data->n_curnt_chip)) {
671 dev_dbg(&pspi->dev,
672 "%s : different slave-Invoking\n", __func__);
673 data->current_chip = NULL;
674 }
675 }
676
677 data->current_chip = pspi;
678
679 data->n_curnt_chip = data->current_chip->chip_select;
680
681 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
682 pch_spi_setup_transfer(pspi);
683}
684
685static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw,
686 struct spi_message **ppmsg)
687{
688 int b_mem_fail;
689 int size;
690 u32 n_writes;
691 int j;
692 struct spi_message *pmsg;
693 const u8 *tx_buf;
694 const u16 *tx_sbuf;
695
696 pmsg = *ppmsg;
697
698 /* set baud rate if needed */
699 if (data->cur_trans->speed_hz) {
700 dev_dbg(&data->master->dev,
701 "%s:pctrldatasetting baud rate\n", __func__);
702 pch_spi_set_baud_rate(data->master,
703 (data->cur_trans->speed_hz));
704 }
705
706 /* set bits per word if needed */
707 if ((data->cur_trans->bits_per_word) &&
708 ((data->current_msg->spi->bits_per_word) !=
709 (data->cur_trans->bits_per_word))) {
710 dev_dbg(&data->master->dev,
711 "%s:setting bits per word\n", __func__);
712 pch_spi_set_bits_per_word(data->master,
713 (data->cur_trans->bits_per_word));
714 *bpw = data->cur_trans->bits_per_word;
715 } else {
716 *bpw = data->current_msg->spi->bits_per_word;
717 }
718
719 /* reset Tx/Rx index */
720 data->tx_index = 0;
721 data->rx_index = 0;
722
723 data->bpw_len = data->cur_trans->len / (*bpw / 8);
724 b_mem_fail = false;
725
726 /* find alloc size */
727 size = (data->cur_trans->len) * (sizeof(*(data->pkt_tx_buff)));
728 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
729 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
730
731 if (data->pkt_tx_buff != NULL) {
732 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
733
734 if (data->pkt_rx_buff == NULL) {
735 b_mem_fail = true;
736 kfree(data->pkt_tx_buff);
737 }
738 } else {
739 b_mem_fail = true;
740 }
741
742 if (b_mem_fail) {
743 /* flush queue and set status of all transfers to -ENOMEM */
744 dev_err(&data->master->dev,
745 "Kzalloc fail in %s messages\n", __func__);
746 list_for_each_entry(pmsg, data->queue.next, queue) {
747 pmsg->status = -ENOMEM;
748
749 if (pmsg->complete != 0)
750 pmsg->complete(pmsg->context);
751
752 /* delete from queue */
753 list_del_init(&pmsg->queue);
754 }
755
756 return;
757 }
758
759 /* copy Tx Data */
760 if ((data->cur_trans->tx_buf) != NULL) {
761 if (*bpw == 8) {
762 for (j = 0; j < (data->bpw_len); j++) {
763 tx_buf = data->cur_trans->tx_buf;
764 data->pkt_tx_buff[j] = tx_buf[j];
765 }
766 } else {
767 for (j = 0; j < (data->bpw_len); j++) {
768 tx_sbuf = data->cur_trans->tx_buf;
769 data->pkt_tx_buff[j] = tx_sbuf[j];
770 }
771 }
772 }
773
774 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
775 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
776 n_writes = PCH_MAX_FIFO_DEPTH;
777 else
778 n_writes = (data->bpw_len);
779
780 dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
781 "0x2 to SSNXCR\n", __func__);
782 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
783
784 for (j = 0; j < n_writes; j++) {
785 pch_spi_writereg(data->master, PCH_SPDWR,
786 data->pkt_tx_buff[j]);
787 }
788
789 /* update tx_index */
790 data->tx_index = j;
791
792 /* reset transfer complete flag */
793 data->transfer_complete = false;
794 data->transfer_active = true;
795}
796
797
798static void pch_spi_nomore_transfer(struct pch_spi_data *data,
799 struct spi_message *pmsg)
800{
801 dev_dbg(&data->master->dev,
802 "%s:no more transfers in this message\n", __func__);
803 /* Invoke complete callback
804 [To the spi core..indicating end of transfer] */
805 data->current_msg->status = 0;
806
807 if ((data->current_msg->complete) != 0) {
808 dev_dbg(&data->master->dev,
809 "%s:Invoking callback of SPI core\n", __func__);
810 data->current_msg->complete(data->current_msg->context);
811 }
812
813 /* update status in global variable */
814 data->bcurrent_msg_processing = false;
815
816 dev_dbg(&data->master->dev,
817 "%s:data->bcurrent_msg_processing = false\n", __func__);
818
819 data->current_msg = NULL;
820 data->cur_trans = NULL;
821
822 /* check if we have items in list and not suspending */
823 /* return 1 if list empty */
824 if ((list_empty(&data->queue) == 0) &&
825 (!(data->board_dat->suspend_sts))
826 && (data->status != STATUS_EXITING)) {
827 /* We have some more work to do (either there is more tranint
828 bpw;sfer requests in the current message or there are
829 more messages)
830 */
831 dev_dbg(&data->master->dev,
832 "%s:we have pending messages-Invoking queue_work\n",
833 __func__);
834 queue_work(data->wk, &data->work);
835 } else if ((data->board_dat->suspend_sts) ||
836 (data->status == STATUS_EXITING)) {
837 dev_dbg(&data->master->dev,
838 "%s suspend/remove initiated, flushing queue\n",
839 __func__);
840 list_for_each_entry(pmsg, data->queue.next, queue) {
841 pmsg->status = -EIO;
842
843 if (pmsg->complete != 0)
844 pmsg->complete(pmsg->context);
845
846 /* delete from queue */
847 list_del_init(&pmsg->queue);
848 }
849 }
850}
851
852static void pch_spi_set_ir(struct pch_spi_data *data)
853{
854 u32 reg_spcr_val;
855
856 /* enable interrupts */
857 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) {
858 /* set receive threhold to PCH_RX_THOLD */
859 pch_spi_set_threshold(data->current_chip, PCH_RX_THOLD, PCH_RX);
860 /* enable FI and RFI interrupts */
861 pch_spi_enable_interrupts(data->master, PCH_RFI | PCH_FI);
862 } else {
863 /* set receive threhold to maximum */
864 pch_spi_set_threshold(data->current_chip, PCH_RX_THOLD_MAX,
865 PCH_RX);
866 /* enable FI interrupt */
867 pch_spi_enable_interrupts(data->master, PCH_FI);
868 }
869
870 dev_dbg(&data->master->dev,
871 "%s:invoking pch_spi_set_enable to enable SPI\n", __func__);
872
873 /* SPI set enable */
874 reg_spcr_val = pch_spi_readreg(data->current_chip->master, PCH_SPCR);
875 pch_set_bitmsk(&reg_spcr_val, SPCR_SPE_BIT);
876 pch_spi_writereg(data->current_chip->master, PCH_SPCR, reg_spcr_val);
877
878
879 /* Wait until the transfer completes; go to sleep after
880 initiating the transfer. */
881 dev_dbg(&data->master->dev,
882 "%s:waiting for transfer to get over\n", __func__);
883
884 wait_event_interruptible(data->wait, data->transfer_complete);
885
886 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
887 dev_dbg(&data->master->dev,
888 "%s:no more control over SSN-writing 0 to SSNXCR.", __func__);
889
890 data->transfer_active = false;
891 dev_dbg(&data->master->dev,
892 "%s set data->transfer_active = false\n", __func__);
893
894 /* clear all interrupts */
895 pch_spi_writereg(data->master, PCH_SPSR,
896 (pch_spi_readreg(data->master, PCH_SPSR)));
897 /* disable interrupts */
898 pch_spi_disable_interrupts(data->master, PCH_ALL);
899}
900
901static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
902{
903 int j;
904 u8 *rx_buf;
905 u16 *rx_sbuf;
906
907 /* copy Rx Data */
908 if (!(data->cur_trans->rx_buf))
909 return;
910
911 if (bpw == 8) {
912 for (j = 0; j < (data->bpw_len); j++) {
913 rx_buf = data->cur_trans->rx_buf;
914 rx_buf[j] = (data->pkt_rx_buff[j]) & 0xFF;
915 }
916 } else {
917 for (j = 0; j < (data->bpw_len); j++) {
918 rx_sbuf = data->cur_trans->rx_buf;
919 rx_sbuf[j] = data->pkt_rx_buff[j];
920 }
921 }
922}
923
924
925static void pch_spi_process_messages(struct work_struct *pwork)
926{
927 struct spi_message *pmsg;
928 int bpw;
929
930 struct pch_spi_data *data =
931 container_of(pwork, struct pch_spi_data, work);
932 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
933
934 spin_lock(&data->lock);
935
936 /* check if suspend has been initiated;if yes flush queue */
937 if ((data->board_dat->suspend_sts) ||
938 (data->status == STATUS_EXITING)) {
939 dev_dbg(&data->master->dev,
940 "%s suspend/remove initiated,flushing queue\n",
941 __func__);
942 list_for_each_entry(pmsg, data->queue.next, queue) {
943 pmsg->status = -EIO;
944
945 if (pmsg->complete != 0) {
946 spin_unlock(&data->lock);
947 pmsg->complete(pmsg->context);
948 spin_lock(&data->lock);
949 }
950
951 /* delete from queue */
952 list_del_init(&pmsg->queue);
953 }
954
955 spin_unlock(&data->lock);
956 return;
957 }
958
959 data->bcurrent_msg_processing = true;
960 dev_dbg(&data->master->dev,
961 "%s Set data->bcurrent_msg_processing= true\n", __func__);
962
963 /* Get the message from the queue and delete it from there. */
964 data->current_msg =
965 list_entry(data->queue.next, struct spi_message, queue);
966
967 list_del_init(&data->current_msg->queue);
968
969 data->current_msg->status = 0;
970
971 pch_spi_select_chip(data, data->current_msg->spi);
972
973 spin_unlock(&data->lock);
974
975 do {
976 /* If we are already processing a message get the next
977 transfer structure from the message otherwise retrieve
978 the 1st transfer request from the message. */
979 spin_lock(&data->lock);
980
981 if (data->cur_trans == NULL) {
982 data->cur_trans =
983 list_entry(data->current_msg->transfers.
984 next, struct spi_transfer,
985 transfer_list);
986 dev_dbg(&data->master->dev,
987 "%s :Getting 1st transfer message\n", __func__);
988 } else {
989 data->cur_trans =
990 list_entry(data->cur_trans->transfer_list.next,
991 struct spi_transfer,
992 transfer_list);
993 dev_dbg(&data->master->dev,
994 "%s :Getting next transfer message\n",
995 __func__);
996 }
997
998 spin_unlock(&data->lock);
999
1000 pch_spi_set_tx(data, &bpw, &pmsg);
1001
1002 /* Control interrupt*/
1003 pch_spi_set_ir(data);
1004
1005 /* Disable SPI transfer */
1006 pch_spi_setclr_reg(data->current_chip->master, PCH_SPCR, 0,
1007 SPCR_SPE_BIT);
1008
1009 /* clear FIFO */
1010 pch_spi_clear_fifo(data->master);
1011
1012 /* copy Rx Data */
1013 pch_spi_copy_rx_data(data, bpw);
1014
1015 /* free memory */
1016 kfree(data->pkt_rx_buff);
1017 data->pkt_rx_buff = NULL;
1018
1019 kfree(data->pkt_tx_buff);
1020 data->pkt_tx_buff = NULL;
1021
1022 /* increment message count */
1023 data->current_msg->actual_length += data->cur_trans->len;
1024
1025 dev_dbg(&data->master->dev,
1026 "%s:data->current_msg->actual_length=%d\n",
1027 __func__, data->current_msg->actual_length);
1028
1029 /* check for delay */
1030 if (data->cur_trans->delay_usecs) {
1031 dev_dbg(&data->master->dev, "%s:"
1032 "delay in usec=%d\n", __func__,
1033 data->cur_trans->delay_usecs);
1034 udelay(data->cur_trans->delay_usecs);
1035 }
1036
1037 spin_lock(&data->lock);
1038
1039 /* No more transfer in this message. */
1040 if ((data->cur_trans->transfer_list.next) ==
1041 &(data->current_msg->transfers)) {
1042 pch_spi_nomore_transfer(data, pmsg);
1043 }
1044
1045 spin_unlock(&data->lock);
1046
1047 } while ((data->cur_trans) != NULL);
1048}
1049
1050static void pch_spi_free_resources(struct pch_spi_board_data *board_dat)
1051{
1052 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1053
1054 /* free workqueue */
1055 if (board_dat->data->wk != NULL) {
1056 destroy_workqueue(board_dat->data->wk);
1057 board_dat->data->wk = NULL;
1058 dev_dbg(&board_dat->pdev->dev,
1059 "%s destroy_workqueue invoked successfully\n",
1060 __func__);
1061 }
1062
1063 /* disable interrupts & free IRQ */
1064 if (board_dat->irq_reg_sts) {
1065 /* disable interrupts */
1066 pch_spi_disable_interrupts(board_dat->data->
1067 master, PCH_ALL);
1068 dev_dbg(&board_dat->pdev->dev,
1069 "%s pch_spi_disable_interrupts invoked "
1070 "successfully\n", __func__);
1071
1072 /* free IRQ */
1073 free_irq(board_dat->pdev->irq, (void *)board_dat);
1074
1075 dev_dbg(&board_dat->pdev->dev,
1076 "%s free_irq invoked successfully\n", __func__);
1077
1078 board_dat->irq_reg_sts = false;
1079 }
1080
1081 /* unmap PCI base address */
1082 if ((board_dat->data->io_remap_addr) != 0) {
1083 pci_iounmap(board_dat->pdev, board_dat->data->io_remap_addr);
1084
1085 board_dat->data->io_remap_addr = 0;
1086
1087 dev_dbg(&board_dat->pdev->dev,
1088 "%s pci_iounmap invoked successfully\n", __func__);
1089 }
1090
1091 /* release PCI region */
1092 if (board_dat->pci_req_sts) {
1093 pci_release_regions(board_dat->pdev);
1094 dev_dbg(&board_dat->pdev->dev,
1095 "%s pci_release_regions invoked successfully\n",
1096 __func__);
1097 board_dat->pci_req_sts = false;
1098 }
1099}
1100
1101static int pch_spi_get_resources(struct pch_spi_board_data *board_dat)
1102{
1103 void __iomem *io_remap_addr;
1104 int retval;
1105 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1106
1107 /* iniatize queue of pending messages */
1108 INIT_LIST_HEAD(&(board_dat->data->queue));
1109
1110 /* initialize spin locks */
1111 spin_lock_init(&(board_dat->data->lock));
1112
1113 /* set channel status */
1114 board_dat->data->status = STATUS_RUNNING;
1115
1116 /* initialize work structure */
1117 INIT_WORK(&(board_dat->data->work),
1118 pch_spi_process_messages);
1119
1120 /* initialize wait queues */
1121 init_waitqueue_head(&(board_dat->data->wait));
1122
1123 /* create workqueue */
1124 board_dat->data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1125
1126 if ((board_dat->data->wk) == NULL) {
1127 dev_err(&board_dat->pdev->dev,
1128 "%s create_singlet hread_workqueue failed\n", __func__);
1129 retval = -EBUSY;
1130 goto err_return;
1131 }
1132
1133 dev_dbg(&board_dat->pdev->dev,
1134 "%s create_singlethread_workqueue success\n", __func__);
1135
1136 retval = pci_request_regions(board_dat->pdev, KBUILD_MODNAME);
1137 if (retval != 0) {
1138 dev_err(&board_dat->pdev->dev,
1139 "%s request_region failed\n", __func__);
1140 goto err_return;
1141 }
1142
1143 board_dat->pci_req_sts = true;
1144
1145 io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
1146
1147 if (io_remap_addr == 0) {
1148 dev_err(&board_dat->pdev->dev,
1149 "%s pci_iomap failed\n", __func__);
1150 retval = -ENOMEM;
1151 goto err_return;
1152 }
1153
1154 /* calculate base address for all channels */
1155 board_dat->data->io_remap_addr = io_remap_addr;
1156
1157 /* reset PCH SPI h/w */
1158 pch_spi_reset(board_dat->data->master);
1159 dev_dbg(&board_dat->pdev->dev,
1160 "%s pch_spi_reset invoked successfully\n", __func__);
1161
1162 /* register IRQ */
1163 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1164 IRQF_SHARED, KBUILD_MODNAME, (void *)board_dat);
1165 if (retval != 0) {
1166 dev_err(&board_dat->pdev->dev,
1167 "%s request_irq failed\n", __func__);
1168 goto err_return;
1169 }
1170
1171 dev_dbg(&board_dat->pdev->dev, "%s request_irq returned=%d\n",
1172 __func__, retval);
1173
1174 board_dat->irq_reg_sts = true;
1175 dev_dbg(&board_dat->pdev->dev,
1176 "%s data->irq_reg_sts=true\n", __func__);
1177
1178err_return:
1179 if (retval != 0) {
1180 dev_err(&board_dat->pdev->dev,
1181 "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1182 pch_spi_free_resources(board_dat);
1183 }
1184
1185 dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1186
1187 return retval;
1188}
1189
1190static int pch_spi_check_request_pending(struct pch_spi_board_data *board_dat)
1191{
1192 int sts;
1193 u16 count;
1194
1195 count = 500;
1196 spin_lock(&(board_dat->data->lock));
1197 board_dat->data->status = STATUS_EXITING;
1198
1199 while ((list_empty(&(board_dat->data->queue)) == 0) &&
1200 (--count)) {
1201 dev_dbg(&board_dat->pdev->dev,
1202 "%s :queue not empty\n", __func__);
1203 spin_unlock(&(board_dat->data->lock));
1204 msleep(PCH_SLEEP_TIME);
1205 spin_lock(&(board_dat->data->lock));
1206 }
1207
1208 spin_unlock(&(board_dat->data->lock));
1209
1210 if (count) {
1211 sts = 0;
1212 dev_dbg(&board_dat->pdev->dev, "%s :queue empty\n", __func__);
1213 } else {
1214 sts = -EBUSY;
1215 }
1216
1217 dev_dbg(&board_dat->pdev->dev, "%s : EXIT=%d\n", __func__, sts);
1218
1219 return sts;
1220}
1221
1222static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1223{
1224
1225 struct spi_master *master;
1226
1227 struct pch_spi_board_data *board_dat;
1228 int retval;
1229
1230 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1231
1232 /* allocate memory for private data */
1233 board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1234 if (board_dat == NULL) {
1235 dev_err(&pdev->dev,
1236 " %s memory allocation for private data failed\n",
1237 __func__);
1238 retval = -ENOMEM;
1239 goto err_kmalloc;
1240 }
1241
1242 dev_dbg(&pdev->dev,
1243 "%s memory allocation for private data success\n", __func__);
1244
1245 /* enable PCI device */
1246 retval = pci_enable_device(pdev);
1247 if (retval != 0) {
1248 dev_err(&pdev->dev, "%s pci_enable_device FAILED\n", __func__);
1249
1250 goto err_pci_en_device;
1251 }
1252
1253 dev_dbg(&pdev->dev, "%s pci_enable_device returned=%d\n",
1254 __func__, retval);
1255
1256 board_dat->pdev = pdev;
1257
1258 /* alllocate memory for SPI master */
1259 master = spi_alloc_master(&pdev->dev, sizeof(struct pch_spi_data));
1260 if (master == NULL) {
1261 retval = -ENOMEM;
1262 dev_err(&pdev->dev, "%s Fail.\n", __func__);
1263 goto err_spi_alloc_master;
1264 }
1265
1266 dev_dbg(&pdev->dev,
1267 "%s spi_alloc_master returned non NULL\n", __func__);
1268
1269 /* initialize members of SPI master */
1270 master->bus_num = -1;
1271 master->num_chipselect = PCH_MAX_CS;
1272 master->setup = pch_spi_setup;
1273 master->transfer = pch_spi_transfer;
1274 dev_dbg(&pdev->dev,
1275 "%s transfer member of SPI master initialized\n", __func__);
1276
1277 board_dat->data = spi_master_get_devdata(master);
1278
1279 board_dat->data->master = master;
1280 board_dat->data->n_curnt_chip = 255;
1281 board_dat->data->board_dat = board_dat;
1282
1283 /* allocate resources for PCH SPI */
1284 retval = pch_spi_get_resources(board_dat);
1285 if (retval != 0) {
1286 dev_err(&pdev->dev, "%s fail(retval=%d)\n",
1287 __func__, retval);
1288 goto err_spi_get_resources;
1289 }
1290
1291 dev_dbg(&pdev->dev, "%s pch_spi_get_resources returned=%d\n",
1292 __func__, retval);
1293
1294 /* save private data in dev */
1295 pci_set_drvdata(pdev, (void *)board_dat);
1296 dev_dbg(&pdev->dev, "%s invoked pci_set_drvdata\n", __func__);
1297
1298 /* set master mode */
1299 pch_spi_set_master_mode(master);
1300 dev_dbg(&pdev->dev,
1301 "%s invoked pch_spi_set_master_mode\n", __func__);
1302
1303 /* Register the controller with the SPI core. */
1304 retval = spi_register_master(master);
1305 if (retval != 0) {
1306 dev_err(&pdev->dev,
1307 "%s spi_register_master FAILED\n", __func__);
1308 goto err_spi_reg_master;
1309 }
1310
1311 dev_dbg(&pdev->dev, "%s spi_register_master returned=%d\n",
1312 __func__, retval);
1313
1314
1315 return 0;
1316
1317err_spi_reg_master:
1318 spi_unregister_master(master);
1319err_spi_get_resources:
1320err_spi_alloc_master:
1321 spi_master_put(master);
1322 pci_disable_device(pdev);
1323err_pci_en_device:
1324 kfree(board_dat);
1325err_kmalloc:
1326 return retval;
1327}
1328
1329static void pch_spi_remove(struct pci_dev *pdev)
1330{
1331 struct pch_spi_board_data *board_dat = pci_get_drvdata(pdev);
1332
1333 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1334
1335 if (!board_dat) {
1336 dev_err(&pdev->dev,
1337 "%s pci_get_drvdata returned NULL\n", __func__);
1338 return;
1339 }
1340
1341 /* check for any pending messages */
1342 if ((-EBUSY) == pch_spi_check_request_pending(board_dat)) {
1343 dev_dbg(&pdev->dev,
1344 "%s pch_spi_check_request_pending returned"
1345 " EBUSY\n", __func__);
1346 /* no need to take any particular action; proceed with remove
1347 even though queue is not empty */
1348 }
1349
1350 /* Free resources allocated for PCH SPI */
1351 pch_spi_free_resources(board_dat);
1352
1353 /* Unregister SPI master */
1354 spi_unregister_master(board_dat->data->master);
1355
1356 /* free memory for private data */
1357 kfree(board_dat);
1358
1359 pci_set_drvdata(pdev, NULL);
1360
1361 /* disable PCI device */
1362 pci_disable_device(pdev);
1363
1364 dev_dbg(&pdev->dev, "%s invoked pci_disable_device\n", __func__);
1365}
1366
1367#ifdef CONFIG_PM
1368static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1369{
1370 u8 count;
1371 int retval;
1372
1373 struct pch_spi_board_data *board_dat = pci_get_drvdata(pdev);
1374
1375 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1376
1377 if (!board_dat) {
1378 dev_err(&pdev->dev,
1379 "%s pci_get_drvdata returned NULL\n", __func__);
1380 return -EFAULT;
1381 }
1382
1383 retval = 0;
1384 board_dat->suspend_sts = true;
1385
1386 /* check if the current message is processed:
1387 Only after thats done the transfer will be suspended */
1388 count = 255;
1389 while ((--count) > 0) {
1390 if (!(board_dat->data->bcurrent_msg_processing)) {
1391 dev_dbg(&pdev->dev, "%s board_dat->data->bCurrent_"
1392 "msg_processing = false\n", __func__);
1393 break;
1394 } else {
1395 dev_dbg(&pdev->dev, "%s board_dat->data->bCurrent_msg_"
1396 "processing = true\n", __func__);
1397 }
1398 msleep(PCH_SLEEP_TIME);
1399 }
1400
1401 /* Free IRQ */
1402 if (board_dat->irq_reg_sts) {
1403 /* disable all interrupts */
1404 pch_spi_disable_interrupts(board_dat->data->master, PCH_ALL);
1405 pch_spi_reset(board_dat->data->master);
1406 dev_dbg(&pdev->dev,
1407 "%s pch_spi_disable_interrupts invoked successfully\n",
1408 __func__);
1409
1410 free_irq(board_dat->pdev->irq, (void *)board_dat);
1411
1412 board_dat->irq_reg_sts = false;
1413 dev_dbg(&pdev->dev,
1414 "%s free_irq invoked successfully.\n", __func__);
1415 }
1416
1417 /* save config space */
1418 retval = pci_save_state(pdev);
1419
1420 if (retval == 0) {
1421 dev_dbg(&pdev->dev, "%s pci_save_state returned=%d\n",
1422 __func__, retval);
1423 /* disable PM notifications */
1424 pci_enable_wake(pdev, PCI_D3hot, 0);
1425 dev_dbg(&pdev->dev,
1426 "%s pci_enable_wake invoked successfully\n", __func__);
1427 /* disable PCI device */
1428 pci_disable_device(pdev);
1429 dev_dbg(&pdev->dev,
1430 "%s pci_disable_device invoked successfully\n",
1431 __func__);
1432 /* move device to D3hot state */
1433 pci_set_power_state(pdev, PCI_D3hot);
1434 dev_dbg(&pdev->dev,
1435 "%s pci_set_power_state invoked successfully\n",
1436 __func__);
1437 } else {
1438 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1439 }
1440
1441 dev_dbg(&pdev->dev, "%s return=%d\n", __func__, retval);
1442
1443 return retval;
1444}
1445
1446static int pch_spi_resume(struct pci_dev *pdev)
1447{
1448 int retval;
1449
1450 struct pch_spi_board_data *board = pci_get_drvdata(pdev);
1451 dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1452
1453 if (!board) {
1454 dev_err(&pdev->dev,
1455 "%s pci_get_drvdata returned NULL\n", __func__);
1456 return -EFAULT;
1457 }
1458
1459 /* move device to DO power state */
1460 pci_set_power_state(pdev, PCI_D0);
1461
1462 /* restore state */
1463 pci_restore_state(pdev);
1464
1465 retval = pci_enable_device(pdev);
1466 if (retval < 0) {
1467 dev_err(&pdev->dev,
1468 "%s pci_enable_device failed\n", __func__);
1469 } else {
1470 /* disable PM notifications */
1471 pci_enable_wake(pdev, PCI_D3hot, 0);
1472
1473 /* register IRQ handler */
1474 if (!(board->irq_reg_sts)) {
1475 /* register IRQ */
1476 retval = request_irq(board->pdev->irq, pch_spi_handler,
1477 IRQF_SHARED, KBUILD_MODNAME,
1478 board);
1479 if (retval < 0) {
1480 dev_err(&pdev->dev,
1481 "%s request_irq failed\n", __func__);
1482 return retval;
1483 }
1484 board->irq_reg_sts = true;
1485
1486 /* reset PCH SPI h/w */
1487 pch_spi_reset(board->data->master);
1488 pch_spi_set_master_mode(board->data->master);
1489
1490 /* set suspend status to false */
1491 board->suspend_sts = false;
1492
1493 }
1494 }
1495
1496 dev_dbg(&pdev->dev, "%s returning=%d\n", __func__, retval);
1497
1498 return retval;
1499}
1500#else
1501#define pch_spi_suspend NULL
1502#define pch_spi_resume NULL
1503
1504#endif
1505
1506static struct pci_driver pch_spi_pcidev = {
1507 .name = "pch_spi",
1508 .id_table = pch_spi_pcidev_id,
1509 .probe = pch_spi_probe,
1510 .remove = pch_spi_remove,
1511 .suspend = pch_spi_suspend,
1512 .resume = pch_spi_resume,
1513};
1514
1515static int __init pch_spi_init(void)
1516{
1517 return pci_register_driver(&pch_spi_pcidev);
1518}
1519module_init(pch_spi_init);
1520
1521
1522static void __exit pch_spi_exit(void)
1523{
1524 pci_unregister_driver(&pch_spi_pcidev);
1525}
1526module_exit(pch_spi_exit);
1527
1528MODULE_LICENSE("GPL");
1529MODULE_DESCRIPTION("PCH SPI PCI Driver");
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-25 20:58:13 -0500