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-rw-r--r--arch/sparc64/kernel/entry.S17
-rw-r--r--arch/sparc64/kernel/irq.c20
-rw-r--r--arch/sparc64/kernel/process.c2
-rw-r--r--arch/sparc64/kernel/smp.c2
-rw-r--r--arch/sparc64/kernel/traps.c2
-rw-r--r--drivers/sbus/char/Kconfig14
-rw-r--r--drivers/sbus/char/aurora.c6
-rw-r--r--drivers/sbus/char/bbc_envctrl.c3
-rw-r--r--drivers/sbus/char/envctrl.c10
-rw-r--r--drivers/sbus/char/vfc_i2c.c8
-rw-r--r--include/asm-sparc64/bitops.h56
-rw-r--r--include/asm-sparc64/ptrace.h5
-rw-r--r--include/asm-sparc64/rwsem.h48
-rw-r--r--include/asm-sparc64/spitfire.h130
-rw-r--r--include/asm-sparc64/system.h11
-rw-r--r--include/asm-sparc64/thread_info.h12
-rw-r--r--include/asm-sparc64/timer.h41
17 files changed, 79 insertions, 308 deletions
diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index d781f10adc52..88332f00094a 100644
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -1600,11 +1600,11 @@ sys_clone: flushw
1600 ba,pt %xcc, sparc_do_fork 1600 ba,pt %xcc, sparc_do_fork
1601 add %sp, PTREGS_OFF, %o2 1601 add %sp, PTREGS_OFF, %o2
1602ret_from_syscall: 1602ret_from_syscall:
1603 /* Clear SPARC_FLAG_NEWCHILD, switch_to leaves thread.flags in 1603 /* Clear current_thread_info()->new_child, and
1604 * %o7 for us. Check performance counter stuff too. 1604 * check performance counter stuff too.
1605 */ 1605 */
1606 andn %o7, _TIF_NEWCHILD, %l0 1606 stb %g0, [%g6 + TI_NEW_CHILD]
1607 stx %l0, [%g6 + TI_FLAGS] 1607 ldx [%g6 + TI_FLAGS], %l0
1608 call schedule_tail 1608 call schedule_tail
1609 mov %g7, %o0 1609 mov %g7, %o0
1610 andcc %l0, _TIF_PERFCTR, %g0 1610 andcc %l0, _TIF_PERFCTR, %g0
@@ -1720,12 +1720,11 @@ ret_sys_call:
1720 /* Check if force_successful_syscall_return() 1720 /* Check if force_successful_syscall_return()
1721 * was invoked. 1721 * was invoked.
1722 */ 1722 */
1723 ldx [%curptr + TI_FLAGS], %l0 1723 ldub [%curptr + TI_SYS_NOERROR], %l0
1724 andcc %l0, _TIF_SYSCALL_SUCCESS, %g0 1724 brz,pt %l0, 1f
1725 be,pt %icc, 1f 1725 nop
1726 andn %l0, _TIF_SYSCALL_SUCCESS, %l0
1727 ba,pt %xcc, 80f 1726 ba,pt %xcc, 80f
1728 stx %l0, [%curptr + TI_FLAGS] 1727 stb %g0, [%curptr + TI_SYS_NOERROR]
1729 1728
17301: 17291:
1731 cmp %o0, -ERESTART_RESTARTBLOCK 1730 cmp %o0, -ERESTART_RESTARTBLOCK
diff --git a/arch/sparc64/kernel/irq.c b/arch/sparc64/kernel/irq.c
index daa2fb93052c..c9b69167632a 100644
--- a/arch/sparc64/kernel/irq.c
+++ b/arch/sparc64/kernel/irq.c
@@ -782,8 +782,14 @@ static void distribute_irqs(void)
782} 782}
783#endif 783#endif
784 784
785struct sun5_timer {
786 u64 count0;
787 u64 limit0;
788 u64 count1;
789 u64 limit1;
790};
785 791
786struct sun5_timer *prom_timers; 792static struct sun5_timer *prom_timers;
787static u64 prom_limit0, prom_limit1; 793static u64 prom_limit0, prom_limit1;
788 794
789static void map_prom_timers(void) 795static void map_prom_timers(void)
@@ -839,18 +845,6 @@ static void kill_prom_timer(void)
839 : "g1", "g2"); 845 : "g1", "g2");
840} 846}
841 847
842void enable_prom_timer(void)
843{
844 if (!prom_timers)
845 return;
846
847 /* Set it to whatever was there before. */
848 prom_timers->limit1 = prom_limit1;
849 prom_timers->count1 = 0;
850 prom_timers->limit0 = prom_limit0;
851 prom_timers->count0 = 0;
852}
853
854void init_irqwork_curcpu(void) 848void init_irqwork_curcpu(void)
855{ 849{
856 register struct irq_work_struct *workp asm("o2"); 850 register struct irq_work_struct *workp asm("o2");
diff --git a/arch/sparc64/kernel/process.c b/arch/sparc64/kernel/process.c
index a0cd2b2494d6..cffb1c8ab4fc 100644
--- a/arch/sparc64/kernel/process.c
+++ b/arch/sparc64/kernel/process.c
@@ -621,8 +621,8 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long sp,
621 memcpy(child_trap_frame, (((struct sparc_stackf *)regs)-1), (TRACEREG_SZ+STACKFRAME_SZ)); 621 memcpy(child_trap_frame, (((struct sparc_stackf *)regs)-1), (TRACEREG_SZ+STACKFRAME_SZ));
622 622
623 t->flags = (t->flags & ~((0xffUL << TI_FLAG_CWP_SHIFT) | (0xffUL << TI_FLAG_CURRENT_DS_SHIFT))) | 623 t->flags = (t->flags & ~((0xffUL << TI_FLAG_CWP_SHIFT) | (0xffUL << TI_FLAG_CURRENT_DS_SHIFT))) |
624 _TIF_NEWCHILD |
625 (((regs->tstate + 1) & TSTATE_CWP) << TI_FLAG_CWP_SHIFT); 624 (((regs->tstate + 1) & TSTATE_CWP) << TI_FLAG_CWP_SHIFT);
625 t->new_child = 1;
626 t->ksp = ((unsigned long) child_trap_frame) - STACK_BIAS; 626 t->ksp = ((unsigned long) child_trap_frame) - STACK_BIAS;
627 t->kregs = (struct pt_regs *)(child_trap_frame+sizeof(struct sparc_stackf)); 627 t->kregs = (struct pt_regs *)(child_trap_frame+sizeof(struct sparc_stackf));
628 t->fpsaved[0] = 0; 628 t->fpsaved[0] = 0;
diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index 7e8e2919e186..b9b42491e118 100644
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -137,7 +137,7 @@ void __init smp_callin(void)
137 /* Clear this or we will die instantly when we 137 /* Clear this or we will die instantly when we
138 * schedule back to this idler... 138 * schedule back to this idler...
139 */ 139 */
140 clear_thread_flag(TIF_NEWCHILD); 140 current_thread_info()->new_child = 0;
141 141
142 /* Attach to the address space of init_task. */ 142 /* Attach to the address space of init_task. */
143 atomic_inc(&init_mm.mm_count); 143 atomic_inc(&init_mm.mm_count);
diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c
index a9f4596d7c2b..100b0107c4be 100644
--- a/arch/sparc64/kernel/traps.c
+++ b/arch/sparc64/kernel/traps.c
@@ -2125,6 +2125,8 @@ void __init trap_init(void)
2125 TI_PCR != offsetof(struct thread_info, pcr_reg) || 2125 TI_PCR != offsetof(struct thread_info, pcr_reg) ||
2126 TI_CEE_STUFF != offsetof(struct thread_info, cee_stuff) || 2126 TI_CEE_STUFF != offsetof(struct thread_info, cee_stuff) ||
2127 TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) || 2127 TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
2128 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2129 TI_SYS_NOERROR != offsetof(struct thread_info, syscall_noerror) ||
2128 TI_FPREGS != offsetof(struct thread_info, fpregs) || 2130 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2129 (TI_FPREGS & (64 - 1))) 2131 (TI_FPREGS & (64 - 1)))
2130 thread_info_offsets_are_bolixed_dave(); 2132 thread_info_offsets_are_bolixed_dave();
diff --git a/drivers/sbus/char/Kconfig b/drivers/sbus/char/Kconfig
index 90d8ef1f0bcc..a41778a490d6 100644
--- a/drivers/sbus/char/Kconfig
+++ b/drivers/sbus/char/Kconfig
@@ -71,20 +71,6 @@ config SUN_JSFLASH
71 71
72# XXX Why don't we do "source drivers/char/Config.in" somewhere? 72# XXX Why don't we do "source drivers/char/Config.in" somewhere?
73# no shit 73# no shit
74config APM_RTC_IS_GMT
75 bool
76 depends on EXPERIMENTAL && SPARC32 && PCI
77 default y
78 help
79 Say Y here if your RTC (Real Time Clock a.k.a. hardware clock)
80 stores the time in GMT (Greenwich Mean Time). Say N if your RTC
81 stores localtime.
82
83 It is in fact recommended to store GMT in your RTC, because then you
84 don't have to worry about daylight savings time changes. The only
85 reason not to use GMT in your RTC is if you also run a broken OS
86 that doesn't understand GMT.
87
88config RTC 74config RTC
89 tristate "PC-style Real Time Clock Support" 75 tristate "PC-style Real Time Clock Support"
90 depends on PCI && EXPERIMENTAL && SPARC32 76 depends on PCI && EXPERIMENTAL && SPARC32
diff --git a/drivers/sbus/char/aurora.c b/drivers/sbus/char/aurora.c
index 650d5e924f47..d96cc47de566 100644
--- a/drivers/sbus/char/aurora.c
+++ b/drivers/sbus/char/aurora.c
@@ -1515,8 +1515,7 @@ static void aurora_close(struct tty_struct * tty, struct file * filp)
1515 */ 1515 */
1516 timeout = jiffies+HZ; 1516 timeout = jiffies+HZ;
1517 while(port->SRER & SRER_TXEMPTY) { 1517 while(port->SRER & SRER_TXEMPTY) {
1518 current->state = TASK_INTERRUPTIBLE; 1518 msleep_interruptible(jiffies_to_msecs(port->timeout));
1519 schedule_timeout(port->timeout);
1520 if (time_after(jiffies, timeout)) 1519 if (time_after(jiffies, timeout))
1521 break; 1520 break;
1522 } 1521 }
@@ -1533,8 +1532,7 @@ static void aurora_close(struct tty_struct * tty, struct file * filp)
1533 port->tty = 0; 1532 port->tty = 0;
1534 if (port->blocked_open) { 1533 if (port->blocked_open) {
1535 if (port->close_delay) { 1534 if (port->close_delay) {
1536 current->state = TASK_INTERRUPTIBLE; 1535 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1537 schedule_timeout(port->close_delay);
1538 } 1536 }
1539 wake_up_interruptible(&port->open_wait); 1537 wake_up_interruptible(&port->open_wait);
1540 } 1538 }
diff --git a/drivers/sbus/char/bbc_envctrl.c b/drivers/sbus/char/bbc_envctrl.c
index d5259f7fee6d..b8a2c7353b0a 100644
--- a/drivers/sbus/char/bbc_envctrl.c
+++ b/drivers/sbus/char/bbc_envctrl.c
@@ -4,13 +4,14 @@
4 * Copyright (C) 2001 David S. Miller (davem@redhat.com) 4 * Copyright (C) 2001 David S. Miller (davem@redhat.com)
5 */ 5 */
6 6
7#define __KERNEL_SYSCALLS__
8
7#include <linux/kernel.h> 9#include <linux/kernel.h>
8#include <linux/sched.h> 10#include <linux/sched.h>
9#include <linux/slab.h> 11#include <linux/slab.h>
10#include <linux/delay.h> 12#include <linux/delay.h>
11#include <asm/oplib.h> 13#include <asm/oplib.h>
12#include <asm/ebus.h> 14#include <asm/ebus.h>
13#define __KERNEL_SYSCALLS__
14static int errno; 15static int errno;
15#include <asm/unistd.h> 16#include <asm/unistd.h>
16 17
diff --git a/drivers/sbus/char/envctrl.c b/drivers/sbus/char/envctrl.c
index f6ed35b24f43..9a8c572554f5 100644
--- a/drivers/sbus/char/envctrl.c
+++ b/drivers/sbus/char/envctrl.c
@@ -19,6 +19,8 @@
19 * Daniele Bellucci <bellucda@tiscali.it> 19 * Daniele Bellucci <bellucda@tiscali.it>
20 */ 20 */
21 21
22#define __KERNEL_SYSCALLS__
23
22#include <linux/config.h> 24#include <linux/config.h>
23#include <linux/module.h> 25#include <linux/module.h>
24#include <linux/sched.h> 26#include <linux/sched.h>
@@ -35,7 +37,6 @@
35#include <asm/uaccess.h> 37#include <asm/uaccess.h>
36#include <asm/envctrl.h> 38#include <asm/envctrl.h>
37 39
38#define __KERNEL_SYSCALLS__
39static int errno; 40static int errno;
40#include <asm/unistd.h> 41#include <asm/unistd.h>
41 42
@@ -1007,7 +1008,7 @@ static int kenvctrld(void *__unused)
1007 return -ENODEV; 1008 return -ENODEV;
1008 } 1009 }
1009 1010
1010 poll_interval = 5 * HZ; /* TODO env_mon_interval */ 1011 poll_interval = 5000; /* TODO env_mon_interval */
1011 1012
1012 daemonize("kenvctrld"); 1013 daemonize("kenvctrld");
1013 allow_signal(SIGKILL); 1014 allow_signal(SIGKILL);
@@ -1016,10 +1017,7 @@ static int kenvctrld(void *__unused)
1016 1017
1017 printk(KERN_INFO "envctrl: %s starting...\n", current->comm); 1018 printk(KERN_INFO "envctrl: %s starting...\n", current->comm);
1018 for (;;) { 1019 for (;;) {
1019 current->state = TASK_INTERRUPTIBLE; 1020 if(msleep_interruptible(poll_interval))
1020 schedule_timeout(poll_interval);
1021
1022 if(signal_pending(current))
1023 break; 1021 break;
1024 1022
1025 for (whichcpu = 0; whichcpu < ENVCTRL_MAX_CPU; ++whichcpu) { 1023 for (whichcpu = 0; whichcpu < ENVCTRL_MAX_CPU; ++whichcpu) {
diff --git a/drivers/sbus/char/vfc_i2c.c b/drivers/sbus/char/vfc_i2c.c
index 95e3cebf792c..1faf1e75f71f 100644
--- a/drivers/sbus/char/vfc_i2c.c
+++ b/drivers/sbus/char/vfc_i2c.c
@@ -88,14 +88,16 @@ void vfc_i2c_delay_wakeup(struct vfc_dev *dev)
88 88
89void vfc_i2c_delay_no_busy(struct vfc_dev *dev, unsigned long usecs) 89void vfc_i2c_delay_no_busy(struct vfc_dev *dev, unsigned long usecs)
90{ 90{
91 DEFINE_WAIT(wait);
91 init_timer(&dev->poll_timer); 92 init_timer(&dev->poll_timer);
92 dev->poll_timer.expires = jiffies + 93 dev->poll_timer.expires = jiffies + usecs_to_jiffies(usecs);
93 ((unsigned long)usecs*(HZ))/1000000;
94 dev->poll_timer.data=(unsigned long)dev; 94 dev->poll_timer.data=(unsigned long)dev;
95 dev->poll_timer.function=(void *)(unsigned long)vfc_i2c_delay_wakeup; 95 dev->poll_timer.function=(void *)(unsigned long)vfc_i2c_delay_wakeup;
96 add_timer(&dev->poll_timer); 96 add_timer(&dev->poll_timer);
97 sleep_on(&dev->poll_wait); 97 prepare_to_wait(&dev->poll_wait, &wait, TASK_UNINTERRUPTIBLE);
98 schedule();
98 del_timer(&dev->poll_timer); 99 del_timer(&dev->poll_timer);
100 finish_wait(&dev->poll_wait, &wait);
99} 101}
100 102
101void inline vfc_i2c_delay(struct vfc_dev *dev) 103void inline vfc_i2c_delay(struct vfc_dev *dev)
diff --git a/include/asm-sparc64/bitops.h b/include/asm-sparc64/bitops.h
index 9d722dc8cca3..9c5e71970287 100644
--- a/include/asm-sparc64/bitops.h
+++ b/include/asm-sparc64/bitops.h
@@ -20,52 +20,52 @@ extern void change_bit(unsigned long nr, volatile unsigned long *addr);
20 20
21/* "non-atomic" versions... */ 21/* "non-atomic" versions... */
22 22
23static __inline__ void __set_bit(int nr, volatile unsigned long *addr) 23static inline void __set_bit(int nr, volatile unsigned long *addr)
24{ 24{
25 volatile unsigned long *m = addr + (nr >> 6); 25 unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
26 26
27 *m |= (1UL << (nr & 63)); 27 *m |= (1UL << (nr & 63));
28} 28}
29 29
30static __inline__ void __clear_bit(int nr, volatile unsigned long *addr) 30static inline void __clear_bit(int nr, volatile unsigned long *addr)
31{ 31{
32 volatile unsigned long *m = addr + (nr >> 6); 32 unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
33 33
34 *m &= ~(1UL << (nr & 63)); 34 *m &= ~(1UL << (nr & 63));
35} 35}
36 36
37static __inline__ void __change_bit(int nr, volatile unsigned long *addr) 37static inline void __change_bit(int nr, volatile unsigned long *addr)
38{ 38{
39 volatile unsigned long *m = addr + (nr >> 6); 39 unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
40 40
41 *m ^= (1UL << (nr & 63)); 41 *m ^= (1UL << (nr & 63));
42} 42}
43 43
44static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr) 44static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
45{ 45{
46 volatile unsigned long *m = addr + (nr >> 6); 46 unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
47 long old = *m; 47 unsigned long old = *m;
48 long mask = (1UL << (nr & 63)); 48 unsigned long mask = (1UL << (nr & 63));
49 49
50 *m = (old | mask); 50 *m = (old | mask);
51 return ((old & mask) != 0); 51 return ((old & mask) != 0);
52} 52}
53 53
54static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr) 54static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
55{ 55{
56 volatile unsigned long *m = addr + (nr >> 6); 56 unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
57 long old = *m; 57 unsigned long old = *m;
58 long mask = (1UL << (nr & 63)); 58 unsigned long mask = (1UL << (nr & 63));
59 59
60 *m = (old & ~mask); 60 *m = (old & ~mask);
61 return ((old & mask) != 0); 61 return ((old & mask) != 0);
62} 62}
63 63
64static __inline__ int __test_and_change_bit(int nr, volatile unsigned long *addr) 64static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
65{ 65{
66 volatile unsigned long *m = addr + (nr >> 6); 66 unsigned long *m = ((unsigned long *)addr) + (nr >> 6);
67 long old = *m; 67 unsigned long old = *m;
68 long mask = (1UL << (nr & 63)); 68 unsigned long mask = (1UL << (nr & 63));
69 69
70 *m = (old ^ mask); 70 *m = (old ^ mask);
71 return ((old & mask) != 0); 71 return ((old & mask) != 0);
@@ -79,13 +79,13 @@ static __inline__ int __test_and_change_bit(int nr, volatile unsigned long *addr
79#define smp_mb__after_clear_bit() barrier() 79#define smp_mb__after_clear_bit() barrier()
80#endif 80#endif
81 81
82static __inline__ int test_bit(int nr, __const__ volatile unsigned long *addr) 82static inline int test_bit(int nr, __const__ volatile unsigned long *addr)
83{ 83{
84 return (1UL & ((addr)[nr >> 6] >> (nr & 63))) != 0UL; 84 return (1UL & (addr[nr >> 6] >> (nr & 63))) != 0UL;
85} 85}
86 86
87/* The easy/cheese version for now. */ 87/* The easy/cheese version for now. */
88static __inline__ unsigned long ffz(unsigned long word) 88static inline unsigned long ffz(unsigned long word)
89{ 89{
90 unsigned long result; 90 unsigned long result;
91 91
@@ -103,7 +103,7 @@ static __inline__ unsigned long ffz(unsigned long word)
103 * 103 *
104 * Undefined if no bit exists, so code should check against 0 first. 104 * Undefined if no bit exists, so code should check against 0 first.
105 */ 105 */
106static __inline__ unsigned long __ffs(unsigned long word) 106static inline unsigned long __ffs(unsigned long word)
107{ 107{
108 unsigned long result = 0; 108 unsigned long result = 0;
109 109
@@ -144,7 +144,7 @@ static inline int sched_find_first_bit(unsigned long *b)
144 * the libc and compiler builtin ffs routines, therefore 144 * the libc and compiler builtin ffs routines, therefore
145 * differs in spirit from the above ffz (man ffs). 145 * differs in spirit from the above ffz (man ffs).
146 */ 146 */
147static __inline__ int ffs(int x) 147static inline int ffs(int x)
148{ 148{
149 if (!x) 149 if (!x)
150 return 0; 150 return 0;
@@ -158,7 +158,7 @@ static __inline__ int ffs(int x)
158 158
159#ifdef ULTRA_HAS_POPULATION_COUNT 159#ifdef ULTRA_HAS_POPULATION_COUNT
160 160
161static __inline__ unsigned int hweight64(unsigned long w) 161static inline unsigned int hweight64(unsigned long w)
162{ 162{
163 unsigned int res; 163 unsigned int res;
164 164
@@ -166,7 +166,7 @@ static __inline__ unsigned int hweight64(unsigned long w)
166 return res; 166 return res;
167} 167}
168 168
169static __inline__ unsigned int hweight32(unsigned int w) 169static inline unsigned int hweight32(unsigned int w)
170{ 170{
171 unsigned int res; 171 unsigned int res;
172 172
@@ -174,7 +174,7 @@ static __inline__ unsigned int hweight32(unsigned int w)
174 return res; 174 return res;
175} 175}
176 176
177static __inline__ unsigned int hweight16(unsigned int w) 177static inline unsigned int hweight16(unsigned int w)
178{ 178{
179 unsigned int res; 179 unsigned int res;
180 180
@@ -182,7 +182,7 @@ static __inline__ unsigned int hweight16(unsigned int w)
182 return res; 182 return res;
183} 183}
184 184
185static __inline__ unsigned int hweight8(unsigned int w) 185static inline unsigned int hweight8(unsigned int w)
186{ 186{
187 unsigned int res; 187 unsigned int res;
188 188
@@ -236,7 +236,7 @@ extern unsigned long find_next_zero_bit(const unsigned long *,
236#define test_and_clear_le_bit(nr,addr) \ 236#define test_and_clear_le_bit(nr,addr) \
237 test_and_clear_bit((nr) ^ 0x38, (addr)) 237 test_and_clear_bit((nr) ^ 0x38, (addr))
238 238
239static __inline__ int test_le_bit(int nr, __const__ unsigned long * addr) 239static inline int test_le_bit(int nr, __const__ unsigned long * addr)
240{ 240{
241 int mask; 241 int mask;
242 __const__ unsigned char *ADDR = (__const__ unsigned char *) addr; 242 __const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
diff --git a/include/asm-sparc64/ptrace.h b/include/asm-sparc64/ptrace.h
index 2d2b5a113d24..6194f771e9fc 100644
--- a/include/asm-sparc64/ptrace.h
+++ b/include/asm-sparc64/ptrace.h
@@ -94,8 +94,9 @@ struct sparc_trapf {
94#define STACKFRAME32_SZ sizeof(struct sparc_stackf32) 94#define STACKFRAME32_SZ sizeof(struct sparc_stackf32)
95 95
96#ifdef __KERNEL__ 96#ifdef __KERNEL__
97#define force_successful_syscall_return() \ 97#define force_successful_syscall_return() \
98 set_thread_flag(TIF_SYSCALL_SUCCESS) 98do { current_thread_info()->syscall_noerror = 1; \
99} while (0)
99#define user_mode(regs) (!((regs)->tstate & TSTATE_PRIV)) 100#define user_mode(regs) (!((regs)->tstate & TSTATE_PRIV))
100#define instruction_pointer(regs) ((regs)->tpc) 101#define instruction_pointer(regs) ((regs)->tpc)
101#ifdef CONFIG_SMP 102#ifdef CONFIG_SMP
diff --git a/include/asm-sparc64/rwsem.h b/include/asm-sparc64/rwsem.h
index a1cc94f95984..4568ee4022df 100644
--- a/include/asm-sparc64/rwsem.h
+++ b/include/asm-sparc64/rwsem.h
@@ -46,54 +46,14 @@ extern void __up_read(struct rw_semaphore *sem);
46extern void __up_write(struct rw_semaphore *sem); 46extern void __up_write(struct rw_semaphore *sem);
47extern void __downgrade_write(struct rw_semaphore *sem); 47extern void __downgrade_write(struct rw_semaphore *sem);
48 48
49static __inline__ int rwsem_atomic_update(int delta, struct rw_semaphore *sem) 49static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
50{ 50{
51 int tmp = delta; 51 return atomic_add_return(delta, (atomic_t *)(&sem->count));
52
53 __asm__ __volatile__(
54 "1:\tlduw [%2], %%g1\n\t"
55 "add %%g1, %1, %%g7\n\t"
56 "cas [%2], %%g1, %%g7\n\t"
57 "cmp %%g1, %%g7\n\t"
58 "membar #StoreLoad | #StoreStore\n\t"
59 "bne,pn %%icc, 1b\n\t"
60 " nop\n\t"
61 "mov %%g7, %0\n\t"
62 : "=&r" (tmp)
63 : "0" (tmp), "r" (sem)
64 : "g1", "g7", "memory", "cc");
65
66 return tmp + delta;
67}
68
69#define rwsem_atomic_add rwsem_atomic_update
70
71static __inline__ __u16 rwsem_cmpxchgw(struct rw_semaphore *sem, __u16 __old, __u16 __new)
72{
73 u32 old = (sem->count & 0xffff0000) | (u32) __old;
74 u32 new = (old & 0xffff0000) | (u32) __new;
75 u32 prev;
76
77again:
78 __asm__ __volatile__("cas [%2], %3, %0\n\t"
79 "membar #StoreLoad | #StoreStore"
80 : "=&r" (prev)
81 : "0" (new), "r" (sem), "r" (old)
82 : "memory");
83
84 /* To give the same semantics as x86 cmpxchgw, keep trying
85 * if only the upper 16-bits changed.
86 */
87 if (prev != old &&
88 ((prev & 0xffff) == (old & 0xffff)))
89 goto again;
90
91 return prev & 0xffff;
92} 52}
93 53
94static __inline__ signed long rwsem_cmpxchg(struct rw_semaphore *sem, signed long old, signed long new) 54static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
95{ 55{
96 return cmpxchg(&sem->count,old,new); 56 atomic_add(delta, (atomic_t *)(&sem->count));
97} 57}
98 58
99#endif /* __KERNEL__ */ 59#endif /* __KERNEL__ */
diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h
index 1aa932773af8..962638c9d122 100644
--- a/include/asm-sparc64/spitfire.h
+++ b/include/asm-sparc64/spitfire.h
@@ -56,52 +56,6 @@ extern void cheetah_enable_pcache(void);
56 SPITFIRE_HIGHEST_LOCKED_TLBENT : \ 56 SPITFIRE_HIGHEST_LOCKED_TLBENT : \
57 CHEETAH_HIGHEST_LOCKED_TLBENT) 57 CHEETAH_HIGHEST_LOCKED_TLBENT)
58 58
59static __inline__ unsigned long spitfire_get_isfsr(void)
60{
61 unsigned long ret;
62
63 __asm__ __volatile__("ldxa [%1] %2, %0"
64 : "=r" (ret)
65 : "r" (TLB_SFSR), "i" (ASI_IMMU));
66 return ret;
67}
68
69static __inline__ unsigned long spitfire_get_dsfsr(void)
70{
71 unsigned long ret;
72
73 __asm__ __volatile__("ldxa [%1] %2, %0"
74 : "=r" (ret)
75 : "r" (TLB_SFSR), "i" (ASI_DMMU));
76 return ret;
77}
78
79static __inline__ unsigned long spitfire_get_sfar(void)
80{
81 unsigned long ret;
82
83 __asm__ __volatile__("ldxa [%1] %2, %0"
84 : "=r" (ret)
85 : "r" (DMMU_SFAR), "i" (ASI_DMMU));
86 return ret;
87}
88
89static __inline__ void spitfire_put_isfsr(unsigned long sfsr)
90{
91 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
92 "membar #Sync"
93 : /* no outputs */
94 : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_IMMU));
95}
96
97static __inline__ void spitfire_put_dsfsr(unsigned long sfsr)
98{
99 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
100 "membar #Sync"
101 : /* no outputs */
102 : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_DMMU));
103}
104
105/* The data cache is write through, so this just invalidates the 59/* The data cache is write through, so this just invalidates the
106 * specified line. 60 * specified line.
107 */ 61 */
@@ -193,90 +147,6 @@ static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
193 "i" (ASI_ITLB_DATA_ACCESS)); 147 "i" (ASI_ITLB_DATA_ACCESS));
194} 148}
195 149
196/* Spitfire hardware assisted TLB flushes. */
197
198/* Context level flushes. */
199static __inline__ void spitfire_flush_dtlb_primary_context(void)
200{
201 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
202 "membar #Sync"
203 : /* No outputs */
204 : "r" (0x40), "i" (ASI_DMMU_DEMAP));
205}
206
207static __inline__ void spitfire_flush_itlb_primary_context(void)
208{
209 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
210 "membar #Sync"
211 : /* No outputs */
212 : "r" (0x40), "i" (ASI_IMMU_DEMAP));
213}
214
215static __inline__ void spitfire_flush_dtlb_secondary_context(void)
216{
217 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
218 "membar #Sync"
219 : /* No outputs */
220 : "r" (0x50), "i" (ASI_DMMU_DEMAP));
221}
222
223static __inline__ void spitfire_flush_itlb_secondary_context(void)
224{
225 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
226 "membar #Sync"
227 : /* No outputs */
228 : "r" (0x50), "i" (ASI_IMMU_DEMAP));
229}
230
231static __inline__ void spitfire_flush_dtlb_nucleus_context(void)
232{
233 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
234 "membar #Sync"
235 : /* No outputs */
236 : "r" (0x60), "i" (ASI_DMMU_DEMAP));
237}
238
239static __inline__ void spitfire_flush_itlb_nucleus_context(void)
240{
241 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
242 "membar #Sync"
243 : /* No outputs */
244 : "r" (0x60), "i" (ASI_IMMU_DEMAP));
245}
246
247/* Page level flushes. */
248static __inline__ void spitfire_flush_dtlb_primary_page(unsigned long page)
249{
250 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
251 "membar #Sync"
252 : /* No outputs */
253 : "r" (page), "i" (ASI_DMMU_DEMAP));
254}
255
256static __inline__ void spitfire_flush_itlb_primary_page(unsigned long page)
257{
258 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
259 "membar #Sync"
260 : /* No outputs */
261 : "r" (page), "i" (ASI_IMMU_DEMAP));
262}
263
264static __inline__ void spitfire_flush_dtlb_secondary_page(unsigned long page)
265{
266 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
267 "membar #Sync"
268 : /* No outputs */
269 : "r" (page | 0x10), "i" (ASI_DMMU_DEMAP));
270}
271
272static __inline__ void spitfire_flush_itlb_secondary_page(unsigned long page)
273{
274 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
275 "membar #Sync"
276 : /* No outputs */
277 : "r" (page | 0x10), "i" (ASI_IMMU_DEMAP));
278}
279
280static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page) 150static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
281{ 151{
282 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" 152 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index f9be2c5b4dc9..ee4bdfc6b88f 100644
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -190,24 +190,23 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \
190 "wrpr %%g1, %%cwp\n\t" \ 190 "wrpr %%g1, %%cwp\n\t" \
191 "ldx [%%g6 + %3], %%o6\n\t" \ 191 "ldx [%%g6 + %3], %%o6\n\t" \
192 "ldub [%%g6 + %2], %%o5\n\t" \ 192 "ldub [%%g6 + %2], %%o5\n\t" \
193 "ldx [%%g6 + %4], %%o7\n\t" \ 193 "ldub [%%g6 + %4], %%o7\n\t" \
194 "mov %%g6, %%l2\n\t" \ 194 "mov %%g6, %%l2\n\t" \
195 "wrpr %%o5, 0x0, %%wstate\n\t" \ 195 "wrpr %%o5, 0x0, %%wstate\n\t" \
196 "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \ 196 "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
197 "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \ 197 "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
198 "wrpr %%g0, 0x94, %%pstate\n\t" \ 198 "wrpr %%g0, 0x94, %%pstate\n\t" \
199 "mov %%l2, %%g6\n\t" \ 199 "mov %%l2, %%g6\n\t" \
200 "ldx [%%g6 + %7], %%g4\n\t" \ 200 "ldx [%%g6 + %6], %%g4\n\t" \
201 "wrpr %%g0, 0x96, %%pstate\n\t" \ 201 "wrpr %%g0, 0x96, %%pstate\n\t" \
202 "andcc %%o7, %6, %%g0\n\t" \ 202 "brz,pt %%o7, 1f\n\t" \
203 "beq,pt %%icc, 1f\n\t" \
204 " mov %%g7, %0\n\t" \ 203 " mov %%g7, %0\n\t" \
205 "b,a ret_from_syscall\n\t" \ 204 "b,a ret_from_syscall\n\t" \
206 "1:\n\t" \ 205 "1:\n\t" \
207 : "=&r" (last) \ 206 : "=&r" (last) \
208 : "0" (next->thread_info), \ 207 : "0" (next->thread_info), \
209 "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_FLAGS), "i" (TI_CWP), \ 208 "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \
210 "i" (_TIF_NEWCHILD), "i" (TI_TASK) \ 209 "i" (TI_CWP), "i" (TI_TASK) \
211 : "cc", \ 210 : "cc", \
212 "g1", "g2", "g3", "g7", \ 211 "g1", "g2", "g3", "g7", \
213 "l2", "l3", "l4", "l5", "l6", "l7", \ 212 "l2", "l3", "l4", "l5", "l6", "l7", \
diff --git a/include/asm-sparc64/thread_info.h b/include/asm-sparc64/thread_info.h
index a1d25c06f92a..352d9943661a 100644
--- a/include/asm-sparc64/thread_info.h
+++ b/include/asm-sparc64/thread_info.h
@@ -47,7 +47,9 @@ struct thread_info {
47 struct pt_regs *kregs; 47 struct pt_regs *kregs;
48 struct exec_domain *exec_domain; 48 struct exec_domain *exec_domain;
49 int preempt_count; /* 0 => preemptable, <0 => BUG */ 49 int preempt_count; /* 0 => preemptable, <0 => BUG */
50 int __pad; 50 __u8 new_child;
51 __u8 syscall_noerror;
52 __u16 __pad;
51 53
52 unsigned long *utraps; 54 unsigned long *utraps;
53 55
@@ -87,6 +89,8 @@ struct thread_info {
87#define TI_KREGS 0x00000028 89#define TI_KREGS 0x00000028
88#define TI_EXEC_DOMAIN 0x00000030 90#define TI_EXEC_DOMAIN 0x00000030
89#define TI_PRE_COUNT 0x00000038 91#define TI_PRE_COUNT 0x00000038
92#define TI_NEW_CHILD 0x0000003c
93#define TI_SYS_NOERROR 0x0000003d
90#define TI_UTRAPS 0x00000040 94#define TI_UTRAPS 0x00000040
91#define TI_REG_WINDOW 0x00000048 95#define TI_REG_WINDOW 0x00000048
92#define TI_RWIN_SPTRS 0x000003c8 96#define TI_RWIN_SPTRS 0x000003c8
@@ -219,10 +223,10 @@ register struct thread_info *current_thread_info_reg asm("g6");
219#define TIF_UNALIGNED 5 /* allowed to do unaligned accesses */ 223#define TIF_UNALIGNED 5 /* allowed to do unaligned accesses */
220#define TIF_NEWSIGNALS 6 /* wants new-style signals */ 224#define TIF_NEWSIGNALS 6 /* wants new-style signals */
221#define TIF_32BIT 7 /* 32-bit binary */ 225#define TIF_32BIT 7 /* 32-bit binary */
222#define TIF_NEWCHILD 8 /* just-spawned child process */ 226/* flag bit 8 is available */
223#define TIF_SECCOMP 9 /* secure computing */ 227#define TIF_SECCOMP 9 /* secure computing */
224#define TIF_SYSCALL_AUDIT 10 /* syscall auditing active */ 228#define TIF_SYSCALL_AUDIT 10 /* syscall auditing active */
225#define TIF_SYSCALL_SUCCESS 11 229/* flag bit 11 is available */
226/* NOTE: Thread flags >= 12 should be ones we have no interest 230/* NOTE: Thread flags >= 12 should be ones we have no interest
227 * in using in assembly, else we can't use the mask as 231 * in using in assembly, else we can't use the mask as
228 * an immediate value in instructions such as andcc. 232 * an immediate value in instructions such as andcc.
@@ -239,10 +243,8 @@ register struct thread_info *current_thread_info_reg asm("g6");
239#define _TIF_UNALIGNED (1<<TIF_UNALIGNED) 243#define _TIF_UNALIGNED (1<<TIF_UNALIGNED)
240#define _TIF_NEWSIGNALS (1<<TIF_NEWSIGNALS) 244#define _TIF_NEWSIGNALS (1<<TIF_NEWSIGNALS)
241#define _TIF_32BIT (1<<TIF_32BIT) 245#define _TIF_32BIT (1<<TIF_32BIT)
242#define _TIF_NEWCHILD (1<<TIF_NEWCHILD)
243#define _TIF_SECCOMP (1<<TIF_SECCOMP) 246#define _TIF_SECCOMP (1<<TIF_SECCOMP)
244#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) 247#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
245#define _TIF_SYSCALL_SUCCESS (1<<TIF_SYSCALL_SUCCESS)
246#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING) 248#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
247#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 249#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
248 250
diff --git a/include/asm-sparc64/timer.h b/include/asm-sparc64/timer.h
index ba33a2b6b7bd..edc8e08c3a39 100644
--- a/include/asm-sparc64/timer.h
+++ b/include/asm-sparc64/timer.h
@@ -9,49 +9,8 @@
9 9
10#include <linux/types.h> 10#include <linux/types.h>
11 11
12/* How timers work:
13 *
14 * On uniprocessors we just use counter zero for the system wide
15 * ticker, this performs thread scheduling, clock book keeping,
16 * and runs timer based events. Previously we used the Ultra
17 * %tick interrupt for this purpose.
18 *
19 * On multiprocessors we pick one cpu as the master level 10 tick
20 * processor. Here this counter zero tick handles clock book
21 * keeping and timer events only. Each Ultra has it's level
22 * 14 %tick interrupt set to fire off as well, even the master
23 * tick cpu runs this locally. This ticker performs thread
24 * scheduling, system/user tick counting for the current thread,
25 * and also profiling if enabled.
26 */
27
28#include <linux/config.h> 12#include <linux/config.h>
29 13
30/* Two timers, traditionally steered to PIL's 10 and 14 respectively.
31 * But since INO packets are used on sun5, we could use any PIL level
32 * we like, however for now we use the normal ones.
33 *
34 * The 'reg' and 'interrupts' properties for these live in nodes named
35 * 'counter-timer'. The first of three 'reg' properties describe where
36 * the sun5_timer registers are. The other two I have no idea. (XXX)
37 */
38struct sun5_timer {
39 u64 count0;
40 u64 limit0;
41 u64 count1;
42 u64 limit1;
43};
44
45#define SUN5_LIMIT_ENABLE 0x80000000
46#define SUN5_LIMIT_TOZERO 0x40000000
47#define SUN5_LIMIT_ZRESTART 0x20000000
48#define SUN5_LIMIT_CMASK 0x1fffffff
49
50/* Given a HZ value, set the limit register to so that the timer IRQ
51 * gets delivered that often.
52 */
53#define SUN5_HZ_TO_LIMIT(__hz) (1000000/(__hz))
54
55struct sparc64_tick_ops { 14struct sparc64_tick_ops {
56 void (*init_tick)(unsigned long); 15 void (*init_tick)(unsigned long);
57 unsigned long (*get_tick)(void); 16 unsigned long (*get_tick)(void);
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-21 17:20:01 -0500