2 files changed, 0 insertions, 17 deletions

diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 3d3a3c4425a9..91e3677ae09d 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -199,11 +199,6 @@ int __init detect_cpu_and_cache_system(void)
                 break;
         }
 
-#ifdef CONFIG_SH_DIRECT_MAPPED
-        boot_cpu_data.icache.ways = 1;
-        boot_cpu_data.dcache.ways = 1;
-#endif
-
 #ifdef CONFIG_CPU_HAS_PTEA
         boot_cpu_data.flags |= CPU_HAS_PTEA;
 #endif
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 10c24356d2d5..d4079cab2d58 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -251,18 +251,6 @@ config SH7705_CACHE_32KB
         depends on CPU_SUBTYPE_SH7705
         default y
 
-config SH_DIRECT_MAPPED
-        bool "Use direct-mapped caching"
-        default n
-        help
-          Selecting this option will configure the caches to be direct-mapped,
-          even if the cache supports a 2 or 4-way mode. This is useful primarily
-          for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
-          SH4-202, SH4-501, etc.)
-
-          Turn this option off for platforms that do not have a direct-mapped
-          cache, and you have no need to run the caches in such a configuration.
-
 choice
         prompt "Cache mode"
         default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5