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-rw-r--r--Documentation/powerpc/dts-bindings/fsl/i2c.txt30
-rw-r--r--drivers/i2c/busses/Kconfig24
-rw-r--r--drivers/i2c/busses/Makefile2
-rw-r--r--drivers/i2c/busses/i2c-imx.c1
-rw-r--r--drivers/i2c/busses/i2c-mpc.c194
-rw-r--r--drivers/i2c/busses/i2c-nomadik.c959
-rw-r--r--drivers/i2c/busses/i2c-omap.c44
-rw-r--r--drivers/i2c/busses/i2c-pnx.c11
-rw-r--r--drivers/i2c/busses/i2c-xiic.c824
9 files changed, 1973 insertions, 116 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/i2c.txt b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
index b6d2e21474f9..50da20310585 100644
--- a/Documentation/powerpc/dts-bindings/fsl/i2c.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
@@ -2,15 +2,14 @@
2 2
3Required properties : 3Required properties :
4 4
5 - device_type : Should be "i2c"
6 - reg : Offset and length of the register set for the device 5 - reg : Offset and length of the register set for the device
6 - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a
7 compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121,
8 mpc5200 or mpc5200b. For the mpc5121, an additional node
9 "fsl,mpc5121-i2c-ctrl" is required as shown in the example below.
7 10
8Recommended properties : 11Recommended properties :
9 12
10 - compatible : compatibility list with 2 entries, the first should
11 be "fsl,CHIP-i2c" where CHIP is the name of a compatible processor,
12 e.g. mpc8313, mpc8543, mpc8544, mpc5200 or mpc5200b. The second one
13 should be "fsl-i2c".
14 - interrupts : <a b> where a is the interrupt number and b is a 13 - interrupts : <a b> where a is the interrupt number and b is a
15 field that represents an encoding of the sense and level 14 field that represents an encoding of the sense and level
16 information for the interrupt. This should be encoded based on 15 information for the interrupt. This should be encoded based on
@@ -24,25 +23,40 @@ Recommended properties :
24 23
25Examples : 24Examples :
26 25
26 /* MPC5121 based board */
27 i2c@1740 {
28 #address-cells = <1>;
29 #size-cells = <0>;
30 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
31 reg = <0x1740 0x20>;
32 interrupts = <11 0x8>;
33 interrupt-parent = <&ipic>;
34 clock-frequency = <100000>;
35 };
36
37 i2ccontrol@1760 {
38 compatible = "fsl,mpc5121-i2c-ctrl";
39 reg = <0x1760 0x8>;
40 };
41
42 /* MPC5200B based board */
27 i2c@3d00 { 43 i2c@3d00 {
28 #address-cells = <1>; 44 #address-cells = <1>;
29 #size-cells = <0>; 45 #size-cells = <0>;
30 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 46 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
31 cell-index = <0>;
32 reg = <0x3d00 0x40>; 47 reg = <0x3d00 0x40>;
33 interrupts = <2 15 0>; 48 interrupts = <2 15 0>;
34 interrupt-parent = <&mpc5200_pic>; 49 interrupt-parent = <&mpc5200_pic>;
35 fsl,preserve-clocking; 50 fsl,preserve-clocking;
36 }; 51 };
37 52
53 /* MPC8544 base board */
38 i2c@3100 { 54 i2c@3100 {
39 #address-cells = <1>; 55 #address-cells = <1>;
40 #size-cells = <0>; 56 #size-cells = <0>;
41 cell-index = <1>;
42 compatible = "fsl,mpc8544-i2c", "fsl-i2c"; 57 compatible = "fsl,mpc8544-i2c", "fsl-i2c";
43 reg = <0x3100 0x100>; 58 reg = <0x3100 0x100>;
44 interrupts = <43 2>; 59 interrupts = <43 2>;
45 interrupt-parent = <&mpic>; 60 interrupt-parent = <&mpic>;
46 clock-frequency = <400000>; 61 clock-frequency = <400000>;
47 }; 62 };
48
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 4cd1ff77ceda..9c6170cd9aac 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -421,13 +421,12 @@ config I2C_IXP2000
421 instead. 421 instead.
422 422
423config I2C_MPC 423config I2C_MPC
424 tristate "MPC107/824x/85xx/52xx/86xx" 424 tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
425 depends on PPC32 425 depends on PPC32
426 help 426 help
427 If you say yes to this option, support will be included for the 427 If you say yes to this option, support will be included for the
428 built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC8245 and 428 built-in I2C interface on the MPC107, Tsi107, MPC512x, MPC52xx,
429 MPC85xx/MPC8641 family processors. The driver may also work on 52xx 429 MPC8240, MPC8245, MPC83xx, MPC85xx and MPC8641 family processors.
430 family processors, though interrupts are known not to work.
431 430
432 This driver can also be built as a module. If so, the module 431 This driver can also be built as a module. If so, the module
433 will be called i2c-mpc. 432 will be called i2c-mpc.
@@ -442,6 +441,13 @@ config I2C_MV64XXX
442 This driver can also be built as a module. If so, the module 441 This driver can also be built as a module. If so, the module
443 will be called i2c-mv64xxx. 442 will be called i2c-mv64xxx.
444 443
444config I2C_NOMADIK
445 tristate "ST-Ericsson Nomadik/Ux500 I2C Controller"
446 depends on PLAT_NOMADIK
447 help
448 If you say yes to this option, support will be included for the
449 I2C interface from ST-Ericsson's Nomadik and Ux500 architectures.
450
445config I2C_OCORES 451config I2C_OCORES
446 tristate "OpenCores I2C Controller" 452 tristate "OpenCores I2C Controller"
447 depends on EXPERIMENTAL 453 depends on EXPERIMENTAL
@@ -577,6 +583,16 @@ config I2C_OCTEON
577 This driver can also be built as a module. If so, the module 583 This driver can also be built as a module. If so, the module
578 will be called i2c-octeon. 584 will be called i2c-octeon.
579 585
586config I2C_XILINX
587 tristate "Xilinx I2C Controller"
588 depends on EXPERIMENTAL && HAS_IOMEM
589 help
590 If you say yes to this option, support will be included for the
591 Xilinx I2C controller.
592
593 This driver can also be built as a module. If so, the module
594 will be called xilinx_i2c.
595
580comment "External I2C/SMBus adapter drivers" 596comment "External I2C/SMBus adapter drivers"
581 597
582config I2C_PARPORT 598config I2C_PARPORT
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index c2c4ea1908d8..097236f631e8 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
42obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o 42obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o
43obj-$(CONFIG_I2C_MPC) += i2c-mpc.o 43obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
44obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o 44obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
45obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
45obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o 46obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
46obj-$(CONFIG_I2C_OMAP) += i2c-omap.o 47obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
47obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o 48obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
@@ -55,6 +56,7 @@ obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
55obj-$(CONFIG_I2C_STU300) += i2c-stu300.o 56obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
56obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o 57obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
57obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o 58obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
59obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
58 60
59# External I2C/SMBus adapter drivers 61# External I2C/SMBus adapter drivers
60obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o 62obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 75bf820e7ccb..32375bddae7d 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -627,7 +627,6 @@ static int __exit i2c_imx_remove(struct platform_device *pdev)
627} 627}
628 628
629static struct platform_driver i2c_imx_driver = { 629static struct platform_driver i2c_imx_driver = {
630 .probe = i2c_imx_probe,
631 .remove = __exit_p(i2c_imx_remove), 630 .remove = __exit_p(i2c_imx_remove),
632 .driver = { 631 .driver = {
633 .name = DRIVER_NAME, 632 .name = DRIVER_NAME,
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index f627001108b8..78a15af32942 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -31,6 +31,9 @@
31 31
32#define DRV_NAME "mpc-i2c" 32#define DRV_NAME "mpc-i2c"
33 33
34#define MPC_I2C_CLOCK_LEGACY 0
35#define MPC_I2C_CLOCK_PRESERVE (~0U)
36
34#define MPC_I2C_FDR 0x04 37#define MPC_I2C_FDR 0x04
35#define MPC_I2C_CR 0x08 38#define MPC_I2C_CR 0x08
36#define MPC_I2C_SR 0x0c 39#define MPC_I2C_SR 0x0c
@@ -66,10 +69,9 @@ struct mpc_i2c_divider {
66 u16 fdr; /* including dfsrr */ 69 u16 fdr; /* including dfsrr */
67}; 70};
68 71
69struct mpc_i2c_match_data { 72struct mpc_i2c_data {
70 void (*setclock)(struct device_node *node, 73 void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
71 struct mpc_i2c *i2c, 74 u32 clock, u32 prescaler);
72 u32 clock, u32 prescaler);
73 u32 prescaler; 75 u32 prescaler;
74}; 76};
75 77
@@ -164,8 +166,8 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
164 return 0; 166 return 0;
165} 167}
166 168
167#ifdef CONFIG_PPC_MPC52xx 169#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
168static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { 170static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = {
169 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, 171 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
170 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, 172 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
171 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28}, 173 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
@@ -186,14 +188,15 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
186 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f} 188 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
187}; 189};
188 190
189int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler) 191static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
192 int prescaler)
190{ 193{
191 const struct mpc_i2c_divider *div = NULL; 194 const struct mpc_i2c_divider *div = NULL;
192 unsigned int pvr = mfspr(SPRN_PVR); 195 unsigned int pvr = mfspr(SPRN_PVR);
193 u32 divider; 196 u32 divider;
194 int i; 197 int i;
195 198
196 if (!clock) 199 if (clock == MPC_I2C_CLOCK_LEGACY)
197 return -EINVAL; 200 return -EINVAL;
198 201
199 /* Determine divider value */ 202 /* Determine divider value */
@@ -215,12 +218,18 @@ int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
215 return div ? (int)div->fdr : -EINVAL; 218 return div ? (int)div->fdr : -EINVAL;
216} 219}
217 220
218static void mpc_i2c_setclock_52xx(struct device_node *node, 221static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
219 struct mpc_i2c *i2c, 222 struct mpc_i2c *i2c,
220 u32 clock, u32 prescaler) 223 u32 clock, u32 prescaler)
221{ 224{
222 int ret, fdr; 225 int ret, fdr;
223 226
227 if (clock == MPC_I2C_CLOCK_PRESERVE) {
228 dev_dbg(i2c->dev, "using fdr %d\n",
229 readb(i2c->base + MPC_I2C_FDR));
230 return;
231 }
232
224 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler); 233 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);
225 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */ 234 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
226 235
@@ -229,16 +238,52 @@ static void mpc_i2c_setclock_52xx(struct device_node *node,
229 if (ret >= 0) 238 if (ret >= 0)
230 dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr); 239 dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
231} 240}
232#else /* !CONFIG_PPC_MPC52xx */ 241#else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
233static void mpc_i2c_setclock_52xx(struct device_node *node, 242static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
234 struct mpc_i2c *i2c, 243 struct mpc_i2c *i2c,
235 u32 clock, u32 prescaler) 244 u32 clock, u32 prescaler)
245{
246}
247#endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
248
249#ifdef CONFIG_PPC_MPC512x
250static void __devinit mpc_i2c_setup_512x(struct device_node *node,
251 struct mpc_i2c *i2c,
252 u32 clock, u32 prescaler)
253{
254 struct device_node *node_ctrl;
255 void __iomem *ctrl;
256 const u32 *pval;
257 u32 idx;
258
259 /* Enable I2C interrupts for mpc5121 */
260 node_ctrl = of_find_compatible_node(NULL, NULL,
261 "fsl,mpc5121-i2c-ctrl");
262 if (node_ctrl) {
263 ctrl = of_iomap(node_ctrl, 0);
264 if (ctrl) {
265 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
266 pval = of_get_property(node, "reg", NULL);
267 idx = (*pval & 0xff) / 0x20;
268 setbits32(ctrl, 1 << (24 + idx * 2));
269 iounmap(ctrl);
270 }
271 of_node_put(node_ctrl);
272 }
273
274 /* The clock setup for the 52xx works also fine for the 512x */
275 mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
276}
277#else /* CONFIG_PPC_MPC512x */
278static void __devinit mpc_i2c_setup_512x(struct device_node *node,
279 struct mpc_i2c *i2c,
280 u32 clock, u32 prescaler)
236{ 281{
237} 282}
238#endif /* CONFIG_PPC_MPC52xx*/ 283#endif /* CONFIG_PPC_MPC512x */
239 284
240#ifdef CONFIG_FSL_SOC 285#ifdef CONFIG_FSL_SOC
241static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = { 286static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] __devinitconst = {
242 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123}, 287 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
243 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102}, 288 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
244 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127}, 289 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
@@ -258,7 +303,7 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
258 {49152, 0x011e}, {61440, 0x011f} 303 {49152, 0x011e}, {61440, 0x011f}
259}; 304};
260 305
261u32 mpc_i2c_get_sec_cfg_8xxx(void) 306static u32 __devinit mpc_i2c_get_sec_cfg_8xxx(void)
262{ 307{
263 struct device_node *node = NULL; 308 struct device_node *node = NULL;
264 u32 __iomem *reg; 309 u32 __iomem *reg;
@@ -287,13 +332,14 @@ u32 mpc_i2c_get_sec_cfg_8xxx(void)
287 return val; 332 return val;
288} 333}
289 334
290int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler) 335static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
336 u32 prescaler)
291{ 337{
292 const struct mpc_i2c_divider *div = NULL; 338 const struct mpc_i2c_divider *div = NULL;
293 u32 divider; 339 u32 divider;
294 int i; 340 int i;
295 341
296 if (!clock) 342 if (clock == MPC_I2C_CLOCK_LEGACY)
297 return -EINVAL; 343 return -EINVAL;
298 344
299 /* Determine proper divider value */ 345 /* Determine proper divider value */
@@ -320,12 +366,19 @@ int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler)
320 return div ? (int)div->fdr : -EINVAL; 366 return div ? (int)div->fdr : -EINVAL;
321} 367}
322 368
323static void mpc_i2c_setclock_8xxx(struct device_node *node, 369static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
324 struct mpc_i2c *i2c, 370 struct mpc_i2c *i2c,
325 u32 clock, u32 prescaler) 371 u32 clock, u32 prescaler)
326{ 372{
327 int ret, fdr; 373 int ret, fdr;
328 374
375 if (clock == MPC_I2C_CLOCK_PRESERVE) {
376 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
377 readb(i2c->base + MPC_I2C_DFSRR),
378 readb(i2c->base + MPC_I2C_FDR));
379 return;
380 }
381
329 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler); 382 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
330 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */ 383 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
331 384
@@ -338,9 +391,9 @@ static void mpc_i2c_setclock_8xxx(struct device_node *node,
338} 391}
339 392
340#else /* !CONFIG_FSL_SOC */ 393#else /* !CONFIG_FSL_SOC */
341static void mpc_i2c_setclock_8xxx(struct device_node *node, 394static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
342 struct mpc_i2c *i2c, 395 struct mpc_i2c *i2c,
343 u32 clock, u32 prescaler) 396 u32 clock, u32 prescaler)
344{ 397{
345} 398}
346#endif /* CONFIG_FSL_SOC */ 399#endif /* CONFIG_FSL_SOC */
@@ -494,7 +547,7 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
494{ 547{
495 struct mpc_i2c *i2c; 548 struct mpc_i2c *i2c;
496 const u32 *prop; 549 const u32 *prop;
497 u32 clock = 0; 550 u32 clock = MPC_I2C_CLOCK_LEGACY;
498 int result = 0; 551 int result = 0;
499 int plen; 552 int plen;
500 553
@@ -523,21 +576,21 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
523 } 576 }
524 } 577 }
525 578
526 if (!of_get_property(op->node, "fsl,preserve-clocking", NULL)) { 579 if (of_get_property(op->node, "fsl,preserve-clocking", NULL)) {
580 clock = MPC_I2C_CLOCK_PRESERVE;
581 } else {
527 prop = of_get_property(op->node, "clock-frequency", &plen); 582 prop = of_get_property(op->node, "clock-frequency", &plen);
528 if (prop && plen == sizeof(u32)) 583 if (prop && plen == sizeof(u32))
529 clock = *prop; 584 clock = *prop;
585 }
530 586
531 if (match->data) { 587 if (match->data) {
532 struct mpc_i2c_match_data *data = 588 struct mpc_i2c_data *data = match->data;
533 (struct mpc_i2c_match_data *)match->data; 589 data->setup(op->node, i2c, clock, data->prescaler);
534 data->setclock(op->node, i2c, clock, data->prescaler); 590 } else {
535 } else { 591 /* Backwards compatibility */
536 /* Backwards compatibility */ 592 if (of_get_property(op->node, "dfsrr", NULL))
537 if (of_get_property(op->node, "dfsrr", NULL)) 593 mpc_i2c_setup_8xxx(op->node, i2c, clock, 0);
538 mpc_i2c_setclock_8xxx(op->node, i2c,
539 clock, 0);
540 }
541 } 594 }
542 595
543 dev_set_drvdata(&op->dev, i2c); 596 dev_set_drvdata(&op->dev, i2c);
@@ -582,47 +635,42 @@ static int __devexit fsl_i2c_remove(struct of_device *op)
582 return 0; 635 return 0;
583}; 636};
584 637
638static struct mpc_i2c_data mpc_i2c_data_512x __devinitdata = {
639 .setup = mpc_i2c_setup_512x,
640};
641
642static struct mpc_i2c_data mpc_i2c_data_52xx __devinitdata = {
643 .setup = mpc_i2c_setup_52xx,
644};
645
646static struct mpc_i2c_data mpc_i2c_data_8313 __devinitdata = {
647 .setup = mpc_i2c_setup_8xxx,
648};
649
650static struct mpc_i2c_data mpc_i2c_data_8543 __devinitdata = {
651 .setup = mpc_i2c_setup_8xxx,
652 .prescaler = 2,
653};
654
655static struct mpc_i2c_data mpc_i2c_data_8544 __devinitdata = {
656 .setup = mpc_i2c_setup_8xxx,
657 .prescaler = 3,
658};
659
585static const struct of_device_id mpc_i2c_of_match[] = { 660static const struct of_device_id mpc_i2c_of_match[] = {
586 {.compatible = "mpc5200-i2c", 661 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
587 .data = &(struct mpc_i2c_match_data) { 662 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
588 .setclock = mpc_i2c_setclock_52xx, 663 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
589 }, 664 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
590 }, 665 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
591 {.compatible = "fsl,mpc5200b-i2c", 666 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
592 .data = &(struct mpc_i2c_match_data) { 667 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
593 .setclock = mpc_i2c_setclock_52xx,
594 },
595 },
596 {.compatible = "fsl,mpc5200-i2c",
597 .data = &(struct mpc_i2c_match_data) {
598 .setclock = mpc_i2c_setclock_52xx,
599 },
600 },
601 {.compatible = "fsl,mpc8313-i2c",
602 .data = &(struct mpc_i2c_match_data) {
603 .setclock = mpc_i2c_setclock_8xxx,
604 },
605 },
606 {.compatible = "fsl,mpc8543-i2c",
607 .data = &(struct mpc_i2c_match_data) {
608 .setclock = mpc_i2c_setclock_8xxx,
609 .prescaler = 2,
610 },
611 },
612 {.compatible = "fsl,mpc8544-i2c",
613 .data = &(struct mpc_i2c_match_data) {
614 .setclock = mpc_i2c_setclock_8xxx,
615 .prescaler = 3,
616 },
617 /* Backward compatibility */ 668 /* Backward compatibility */
618 },
619 {.compatible = "fsl-i2c", }, 669 {.compatible = "fsl-i2c", },
620 {}, 670 {},
621}; 671};
622
623MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); 672MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
624 673
625
626/* Structure for a device driver */ 674/* Structure for a device driver */
627static struct of_platform_driver mpc_i2c_driver = { 675static struct of_platform_driver mpc_i2c_driver = {
628 .match_table = mpc_i2c_of_match, 676 .match_table = mpc_i2c_of_match,
@@ -655,5 +703,5 @@ module_exit(fsl_i2c_exit);
655 703
656MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>"); 704MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
657MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and " 705MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
658 "MPC824x/85xx/52xx processors"); 706 "MPC824x/83xx/85xx/86xx/512x/52xx processors");
659MODULE_LICENSE("GPL"); 707MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
new file mode 100644
index 000000000000..a15f731fa451
--- /dev/null
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -0,0 +1,959 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 * Copyright (C) 2009 STMicroelectronics
4 *
5 * I2C master mode controller driver, used in Nomadik 8815
6 * and Ux500 platforms.
7 *
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
14 */
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/i2c.h>
21#include <linux/err.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24
25#include <plat/i2c.h>
26
27#define DRIVER_NAME "nmk-i2c"
28
29/* I2C Controller register offsets */
30#define I2C_CR (0x000)
31#define I2C_SCR (0x004)
32#define I2C_HSMCR (0x008)
33#define I2C_MCR (0x00C)
34#define I2C_TFR (0x010)
35#define I2C_SR (0x014)
36#define I2C_RFR (0x018)
37#define I2C_TFTR (0x01C)
38#define I2C_RFTR (0x020)
39#define I2C_DMAR (0x024)
40#define I2C_BRCR (0x028)
41#define I2C_IMSCR (0x02C)
42#define I2C_RISR (0x030)
43#define I2C_MISR (0x034)
44#define I2C_ICR (0x038)
45
46/* Control registers */
47#define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
48#define I2C_CR_OM (0x3 << 1) /* Operating mode */
49#define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
50#define I2C_CR_SM (0x3 << 4) /* Speed mode */
51#define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
52#define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
53#define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
54#define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
55#define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
56#define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
57#define I2C_CR_LM (0x1 << 12) /* Loopback mode */
58#define I2C_CR_FON (0x3 << 13) /* Filtering on */
59#define I2C_CR_FS (0x3 << 15) /* Force stop enable */
60
61/* Master controller (MCR) register */
62#define I2C_MCR_OP (0x1 << 0) /* Operation */
63#define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
64#define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
65#define I2C_MCR_SB (0x1 << 11) /* Extended address */
66#define I2C_MCR_AM (0x3 << 12) /* Address type */
67#define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
68#define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
69
70/* Status register (SR) */
71#define I2C_SR_OP (0x3 << 0) /* Operation */
72#define I2C_SR_STATUS (0x3 << 2) /* controller status */
73#define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
74#define I2C_SR_TYPE (0x3 << 7) /* Receive type */
75#define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
76
77/* Interrupt mask set/clear (IMSCR) bits */
78#define I2C_IT_TXFE (0x1 << 0)
79#define I2C_IT_TXFNE (0x1 << 1)
80#define I2C_IT_TXFF (0x1 << 2)
81#define I2C_IT_TXFOVR (0x1 << 3)
82#define I2C_IT_RXFE (0x1 << 4)
83#define I2C_IT_RXFNF (0x1 << 5)
84#define I2C_IT_RXFF (0x1 << 6)
85#define I2C_IT_RFSR (0x1 << 16)
86#define I2C_IT_RFSE (0x1 << 17)
87#define I2C_IT_WTSR (0x1 << 18)
88#define I2C_IT_MTD (0x1 << 19)
89#define I2C_IT_STD (0x1 << 20)
90#define I2C_IT_MAL (0x1 << 24)
91#define I2C_IT_BERR (0x1 << 25)
92#define I2C_IT_MTDWS (0x1 << 28)
93
94#define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
95
96/* some bits in ICR are reserved */
97#define I2C_CLEAR_ALL_INTS 0x131f007f
98
99/* first three msb bits are reserved */
100#define IRQ_MASK(mask) (mask & 0x1fffffff)
101
102/* maximum threshold value */
103#define MAX_I2C_FIFO_THRESHOLD 15
104
105enum i2c_status {
106 I2C_NOP,
107 I2C_ON_GOING,
108 I2C_OK,
109 I2C_ABORT
110};
111
112/* operation */
113enum i2c_operation {
114 I2C_NO_OPERATION = 0xff,
115 I2C_WRITE = 0x00,
116 I2C_READ = 0x01
117};
118
119/* controller response timeout in ms */
120#define I2C_TIMEOUT_MS 500
121
122/**
123 * struct i2c_nmk_client - client specific data
124 * @slave_adr: 7-bit slave address
125 * @count: no. bytes to be transfered
126 * @buffer: client data buffer
127 * @xfer_bytes: bytes transfered till now
128 * @operation: current I2C operation
129 */
130struct i2c_nmk_client {
131 unsigned short slave_adr;
132 unsigned long count;
133 unsigned char *buffer;
134 unsigned long xfer_bytes;
135 enum i2c_operation operation;
136};
137
138/**
139 * struct nmk_i2c_dev - private data structure of the controller
140 * @pdev: parent platform device
141 * @adap: corresponding I2C adapter
142 * @irq: interrupt line for the controller
143 * @virtbase: virtual io memory area
144 * @clk: hardware i2c block clock
145 * @cfg: machine provided controller configuration
146 * @cli: holder of client specific data
147 * @stop: stop condition
148 * @xfer_complete: acknowledge completion for a I2C message
149 * @result: controller propogated result
150 */
151struct nmk_i2c_dev {
152 struct platform_device *pdev;
153 struct i2c_adapter adap;
154 int irq;
155 void __iomem *virtbase;
156 struct clk *clk;
157 struct nmk_i2c_controller cfg;
158 struct i2c_nmk_client cli;
159 int stop;
160 struct completion xfer_complete;
161 int result;
162};
163
164/* controller's abort causes */
165static const char *abort_causes[] = {
166 "no ack received after address transmission",
167 "no ack received during data phase",
168 "ack received after xmission of master code",
169 "master lost arbitration",
170 "slave restarts",
171 "slave reset",
172 "overflow, maxsize is 2047 bytes",
173};
174
175static inline void i2c_set_bit(void __iomem *reg, u32 mask)
176{
177 writel(readl(reg) | mask, reg);
178}
179
180static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
181{
182 writel(readl(reg) & ~mask, reg);
183}
184
185/**
186 * flush_i2c_fifo() - This function flushes the I2C FIFO
187 * @dev: private data of I2C Driver
188 *
189 * This function flushes the I2C Tx and Rx FIFOs. It returns
190 * 0 on successful flushing of FIFO
191 */
192static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
193{
194#define LOOP_ATTEMPTS 10
195 int i;
196 unsigned long timeout;
197
198 /*
199 * flush the transmit and receive FIFO. The flushing
200 * operation takes several cycles before to be completed.
201 * On the completion, the I2C internal logic clears these
202 * bits, until then no one must access Tx, Rx FIFO and
203 * should poll on these bits waiting for the completion.
204 */
205 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
206
207 for (i = 0; i < LOOP_ATTEMPTS; i++) {
208 timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT_MS);
209
210 while (!time_after(jiffies, timeout)) {
211 if ((readl(dev->virtbase + I2C_CR) &
212 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
213 return 0;
214 }
215 }
216
217 dev_err(&dev->pdev->dev, "flushing operation timed out "
218 "giving up after %d attempts", LOOP_ATTEMPTS);
219
220 return -ETIMEDOUT;
221}
222
223/**
224 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
225 * @dev: private data of I2C Driver
226 */
227static void disable_all_interrupts(struct nmk_i2c_dev *dev)
228{
229 u32 mask = IRQ_MASK(0);
230 writel(mask, dev->virtbase + I2C_IMSCR);
231}
232
233/**
234 * clear_all_interrupts() - Clear all interrupts of I2C Controller
235 * @dev: private data of I2C Driver
236 */
237static void clear_all_interrupts(struct nmk_i2c_dev *dev)
238{
239 u32 mask;
240 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
241 writel(mask, dev->virtbase + I2C_ICR);
242}
243
244/**
245 * init_hw() - initialize the I2C hardware
246 * @dev: private data of I2C Driver
247 */
248static int init_hw(struct nmk_i2c_dev *dev)
249{
250 int stat;
251
252 stat = flush_i2c_fifo(dev);
253 if (stat)
254 return stat;
255
256 /* disable the controller */
257 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
258
259 disable_all_interrupts(dev);
260
261 clear_all_interrupts(dev);
262
263 dev->cli.operation = I2C_NO_OPERATION;
264
265 return 0;
266}
267
268/* enable peripheral, master mode operation */
269#define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
270
271/**
272 * load_i2c_mcr_reg() - load the MCR register
273 * @dev: private data of controller
274 */
275static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev)
276{
277 u32 mcr = 0;
278
279 /* 7-bit address transaction */
280 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
281 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
282
283 /* start byte procedure not applied */
284 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
285
286 /* check the operation, master read/write? */
287 if (dev->cli.operation == I2C_WRITE)
288 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
289 else
290 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
291
292 /* stop or repeated start? */
293 if (dev->stop)
294 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
295 else
296 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
297
298 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
299
300 return mcr;
301}
302
303/**
304 * setup_i2c_controller() - setup the controller
305 * @dev: private data of controller
306 */
307static void setup_i2c_controller(struct nmk_i2c_dev *dev)
308{
309 u32 brcr1, brcr2;
310 u32 i2c_clk, div;
311
312 writel(0x0, dev->virtbase + I2C_CR);
313 writel(0x0, dev->virtbase + I2C_HSMCR);
314 writel(0x0, dev->virtbase + I2C_TFTR);
315 writel(0x0, dev->virtbase + I2C_RFTR);
316 writel(0x0, dev->virtbase + I2C_DMAR);
317
318 /*
319 * set the slsu:
320 *
321 * slsu defines the data setup time after SCL clock
322 * stretching in terms of i2c clk cycles. The
323 * needed setup time for the three modes are 250ns,
324 * 100ns, 10ns repectively thus leading to the values
325 * of 14, 6, 2 for a 48 MHz i2c clk.
326 */
327 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR);
328
329 i2c_clk = clk_get_rate(dev->clk);
330
331 /* fallback to std. mode if machine has not provided it */
332 if (dev->cfg.clk_freq == 0)
333 dev->cfg.clk_freq = 100000;
334
335 /*
336 * The spec says, in case of std. mode the divider is
337 * 2 whereas it is 3 for fast and fastplus mode of
338 * operation. TODO - high speed support.
339 */
340 div = (dev->cfg.clk_freq > 100000) ? 3 : 2;
341
342 /*
343 * generate the mask for baud rate counters. The controller
344 * has two baud rate counters. One is used for High speed
345 * operation, and the other is for std, fast mode, fast mode
346 * plus operation. Currently we do not supprt high speed mode
347 * so set brcr1 to 0.
348 */
349 brcr1 = 0 << 16;
350 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff;
351
352 /* set the baud rate counter register */
353 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
354
355 /*
356 * set the speed mode. Currently we support
357 * only standard and fast mode of operation
358 * TODO - support for fast mode plus (upto 1Mb/s)
359 * and high speed (up to 3.4 Mb/s)
360 */
361 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) {
362 dev_err(&dev->pdev->dev, "do not support this mode "
363 "defaulting to std. mode\n");
364 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
365 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
366 writel(I2C_FREQ_MODE_STANDARD << 4,
367 dev->virtbase + I2C_CR);
368 }
369 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR);
370
371 /* set the Tx and Rx FIFO threshold */
372 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR);
373 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR);
374}
375
376/**
377 * read_i2c() - Read from I2C client device
378 * @dev: private data of I2C Driver
379 *
380 * This function reads from i2c client device when controller is in
381 * master mode. There is a completion timeout. If there is no transfer
382 * before timeout error is returned.
383 */
384static int read_i2c(struct nmk_i2c_dev *dev)
385{
386 u32 status = 0;
387 u32 mcr;
388 u32 irq_mask = 0;
389 int timeout;
390
391 mcr = load_i2c_mcr_reg(dev);
392 writel(mcr, dev->virtbase + I2C_MCR);
393
394 /* load the current CR value */
395 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
396 dev->virtbase + I2C_CR);
397
398 /* enable the controller */
399 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
400
401 init_completion(&dev->xfer_complete);
402
403 /* enable interrupts by setting the mask */
404 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
405 I2C_IT_MAL | I2C_IT_BERR);
406
407 if (dev->stop)
408 irq_mask |= I2C_IT_MTD;
409 else
410 irq_mask |= I2C_IT_MTDWS;
411
412 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
413
414 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
415 dev->virtbase + I2C_IMSCR);
416
417 timeout = wait_for_completion_interruptible_timeout(
418 &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
419
420 if (timeout < 0) {
421 dev_err(&dev->pdev->dev,
422 "wait_for_completion_interruptible_timeout"
423 "returned %d waiting for event\n", timeout);
424 status = timeout;
425 }
426
427 if (timeout == 0) {
428 /* controler has timedout, re-init the h/w */
429 dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
430 (void) init_hw(dev);
431 status = -ETIMEDOUT;
432 }
433
434 return status;
435}
436
437/**
438 * write_i2c() - Write data to I2C client.
439 * @dev: private data of I2C Driver
440 *
441 * This function writes data to I2C client
442 */
443static int write_i2c(struct nmk_i2c_dev *dev)
444{
445 u32 status = 0;
446 u32 mcr;
447 u32 irq_mask = 0;
448 int timeout;
449
450 mcr = load_i2c_mcr_reg(dev);
451
452 writel(mcr, dev->virtbase + I2C_MCR);
453
454 /* load the current CR value */
455 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
456 dev->virtbase + I2C_CR);
457
458 /* enable the controller */
459 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
460
461 init_completion(&dev->xfer_complete);
462
463 /* enable interrupts by settings the masks */
464 irq_mask = (I2C_IT_TXFNE | I2C_IT_TXFOVR |
465 I2C_IT_MAL | I2C_IT_BERR);
466
467 /*
468 * check if we want to transfer a single or multiple bytes, if so
469 * set the MTDWS bit (Master Transaction Done Without Stop)
470 * to start repeated start operation
471 */
472 if (dev->stop)
473 irq_mask |= I2C_IT_MTD;
474 else
475 irq_mask |= I2C_IT_MTDWS;
476
477 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
478
479 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
480 dev->virtbase + I2C_IMSCR);
481
482 timeout = wait_for_completion_interruptible_timeout(
483 &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
484
485 if (timeout < 0) {
486 dev_err(&dev->pdev->dev,
487 "wait_for_completion_interruptible_timeout"
488 "returned %d waiting for event\n", timeout);
489 status = timeout;
490 }
491
492 if (timeout == 0) {
493 /* controler has timedout, re-init the h/w */
494 dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
495 (void) init_hw(dev);
496 status = -ETIMEDOUT;
497 }
498
499 return status;
500}
501
502/**
503 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
504 * @i2c_adap - Adapter pointer to the controller
505 * @msgs[] - Pointer to data to be written.
506 * @num_msgs - Number of messages to be executed
507 *
508 * This is the function called by the generic kernel i2c_transfer()
509 * or i2c_smbus...() API calls. Note that this code is protected by the
510 * semaphore set in the kernel i2c_transfer() function.
511 *
512 * NOTE:
513 * READ TRANSFER : We impose a restriction of the first message to be the
514 * index message for any read transaction.
515 * - a no index is coded as '0',
516 * - 2byte big endian index is coded as '3'
517 * !!! msg[0].buf holds the actual index.
518 * This is compatible with generic messages of smbus emulator
519 * that send a one byte index.
520 * eg. a I2C transation to read 2 bytes from index 0
521 * idx = 0;
522 * msg[0].addr = client->addr;
523 * msg[0].flags = 0x0;
524 * msg[0].len = 1;
525 * msg[0].buf = &idx;
526 *
527 * msg[1].addr = client->addr;
528 * msg[1].flags = I2C_M_RD;
529 * msg[1].len = 2;
530 * msg[1].buf = rd_buff
531 * i2c_transfer(adap, msg, 2);
532 *
533 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
534 * If you want to emulate an SMBUS write transaction put the
535 * index as first byte(or first and second) in the payload.
536 * eg. a I2C transation to write 2 bytes from index 1
537 * wr_buff[0] = 0x1;
538 * wr_buff[1] = 0x23;
539 * wr_buff[2] = 0x46;
540 * msg[0].flags = 0x0;
541 * msg[0].len = 3;
542 * msg[0].buf = wr_buff;
543 * i2c_transfer(adap, msg, 1);
544 *
545 * To read or write a block of data (multiple bytes) using SMBUS emulation
546 * please use the i2c_smbus_read_i2c_block_data()
547 * or i2c_smbus_write_i2c_block_data() API
548 */
549static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
550 struct i2c_msg msgs[], int num_msgs)
551{
552 int status;
553 int i;
554 u32 cause;
555 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
556
557 status = init_hw(dev);
558 if (status)
559 return status;
560
561 /* setup the i2c controller */
562 setup_i2c_controller(dev);
563
564 for (i = 0; i < num_msgs; i++) {
565 if (unlikely(msgs[i].flags & I2C_M_TEN)) {
566 dev_err(&dev->pdev->dev, "10 bit addressing"
567 "not supported\n");
568 return -EINVAL;
569 }
570 dev->cli.slave_adr = msgs[i].addr;
571 dev->cli.buffer = msgs[i].buf;
572 dev->cli.count = msgs[i].len;
573 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
574 dev->result = 0;
575
576 if (msgs[i].flags & I2C_M_RD) {
577 /* it is a read operation */
578 dev->cli.operation = I2C_READ;
579 status = read_i2c(dev);
580 } else {
581 /* write operation */
582 dev->cli.operation = I2C_WRITE;
583 status = write_i2c(dev);
584 }
585 if (status || (dev->result)) {
586 /* get the abort cause */
587 cause = (readl(dev->virtbase + I2C_SR) >> 4) & 0x7;
588 dev_err(&dev->pdev->dev, "error during I2C"
589 "message xfer: %d\n", cause);
590 dev_err(&dev->pdev->dev, "%s\n",
591 cause >= ARRAY_SIZE(abort_causes)
592 ? "unknown reason" : abort_causes[cause]);
593 return status;
594 }
595 mdelay(1);
596 }
597 /* return the no. messages processed */
598 if (status)
599 return status;
600 else
601 return num_msgs;
602}
603
604/**
605 * disable_interrupts() - disable the interrupts
606 * @dev: private data of controller
607 */
608static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
609{
610 irq = IRQ_MASK(irq);
611 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
612 dev->virtbase + I2C_IMSCR);
613 return 0;
614}
615
616/**
617 * i2c_irq_handler() - interrupt routine
618 * @irq: interrupt number
619 * @arg: data passed to the handler
620 *
621 * This is the interrupt handler for the i2c driver. Currently
622 * it handles the major interrupts like Rx & Tx FIFO management
623 * interrupts, master transaction interrupts, arbitration and
624 * bus error interrupts. The rest of the interrupts are treated as
625 * unhandled.
626 */
627static irqreturn_t i2c_irq_handler(int irq, void *arg)
628{
629 struct nmk_i2c_dev *dev = arg;
630 u32 tft, rft;
631 u32 count;
632 u32 misr;
633 u32 src = 0;
634
635 /* load Tx FIFO and Rx FIFO threshold values */
636 tft = readl(dev->virtbase + I2C_TFTR);
637 rft = readl(dev->virtbase + I2C_RFTR);
638
639 /* read interrupt status register */
640 misr = readl(dev->virtbase + I2C_MISR);
641
642 src = __ffs(misr);
643 switch ((1 << src)) {
644
645 /* Transmit FIFO nearly empty interrupt */
646 case I2C_IT_TXFNE:
647 {
648 if (dev->cli.operation == I2C_READ) {
649 /*
650 * in read operation why do we care for writing?
651 * so disable the Transmit FIFO interrupt
652 */
653 disable_interrupts(dev, I2C_IT_TXFNE);
654 } else {
655 for (count = (MAX_I2C_FIFO_THRESHOLD - tft - 2);
656 (count > 0) &&
657 (dev->cli.count != 0);
658 count--) {
659 /* write to the Tx FIFO */
660 writeb(*dev->cli.buffer,
661 dev->virtbase + I2C_TFR);
662 dev->cli.buffer++;
663 dev->cli.count--;
664 dev->cli.xfer_bytes++;
665 }
666 /*
667 * if done, close the transfer by disabling the
668 * corresponding TXFNE interrupt
669 */
670 if (dev->cli.count == 0)
671 disable_interrupts(dev, I2C_IT_TXFNE);
672 }
673 }
674 break;
675
676 /*
677 * Rx FIFO nearly full interrupt.
678 * This is set when the numer of entries in Rx FIFO is
679 * greater or equal than the threshold value programmed
680 * in RFT
681 */
682 case I2C_IT_RXFNF:
683 for (count = rft; count > 0; count--) {
684 /* Read the Rx FIFO */
685 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
686 dev->cli.buffer++;
687 }
688 dev->cli.count -= rft;
689 dev->cli.xfer_bytes += rft;
690 break;
691
692 /* Rx FIFO full */
693 case I2C_IT_RXFF:
694 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
695 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
696 dev->cli.buffer++;
697 }
698 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
699 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
700 break;
701
702 /* Master Transaction Done with/without stop */
703 case I2C_IT_MTD:
704 case I2C_IT_MTDWS:
705 if (dev->cli.operation == I2C_READ) {
706 while (!readl(dev->virtbase + I2C_RISR) & I2C_IT_RXFE) {
707 if (dev->cli.count == 0)
708 break;
709 *dev->cli.buffer =
710 readb(dev->virtbase + I2C_RFR);
711 dev->cli.buffer++;
712 dev->cli.count--;
713 dev->cli.xfer_bytes++;
714 }
715 }
716
717 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTD);
718 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTDWS);
719
720 disable_interrupts(dev,
721 (I2C_IT_TXFNE | I2C_IT_TXFE | I2C_IT_TXFF
722 | I2C_IT_TXFOVR | I2C_IT_RXFNF
723 | I2C_IT_RXFF | I2C_IT_RXFE));
724
725 if (dev->cli.count) {
726 dev->result = -1;
727 dev_err(&dev->pdev->dev, "%lu bytes still remain to be"
728 "xfered\n", dev->cli.count);
729 (void) init_hw(dev);
730 }
731 complete(&dev->xfer_complete);
732
733 break;
734
735 /* Master Arbitration lost interrupt */
736 case I2C_IT_MAL:
737 dev->result = -1;
738 (void) init_hw(dev);
739
740 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
741 complete(&dev->xfer_complete);
742
743 break;
744
745 /*
746 * Bus Error interrupt.
747 * This happens when an unexpected start/stop condition occurs
748 * during the transaction.
749 */
750 case I2C_IT_BERR:
751 dev->result = -1;
752 /* get the status */
753 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
754 (void) init_hw(dev);
755
756 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
757 complete(&dev->xfer_complete);
758
759 break;
760
761 /*
762 * Tx FIFO overrun interrupt.
763 * This is set when a write operation in Tx FIFO is performed and
764 * the Tx FIFO is full.
765 */
766 case I2C_IT_TXFOVR:
767 dev->result = -1;
768 (void) init_hw(dev);
769
770 dev_err(&dev->pdev->dev, "Tx Fifo Over run\n");
771 complete(&dev->xfer_complete);
772
773 break;
774
775 /* unhandled interrupts by this driver - TODO*/
776 case I2C_IT_TXFE:
777 case I2C_IT_TXFF:
778 case I2C_IT_RXFE:
779 case I2C_IT_RFSR:
780 case I2C_IT_RFSE:
781 case I2C_IT_WTSR:
782 case I2C_IT_STD:
783 dev_err(&dev->pdev->dev, "unhandled Interrupt\n");
784 break;
785 default:
786 dev_err(&dev->pdev->dev, "spurious Interrupt..\n");
787 break;
788 }
789
790 return IRQ_HANDLED;
791}
792
793static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
794{
795 return I2C_FUNC_I2C
796 | I2C_FUNC_SMBUS_BYTE_DATA
797 | I2C_FUNC_SMBUS_WORD_DATA
798 | I2C_FUNC_SMBUS_I2C_BLOCK;
799}
800
801static const struct i2c_algorithm nmk_i2c_algo = {
802 .master_xfer = nmk_i2c_xfer,
803 .functionality = nmk_i2c_functionality
804};
805
806static int __devinit nmk_i2c_probe(struct platform_device *pdev)
807{
808 int ret = 0;
809 struct resource *res;
810 struct nmk_i2c_controller *pdata =
811 pdev->dev.platform_data;
812 struct nmk_i2c_dev *dev;
813 struct i2c_adapter *adap;
814
815 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
816 if (!dev) {
817 dev_err(&pdev->dev, "cannot allocate memory\n");
818 ret = -ENOMEM;
819 goto err_no_mem;
820 }
821
822 dev->pdev = pdev;
823 platform_set_drvdata(pdev, dev);
824
825 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
826 if (!res) {
827 ret = -ENOENT;
828 goto err_no_resource;
829 }
830
831 if (request_mem_region(res->start, resource_size(res),
832 DRIVER_NAME "I/O region") == NULL) {
833 ret = -EBUSY;
834 goto err_no_region;
835 }
836
837 dev->virtbase = ioremap(res->start, resource_size(res));
838 if (!dev->virtbase) {
839 ret = -ENOMEM;
840 goto err_no_ioremap;
841 }
842
843 dev->irq = platform_get_irq(pdev, 0);
844 ret = request_irq(dev->irq, i2c_irq_handler, IRQF_DISABLED,
845 DRIVER_NAME, dev);
846 if (ret) {
847 dev_err(&pdev->dev, "cannot claim the irq %d\n", dev->irq);
848 goto err_irq;
849 }
850
851 dev->clk = clk_get(&pdev->dev, NULL);
852 if (IS_ERR(dev->clk)) {
853 dev_err(&pdev->dev, "could not get i2c clock\n");
854 ret = PTR_ERR(dev->clk);
855 goto err_no_clk;
856 }
857
858 clk_enable(dev->clk);
859
860 adap = &dev->adap;
861 adap->dev.parent = &pdev->dev;
862 adap->owner = THIS_MODULE;
863 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
864 adap->algo = &nmk_i2c_algo;
865
866 /* fetch the controller id */
867 adap->nr = pdev->id;
868
869 /* fetch the controller configuration from machine */
870 dev->cfg.clk_freq = pdata->clk_freq;
871 dev->cfg.slsu = pdata->slsu;
872 dev->cfg.tft = pdata->tft;
873 dev->cfg.rft = pdata->rft;
874 dev->cfg.sm = pdata->sm;
875
876 i2c_set_adapdata(adap, dev);
877
878 ret = init_hw(dev);
879 if (ret != 0) {
880 dev_err(&pdev->dev, "error in initializing i2c hardware\n");
881 goto err_init_hw;
882 }
883
884 dev_dbg(&pdev->dev, "initialize I2C%d bus on virtual "
885 "base %p\n", pdev->id, dev->virtbase);
886
887 ret = i2c_add_numbered_adapter(adap);
888 if (ret) {
889 dev_err(&pdev->dev, "failed to add adapter\n");
890 goto err_add_adap;
891 }
892
893 return 0;
894
895 err_init_hw:
896 clk_disable(dev->clk);
897 err_add_adap:
898 clk_put(dev->clk);
899 err_no_clk:
900 free_irq(dev->irq, dev);
901 err_irq:
902 iounmap(dev->virtbase);
903 err_no_ioremap:
904 release_mem_region(res->start, resource_size(res));
905 err_no_region:
906 platform_set_drvdata(pdev, NULL);
907 err_no_resource:
908 kfree(dev);
909 err_no_mem:
910
911 return ret;
912}
913
914static int __devexit nmk_i2c_remove(struct platform_device *pdev)
915{
916 struct nmk_i2c_dev *dev = platform_get_drvdata(pdev);
917
918 i2c_del_adapter(&dev->adap);
919 flush_i2c_fifo(dev);
920 disable_all_interrupts(dev);
921 clear_all_interrupts(dev);
922 /* disable the controller */
923 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
924 free_irq(dev->irq, dev);
925 iounmap(dev->virtbase);
926 clk_disable(dev->clk);
927 clk_put(dev->clk);
928 platform_set_drvdata(pdev, NULL);
929 kfree(dev);
930
931 return 0;
932}
933
934static struct platform_driver nmk_i2c_driver = {
935 .driver = {
936 .owner = THIS_MODULE,
937 .name = DRIVER_NAME,
938 },
939 .probe = nmk_i2c_probe,
940 .remove = __devexit_p(nmk_i2c_remove),
941};
942
943static int __init nmk_i2c_init(void)
944{
945 return platform_driver_register(&nmk_i2c_driver);
946}
947
948static void __exit nmk_i2c_exit(void)
949{
950 platform_driver_unregister(&nmk_i2c_driver);
951}
952
953subsys_initcall(nmk_i2c_init);
954module_exit(nmk_i2c_exit);
955
956MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
957MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
958MODULE_LICENSE("GPL");
959MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 0037e31076ba..913abd7c172f 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -49,24 +49,24 @@
49#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) 49#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
50 50
51#define OMAP_I2C_REV_REG 0x00 51#define OMAP_I2C_REV_REG 0x00
52#define OMAP_I2C_IE_REG 0x04 52#define OMAP_I2C_IE_REG 0x01
53#define OMAP_I2C_STAT_REG 0x08 53#define OMAP_I2C_STAT_REG 0x02
54#define OMAP_I2C_IV_REG 0x0c 54#define OMAP_I2C_IV_REG 0x03
55/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ 55/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56#define OMAP_I2C_WE_REG 0x0c 56#define OMAP_I2C_WE_REG 0x03
57#define OMAP_I2C_SYSS_REG 0x10 57#define OMAP_I2C_SYSS_REG 0x04
58#define OMAP_I2C_BUF_REG 0x14 58#define OMAP_I2C_BUF_REG 0x05
59#define OMAP_I2C_CNT_REG 0x18 59#define OMAP_I2C_CNT_REG 0x06
60#define OMAP_I2C_DATA_REG 0x1c 60#define OMAP_I2C_DATA_REG 0x07
61#define OMAP_I2C_SYSC_REG 0x20 61#define OMAP_I2C_SYSC_REG 0x08
62#define OMAP_I2C_CON_REG 0x24 62#define OMAP_I2C_CON_REG 0x09
63#define OMAP_I2C_OA_REG 0x28 63#define OMAP_I2C_OA_REG 0x0a
64#define OMAP_I2C_SA_REG 0x2c 64#define OMAP_I2C_SA_REG 0x0b
65#define OMAP_I2C_PSC_REG 0x30 65#define OMAP_I2C_PSC_REG 0x0c
66#define OMAP_I2C_SCLL_REG 0x34 66#define OMAP_I2C_SCLL_REG 0x0d
67#define OMAP_I2C_SCLH_REG 0x38 67#define OMAP_I2C_SCLH_REG 0x0e
68#define OMAP_I2C_SYSTEST_REG 0x3c 68#define OMAP_I2C_SYSTEST_REG 0x0f
69#define OMAP_I2C_BUFSTAT_REG 0x40 69#define OMAP_I2C_BUFSTAT_REG 0x10
70 70
71/* I2C Interrupt Enable Register (OMAP_I2C_IE): */ 71/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
72#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ 72#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
@@ -161,6 +161,7 @@ struct omap_i2c_dev {
161 struct device *dev; 161 struct device *dev;
162 void __iomem *base; /* virtual */ 162 void __iomem *base; /* virtual */
163 int irq; 163 int irq;
164 int reg_shift; /* bit shift for I2C register addresses */
164 struct clk *iclk; /* Interface clock */ 165 struct clk *iclk; /* Interface clock */
165 struct clk *fclk; /* Functional clock */ 166 struct clk *fclk; /* Functional clock */
166 struct completion cmd_complete; 167 struct completion cmd_complete;
@@ -189,12 +190,12 @@ struct omap_i2c_dev {
189static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, 190static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
190 int reg, u16 val) 191 int reg, u16 val)
191{ 192{
192 __raw_writew(val, i2c_dev->base + reg); 193 __raw_writew(val, i2c_dev->base + (reg << i2c_dev->reg_shift));
193} 194}
194 195
195static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) 196static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
196{ 197{
197 return __raw_readw(i2c_dev->base + reg); 198 return __raw_readw(i2c_dev->base + (reg << i2c_dev->reg_shift));
198} 199}
199 200
200static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) 201static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
@@ -924,6 +925,11 @@ omap_i2c_probe(struct platform_device *pdev)
924 dev->b_hw = 1; /* Enable hardware fixes */ 925 dev->b_hw = 1; /* Enable hardware fixes */
925 } 926 }
926 927
928 if (cpu_is_omap7xx())
929 dev->reg_shift = 1;
930 else
931 dev->reg_shift = 2;
932
927 /* reset ASAP, clearing any IRQs */ 933 /* reset ASAP, clearing any IRQs */
928 omap_i2c_init(dev); 934 omap_i2c_init(dev);
929 935
diff --git a/drivers/i2c/busses/i2c-pnx.c b/drivers/i2c/busses/i2c-pnx.c
index 2b0bd0b042d6..9532dee6b580 100644
--- a/drivers/i2c/busses/i2c-pnx.c
+++ b/drivers/i2c/busses/i2c-pnx.c
@@ -172,12 +172,6 @@ static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
172 /* We still have something to talk about... */ 172 /* We still have something to talk about... */
173 val = *alg_data->mif.buf++; 173 val = *alg_data->mif.buf++;
174 174
175 if (alg_data->mif.len == 1) {
176 val |= stop_bit;
177 if (!alg_data->last)
178 val |= start_bit;
179 }
180
181 alg_data->mif.len--; 175 alg_data->mif.len--;
182 iowrite32(val, I2C_REG_TX(alg_data)); 176 iowrite32(val, I2C_REG_TX(alg_data));
183 177
@@ -251,11 +245,6 @@ static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
251 __func__); 245 __func__);
252 246
253 if (alg_data->mif.len == 1) { 247 if (alg_data->mif.len == 1) {
254 /* Last byte, do not acknowledge next rcv. */
255 val |= stop_bit;
256 if (!alg_data->last)
257 val |= start_bit;
258
259 /* 248 /*
260 * Enable interrupt RFDAIE (data in Rx fifo), 249 * Enable interrupt RFDAIE (data in Rx fifo),
261 * and disable DRMIE (need data for Tx) 250 * and disable DRMIE (need data for Tx)
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
new file mode 100644
index 000000000000..eece39a5a30e
--- /dev/null
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -0,0 +1,824 @@
1/*
2 * i2c-xiic.c
3 * Copyright (c) 2002-2007 Xilinx Inc.
4 * Copyright (c) 2009-2010 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 *
20 * This code was implemented by Mocean Laboratories AB when porting linux
21 * to the automotive development board Russellville. The copyright holder
22 * as seen in the header is Intel corporation.
23 * Mocean Laboratories forked off the GNU/Linux platform work into a
24 * separate company called Pelagicore AB, which commited the code to the
25 * kernel.
26 */
27
28/* Supports:
29 * Xilinx IIC
30 */
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/init.h>
34#include <linux/errno.h>
35#include <linux/platform_device.h>
36#include <linux/i2c.h>
37#include <linux/interrupt.h>
38#include <linux/wait.h>
39#include <linux/i2c-xiic.h>
40#include <linux/io.h>
41
42#define DRIVER_NAME "xiic-i2c"
43
44enum xilinx_i2c_state {
45 STATE_DONE,
46 STATE_ERROR,
47 STATE_START
48};
49
50/**
51 * struct xiic_i2c - Internal representation of the XIIC I2C bus
52 * @base: Memory base of the HW registers
53 * @wait: Wait queue for callers
54 * @adap: Kernel adapter representation
55 * @tx_msg: Messages from above to be sent
56 * @lock: Mutual exclusion
57 * @tx_pos: Current pos in TX message
58 * @nmsgs: Number of messages in tx_msg
59 * @state: See STATE_
60 * @rx_msg: Current RX message
61 * @rx_pos: Position within current RX message
62 */
63struct xiic_i2c {
64 void __iomem *base;
65 wait_queue_head_t wait;
66 struct i2c_adapter adap;
67 struct i2c_msg *tx_msg;
68 spinlock_t lock;
69 unsigned int tx_pos;
70 unsigned int nmsgs;
71 enum xilinx_i2c_state state;
72 struct i2c_msg *rx_msg;
73 int rx_pos;
74};
75
76
77#define XIIC_MSB_OFFSET 0
78#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
79
80/*
81 * Register offsets in bytes from RegisterBase. Three is added to the
82 * base offset to access LSB (IBM style) of the word
83 */
84#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
85#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
86#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
87#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
88#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
89#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
90#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
91#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
92#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
93#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
94
95/* Control Register masks */
96#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
97#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
98#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
99#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
100#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
101#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
102#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
103
104/* Status Register masks */
105#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
106#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
107#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
108#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
109#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
110#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
111#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
112#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
113
114/* Interrupt Status Register masks Interrupt occurs when... */
115#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
116#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
117#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
118#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
119#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
120#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
121#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
122#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
123
124/* The following constants specify the depth of the FIFOs */
125#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
126#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
127
128/* The following constants specify groups of interrupts that are typically
129 * enabled or disables at the same time
130 */
131#define XIIC_TX_INTERRUPTS \
132(XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
133
134#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
135
136/* The following constants are used with the following macros to specify the
137 * operation, a read or write operation.
138 */
139#define XIIC_READ_OPERATION 1
140#define XIIC_WRITE_OPERATION 0
141
142/*
143 * Tx Fifo upper bit masks.
144 */
145#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
146#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
147
148/*
149 * The following constants define the register offsets for the Interrupt
150 * registers. There are some holes in the memory map for reserved addresses
151 * to allow other registers to be added and still match the memory map of the
152 * interrupt controller registers
153 */
154#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
155#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
156#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
157#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
158
159#define XIIC_RESET_MASK 0xAUL
160
161/*
162 * The following constant is used for the device global interrupt enable
163 * register, to enable all interrupts for the device, this is the only bit
164 * in the register
165 */
166#define XIIC_GINTR_ENABLE_MASK 0x80000000UL
167
168#define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
169#define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
170
171static void xiic_start_xfer(struct xiic_i2c *i2c);
172static void __xiic_start_xfer(struct xiic_i2c *i2c);
173
174static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
175{
176 iowrite8(value, i2c->base + reg);
177}
178
179static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
180{
181 return ioread8(i2c->base + reg);
182}
183
184static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
185{
186 iowrite16(value, i2c->base + reg);
187}
188
189static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
190{
191 iowrite32(value, i2c->base + reg);
192}
193
194static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
195{
196 return ioread32(i2c->base + reg);
197}
198
199static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
200{
201 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
202 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
203}
204
205static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
206{
207 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
208 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
209}
210
211static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
212{
213 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
214 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
215}
216
217static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
218{
219 xiic_irq_clr(i2c, mask);
220 xiic_irq_en(i2c, mask);
221}
222
223static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
224{
225 u8 sr;
226 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
227 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
228 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
229 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
230}
231
232static void xiic_reinit(struct xiic_i2c *i2c)
233{
234 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
235
236 /* Set receive Fifo depth to maximum (zero based). */
237 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
238
239 /* Reset Tx Fifo. */
240 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
241
242 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
243 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
244
245 /* make sure RX fifo is empty */
246 xiic_clear_rx_fifo(i2c);
247
248 /* Enable interrupts */
249 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
250
251 xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK);
252}
253
254static void xiic_deinit(struct xiic_i2c *i2c)
255{
256 u8 cr;
257
258 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
259
260 /* Disable IIC Device. */
261 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
262 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
263}
264
265static void xiic_read_rx(struct xiic_i2c *i2c)
266{
267 u8 bytes_in_fifo;
268 int i;
269
270 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
271
272 dev_dbg(i2c->adap.dev.parent, "%s entry, bytes in fifo: %d, msg: %d"
273 ", SR: 0x%x, CR: 0x%x\n",
274 __func__, bytes_in_fifo, xiic_rx_space(i2c),
275 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
276 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
277
278 if (bytes_in_fifo > xiic_rx_space(i2c))
279 bytes_in_fifo = xiic_rx_space(i2c);
280
281 for (i = 0; i < bytes_in_fifo; i++)
282 i2c->rx_msg->buf[i2c->rx_pos++] =
283 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
284
285 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
286 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
287 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
288}
289
290static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
291{
292 /* return the actual space left in the FIFO */
293 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
294}
295
296static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
297{
298 u8 fifo_space = xiic_tx_fifo_space(i2c);
299 int len = xiic_tx_space(i2c);
300
301 len = (len > fifo_space) ? fifo_space : len;
302
303 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
304 __func__, len, fifo_space);
305
306 while (len--) {
307 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
308 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
309 /* last message in transfer -> STOP */
310 data |= XIIC_TX_DYN_STOP_MASK;
311 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
312
313 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
314 } else
315 xiic_setreg8(i2c, XIIC_DTR_REG_OFFSET, data);
316 }
317}
318
319static void xiic_wakeup(struct xiic_i2c *i2c, int code)
320{
321 i2c->tx_msg = NULL;
322 i2c->rx_msg = NULL;
323 i2c->nmsgs = 0;
324 i2c->state = code;
325 wake_up(&i2c->wait);
326}
327
328static void xiic_process(struct xiic_i2c *i2c)
329{
330 u32 pend, isr, ier;
331 u32 clr = 0;
332
333 /* Get the interrupt Status from the IPIF. There is no clearing of
334 * interrupts in the IPIF. Interrupts must be cleared at the source.
335 * To find which interrupts are pending; AND interrupts pending with
336 * interrupts masked.
337 */
338 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
339 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
340 pend = isr & ier;
341
342 dev_dbg(i2c->adap.dev.parent, "%s entry, IER: 0x%x, ISR: 0x%x, "
343 "pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n",
344 __func__, ier, isr, pend, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
345 i2c->tx_msg, i2c->nmsgs);
346
347 /* Do not processes a devices interrupts if the device has no
348 * interrupts pending
349 */
350 if (!pend)
351 return;
352
353 /* Service requesting interrupt */
354 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
355 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
356 !(pend & XIIC_INTR_RX_FULL_MASK))) {
357 /* bus arbritration lost, or...
358 * Transmit error _OR_ RX completed
359 * if this happens when RX_FULL is not set
360 * this is probably a TX error
361 */
362
363 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
364
365 /* dynamic mode seem to suffer from problems if we just flushes
366 * fifos and the next message is a TX with len 0 (only addr)
367 * reset the IP instead of just flush fifos
368 */
369 xiic_reinit(i2c);
370
371 if (i2c->tx_msg)
372 xiic_wakeup(i2c, STATE_ERROR);
373
374 } else if (pend & XIIC_INTR_RX_FULL_MASK) {
375 /* Receive register/FIFO is full */
376
377 clr = XIIC_INTR_RX_FULL_MASK;
378 if (!i2c->rx_msg) {
379 dev_dbg(i2c->adap.dev.parent,
380 "%s unexpexted RX IRQ\n", __func__);
381 xiic_clear_rx_fifo(i2c);
382 goto out;
383 }
384
385 xiic_read_rx(i2c);
386 if (xiic_rx_space(i2c) == 0) {
387 /* this is the last part of the message */
388 i2c->rx_msg = NULL;
389
390 /* also clear TX error if there (RX complete) */
391 clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
392
393 dev_dbg(i2c->adap.dev.parent,
394 "%s end of message, nmsgs: %d\n",
395 __func__, i2c->nmsgs);
396
397 /* send next message if this wasn't the last,
398 * otherwise the transfer will be finialise when
399 * receiving the bus not busy interrupt
400 */
401 if (i2c->nmsgs > 1) {
402 i2c->nmsgs--;
403 i2c->tx_msg++;
404 dev_dbg(i2c->adap.dev.parent,
405 "%s will start next...\n", __func__);
406
407 __xiic_start_xfer(i2c);
408 }
409 }
410 } else if (pend & XIIC_INTR_BNB_MASK) {
411 /* IIC bus has transitioned to not busy */
412 clr = XIIC_INTR_BNB_MASK;
413
414 /* The bus is not busy, disable BusNotBusy interrupt */
415 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
416
417 if (!i2c->tx_msg)
418 goto out;
419
420 if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
421 xiic_tx_space(i2c) == 0)
422 xiic_wakeup(i2c, STATE_DONE);
423 else
424 xiic_wakeup(i2c, STATE_ERROR);
425
426 } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
427 /* Transmit register/FIFO is empty or ½ empty */
428
429 clr = pend &
430 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK);
431
432 if (!i2c->tx_msg) {
433 dev_dbg(i2c->adap.dev.parent,
434 "%s unexpexted TX IRQ\n", __func__);
435 goto out;
436 }
437
438 xiic_fill_tx_fifo(i2c);
439
440 /* current message sent and there is space in the fifo */
441 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
442 dev_dbg(i2c->adap.dev.parent,
443 "%s end of message sent, nmsgs: %d\n",
444 __func__, i2c->nmsgs);
445 if (i2c->nmsgs > 1) {
446 i2c->nmsgs--;
447 i2c->tx_msg++;
448 __xiic_start_xfer(i2c);
449 } else {
450 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
451
452 dev_dbg(i2c->adap.dev.parent,
453 "%s Got TX IRQ but no more to do...\n",
454 __func__);
455 }
456 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
457 /* current frame is sent and is last,
458 * make sure to disable tx half
459 */
460 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
461 } else {
462 /* got IRQ which is not acked */
463 dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n",
464 __func__);
465 clr = pend;
466 }
467out:
468 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
469
470 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
471}
472
473static int xiic_bus_busy(struct xiic_i2c *i2c)
474{
475 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
476
477 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
478}
479
480static int xiic_busy(struct xiic_i2c *i2c)
481{
482 int tries = 3;
483 int err;
484
485 if (i2c->tx_msg)
486 return -EBUSY;
487
488 /* for instance if previous transfer was terminated due to TX error
489 * it might be that the bus is on it's way to become available
490 * give it at most 3 ms to wake
491 */
492 err = xiic_bus_busy(i2c);
493 while (err && tries--) {
494 mdelay(1);
495 err = xiic_bus_busy(i2c);
496 }
497
498 return err;
499}
500
501static void xiic_start_recv(struct xiic_i2c *i2c)
502{
503 u8 rx_watermark;
504 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
505
506 /* Clear and enable Rx full interrupt. */
507 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
508
509 /* we want to get all but last byte, because the TX_ERROR IRQ is used
510 * to inidicate error ACK on the address, and negative ack on the last
511 * received byte, so to not mix them receive all but last.
512 * In the case where there is only one byte to receive
513 * we can check if ERROR and RX full is set at the same time
514 */
515 rx_watermark = msg->len;
516 if (rx_watermark > IIC_RX_FIFO_DEPTH)
517 rx_watermark = IIC_RX_FIFO_DEPTH;
518 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
519
520 if (!(msg->flags & I2C_M_NOSTART))
521 /* write the address */
522 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
523 (msg->addr << 1) | XIIC_READ_OPERATION |
524 XIIC_TX_DYN_START_MASK);
525
526 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
527
528 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
529 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
530 if (i2c->nmsgs == 1)
531 /* very last, enable bus not busy as well */
532 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
533
534 /* the message is tx:ed */
535 i2c->tx_pos = msg->len;
536}
537
538static void xiic_start_send(struct xiic_i2c *i2c)
539{
540 struct i2c_msg *msg = i2c->tx_msg;
541
542 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
543
544 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d, "
545 "ISR: 0x%x, CR: 0x%x\n",
546 __func__, msg, msg->len, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
547 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
548
549 if (!(msg->flags & I2C_M_NOSTART)) {
550 /* write the address */
551 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION |
552 XIIC_TX_DYN_START_MASK;
553 if ((i2c->nmsgs == 1) && msg->len == 0)
554 /* no data and last message -> add STOP */
555 data |= XIIC_TX_DYN_STOP_MASK;
556
557 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
558 }
559
560 xiic_fill_tx_fifo(i2c);
561
562 /* Clear any pending Tx empty, Tx Error and then enable them. */
563 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
564 XIIC_INTR_BNB_MASK);
565}
566
567static irqreturn_t xiic_isr(int irq, void *dev_id)
568{
569 struct xiic_i2c *i2c = dev_id;
570
571 spin_lock(&i2c->lock);
572 /* disable interrupts globally */
573 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
574
575 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
576
577 xiic_process(i2c);
578
579 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
580 spin_unlock(&i2c->lock);
581
582 return IRQ_HANDLED;
583}
584
585static void __xiic_start_xfer(struct xiic_i2c *i2c)
586{
587 int first = 1;
588 int fifo_space = xiic_tx_fifo_space(i2c);
589 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
590 __func__, i2c->tx_msg, fifo_space);
591
592 if (!i2c->tx_msg)
593 return;
594
595 i2c->rx_pos = 0;
596 i2c->tx_pos = 0;
597 i2c->state = STATE_START;
598 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
599 if (!first) {
600 i2c->nmsgs--;
601 i2c->tx_msg++;
602 i2c->tx_pos = 0;
603 } else
604 first = 0;
605
606 if (i2c->tx_msg->flags & I2C_M_RD) {
607 /* we dont date putting several reads in the FIFO */
608 xiic_start_recv(i2c);
609 return;
610 } else {
611 xiic_start_send(i2c);
612 if (xiic_tx_space(i2c) != 0) {
613 /* the message could not be completely sent */
614 break;
615 }
616 }
617
618 fifo_space = xiic_tx_fifo_space(i2c);
619 }
620
621 /* there are more messages or the current one could not be completely
622 * put into the FIFO, also enable the half empty interrupt
623 */
624 if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
625 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
626
627}
628
629static void xiic_start_xfer(struct xiic_i2c *i2c)
630{
631 unsigned long flags;
632
633 spin_lock_irqsave(&i2c->lock, flags);
634 xiic_reinit(i2c);
635 /* disable interrupts globally */
636 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
637 spin_unlock_irqrestore(&i2c->lock, flags);
638
639 __xiic_start_xfer(i2c);
640 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
641}
642
643static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
644{
645 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
646 int err;
647
648 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
649 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
650
651 err = xiic_busy(i2c);
652 if (err)
653 return err;
654
655 i2c->tx_msg = msgs;
656 i2c->nmsgs = num;
657
658 xiic_start_xfer(i2c);
659
660 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
661 (i2c->state == STATE_DONE), HZ))
662 return (i2c->state == STATE_DONE) ? num : -EIO;
663 else {
664 i2c->tx_msg = NULL;
665 i2c->rx_msg = NULL;
666 i2c->nmsgs = 0;
667 return -ETIMEDOUT;
668 }
669}
670
671static u32 xiic_func(struct i2c_adapter *adap)
672{
673 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
674}
675
676static const struct i2c_algorithm xiic_algorithm = {
677 .master_xfer = xiic_xfer,
678 .functionality = xiic_func,
679};
680
681static struct i2c_adapter xiic_adapter = {
682 .owner = THIS_MODULE,
683 .name = DRIVER_NAME,
684 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
685 .algo = &xiic_algorithm,
686};
687
688
689static int __devinit xiic_i2c_probe(struct platform_device *pdev)
690{
691 struct xiic_i2c *i2c;
692 struct xiic_i2c_platform_data *pdata;
693 struct resource *res;
694 int ret, irq;
695 u8 i;
696
697 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
698 if (!res)
699 goto resource_missing;
700
701 irq = platform_get_irq(pdev, 0);
702 if (irq < 0)
703 goto resource_missing;
704
705 pdata = (struct xiic_i2c_platform_data *) pdev->dev.platform_data;
706 if (!pdata)
707 return -EINVAL;
708
709 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
710 if (!i2c)
711 return -ENOMEM;
712
713 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
714 dev_err(&pdev->dev, "Memory region busy\n");
715 ret = -EBUSY;
716 goto request_mem_failed;
717 }
718
719 i2c->base = ioremap(res->start, resource_size(res));
720 if (!i2c->base) {
721 dev_err(&pdev->dev, "Unable to map registers\n");
722 ret = -EIO;
723 goto map_failed;
724 }
725
726 /* hook up driver to tree */
727 platform_set_drvdata(pdev, i2c);
728 i2c->adap = xiic_adapter;
729 i2c_set_adapdata(&i2c->adap, i2c);
730 i2c->adap.dev.parent = &pdev->dev;
731
732 xiic_reinit(i2c);
733
734 spin_lock_init(&i2c->lock);
735 init_waitqueue_head(&i2c->wait);
736 ret = request_irq(irq, xiic_isr, 0, pdev->name, i2c);
737 if (ret) {
738 dev_err(&pdev->dev, "Cannot claim IRQ\n");
739 goto request_irq_failed;
740 }
741
742 /* add i2c adapter to i2c tree */
743 ret = i2c_add_adapter(&i2c->adap);
744 if (ret) {
745 dev_err(&pdev->dev, "Failed to add adapter\n");
746 goto add_adapter_failed;
747 }
748
749 /* add in known devices to the bus */
750 for (i = 0; i < pdata->num_devices; i++)
751 i2c_new_device(&i2c->adap, pdata->devices + i);
752
753 return 0;
754
755add_adapter_failed:
756 free_irq(irq, i2c);
757request_irq_failed:
758 xiic_deinit(i2c);
759 iounmap(i2c->base);
760map_failed:
761 release_mem_region(res->start, resource_size(res));
762request_mem_failed:
763 kfree(i2c);
764
765 return ret;
766resource_missing:
767 dev_err(&pdev->dev, "IRQ or Memory resource is missing\n");
768 return -ENOENT;
769}
770
771static int __devexit xiic_i2c_remove(struct platform_device* pdev)
772{
773 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
774 struct resource *res;
775
776 /* remove adapter & data */
777 i2c_del_adapter(&i2c->adap);
778
779 xiic_deinit(i2c);
780
781 platform_set_drvdata(pdev, NULL);
782
783 free_irq(platform_get_irq(pdev, 0), i2c);
784
785 iounmap(i2c->base);
786
787 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
788 if (res)
789 release_mem_region(res->start, resource_size(res));
790
791 kfree(i2c);
792
793 return 0;
794}
795
796
797/* work with hotplug and coldplug */
798MODULE_ALIAS("platform:"DRIVER_NAME);
799
800static struct platform_driver xiic_i2c_driver = {
801 .probe = xiic_i2c_probe,
802 .remove = __devexit_p(xiic_i2c_remove),
803 .driver = {
804 .owner = THIS_MODULE,
805 .name = DRIVER_NAME,
806 },
807};
808
809static int __init xiic_i2c_init(void)
810{
811 return platform_driver_register(&xiic_i2c_driver);
812}
813
814static void __exit xiic_i2c_exit(void)
815{
816 platform_driver_unregister(&xiic_i2c_driver);
817}
818
819module_init(xiic_i2c_init);
820module_exit(xiic_i2c_exit);
821
822MODULE_AUTHOR("info@mocean-labs.com");
823MODULE_DESCRIPTION("Xilinx I2C bus driver");
824MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-27 07:23:59 -0500