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-rw-r--r--arch/arm/mach-tcc8k/Makefile6
-rw-r--r--arch/arm/mach-tcc8k/clock.c566
-rw-r--r--arch/arm/mach-tcc8k/common.h6
-rw-r--r--arch/arm/plat-tcc/Makefile2
-rw-r--r--arch/arm/plat-tcc/clock.c179
-rw-r--r--arch/arm/plat-tcc/include/mach/clkdev.h7
-rw-r--r--arch/arm/plat-tcc/include/mach/clock.h48
-rw-r--r--arch/arm/plat-tcc/include/mach/tcc8k-regs.h31
8 files changed, 834 insertions, 11 deletions
diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile
new file mode 100644
index 000000000000..805d850919eb
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for TCC8K boards and common files.
3#
4
5# Common support
6obj-y += clock.o
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
new file mode 100644
index 000000000000..a8982af15326
--- /dev/null
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -0,0 +1,566 @@
1/*
2 * Lowlevel clock handling for Telechips TCC8xxx SoCs
3 *
4 * Copyright (C) 2010 by Hans J. Koch <hjk@linutronix.de>
5 *
6 * Licensed under the terms of the GPL v2
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/err.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/spinlock.h>
15
16#include <asm/clkdev.h>
17
18#include <mach/clock.h>
19#include <mach/irqs.h>
20#include <mach/tcc8k-regs.h>
21
22#include "common.h"
23
24#define BCLKCTR0 (CKC_BASE + BCLKCTR0_OFFS)
25#define BCLKCTR1 (CKC_BASE + BCLKCTR1_OFFS)
26
27#define ACLKREF (CKC_BASE + ACLKREF_OFFS)
28#define ACLKUART0 (CKC_BASE + ACLKUART0_OFFS)
29#define ACLKUART1 (CKC_BASE + ACLKUART1_OFFS)
30#define ACLKUART2 (CKC_BASE + ACLKUART2_OFFS)
31#define ACLKUART3 (CKC_BASE + ACLKUART3_OFFS)
32#define ACLKUART4 (CKC_BASE + ACLKUART4_OFFS)
33#define ACLKI2C (CKC_BASE + ACLKI2C_OFFS)
34#define ACLKADC (CKC_BASE + ACLKADC_OFFS)
35#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
36#define ACLKLCD (CKC_BASE + ACLKLCD_OFFS)
37#define ACLKSDH0 (CKC_BASE + ACLKSDH0_OFFS)
38#define ACLKSDH1 (CKC_BASE + ACLKSDH1_OFFS)
39#define ACLKSPI0 (CKC_BASE + ACLKSPI0_OFFS)
40#define ACLKSPI1 (CKC_BASE + ACLKSPI1_OFFS)
41#define ACLKSPDIF (CKC_BASE + ACLKSPDIF_OFFS)
42#define ACLKC3DEC (CKC_BASE + ACLKC3DEC_OFFS)
43#define ACLKCAN0 (CKC_BASE + ACLKCAN0_OFFS)
44#define ACLKCAN1 (CKC_BASE + ACLKCAN1_OFFS)
45#define ACLKGSB0 (CKC_BASE + ACLKGSB0_OFFS)
46#define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS)
47#define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS)
48#define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS)
49#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
50#define ACLKTCT (CKC_BASE + ACLKTCT_OFFS)
51#define ACLKTCX (CKC_BASE + ACLKTCX_OFFS)
52#define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS)
53
54/* Crystal frequencies */
55static unsigned long xi_rate, xti_rate;
56
57static void __iomem *pll_cfg_addr(int pll)
58{
59 switch (pll) {
60 case 0: return (CKC_BASE + PLL0CFG_OFFS);
61 case 1: return (CKC_BASE + PLL1CFG_OFFS);
62 case 2: return (CKC_BASE + PLL2CFG_OFFS);
63 default:
64 BUG();
65 }
66}
67
68static int pll_enable(int pll, int enable)
69{
70 u32 reg;
71 void __iomem *addr = pll_cfg_addr(pll);
72
73 reg = __raw_readl(addr);
74 if (enable)
75 reg &= ~PLLxCFG_PD;
76 else
77 reg |= PLLxCFG_PD;
78
79 __raw_writel(reg, addr);
80 return 0;
81}
82
83static int xi_enable(int enable)
84{
85 u32 reg;
86
87 reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
88 if (enable)
89 reg |= CLKCTRL_XE;
90 else
91 reg &= ~CLKCTRL_XE;
92
93 __raw_writel(reg, CKC_BASE + CLKCTRL_OFFS);
94 return 0;
95}
96
97static int root_clk_enable(enum root_clks src)
98{
99 switch (src) {
100 case CLK_SRC_PLL0: return pll_enable(0, 1);
101 case CLK_SRC_PLL1: return pll_enable(1, 1);
102 case CLK_SRC_PLL2: return pll_enable(2, 1);
103 case CLK_SRC_XI: return xi_enable(1);
104 default:
105 BUG();
106 }
107 return 0;
108}
109
110static int root_clk_disable(enum root_clks root_src)
111{
112 switch (root_src) {
113 case CLK_SRC_PLL0: return pll_enable(0, 0);
114 case CLK_SRC_PLL1: return pll_enable(1, 0);
115 case CLK_SRC_PLL2: return pll_enable(2, 0);
116 case CLK_SRC_XI: return xi_enable(0);
117 default:
118 BUG();
119 }
120 return 0;
121}
122
123static int enable_clk(struct clk *clk)
124{
125 u32 reg;
126
127 if (clk->root_id != CLK_SRC_NOROOT)
128 return root_clk_enable(clk->root_id);
129
130 if (clk->aclkreg) {
131 reg = __raw_readl(clk->aclkreg);
132 reg |= ACLK_EN;
133 __raw_writel(reg, clk->aclkreg);
134 }
135 if (clk->bclkctr) {
136 reg = __raw_readl(clk->bclkctr);
137 reg |= 1 << clk->bclk_shift;
138 __raw_writel(reg, clk->bclkctr);
139 }
140 return 0;
141}
142
143static void disable_clk(struct clk *clk)
144{
145 u32 reg;
146
147 if (clk->root_id != CLK_SRC_NOROOT) {
148 root_clk_disable(clk->root_id);
149 return;
150 }
151
152 if (clk->bclkctr) {
153 reg = __raw_readl(clk->bclkctr);
154 reg &= ~(1 << clk->bclk_shift);
155 __raw_writel(reg, clk->bclkctr);
156 }
157 if (clk->aclkreg) {
158 reg = __raw_readl(clk->aclkreg);
159 reg &= ~ACLK_EN;
160 __raw_writel(reg, clk->aclkreg);
161 }
162}
163
164static unsigned long get_rate_pll(int pll)
165{
166 u32 reg;
167 unsigned long s, m, p;
168 void __iomem *addr = pll_cfg_addr(pll);
169
170 reg = __raw_readl(addr);
171 s = (reg >> 16) & 0x07;
172 m = (reg >> 8) & 0xff;
173 p = reg & 0x3f;
174
175 return (m * xi_rate) / (p * (1 << s));
176}
177
178static unsigned long get_rate_pll_div(int pll)
179{
180 u32 reg;
181 unsigned long div = 0;
182 void __iomem *addr;
183
184 switch (pll) {
185 case 0:
186 addr = CKC_BASE + CLKDIVC0_OFFS;
187 reg = __raw_readl(addr);
188 if (reg & CLKDIVC0_P0E)
189 div = (reg >> 24) & 0x3f;
190 break;
191 case 1:
192 addr = CKC_BASE + CLKDIVC0_OFFS;
193 reg = __raw_readl(addr);
194 if (reg & CLKDIVC0_P1E)
195 div = (reg >> 16) & 0x3f;
196 break;
197 case 2:
198 addr = CKC_BASE + CLKDIVC1_OFFS;
199 reg = __raw_readl(addr);
200 if (reg & CLKDIVC1_P2E)
201 div = __raw_readl(addr) & 0x3f;
202 break;
203 }
204 return get_rate_pll(pll) / (div + 1);
205}
206
207static unsigned long get_rate_xi_div(void)
208{
209 unsigned long div = 0;
210 u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
211
212 if (reg & CLKDIVC0_XE)
213 div = (reg >> 8) & 0x3f;
214
215 return xi_rate / (div + 1);
216}
217
218static unsigned long get_rate_xti_div(void)
219{
220 unsigned long div = 0;
221 u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
222
223 if (reg & CLKDIVC0_XTE)
224 div = reg & 0x3f;
225
226 return xti_rate / (div + 1);
227}
228
229static unsigned long root_clk_get_rate(enum root_clks src)
230{
231 switch (src) {
232 case CLK_SRC_PLL0: return get_rate_pll(0);
233 case CLK_SRC_PLL1: return get_rate_pll(1);
234 case CLK_SRC_PLL2: return get_rate_pll(2);
235 case CLK_SRC_PLL0DIV: return get_rate_pll_div(0);
236 case CLK_SRC_PLL1DIV: return get_rate_pll_div(1);
237 case CLK_SRC_PLL2DIV: return get_rate_pll_div(2);
238 case CLK_SRC_XI: return xi_rate;
239 case CLK_SRC_XTI: return xti_rate;
240 case CLK_SRC_XIDIV: return get_rate_xi_div();
241 case CLK_SRC_XTIDIV: return get_rate_xti_div();
242 default: return 0;
243 }
244}
245
246static unsigned long aclk_get_rate(struct clk *clk)
247{
248 u32 reg;
249 unsigned long div;
250 unsigned int src;
251
252 reg = __raw_readl(clk->aclkreg);
253 div = reg & 0x0fff;
254 src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK;
255 return root_clk_get_rate(src) / (div + 1);
256}
257
258static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
259{
260 unsigned long div, src, freq, r1, r2;
261
262 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
263 src &= CLK_SRC_MASK;
264 freq = root_clk_get_rate(src);
265 div = freq / rate + 1;
266 r1 = freq / div;
267 r2 = freq / (div + 1);
268 if (r2 >= rate)
269 return div + 1;
270 if ((rate - r2) < (r1 - rate))
271 return div + 1;
272
273 return div;
274}
275
276static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate)
277{
278 unsigned int src;
279
280 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
281 src &= CLK_SRC_MASK;
282
283 return root_clk_get_rate(src) / aclk_best_div(clk, rate);
284}
285
286static int aclk_set_rate(struct clk *clk, unsigned long rate)
287{
288 u32 reg;
289
290 reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
291 reg |= aclk_best_div(clk, rate);
292 return 0;
293}
294
295static unsigned long get_rate_sys(struct clk *clk)
296{
297 unsigned int src;
298
299 src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
300 return root_clk_get_rate(src);
301}
302
303static unsigned long get_rate_bus(struct clk *clk)
304{
305 unsigned int div;
306
307 div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
308 return get_rate_sys(clk) / (div + 1);
309}
310
311static unsigned long get_rate_cpu(struct clk *clk)
312{
313 unsigned int reg, div, fsys, fbus;
314
315 fbus = get_rate_bus(clk);
316 reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
317 if (reg & (1 << 29))
318 return fbus;
319 fsys = get_rate_sys(clk);
320 div = (reg >> 16) & 0x0f;
321 return fbus + ((fsys - fbus) * (div + 1)) / 16;
322}
323
324static unsigned long get_rate_root(struct clk *clk)
325{
326 return root_clk_get_rate(clk->root_id);
327}
328
329static int aclk_set_parent(struct clk *clock, struct clk *parent)
330{
331 u32 reg;
332
333 if (clock->parent == parent)
334 return 0;
335
336 clock->parent = parent;
337
338 if (!parent)
339 return 0;
340
341 if (parent->root_id == CLK_SRC_NOROOT)
342 return 0;
343 reg = __raw_readl(clock->aclkreg);
344 reg &= ~ACLK_SEL_MASK;
345 reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK;
346 __raw_writel(reg, clock->aclkreg);
347
348 return 0;
349}
350
351#define DEFINE_ROOT_CLOCK(name, ri, p) \
352 static struct clk name = { \
353 .root_id = ri, \
354 .get_rate = get_rate_root, \
355 .enable = enable_clk, \
356 .disable = disable_clk, \
357 .parent = p, \
358 };
359
360#define DEFINE_SPECIAL_CLOCK(name, gr, p) \
361 static struct clk name = { \
362 .root_id = CLK_SRC_NOROOT, \
363 .get_rate = gr, \
364 .parent = p, \
365 };
366
367#define DEFINE_ACLOCK(name, bc, bs, ar) \
368 static struct clk name = { \
369 .root_id = CLK_SRC_NOROOT, \
370 .bclkctr = bc, \
371 .bclk_shift = bs, \
372 .aclkreg = ar, \
373 .get_rate = aclk_get_rate, \
374 .set_rate = aclk_set_rate, \
375 .round_rate = aclk_round_rate, \
376 .enable = enable_clk, \
377 .disable = disable_clk, \
378 .set_parent = aclk_set_parent, \
379 };
380
381#define DEFINE_BCLOCK(name, bc, bs, gr, p) \
382 static struct clk name = { \
383 .root_id = CLK_SRC_NOROOT, \
384 .bclkctr = bc, \
385 .bclk_shift = bs, \
386 .get_rate = gr, \
387 .enable = enable_clk, \
388 .disable = disable_clk, \
389 .parent = p, \
390 };
391
392DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL)
393DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL)
394DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi)
395DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti)
396DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi)
397DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi)
398DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi)
399DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0)
400DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1)
401DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2)
402
403/* The following 3 clocks are special and are initialized explicitly later */
404DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL)
405DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys)
406DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys)
407
408DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT)
409DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX)
410DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ)
411DEFINE_ACLOCK(ref, NULL, 0, ACLKREF)
412DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0)
413DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1)
414DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2)
415DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3)
416DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4)
417DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C)
418DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC)
419DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH)
420DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD)
421DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0)
422DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1)
423DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0)
424DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1)
425DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF)
426DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC)
427DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0)
428DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1)
429DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0)
430DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1)
431DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2)
432DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3)
433DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH)
434
435DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL)
436DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL)
437DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL)
438DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL)
439DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL)
440DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL)
441DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL)
442DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL)
443DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL)
444DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL)
445DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL)
446DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL)
447DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL)
448DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL)
449DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL)
450DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL)
451DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL)
452DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL)
453DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL)
454DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL)
455DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL)
456DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL)
457
458#define _REGISTER_CLOCK(d, n, c) \
459 { \
460 .dev_id = d, \
461 .con_id = n, \
462 .clk = &c, \
463 },
464
465static struct clk_lookup lookups[] = {
466 _REGISTER_CLOCK(NULL, "bus", bus)
467 _REGISTER_CLOCK(NULL, "cpu", cpu)
468 _REGISTER_CLOCK(NULL, "tct", tct)
469 _REGISTER_CLOCK(NULL, "tcx", tcx)
470 _REGISTER_CLOCK(NULL, "tcz", tcz)
471 _REGISTER_CLOCK(NULL, "ref", ref)
472 _REGISTER_CLOCK(NULL, "dai0", dai0)
473 _REGISTER_CLOCK(NULL, "pic", pic)
474 _REGISTER_CLOCK(NULL, "tc", tc)
475 _REGISTER_CLOCK(NULL, "gpio", gpio)
476 _REGISTER_CLOCK(NULL, "usbd", usbd)
477 _REGISTER_CLOCK("tcc-uart.0", NULL, uart0)
478 _REGISTER_CLOCK("tcc-uart.2", NULL, uart2)
479 _REGISTER_CLOCK("tcc-i2c", NULL, i2c)
480 _REGISTER_CLOCK("tcc-uart.3", NULL, uart3)
481 _REGISTER_CLOCK(NULL, "ecc", ecc)
482 _REGISTER_CLOCK(NULL, "adc", adc)
483 _REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0)
484 _REGISTER_CLOCK(NULL, "gdma0", gdma0)
485 _REGISTER_CLOCK(NULL, "lcd", lcd)
486 _REGISTER_CLOCK(NULL, "rtc", rtc)
487 _REGISTER_CLOCK(NULL, "nfc", nfc)
488 _REGISTER_CLOCK("tcc-mmc.0", NULL, sd0)
489 _REGISTER_CLOCK(NULL, "g2d", g2d)
490 _REGISTER_CLOCK(NULL, "gdma1", gdma1)
491 _REGISTER_CLOCK("tcc-uart.1", NULL, uart1)
492 _REGISTER_CLOCK("tcc-spi.0", NULL, spi0)
493 _REGISTER_CLOCK(NULL, "mscl", mscl)
494 _REGISTER_CLOCK("tcc-spi.1", NULL, spi1)
495 _REGISTER_CLOCK(NULL, "bdma", bdma)
496 _REGISTER_CLOCK(NULL, "adma0", adma0)
497 _REGISTER_CLOCK(NULL, "spdif", spdif)
498 _REGISTER_CLOCK(NULL, "scfg", scfg)
499 _REGISTER_CLOCK(NULL, "cid", cid)
500 _REGISTER_CLOCK("tcc-mmc.1", NULL, sd1)
501 _REGISTER_CLOCK("tcc-uart.4", NULL, uart4)
502 _REGISTER_CLOCK(NULL, "dai1", dai1)
503 _REGISTER_CLOCK(NULL, "adma1", adma1)
504 _REGISTER_CLOCK(NULL, "c3dec", c3dec)
505 _REGISTER_CLOCK("tcc-can.0", NULL, can0)
506 _REGISTER_CLOCK("tcc-can.1", NULL, can1)
507 _REGISTER_CLOCK(NULL, "gps", gps)
508 _REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0)
509 _REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1)
510 _REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2)
511 _REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3)
512 _REGISTER_CLOCK(NULL, "gdma2", gdma2)
513 _REGISTER_CLOCK(NULL, "gdma3", gdma3)
514 _REGISTER_CLOCK(NULL, "ddrc", ddrc)
515 _REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1)
516};
517
518static struct clk *root_clk_by_index(enum root_clks src)
519{
520 switch (src) {
521 case CLK_SRC_PLL0: return &pll0;
522 case CLK_SRC_PLL1: return &pll1;
523 case CLK_SRC_PLL2: return &pll2;
524 case CLK_SRC_PLL0DIV: return &pll0div;
525 case CLK_SRC_PLL1DIV: return &pll1div;
526 case CLK_SRC_PLL2DIV: return &pll2div;
527 case CLK_SRC_XI: return &xi;
528 case CLK_SRC_XTI: return &xti;
529 case CLK_SRC_XIDIV: return &xidiv;
530 case CLK_SRC_XTIDIV: return &xtidiv;
531 default: return NULL;
532 }
533}
534
535static void find_aclk_parent(struct clk *clk)
536{
537 unsigned int src;
538 struct clk *clock;
539
540 if (!clk->aclkreg)
541 return;
542
543 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
544 src &= CLK_SRC_MASK;
545
546 clock = root_clk_by_index(src);
547 if (!clock)
548 return;
549
550 clk->parent = clock;
551 clk->set_parent = aclk_set_parent;
552}
553
554void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq)
555{
556 int i;
557
558 xi_rate = xi_freq;
559 xti_rate = xti_freq;
560
561 /* fixup parents and add the clock */
562 for (i = 0; i < ARRAY_SIZE(lookups); i++) {
563 find_aclk_parent(lookups[i].clk);
564 clkdev_add(&lookups[i]);
565 }
566}
diff --git a/arch/arm/mach-tcc8k/common.h b/arch/arm/mach-tcc8k/common.h
new file mode 100644
index 000000000000..e2c902c1639c
--- /dev/null
+++ b/arch/arm/mach-tcc8k/common.h
@@ -0,0 +1,6 @@
1#ifndef MACH_TCC8K_COMMON_H
2#define MACH_TCC8K_COMMON_H
3
4extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq);
5
6#endif
diff --git a/arch/arm/plat-tcc/Makefile b/arch/arm/plat-tcc/Makefile
index 3f2e4fe70d5a..eceabc869b8f 100644
--- a/arch/arm/plat-tcc/Makefile
+++ b/arch/arm/plat-tcc/Makefile
@@ -1,3 +1,3 @@
1# "Telechips Platform Common Modules" 1# "Telechips Platform Common Modules"
2 2
3obj-y := system.o 3obj-y := clock.o system.o
diff --git a/arch/arm/plat-tcc/clock.c b/arch/arm/plat-tcc/clock.c
new file mode 100644
index 000000000000..f3ced10d5271
--- /dev/null
+++ b/arch/arm/plat-tcc/clock.c
@@ -0,0 +1,179 @@
1/*
2 * Clock framework for Telechips SoCs
3 * Based on arch/arm/plat-mxc/clock.c
4 *
5 * Copyright (C) 2004 - 2005 Nokia corporation
6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
8 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
9 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
10 * Copyright 2010 Hans J. Koch, hjk@linutronix.de
11 *
12 * Licensed under the terms of the GPL v2.
13 */
14
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/errno.h>
18#include <linux/module.h>
19#include <linux/mutex.h>
20#include <linux/string.h>
21
22#include <mach/clock.h>
23#include <mach/hardware.h>
24
25static DEFINE_MUTEX(clocks_mutex);
26
27/*-------------------------------------------------------------------------
28 * Standard clock functions defined in include/linux/clk.h
29 *-------------------------------------------------------------------------*/
30
31static void __clk_disable(struct clk *clk)
32{
33 BUG_ON(clk->refcount == 0);
34
35 if (!(--clk->refcount) && clk->disable) {
36 /* Unconditionally disable the clock in hardware */
37 clk->disable(clk);
38 /* recursively disable parents */
39 if (clk->parent)
40 __clk_disable(clk->parent);
41 }
42}
43
44static int __clk_enable(struct clk *clk)
45{
46 int ret = 0;
47
48 if (clk->refcount++ == 0 && clk->enable) {
49 if (clk->parent)
50 ret = __clk_enable(clk->parent);
51 if (ret)
52 return ret;
53 else
54 return clk->enable(clk);
55 }
56
57 return 0;
58}
59
60/* This function increments the reference count on the clock and enables the
61 * clock if not already enabled. The parent clock tree is recursively enabled
62 */
63int clk_enable(struct clk *clk)
64{
65 int ret = 0;
66
67 if (!clk)
68 return -EINVAL;
69
70 mutex_lock(&clocks_mutex);
71 ret = __clk_enable(clk);
72 mutex_unlock(&clocks_mutex);
73
74 return ret;
75}
76EXPORT_SYMBOL_GPL(clk_enable);
77
78/* This function decrements the reference count on the clock and disables
79 * the clock when reference count is 0. The parent clock tree is
80 * recursively disabled
81 */
82void clk_disable(struct clk *clk)
83{
84 if (!clk)
85 return;
86
87 mutex_lock(&clocks_mutex);
88 __clk_disable(clk);
89 mutex_unlock(&clocks_mutex);
90}
91EXPORT_SYMBOL_GPL(clk_disable);
92
93/* Retrieve the *current* clock rate. If the clock itself
94 * does not provide a special calculation routine, ask
95 * its parent and so on, until one is able to return
96 * a valid clock rate
97 */
98unsigned long clk_get_rate(struct clk *clk)
99{
100 if (!clk)
101 return 0UL;
102
103 if (clk->get_rate)
104 return clk->get_rate(clk);
105
106 return clk_get_rate(clk->parent);
107}
108EXPORT_SYMBOL_GPL(clk_get_rate);
109
110/* Round the requested clock rate to the nearest supported
111 * rate that is less than or equal to the requested rate.
112 * This is dependent on the clock's current parent.
113 */
114long clk_round_rate(struct clk *clk, unsigned long rate)
115{
116 if (!clk)
117 return 0;
118 if (!clk->round_rate)
119 return 0;
120
121 return clk->round_rate(clk, rate);
122}
123EXPORT_SYMBOL_GPL(clk_round_rate);
124
125/* Set the clock to the requested clock rate. The rate must
126 * match a supported rate exactly based on what clk_round_rate returns
127 */
128int clk_set_rate(struct clk *clk, unsigned long rate)
129{
130 int ret = -EINVAL;
131
132 if (!clk)
133 return ret;
134 if (!clk->set_rate || !rate)
135 return ret;
136
137 mutex_lock(&clocks_mutex);
138 ret = clk->set_rate(clk, rate);
139 mutex_unlock(&clocks_mutex);
140
141 return ret;
142}
143EXPORT_SYMBOL_GPL(clk_set_rate);
144
145/* Set the clock's parent to another clock source */
146int clk_set_parent(struct clk *clk, struct clk *parent)
147{
148 struct clk *old;
149 int ret = -EINVAL;
150
151 if (!clk)
152 return ret;
153 if (!clk->set_parent || !parent)
154 return ret;
155
156 mutex_lock(&clocks_mutex);
157 old = clk->parent;
158 if (clk->refcount)
159 __clk_enable(parent);
160 ret = clk->set_parent(clk, parent);
161 if (ret)
162 old = parent;
163 if (clk->refcount)
164 __clk_disable(old);
165 mutex_unlock(&clocks_mutex);
166
167 return ret;
168}
169EXPORT_SYMBOL_GPL(clk_set_parent);
170
171/* Retrieve the clock's parent clock source */
172struct clk *clk_get_parent(struct clk *clk)
173{
174 if (!clk)
175 return NULL;
176
177 return clk->parent;
178}
179EXPORT_SYMBOL_GPL(clk_get_parent);
diff --git a/arch/arm/plat-tcc/include/mach/clkdev.h b/arch/arm/plat-tcc/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do { } while (0)
6
7#endif
diff --git a/arch/arm/plat-tcc/include/mach/clock.h b/arch/arm/plat-tcc/include/mach/clock.h
new file mode 100644
index 000000000000..a12f58ad71a8
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clock.h
@@ -0,0 +1,48 @@
1/*
2 * Low level clock header file for Telechips TCC architecture
3 * (C) 2010 Hans J. Koch <hjk@linutronix.de>
4 *
5 * Licensed under the GPL v2.
6 */
7
8#ifndef __ASM_ARCH_TCC_CLOCK_H__
9#define __ASM_ARCH_TCC_CLOCK_H__
10
11#ifndef __ASSEMBLY__
12
13struct clk {
14 struct clk *parent;
15 /* id number of a root clock, 0 for normal clocks */
16 int root_id;
17 /* Reference count of clock enable/disable */
18 int refcount;
19 /* Address of associated BCLKCTRx register. Must be set. */
20 void __iomem *bclkctr;
21 /* Bit position for BCLKCTRx. Must be set. */
22 int bclk_shift;
23 /* Address of ACLKxxx register, if any. */
24 void __iomem *aclkreg;
25 /* get the current clock rate (always a fresh value) */
26 unsigned long (*get_rate) (struct clk *);
27 /* Function ptr to set the clock to a new rate. The rate must match a
28 supported rate returned from round_rate. Leave blank if clock is not
29 programmable */
30 int (*set_rate) (struct clk *, unsigned long);
31 /* Function ptr to round the requested clock rate to the nearest
32 supported rate that is less than or equal to the requested rate. */
33 unsigned long (*round_rate) (struct clk *, unsigned long);
34 /* Function ptr to enable the clock. Leave blank if clock can not
35 be gated. */
36 int (*enable) (struct clk *);
37 /* Function ptr to disable the clock. Leave blank if clock can not
38 be gated. */
39 void (*disable) (struct clk *);
40 /* Function ptr to set the parent clock of the clock. */
41 int (*set_parent) (struct clk *, struct clk *);
42};
43
44int clk_register(struct clk *clk);
45void clk_unregister(struct clk *clk);
46
47#endif /* __ASSEMBLY__ */
48#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
index f3243ebea463..1d9428295332 100644
--- a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
+++ b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
@@ -30,13 +30,13 @@
30#define EXT_MEM_CTRL_BASE 0xf0000000 30#define EXT_MEM_CTRL_BASE 0xf0000000
31#define EXT_MEM_CTRL_SIZE SZ_4K 31#define EXT_MEM_CTRL_SIZE SZ_4K
32 32
33#define CS1_BASE_VIRT 0xf7000000 33#define CS1_BASE_VIRT (void __iomem *)0xf7000000
34#define AHB_PERI_BASE_VIRT 0xf4000000 34#define AHB_PERI_BASE_VIRT (void __iomem *)0xf4000000
35#define APB0_PERI_BASE_VIRT 0xf1000000 35#define APB0_PERI_BASE_VIRT (void __iomem *)0xf1000000
36#define APB1_PERI_BASE_VIRT 0xf2000000 36#define APB1_PERI_BASE_VIRT (void __iomem *)0xf2000000
37#define EXT_MEM_CTRL_BASE_VIRT 0xf3000000 37#define EXT_MEM_CTRL_BASE_VIRT (void __iomem *)0xf3000000
38#define INT_SRAM_BASE_VIRT 0xf5000000 38#define INT_SRAM_BASE_VIRT (void __iomem *)0xf5000000
39#define DATA_TCM_BASE_VIRT 0xf6000000 39#define DATA_TCM_BASE_VIRT (void __iomem *)0xf6000000
40 40
41#define __REG(x) (*((volatile u32 *)(x))) 41#define __REG(x) (*((volatile u32 *)(x)))
42 42
@@ -649,8 +649,7 @@
649#define PMGPIO_APB_OFFS 0x800 649#define PMGPIO_APB_OFFS 0x800
650 650
651/* Clock controller registers */ 651/* Clock controller registers */
652#define CKC_BASE (APB1_PERI_BASE_VIRT + 0x6000) 652#define CKC_BASE ((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000))
653#define CKC_BASE_PHYS (APB1_PERI_BASE + 0x6000)
654 653
655#define CLKCTRL_OFFS 0x00 654#define CLKCTRL_OFFS 0x00
656#define PLL0CFG_OFFS 0x04 655#define PLL0CFG_OFFS 0x04
@@ -724,8 +723,20 @@
724/* SWRESET1 bits */ 723/* SWRESET1 bits */
725#define SWRESET1_USBH1 (1 << 20) 724#define SWRESET1_USBH1 (1 << 20)
726 725
727/* System clock sources */ 726/* System clock sources.
727 * Note: These are the clock sources that serve as parents for
728 * all other clocks. They have no parents themselves.
729 *
730 * These values are used for struct clk->root_id. All clocks
731 * that are not system clock sources have this value set to
732 * CLK_SRC_NOROOT.
733 * The values for system clocks start with CLK_SRC_PLL0 == 0
734 * because this gives us exactly the values needed for the lower
735 * 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is
736 * defined as -1 to not disturb the order.
737 */
728enum root_clks { 738enum root_clks {
739 CLK_SRC_NOROOT = -1,
729 CLK_SRC_PLL0 = 0, 740 CLK_SRC_PLL0 = 0,
730 CLK_SRC_PLL1, 741 CLK_SRC_PLL1,
731 CLK_SRC_PLL0DIV, 742 CLK_SRC_PLL0DIV,
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-23 02:45:40 -0500