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-rw-r--r--drivers/infiniband/hw/ipath/ipath_common.h616
-rw-r--r--drivers/infiniband/hw/ipath/ipath_debug.h96
-rw-r--r--drivers/infiniband/hw/ipath/ipath_kernel.h884
-rw-r--r--drivers/infiniband/hw/ipath/ipath_registers.h446
-rw-r--r--drivers/infiniband/hw/ipath/ips_common.h263
5 files changed, 2305 insertions, 0 deletions
diff --git a/drivers/infiniband/hw/ipath/ipath_common.h b/drivers/infiniband/hw/ipath/ipath_common.h
new file mode 100644
index 000000000000..48a55247b832
--- /dev/null
+++ b/drivers/infiniband/hw/ipath/ipath_common.h
@@ -0,0 +1,616 @@
1/*
2 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef _IPATH_COMMON_H
34#define _IPATH_COMMON_H
35
36/*
37 * This file contains defines, structures, etc. that are used
38 * to communicate between kernel and user code.
39 */
40
41/* This is the IEEE-assigned OUI for PathScale, Inc. */
42#define IPATH_SRC_OUI_1 0x00
43#define IPATH_SRC_OUI_2 0x11
44#define IPATH_SRC_OUI_3 0x75
45
46/* version of protocol header (known to chip also). In the long run,
47 * we should be able to generate and accept a range of version numbers;
48 * for now we only accept one, and it's compiled in.
49 */
50#define IPS_PROTO_VERSION 2
51
52/*
53 * These are compile time constants that you may want to enable or disable
54 * if you are trying to debug problems with code or performance.
55 * IPATH_VERBOSE_TRACING define as 1 if you want additional tracing in
56 * fastpath code
57 * IPATH_TRACE_REGWRITES define as 1 if you want register writes to be
58 * traced in faspath code
59 * _IPATH_TRACING define as 0 if you want to remove all tracing in a
60 * compilation unit
61 * _IPATH_DEBUGGING define as 0 if you want to remove debug prints
62 */
63
64/*
65 * The value in the BTH QP field that InfiniPath uses to differentiate
66 * an infinipath protocol IB packet vs standard IB transport
67 */
68#define IPATH_KD_QP 0x656b79
69
70/*
71 * valid states passed to ipath_set_linkstate() user call
72 */
73#define IPATH_IB_LINKDOWN 0
74#define IPATH_IB_LINKARM 1
75#define IPATH_IB_LINKACTIVE 2
76#define IPATH_IB_LINKINIT 3
77#define IPATH_IB_LINKDOWN_SLEEP 4
78#define IPATH_IB_LINKDOWN_DISABLE 5
79
80/*
81 * stats maintained by the driver. For now, at least, this is global
82 * to all minor devices.
83 */
84struct infinipath_stats {
85 /* number of interrupts taken */
86 __u64 sps_ints;
87 /* number of interrupts for errors */
88 __u64 sps_errints;
89 /* number of errors from chip (not incl. packet errors or CRC) */
90 __u64 sps_errs;
91 /* number of packet errors from chip other than CRC */
92 __u64 sps_pkterrs;
93 /* number of packets with CRC errors (ICRC and VCRC) */
94 __u64 sps_crcerrs;
95 /* number of hardware errors reported (parity, etc.) */
96 __u64 sps_hwerrs;
97 /* number of times IB link changed state unexpectedly */
98 __u64 sps_iblink;
99 /* no longer used; left for compatibility */
100 __u64 sps_unused3;
101 /* number of kernel (port0) packets received */
102 __u64 sps_port0pkts;
103 /* number of "ethernet" packets sent by driver */
104 __u64 sps_ether_spkts;
105 /* number of "ethernet" packets received by driver */
106 __u64 sps_ether_rpkts;
107 /* number of SMA packets sent by driver */
108 __u64 sps_sma_spkts;
109 /* number of SMA packets received by driver */
110 __u64 sps_sma_rpkts;
111 /* number of times all ports rcvhdrq was full and packet dropped */
112 __u64 sps_hdrqfull;
113 /* number of times all ports egrtid was full and packet dropped */
114 __u64 sps_etidfull;
115 /*
116 * number of times we tried to send from driver, but no pio buffers
117 * avail
118 */
119 __u64 sps_nopiobufs;
120 /* number of ports currently open */
121 __u64 sps_ports;
122 /* list of pkeys (other than default) accepted (0 means not set) */
123 __u16 sps_pkeys[4];
124 /* lids for up to 4 infinipaths, indexed by infinipath # */
125 __u16 sps_lid[4];
126 /* number of user ports per chip (not IB ports) */
127 __u32 sps_nports;
128 /* not our interrupt, or already handled */
129 __u32 sps_nullintr;
130 /* max number of packets handled per receive call */
131 __u32 sps_maxpkts_call;
132 /* avg number of packets handled per receive call */
133 __u32 sps_avgpkts_call;
134 /* total number of pages locked */
135 __u64 sps_pagelocks;
136 /* total number of pages unlocked */
137 __u64 sps_pageunlocks;
138 /*
139 * Number of packets dropped in kernel other than errors (ether
140 * packets if ipath not configured, sma/mad, etc.)
141 */
142 __u64 sps_krdrops;
143 /* mlids for up to 4 infinipaths, indexed by infinipath # */
144 __u16 sps_mlid[4];
145 /* pad for future growth */
146 __u64 __sps_pad[45];
147};
148
149/*
150 * These are the status bits readable (in ascii form, 64bit value)
151 * from the "status" sysfs file.
152 */
153#define IPATH_STATUS_INITTED 0x1 /* basic initialization done */
154#define IPATH_STATUS_DISABLED 0x2 /* hardware disabled */
155/* Device has been disabled via admin request */
156#define IPATH_STATUS_ADMIN_DISABLED 0x4
157#define IPATH_STATUS_OIB_SMA 0x8 /* ipath_mad kernel SMA running */
158#define IPATH_STATUS_SMA 0x10 /* user SMA running */
159/* Chip has been found and initted */
160#define IPATH_STATUS_CHIP_PRESENT 0x20
161/* IB link is at ACTIVE, usable for data traffic */
162#define IPATH_STATUS_IB_READY 0x40
163/* link is configured, LID, MTU, etc. have been set */
164#define IPATH_STATUS_IB_CONF 0x80
165/* no link established, probably no cable */
166#define IPATH_STATUS_IB_NOCABLE 0x100
167/* A Fatal hardware error has occurred. */
168#define IPATH_STATUS_HWERROR 0x200
169
170/*
171 * The list of usermode accessible registers. Also see Reg_* later in file.
172 */
173typedef enum _ipath_ureg {
174 /* (RO) DMA RcvHdr to be used next. */
175 ur_rcvhdrtail = 0,
176 /* (RW) RcvHdr entry to be processed next by host. */
177 ur_rcvhdrhead = 1,
178 /* (RO) Index of next Eager index to use. */
179 ur_rcvegrindextail = 2,
180 /* (RW) Eager TID to be processed next */
181 ur_rcvegrindexhead = 3,
182 /* For internal use only; max register number. */
183 _IPATH_UregMax
184} ipath_ureg;
185
186/* bit values for spi_runtime_flags */
187#define IPATH_RUNTIME_HT 0x1
188#define IPATH_RUNTIME_PCIE 0x2
189#define IPATH_RUNTIME_FORCE_WC_ORDER 0x4
190#define IPATH_RUNTIME_RCVHDR_COPY 0x8
191
192/*
193 * This structure is returned by ipath_userinit() immediately after
194 * open to get implementation-specific info, and info specific to this
195 * instance.
196 *
197 * This struct must have explict pad fields where type sizes
198 * may result in different alignments between 32 and 64 bit
199 * programs, since the 64 bit * bit kernel requires the user code
200 * to have matching offsets
201 */
202struct ipath_base_info {
203 /* version of hardware, for feature checking. */
204 __u32 spi_hw_version;
205 /* version of software, for feature checking. */
206 __u32 spi_sw_version;
207 /* InfiniPath port assigned, goes into sent packets */
208 __u32 spi_port;
209 /*
210 * IB MTU, packets IB data must be less than this.
211 * The MTU is in bytes, and will be a multiple of 4 bytes.
212 */
213 __u32 spi_mtu;
214 /*
215 * Size of a PIO buffer. Any given packet's total size must be less
216 * than this (in words). Included is the starting control word, so
217 * if 513 is returned, then total pkt size is 512 words or less.
218 */
219 __u32 spi_piosize;
220 /* size of the TID cache in infinipath, in entries */
221 __u32 spi_tidcnt;
222 /* size of the TID Eager list in infinipath, in entries */
223 __u32 spi_tidegrcnt;
224 /* size of a single receive header queue entry. */
225 __u32 spi_rcvhdrent_size;
226 /*
227 * Count of receive header queue entries allocated.
228 * This may be less than the spu_rcvhdrcnt passed in!.
229 */
230 __u32 spi_rcvhdr_cnt;
231
232 /* per-chip and other runtime features bitmap (IPATH_RUNTIME_*) */
233 __u32 spi_runtime_flags;
234
235 /* address where receive buffer queue is mapped into */
236 __u64 spi_rcvhdr_base;
237
238 /* user program. */
239
240 /* base address of eager TID receive buffers. */
241 __u64 spi_rcv_egrbufs;
242
243 /* Allocated by initialization code, not by protocol. */
244
245 /*
246 * Size of each TID buffer in host memory, starting at
247 * spi_rcv_egrbufs. The buffers are virtually contiguous.
248 */
249 __u32 spi_rcv_egrbufsize;
250 /*
251 * The special QP (queue pair) value that identifies an infinipath
252 * protocol packet from standard IB packets. More, probably much
253 * more, to be added.
254 */
255 __u32 spi_qpair;
256
257 /*
258 * User register base for init code, not to be used directly by
259 * protocol or applications.
260 */
261 __u64 __spi_uregbase;
262 /*
263 * Maximum buffer size in bytes that can be used in a single TID
264 * entry (assuming the buffer is aligned to this boundary). This is
265 * the minimum of what the hardware and software support Guaranteed
266 * to be a power of 2.
267 */
268 __u32 spi_tid_maxsize;
269 /*
270 * alignment of each pio send buffer (byte count
271 * to add to spi_piobufbase to get to second buffer)
272 */
273 __u32 spi_pioalign;
274 /*
275 * The index of the first pio buffer available to this process;
276 * needed to do lookup in spi_pioavailaddr; not added to
277 * spi_piobufbase.
278 */
279 __u32 spi_pioindex;
280 /* number of buffers mapped for this process */
281 __u32 spi_piocnt;
282
283 /*
284 * Base address of writeonly pio buffers for this process.
285 * Each buffer has spi_piosize words, and is aligned on spi_pioalign
286 * boundaries. spi_piocnt buffers are mapped from this address
287 */
288 __u64 spi_piobufbase;
289
290 /*
291 * Base address of readonly memory copy of the pioavail registers.
292 * There are 2 bits for each buffer.
293 */
294 __u64 spi_pioavailaddr;
295
296 /*
297 * Address where driver updates a copy of the interface and driver
298 * status (IPATH_STATUS_*) as a 64 bit value. It's followed by a
299 * string indicating hardware error, if there was one.
300 */
301 __u64 spi_status;
302
303 /* number of chip ports available to user processes */
304 __u32 spi_nports;
305 /* unit number of chip we are using */
306 __u32 spi_unit;
307 /* num bufs in each contiguous set */
308 __u32 spi_rcv_egrperchunk;
309 /* size in bytes of each contiguous set */
310 __u32 spi_rcv_egrchunksize;
311 /* total size of mmap to cover full rcvegrbuffers */
312 __u32 spi_rcv_egrbuftotlen;
313} __attribute__ ((aligned(8)));
314
315
316/*
317 * This version number is given to the driver by the user code during
318 * initialization in the spu_userversion field of ipath_user_info, so
319 * the driver can check for compatibility with user code.
320 *
321 * The major version changes when data structures
322 * change in an incompatible way. The driver must be the same or higher
323 * for initialization to succeed. In some cases, a higher version
324 * driver will not interoperate with older software, and initialization
325 * will return an error.
326 */
327#define IPATH_USER_SWMAJOR 1
328
329/*
330 * Minor version differences are always compatible
331 * a within a major version, however if if user software is larger
332 * than driver software, some new features and/or structure fields
333 * may not be implemented; the user code must deal with this if it
334 * cares, or it must abort after initialization reports the difference
335 */
336#define IPATH_USER_SWMINOR 2
337
338#define IPATH_USER_SWVERSION ((IPATH_USER_SWMAJOR<<16) | IPATH_USER_SWMINOR)
339
340#define IPATH_KERN_TYPE 0
341
342/*
343 * Similarly, this is the kernel version going back to the user. It's
344 * slightly different, in that we want to tell if the driver was built as
345 * part of a PathScale release, or from the driver from OpenIB, kernel.org,
346 * or a standard distribution, for support reasons. The high bit is 0 for
347 * non-PathScale, and 1 for PathScale-built/supplied.
348 *
349 * It's returned by the driver to the user code during initialization in the
350 * spi_sw_version field of ipath_base_info, so the user code can in turn
351 * check for compatibility with the kernel.
352*/
353#define IPATH_KERN_SWVERSION ((IPATH_KERN_TYPE<<31) | IPATH_USER_SWVERSION)
354
355/*
356 * This structure is passed to ipath_userinit() to tell the driver where
357 * user code buffers are, sizes, etc. The offsets and sizes of the
358 * fields must remain unchanged, for binary compatibility. It can
359 * be extended, if userversion is changed so user code can tell, if needed
360 */
361struct ipath_user_info {
362 /*
363 * version of user software, to detect compatibility issues.
364 * Should be set to IPATH_USER_SWVERSION.
365 */
366 __u32 spu_userversion;
367
368 /* desired number of receive header queue entries */
369 __u32 spu_rcvhdrcnt;
370
371 /* size of struct base_info to write to */
372 __u32 spu_base_info_size;
373
374 /*
375 * number of words in KD protocol header
376 * This tells InfiniPath how many words to copy to rcvhdrq. If 0,
377 * kernel uses a default. Once set, attempts to set any other value
378 * are an error (EAGAIN) until driver is reloaded.
379 */
380 __u32 spu_rcvhdrsize;
381
382 /*
383 * cache line aligned (64 byte) user address to
384 * which the rcvhdrtail register will be written by infinipath
385 * whenever it changes, so that no chip registers are read in
386 * the performance path.
387 */
388 __u64 spu_rcvhdraddr;
389
390 /*
391 * address of struct base_info to write to
392 */
393 __u64 spu_base_info;
394
395} __attribute__ ((aligned(8)));
396
397/* User commands. */
398
399#define IPATH_CMD_MIN 16
400
401#define IPATH_CMD_USER_INIT 16 /* set up userspace */
402#define IPATH_CMD_PORT_INFO 17 /* find out what resources we got */
403#define IPATH_CMD_RECV_CTRL 18 /* control receipt of packets */
404#define IPATH_CMD_TID_UPDATE 19 /* update expected TID entries */
405#define IPATH_CMD_TID_FREE 20 /* free expected TID entries */
406#define IPATH_CMD_SET_PART_KEY 21 /* add partition key */
407
408#define IPATH_CMD_MAX 21
409
410struct ipath_port_info {
411 __u32 num_active; /* number of active units */
412 __u32 unit; /* unit (chip) assigned to caller */
413 __u32 port; /* port on unit assigned to caller */
414};
415
416struct ipath_tid_info {
417 __u32 tidcnt;
418 /* make structure same size in 32 and 64 bit */
419 __u32 tid__unused;
420 /* virtual address of first page in transfer */
421 __u64 tidvaddr;
422 /* pointer (same size 32/64 bit) to __u16 tid array */
423 __u64 tidlist;
424
425 /*
426 * pointer (same size 32/64 bit) to bitmap of TIDs used
427 * for this call; checked for being large enough at open
428 */
429 __u64 tidmap;
430};
431
432struct ipath_cmd {
433 __u32 type; /* command type */
434 union {
435 struct ipath_tid_info tid_info;
436 struct ipath_user_info user_info;
437 /* address in userspace of struct ipath_port_info to
438 write result to */
439 __u64 port_info;
440 /* enable/disable receipt of packets */
441 __u32 recv_ctrl;
442 /* partition key to set */
443 __u16 part_key;
444 } cmd;
445};
446
447struct ipath_iovec {
448 /* Pointer to data, but same size 32 and 64 bit */
449 __u64 iov_base;
450
451 /*
452 * Length of data; don't need 64 bits, but want
453 * ipath_sendpkt to remain same size as before 32 bit changes, so...
454 */
455 __u64 iov_len;
456};
457
458/*
459 * Describes a single packet for send. Each packet can have one or more
460 * buffers, but the total length (exclusive of IB headers) must be less
461 * than the MTU, and if using the PIO method, entire packet length,
462 * including IB headers, must be less than the ipath_piosize value (words).
463 * Use of this necessitates including sys/uio.h
464 */
465struct __ipath_sendpkt {
466 __u32 sps_flags; /* flags for packet (TBD) */
467 __u32 sps_cnt; /* number of entries to use in sps_iov */
468 /* array of iov's describing packet. TEMPORARY */
469 struct ipath_iovec sps_iov[4];
470};
471
472/* Passed into SMA special file's ->read and ->write methods. */
473struct ipath_sma_pkt
474{
475 __u32 unit; /* unit on which to send packet */
476 __u64 data; /* address of payload in userspace */
477 __u32 len; /* length of payload */
478};
479
480/*
481 * Data layout in I2C flash (for GUID, etc.)
482 * All fields are little-endian binary unless otherwise stated
483 */
484#define IPATH_FLASH_VERSION 1
485struct ipath_flash {
486 /* flash layout version (IPATH_FLASH_VERSION) */
487 __u8 if_fversion;
488 /* checksum protecting if_length bytes */
489 __u8 if_csum;
490 /*
491 * valid length (in use, protected by if_csum), including
492 * if_fversion and if_sum themselves)
493 */
494 __u8 if_length;
495 /* the GUID, in network order */
496 __u8 if_guid[8];
497 /* number of GUIDs to use, starting from if_guid */
498 __u8 if_numguid;
499 /* the board serial number, in ASCII */
500 char if_serial[12];
501 /* board mfg date (YYYYMMDD ASCII) */
502 char if_mfgdate[8];
503 /* last board rework/test date (YYYYMMDD ASCII) */
504 char if_testdate[8];
505 /* logging of error counts, TBD */
506 __u8 if_errcntp[4];
507 /* powered on hours, updated at driver unload */
508 __u8 if_powerhour[2];
509 /* ASCII free-form comment field */
510 char if_comment[32];
511 /* 78 bytes used, min flash size is 128 bytes */
512 __u8 if_future[50];
513};
514
515/*
516 * These are the counters implemented in the chip, and are listed in order.
517 * The InterCaps naming is taken straight from the chip spec.
518 */
519struct infinipath_counters {
520 __u64 LBIntCnt;
521 __u64 LBFlowStallCnt;
522 __u64 Reserved1;
523 __u64 TxUnsupVLErrCnt;
524 __u64 TxDataPktCnt;
525 __u64 TxFlowPktCnt;
526 __u64 TxDwordCnt;
527 __u64 TxLenErrCnt;
528 __u64 TxMaxMinLenErrCnt;
529 __u64 TxUnderrunCnt;
530 __u64 TxFlowStallCnt;
531 __u64 TxDroppedPktCnt;
532 __u64 RxDroppedPktCnt;
533 __u64 RxDataPktCnt;
534 __u64 RxFlowPktCnt;
535 __u64 RxDwordCnt;
536 __u64 RxLenErrCnt;
537 __u64 RxMaxMinLenErrCnt;
538 __u64 RxICRCErrCnt;
539 __u64 RxVCRCErrCnt;
540 __u64 RxFlowCtrlErrCnt;
541 __u64 RxBadFormatCnt;
542 __u64 RxLinkProblemCnt;
543 __u64 RxEBPCnt;
544 __u64 RxLPCRCErrCnt;
545 __u64 RxBufOvflCnt;
546 __u64 RxTIDFullErrCnt;
547 __u64 RxTIDValidErrCnt;
548 __u64 RxPKeyMismatchCnt;
549 __u64 RxP0HdrEgrOvflCnt;
550 __u64 RxP1HdrEgrOvflCnt;
551 __u64 RxP2HdrEgrOvflCnt;
552 __u64 RxP3HdrEgrOvflCnt;
553 __u64 RxP4HdrEgrOvflCnt;
554 __u64 RxP5HdrEgrOvflCnt;
555 __u64 RxP6HdrEgrOvflCnt;
556 __u64 RxP7HdrEgrOvflCnt;
557 __u64 RxP8HdrEgrOvflCnt;
558 __u64 Reserved6;
559 __u64 Reserved7;
560 __u64 IBStatusChangeCnt;
561 __u64 IBLinkErrRecoveryCnt;
562 __u64 IBLinkDownedCnt;
563 __u64 IBSymbolErrCnt;
564};
565
566/*
567 * The next set of defines are for packet headers, and chip register
568 * and memory bits that are visible to and/or used by user-mode software
569 * The other bits that are used only by the driver or diags are in
570 * ipath_registers.h
571 */
572
573/* RcvHdrFlags bits */
574#define INFINIPATH_RHF_LENGTH_MASK 0x7FF
575#define INFINIPATH_RHF_LENGTH_SHIFT 0
576#define INFINIPATH_RHF_RCVTYPE_MASK 0x7
577#define INFINIPATH_RHF_RCVTYPE_SHIFT 11
578#define INFINIPATH_RHF_EGRINDEX_MASK 0x7FF
579#define INFINIPATH_RHF_EGRINDEX_SHIFT 16
580#define INFINIPATH_RHF_H_ICRCERR 0x80000000
581#define INFINIPATH_RHF_H_VCRCERR 0x40000000
582#define INFINIPATH_RHF_H_PARITYERR 0x20000000
583#define INFINIPATH_RHF_H_LENERR 0x10000000
584#define INFINIPATH_RHF_H_MTUERR 0x08000000
585#define INFINIPATH_RHF_H_IHDRERR 0x04000000
586#define INFINIPATH_RHF_H_TIDERR 0x02000000
587#define INFINIPATH_RHF_H_MKERR 0x01000000
588#define INFINIPATH_RHF_H_IBERR 0x00800000
589#define INFINIPATH_RHF_L_SWA 0x00008000
590#define INFINIPATH_RHF_L_SWB 0x00004000
591
592/* infinipath header fields */
593#define INFINIPATH_I_VERS_MASK 0xF
594#define INFINIPATH_I_VERS_SHIFT 28
595#define INFINIPATH_I_PORT_MASK 0xF
596#define INFINIPATH_I_PORT_SHIFT 24
597#define INFINIPATH_I_TID_MASK 0x7FF
598#define INFINIPATH_I_TID_SHIFT 13
599#define INFINIPATH_I_OFFSET_MASK 0x1FFF
600#define INFINIPATH_I_OFFSET_SHIFT 0
601
602/* K_PktFlags bits */
603#define INFINIPATH_KPF_INTR 0x1
604
605/* SendPIO per-buffer control */
606#define INFINIPATH_SP_LENGTHP1_MASK 0x3FF
607#define INFINIPATH_SP_LENGTHP1_SHIFT 0
608#define INFINIPATH_SP_INTR 0x80000000
609#define INFINIPATH_SP_TEST 0x40000000
610#define INFINIPATH_SP_TESTEBP 0x20000000
611
612/* SendPIOAvail bits */
613#define INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT 1
614#define INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT 0
615
616#endif /* _IPATH_COMMON_H */
diff --git a/drivers/infiniband/hw/ipath/ipath_debug.h b/drivers/infiniband/hw/ipath/ipath_debug.h
new file mode 100644
index 000000000000..593e28969c69
--- /dev/null
+++ b/drivers/infiniband/hw/ipath/ipath_debug.h
@@ -0,0 +1,96 @@
1/*
2 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef _IPATH_DEBUG_H
34#define _IPATH_DEBUG_H
35
36#ifndef _IPATH_DEBUGGING /* debugging enabled or not */
37#define _IPATH_DEBUGGING 1
38#endif
39
40#if _IPATH_DEBUGGING
41
42/*
43 * Mask values for debugging. The scheme allows us to compile out any
44 * of the debug tracing stuff, and if compiled in, to enable or disable
45 * dynamically. This can be set at modprobe time also:
46 * modprobe infinipath.ko infinipath_debug=7
47 */
48
49#define __IPATH_INFO 0x1 /* generic low verbosity stuff */
50#define __IPATH_DBG 0x2 /* generic debug */
51#define __IPATH_TRSAMPLE 0x8 /* generate trace buffer sample entries */
52/* leave some low verbosity spots open */
53#define __IPATH_VERBDBG 0x40 /* very verbose debug */
54#define __IPATH_PKTDBG 0x80 /* print packet data */
55/* print process startup (init)/exit messages */
56#define __IPATH_PROCDBG 0x100
57/* print mmap/nopage stuff, not using VDBG any more */
58#define __IPATH_MMDBG 0x200
59#define __IPATH_USER_SEND 0x1000 /* use user mode send */
60#define __IPATH_KERNEL_SEND 0x2000 /* use kernel mode send */
61#define __IPATH_EPKTDBG 0x4000 /* print ethernet packet data */
62#define __IPATH_SMADBG 0x8000 /* sma packet debug */
63#define __IPATH_IPATHDBG 0x10000 /* Ethernet (IPATH) general debug on */
64#define __IPATH_IPATHWARN 0x20000 /* Ethernet (IPATH) warnings on */
65#define __IPATH_IPATHERR 0x40000 /* Ethernet (IPATH) errors on */
66#define __IPATH_IPATHPD 0x80000 /* Ethernet (IPATH) packet dump on */
67#define __IPATH_IPATHTABLE 0x100000 /* Ethernet (IPATH) table dump on */
68
69#else /* _IPATH_DEBUGGING */
70
71/*
72 * define all of these even with debugging off, for the few places that do
73 * if(infinipath_debug & _IPATH_xyzzy), but in a way that will make the
74 * compiler eliminate the code
75 */
76
77#define __IPATH_INFO 0x0 /* generic low verbosity stuff */
78#define __IPATH_DBG 0x0 /* generic debug */
79#define __IPATH_TRSAMPLE 0x0 /* generate trace buffer sample entries */
80#define __IPATH_VERBDBG 0x0 /* very verbose debug */
81#define __IPATH_PKTDBG 0x0 /* print packet data */
82#define __IPATH_PROCDBG 0x0 /* print process startup (init)/exit messages */
83/* print mmap/nopage stuff, not using VDBG any more */
84#define __IPATH_MMDBG 0x0
85#define __IPATH_EPKTDBG 0x0 /* print ethernet packet data */
86#define __IPATH_SMADBG 0x0 /* print process startup (init)/exit messages */#define __IPATH_IPATHDBG 0x0 /* Ethernet (IPATH) table dump on */
87#define __IPATH_IPATHWARN 0x0 /* Ethernet (IPATH) warnings on */
88#define __IPATH_IPATHERR 0x0 /* Ethernet (IPATH) errors on */
89#define __IPATH_IPATHPD 0x0 /* Ethernet (IPATH) packet dump on */
90#define __IPATH_IPATHTABLE 0x0 /* Ethernet (IPATH) packet dump on */
91
92#endif /* _IPATH_DEBUGGING */
93
94#define __IPATH_VERBOSEDBG __IPATH_VERBDBG
95
96#endif /* _IPATH_DEBUG_H */
diff --git a/drivers/infiniband/hw/ipath/ipath_kernel.h b/drivers/infiniband/hw/ipath/ipath_kernel.h
new file mode 100644
index 000000000000..159d0aed31a5
--- /dev/null
+++ b/drivers/infiniband/hw/ipath/ipath_kernel.h
@@ -0,0 +1,884 @@
1#ifndef _IPATH_KERNEL_H
2#define _IPATH_KERNEL_H
3/*
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35/*
36 * This header file is the base header file for infinipath kernel code
37 * ipath_user.h serves a similar purpose for user code.
38 */
39
40#include <linux/interrupt.h>
41#include <asm/io.h>
42
43#include "ipath_common.h"
44#include "ipath_debug.h"
45#include "ipath_registers.h"
46
47/* only s/w major version of InfiniPath we can handle */
48#define IPATH_CHIP_VERS_MAJ 2U
49
50/* don't care about this except printing */
51#define IPATH_CHIP_VERS_MIN 0U
52
53/* temporary, maybe always */
54extern struct infinipath_stats ipath_stats;
55
56#define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ
57
58struct ipath_portdata {
59 void **port_rcvegrbuf;
60 dma_addr_t *port_rcvegrbuf_phys;
61 /* rcvhdrq base, needs mmap before useful */
62 void *port_rcvhdrq;
63 /* kernel virtual address where hdrqtail is updated */
64 u64 *port_rcvhdrtail_kvaddr;
65 /* page * used for uaddr */
66 struct page *port_rcvhdrtail_pagep;
67 /*
68 * temp buffer for expected send setup, allocated at open, instead
69 * of each setup call
70 */
71 void *port_tid_pg_list;
72 /* when waiting for rcv or pioavail */
73 wait_queue_head_t port_wait;
74 /*
75 * rcvegr bufs base, physical, must fit
76 * in 44 bits so 32 bit programs mmap64 44 bit works)
77 */
78 dma_addr_t port_rcvegr_phys;
79 /* mmap of hdrq, must fit in 44 bits */
80 dma_addr_t port_rcvhdrq_phys;
81 /*
82 * the actual user address that we ipath_mlock'ed, so we can
83 * ipath_munlock it at close
84 */
85 unsigned long port_rcvhdrtail_uaddr;
86 /*
87 * number of opens on this instance (0 or 1; ignoring forks, dup,
88 * etc. for now)
89 */
90 int port_cnt;
91 /*
92 * how much space to leave at start of eager TID entries for
93 * protocol use, on each TID
94 */
95 /* instead of calculating it */
96 unsigned port_port;
97 /* chip offset of PIO buffers for this port */
98 u32 port_piobufs;
99 /* how many alloc_pages() chunks in port_rcvegrbuf_pages */
100 u32 port_rcvegrbuf_chunks;
101 /* how many egrbufs per chunk */
102 u32 port_rcvegrbufs_perchunk;
103 /* order for port_rcvegrbuf_pages */
104 size_t port_rcvegrbuf_size;
105 /* rcvhdrq size (for freeing) */
106 size_t port_rcvhdrq_size;
107 /* next expected TID to check when looking for free */
108 u32 port_tidcursor;
109 /* next expected TID to check */
110 unsigned long port_flag;
111 /* WAIT_RCV that timed out, no interrupt */
112 u32 port_rcvwait_to;
113 /* WAIT_PIO that timed out, no interrupt */
114 u32 port_piowait_to;
115 /* WAIT_RCV already happened, no wait */
116 u32 port_rcvnowait;
117 /* WAIT_PIO already happened, no wait */
118 u32 port_pionowait;
119 /* total number of rcvhdrqfull errors */
120 u32 port_hdrqfull;
121 /* pid of process using this port */
122 pid_t port_pid;
123 /* same size as task_struct .comm[] */
124 char port_comm[16];
125 /* pkeys set by this use of this port */
126 u16 port_pkeys[4];
127 /* so file ops can get at unit */
128 struct ipath_devdata *port_dd;
129};
130
131struct sk_buff;
132
133/*
134 * control information for layered drivers
135 */
136struct _ipath_layer {
137 void *l_arg;
138};
139
140/* Verbs layer interface */
141struct _verbs_layer {
142 void *l_arg;
143 struct timer_list l_timer;
144};
145
146struct ipath_devdata {
147 struct list_head ipath_list;
148
149 struct ipath_kregs const *ipath_kregs;
150 struct ipath_cregs const *ipath_cregs;
151
152 /* mem-mapped pointer to base of chip regs */
153 u64 __iomem *ipath_kregbase;
154 /* end of mem-mapped chip space; range checking */
155 u64 __iomem *ipath_kregend;
156 /* physical address of chip for io_remap, etc. */
157 unsigned long ipath_physaddr;
158 /* base of memory alloced for ipath_kregbase, for free */
159 u64 *ipath_kregalloc;
160 /*
161 * version of kregbase that doesn't have high bits set (for 32 bit
162 * programs, so mmap64 44 bit works)
163 */
164 u64 __iomem *ipath_kregvirt;
165 /*
166 * virtual address where port0 rcvhdrqtail updated for this unit.
167 * only written to by the chip, not the driver.
168 */
169 volatile __le64 *ipath_hdrqtailptr;
170 dma_addr_t ipath_dma_addr;
171 /* ipath_cfgports pointers */
172 struct ipath_portdata **ipath_pd;
173 /* sk_buffs used by port 0 eager receive queue */
174 struct sk_buff **ipath_port0_skbs;
175 /* kvirt address of 1st 2k pio buffer */
176 void __iomem *ipath_pio2kbase;
177 /* kvirt address of 1st 4k pio buffer */
178 void __iomem *ipath_pio4kbase;
179 /*
180 * points to area where PIOavail registers will be DMA'ed.
181 * Has to be on a page of it's own, because the page will be
182 * mapped into user program space. This copy is *ONLY* ever
183 * written by DMA, not by the driver! Need a copy per device
184 * when we get to multiple devices
185 */
186 volatile __le64 *ipath_pioavailregs_dma;
187 /* physical address where updates occur */
188 dma_addr_t ipath_pioavailregs_phys;
189 struct _ipath_layer ipath_layer;
190 /* setup intr */
191 int (*ipath_f_intrsetup)(struct ipath_devdata *);
192 /* setup on-chip bus config */
193 int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *);
194 /* hard reset chip */
195 int (*ipath_f_reset)(struct ipath_devdata *);
196 int (*ipath_f_get_boardname)(struct ipath_devdata *, char *,
197 size_t);
198 void (*ipath_f_init_hwerrors)(struct ipath_devdata *);
199 void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *,
200 size_t);
201 void (*ipath_f_quiet_serdes)(struct ipath_devdata *);
202 int (*ipath_f_bringup_serdes)(struct ipath_devdata *);
203 int (*ipath_f_early_init)(struct ipath_devdata *);
204 void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned);
205 void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*,
206 u32, unsigned long);
207 void (*ipath_f_tidtemplate)(struct ipath_devdata *);
208 void (*ipath_f_cleanup)(struct ipath_devdata *);
209 void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64);
210 /* fill out chip-specific fields */
211 int (*ipath_f_get_base_info)(struct ipath_portdata *, void *);
212 struct _verbs_layer verbs_layer;
213 /* total dwords sent (summed from counter) */
214 u64 ipath_sword;
215 /* total dwords rcvd (summed from counter) */
216 u64 ipath_rword;
217 /* total packets sent (summed from counter) */
218 u64 ipath_spkts;
219 /* total packets rcvd (summed from counter) */
220 u64 ipath_rpkts;
221 /* ipath_statusp initially points to this. */
222 u64 _ipath_status;
223 /* GUID for this interface, in network order */
224 __be64 ipath_guid;
225 /*
226 * aggregrate of error bits reported since last cleared, for
227 * limiting of error reporting
228 */
229 ipath_err_t ipath_lasterror;
230 /*
231 * aggregrate of error bits reported since last cleared, for
232 * limiting of hwerror reporting
233 */
234 ipath_err_t ipath_lasthwerror;
235 /*
236 * errors masked because they occur too fast, also includes errors
237 * that are always ignored (ipath_ignorederrs)
238 */
239 ipath_err_t ipath_maskederrs;
240 /* time in jiffies at which to re-enable maskederrs */
241 unsigned long ipath_unmasktime;
242 /*
243 * errors always ignored (masked), at least for a given
244 * chip/device, because they are wrong or not useful
245 */
246 ipath_err_t ipath_ignorederrs;
247 /* count of egrfull errors, combined for all ports */
248 u64 ipath_last_tidfull;
249 /* for ipath_qcheck() */
250 u64 ipath_lastport0rcv_cnt;
251 /* template for writing TIDs */
252 u64 ipath_tidtemplate;
253 /* value to write to free TIDs */
254 u64 ipath_tidinvalid;
255 /* PE-800 rcv interrupt setup */
256 u64 ipath_rhdrhead_intr_off;
257
258 /* size of memory at ipath_kregbase */
259 u32 ipath_kregsize;
260 /* number of registers used for pioavail */
261 u32 ipath_pioavregs;
262 /* IPATH_POLL, etc. */
263 u32 ipath_flags;
264 /* ipath_flags sma is waiting for */
265 u32 ipath_sma_state_wanted;
266 /* last buffer for user use, first buf for kernel use is this
267 * index. */
268 u32 ipath_lastport_piobuf;
269 /* is a stats timer active */
270 u32 ipath_stats_timer_active;
271 /* dwords sent read from counter */
272 u32 ipath_lastsword;
273 /* dwords received read from counter */
274 u32 ipath_lastrword;
275 /* sent packets read from counter */
276 u32 ipath_lastspkts;
277 /* received packets read from counter */
278 u32 ipath_lastrpkts;
279 /* pio bufs allocated per port */
280 u32 ipath_pbufsport;
281 /*
282 * number of ports configured as max; zero is set to number chip
283 * supports, less gives more pio bufs/port, etc.
284 */
285 u32 ipath_cfgports;
286 /* port0 rcvhdrq head offset */
287 u32 ipath_port0head;
288 /* count of port 0 hdrqfull errors */
289 u32 ipath_p0_hdrqfull;
290
291 /*
292 * (*cfgports) used to suppress multiple instances of same
293 * port staying stuck at same point
294 */
295 u32 *ipath_lastrcvhdrqtails;
296 /*
297 * (*cfgports) used to suppress multiple instances of same
298 * port staying stuck at same point
299 */
300 u32 *ipath_lastegrheads;
301 /*
302 * index of last piobuffer we used. Speeds up searching, by
303 * starting at this point. Doesn't matter if multiple cpu's use and
304 * update, last updater is only write that matters. Whenever it
305 * wraps, we update shadow copies. Need a copy per device when we
306 * get to multiple devices
307 */
308 u32 ipath_lastpioindex;
309 /* max length of freezemsg */
310 u32 ipath_freezelen;
311 /*
312 * consecutive times we wanted a PIO buffer but were unable to
313 * get one
314 */
315 u32 ipath_consec_nopiobuf;
316 /*
317 * hint that we should update ipath_pioavailshadow before
318 * looking for a PIO buffer
319 */
320 u32 ipath_upd_pio_shadow;
321 /* so we can rewrite it after a chip reset */
322 u32 ipath_pcibar0;
323 /* so we can rewrite it after a chip reset */
324 u32 ipath_pcibar1;
325 /* sequential tries for SMA send and no bufs */
326 u32 ipath_nosma_bufs;
327 /* duration (seconds) ipath_nosma_bufs set */
328 u32 ipath_nosma_secs;
329
330 /* HT/PCI Vendor ID (here for NodeInfo) */
331 u16 ipath_vendorid;
332 /* HT/PCI Device ID (here for NodeInfo) */
333 u16 ipath_deviceid;
334 /* offset in HT config space of slave/primary interface block */
335 u8 ipath_ht_slave_off;
336 /* for write combining settings */
337 unsigned long ipath_wc_cookie;
338 /* ref count for each pkey */
339 atomic_t ipath_pkeyrefs[4];
340 /* shadow copy of all exptids physaddr; used only by funcsim */
341 u64 *ipath_tidsimshadow;
342 /* shadow copy of struct page *'s for exp tid pages */
343 struct page **ipath_pageshadow;
344 /* lock to workaround chip bug 9437 */
345 spinlock_t ipath_tid_lock;
346
347 /*
348 * IPATH_STATUS_*,
349 * this address is mapped readonly into user processes so they can
350 * get status cheaply, whenever they want.
351 */
352 u64 *ipath_statusp;
353 /* freeze msg if hw error put chip in freeze */
354 char *ipath_freezemsg;
355 /* pci access data structure */
356 struct pci_dev *pcidev;
357 struct cdev *cdev;
358 struct class_device *class_dev;
359 /* timer used to prevent stats overflow, error throttling, etc. */
360 struct timer_list ipath_stats_timer;
361 /* check for stale messages in rcv queue */
362 /* only allow one intr at a time. */
363 unsigned long ipath_rcv_pending;
364
365 /*
366 * Shadow copies of registers; size indicates read access size.
367 * Most of them are readonly, but some are write-only register,
368 * where we manipulate the bits in the shadow copy, and then write
369 * the shadow copy to infinipath.
370 *
371 * We deliberately make most of these 32 bits, since they have
372 * restricted range. For any that we read, we won't to generate 32
373 * bit accesses, since Opteron will generate 2 separate 32 bit HT
374 * transactions for a 64 bit read, and we want to avoid unnecessary
375 * HT transactions.
376 */
377
378 /* This is the 64 bit group */
379
380 /*
381 * shadow of pioavail, check to be sure it's large enough at
382 * init time.
383 */
384 unsigned long ipath_pioavailshadow[8];
385 /* shadow of kr_gpio_out, for rmw ops */
386 u64 ipath_gpio_out;
387 /* kr_revision shadow */
388 u64 ipath_revision;
389 /*
390 * shadow of ibcctrl, for interrupt handling of link changes,
391 * etc.
392 */
393 u64 ipath_ibcctrl;
394 /*
395 * last ibcstatus, to suppress "duplicate" status change messages,
396 * mostly from 2 to 3
397 */
398 u64 ipath_lastibcstat;
399 /* hwerrmask shadow */
400 ipath_err_t ipath_hwerrmask;
401 /* interrupt config reg shadow */
402 u64 ipath_intconfig;
403 /* kr_sendpiobufbase value */
404 u64 ipath_piobufbase;
405
406 /* these are the "32 bit" regs */
407
408 /*
409 * number of GUIDs in the flash for this interface; may need some
410 * rethinking for setting on other ifaces
411 */
412 u32 ipath_nguid;
413 /*
414 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
415 * all expect bit fields to be "unsigned long"
416 */
417 /* shadow kr_rcvctrl */
418 unsigned long ipath_rcvctrl;
419 /* shadow kr_sendctrl */
420 unsigned long ipath_sendctrl;
421
422 /* value we put in kr_rcvhdrcnt */
423 u32 ipath_rcvhdrcnt;
424 /* value we put in kr_rcvhdrsize */
425 u32 ipath_rcvhdrsize;
426 /* value we put in kr_rcvhdrentsize */
427 u32 ipath_rcvhdrentsize;
428 /* offset of last entry in rcvhdrq */
429 u32 ipath_hdrqlast;
430 /* kr_portcnt value */
431 u32 ipath_portcnt;
432 /* kr_pagealign value */
433 u32 ipath_palign;
434 /* number of "2KB" PIO buffers */
435 u32 ipath_piobcnt2k;
436 /* size in bytes of "2KB" PIO buffers */
437 u32 ipath_piosize2k;
438 /* number of "4KB" PIO buffers */
439 u32 ipath_piobcnt4k;
440 /* size in bytes of "4KB" PIO buffers */
441 u32 ipath_piosize4k;
442 /* kr_rcvegrbase value */
443 u32 ipath_rcvegrbase;
444 /* kr_rcvegrcnt value */
445 u32 ipath_rcvegrcnt;
446 /* kr_rcvtidbase value */
447 u32 ipath_rcvtidbase;
448 /* kr_rcvtidcnt value */
449 u32 ipath_rcvtidcnt;
450 /* kr_sendregbase */
451 u32 ipath_sregbase;
452 /* kr_userregbase */
453 u32 ipath_uregbase;
454 /* kr_counterregbase */
455 u32 ipath_cregbase;
456 /* shadow the control register contents */
457 u32 ipath_control;
458 /* shadow the gpio output contents */
459 u32 ipath_extctrl;
460 /* PCI revision register (HTC rev on FPGA) */
461 u32 ipath_pcirev;
462
463 /* chip address space used by 4k pio buffers */
464 u32 ipath_4kalign;
465 /* The MTU programmed for this unit */
466 u32 ipath_ibmtu;
467 /*
468 * The max size IB packet, included IB headers that we can send.
469 * Starts same as ipath_piosize, but is affected when ibmtu is
470 * changed, or by size of eager buffers
471 */
472 u32 ipath_ibmaxlen;
473 /*
474 * ibmaxlen at init time, limited by chip and by receive buffer
475 * size. Not changed after init.
476 */
477 u32 ipath_init_ibmaxlen;
478 /* size of each rcvegrbuffer */
479 u32 ipath_rcvegrbufsize;
480 /* width (2,4,8,16,32) from HT config reg */
481 u32 ipath_htwidth;
482 /* HT speed (200,400,800,1000) from HT config */
483 u32 ipath_htspeed;
484 /* ports waiting for PIOavail intr */
485 unsigned long ipath_portpiowait;
486 /*
487 * number of sequential ibcstatus change for polling active/quiet
488 * (i.e., link not coming up).
489 */
490 u32 ipath_ibpollcnt;
491 /* low and high portions of MSI capability/vector */
492 u32 ipath_msi_lo;
493 /* saved after PCIe init for restore after reset */
494 u32 ipath_msi_hi;
495 /* MSI data (vector) saved for restore */
496 u16 ipath_msi_data;
497 /* MLID programmed for this instance */
498 u16 ipath_mlid;
499 /* LID programmed for this instance */
500 u16 ipath_lid;
501 /* list of pkeys programmed; 0 if not set */
502 u16 ipath_pkeys[4];
503 /* ASCII serial number, from flash */
504 u8 ipath_serial[12];
505 /* human readable board version */
506 u8 ipath_boardversion[80];
507 /* chip major rev, from ipath_revision */
508 u8 ipath_majrev;
509 /* chip minor rev, from ipath_revision */
510 u8 ipath_minrev;
511 /* board rev, from ipath_revision */
512 u8 ipath_boardrev;
513 /* unit # of this chip, if present */
514 int ipath_unit;
515 /* saved for restore after reset */
516 u8 ipath_pci_cacheline;
517 /* LID mask control */
518 u8 ipath_lmc;
519};
520
521extern volatile __le64 *ipath_port0_rcvhdrtail;
522extern dma_addr_t ipath_port0_rcvhdrtail_dma;
523
524#define IPATH_PORT0_RCVHDRTAIL_SIZE PAGE_SIZE
525
526extern struct list_head ipath_dev_list;
527extern spinlock_t ipath_devs_lock;
528extern struct ipath_devdata *ipath_lookup(int unit);
529
530extern u16 ipath_layer_rcv_opcode;
531extern int ipath_verbs_registered;
532extern int __ipath_layer_intr(struct ipath_devdata *, u32);
533extern int ipath_layer_intr(struct ipath_devdata *, u32);
534extern int __ipath_layer_rcv(struct ipath_devdata *, void *,
535 struct sk_buff *);
536extern int __ipath_layer_rcv_lid(struct ipath_devdata *, void *);
537extern int __ipath_verbs_piobufavail(struct ipath_devdata *);
538extern int __ipath_verbs_rcv(struct ipath_devdata *, void *, void *, u32);
539
540void ipath_layer_add(struct ipath_devdata *);
541void ipath_layer_del(struct ipath_devdata *);
542
543int ipath_init_chip(struct ipath_devdata *, int);
544int ipath_enable_wc(struct ipath_devdata *dd);
545void ipath_disable_wc(struct ipath_devdata *dd);
546int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp);
547void ipath_shutdown_device(struct ipath_devdata *);
548
549struct file_operations;
550int ipath_cdev_init(int minor, char *name, struct file_operations *fops,
551 struct cdev **cdevp, struct class_device **class_devp);
552void ipath_cdev_cleanup(struct cdev **cdevp,
553 struct class_device **class_devp);
554
555int ipath_diag_init(void);
556void ipath_diag_cleanup(void);
557void ipath_diag_bringup_link(struct ipath_devdata *);
558
559extern wait_queue_head_t ipath_sma_state_wait;
560
561int ipath_user_add(struct ipath_devdata *dd);
562void ipath_user_del(struct ipath_devdata *dd);
563
564struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t);
565
566extern int ipath_diag_inuse;
567
568irqreturn_t ipath_intr(int irq, void *devid, struct pt_regs *regs);
569void ipath_decode_err(char *buf, size_t blen, ipath_err_t err);
570#if __IPATH_INFO || __IPATH_DBG
571extern const char *ipath_ibcstatus_str[];
572#endif
573
574/* clean up any per-chip chip-specific stuff */
575void ipath_chip_cleanup(struct ipath_devdata *);
576/* clean up any chip type-specific stuff */
577void ipath_chip_done(void);
578
579/* check to see if we have to force ordering for write combining */
580int ipath_unordered_wc(void);
581
582void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first,
583 unsigned cnt);
584
585int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *);
586void ipath_free_pddata(struct ipath_devdata *, u32, int);
587
588int ipath_parse_ushort(const char *str, unsigned short *valp);
589
590int ipath_wait_linkstate(struct ipath_devdata *, u32, int);
591void ipath_set_ib_lstate(struct ipath_devdata *, int);
592void ipath_kreceive(struct ipath_devdata *);
593int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned);
594int ipath_reset_device(int);
595void ipath_get_faststats(unsigned long);
596
597/* for use in system calls, where we want to know device type, etc. */
598#define port_fp(fp) ((struct ipath_portdata *) (fp)->private_data)
599
600/*
601 * values for ipath_flags
602 */
603/* The chip is up and initted */
604#define IPATH_INITTED 0x2
605 /* set if any user code has set kr_rcvhdrsize */
606#define IPATH_RCVHDRSZ_SET 0x4
607 /* The chip is present and valid for accesses */
608#define IPATH_PRESENT 0x8
609 /* HT link0 is only 8 bits wide, ignore upper byte crc
610 * errors, etc. */
611#define IPATH_8BIT_IN_HT0 0x10
612 /* HT link1 is only 8 bits wide, ignore upper byte crc
613 * errors, etc. */
614#define IPATH_8BIT_IN_HT1 0x20
615 /* The link is down */
616#define IPATH_LINKDOWN 0x40
617 /* The link level is up (0x11) */
618#define IPATH_LINKINIT 0x80
619 /* The link is in the armed (0x21) state */
620#define IPATH_LINKARMED 0x100
621 /* The link is in the active (0x31) state */
622#define IPATH_LINKACTIVE 0x200
623 /* link current state is unknown */
624#define IPATH_LINKUNK 0x400
625 /* no IB cable, or no device on IB cable */
626#define IPATH_NOCABLE 0x4000
627 /* Supports port zero per packet receive interrupts via
628 * GPIO */
629#define IPATH_GPIO_INTR 0x8000
630 /* uses the coded 4byte TID, not 8 byte */
631#define IPATH_4BYTE_TID 0x10000
632 /* packet/word counters are 32 bit, else those 4 counters
633 * are 64bit */
634#define IPATH_32BITCOUNTERS 0x20000
635 /* can miss port0 rx interrupts */
636#define IPATH_POLL_RX_INTR 0x40000
637#define IPATH_DISABLED 0x80000 /* administratively disabled */
638
639/* portdata flag bit offsets */
640 /* waiting for a packet to arrive */
641#define IPATH_PORT_WAITING_RCV 2
642 /* waiting for a PIO buffer to be available */
643#define IPATH_PORT_WAITING_PIO 3
644
645/* free up any allocated data at closes */
646void ipath_free_data(struct ipath_portdata *dd);
647int ipath_waitfor_mdio_cmdready(struct ipath_devdata *);
648int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *);
649u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *);
650/* init PE-800-specific func */
651void ipath_init_pe800_funcs(struct ipath_devdata *);
652/* init HT-400-specific func */
653void ipath_init_ht400_funcs(struct ipath_devdata *);
654void ipath_get_guid(struct ipath_devdata *);
655u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg);
656
657/*
658 * number of words used for protocol header if not set by ipath_userinit();
659 */
660#define IPATH_DFLT_RCVHDRSIZE 9
661
662#define IPATH_MDIO_CMD_WRITE 1
663#define IPATH_MDIO_CMD_READ 2
664#define IPATH_MDIO_CLD_DIV 25 /* to get 2.5 Mhz mdio clock */
665#define IPATH_MDIO_CMDVALID 0x40000000 /* bit 30 */
666#define IPATH_MDIO_DATAVALID 0x80000000 /* bit 31 */
667#define IPATH_MDIO_CTRL_STD 0x0
668
669static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data)
670{
671 return (((u64) IPATH_MDIO_CLD_DIV) << 32) |
672 (cmd << 26) |
673 (dev << 21) |
674 (reg << 16) |
675 (data & 0xFFFF);
676}
677
678 /* signal and fifo status, in bank 31 */
679#define IPATH_MDIO_CTRL_XGXS_REG_8 0x8
680 /* controls loopback, redundancy */
681#define IPATH_MDIO_CTRL_8355_REG_1 0x10
682 /* premph, encdec, etc. */
683#define IPATH_MDIO_CTRL_8355_REG_2 0x11
684 /* Kchars, etc. */
685#define IPATH_MDIO_CTRL_8355_REG_6 0x15
686#define IPATH_MDIO_CTRL_8355_REG_9 0x18
687#define IPATH_MDIO_CTRL_8355_REG_10 0x1D
688
689int ipath_get_user_pages(unsigned long, size_t, struct page **);
690int ipath_get_user_pages_nocopy(unsigned long, struct page **);
691void ipath_release_user_pages(struct page **, size_t);
692void ipath_release_user_pages_on_close(struct page **, size_t);
693int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int);
694int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int);
695
696/* these are used for the registers that vary with port */
697void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg,
698 unsigned, u64);
699u64 ipath_read_kreg64_port(const struct ipath_devdata *, ipath_kreg,
700 unsigned);
701
702/*
703 * We could have a single register get/put routine, that takes a group type,
704 * but this is somewhat clearer and cleaner. It also gives us some error
705 * checking. 64 bit register reads should always work, but are inefficient
706 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
707 * so we use kreg32 wherever possible. User register and counter register
708 * reads are always 32 bit reads, so only one form of those routines.
709 */
710
711/*
712 * At the moment, none of the s-registers are writable, so no
713 * ipath_write_sreg(), and none of the c-registers are writable, so no
714 * ipath_write_creg().
715 */
716
717/**
718 * ipath_read_ureg32 - read 32-bit virtualized per-port register
719 * @dd: device
720 * @regno: register number
721 * @port: port number
722 *
723 * Return the contents of a register that is virtualized to be per port.
724 * Prints a debug message and returns -1 on errors (not distinguishable from
725 * valid contents at runtime; we may add a separate error variable at some
726 * point).
727 *
728 * This is normally not used by the kernel, but may be for debugging, and
729 * has a different implementation than user mode, which is why it's not in
730 * _common.h.
731 */
732static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd,
733 ipath_ureg regno, int port)
734{
735 if (!dd->ipath_kregbase)
736 return 0;
737
738 return readl(regno + (u64 __iomem *)
739 (dd->ipath_uregbase +
740 (char __iomem *)dd->ipath_kregbase +
741 dd->ipath_palign * port));
742}
743
744/**
745 * ipath_write_ureg - write 32-bit virtualized per-port register
746 * @dd: device
747 * @regno: register number
748 * @value: value
749 * @port: port
750 *
751 * Write the contents of a register that is virtualized to be per port.
752 */
753static inline void ipath_write_ureg(const struct ipath_devdata *dd,
754 ipath_ureg regno, u64 value, int port)
755{
756 u64 __iomem *ubase = (u64 __iomem *)
757 (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
758 dd->ipath_palign * port);
759 if (dd->ipath_kregbase)
760 writeq(value, &ubase[regno]);
761}
762
763static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd,
764 ipath_kreg regno)
765{
766 if (!dd->ipath_kregbase)
767 return -1;
768 return readl((u32 __iomem *) & dd->ipath_kregbase[regno]);
769}
770
771static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd,
772 ipath_kreg regno)
773{
774 if (!dd->ipath_kregbase)
775 return -1;
776
777 return readq(&dd->ipath_kregbase[regno]);
778}
779
780static inline void ipath_write_kreg(const struct ipath_devdata *dd,
781 ipath_kreg regno, u64 value)
782{
783 if (dd->ipath_kregbase)
784 writeq(value, &dd->ipath_kregbase[regno]);
785}
786
787static inline u64 ipath_read_creg(const struct ipath_devdata *dd,
788 ipath_sreg regno)
789{
790 if (!dd->ipath_kregbase)
791 return 0;
792
793 return readq(regno + (u64 __iomem *)
794 (dd->ipath_cregbase +
795 (char __iomem *)dd->ipath_kregbase));
796}
797
798static inline u32 ipath_read_creg32(const struct ipath_devdata *dd,
799 ipath_sreg regno)
800{
801 if (!dd->ipath_kregbase)
802 return 0;
803 return readl(regno + (u64 __iomem *)
804 (dd->ipath_cregbase +
805 (char __iomem *)dd->ipath_kregbase));
806}
807
808/*
809 * sysfs interface.
810 */
811
812struct device_driver;
813
814extern const char ipath_core_version[];
815
816int ipath_driver_create_group(struct device_driver *);
817void ipath_driver_remove_group(struct device_driver *);
818
819int ipath_device_create_group(struct device *, struct ipath_devdata *);
820void ipath_device_remove_group(struct device *, struct ipath_devdata *);
821int ipath_expose_reset(struct device *);
822
823int ipath_init_ipathfs(void);
824void ipath_exit_ipathfs(void);
825int ipathfs_add_device(struct ipath_devdata *);
826int ipathfs_remove_device(struct ipath_devdata *);
827
828/*
829 * Flush write combining store buffers (if present) and perform a write
830 * barrier.
831 */
832#if defined(CONFIG_X86_64)
833#define ipath_flush_wc() asm volatile("sfence" ::: "memory")
834#else
835#define ipath_flush_wc() wmb()
836#endif
837
838extern unsigned ipath_debug; /* debugging bit mask */
839
840const char *ipath_get_unit_name(int unit);
841
842extern struct mutex ipath_mutex;
843
844#define IPATH_DRV_NAME "ipath_core"
845#define IPATH_MAJOR 233
846#define IPATH_SMA_MINOR 128
847#define IPATH_DIAG_MINOR 129
848#define IPATH_NMINORS 130
849
850#define ipath_dev_err(dd,fmt,...) \
851 do { \
852 const struct ipath_devdata *__dd = (dd); \
853 if (__dd->pcidev) \
854 dev_err(&__dd->pcidev->dev, "%s: " fmt, \
855 ipath_get_unit_name(__dd->ipath_unit), \
856 ##__VA_ARGS__); \
857 else \
858 printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \
859 ipath_get_unit_name(__dd->ipath_unit), \
860 ##__VA_ARGS__); \
861 } while (0)
862
863#if _IPATH_DEBUGGING
864
865# define __IPATH_DBG_WHICH(which,fmt,...) \
866 do { \
867 if(unlikely(ipath_debug&(which))) \
868 printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
869 __func__,##__VA_ARGS__); \
870 } while(0)
871
872# define ipath_dbg(fmt,...) \
873 __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__)
874# define ipath_cdbg(which,fmt,...) \
875 __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__)
876
877#else /* ! _IPATH_DEBUGGING */
878
879# define ipath_dbg(fmt,...)
880# define ipath_cdbg(which,fmt,...)
881
882#endif /* _IPATH_DEBUGGING */
883
884#endif /* _IPATH_KERNEL_H */
diff --git a/drivers/infiniband/hw/ipath/ipath_registers.h b/drivers/infiniband/hw/ipath/ipath_registers.h
new file mode 100644
index 000000000000..1e59750c5f63
--- /dev/null
+++ b/drivers/infiniband/hw/ipath/ipath_registers.h
@@ -0,0 +1,446 @@
1/*
2 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef _IPATH_REGISTERS_H
34#define _IPATH_REGISTERS_H
35
36/*
37 * This file should only be included by kernel source, and by the diags.
38 * It defines the registers, and their contents, for the InfiniPath HT-400 chip
39 */
40
41/*
42 * These are the InfiniPath register and buffer bit definitions,
43 * that are visible to software, and needed only by the kernel
44 * and diag code. A few, that are visible to protocol and user
45 * code are in ipath_common.h. Some bits are specific
46 * to a given chip implementation, and have been moved to the
47 * chip-specific source file
48 */
49
50/* kr_revision bits */
51#define INFINIPATH_R_CHIPREVMINOR_MASK 0xFF
52#define INFINIPATH_R_CHIPREVMINOR_SHIFT 0
53#define INFINIPATH_R_CHIPREVMAJOR_MASK 0xFF
54#define INFINIPATH_R_CHIPREVMAJOR_SHIFT 8
55#define INFINIPATH_R_ARCH_MASK 0xFF
56#define INFINIPATH_R_ARCH_SHIFT 16
57#define INFINIPATH_R_SOFTWARE_MASK 0xFF
58#define INFINIPATH_R_SOFTWARE_SHIFT 24
59#define INFINIPATH_R_BOARDID_MASK 0xFF
60#define INFINIPATH_R_BOARDID_SHIFT 32
61
62/* kr_control bits */
63#define INFINIPATH_C_FREEZEMODE 0x00000002
64#define INFINIPATH_C_LINKENABLE 0x00000004
65#define INFINIPATH_C_RESET 0x00000001
66
67/* kr_sendctrl bits */
68#define INFINIPATH_S_DISARMPIOBUF_SHIFT 16
69
70#define IPATH_S_ABORT 0
71#define IPATH_S_PIOINTBUFAVAIL 1
72#define IPATH_S_PIOBUFAVAILUPD 2
73#define IPATH_S_PIOENABLE 3
74#define IPATH_S_DISARM 31
75
76#define INFINIPATH_S_ABORT (1U << IPATH_S_ABORT)
77#define INFINIPATH_S_PIOINTBUFAVAIL (1U << IPATH_S_PIOINTBUFAVAIL)
78#define INFINIPATH_S_PIOBUFAVAILUPD (1U << IPATH_S_PIOBUFAVAILUPD)
79#define INFINIPATH_S_PIOENABLE (1U << IPATH_S_PIOENABLE)
80#define INFINIPATH_S_DISARM (1U << IPATH_S_DISARM)
81
82/* kr_rcvctrl bits */
83#define INFINIPATH_R_PORTENABLE_SHIFT 0
84#define INFINIPATH_R_INTRAVAIL_SHIFT 16
85#define INFINIPATH_R_TAILUPD 0x80000000
86
87/* kr_intstatus, kr_intclear, kr_intmask bits */
88#define INFINIPATH_I_RCVURG_SHIFT 0
89#define INFINIPATH_I_RCVAVAIL_SHIFT 12
90#define INFINIPATH_I_ERROR 0x80000000
91#define INFINIPATH_I_SPIOSENT 0x40000000
92#define INFINIPATH_I_SPIOBUFAVAIL 0x20000000
93#define INFINIPATH_I_GPIO 0x10000000
94
95/* kr_errorstatus, kr_errorclear, kr_errormask bits */
96#define INFINIPATH_E_RFORMATERR 0x0000000000000001ULL
97#define INFINIPATH_E_RVCRC 0x0000000000000002ULL
98#define INFINIPATH_E_RICRC 0x0000000000000004ULL
99#define INFINIPATH_E_RMINPKTLEN 0x0000000000000008ULL
100#define INFINIPATH_E_RMAXPKTLEN 0x0000000000000010ULL
101#define INFINIPATH_E_RLONGPKTLEN 0x0000000000000020ULL
102#define INFINIPATH_E_RSHORTPKTLEN 0x0000000000000040ULL
103#define INFINIPATH_E_RUNEXPCHAR 0x0000000000000080ULL
104#define INFINIPATH_E_RUNSUPVL 0x0000000000000100ULL
105#define INFINIPATH_E_REBP 0x0000000000000200ULL
106#define INFINIPATH_E_RIBFLOW 0x0000000000000400ULL
107#define INFINIPATH_E_RBADVERSION 0x0000000000000800ULL
108#define INFINIPATH_E_RRCVEGRFULL 0x0000000000001000ULL
109#define INFINIPATH_E_RRCVHDRFULL 0x0000000000002000ULL
110#define INFINIPATH_E_RBADTID 0x0000000000004000ULL
111#define INFINIPATH_E_RHDRLEN 0x0000000000008000ULL
112#define INFINIPATH_E_RHDR 0x0000000000010000ULL
113#define INFINIPATH_E_RIBLOSTLINK 0x0000000000020000ULL
114#define INFINIPATH_E_SMINPKTLEN 0x0000000020000000ULL
115#define INFINIPATH_E_SMAXPKTLEN 0x0000000040000000ULL
116#define INFINIPATH_E_SUNDERRUN 0x0000000080000000ULL
117#define INFINIPATH_E_SPKTLEN 0x0000000100000000ULL
118#define INFINIPATH_E_SDROPPEDSMPPKT 0x0000000200000000ULL
119#define INFINIPATH_E_SDROPPEDDATAPKT 0x0000000400000000ULL
120#define INFINIPATH_E_SPIOARMLAUNCH 0x0000000800000000ULL
121#define INFINIPATH_E_SUNEXPERRPKTNUM 0x0000001000000000ULL
122#define INFINIPATH_E_SUNSUPVL 0x0000002000000000ULL
123#define INFINIPATH_E_IBSTATUSCHANGED 0x0001000000000000ULL
124#define INFINIPATH_E_INVALIDADDR 0x0002000000000000ULL
125#define INFINIPATH_E_RESET 0x0004000000000000ULL
126#define INFINIPATH_E_HARDWARE 0x0008000000000000ULL
127
128/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
129/* TXEMEMPARITYERR bit 0: PIObuf, 1: PIOpbc, 2: launchfifo
130 * RXEMEMPARITYERR bit 0: rcvbuf, 1: lookupq, 2: eagerTID, 3: expTID
131 * bit 4: flag buffer, 5: datainfo, 6: header info */
132#define INFINIPATH_HWE_TXEMEMPARITYERR_MASK 0xFULL
133#define INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT 40
134#define INFINIPATH_HWE_RXEMEMPARITYERR_MASK 0x7FULL
135#define INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT 44
136#define INFINIPATH_HWE_RXDSYNCMEMPARITYERR 0x0000000400000000ULL
137#define INFINIPATH_HWE_MEMBISTFAILED 0x0040000000000000ULL
138#define INFINIPATH_HWE_IBCBUSTOSPCPARITYERR 0x4000000000000000ULL
139#define INFINIPATH_HWE_IBCBUSFRSPCPARITYERR 0x8000000000000000ULL
140
141/* kr_hwdiagctrl bits */
142#define INFINIPATH_DC_FORCETXEMEMPARITYERR_MASK 0xFULL
143#define INFINIPATH_DC_FORCETXEMEMPARITYERR_SHIFT 40
144#define INFINIPATH_DC_FORCERXEMEMPARITYERR_MASK 0x7FULL
145#define INFINIPATH_DC_FORCERXEMEMPARITYERR_SHIFT 44
146#define INFINIPATH_DC_FORCERXDSYNCMEMPARITYERR 0x0000000400000000ULL
147#define INFINIPATH_DC_COUNTERDISABLE 0x1000000000000000ULL
148#define INFINIPATH_DC_COUNTERWREN 0x2000000000000000ULL
149#define INFINIPATH_DC_FORCEIBCBUSTOSPCPARITYERR 0x4000000000000000ULL
150#define INFINIPATH_DC_FORCEIBCBUSFRSPCPARITYERR 0x8000000000000000ULL
151
152/* kr_ibcctrl bits */
153#define INFINIPATH_IBCC_FLOWCTRLPERIOD_MASK 0xFFULL
154#define INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT 0
155#define INFINIPATH_IBCC_FLOWCTRLWATERMARK_MASK 0xFFULL
156#define INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT 8
157#define INFINIPATH_IBCC_LINKINITCMD_MASK 0x3ULL
158#define INFINIPATH_IBCC_LINKINITCMD_DISABLE 1
159#define INFINIPATH_IBCC_LINKINITCMD_POLL 2 /* cycle through TS1/TS2 till OK */
160#define INFINIPATH_IBCC_LINKINITCMD_SLEEP 3 /* wait for TS1, then go on */
161#define INFINIPATH_IBCC_LINKINITCMD_SHIFT 16
162#define INFINIPATH_IBCC_LINKCMD_MASK 0x3ULL
163#define INFINIPATH_IBCC_LINKCMD_INIT 1 /* move to 0x11 */
164#define INFINIPATH_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
165#define INFINIPATH_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
166#define INFINIPATH_IBCC_LINKCMD_SHIFT 18
167#define INFINIPATH_IBCC_MAXPKTLEN_MASK 0x7FFULL
168#define INFINIPATH_IBCC_MAXPKTLEN_SHIFT 20
169#define INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK 0xFULL
170#define INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT 32
171#define INFINIPATH_IBCC_OVERRUNTHRESHOLD_MASK 0xFULL
172#define INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT 36
173#define INFINIPATH_IBCC_CREDITSCALE_MASK 0x7ULL
174#define INFINIPATH_IBCC_CREDITSCALE_SHIFT 40
175#define INFINIPATH_IBCC_LOOPBACK 0x8000000000000000ULL
176#define INFINIPATH_IBCC_LINKDOWNDEFAULTSTATE 0x4000000000000000ULL
177
178/* kr_ibcstatus bits */
179#define INFINIPATH_IBCS_LINKTRAININGSTATE_MASK 0xF
180#define INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT 0
181#define INFINIPATH_IBCS_LINKSTATE_MASK 0x7
182#define INFINIPATH_IBCS_LINKSTATE_SHIFT 4
183#define INFINIPATH_IBCS_TXREADY 0x40000000
184#define INFINIPATH_IBCS_TXCREDITOK 0x80000000
185/* link training states (shift by INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) */
186#define INFINIPATH_IBCS_LT_STATE_DISABLED 0x00
187#define INFINIPATH_IBCS_LT_STATE_LINKUP 0x01
188#define INFINIPATH_IBCS_LT_STATE_POLLACTIVE 0x02
189#define INFINIPATH_IBCS_LT_STATE_POLLQUIET 0x03
190#define INFINIPATH_IBCS_LT_STATE_SLEEPDELAY 0x04
191#define INFINIPATH_IBCS_LT_STATE_SLEEPQUIET 0x05
192#define INFINIPATH_IBCS_LT_STATE_CFGDEBOUNCE 0x08
193#define INFINIPATH_IBCS_LT_STATE_CFGRCVFCFG 0x09
194#define INFINIPATH_IBCS_LT_STATE_CFGWAITRMT 0x0a
195#define INFINIPATH_IBCS_LT_STATE_CFGIDLE 0x0b
196#define INFINIPATH_IBCS_LT_STATE_RECOVERRETRAIN 0x0c
197#define INFINIPATH_IBCS_LT_STATE_RECOVERWAITRMT 0x0e
198#define INFINIPATH_IBCS_LT_STATE_RECOVERIDLE 0x0f
199/* link state machine states (shift by INFINIPATH_IBCS_LINKSTATE_SHIFT) */
200#define INFINIPATH_IBCS_L_STATE_DOWN 0x0
201#define INFINIPATH_IBCS_L_STATE_INIT 0x1
202#define INFINIPATH_IBCS_L_STATE_ARM 0x2
203#define INFINIPATH_IBCS_L_STATE_ACTIVE 0x3
204#define INFINIPATH_IBCS_L_STATE_ACT_DEFER 0x4
205
206/* combination link status states that we use with some frequency */
207#define IPATH_IBSTATE_MASK ((INFINIPATH_IBCS_LINKTRAININGSTATE_MASK \
208 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
209 (INFINIPATH_IBCS_LINKSTATE_MASK \
210 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
211#define IPATH_IBSTATE_INIT ((INFINIPATH_IBCS_L_STATE_INIT \
212 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
213 (INFINIPATH_IBCS_LT_STATE_LINKUP \
214 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
215#define IPATH_IBSTATE_ARM ((INFINIPATH_IBCS_L_STATE_ARM \
216 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
217 (INFINIPATH_IBCS_LT_STATE_LINKUP \
218 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
219#define IPATH_IBSTATE_ACTIVE ((INFINIPATH_IBCS_L_STATE_ACTIVE \
220 << INFINIPATH_IBCS_LINKSTATE_SHIFT) | \
221 (INFINIPATH_IBCS_LT_STATE_LINKUP \
222 <<INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT))
223
224/* kr_extstatus bits */
225#define INFINIPATH_EXTS_SERDESPLLLOCK 0x1
226#define INFINIPATH_EXTS_GPIOIN_MASK 0xFFFFULL
227#define INFINIPATH_EXTS_GPIOIN_SHIFT 48
228
229/* kr_extctrl bits */
230#define INFINIPATH_EXTC_GPIOINVERT_MASK 0xFFFFULL
231#define INFINIPATH_EXTC_GPIOINVERT_SHIFT 32
232#define INFINIPATH_EXTC_GPIOOE_MASK 0xFFFFULL
233#define INFINIPATH_EXTC_GPIOOE_SHIFT 48
234#define INFINIPATH_EXTC_SERDESENABLE 0x80000000ULL
235#define INFINIPATH_EXTC_SERDESCONNECT 0x40000000ULL
236#define INFINIPATH_EXTC_SERDESENTRUNKING 0x20000000ULL
237#define INFINIPATH_EXTC_SERDESDISRXFIFO 0x10000000ULL
238#define INFINIPATH_EXTC_SERDESENPLPBK1 0x08000000ULL
239#define INFINIPATH_EXTC_SERDESENPLPBK2 0x04000000ULL
240#define INFINIPATH_EXTC_SERDESENENCDEC 0x02000000ULL
241#define INFINIPATH_EXTC_LED1SECPORT_ON 0x00000020ULL
242#define INFINIPATH_EXTC_LED2SECPORT_ON 0x00000010ULL
243#define INFINIPATH_EXTC_LED1PRIPORT_ON 0x00000008ULL
244#define INFINIPATH_EXTC_LED2PRIPORT_ON 0x00000004ULL
245#define INFINIPATH_EXTC_LEDGBLOK_ON 0x00000002ULL
246#define INFINIPATH_EXTC_LEDGBLERR_OFF 0x00000001ULL
247
248/* kr_mdio bits */
249#define INFINIPATH_MDIO_CLKDIV_MASK 0x7FULL
250#define INFINIPATH_MDIO_CLKDIV_SHIFT 32
251#define INFINIPATH_MDIO_COMMAND_MASK 0x7ULL
252#define INFINIPATH_MDIO_COMMAND_SHIFT 26
253#define INFINIPATH_MDIO_DEVADDR_MASK 0x1FULL
254#define INFINIPATH_MDIO_DEVADDR_SHIFT 21
255#define INFINIPATH_MDIO_REGADDR_MASK 0x1FULL
256#define INFINIPATH_MDIO_REGADDR_SHIFT 16
257#define INFINIPATH_MDIO_DATA_MASK 0xFFFFULL
258#define INFINIPATH_MDIO_DATA_SHIFT 0
259#define INFINIPATH_MDIO_CMDVALID 0x0000000040000000ULL
260#define INFINIPATH_MDIO_RDDATAVALID 0x0000000080000000ULL
261
262/* kr_partitionkey bits */
263#define INFINIPATH_PKEY_SIZE 16
264#define INFINIPATH_PKEY_MASK 0xFFFF
265#define INFINIPATH_PKEY_DEFAULT_PKEY 0xFFFF
266
267/* kr_serdesconfig0 bits */
268#define INFINIPATH_SERDC0_RESET_MASK 0xfULL /* overal reset bits */
269#define INFINIPATH_SERDC0_RESET_PLL 0x10000000ULL /* pll reset */
270#define INFINIPATH_SERDC0_TXIDLE 0xF000ULL /* tx idle enables (per lane) */
271#define INFINIPATH_SERDC0_RXDETECT_EN 0xF0000ULL /* rx detect enables (per lane) */
272#define INFINIPATH_SERDC0_L1PWR_DN 0xF0ULL /* L1 Power down; use with RXDETECT,
273 Otherwise not used on IB side */
274
275/* kr_xgxsconfig bits */
276#define INFINIPATH_XGXS_RESET 0x7ULL
277#define INFINIPATH_XGXS_MDIOADDR_MASK 0xfULL
278#define INFINIPATH_XGXS_MDIOADDR_SHIFT 4
279
280#define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
281
282/* TID entries (memory), HT400-only */
283#define INFINIPATH_RT_VALID 0x8000000000000000ULL
284#define INFINIPATH_RT_ADDR_SHIFT 0
285#define INFINIPATH_RT_BUFSIZE_MASK 0x3FFF
286#define INFINIPATH_RT_BUFSIZE_SHIFT 48
287
288/*
289 * IPATH_PIO_MAXIBHDR is the max IB header size allowed for in our
290 * PIO send buffers. This is well beyond anything currently
291 * defined in the InfiniBand spec.
292 */
293#define IPATH_PIO_MAXIBHDR 128
294
295typedef u64 ipath_err_t;
296
297/* mask of defined bits for various registers */
298extern u64 infinipath_i_bitsextant;
299extern ipath_err_t infinipath_e_bitsextant, infinipath_hwe_bitsextant;
300
301/* masks that are different in various chips, or only exist in some chips */
302extern u32 infinipath_i_rcvavail_mask, infinipath_i_rcvurg_mask;
303
304/*
305 * register bits for selecting i2c direction and values, used for I2C serial
306 * flash
307 */
308extern u16 ipath_gpio_sda_num, ipath_gpio_scl_num;
309extern u64 ipath_gpio_sda, ipath_gpio_scl;
310
311/*
312 * These are the infinipath general register numbers (not offsets).
313 * The kernel registers are used directly, those beyond the kernel
314 * registers are calculated from one of the base registers. The use of
315 * an integer type doesn't allow type-checking as thorough as, say,
316 * an enum but allows for better hiding of chip differences.
317 */
318typedef const u16 ipath_kreg, /* infinipath general registers */
319 ipath_creg, /* infinipath counter registers */
320 ipath_sreg; /* kernel-only, infinipath send registers */
321
322/*
323 * These are the chip registers common to all infinipath chips, and
324 * used both by the kernel and the diagnostics or other user code.
325 * They are all implemented such that 64 bit accesses work.
326 * Some implement no more than 32 bits. Because 64 bit reads
327 * require 2 HT cmds on opteron, we access those with 32 bit
328 * reads for efficiency (they are written as 64 bits, since
329 * the extra 32 bits are nearly free on writes, and it slightly reduces
330 * complexity). The rest are all accessed as 64 bits.
331 */
332struct ipath_kregs {
333 /* These are the 32 bit group */
334 ipath_kreg kr_control;
335 ipath_kreg kr_counterregbase;
336 ipath_kreg kr_intmask;
337 ipath_kreg kr_intstatus;
338 ipath_kreg kr_pagealign;
339 ipath_kreg kr_portcnt;
340 ipath_kreg kr_rcvtidbase;
341 ipath_kreg kr_rcvtidcnt;
342 ipath_kreg kr_rcvegrbase;
343 ipath_kreg kr_rcvegrcnt;
344 ipath_kreg kr_scratch;
345 ipath_kreg kr_sendctrl;
346 ipath_kreg kr_sendpiobufbase;
347 ipath_kreg kr_sendpiobufcnt;
348 ipath_kreg kr_sendpiosize;
349 ipath_kreg kr_sendregbase;
350 ipath_kreg kr_userregbase;
351 /* These are the 64 bit group */
352 ipath_kreg kr_debugport;
353 ipath_kreg kr_debugportselect;
354 ipath_kreg kr_errorclear;
355 ipath_kreg kr_errormask;
356 ipath_kreg kr_errorstatus;
357 ipath_kreg kr_extctrl;
358 ipath_kreg kr_extstatus;
359 ipath_kreg kr_gpio_clear;
360 ipath_kreg kr_gpio_mask;
361 ipath_kreg kr_gpio_out;
362 ipath_kreg kr_gpio_status;
363 ipath_kreg kr_hwdiagctrl;
364 ipath_kreg kr_hwerrclear;
365 ipath_kreg kr_hwerrmask;
366 ipath_kreg kr_hwerrstatus;
367 ipath_kreg kr_ibcctrl;
368 ipath_kreg kr_ibcstatus;
369 ipath_kreg kr_intblocked;
370 ipath_kreg kr_intclear;
371 ipath_kreg kr_interruptconfig;
372 ipath_kreg kr_mdio;
373 ipath_kreg kr_partitionkey;
374 ipath_kreg kr_rcvbthqp;
375 ipath_kreg kr_rcvbufbase;
376 ipath_kreg kr_rcvbufsize;
377 ipath_kreg kr_rcvctrl;
378 ipath_kreg kr_rcvhdrcnt;
379 ipath_kreg kr_rcvhdrentsize;
380 ipath_kreg kr_rcvhdrsize;
381 ipath_kreg kr_rcvintmembase;
382 ipath_kreg kr_rcvintmemsize;
383 ipath_kreg kr_revision;
384 ipath_kreg kr_sendbuffererror;
385 ipath_kreg kr_sendpioavailaddr;
386 ipath_kreg kr_serdesconfig0;
387 ipath_kreg kr_serdesconfig1;
388 ipath_kreg kr_serdesstatus;
389 ipath_kreg kr_txintmembase;
390 ipath_kreg kr_txintmemsize;
391 ipath_kreg kr_xgxsconfig;
392 ipath_kreg kr_ibpllcfg;
393 /* use these two (and the following N ports) only with ipath_k*_kreg64_port();
394 * not *kreg64() */
395 ipath_kreg kr_rcvhdraddr;
396 ipath_kreg kr_rcvhdrtailaddr;
397
398 /* remaining registers are not present on all types of infinipath chips */
399 ipath_kreg kr_rcvpktledcnt;
400 ipath_kreg kr_pcierbuftestreg0;
401 ipath_kreg kr_pcierbuftestreg1;
402 ipath_kreg kr_pcieq0serdesconfig0;
403 ipath_kreg kr_pcieq0serdesconfig1;
404 ipath_kreg kr_pcieq0serdesstatus;
405 ipath_kreg kr_pcieq1serdesconfig0;
406 ipath_kreg kr_pcieq1serdesconfig1;
407 ipath_kreg kr_pcieq1serdesstatus;
408};
409
410struct ipath_cregs {
411 ipath_creg cr_badformatcnt;
412 ipath_creg cr_erricrccnt;
413 ipath_creg cr_errlinkcnt;
414 ipath_creg cr_errlpcrccnt;
415 ipath_creg cr_errpkey;
416 ipath_creg cr_errrcvflowctrlcnt;
417 ipath_creg cr_err_rlencnt;
418 ipath_creg cr_errslencnt;
419 ipath_creg cr_errtidfull;
420 ipath_creg cr_errtidvalid;
421 ipath_creg cr_errvcrccnt;
422 ipath_creg cr_ibstatuschange;
423 ipath_creg cr_intcnt;
424 ipath_creg cr_invalidrlencnt;
425 ipath_creg cr_invalidslencnt;
426 ipath_creg cr_lbflowstallcnt;
427 ipath_creg cr_iblinkdowncnt;
428 ipath_creg cr_iblinkerrrecovcnt;
429 ipath_creg cr_ibsymbolerrcnt;
430 ipath_creg cr_pktrcvcnt;
431 ipath_creg cr_pktrcvflowctrlcnt;
432 ipath_creg cr_pktsendcnt;
433 ipath_creg cr_pktsendflowcnt;
434 ipath_creg cr_portovflcnt;
435 ipath_creg cr_rcvebpcnt;
436 ipath_creg cr_rcvovflcnt;
437 ipath_creg cr_rxdroppktcnt;
438 ipath_creg cr_senddropped;
439 ipath_creg cr_sendstallcnt;
440 ipath_creg cr_sendunderruncnt;
441 ipath_creg cr_unsupvlcnt;
442 ipath_creg cr_wordrcvcnt;
443 ipath_creg cr_wordsendcnt;
444};
445
446#endif /* _IPATH_REGISTERS_H */
diff --git a/drivers/infiniband/hw/ipath/ips_common.h b/drivers/infiniband/hw/ipath/ips_common.h
new file mode 100644
index 000000000000..410a764dfcef
--- /dev/null
+++ b/drivers/infiniband/hw/ipath/ips_common.h
@@ -0,0 +1,263 @@
1#ifndef IPS_COMMON_H
2#define IPS_COMMON_H
3/*
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include "ipath_common.h"
36
37struct ipath_header {
38 /*
39 * Version - 4 bits, Port - 4 bits, TID - 10 bits and Offset -
40 * 14 bits before ECO change ~28 Dec 03. After that, Vers 4,
41 * Port 3, TID 11, offset 14.
42 */
43 __le32 ver_port_tid_offset;
44 __le16 chksum;
45 __le16 pkt_flags;
46};
47
48struct ips_message_header {
49 __be16 lrh[4];
50 __be32 bth[3];
51 /* fields below this point are in host byte order */
52 struct ipath_header iph;
53 __u8 sub_opcode;
54 __u8 flags;
55 __u16 src_rank;
56 /* 24 bits. The upper 8 bit is available for other use */
57 union {
58 struct {
59 unsigned ack_seq_num:24;
60 unsigned port:4;
61 unsigned unused:4;
62 };
63 __u32 ack_seq_num_org;
64 };
65 __u8 expected_tid_session_id;
66 __u8 tinylen; /* to aid MPI */
67 union {
68 __u16 tag; /* to aid MPI */
69 __u16 mqhdr; /* for PSM MQ */
70 };
71 union {
72 __u32 mpi[4]; /* to aid MPI */
73 __u32 data[4];
74 __u64 mq[2]; /* for PSM MQ */
75 struct {
76 __u16 mtu;
77 __u8 major_ver;
78 __u8 minor_ver;
79 __u32 not_used; //free
80 __u32 run_id;
81 __u32 client_ver;
82 };
83 };
84};
85
86struct ether_header {
87 __be16 lrh[4];
88 __be32 bth[3];
89 struct ipath_header iph;
90 __u8 sub_opcode;
91 __u8 cmd;
92 __be16 lid;
93 __u16 mac[3];
94 __u8 frag_num;
95 __u8 seq_num;
96 __le32 len;
97 /* MUST be of word size due to PIO write requirements */
98 __u32 csum;
99 __le16 csum_offset;
100 __le16 flags;
101 __u16 first_2_bytes;
102 __u8 unused[2]; /* currently unused */
103};
104
105/*
106 * The PIO buffer used for sending infinipath messages must only be written
107 * in 32-bit words, all the data must be written, and no writes can occur
108 * after the last word is written (which transfers "ownership" of the buffer
109 * to the chip and triggers the message to be sent).
110 * Since the Linux sk_buff structure can be recursive, non-aligned, and
111 * any number of bytes in each segment, we use the following structure
112 * to keep information about the overall state of the copy operation.
113 * This is used to save the information needed to store the checksum
114 * in the right place before sending the last word to the hardware and
115 * to buffer the last 0-3 bytes of non-word sized segments.
116 */
117struct copy_data_s {
118 struct ether_header *hdr;
119 /* addr of PIO buf to write csum to */
120 __u32 __iomem *csum_pio;
121 __u32 __iomem *to; /* addr of PIO buf to write data to */
122 __u32 device; /* which device to allocate PIO bufs from */
123 __s32 error; /* set if there is an error. */
124 __s32 extra; /* amount of data saved in u.buf below */
125 __u32 len; /* total length to send in bytes */
126 __u32 flen; /* frament length in words */
127 __u32 csum; /* partial IP checksum */
128 __u32 pos; /* position for partial checksum */
129 __u32 offset; /* offset to where data currently starts */
130 __s32 checksum_calc; /* set to 1 when csum has been calculated */
131 struct sk_buff *skb;
132 union {
133 __u32 w;
134 __u8 buf[4];
135 } u;
136};
137
138/* IB - LRH header consts */
139#define IPS_LRH_GRH 0x0003 /* 1. word of IB LRH - next header: GRH */
140#define IPS_LRH_BTH 0x0002 /* 1. word of IB LRH - next header: BTH */
141
142#define IPS_OFFSET 0
143
144/*
145 * defines the cut-off point between the header queue and eager/expected
146 * TID queue
147 */
148#define NUM_OF_EXTRA_WORDS_IN_HEADER_QUEUE \
149 ((sizeof(struct ips_message_header) - \
150 offsetof(struct ips_message_header, iph)) >> 2)
151
152/* OpCodes */
153#define OPCODE_IPS 0xC0
154#define OPCODE_ITH4X 0xC1
155
156/* OpCode 30 is use by stand-alone test programs */
157#define OPCODE_RAW_DATA 0xDE
158/* last OpCode (31) is reserved for test */
159#define OPCODE_TEST 0xDF
160
161/* sub OpCodes - ips */
162#define OPCODE_SEQ_DATA 0x01
163#define OPCODE_SEQ_CTRL 0x02
164
165#define OPCODE_SEQ_MQ_DATA 0x03
166#define OPCODE_SEQ_MQ_CTRL 0x04
167
168#define OPCODE_ACK 0x10
169#define OPCODE_NAK 0x11
170
171#define OPCODE_ERR_CHK 0x20
172#define OPCODE_ERR_CHK_PLS 0x21
173
174#define OPCODE_STARTUP 0x30
175#define OPCODE_STARTUP_ACK 0x31
176#define OPCODE_STARTUP_NAK 0x32
177
178#define OPCODE_STARTUP_EXT 0x34
179#define OPCODE_STARTUP_ACK_EXT 0x35
180#define OPCODE_STARTUP_NAK_EXT 0x36
181
182#define OPCODE_TIDS_RELEASE 0x40
183#define OPCODE_TIDS_RELEASE_CONFIRM 0x41
184
185#define OPCODE_CLOSE 0x50
186#define OPCODE_CLOSE_ACK 0x51
187/*
188 * like OPCODE_CLOSE, but no complaint if other side has already closed.
189 * Used when doing abort(), MPI_Abort(), etc.
190 */
191#define OPCODE_ABORT 0x52
192
193/* sub OpCodes - ith4x */
194#define OPCODE_ENCAP 0x81
195#define OPCODE_LID_ARP 0x82
196
197/* Receive Header Queue: receive type (from infinipath) */
198#define RCVHQ_RCV_TYPE_EXPECTED 0
199#define RCVHQ_RCV_TYPE_EAGER 1
200#define RCVHQ_RCV_TYPE_NON_KD 2
201#define RCVHQ_RCV_TYPE_ERROR 3
202
203/* misc. */
204#define SIZE_OF_CRC 1
205
206#define EAGER_TID_ID INFINIPATH_I_TID_MASK
207
208#define IPS_DEFAULT_P_KEY 0xFFFF
209
210#define IPS_PERMISSIVE_LID 0xFFFF
211#define IPS_MULTICAST_LID_BASE 0xC000
212
213#define IPS_AETH_CREDIT_SHIFT 24
214#define IPS_AETH_CREDIT_MASK 0x1F
215#define IPS_AETH_CREDIT_INVAL 0x1F
216
217#define IPS_PSN_MASK 0xFFFFFF
218#define IPS_MSN_MASK 0xFFFFFF
219#define IPS_QPN_MASK 0xFFFFFF
220#define IPS_MULTICAST_QPN 0xFFFFFF
221
222/* functions for extracting fields from rcvhdrq entries */
223static inline __u32 ips_get_hdr_err_flags(const __le32 * rbuf)
224{
225 return __le32_to_cpu(rbuf[1]);
226}
227
228static inline __u32 ips_get_index(const __le32 * rbuf)
229{
230 return (__le32_to_cpu(rbuf[0]) >> INFINIPATH_RHF_EGRINDEX_SHIFT)
231 & INFINIPATH_RHF_EGRINDEX_MASK;
232}
233
234static inline __u32 ips_get_rcv_type(const __le32 * rbuf)
235{
236 return (__le32_to_cpu(rbuf[0]) >> INFINIPATH_RHF_RCVTYPE_SHIFT)
237 & INFINIPATH_RHF_RCVTYPE_MASK;
238}
239
240static inline __u32 ips_get_length_in_bytes(const __le32 * rbuf)
241{
242 return ((__le32_to_cpu(rbuf[0]) >> INFINIPATH_RHF_LENGTH_SHIFT)
243 & INFINIPATH_RHF_LENGTH_MASK) << 2;
244}
245
246static inline void *ips_get_first_protocol_header(const __u32 * rbuf)
247{
248 return (void *)&rbuf[2];
249}
250
251static inline struct ips_message_header *ips_get_ips_header(const __u32 *
252 rbuf)
253{
254 return (struct ips_message_header *)&rbuf[2];
255}
256
257static inline __u32 ips_get_ipath_ver(__le32 hdrword)
258{
259 return (__le32_to_cpu(hdrword) >> INFINIPATH_I_VERS_SHIFT)
260 & INFINIPATH_I_VERS_MASK;
261}
262
263#endif /* IPS_COMMON_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-07 11:58:37 -0500