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-rw-r--r--drivers/net/s2io.c386
-rw-r--r--drivers/net/s2io.h30
2 files changed, 208 insertions, 208 deletions
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index 1dcda887cef7..078a49e85936 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -223,9 +223,7 @@ static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
223 * the XAUI. 223 * the XAUI.
224 */ 224 */
225 225
226#define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL
227#define END_SIGN 0x0 226#define END_SIGN 0x0
228
229static const u64 herc_act_dtx_cfg[] = { 227static const u64 herc_act_dtx_cfg[] = {
230 /* Set address */ 228 /* Set address */
231 0x8000051536750000ULL, 0x80000515367500E0ULL, 229 0x8000051536750000ULL, 0x80000515367500E0ULL,
@@ -247,37 +245,19 @@ static const u64 herc_act_dtx_cfg[] = {
247 END_SIGN 245 END_SIGN
248}; 246};
249 247
250static const u64 xena_mdio_cfg[] = {
251 /* Reset PMA PLL */
252 0xC001010000000000ULL, 0xC0010100000000E0ULL,
253 0xC0010100008000E4ULL,
254 /* Remove Reset from PMA PLL */
255 0xC001010000000000ULL, 0xC0010100000000E0ULL,
256 0xC0010100000000E4ULL,
257 END_SIGN
258};
259
260static const u64 xena_dtx_cfg[] = { 248static const u64 xena_dtx_cfg[] = {
249 /* Set address */
261 0x8000051500000000ULL, 0x80000515000000E0ULL, 250 0x8000051500000000ULL, 0x80000515000000E0ULL,
262 0x80000515D93500E4ULL, 0x8001051500000000ULL, 251 /* Write data */
263 0x80010515000000E0ULL, 0x80010515001E00E4ULL, 252 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
264 0x8002051500000000ULL, 0x80020515000000E0ULL, 253 /* Set address */
265 0x80020515F21000E4ULL, 254 0x8001051500000000ULL, 0x80010515000000E0ULL,
266 /* Set PADLOOPBACKN */ 255 /* Write data */
267 0x8002051500000000ULL, 0x80020515000000E0ULL, 256 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
268 0x80020515B20000E4ULL, 0x8003051500000000ULL, 257 /* Set address */
269 0x80030515000000E0ULL, 0x80030515B20000E4ULL,
270 0x8004051500000000ULL, 0x80040515000000E0ULL,
271 0x80040515B20000E4ULL, 0x8005051500000000ULL,
272 0x80050515000000E0ULL, 0x80050515B20000E4ULL,
273 SWITCH_SIGN,
274 /* Remove PADLOOPBACKN */
275 0x8002051500000000ULL, 0x80020515000000E0ULL, 258 0x8002051500000000ULL, 0x80020515000000E0ULL,
276 0x80020515F20000E4ULL, 0x8003051500000000ULL, 259 /* Write data */
277 0x80030515000000E0ULL, 0x80030515F20000E4ULL, 260 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
278 0x8004051500000000ULL, 0x80040515000000E0ULL,
279 0x80040515F20000E4ULL, 0x8005051500000000ULL,
280 0x80050515000000E0ULL, 0x80050515F20000E4ULL,
281 END_SIGN 261 END_SIGN
282}; 262};
283 263
@@ -552,11 +532,6 @@ static int init_shared_mem(struct s2io_nic *nic)
552 rx_blocks->block_dma_addr + 532 rx_blocks->block_dma_addr +
553 (rxd_size[nic->rxd_mode] * l); 533 (rxd_size[nic->rxd_mode] * l);
554 } 534 }
555
556 mac_control->rings[i].rx_blocks[j].block_virt_addr =
557 tmp_v_addr;
558 mac_control->rings[i].rx_blocks[j].block_dma_addr =
559 tmp_p_addr;
560 } 535 }
561 /* Interlinking all Rx Blocks */ 536 /* Interlinking all Rx Blocks */
562 for (j = 0; j < blk_cnt; j++) { 537 for (j = 0; j < blk_cnt; j++) {
@@ -775,7 +750,21 @@ static int s2io_verify_pci_mode(nic_t *nic)
775 return mode; 750 return mode;
776} 751}
777 752
753#define NEC_VENID 0x1033
754#define NEC_DEVID 0x0125
755static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
756{
757 struct pci_dev *tdev = NULL;
758 while ((tdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
759 if ((tdev->vendor == NEC_VENID) && (tdev->device == NEC_DEVID)){
760 if (tdev->bus == s2io_pdev->bus->parent)
761 return 1;
762 }
763 }
764 return 0;
765}
778 766
767int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
779/** 768/**
780 * s2io_print_pci_mode - 769 * s2io_print_pci_mode -
781 */ 770 */
@@ -792,6 +781,14 @@ static int s2io_print_pci_mode(nic_t *nic)
792 if ( val64 & PCI_MODE_UNKNOWN_MODE) 781 if ( val64 & PCI_MODE_UNKNOWN_MODE)
793 return -1; /* Unknown PCI mode */ 782 return -1; /* Unknown PCI mode */
794 783
784 config->bus_speed = bus_speed[mode];
785
786 if (s2io_on_nec_bridge(nic->pdev)) {
787 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
788 nic->dev->name);
789 return mode;
790 }
791
795 if (val64 & PCI_MODE_32_BITS) { 792 if (val64 & PCI_MODE_32_BITS) {
796 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name); 793 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
797 } else { 794 } else {
@@ -801,35 +798,27 @@ static int s2io_print_pci_mode(nic_t *nic)
801 switch(mode) { 798 switch(mode) {
802 case PCI_MODE_PCI_33: 799 case PCI_MODE_PCI_33:
803 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n"); 800 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
804 config->bus_speed = 33;
805 break; 801 break;
806 case PCI_MODE_PCI_66: 802 case PCI_MODE_PCI_66:
807 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n"); 803 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
808 config->bus_speed = 133;
809 break; 804 break;
810 case PCI_MODE_PCIX_M1_66: 805 case PCI_MODE_PCIX_M1_66:
811 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n"); 806 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
812 config->bus_speed = 133; /* Herc doubles the clock rate */
813 break; 807 break;
814 case PCI_MODE_PCIX_M1_100: 808 case PCI_MODE_PCIX_M1_100:
815 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n"); 809 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
816 config->bus_speed = 200;
817 break; 810 break;
818 case PCI_MODE_PCIX_M1_133: 811 case PCI_MODE_PCIX_M1_133:
819 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n"); 812 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
820 config->bus_speed = 266;
821 break; 813 break;
822 case PCI_MODE_PCIX_M2_66: 814 case PCI_MODE_PCIX_M2_66:
823 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n"); 815 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
824 config->bus_speed = 133;
825 break; 816 break;
826 case PCI_MODE_PCIX_M2_100: 817 case PCI_MODE_PCIX_M2_100:
827 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n"); 818 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
828 config->bus_speed = 200;
829 break; 819 break;
830 case PCI_MODE_PCIX_M2_133: 820 case PCI_MODE_PCIX_M2_133:
831 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n"); 821 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
832 config->bus_speed = 266;
833 break; 822 break;
834 default: 823 default:
835 return -1; /* Unsupported bus speed */ 824 return -1; /* Unsupported bus speed */
@@ -857,7 +846,7 @@ static int init_nic(struct s2io_nic *nic)
857 int i, j; 846 int i, j;
858 mac_info_t *mac_control; 847 mac_info_t *mac_control;
859 struct config_param *config; 848 struct config_param *config;
860 int mdio_cnt = 0, dtx_cnt = 0; 849 int dtx_cnt = 0;
861 unsigned long long mem_share; 850 unsigned long long mem_share;
862 int mem_size; 851 int mem_size;
863 852
@@ -904,20 +893,6 @@ static int init_nic(struct s2io_nic *nic)
904 val64 = dev->mtu; 893 val64 = dev->mtu;
905 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); 894 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
906 895
907 /*
908 * Configuring the XAUI Interface of Xena.
909 * ***************************************
910 * To Configure the Xena's XAUI, one has to write a series
911 * of 64 bit values into two registers in a particular
912 * sequence. Hence a macro 'SWITCH_SIGN' has been defined
913 * which will be defined in the array of configuration values
914 * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places
915 * to switch writing from one regsiter to another. We continue
916 * writing these values until we encounter the 'END_SIGN' macro.
917 * For example, After making a series of 21 writes into
918 * dtx_control register the 'SWITCH_SIGN' appears and hence we
919 * start writing into mdio_control until we encounter END_SIGN.
920 */
921 if (nic->device_type & XFRAME_II_DEVICE) { 896 if (nic->device_type & XFRAME_II_DEVICE) {
922 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) { 897 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
923 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt], 898 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
@@ -927,35 +902,11 @@ static int init_nic(struct s2io_nic *nic)
927 dtx_cnt++; 902 dtx_cnt++;
928 } 903 }
929 } else { 904 } else {
930 while (1) { 905 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
931 dtx_cfg: 906 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
932 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) { 907 &bar0->dtx_control, UF);
933 if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) { 908 val64 = readq(&bar0->dtx_control);
934 dtx_cnt++; 909 dtx_cnt++;
935 goto mdio_cfg;
936 }
937 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
938 &bar0->dtx_control, UF);
939 val64 = readq(&bar0->dtx_control);
940 dtx_cnt++;
941 }
942 mdio_cfg:
943 while (xena_mdio_cfg[mdio_cnt] != END_SIGN) {
944 if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
945 mdio_cnt++;
946 goto dtx_cfg;
947 }
948 SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt],
949 &bar0->mdio_control, UF);
950 val64 = readq(&bar0->mdio_control);
951 mdio_cnt++;
952 }
953 if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) &&
954 (xena_mdio_cfg[mdio_cnt] == END_SIGN)) {
955 break;
956 } else {
957 goto dtx_cfg;
958 }
959 } 910 }
960 } 911 }
961 912
@@ -1565,11 +1516,9 @@ static int init_nic(struct s2io_nic *nic)
1565 val64 &= ~(BIT(13)|BIT(14)|BIT(15)); 1516 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1566 writeq(val64, &bar0->pic_control2); 1517 writeq(val64, &bar0->pic_control2);
1567 } 1518 }
1568 1519 if (strstr(nic->product_name, "CX4")) {
1569 /* Setting Link stability period to 64 ms */ 1520 val64 = TMAC_AVG_IPG(0x17);
1570 if (nic->device_type == XFRAME_II_DEVICE) { 1521 writeq(val64, &bar0->tmac_avg_ipg);
1571 val64 = MISC_LINK_STABILITY_PRD(3);
1572 writeq(val64, &bar0->misc_control);
1573 } 1522 }
1574 1523
1575 return SUCCESS; 1524 return SUCCESS;
@@ -2034,6 +1983,13 @@ static int start_nic(struct s2io_nic *nic)
2034 val64 |= ADAPTER_EOI_TX_ON; 1983 val64 |= ADAPTER_EOI_TX_ON;
2035 writeq(val64, &bar0->adapter_control); 1984 writeq(val64, &bar0->adapter_control);
2036 1985
1986 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
1987 /*
1988 * Dont see link state interrupts initally on some switches,
1989 * so directly scheduling the link state task here.
1990 */
1991 schedule_work(&nic->set_link_task);
1992 }
2037 /* SXE-002: Initialize link and activity LED */ 1993 /* SXE-002: Initialize link and activity LED */
2038 subid = nic->pdev->subsystem_device; 1994 subid = nic->pdev->subsystem_device;
2039 if (((subid & 0xFF) >= 0x07) && 1995 if (((subid & 0xFF) >= 0x07) &&
@@ -2045,12 +2001,6 @@ static int start_nic(struct s2io_nic *nic)
2045 writeq(val64, (void __iomem *)bar0 + 0x2700); 2001 writeq(val64, (void __iomem *)bar0 + 0x2700);
2046 } 2002 }
2047 2003
2048 /*
2049 * Don't see link state interrupts on certain switches, so
2050 * directly scheduling a link state task from here.
2051 */
2052 schedule_work(&nic->set_link_task);
2053
2054 return SUCCESS; 2004 return SUCCESS;
2055} 2005}
2056/** 2006/**
@@ -2569,7 +2519,8 @@ static int s2io_poll(struct net_device *dev, int *budget)
2569 } 2519 }
2570 } 2520 }
2571 /* Re enable the Rx interrupts. */ 2521 /* Re enable the Rx interrupts. */
2572 en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS); 2522 writeq(0x0, &bar0->rx_traffic_mask);
2523 val64 = readl(&bar0->rx_traffic_mask);
2573 atomic_dec(&nic->isr_cnt); 2524 atomic_dec(&nic->isr_cnt);
2574 return 0; 2525 return 0;
2575 2526
@@ -2881,23 +2832,26 @@ static void alarm_intr_handler(struct s2io_nic *nic)
2881 * SUCCESS on success and FAILURE on failure. 2832 * SUCCESS on success and FAILURE on failure.
2882 */ 2833 */
2883 2834
2884static int wait_for_cmd_complete(nic_t * sp) 2835static int wait_for_cmd_complete(void *addr, u64 busy_bit)
2885{ 2836{
2886 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2887 int ret = FAILURE, cnt = 0; 2837 int ret = FAILURE, cnt = 0;
2888 u64 val64; 2838 u64 val64;
2889 2839
2890 while (TRUE) { 2840 while (TRUE) {
2891 val64 = readq(&bar0->rmac_addr_cmd_mem); 2841 val64 = readq(addr);
2892 if (!(val64 & RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) { 2842 if (!(val64 & busy_bit)) {
2893 ret = SUCCESS; 2843 ret = SUCCESS;
2894 break; 2844 break;
2895 } 2845 }
2896 msleep(50); 2846
2847 if(in_interrupt())
2848 mdelay(50);
2849 else
2850 msleep(50);
2851
2897 if (cnt++ > 10) 2852 if (cnt++ > 10)
2898 break; 2853 break;
2899 } 2854 }
2900
2901 return ret; 2855 return ret;
2902} 2856}
2903 2857
@@ -2936,6 +2890,9 @@ static void s2io_reset(nic_t * sp)
2936 * PCI write to sw_reset register is done by this time. 2890 * PCI write to sw_reset register is done by this time.
2937 */ 2891 */
2938 msleep(250); 2892 msleep(250);
2893 if (strstr(sp->product_name, "CX4")) {
2894 msleep(750);
2895 }
2939 2896
2940 /* Restore the PCI state saved during initialization. */ 2897 /* Restore the PCI state saved during initialization. */
2941 pci_restore_state(sp->pdev); 2898 pci_restore_state(sp->pdev);
@@ -3154,7 +3111,7 @@ static void restore_xmsi_data(nic_t *nic)
3154 u64 val64; 3111 u64 val64;
3155 int i; 3112 int i;
3156 3113
3157 for (i=0; i< MAX_REQUESTED_MSI_X; i++) { 3114 for (i=0; i< nic->avail_msix_vectors; i++) {
3158 writeq(nic->msix_info[i].addr, &bar0->xmsi_address); 3115 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3159 writeq(nic->msix_info[i].data, &bar0->xmsi_data); 3116 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3160 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6)); 3117 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
@@ -3173,7 +3130,7 @@ static void store_xmsi_data(nic_t *nic)
3173 int i; 3130 int i;
3174 3131
3175 /* Store and display */ 3132 /* Store and display */
3176 for (i=0; i< MAX_REQUESTED_MSI_X; i++) { 3133 for (i=0; i< nic->avail_msix_vectors; i++) {
3177 val64 = (BIT(15) | vBIT(i, 26, 6)); 3134 val64 = (BIT(15) | vBIT(i, 26, 6));
3178 writeq(val64, &bar0->xmsi_access); 3135 writeq(val64, &bar0->xmsi_access);
3179 if (wait_for_msix_trans(nic, i)) { 3136 if (wait_for_msix_trans(nic, i)) {
@@ -3301,15 +3258,24 @@ static int s2io_enable_msi_x(nic_t *nic)
3301 writeq(tx_mat, &bar0->tx_mat0_n[7]); 3258 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3302 } 3259 }
3303 3260
3261 nic->avail_msix_vectors = 0;
3304 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X); 3262 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3263 /* We fail init if error or we get less vectors than min required */
3264 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3265 nic->avail_msix_vectors = ret;
3266 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3267 }
3305 if (ret) { 3268 if (ret) {
3306 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name); 3269 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3307 kfree(nic->entries); 3270 kfree(nic->entries);
3308 kfree(nic->s2io_entries); 3271 kfree(nic->s2io_entries);
3309 nic->entries = NULL; 3272 nic->entries = NULL;
3310 nic->s2io_entries = NULL; 3273 nic->s2io_entries = NULL;
3274 nic->avail_msix_vectors = 0;
3311 return -ENOMEM; 3275 return -ENOMEM;
3312 } 3276 }
3277 if (!nic->avail_msix_vectors)
3278 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3313 3279
3314 /* 3280 /*
3315 * To enable MSI-X, MSI also needs to be enabled, due to a bug 3281 * To enable MSI-X, MSI also needs to be enabled, due to a bug
@@ -3342,8 +3308,6 @@ static int s2io_open(struct net_device *dev)
3342{ 3308{
3343 nic_t *sp = dev->priv; 3309 nic_t *sp = dev->priv;
3344 int err = 0; 3310 int err = 0;
3345 int i;
3346 u16 msi_control; /* Temp variable */
3347 3311
3348 /* 3312 /*
3349 * Make sure you have link off by default every time 3313 * Make sure you have link off by default every time
@@ -3353,11 +3317,14 @@ static int s2io_open(struct net_device *dev)
3353 sp->last_link_state = 0; 3317 sp->last_link_state = 0;
3354 3318
3355 /* Initialize H/W and enable interrupts */ 3319 /* Initialize H/W and enable interrupts */
3356 if (s2io_card_up(sp)) { 3320 err = s2io_card_up(sp);
3321 if (err) {
3357 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", 3322 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3358 dev->name); 3323 dev->name);
3359 err = -ENODEV; 3324 if (err == -ENODEV)
3360 goto hw_init_failed; 3325 goto hw_init_failed;
3326 else
3327 goto hw_enable_failed;
3361 } 3328 }
3362 3329
3363 /* Store the values of the MSIX table in the nic_t structure */ 3330 /* Store the values of the MSIX table in the nic_t structure */
@@ -3374,6 +3341,8 @@ failed\n", dev->name);
3374 } 3341 }
3375 } 3342 }
3376 if (sp->intr_type == MSI_X) { 3343 if (sp->intr_type == MSI_X) {
3344 int i;
3345
3377 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) { 3346 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
3378 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) { 3347 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
3379 sprintf(sp->desc1, "%s:MSI-X-%d-TX", 3348 sprintf(sp->desc1, "%s:MSI-X-%d-TX",
@@ -3426,24 +3395,25 @@ setting_mac_address_failed:
3426isr_registration_failed: 3395isr_registration_failed:
3427 del_timer_sync(&sp->alarm_timer); 3396 del_timer_sync(&sp->alarm_timer);
3428 if (sp->intr_type == MSI_X) { 3397 if (sp->intr_type == MSI_X) {
3429 if (sp->device_type == XFRAME_II_DEVICE) { 3398 int i;
3430 for (i=1; (sp->s2io_entries[i].in_use == 3399 u16 msi_control; /* Temp variable */
3400 for (i=1; (sp->s2io_entries[i].in_use ==
3431 MSIX_REGISTERED_SUCCESS); i++) { 3401 MSIX_REGISTERED_SUCCESS); i++) {
3432 int vector = sp->entries[i].vector; 3402 int vector = sp->entries[i].vector;
3433 void *arg = sp->s2io_entries[i].arg; 3403 void *arg = sp->s2io_entries[i].arg;
3434
3435 free_irq(vector, arg);
3436 }
3437 pci_disable_msix(sp->pdev);
3438 3404
3439 /* Temp */ 3405 free_irq(vector, arg);
3440 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3441 msi_control &= 0xFFFE; /* Disable MSI */
3442 pci_write_config_word(sp->pdev, 0x42, msi_control);
3443 } 3406 }
3407 pci_disable_msix(sp->pdev);
3408
3409 /* Temp */
3410 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3411 msi_control &= 0xFFFE; /* Disable MSI */
3412 pci_write_config_word(sp->pdev, 0x42, msi_control);
3444 } 3413 }
3445 else if (sp->intr_type == MSI) 3414 else if (sp->intr_type == MSI)
3446 pci_disable_msi(sp->pdev); 3415 pci_disable_msi(sp->pdev);
3416hw_enable_failed:
3447 s2io_reset(sp); 3417 s2io_reset(sp);
3448hw_init_failed: 3418hw_init_failed:
3449 if (sp->intr_type == MSI_X) { 3419 if (sp->intr_type == MSI_X) {
@@ -3471,35 +3441,12 @@ hw_init_failed:
3471static int s2io_close(struct net_device *dev) 3441static int s2io_close(struct net_device *dev)
3472{ 3442{
3473 nic_t *sp = dev->priv; 3443 nic_t *sp = dev->priv;
3474 int i;
3475 u16 msi_control;
3476 3444
3477 flush_scheduled_work(); 3445 flush_scheduled_work();
3478 netif_stop_queue(dev); 3446 netif_stop_queue(dev);
3479 /* Reset card, kill tasklet and free Tx and Rx buffers. */ 3447 /* Reset card, kill tasklet and free Tx and Rx buffers. */
3480 s2io_card_down(sp); 3448 s2io_card_down(sp, 1);
3481
3482 if (sp->intr_type == MSI_X) {
3483 if (sp->device_type == XFRAME_II_DEVICE) {
3484 for (i=1; (sp->s2io_entries[i].in_use ==
3485 MSIX_REGISTERED_SUCCESS); i++) {
3486 int vector = sp->entries[i].vector;
3487 void *arg = sp->s2io_entries[i].arg;
3488
3489 free_irq(vector, arg);
3490 }
3491 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3492 msi_control &= 0xFFFE; /* Disable MSI */
3493 pci_write_config_word(sp->pdev, 0x42, msi_control);
3494 3449
3495 pci_disable_msix(sp->pdev);
3496 }
3497 }
3498 else {
3499 free_irq(sp->pdev->irq, dev);
3500 if (sp->intr_type == MSI)
3501 pci_disable_msi(sp->pdev);
3502 }
3503 sp->device_close_flag = TRUE; /* Device is shut down. */ 3450 sp->device_close_flag = TRUE; /* Device is shut down. */
3504 return 0; 3451 return 0;
3505} 3452}
@@ -3825,41 +3772,56 @@ static void s2io_txpic_intr_handle(nic_t *sp)
3825 val64 = readq(&bar0->gpio_int_reg); 3772 val64 = readq(&bar0->gpio_int_reg);
3826 if ((val64 & GPIO_INT_REG_LINK_DOWN) && 3773 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
3827 (val64 & GPIO_INT_REG_LINK_UP)) { 3774 (val64 & GPIO_INT_REG_LINK_UP)) {
3775 /*
3776 * This is unstable state so clear both up/down
3777 * interrupt and adapter to re-evaluate the link state.
3778 */
3828 val64 |= GPIO_INT_REG_LINK_DOWN; 3779 val64 |= GPIO_INT_REG_LINK_DOWN;
3829 val64 |= GPIO_INT_REG_LINK_UP; 3780 val64 |= GPIO_INT_REG_LINK_UP;
3830 writeq(val64, &bar0->gpio_int_reg); 3781 writeq(val64, &bar0->gpio_int_reg);
3831 goto masking;
3832 }
3833
3834 if (((sp->last_link_state == LINK_UP) &&
3835 (val64 & GPIO_INT_REG_LINK_DOWN)) ||
3836 ((sp->last_link_state == LINK_DOWN) &&
3837 (val64 & GPIO_INT_REG_LINK_UP))) {
3838 val64 = readq(&bar0->gpio_int_mask); 3782 val64 = readq(&bar0->gpio_int_mask);
3839 val64 |= GPIO_INT_MASK_LINK_DOWN; 3783 val64 &= ~(GPIO_INT_MASK_LINK_UP |
3840 val64 |= GPIO_INT_MASK_LINK_UP; 3784 GPIO_INT_MASK_LINK_DOWN);
3841 writeq(val64, &bar0->gpio_int_mask); 3785 writeq(val64, &bar0->gpio_int_mask);
3842 s2io_set_link((unsigned long)sp);
3843 } 3786 }
3844masking: 3787 else if (val64 & GPIO_INT_REG_LINK_UP) {
3845 if (sp->last_link_state == LINK_UP) { 3788 val64 = readq(&bar0->adapter_status);
3846 /*enable down interrupt */ 3789 if (verify_xena_quiescence(sp, val64,
3847 val64 = readq(&bar0->gpio_int_mask); 3790 sp->device_enabled_once)) {
3848 /* unmasks link down intr */ 3791 /* Enable Adapter */
3849 val64 &= ~GPIO_INT_MASK_LINK_DOWN; 3792 val64 = readq(&bar0->adapter_control);
3850 /* masks link up intr */ 3793 val64 |= ADAPTER_CNTL_EN;
3851 val64 |= GPIO_INT_MASK_LINK_UP; 3794 writeq(val64, &bar0->adapter_control);
3852 writeq(val64, &bar0->gpio_int_mask); 3795 val64 |= ADAPTER_LED_ON;
3853 } else { 3796 writeq(val64, &bar0->adapter_control);
3854 /*enable UP Interrupt */ 3797 if (!sp->device_enabled_once)
3855 val64 = readq(&bar0->gpio_int_mask); 3798 sp->device_enabled_once = 1;
3856 /* unmasks link up interrupt */ 3799
3857 val64 &= ~GPIO_INT_MASK_LINK_UP; 3800 s2io_link(sp, LINK_UP);
3858 /* masks link down interrupt */ 3801 /*
3859 val64 |= GPIO_INT_MASK_LINK_DOWN; 3802 * unmask link down interrupt and mask link-up
3860 writeq(val64, &bar0->gpio_int_mask); 3803 * intr
3804 */
3805 val64 = readq(&bar0->gpio_int_mask);
3806 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
3807 val64 |= GPIO_INT_MASK_LINK_UP;
3808 writeq(val64, &bar0->gpio_int_mask);
3809
3810 }
3811 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
3812 val64 = readq(&bar0->adapter_status);
3813 if (verify_xena_quiescence(sp, val64,
3814 sp->device_enabled_once)) {
3815 s2io_link(sp, LINK_DOWN);
3816 /* Link is down so unmaks link up interrupt */
3817 val64 = readq(&bar0->gpio_int_mask);
3818 val64 &= ~GPIO_INT_MASK_LINK_UP;
3819 val64 |= GPIO_INT_MASK_LINK_DOWN;
3820 writeq(val64, &bar0->gpio_int_mask);
3821 }
3861 } 3822 }
3862 } 3823 }
3824 val64 = readq(&bar0->gpio_int_mask);
3863} 3825}
3864 3826
3865/** 3827/**
@@ -4080,7 +4042,8 @@ static void s2io_set_multicast(struct net_device *dev)
4080 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET); 4042 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4081 writeq(val64, &bar0->rmac_addr_cmd_mem); 4043 writeq(val64, &bar0->rmac_addr_cmd_mem);
4082 /* Wait till command completes */ 4044 /* Wait till command completes */
4083 wait_for_cmd_complete(sp); 4045 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4046 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4084 4047
4085 sp->m_cast_flg = 1; 4048 sp->m_cast_flg = 1;
4086 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET; 4049 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
@@ -4095,7 +4058,8 @@ static void s2io_set_multicast(struct net_device *dev)
4095 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos); 4058 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4096 writeq(val64, &bar0->rmac_addr_cmd_mem); 4059 writeq(val64, &bar0->rmac_addr_cmd_mem);
4097 /* Wait till command completes */ 4060 /* Wait till command completes */
4098 wait_for_cmd_complete(sp); 4061 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4062 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4099 4063
4100 sp->m_cast_flg = 0; 4064 sp->m_cast_flg = 0;
4101 sp->all_multi_pos = 0; 4065 sp->all_multi_pos = 0;
@@ -4160,7 +4124,8 @@ static void s2io_set_multicast(struct net_device *dev)
4160 writeq(val64, &bar0->rmac_addr_cmd_mem); 4124 writeq(val64, &bar0->rmac_addr_cmd_mem);
4161 4125
4162 /* Wait for command completes */ 4126 /* Wait for command completes */
4163 if (wait_for_cmd_complete(sp)) { 4127 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4128 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4164 DBG_PRINT(ERR_DBG, "%s: Adding ", 4129 DBG_PRINT(ERR_DBG, "%s: Adding ",
4165 dev->name); 4130 dev->name);
4166 DBG_PRINT(ERR_DBG, "Multicasts failed\n"); 4131 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
@@ -4190,7 +4155,8 @@ static void s2io_set_multicast(struct net_device *dev)
4190 writeq(val64, &bar0->rmac_addr_cmd_mem); 4155 writeq(val64, &bar0->rmac_addr_cmd_mem);
4191 4156
4192 /* Wait for command completes */ 4157 /* Wait for command completes */
4193 if (wait_for_cmd_complete(sp)) { 4158 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4159 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4194 DBG_PRINT(ERR_DBG, "%s: Adding ", 4160 DBG_PRINT(ERR_DBG, "%s: Adding ",
4195 dev->name); 4161 dev->name);
4196 DBG_PRINT(ERR_DBG, "Multicasts failed\n"); 4162 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
@@ -4235,7 +4201,8 @@ static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4235 RMAC_ADDR_CMD_MEM_OFFSET(0); 4201 RMAC_ADDR_CMD_MEM_OFFSET(0);
4236 writeq(val64, &bar0->rmac_addr_cmd_mem); 4202 writeq(val64, &bar0->rmac_addr_cmd_mem);
4237 /* Wait till command completes */ 4203 /* Wait till command completes */
4238 if (wait_for_cmd_complete(sp)) { 4204 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4205 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4239 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name); 4206 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4240 return FAILURE; 4207 return FAILURE;
4241 } 4208 }
@@ -4632,7 +4599,6 @@ static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4632 } 4599 }
4633 return ret; 4600 return ret;
4634} 4601}
4635
4636static void s2io_vpd_read(nic_t *nic) 4602static void s2io_vpd_read(nic_t *nic)
4637{ 4603{
4638 u8 vpd_data[256],data; 4604 u8 vpd_data[256],data;
@@ -4983,8 +4949,10 @@ static int s2io_link_test(nic_t * sp, uint64_t * data)
4983 u64 val64; 4949 u64 val64;
4984 4950
4985 val64 = readq(&bar0->adapter_status); 4951 val64 = readq(&bar0->adapter_status);
4986 if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT) 4952 if(!(LINK_IS_UP(val64)))
4987 *data = 1; 4953 *data = 1;
4954 else
4955 *data = 0;
4988 4956
4989 return 0; 4957 return 0;
4990} 4958}
@@ -5403,7 +5371,7 @@ static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5403 5371
5404 dev->mtu = new_mtu; 5372 dev->mtu = new_mtu;
5405 if (netif_running(dev)) { 5373 if (netif_running(dev)) {
5406 s2io_card_down(sp); 5374 s2io_card_down(sp, 0);
5407 netif_stop_queue(dev); 5375 netif_stop_queue(dev);
5408 if (s2io_card_up(sp)) { 5376 if (s2io_card_up(sp)) {
5409 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", 5377 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
@@ -5541,12 +5509,13 @@ static void s2io_set_link(unsigned long data)
5541 clear_bit(0, &(nic->link_state)); 5509 clear_bit(0, &(nic->link_state));
5542} 5510}
5543 5511
5544static void s2io_card_down(nic_t * sp) 5512static void s2io_card_down(nic_t * sp, int flag)
5545{ 5513{
5546 int cnt = 0; 5514 int cnt = 0;
5547 XENA_dev_config_t __iomem *bar0 = sp->bar0; 5515 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5548 unsigned long flags; 5516 unsigned long flags;
5549 register u64 val64 = 0; 5517 register u64 val64 = 0;
5518 struct net_device *dev = sp->dev;
5550 5519
5551 del_timer_sync(&sp->alarm_timer); 5520 del_timer_sync(&sp->alarm_timer);
5552 /* If s2io_set_link task is executing, wait till it completes. */ 5521 /* If s2io_set_link task is executing, wait till it completes. */
@@ -5557,6 +5526,36 @@ static void s2io_card_down(nic_t * sp)
5557 5526
5558 /* disable Tx and Rx traffic on the NIC */ 5527 /* disable Tx and Rx traffic on the NIC */
5559 stop_nic(sp); 5528 stop_nic(sp);
5529 if (flag) {
5530 if (sp->intr_type == MSI_X) {
5531 int i;
5532 u16 msi_control;
5533
5534 for (i=1; (sp->s2io_entries[i].in_use ==
5535 MSIX_REGISTERED_SUCCESS); i++) {
5536 int vector = sp->entries[i].vector;
5537 void *arg = sp->s2io_entries[i].arg;
5538
5539 free_irq(vector, arg);
5540 }
5541 pci_read_config_word(sp->pdev, 0x42, &msi_control);
5542 msi_control &= 0xFFFE; /* Disable MSI */
5543 pci_write_config_word(sp->pdev, 0x42, msi_control);
5544 pci_disable_msix(sp->pdev);
5545 } else {
5546 free_irq(sp->pdev->irq, dev);
5547 if (sp->intr_type == MSI)
5548 pci_disable_msi(sp->pdev);
5549 }
5550 }
5551 /* Waiting till all Interrupt handlers are complete */
5552 cnt = 0;
5553 do {
5554 msleep(10);
5555 if (!atomic_read(&sp->isr_cnt))
5556 break;
5557 cnt++;
5558 } while(cnt < 5);
5560 5559
5561 /* Kill tasklet. */ 5560 /* Kill tasklet. */
5562 tasklet_kill(&sp->task); 5561 tasklet_kill(&sp->task);
@@ -5580,15 +5579,6 @@ static void s2io_card_down(nic_t * sp)
5580 } while (1); 5579 } while (1);
5581 s2io_reset(sp); 5580 s2io_reset(sp);
5582 5581
5583 /* Waiting till all Interrupt handlers are complete */
5584 cnt = 0;
5585 do {
5586 msleep(10);
5587 if (!atomic_read(&sp->isr_cnt))
5588 break;
5589 cnt++;
5590 } while(cnt < 5);
5591
5592 spin_lock_irqsave(&sp->tx_lock, flags); 5582 spin_lock_irqsave(&sp->tx_lock, flags);
5593 /* Free all Tx buffers */ 5583 /* Free all Tx buffers */
5594 free_tx_buffers(sp); 5584 free_tx_buffers(sp);
@@ -5689,7 +5679,7 @@ static void s2io_restart_nic(unsigned long data)
5689 struct net_device *dev = (struct net_device *) data; 5679 struct net_device *dev = (struct net_device *) data;
5690 nic_t *sp = dev->priv; 5680 nic_t *sp = dev->priv;
5691 5681
5692 s2io_card_down(sp); 5682 s2io_card_down(sp, 0);
5693 if (s2io_card_up(sp)) { 5683 if (s2io_card_up(sp)) {
5694 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", 5684 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5695 dev->name); 5685 dev->name);
@@ -5751,6 +5741,7 @@ static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
5751 lro_t *lro; 5741 lro_t *lro;
5752 5742
5753 skb->dev = dev; 5743 skb->dev = dev;
5744
5754 if (err) { 5745 if (err) {
5755 /* 5746 /*
5756 * Drop the packet if bad transfer code. Exception being 5747 * Drop the packet if bad transfer code. Exception being
@@ -5853,6 +5844,9 @@ static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
5853 clear_lro_session(lro); 5844 clear_lro_session(lro);
5854 goto send_up; 5845 goto send_up;
5855 case 0: /* sessions exceeded */ 5846 case 0: /* sessions exceeded */
5847 case -1: /* non-TCP or not
5848 * L2 aggregatable
5849 */
5856 case 5: /* 5850 case 5: /*
5857 * First pkt in session not 5851 * First pkt in session not
5858 * L3/L4 aggregatable 5852 * L3/L4 aggregatable
@@ -6351,8 +6345,8 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6351 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | 6345 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
6352 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET); 6346 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
6353 writeq(val64, &bar0->rmac_addr_cmd_mem); 6347 writeq(val64, &bar0->rmac_addr_cmd_mem);
6354 wait_for_cmd_complete(sp); 6348 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
6355 6349 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
6356 tmp64 = readq(&bar0->rmac_addr_data0_mem); 6350 tmp64 = readq(&bar0->rmac_addr_data0_mem);
6357 mac_down = (u32) tmp64; 6351 mac_down = (u32) tmp64;
6358 mac_up = (u32) (tmp64 >> 32); 6352 mac_up = (u32) (tmp64 >> 32);
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index a83a1d85f72e..fb46a4fed334 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -661,8 +661,8 @@ typedef struct {
661/* Default Tunable parameters of the NIC. */ 661/* Default Tunable parameters of the NIC. */
662#define DEFAULT_FIFO_0_LEN 4096 662#define DEFAULT_FIFO_0_LEN 4096
663#define DEFAULT_FIFO_1_7_LEN 512 663#define DEFAULT_FIFO_1_7_LEN 512
664#define SMALL_BLK_CNT 30 664#define SMALL_BLK_CNT 30
665#define LARGE_BLK_CNT 100 665#define LARGE_BLK_CNT 100
666 666
667/* 667/*
668 * Structure to keep track of the MSI-X vectors and the corresponding 668 * Structure to keep track of the MSI-X vectors and the corresponding
@@ -733,7 +733,7 @@ struct s2io_nic {
733 int device_close_flag; 733 int device_close_flag;
734 int device_enabled_once; 734 int device_enabled_once;
735 735
736 char name[50]; 736 char name[60];
737 struct tasklet_struct task; 737 struct tasklet_struct task;
738 volatile unsigned long tasklet_status; 738 volatile unsigned long tasklet_status;
739 739
@@ -804,6 +804,8 @@ struct s2io_nic {
804 char desc1[35]; 804 char desc1[35];
805 char desc2[35]; 805 char desc2[35];
806 806
807 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
808
807 struct msix_info_st msix_info[0x3f]; 809 struct msix_info_st msix_info[0x3f];
808 810
809#define XFRAME_I_DEVICE 1 811#define XFRAME_I_DEVICE 1
@@ -851,28 +853,32 @@ static inline void writeq(u64 val, void __iomem *addr)
851 writel((u32) (val), addr); 853 writel((u32) (val), addr);
852 writel((u32) (val >> 32), (addr + 4)); 854 writel((u32) (val >> 32), (addr + 4));
853} 855}
856#endif
854 857
855/* In 32 bit modes, some registers have to be written in a 858/*
856 * particular order to expect correct hardware operation. The 859 * Some registers have to be written in a particular order to
857 * macro SPECIAL_REG_WRITE is used to perform such ordered 860 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
858 * writes. Defines UF (Upper First) and LF (Lower First) will 861 * is used to perform such ordered writes. Defines UF (Upper First)
859 * be used to specify the required write order. 862 * and LF (Lower First) will be used to specify the required write order.
860 */ 863 */
861#define UF 1 864#define UF 1
862#define LF 2 865#define LF 2
863static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order) 866static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
864{ 867{
868 u32 ret;
869
865 if (order == LF) { 870 if (order == LF) {
866 writel((u32) (val), addr); 871 writel((u32) (val), addr);
872 ret = readl(addr);
867 writel((u32) (val >> 32), (addr + 4)); 873 writel((u32) (val >> 32), (addr + 4));
874 ret = readl(addr + 4);
868 } else { 875 } else {
869 writel((u32) (val >> 32), (addr + 4)); 876 writel((u32) (val >> 32), (addr + 4));
877 ret = readl(addr + 4);
870 writel((u32) (val), addr); 878 writel((u32) (val), addr);
879 ret = readl(addr);
871 } 880 }
872} 881}
873#else
874#define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
875#endif
876 882
877/* Interrupt related values of Xena */ 883/* Interrupt related values of Xena */
878 884
@@ -968,7 +974,7 @@ static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
968static struct ethtool_ops netdev_ethtool_ops; 974static struct ethtool_ops netdev_ethtool_ops;
969static void s2io_set_link(unsigned long data); 975static void s2io_set_link(unsigned long data);
970static int s2io_set_swapper(nic_t * sp); 976static int s2io_set_swapper(nic_t * sp);
971static void s2io_card_down(nic_t *nic); 977static void s2io_card_down(nic_t *nic, int flag);
972static int s2io_card_up(nic_t *nic); 978static int s2io_card_up(nic_t *nic);
973static int get_xena_rev_id(struct pci_dev *pdev); 979static int get_xena_rev_id(struct pci_dev *pdev);
974static void restore_xmsi_data(nic_t *nic); 980static void restore_xmsi_data(nic_t *nic);
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-28 09:11:53 -0400