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-rw-r--r--arch/arm/mach-s5p6440/mach-smdk6440.c30
-rw-r--r--arch/arm/mach-s5p6442/mach-smdk6442.c24
-rw-r--r--arch/arm/mach-s5pc100/mach-smdkc100.c30
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c30
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c30
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkc110.c30
-rw-r--r--arch/arm/mach-s5pv210/mach-smdkv210.c30
7 files changed, 102 insertions, 102 deletions
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c
index 8291fecc701a..fedc1423f1f9 100644
--- a/arch/arm/mach-s5p6440/mach-smdk6440.c
+++ b/arch/arm/mach-s5p6440/mach-smdk6440.c
@@ -41,16 +41,16 @@
41#include <plat/adc.h> 41#include <plat/adc.h>
42#include <plat/ts.h> 42#include <plat/ts.h>
43 43
44#define S5P6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 44#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
45 S3C2410_UCON_RXILEVEL | \ 45 S3C2410_UCON_RXILEVEL | \
46 S3C2410_UCON_TXIRQMODE | \ 46 S3C2410_UCON_TXIRQMODE | \
47 S3C2410_UCON_RXIRQMODE | \ 47 S3C2410_UCON_RXIRQMODE | \
48 S3C2410_UCON_RXFIFO_TOI | \ 48 S3C2410_UCON_RXFIFO_TOI | \
49 S3C2443_UCON_RXERR_IRQEN) 49 S3C2443_UCON_RXERR_IRQEN)
50 50
51#define S5P6440_ULCON_DEFAULT S3C2410_LCON_CS8 51#define SMDK6440_ULCON_DEFAULT S3C2410_LCON_CS8
52 52
53#define S5P6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 53#define SMDK6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
54 S3C2440_UFCON_TXTRIG16 | \ 54 S3C2440_UFCON_TXTRIG16 | \
55 S3C2410_UFCON_RXTRIG8) 55 S3C2410_UFCON_RXTRIG8)
56 56
@@ -58,30 +58,30 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
58 [0] = { 58 [0] = {
59 .hwport = 0, 59 .hwport = 0,
60 .flags = 0, 60 .flags = 0,
61 .ucon = S5P6440_UCON_DEFAULT, 61 .ucon = SMDK6440_UCON_DEFAULT,
62 .ulcon = S5P6440_ULCON_DEFAULT, 62 .ulcon = SMDK6440_ULCON_DEFAULT,
63 .ufcon = S5P6440_UFCON_DEFAULT, 63 .ufcon = SMDK6440_UFCON_DEFAULT,
64 }, 64 },
65 [1] = { 65 [1] = {
66 .hwport = 1, 66 .hwport = 1,
67 .flags = 0, 67 .flags = 0,
68 .ucon = S5P6440_UCON_DEFAULT, 68 .ucon = SMDK6440_UCON_DEFAULT,
69 .ulcon = S5P6440_ULCON_DEFAULT, 69 .ulcon = SMDK6440_ULCON_DEFAULT,
70 .ufcon = S5P6440_UFCON_DEFAULT, 70 .ufcon = SMDK6440_UFCON_DEFAULT,
71 }, 71 },
72 [2] = { 72 [2] = {
73 .hwport = 2, 73 .hwport = 2,
74 .flags = 0, 74 .flags = 0,
75 .ucon = S5P6440_UCON_DEFAULT, 75 .ucon = SMDK6440_UCON_DEFAULT,
76 .ulcon = S5P6440_ULCON_DEFAULT, 76 .ulcon = SMDK6440_ULCON_DEFAULT,
77 .ufcon = S5P6440_UFCON_DEFAULT, 77 .ufcon = SMDK6440_UFCON_DEFAULT,
78 }, 78 },
79 [3] = { 79 [3] = {
80 .hwport = 3, 80 .hwport = 3,
81 .flags = 0, 81 .flags = 0,
82 .ucon = S5P6440_UCON_DEFAULT, 82 .ucon = SMDK6440_UCON_DEFAULT,
83 .ulcon = S5P6440_ULCON_DEFAULT, 83 .ulcon = SMDK6440_ULCON_DEFAULT,
84 .ufcon = S5P6440_UFCON_DEFAULT, 84 .ufcon = SMDK6440_UFCON_DEFAULT,
85 }, 85 },
86}; 86};
87 87
diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c
index ebcf99777259..6107bd8b47c2 100644
--- a/arch/arm/mach-s5p6442/mach-smdk6442.c
+++ b/arch/arm/mach-s5p6442/mach-smdk6442.c
@@ -27,16 +27,16 @@
27#include <plat/cpu.h> 27#include <plat/cpu.h>
28 28
29/* Following are default values for UCON, ULCON and UFCON UART registers */ 29/* Following are default values for UCON, ULCON and UFCON UART registers */
30#define S5P6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 30#define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
31 S3C2410_UCON_RXILEVEL | \ 31 S3C2410_UCON_RXILEVEL | \
32 S3C2410_UCON_TXIRQMODE | \ 32 S3C2410_UCON_TXIRQMODE | \
33 S3C2410_UCON_RXIRQMODE | \ 33 S3C2410_UCON_RXIRQMODE | \
34 S3C2410_UCON_RXFIFO_TOI | \ 34 S3C2410_UCON_RXFIFO_TOI | \
35 S3C2443_UCON_RXERR_IRQEN) 35 S3C2443_UCON_RXERR_IRQEN)
36 36
37#define S5P6442_ULCON_DEFAULT S3C2410_LCON_CS8 37#define SMDK6442_ULCON_DEFAULT S3C2410_LCON_CS8
38 38
39#define S5P6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 39#define SMDK6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
40 S5PV210_UFCON_TXTRIG4 | \ 40 S5PV210_UFCON_TXTRIG4 | \
41 S5PV210_UFCON_RXTRIG4) 41 S5PV210_UFCON_RXTRIG4)
42 42
@@ -44,23 +44,23 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
44 [0] = { 44 [0] = {
45 .hwport = 0, 45 .hwport = 0,
46 .flags = 0, 46 .flags = 0,
47 .ucon = S5P6442_UCON_DEFAULT, 47 .ucon = SMDK6442_UCON_DEFAULT,
48 .ulcon = S5P6442_ULCON_DEFAULT, 48 .ulcon = SMDK6442_ULCON_DEFAULT,
49 .ufcon = S5P6442_UFCON_DEFAULT, 49 .ufcon = SMDK6442_UFCON_DEFAULT,
50 }, 50 },
51 [1] = { 51 [1] = {
52 .hwport = 1, 52 .hwport = 1,
53 .flags = 0, 53 .flags = 0,
54 .ucon = S5P6442_UCON_DEFAULT, 54 .ucon = SMDK6442_UCON_DEFAULT,
55 .ulcon = S5P6442_ULCON_DEFAULT, 55 .ulcon = SMDK6442_ULCON_DEFAULT,
56 .ufcon = S5P6442_UFCON_DEFAULT, 56 .ufcon = SMDK6442_UFCON_DEFAULT,
57 }, 57 },
58 [2] = { 58 [2] = {
59 .hwport = 2, 59 .hwport = 2,
60 .flags = 0, 60 .flags = 0,
61 .ucon = S5P6442_UCON_DEFAULT, 61 .ucon = SMDK6442_UCON_DEFAULT,
62 .ulcon = S5P6442_ULCON_DEFAULT, 62 .ulcon = SMDK6442_ULCON_DEFAULT,
63 .ufcon = S5P6442_UFCON_DEFAULT, 63 .ufcon = SMDK6442_UFCON_DEFAULT,
64 }, 64 },
65}; 65};
66 66
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index af22f8202a07..c708db35960d 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -44,16 +44,16 @@
44#include <plat/iic.h> 44#include <plat/iic.h>
45 45
46/* Following are default values for UCON, ULCON and UFCON UART registers */ 46/* Following are default values for UCON, ULCON and UFCON UART registers */
47#define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 47#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48 S3C2410_UCON_RXILEVEL | \ 48 S3C2410_UCON_RXILEVEL | \
49 S3C2410_UCON_TXIRQMODE | \ 49 S3C2410_UCON_TXIRQMODE | \
50 S3C2410_UCON_RXIRQMODE | \ 50 S3C2410_UCON_RXIRQMODE | \
51 S3C2410_UCON_RXFIFO_TOI | \ 51 S3C2410_UCON_RXFIFO_TOI | \
52 S3C2443_UCON_RXERR_IRQEN) 52 S3C2443_UCON_RXERR_IRQEN)
53 53
54#define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8 54#define SMDKC100_ULCON_DEFAULT S3C2410_LCON_CS8
55 55
56#define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 56#define SMDKC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
57 S3C2440_UFCON_RXTRIG8 | \ 57 S3C2440_UFCON_RXTRIG8 | \
58 S3C2440_UFCON_TXTRIG16) 58 S3C2440_UFCON_TXTRIG16)
59 59
@@ -61,30 +61,30 @@ static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
61 [0] = { 61 [0] = {
62 .hwport = 0, 62 .hwport = 0,
63 .flags = 0, 63 .flags = 0,
64 .ucon = S5PC100_UCON_DEFAULT, 64 .ucon = SMDKC100_UCON_DEFAULT,
65 .ulcon = S5PC100_ULCON_DEFAULT, 65 .ulcon = SMDKC100_ULCON_DEFAULT,
66 .ufcon = S5PC100_UFCON_DEFAULT, 66 .ufcon = SMDKC100_UFCON_DEFAULT,
67 }, 67 },
68 [1] = { 68 [1] = {
69 .hwport = 1, 69 .hwport = 1,
70 .flags = 0, 70 .flags = 0,
71 .ucon = S5PC100_UCON_DEFAULT, 71 .ucon = SMDKC100_UCON_DEFAULT,
72 .ulcon = S5PC100_ULCON_DEFAULT, 72 .ulcon = SMDKC100_ULCON_DEFAULT,
73 .ufcon = S5PC100_UFCON_DEFAULT, 73 .ufcon = SMDKC100_UFCON_DEFAULT,
74 }, 74 },
75 [2] = { 75 [2] = {
76 .hwport = 2, 76 .hwport = 2,
77 .flags = 0, 77 .flags = 0,
78 .ucon = S5PC100_UCON_DEFAULT, 78 .ucon = SMDKC100_UCON_DEFAULT,
79 .ulcon = S5PC100_ULCON_DEFAULT, 79 .ulcon = SMDKC100_ULCON_DEFAULT,
80 .ufcon = S5PC100_UFCON_DEFAULT, 80 .ufcon = SMDKC100_UFCON_DEFAULT,
81 }, 81 },
82 [3] = { 82 [3] = {
83 .hwport = 3, 83 .hwport = 3,
84 .flags = 0, 84 .flags = 0,
85 .ucon = S5PC100_UCON_DEFAULT, 85 .ucon = SMDKC100_UCON_DEFAULT,
86 .ulcon = S5PC100_ULCON_DEFAULT, 86 .ulcon = SMDKC100_ULCON_DEFAULT,
87 .ufcon = S5PC100_UFCON_DEFAULT, 87 .ufcon = SMDKC100_UFCON_DEFAULT,
88 }, 88 },
89}; 89};
90 90
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 10bc76ec4025..9d30213463ef 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -30,16 +30,16 @@
30#include <plat/fb.h> 30#include <plat/fb.h>
31 31
32/* Following are default values for UCON, ULCON and UFCON UART registers */ 32/* Following are default values for UCON, ULCON and UFCON UART registers */
33#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 33#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
34 S3C2410_UCON_RXILEVEL | \ 34 S3C2410_UCON_RXILEVEL | \
35 S3C2410_UCON_TXIRQMODE | \ 35 S3C2410_UCON_TXIRQMODE | \
36 S3C2410_UCON_RXIRQMODE | \ 36 S3C2410_UCON_RXIRQMODE | \
37 S3C2410_UCON_RXFIFO_TOI | \ 37 S3C2410_UCON_RXFIFO_TOI | \
38 S3C2443_UCON_RXERR_IRQEN) 38 S3C2443_UCON_RXERR_IRQEN)
39 39
40#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 40#define AQUILA_ULCON_DEFAULT S3C2410_LCON_CS8
41 41
42#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 42#define AQUILA_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
43 S5PV210_UFCON_TXTRIG4 | \ 43 S5PV210_UFCON_TXTRIG4 | \
44 S5PV210_UFCON_RXTRIG4) 44 S5PV210_UFCON_RXTRIG4)
45 45
@@ -47,30 +47,30 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
47 [0] = { 47 [0] = {
48 .hwport = 0, 48 .hwport = 0,
49 .flags = 0, 49 .flags = 0,
50 .ucon = S5PV210_UCON_DEFAULT, 50 .ucon = AQUILA_UCON_DEFAULT,
51 .ulcon = S5PV210_ULCON_DEFAULT, 51 .ulcon = AQUILA_ULCON_DEFAULT,
52 .ufcon = S5PV210_UFCON_DEFAULT, 52 .ufcon = AQUILA_UFCON_DEFAULT,
53 }, 53 },
54 [1] = { 54 [1] = {
55 .hwport = 1, 55 .hwport = 1,
56 .flags = 0, 56 .flags = 0,
57 .ucon = S5PV210_UCON_DEFAULT, 57 .ucon = AQUILA_UCON_DEFAULT,
58 .ulcon = S5PV210_ULCON_DEFAULT, 58 .ulcon = AQUILA_ULCON_DEFAULT,
59 .ufcon = S5PV210_UFCON_DEFAULT, 59 .ufcon = AQUILA_UFCON_DEFAULT,
60 }, 60 },
61 [2] = { 61 [2] = {
62 .hwport = 2, 62 .hwport = 2,
63 .flags = 0, 63 .flags = 0,
64 .ucon = S5PV210_UCON_DEFAULT, 64 .ucon = AQUILA_UCON_DEFAULT,
65 .ulcon = S5PV210_ULCON_DEFAULT, 65 .ulcon = AQUILA_ULCON_DEFAULT,
66 .ufcon = S5PV210_UFCON_DEFAULT, 66 .ufcon = AQUILA_UFCON_DEFAULT,
67 }, 67 },
68 [3] = { 68 [3] = {
69 .hwport = 3, 69 .hwport = 3,
70 .flags = 0, 70 .flags = 0,
71 .ucon = S5PV210_UCON_DEFAULT, 71 .ucon = AQUILA_UCON_DEFAULT,
72 .ulcon = S5PV210_ULCON_DEFAULT, 72 .ulcon = AQUILA_ULCON_DEFAULT,
73 .ufcon = S5PV210_UFCON_DEFAULT, 73 .ufcon = AQUILA_UFCON_DEFAULT,
74 }, 74 },
75}; 75};
76 76
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 4863b13824e4..1521ea11e8c7 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -27,16 +27,16 @@
27#include <plat/cpu.h> 27#include <plat/cpu.h>
28 28
29/* Following are default values for UCON, ULCON and UFCON UART registers */ 29/* Following are default values for UCON, ULCON and UFCON UART registers */
30#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 30#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
31 S3C2410_UCON_RXILEVEL | \ 31 S3C2410_UCON_RXILEVEL | \
32 S3C2410_UCON_TXIRQMODE | \ 32 S3C2410_UCON_TXIRQMODE | \
33 S3C2410_UCON_RXIRQMODE | \ 33 S3C2410_UCON_RXIRQMODE | \
34 S3C2410_UCON_RXFIFO_TOI | \ 34 S3C2410_UCON_RXFIFO_TOI | \
35 S3C2443_UCON_RXERR_IRQEN) 35 S3C2443_UCON_RXERR_IRQEN)
36 36
37#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 37#define GONI_ULCON_DEFAULT S3C2410_LCON_CS8
38 38
39#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 39#define GONI_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
40 S5PV210_UFCON_TXTRIG4 | \ 40 S5PV210_UFCON_TXTRIG4 | \
41 S5PV210_UFCON_RXTRIG4) 41 S5PV210_UFCON_RXTRIG4)
42 42
@@ -44,30 +44,30 @@ static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
44 [0] = { 44 [0] = {
45 .hwport = 0, 45 .hwport = 0,
46 .flags = 0, 46 .flags = 0,
47 .ucon = S5PV210_UCON_DEFAULT, 47 .ucon = GONI_UCON_DEFAULT,
48 .ulcon = S5PV210_ULCON_DEFAULT, 48 .ulcon = GONI_ULCON_DEFAULT,
49 .ufcon = S5PV210_UFCON_DEFAULT, 49 .ufcon = GONI_UFCON_DEFAULT,
50 }, 50 },
51 [1] = { 51 [1] = {
52 .hwport = 1, 52 .hwport = 1,
53 .flags = 0, 53 .flags = 0,
54 .ucon = S5PV210_UCON_DEFAULT, 54 .ucon = GONI_UCON_DEFAULT,
55 .ulcon = S5PV210_ULCON_DEFAULT, 55 .ulcon = GONI_ULCON_DEFAULT,
56 .ufcon = S5PV210_UFCON_DEFAULT, 56 .ufcon = GONI_UFCON_DEFAULT,
57 }, 57 },
58 [2] = { 58 [2] = {
59 .hwport = 2, 59 .hwport = 2,
60 .flags = 0, 60 .flags = 0,
61 .ucon = S5PV210_UCON_DEFAULT, 61 .ucon = GONI_UCON_DEFAULT,
62 .ulcon = S5PV210_ULCON_DEFAULT, 62 .ulcon = GONI_ULCON_DEFAULT,
63 .ufcon = S5PV210_UFCON_DEFAULT, 63 .ufcon = GONI_UFCON_DEFAULT,
64 }, 64 },
65 [3] = { 65 [3] = {
66 .hwport = 3, 66 .hwport = 3,
67 .flags = 0, 67 .flags = 0,
68 .ucon = S5PV210_UCON_DEFAULT, 68 .ucon = GONI_UCON_DEFAULT,
69 .ulcon = S5PV210_ULCON_DEFAULT, 69 .ulcon = GONI_ULCON_DEFAULT,
70 .ufcon = S5PV210_UFCON_DEFAULT, 70 .ufcon = GONI_UFCON_DEFAULT,
71 }, 71 },
72}; 72};
73 73
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 4c8903c6d104..7878f695f2ce 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -27,16 +27,16 @@
27#include <plat/cpu.h> 27#include <plat/cpu.h>
28 28
29/* Following are default values for UCON, ULCON and UFCON UART registers */ 29/* Following are default values for UCON, ULCON and UFCON UART registers */
30#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 30#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
31 S3C2410_UCON_RXILEVEL | \ 31 S3C2410_UCON_RXILEVEL | \
32 S3C2410_UCON_TXIRQMODE | \ 32 S3C2410_UCON_TXIRQMODE | \
33 S3C2410_UCON_RXIRQMODE | \ 33 S3C2410_UCON_RXIRQMODE | \
34 S3C2410_UCON_RXFIFO_TOI | \ 34 S3C2410_UCON_RXFIFO_TOI | \
35 S3C2443_UCON_RXERR_IRQEN) 35 S3C2443_UCON_RXERR_IRQEN)
36 36
37#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 37#define SMDKC110_ULCON_DEFAULT S3C2410_LCON_CS8
38 38
39#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 39#define SMDKC110_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
40 S5PV210_UFCON_TXTRIG4 | \ 40 S5PV210_UFCON_TXTRIG4 | \
41 S5PV210_UFCON_RXTRIG4) 41 S5PV210_UFCON_RXTRIG4)
42 42
@@ -44,30 +44,30 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
44 [0] = { 44 [0] = {
45 .hwport = 0, 45 .hwport = 0,
46 .flags = 0, 46 .flags = 0,
47 .ucon = S5PV210_UCON_DEFAULT, 47 .ucon = SMDKC110_UCON_DEFAULT,
48 .ulcon = S5PV210_ULCON_DEFAULT, 48 .ulcon = SMDKC110_ULCON_DEFAULT,
49 .ufcon = S5PV210_UFCON_DEFAULT, 49 .ufcon = SMDKC110_UFCON_DEFAULT,
50 }, 50 },
51 [1] = { 51 [1] = {
52 .hwport = 1, 52 .hwport = 1,
53 .flags = 0, 53 .flags = 0,
54 .ucon = S5PV210_UCON_DEFAULT, 54 .ucon = SMDKC110_UCON_DEFAULT,
55 .ulcon = S5PV210_ULCON_DEFAULT, 55 .ulcon = SMDKC110_ULCON_DEFAULT,
56 .ufcon = S5PV210_UFCON_DEFAULT, 56 .ufcon = SMDKC110_UFCON_DEFAULT,
57 }, 57 },
58 [2] = { 58 [2] = {
59 .hwport = 2, 59 .hwport = 2,
60 .flags = 0, 60 .flags = 0,
61 .ucon = S5PV210_UCON_DEFAULT, 61 .ucon = SMDKC110_UCON_DEFAULT,
62 .ulcon = S5PV210_ULCON_DEFAULT, 62 .ulcon = SMDKC110_ULCON_DEFAULT,
63 .ufcon = S5PV210_UFCON_DEFAULT, 63 .ufcon = SMDKC110_UFCON_DEFAULT,
64 }, 64 },
65 [3] = { 65 [3] = {
66 .hwport = 3, 66 .hwport = 3,
67 .flags = 0, 67 .flags = 0,
68 .ucon = S5PV210_UCON_DEFAULT, 68 .ucon = SMDKC110_UCON_DEFAULT,
69 .ulcon = S5PV210_ULCON_DEFAULT, 69 .ulcon = SMDKC110_ULCON_DEFAULT,
70 .ufcon = S5PV210_UFCON_DEFAULT, 70 .ufcon = SMDKC110_UFCON_DEFAULT,
71 }, 71 },
72}; 72};
73 73
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 0d4627948040..d1df1882ab18 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -29,16 +29,16 @@
29#include <plat/ts.h> 29#include <plat/ts.h>
30 30
31/* Following are default values for UCON, ULCON and UFCON UART registers */ 31/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ 32#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
33 S3C2410_UCON_RXILEVEL | \ 33 S3C2410_UCON_RXILEVEL | \
34 S3C2410_UCON_TXIRQMODE | \ 34 S3C2410_UCON_TXIRQMODE | \
35 S3C2410_UCON_RXIRQMODE | \ 35 S3C2410_UCON_RXIRQMODE | \
36 S3C2410_UCON_RXFIFO_TOI | \ 36 S3C2410_UCON_RXFIFO_TOI | \
37 S3C2443_UCON_RXERR_IRQEN) 37 S3C2443_UCON_RXERR_IRQEN)
38 38
39#define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 39#define SMDKV210_ULCON_DEFAULT S3C2410_LCON_CS8
40 40
41#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ 41#define SMDKV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
42 S5PV210_UFCON_TXTRIG4 | \ 42 S5PV210_UFCON_TXTRIG4 | \
43 S5PV210_UFCON_RXTRIG4) 43 S5PV210_UFCON_RXTRIG4)
44 44
@@ -46,30 +46,30 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
46 [0] = { 46 [0] = {
47 .hwport = 0, 47 .hwport = 0,
48 .flags = 0, 48 .flags = 0,
49 .ucon = S5PV210_UCON_DEFAULT, 49 .ucon = SMDKV210_UCON_DEFAULT,
50 .ulcon = S5PV210_ULCON_DEFAULT, 50 .ulcon = SMDKV210_ULCON_DEFAULT,
51 .ufcon = S5PV210_UFCON_DEFAULT, 51 .ufcon = SMDKV210_UFCON_DEFAULT,
52 }, 52 },
53 [1] = { 53 [1] = {
54 .hwport = 1, 54 .hwport = 1,
55 .flags = 0, 55 .flags = 0,
56 .ucon = S5PV210_UCON_DEFAULT, 56 .ucon = SMDKV210_UCON_DEFAULT,
57 .ulcon = S5PV210_ULCON_DEFAULT, 57 .ulcon = SMDKV210_ULCON_DEFAULT,
58 .ufcon = S5PV210_UFCON_DEFAULT, 58 .ufcon = SMDKV210_UFCON_DEFAULT,
59 }, 59 },
60 [2] = { 60 [2] = {
61 .hwport = 2, 61 .hwport = 2,
62 .flags = 0, 62 .flags = 0,
63 .ucon = S5PV210_UCON_DEFAULT, 63 .ucon = SMDKV210_UCON_DEFAULT,
64 .ulcon = S5PV210_ULCON_DEFAULT, 64 .ulcon = SMDKV210_ULCON_DEFAULT,
65 .ufcon = S5PV210_UFCON_DEFAULT, 65 .ufcon = SMDKV210_UFCON_DEFAULT,
66 }, 66 },
67 [3] = { 67 [3] = {
68 .hwport = 3, 68 .hwport = 3,
69 .flags = 0, 69 .flags = 0,
70 .ucon = S5PV210_UCON_DEFAULT, 70 .ucon = SMDKV210_UCON_DEFAULT,
71 .ulcon = S5PV210_ULCON_DEFAULT, 71 .ulcon = SMDKV210_ULCON_DEFAULT,
72 .ufcon = S5PV210_UFCON_DEFAULT, 72 .ufcon = SMDKV210_UFCON_DEFAULT,
73 }, 73 },
74}; 74};
75 75
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-06 10:24:39 -0500