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-rw-r--r--drivers/char/drm/r300_cmdbuf.c41
-rw-r--r--drivers/char/drm/r300_reg.h1163
2 files changed, 698 insertions, 506 deletions
diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c
index 032a022ec6a8..28fbf3dda28d 100644
--- a/drivers/char/drm/r300_cmdbuf.c
+++ b/drivers/char/drm/r300_cmdbuf.c
@@ -148,15 +148,16 @@ void r300_init_reg_flags(void)
148 148
149 /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */ 149 /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
150 ADD_RANGE(R300_SE_VPORT_XSCALE, 6); 150 ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
151 ADD_RANGE(0x2080, 1); 151 ADD_RANGE(R300_VAP_CNTL, 1);
152 ADD_RANGE(R300_SE_VTE_CNTL, 2); 152 ADD_RANGE(R300_SE_VTE_CNTL, 2);
153 ADD_RANGE(0x2134, 2); 153 ADD_RANGE(0x2134, 2);
154 ADD_RANGE(0x2140, 1); 154 ADD_RANGE(R300_VAP_CNTL_STATUS, 1);
155 ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2); 155 ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
156 ADD_RANGE(0x21DC, 1); 156 ADD_RANGE(0x21DC, 1);
157 ADD_RANGE(0x221C, 1); 157 ADD_RANGE(R300_VAP_UNKNOWN_221C, 1);
158 ADD_RANGE(0x2220, 4); 158 ADD_RANGE(R300_VAP_CLIP_X_0, 4);
159 ADD_RANGE(0x2288, 1); 159 ADD_RANGE(R300_VAP_PVS_WAITIDLE, 1);
160 ADD_RANGE(R300_VAP_UNKNOWN_2288, 1);
160 ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2); 161 ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
161 ADD_RANGE(R300_VAP_PVS_CNTL_1, 3); 162 ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
162 ADD_RANGE(R300_GB_ENABLE, 1); 163 ADD_RANGE(R300_GB_ENABLE, 1);
@@ -168,13 +169,13 @@ void r300_init_reg_flags(void)
168 ADD_RANGE(R300_RE_POINTSIZE, 1); 169 ADD_RANGE(R300_RE_POINTSIZE, 1);
169 ADD_RANGE(0x4230, 3); 170 ADD_RANGE(0x4230, 3);
170 ADD_RANGE(R300_RE_LINE_CNT, 1); 171 ADD_RANGE(R300_RE_LINE_CNT, 1);
171 ADD_RANGE(0x4238, 1); 172 ADD_RANGE(R300_RE_UNK4238, 1);
172 ADD_RANGE(0x4260, 3); 173 ADD_RANGE(0x4260, 3);
173 ADD_RANGE(0x4274, 4); 174 ADD_RANGE(R300_RE_SHADE, 4);
174 ADD_RANGE(0x4288, 5); 175 ADD_RANGE(R300_RE_POLYGON_MODE, 5);
175 ADD_RANGE(0x42A0, 1); 176 ADD_RANGE(R300_RE_ZBIAS_CNTL, 1);
176 ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4); 177 ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
177 ADD_RANGE(0x42B4, 1); 178 ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1);
178 ADD_RANGE(R300_RE_CULL_CNTL, 1); 179 ADD_RANGE(R300_RE_CULL_CNTL, 1);
179 ADD_RANGE(0x42C0, 2); 180 ADD_RANGE(0x42C0, 2);
180 ADD_RANGE(R300_RS_CNTL_0, 2); 181 ADD_RANGE(R300_RS_CNTL_0, 2);
@@ -190,22 +191,22 @@ void r300_init_reg_flags(void)
190 ADD_RANGE(R300_PFS_INSTR1_0, 64); 191 ADD_RANGE(R300_PFS_INSTR1_0, 64);
191 ADD_RANGE(R300_PFS_INSTR2_0, 64); 192 ADD_RANGE(R300_PFS_INSTR2_0, 64);
192 ADD_RANGE(R300_PFS_INSTR3_0, 64); 193 ADD_RANGE(R300_PFS_INSTR3_0, 64);
193 ADD_RANGE(0x4BC0, 1); 194 ADD_RANGE(R300_RE_FOG_STATE, 1);
194 ADD_RANGE(0x4BC8, 3); 195 ADD_RANGE(R300_FOG_COLOR_R, 3);
195 ADD_RANGE(R300_PP_ALPHA_TEST, 2); 196 ADD_RANGE(R300_PP_ALPHA_TEST, 2);
196 ADD_RANGE(0x4BD8, 1); 197 ADD_RANGE(0x4BD8, 1);
197 ADD_RANGE(R300_PFS_PARAM_0_X, 64); 198 ADD_RANGE(R300_PFS_PARAM_0_X, 64);
198 ADD_RANGE(0x4E00, 1); 199 ADD_RANGE(0x4E00, 1);
199 ADD_RANGE(R300_RB3D_CBLEND, 2); 200 ADD_RANGE(R300_RB3D_CBLEND, 2);
200 ADD_RANGE(R300_RB3D_COLORMASK, 1); 201 ADD_RANGE(R300_RB3D_COLORMASK, 1);
201 ADD_RANGE(0x4E10, 3); 202 ADD_RANGE(R300_RB3D_BLEND_COLOR, 3);
202 ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */ 203 ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */
203 ADD_RANGE(R300_RB3D_COLORPITCH0, 1); 204 ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
204 ADD_RANGE(0x4E50, 9); 205 ADD_RANGE(0x4E50, 9);
205 ADD_RANGE(0x4E88, 1); 206 ADD_RANGE(0x4E88, 1);
206 ADD_RANGE(0x4EA0, 2); 207 ADD_RANGE(0x4EA0, 2);
207 ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3); 208 ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
208 ADD_RANGE(0x4F10, 4); 209 ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
209 ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ 210 ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
210 ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); 211 ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
211 ADD_RANGE(0x4F28, 1); 212 ADD_RANGE(0x4F28, 1);
@@ -224,7 +225,7 @@ void r300_init_reg_flags(void)
224 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); 225 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
225 226
226 /* Sporadic registers used as primitives are emitted */ 227 /* Sporadic registers used as primitives are emitted */
227 ADD_RANGE(0x4f18, 1); 228 ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1);
228 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); 229 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
229 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); 230 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
230 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); 231 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
@@ -692,9 +693,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
692 693
693 BEGIN_RING(6); 694 BEGIN_RING(6);
694 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 695 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
695 OUT_RING(0xa); 696 OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
696 OUT_RING(CP_PACKET0(0x4f18, 0)); 697 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
697 OUT_RING(0x3); 698 OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03);
698 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0)); 699 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
699 OUT_RING(0x0); 700 OUT_RING(0x0);
700 ADVANCE_RING(); 701 ADVANCE_RING();
@@ -766,8 +767,8 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
766 } 767 }
767 768
768 BEGIN_RING(2); 769 BEGIN_RING(2);
769 OUT_RING(CP_PACKET0(RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0)); 770 OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) );
770 OUT_RING(dev_priv->scratch_ages[header.scratch.reg]); 771 OUT_RING( dev_priv->scratch_ages[header.scratch.reg] );
771 ADVANCE_RING(); 772 ADVANCE_RING();
772 773
773 return 0; 774 return 0;
diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h
index ecda760ae8c0..3ae57ecc7afd 100644
--- a/drivers/char/drm/r300_reg.h
+++ b/drivers/char/drm/r300_reg.h
@@ -47,12 +47,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
47# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 47# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28
48 48
49/* 49/*
50This file contains registers and constants for the R300. They have been 50 * This file contains registers and constants for the R300. They have been
51found mostly by examining command buffers captured using glxtest, as well 51 * found mostly by examining command buffers captured using glxtest, as well
52as by extrapolating some known registers and constants from the R200. 52 * as by extrapolating some known registers and constants from the R200.
53 53 * I am fairly certain that they are correct unless stated otherwise
54I am fairly certain that they are correct unless stated otherwise in comments. 54 * in comments.
55*/ 55 */
56 56
57#define R300_SE_VPORT_XSCALE 0x1D98 57#define R300_SE_VPORT_XSCALE 0x1D98
58#define R300_SE_VPORT_XOFFSET 0x1D9C 58#define R300_SE_VPORT_XOFFSET 0x1D9C
@@ -61,49 +61,60 @@ I am fairly certain that they are correct unless stated otherwise in comments.
61#define R300_SE_VPORT_ZSCALE 0x1DA8 61#define R300_SE_VPORT_ZSCALE 0x1DA8
62#define R300_SE_VPORT_ZOFFSET 0x1DAC 62#define R300_SE_VPORT_ZOFFSET 0x1DAC
63 63
64/* This register is written directly and also starts data section in many 3d CP_PACKET3's */
65#define R300_VAP_VF_CNTL 0x2084
66 64
67# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0 65/*
68# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0) 66 * Vertex Array Processing (VAP) Control
69# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0) 67 * Stolen from r200 code from Christoph Brill (It's a guess!)
70# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0) 68 */
71# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0) 69#define R300_VAP_CNTL 0x2080
72# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0) 70
73# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0) 71/* This register is written directly and also starts data section
74# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0) 72 * in many 3d CP_PACKET3's
75# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0) 73 */
76# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0) 74#define R300_VAP_VF_CNTL 0x2084
77# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0) 75# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0
78# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0) 76# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0)
79 77# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0)
80# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4 78# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0)
81 /* State based - direct writes to registers trigger vertex generation */ 79# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0)
82# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4) 80# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0)
83# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4) 81# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0)
84# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4) 82# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)
85# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4) 83# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0)
86 84# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0)
87 /* I don't think I saw these three used.. */ 85# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0)
88# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6 86# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0)
89# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9 87
90# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10 88# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4
91 89 /* State based - direct writes to registers trigger vertex
92 /* index size - when not set the indices are assumed to be 16 bit */ 90 generation */
93# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) 91# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)
94 /* number of vertices */ 92# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4)
95# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 93# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)
94# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)
95
96 /* I don't think I saw these three used.. */
97# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6
98# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9
99# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10
100
101 /* index size - when not set the indices are assumed to be 16 bit */
102# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)
103 /* number of vertices */
104# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
96 105
97/* BEGIN: Wild guesses */ 106/* BEGIN: Wild guesses */
98#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 107#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090
99# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) 108# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
100# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1) 109# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1)
101# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */ 110# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */
102# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */ 111# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */
103# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */ 112# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */
104# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ 113# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */
105 114
106#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 115#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094
116 /* each of the following is 3 bits wide, specifies number
117 of components */
107# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 118# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
108# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 119# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
109# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 120# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
@@ -112,7 +123,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
112# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 123# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
113# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 124# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
114# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 125# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
115/* END */ 126/* END: Wild guesses */
116 127
117#define R300_SE_VTE_CNTL 0x20b0 128#define R300_SE_VTE_CNTL 0x20b0
118# define R300_VPORT_X_SCALE_ENA 0x00000001 129# define R300_VPORT_X_SCALE_ENA 0x00000001
@@ -128,43 +139,54 @@ I am fairly certain that they are correct unless stated otherwise in comments.
128# define R300_VTX_ST_DENORMALIZED 0x00001000 139# define R300_VTX_ST_DENORMALIZED 0x00001000
129 140
130/* BEGIN: Vertex data assembly - lots of uncertainties */ 141/* BEGIN: Vertex data assembly - lots of uncertainties */
142
143/* gap */
144
145#define R300_VAP_CNTL_STATUS 0x2140
146# define R300_VC_NO_SWAP (0 << 0)
147# define R300_VC_16BIT_SWAP (1 << 0)
148# define R300_VC_32BIT_SWAP (2 << 0)
149# define R300_VAP_TCL_BYPASS (1 << 8)
150
131/* gap */ 151/* gap */
152
132/* Where do we get our vertex data? 153/* Where do we get our vertex data?
133// 154 *
134// Vertex data either comes either from immediate mode registers or from 155 * Vertex data either comes either from immediate mode registers or from
135// vertex arrays. 156 * vertex arrays.
136// There appears to be no mixed mode (though we can force the pitch of 157 * There appears to be no mixed mode (though we can force the pitch of
137// vertex arrays to 0, effectively reusing the same element over and over 158 * vertex arrays to 0, effectively reusing the same element over and over
138// again). 159 * again).
139// 160 *
140// Immediate mode is controlled by the INPUT_CNTL registers. I am not sure 161 * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
141// if these registers influence vertex array processing. 162 * if these registers influence vertex array processing.
142// 163 *
143// Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3. 164 * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
144// 165 *
145// In both cases, vertex attributes are then passed through INPUT_ROUTE. 166 * In both cases, vertex attributes are then passed through INPUT_ROUTE.
146 167 *
147// Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data 168 * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
148// into the vertex processor's input registers. 169 * into the vertex processor's input registers.
149// The first word routes the first input, the second word the second, etc. 170 * The first word routes the first input, the second word the second, etc.
150// The corresponding input is routed into the register with the given index. 171 * The corresponding input is routed into the register with the given index.
151// The list is ended by a word with INPUT_ROUTE_END set. 172 * The list is ended by a word with INPUT_ROUTE_END set.
152// 173 *
153// Always set COMPONENTS_4 in immediate mode. */ 174 * Always set COMPONENTS_4 in immediate mode.
175 */
154 176
155#define R300_VAP_INPUT_ROUTE_0_0 0x2150 177#define R300_VAP_INPUT_ROUTE_0_0 0x2150
156# define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0) 178# define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0)
157# define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0) 179# define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0)
158# define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0) 180# define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0)
159# define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0) 181# define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0)
160# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */ 182# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */
161# define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8 183# define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8
162# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */ 184# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */
163# define R300_VAP_INPUT_ROUTE_END (1 << 13) 185# define R300_VAP_INPUT_ROUTE_END (1 << 13)
164# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */ 186# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */
165# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */ 187# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */
166# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */ 188# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */
167# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */ 189# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */
168#define R300_VAP_INPUT_ROUTE_0_1 0x2154 190#define R300_VAP_INPUT_ROUTE_0_1 0x2154
169#define R300_VAP_INPUT_ROUTE_0_2 0x2158 191#define R300_VAP_INPUT_ROUTE_0_2 0x2158
170#define R300_VAP_INPUT_ROUTE_0_3 0x215C 192#define R300_VAP_INPUT_ROUTE_0_3 0x215C
@@ -174,10 +196,12 @@ I am fairly certain that they are correct unless stated otherwise in comments.
174#define R300_VAP_INPUT_ROUTE_0_7 0x216C 196#define R300_VAP_INPUT_ROUTE_0_7 0x216C
175 197
176/* gap */ 198/* gap */
199
177/* Notes: 200/* Notes:
178// - always set up to produce at least two attributes: 201 * - always set up to produce at least two attributes:
179// if vertex program uses only position, fglrx will set normal, too 202 * if vertex program uses only position, fglrx will set normal, too
180// - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal */ 203 * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
204 */
181#define R300_VAP_INPUT_CNTL_0 0x2180 205#define R300_VAP_INPUT_CNTL_0 0x2180
182# define R300_INPUT_CNTL_0_COLOR 0x00000001 206# define R300_INPUT_CNTL_0_COLOR 0x00000001
183#define R300_VAP_INPUT_CNTL_1 0x2184 207#define R300_VAP_INPUT_CNTL_1 0x2184
@@ -186,20 +210,22 @@ I am fairly certain that they are correct unless stated otherwise in comments.
186# define R300_INPUT_CNTL_COLOR 0x00000004 210# define R300_INPUT_CNTL_COLOR 0x00000004
187# define R300_INPUT_CNTL_TC0 0x00000400 211# define R300_INPUT_CNTL_TC0 0x00000400
188# define R300_INPUT_CNTL_TC1 0x00000800 212# define R300_INPUT_CNTL_TC1 0x00000800
189# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ 213# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */
190# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ 214# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */
191# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ 215# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */
192# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ 216# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */
193# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ 217# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */
194# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ 218# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */
195 219
196/* gap */ 220/* gap */
221
197/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 222/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
198// are set to a swizzling bit pattern, other words are 0. 223 * are set to a swizzling bit pattern, other words are 0.
199// 224 *
200// In immediate mode, the pattern is always set to xyzw. In vertex array 225 * In immediate mode, the pattern is always set to xyzw. In vertex array
201// mode, the swizzling pattern is e.g. used to set zw components in texture 226 * mode, the swizzling pattern is e.g. used to set zw components in texture
202// coordinates with only tweo components. */ 227 * coordinates with only tweo components.
228 */
203#define R300_VAP_INPUT_ROUTE_1_0 0x21E0 229#define R300_VAP_INPUT_ROUTE_1_0 0x21E0
204# define R300_INPUT_ROUTE_SELECT_X 0 230# define R300_INPUT_ROUTE_SELECT_X 0
205# define R300_INPUT_ROUTE_SELECT_Y 1 231# define R300_INPUT_ROUTE_SELECT_Y 1
@@ -208,11 +234,11 @@ I am fairly certain that they are correct unless stated otherwise in comments.
208# define R300_INPUT_ROUTE_SELECT_ZERO 4 234# define R300_INPUT_ROUTE_SELECT_ZERO 4
209# define R300_INPUT_ROUTE_SELECT_ONE 5 235# define R300_INPUT_ROUTE_SELECT_ONE 5
210# define R300_INPUT_ROUTE_SELECT_MASK 7 236# define R300_INPUT_ROUTE_SELECT_MASK 7
211# define R300_INPUT_ROUTE_X_SHIFT 0 237# define R300_INPUT_ROUTE_X_SHIFT 0
212# define R300_INPUT_ROUTE_Y_SHIFT 3 238# define R300_INPUT_ROUTE_Y_SHIFT 3
213# define R300_INPUT_ROUTE_Z_SHIFT 6 239# define R300_INPUT_ROUTE_Z_SHIFT 6
214# define R300_INPUT_ROUTE_W_SHIFT 9 240# define R300_INPUT_ROUTE_W_SHIFT 9
215# define R300_INPUT_ROUTE_ENABLE (15 << 12) 241# define R300_INPUT_ROUTE_ENABLE (15 << 12)
216#define R300_VAP_INPUT_ROUTE_1_1 0x21E4 242#define R300_VAP_INPUT_ROUTE_1_1 0x21E4
217#define R300_VAP_INPUT_ROUTE_1_2 0x21E8 243#define R300_VAP_INPUT_ROUTE_1_2 0x21E8
218#define R300_VAP_INPUT_ROUTE_1_3 0x21EC 244#define R300_VAP_INPUT_ROUTE_1_3 0x21EC
@@ -221,79 +247,107 @@ I am fairly certain that they are correct unless stated otherwise in comments.
221#define R300_VAP_INPUT_ROUTE_1_6 0x21F8 247#define R300_VAP_INPUT_ROUTE_1_6 0x21F8
222#define R300_VAP_INPUT_ROUTE_1_7 0x21FC 248#define R300_VAP_INPUT_ROUTE_1_7 0x21FC
223 249
224/* END */ 250/* END: Vertex data assembly */
225 251
226/* gap */ 252/* gap */
227/* BEGIN: Upload vertex program and data 253
228// The programmable vertex shader unit has a memory bank of unknown size 254/* BEGIN: Upload vertex program and data */
229// that can be written to in 16 byte units by writing the address into 255
230// UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs). 256/*
231// 257 * The programmable vertex shader unit has a memory bank of unknown size
232// Pointers into the memory bank are always in multiples of 16 bytes. 258 * that can be written to in 16 byte units by writing the address into
233// 259 * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
234// The memory bank is divided into areas with fixed meaning. 260 *
235// 261 * Pointers into the memory bank are always in multiples of 16 bytes.
236// Starting at address UPLOAD_PROGRAM: Vertex program instructions. 262 *
237// Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB), 263 * The memory bank is divided into areas with fixed meaning.
238// whereas the difference between known addresses suggests size 512. 264 *
239// 265 * Starting at address UPLOAD_PROGRAM: Vertex program instructions.
240// Starting at address UPLOAD_PARAMETERS: Vertex program parameters. 266 * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
241// Native reported limits and the VPI layout suggest size 256, whereas 267 * whereas the difference between known addresses suggests size 512.
242// difference between known addresses suggests size 512. 268 *
243// 269 * Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
244// At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the 270 * Native reported limits and the VPI layout suggest size 256, whereas
245// floating point pointsize. The exact purpose of this state is uncertain, 271 * difference between known addresses suggests size 512.
246// as there is also the R300_RE_POINTSIZE register. 272 *
247// 273 * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
248// Multiple vertex programs and parameter sets can be loaded at once, 274 * floating point pointsize. The exact purpose of this state is uncertain,
249// which could explain the size discrepancy. */ 275 * as there is also the R300_RE_POINTSIZE register.
276 *
277 * Multiple vertex programs and parameter sets can be loaded at once,
278 * which could explain the size discrepancy.
279 */
250#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 280#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
251# define R300_PVS_UPLOAD_PROGRAM 0x00000000 281# define R300_PVS_UPLOAD_PROGRAM 0x00000000
252# define R300_PVS_UPLOAD_PARAMETERS 0x00000200 282# define R300_PVS_UPLOAD_PARAMETERS 0x00000200
253# define R300_PVS_UPLOAD_POINTSIZE 0x00000406 283# define R300_PVS_UPLOAD_POINTSIZE 0x00000406
284
254/* gap */ 285/* gap */
286
255#define R300_VAP_PVS_UPLOAD_DATA 0x2208 287#define R300_VAP_PVS_UPLOAD_DATA 0x2208
256/* END */ 288
289/* END: Upload vertex program and data */
257 290
258/* gap */ 291/* gap */
292
259/* I do not know the purpose of this register. However, I do know that 293/* I do not know the purpose of this register. However, I do know that
260// it is set to 221C_CLEAR for clear operations and to 221C_NORMAL 294 * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
261// for normal rendering. */ 295 * for normal rendering.
296 */
262#define R300_VAP_UNKNOWN_221C 0x221C 297#define R300_VAP_UNKNOWN_221C 0x221C
263# define R300_221C_NORMAL 0x00000000 298# define R300_221C_NORMAL 0x00000000
264# define R300_221C_CLEAR 0x0001C000 299# define R300_221C_CLEAR 0x0001C000
265 300
301/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
302 * plane is per-pixel and the second plane is per-vertex.
303 *
304 * This was determined by experimentation alone but I believe it is correct.
305 *
306 * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest.
307 */
308#define R300_VAP_CLIP_X_0 0x2220
309#define R300_VAP_CLIP_X_1 0x2224
310#define R300_VAP_CLIP_Y_0 0x2228
311#define R300_VAP_CLIP_Y_1 0x2230
312
266/* gap */ 313/* gap */
314
267/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between 315/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between
268// rendering commands and overwriting vertex program parameters. 316 * rendering commands and overwriting vertex program parameters.
269// Therefore, I suspect writing zero to 0x2284 synchronizes the engine and 317 * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
270// avoids bugs caused by still running shaders reading bad data from memory. */ 318 * avoids bugs caused by still running shaders reading bad data from memory.
271#define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */ 319 */
320#define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */
272 321
273/* Absolutely no clue what this register is about. */ 322/* Absolutely no clue what this register is about. */
274#define R300_VAP_UNKNOWN_2288 0x2288 323#define R300_VAP_UNKNOWN_2288 0x2288
275# define R300_2288_R300 0x00750000 /* -- nh */ 324# define R300_2288_R300 0x00750000 /* -- nh */
276# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ 325# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
277 326
278/* gap */ 327/* gap */
328
279/* Addresses are relative to the vertex program instruction area of the 329/* Addresses are relative to the vertex program instruction area of the
280// memory bank. PROGRAM_END points to the last instruction of the active 330 * memory bank. PROGRAM_END points to the last instruction of the active
281// program 331 * program
282// 332 *
283// The meaning of the two UNKNOWN fields is obviously not known. However, 333 * The meaning of the two UNKNOWN fields is obviously not known. However,
284// experiments so far have shown that both *must* point to an instruction 334 * experiments so far have shown that both *must* point to an instruction
285// inside the vertex program, otherwise the GPU locks up. 335 * inside the vertex program, otherwise the GPU locks up.
286// fglrx usually sets CNTL_3_UNKNOWN to the end of the program and 336 *
287// CNTL_1_UNKNOWN points to instruction where last write to position takes place. 337 * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
288// Most likely this is used to ignore rest of the program in cases where group of verts arent visible. 338 * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to
289// For some reason this "section" is sometimes accepted other instruction that have 339 * position takes place.
290// no relationship with position calculations. 340 *
291*/ 341 * Most likely this is used to ignore rest of the program in cases
342 * where group of verts arent visible. For some reason this "section"
343 * is sometimes accepted other instruction that have no relationship with
344 * position calculations.
345 */
292#define R300_VAP_PVS_CNTL_1 0x22D0 346#define R300_VAP_PVS_CNTL_1 0x22D0
293# define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 347# define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0
294# define R300_PVS_CNTL_1_POS_END_SHIFT 10 348# define R300_PVS_CNTL_1_POS_END_SHIFT 10
295# define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20 349# define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20
296/* Addresses are relative to the vertex program parameters area. */ 350/* Addresses are relative the the vertex program parameters area. */
297#define R300_VAP_PVS_CNTL_2 0x22D4 351#define R300_VAP_PVS_CNTL_2 0x22D4
298# define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0 352# define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0
299# define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16 353# define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16
@@ -302,23 +356,26 @@ I am fairly certain that they are correct unless stated otherwise in comments.
302# define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0 356# define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0
303 357
304/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for 358/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
305// immediate vertices */ 359 * immediate vertices
360 */
306#define R300_VAP_VTX_COLOR_R 0x2464 361#define R300_VAP_VTX_COLOR_R 0x2464
307#define R300_VAP_VTX_COLOR_G 0x2468 362#define R300_VAP_VTX_COLOR_G 0x2468
308#define R300_VAP_VTX_COLOR_B 0x246C 363#define R300_VAP_VTX_COLOR_B 0x246C
309#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ 364#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */
310#define R300_VAP_VTX_POS_0_Y_1 0x2494 365#define R300_VAP_VTX_POS_0_Y_1 0x2494
311#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ 366#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */
312#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ 367#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */
313#define R300_VAP_VTX_POS_0_Y_2 0x24A4 368#define R300_VAP_VTX_POS_0_Y_2 0x24A4
314#define R300_VAP_VTX_POS_0_Z_2 0x24A8 369#define R300_VAP_VTX_POS_0_Z_2 0x24A8
315#define R300_VAP_VTX_END_OF_PKT 0x24AC /* write 0 to indicate end of packet? */ 370/* write 0 to indicate end of packet? */
371#define R300_VAP_VTX_END_OF_PKT 0x24AC
316 372
317/* gap */ 373/* gap */
318 374
319/* These are values from r300_reg/r300_reg.h - they are known to be correct 375/* These are values from r300_reg/r300_reg.h - they are known to be correct
320 and are here so we can use one register file instead of several 376 * and are here so we can use one register file instead of several
321 - Vladimir */ 377 * - Vladimir
378 */
322#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000 379#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000
323# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) 380# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0)
324# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) 381# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
@@ -341,14 +398,16 @@ I am fairly certain that they are correct unless stated otherwise in comments.
341# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 398# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
342 399
343/* UNK30 seems to enables point to quad transformation on textures 400/* UNK30 seems to enables point to quad transformation on textures
344 (or something closely related to that). 401 * (or something closely related to that).
345 This bit is rather fatal at the time being due to lackings at pixel shader side */ 402 * This bit is rather fatal at the time being due to lackings at pixel
403 * shader side
404 */
346#define R300_GB_ENABLE 0x4008 405#define R300_GB_ENABLE 0x4008
347# define R300_GB_POINT_STUFF_ENABLE (1<<0) 406# define R300_GB_POINT_STUFF_ENABLE (1<<0)
348# define R300_GB_LINE_STUFF_ENABLE (1<<1) 407# define R300_GB_LINE_STUFF_ENABLE (1<<1)
349# define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2) 408# define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2)
350# define R300_GB_STENCIL_AUTO_ENABLE (1<<4) 409# define R300_GB_STENCIL_AUTO_ENABLE (1<<4)
351# define R300_GB_UNK30 (1<<30) 410# define R300_GB_UNK31 (1<<31)
352 /* each of the following is 2 bits wide */ 411 /* each of the following is 2 bits wide */
353#define R300_GB_TEX_REPLICATE 0 412#define R300_GB_TEX_REPLICATE 0
354#define R300_GB_TEX_ST 1 413#define R300_GB_TEX_ST 1
@@ -383,11 +442,13 @@ I am fairly certain that they are correct unless stated otherwise in comments.
383# define R300_GB_MSPOS1__MS_Y5_SHIFT 20 442# define R300_GB_MSPOS1__MS_Y5_SHIFT 20
384# define R300_GB_MSPOS1__MSBD1 24 443# define R300_GB_MSPOS1__MSBD1 24
385 444
445
386#define R300_GB_TILE_CONFIG 0x4018 446#define R300_GB_TILE_CONFIG 0x4018
387# define R300_GB_TILE_ENABLE (1<<0) 447# define R300_GB_TILE_ENABLE (1<<0)
388# define R300_GB_TILE_PIPE_COUNT_RV300 0 448# define R300_GB_TILE_PIPE_COUNT_RV300 0
389# define R300_GB_TILE_PIPE_COUNT_R300 (3<<1) 449# define R300_GB_TILE_PIPE_COUNT_R300 (3<<1)
390# define R300_GB_TILE_PIPE_COUNT_R420 (7<<1) 450# define R300_GB_TILE_PIPE_COUNT_R420 (7<<1)
451# define R300_GB_TILE_PIPE_COUNT_RV410 (3<<1)
391# define R300_GB_TILE_SIZE_8 0 452# define R300_GB_TILE_SIZE_8 0
392# define R300_GB_TILE_SIZE_16 (1<<4) 453# define R300_GB_TILE_SIZE_16 (1<<4)
393# define R300_GB_TILE_SIZE_32 (2<<4) 454# define R300_GB_TILE_SIZE_32 (2<<4)
@@ -442,17 +503,18 @@ I am fairly certain that they are correct unless stated otherwise in comments.
442# define R300_GB_W_SELECT_1 (1<<4) 503# define R300_GB_W_SELECT_1 (1<<4)
443 504
444#define R300_GB_AA_CONFIG 0x4020 505#define R300_GB_AA_CONFIG 0x4020
506# define R300_AA_DISABLE 0x00
445# define R300_AA_ENABLE 0x01 507# define R300_AA_ENABLE 0x01
446# define R300_AA_SUBSAMPLES_2 0 508# define R300_AA_SUBSAMPLES_2 0
447# define R300_AA_SUBSAMPLES_3 (1<<1) 509# define R300_AA_SUBSAMPLES_3 (1<<1)
448# define R300_AA_SUBSAMPLES_4 (2<<1) 510# define R300_AA_SUBSAMPLES_4 (2<<1)
449# define R300_AA_SUBSAMPLES_6 (3<<1) 511# define R300_AA_SUBSAMPLES_6 (3<<1)
450 512
451/* END */
452
453/* gap */ 513/* gap */
514
454/* Zero to flush caches. */ 515/* Zero to flush caches. */
455#define R300_TX_CNTL 0x4100 516#define R300_TX_CNTL 0x4100
517#define R300_TX_FLUSH 0x0
456 518
457/* The upper enable bits are guessed, based on fglrx reported limits. */ 519/* The upper enable bits are guessed, based on fglrx reported limits. */
458#define R300_TX_ENABLE 0x4104 520#define R300_TX_ENABLE 0x4104
@@ -474,24 +536,25 @@ I am fairly certain that they are correct unless stated otherwise in comments.
474# define R300_TX_ENABLE_15 (1 << 15) 536# define R300_TX_ENABLE_15 (1 << 15)
475 537
476/* The pointsize is given in multiples of 6. The pointsize can be 538/* The pointsize is given in multiples of 6. The pointsize can be
477// enormous: Clear() renders a single point that fills the entire 539 * enormous: Clear() renders a single point that fills the entire
478// framebuffer. */ 540 * framebuffer.
541 */
479#define R300_RE_POINTSIZE 0x421C 542#define R300_RE_POINTSIZE 0x421C
480# define R300_POINTSIZE_Y_SHIFT 0 543# define R300_POINTSIZE_Y_SHIFT 0
481# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */ 544# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */
482# define R300_POINTSIZE_X_SHIFT 16 545# define R300_POINTSIZE_X_SHIFT 16
483# define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */ 546# define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */
484# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) 547# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6)
485 548
486/* The line width is given in multiples of 6. 549/* The line width is given in multiples of 6.
487 In default mode lines are classified as vertical lines. 550 * In default mode lines are classified as vertical lines.
488 HO: horizontal 551 * HO: horizontal
489 VE: vertical or horizontal 552 * VE: vertical or horizontal
490 HO & VE: no classification 553 * HO & VE: no classification
491*/ 554 */
492#define R300_RE_LINE_CNT 0x4234 555#define R300_RE_LINE_CNT 0x4234
493# define R300_LINESIZE_SHIFT 0 556# define R300_LINESIZE_SHIFT 0
494# define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */ 557# define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */
495# define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6) 558# define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6)
496# define R300_LINE_CNT_HO (1 << 16) 559# define R300_LINE_CNT_HO (1 << 16)
497# define R300_LINE_CNT_VE (1 << 17) 560# define R300_LINE_CNT_VE (1 << 17)
@@ -499,6 +562,9 @@ I am fairly certain that they are correct unless stated otherwise in comments.
499/* Some sort of scale or clamp value for texcoordless textures. */ 562/* Some sort of scale or clamp value for texcoordless textures. */
500#define R300_RE_UNK4238 0x4238 563#define R300_RE_UNK4238 0x4238
501 564
565/* Something shade related */
566#define R300_RE_SHADE 0x4274
567
502#define R300_RE_SHADE_MODEL 0x4278 568#define R300_RE_SHADE_MODEL 0x4278
503# define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa 569# define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa
504# define R300_RE_SHADE_MODEL_FLAT 0x39595 570# define R300_RE_SHADE_MODEL_FLAT 0x39595
@@ -513,24 +579,31 @@ I am fairly certain that they are correct unless stated otherwise in comments.
513# define R300_PM_BACK_LINE (1 << 7) 579# define R300_PM_BACK_LINE (1 << 7)
514# define R300_PM_BACK_FILL (1 << 8) 580# define R300_PM_BACK_FILL (1 << 8)
515 581
582/* Fog parameters */
583#define R300_RE_FOG_SCALE 0x4294
584#define R300_RE_FOG_START 0x4298
585
516/* Not sure why there are duplicate of factor and constant values. 586/* Not sure why there are duplicate of factor and constant values.
517 My best guess so far is that there are seperate zbiases for test and write. 587 * My best guess so far is that there are seperate zbiases for test and write.
518 Ordering might be wrong. 588 * Ordering might be wrong.
519 Some of the tests indicate that fgl has a fallback implementation of zbias 589 * Some of the tests indicate that fgl has a fallback implementation of zbias
520 via pixel shaders. */ 590 * via pixel shaders.
591 */
592#define R300_RE_ZBIAS_CNTL 0x42A0 /* GUESS */
521#define R300_RE_ZBIAS_T_FACTOR 0x42A4 593#define R300_RE_ZBIAS_T_FACTOR 0x42A4
522#define R300_RE_ZBIAS_T_CONSTANT 0x42A8 594#define R300_RE_ZBIAS_T_CONSTANT 0x42A8
523#define R300_RE_ZBIAS_W_FACTOR 0x42AC 595#define R300_RE_ZBIAS_W_FACTOR 0x42AC
524#define R300_RE_ZBIAS_W_CONSTANT 0x42B0 596#define R300_RE_ZBIAS_W_CONSTANT 0x42B0
525 597
526/* This register needs to be set to (1<<1) for RV350 to correctly 598/* This register needs to be set to (1<<1) for RV350 to correctly
527 perform depth test (see --vb-triangles in r300_demo) 599 * perform depth test (see --vb-triangles in r300_demo)
528 Don't know about other chips. - Vladimir 600 * Don't know about other chips. - Vladimir
529 This is set to 3 when GL_POLYGON_OFFSET_FILL is on. 601 * This is set to 3 when GL_POLYGON_OFFSET_FILL is on.
530 My guess is that there are two bits for each zbias primitive (FILL, LINE, POINT). 602 * My guess is that there are two bits for each zbias primitive
531 One to enable depth test and one for depth write. 603 * (FILL, LINE, POINT).
532 Yet this doesnt explain why depth writes work ... 604 * One to enable depth test and one for depth write.
533 */ 605 * Yet this doesnt explain why depth writes work ...
606 */
534#define R300_RE_OCCLUSION_CNTL 0x42B4 607#define R300_RE_OCCLUSION_CNTL 0x42B4
535# define R300_OCCLUSION_ON (1<<1) 608# define R300_OCCLUSION_ON (1<<1)
536 609
@@ -540,30 +613,38 @@ I am fairly certain that they are correct unless stated otherwise in comments.
540# define R300_FRONT_FACE_CCW (0 << 2) 613# define R300_FRONT_FACE_CCW (0 << 2)
541# define R300_FRONT_FACE_CW (1 << 2) 614# define R300_FRONT_FACE_CW (1 << 2)
542 615
543/* BEGIN: Rasterization / Interpolators - many guesses 616
544// 0_UNKNOWN_18 has always been set except for clear operations. 617/* BEGIN: Rasterization / Interpolators - many guesses */
545// TC_CNT is the number of incoming texture coordinate sets (i.e. it depends 618
546// on the vertex program, *not* the fragment program) */ 619/* 0_UNKNOWN_18 has always been set except for clear operations.
620 * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
621 * on the vertex program, *not* the fragment program)
622 */
547#define R300_RS_CNTL_0 0x4300 623#define R300_RS_CNTL_0 0x4300
548# define R300_RS_CNTL_TC_CNT_SHIFT 2 624# define R300_RS_CNTL_TC_CNT_SHIFT 2
549# define R300_RS_CNTL_TC_CNT_MASK (7 << 2) 625# define R300_RS_CNTL_TC_CNT_MASK (7 << 2)
550# define R300_RS_CNTL_CI_CNT_SHIFT 7 /* number of color interpolators used */ 626 /* number of color interpolators used */
627# define R300_RS_CNTL_CI_CNT_SHIFT 7
551# define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18) 628# define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18)
552/* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register. */ 629 /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n
630 register. */
553#define R300_RS_CNTL_1 0x4304 631#define R300_RS_CNTL_1 0x4304
554 632
555/* gap */ 633/* gap */
634
556/* Only used for texture coordinates. 635/* Only used for texture coordinates.
557// Use the source field to route texture coordinate input from the vertex program 636 * Use the source field to route texture coordinate input from the
558// to the desired interpolator. Note that the source field is relative to the 637 * vertex program to the desired interpolator. Note that the source
559// outputs the vertex program *actually* writes. If a vertex program only writes 638 * field is relative to the outputs the vertex program *actually*
560// texcoord[1], this will be source index 0. 639 * writes. If a vertex program only writes texcoord[1], this will
561// Set INTERP_USED on all interpolators that produce data used by the 640 * be source index 0.
562// fragment program. INTERP_USED looks like a swizzling mask, but 641 * Set INTERP_USED on all interpolators that produce data used by
563// I haven't seen it used that way. 642 * the fragment program. INTERP_USED looks like a swizzling mask,
564// 643 * but I haven't seen it used that way.
565// Note: The _UNKNOWN constants are always set in their respective register. 644 *
566// I don't know if this is necessary. */ 645 * Note: The _UNKNOWN constants are always set in their respective
646 * register. I don't know if this is necessary.
647 */
567#define R300_RS_INTERP_0 0x4310 648#define R300_RS_INTERP_0 0x4310
568#define R300_RS_INTERP_1 0x4314 649#define R300_RS_INTERP_1 0x4314
569# define R300_RS_INTERP_1_UNKNOWN 0x40 650# define R300_RS_INTERP_1_UNKNOWN 0x40
@@ -580,54 +661,63 @@ I am fairly certain that they are correct unless stated otherwise in comments.
580# define R300_RS_INTERP_USED 0x00D10000 661# define R300_RS_INTERP_USED 0x00D10000
581 662
582/* These DWORDs control how vertex data is routed into fragment program 663/* These DWORDs control how vertex data is routed into fragment program
583// registers, after interpolators. */ 664 * registers, after interpolators.
665 */
584#define R300_RS_ROUTE_0 0x4330 666#define R300_RS_ROUTE_0 0x4330
585#define R300_RS_ROUTE_1 0x4334 667#define R300_RS_ROUTE_1 0x4334
586#define R300_RS_ROUTE_2 0x4338 668#define R300_RS_ROUTE_2 0x4338
587#define R300_RS_ROUTE_3 0x433C /* GUESS */ 669#define R300_RS_ROUTE_3 0x433C /* GUESS */
588#define R300_RS_ROUTE_4 0x4340 /* GUESS */ 670#define R300_RS_ROUTE_4 0x4340 /* GUESS */
589#define R300_RS_ROUTE_5 0x4344 /* GUESS */ 671#define R300_RS_ROUTE_5 0x4344 /* GUESS */
590#define R300_RS_ROUTE_6 0x4348 /* GUESS */ 672#define R300_RS_ROUTE_6 0x4348 /* GUESS */
591#define R300_RS_ROUTE_7 0x434C /* GUESS */ 673#define R300_RS_ROUTE_7 0x434C /* GUESS */
592# define R300_RS_ROUTE_SOURCE_INTERP_0 0 674# define R300_RS_ROUTE_SOURCE_INTERP_0 0
593# define R300_RS_ROUTE_SOURCE_INTERP_1 1 675# define R300_RS_ROUTE_SOURCE_INTERP_1 1
594# define R300_RS_ROUTE_SOURCE_INTERP_2 2 676# define R300_RS_ROUTE_SOURCE_INTERP_2 2
595# define R300_RS_ROUTE_SOURCE_INTERP_3 3 677# define R300_RS_ROUTE_SOURCE_INTERP_3 3
596# define R300_RS_ROUTE_SOURCE_INTERP_4 4 678# define R300_RS_ROUTE_SOURCE_INTERP_4 4
597# define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */ 679# define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */
598# define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */ 680# define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */
599# define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */ 681# define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */
600# define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */ 682# define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */
601# define R300_RS_ROUTE_DEST_SHIFT 6 683# define R300_RS_ROUTE_DEST_SHIFT 6
602# define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */ 684# define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */
603 685
604/* Special handling for color: When the fragment program uses color, 686/* Special handling for color: When the fragment program uses color,
605// the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the 687 * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
606// color register index. */ 688 * color register index.
689 *
690 * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any
691 * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state.
692 * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly
693 * correct or not. - Oliver.
694 */
607# define R300_RS_ROUTE_0_COLOR (1 << 14) 695# define R300_RS_ROUTE_0_COLOR (1 << 14)
608# define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17 696# define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17
609# define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */ 697# define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */
610/* As above, but for secondary color */ 698/* As above, but for secondary color */
611# define R300_RS_ROUTE_1_COLOR1 (1 << 14) 699# define R300_RS_ROUTE_1_COLOR1 (1 << 14)
612# define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17 700# define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17
613# define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17) 701# define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17)
614# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) 702# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)
615/* END */ 703/* END: Rasterization / Interpolators - many guesses */
616 704
617/* BEGIN: Scissors and cliprects 705/* BEGIN: Scissors and cliprects */
618// There are four clipping rectangles. Their corner coordinates are inclusive. 706
619// Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending 707/* There are four clipping rectangles. Their corner coordinates are inclusive.
620// on whether the pixel is inside cliprects 0-3, respectively. For example, 708 * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
621// if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned 709 * on whether the pixel is inside cliprects 0-3, respectively. For example,
622// the number 3 (binary 0011). 710 * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
623// Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, 711 * the number 3 (binary 0011).
624// the pixel is rasterized. 712 * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,
625// 713 * the pixel is rasterized.
626// In addition to this, there is a scissors rectangle. Only pixels inside the 714 *
627// scissors rectangle are drawn. (coordinates are inclusive) 715 * In addition to this, there is a scissors rectangle. Only pixels inside the
628// 716 * scissors rectangle are drawn. (coordinates are inclusive)
629// For some reason, the top-left corner of the framebuffer is at (1440, 1440) 717 *
630// for the purpose of clipping and scissors. */ 718 * For some reason, the top-left corner of the framebuffer is at (1440, 1440)
719 * for the purpose of clipping and scissors.
720 */
631#define R300_RE_CLIPRECT_TL_0 0x43B0 721#define R300_RE_CLIPRECT_TL_0 0x43B0
632#define R300_RE_CLIPRECT_BR_0 0x43B4 722#define R300_RE_CLIPRECT_BR_0 0x43B4
633#define R300_RE_CLIPRECT_TL_1 0x43B8 723#define R300_RE_CLIPRECT_TL_1 0x43B8
@@ -661,6 +751,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
661# define R300_CLIP_3210 (1 << 15) 751# define R300_CLIP_3210 (1 << 15)
662 752
663/* gap */ 753/* gap */
754
664#define R300_RE_SCISSORS_TL 0x43E0 755#define R300_RE_SCISSORS_TL 0x43E0
665#define R300_RE_SCISSORS_BR 0x43E4 756#define R300_RE_SCISSORS_BR 0x43E4
666# define R300_SCISSORS_OFFSET 1440 757# define R300_SCISSORS_OFFSET 1440
@@ -668,12 +759,15 @@ I am fairly certain that they are correct unless stated otherwise in comments.
668# define R300_SCISSORS_X_MASK (0x1FFF << 0) 759# define R300_SCISSORS_X_MASK (0x1FFF << 0)
669# define R300_SCISSORS_Y_SHIFT 13 760# define R300_SCISSORS_Y_SHIFT 13
670# define R300_SCISSORS_Y_MASK (0x1FFF << 13) 761# define R300_SCISSORS_Y_MASK (0x1FFF << 13)
671/* END */ 762/* END: Scissors and cliprects */
672 763
673/* BEGIN: Texture specification 764/* BEGIN: Texture specification */
674// The texture specification dwords are grouped by meaning and not by texture unit. 765
675// This means that e.g. the offset for texture image unit N is found in register 766/*
676// TX_OFFSET_0 + (4*N) */ 767 * The texture specification dwords are grouped by meaning and not by texture
768 * unit. This means that e.g. the offset for texture image unit N is found in
769 * register TX_OFFSET_0 + (4*N)
770 */
677#define R300_TX_FILTER_0 0x4400 771#define R300_TX_FILTER_0 0x4400
678# define R300_TX_REPEAT 0 772# define R300_TX_REPEAT 0
679# define R300_TX_MIRRORED 1 773# define R300_TX_MIRRORED 1
@@ -697,13 +791,14 @@ I am fairly certain that they are correct unless stated otherwise in comments.
697# define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11) 791# define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11)
698 792
699/* NOTE: NEAREST doesnt seem to exist. 793/* NOTE: NEAREST doesnt seem to exist.
700 Im not seting MAG_FILTER_MASK and (3 << 11) on for all 794 * Im not seting MAG_FILTER_MASK and (3 << 11) on for all
701 anisotropy modes because that would void selected mag filter */ 795 * anisotropy modes because that would void selected mag filter
702# define R300_TX_MIN_FILTER_ANISO_NEAREST ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) 796 */
703# define R300_TX_MIN_FILTER_ANISO_LINEAR ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) 797# define R300_TX_MIN_FILTER_ANISO_NEAREST (0 << 13)
704# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST ((1 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) 798# define R300_TX_MIN_FILTER_ANISO_LINEAR (0 << 13)
705# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR ((2 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) 799# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (1 << 13)
706# define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) ) 800# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (2 << 13)
801# define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) )
707# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) 802# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21)
708# define R300_TX_MAX_ANISO_2_TO_1 (2 << 21) 803# define R300_TX_MAX_ANISO_2_TO_1 (2 << 21)
709# define R300_TX_MAX_ANISO_4_TO_1 (4 << 21) 804# define R300_TX_MAX_ANISO_4_TO_1 (4 << 21)
@@ -734,10 +829,10 @@ I am fairly certain that they are correct unless stated otherwise in comments.
734# define R300_TX_HEIGHTMASK_SHIFT 11 829# define R300_TX_HEIGHTMASK_SHIFT 11
735# define R300_TX_HEIGHTMASK_MASK (2047 << 11) 830# define R300_TX_HEIGHTMASK_MASK (2047 << 11)
736# define R300_TX_UNK23 (1 << 23) 831# define R300_TX_UNK23 (1 << 23)
737# define R300_TX_SIZE_SHIFT 26 /* largest of width, height */ 832# define R300_TX_MAX_MIP_LEVEL_SHIFT 26
738# define R300_TX_SIZE_MASK (15 << 26) 833# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26)
739# define R300_TX_SIZE_PROJECTED (1<<30) 834# define R300_TX_SIZE_PROJECTED (1<<30)
740# define R300_TX_SIZE_TXPITCH_EN (1<<31) 835# define R300_TX_SIZE_TXPITCH_EN (1<<31)
741#define R300_TX_FORMAT_0 0x44C0 836#define R300_TX_FORMAT_0 0x44C0
742 /* The interpretation of the format word by Wladimir van der Laan */ 837 /* The interpretation of the format word by Wladimir van der Laan */
743 /* The X, Y, Z and W refer to the layout of the components. 838 /* The X, Y, Z and W refer to the layout of the components.
@@ -761,11 +856,11 @@ I am fairly certain that they are correct unless stated otherwise in comments.
761# define R300_TX_FORMAT_DXT1 0xF 856# define R300_TX_FORMAT_DXT1 0xF
762# define R300_TX_FORMAT_DXT3 0x10 857# define R300_TX_FORMAT_DXT3 0x10
763# define R300_TX_FORMAT_DXT5 0x11 858# define R300_TX_FORMAT_DXT5 0x11
764# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ 859# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
765# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ 860# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
766# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ 861# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
767# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ 862# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
768 /* 0x16 - some 16 bit green format.. ?? */ 863 /* 0x16 - some 16 bit green format.. ?? */
769# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ 864# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */
770# define R300_TX_FORMAT_CUBIC_MAP (1 << 26) 865# define R300_TX_FORMAT_CUBIC_MAP (1 << 26)
771 866
@@ -793,23 +888,26 @@ I am fairly certain that they are correct unless stated otherwise in comments.
793# define R300_TX_FORMAT_W 3 888# define R300_TX_FORMAT_W 3
794# define R300_TX_FORMAT_ZERO 4 889# define R300_TX_FORMAT_ZERO 4
795# define R300_TX_FORMAT_ONE 5 890# define R300_TX_FORMAT_ONE 5
796# define R300_TX_FORMAT_CUT_Z 6 /* 2.0*Z, everything above 1.0 is set to 0.0 */ 891 /* 2.0*Z, everything above 1.0 is set to 0.0 */
797# define R300_TX_FORMAT_CUT_W 7 /* 2.0*W, everything above 1.0 is set to 0.0 */ 892# define R300_TX_FORMAT_CUT_Z 6
893 /* 2.0*W, everything above 1.0 is set to 0.0 */
894# define R300_TX_FORMAT_CUT_W 7
798 895
799# define R300_TX_FORMAT_B_SHIFT 18 896# define R300_TX_FORMAT_B_SHIFT 18
800# define R300_TX_FORMAT_G_SHIFT 15 897# define R300_TX_FORMAT_G_SHIFT 15
801# define R300_TX_FORMAT_R_SHIFT 12 898# define R300_TX_FORMAT_R_SHIFT 12
802# define R300_TX_FORMAT_A_SHIFT 9 899# define R300_TX_FORMAT_A_SHIFT 9
803 /* Convenience macro to take care of layout and swizzling */ 900 /* Convenience macro to take care of layout and swizzling */
804# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) (\ 901# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \
805 ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \ 902 ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \
806 | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \ 903 | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \
807 | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \ 904 | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \
808 | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \ 905 | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \
809 | (R300_TX_FORMAT_##FMT) \ 906 | (R300_TX_FORMAT_##FMT) \
810 ) 907 )
811 /* These can be ORed with result of R300_EASY_TX_FORMAT() */ 908 /* These can be ORed with result of R300_EASY_TX_FORMAT()
812 /* We don't really know what they do. Take values from a constant color ? */ 909 We don't really know what they do. Take values from a
910 constant color ? */
813# define R300_TX_FORMAT_CONST_X (1<<5) 911# define R300_TX_FORMAT_CONST_X (1<<5)
814# define R300_TX_FORMAT_CONST_Y (2<<5) 912# define R300_TX_FORMAT_CONST_Y (2<<5)
815# define R300_TX_FORMAT_CONST_Z (4<<5) 913# define R300_TX_FORMAT_CONST_Z (4<<5)
@@ -819,7 +917,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
819 917
820#define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */ 918#define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */
821#define R300_TX_OFFSET_0 0x4540 919#define R300_TX_OFFSET_0 0x4540
822/* BEGIN: Guess from R200 */ 920 /* BEGIN: Guess from R200 */
823# define R300_TXO_ENDIAN_NO_SWAP (0 << 0) 921# define R300_TXO_ENDIAN_NO_SWAP (0 << 0)
824# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) 922# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0)
825# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0) 923# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0)
@@ -828,53 +926,61 @@ I am fairly certain that they are correct unless stated otherwise in comments.
828# define R300_TXO_MICRO_TILE (1 << 3) 926# define R300_TXO_MICRO_TILE (1 << 3)
829# define R300_TXO_OFFSET_MASK 0xffffffe0 927# define R300_TXO_OFFSET_MASK 0xffffffe0
830# define R300_TXO_OFFSET_SHIFT 5 928# define R300_TXO_OFFSET_SHIFT 5
831/* END */ 929 /* END: Guess from R200 */
832#define R300_TX_CHROMA_KEY_0 0x4580 /* 32 bit chroma key */ 930
833#define R300_TX_BORDER_COLOR_0 0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 } 931/* 32 bit chroma key */
834 932#define R300_TX_CHROMA_KEY_0 0x4580
835/* END */ 933/* ff00ff00 == { 0, 1.0, 0, 1.0 } */
836 934#define R300_TX_BORDER_COLOR_0 0x45C0
837/* BEGIN: Fragment program instruction set 935
838// Fragment programs are written directly into register space. 936/* END: Texture specification */
839// There are separate instruction streams for texture instructions and ALU 937
840// instructions. 938/* BEGIN: Fragment program instruction set */
841// In order to synchronize these streams, the program is divided into up 939
842// to 4 nodes. Each node begins with a number of TEX operations, followed 940/* Fragment programs are written directly into register space.
843// by a number of ALU operations. 941 * There are separate instruction streams for texture instructions and ALU
844// The first node can have zero TEX ops, all subsequent nodes must have at least 942 * instructions.
845// one TEX ops. 943 * In order to synchronize these streams, the program is divided into up
846// All nodes must have at least one ALU op. 944 * to 4 nodes. Each node begins with a number of TEX operations, followed
847// 945 * by a number of ALU operations.
848// The index of the last node is stored in PFS_CNTL_0: A value of 0 means 946 * The first node can have zero TEX ops, all subsequent nodes must have at
849// 1 node, a value of 3 means 4 nodes. 947 * least
850// The total amount of instructions is defined in PFS_CNTL_2. The offsets are 948 * one TEX ops.
851// offsets into the respective instruction streams, while *_END points to the 949 * All nodes must have at least one ALU op.
852// last instruction relative to this offset. */ 950 *
951 * The index of the last node is stored in PFS_CNTL_0: A value of 0 means
952 * 1 node, a value of 3 means 4 nodes.
953 * The total amount of instructions is defined in PFS_CNTL_2. The offsets are
954 * offsets into the respective instruction streams, while *_END points to the
955 * last instruction relative to this offset.
956 */
853#define R300_PFS_CNTL_0 0x4600 957#define R300_PFS_CNTL_0 0x4600
854# define R300_PFS_CNTL_LAST_NODES_SHIFT 0 958# define R300_PFS_CNTL_LAST_NODES_SHIFT 0
855# define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0) 959# define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0)
856# define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3) 960# define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3)
857#define R300_PFS_CNTL_1 0x4604 961#define R300_PFS_CNTL_1 0x4604
858/* There is an unshifted value here which has so far always been equal to the 962/* There is an unshifted value here which has so far always been equal to the
859// index of the highest used temporary register. */ 963 * index of the highest used temporary register.
964 */
860#define R300_PFS_CNTL_2 0x4608 965#define R300_PFS_CNTL_2 0x4608
861# define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0 966# define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0
862# define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0) 967# define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0)
863# define R300_PFS_CNTL_ALU_END_SHIFT 6 968# define R300_PFS_CNTL_ALU_END_SHIFT 6
864# define R300_PFS_CNTL_ALU_END_MASK (63 << 0) 969# define R300_PFS_CNTL_ALU_END_MASK (63 << 6)
865# define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12 970# define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12
866# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */ 971# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */
867# define R300_PFS_CNTL_TEX_END_SHIFT 18 972# define R300_PFS_CNTL_TEX_END_SHIFT 18
868# define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */ 973# define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */
869 974
870/* gap */ 975/* gap */
976
871/* Nodes are stored backwards. The last active node is always stored in 977/* Nodes are stored backwards. The last active node is always stored in
872// PFS_NODE_3. 978 * PFS_NODE_3.
873// Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The 979 * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
874// first node is stored in NODE_2, the second node is stored in NODE_3. 980 * first node is stored in NODE_2, the second node is stored in NODE_3.
875// 981 *
876// Offsets are relative to the master offset from PFS_CNTL_2. 982 * Offsets are relative to the master offset from PFS_CNTL_2.
877// LAST_NODE is set for the last node, and only for the last node. */ 983 */
878#define R300_PFS_NODE_0 0x4610 984#define R300_PFS_NODE_0 0x4610
879#define R300_PFS_NODE_1 0x4614 985#define R300_PFS_NODE_1 0x4614
880#define R300_PFS_NODE_2 0x4618 986#define R300_PFS_NODE_2 0x4618
@@ -887,91 +993,98 @@ I am fairly certain that they are correct unless stated otherwise in comments.
887# define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12) 993# define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12)
888# define R300_PFS_NODE_TEX_END_SHIFT 17 994# define R300_PFS_NODE_TEX_END_SHIFT 17
889# define R300_PFS_NODE_TEX_END_MASK (31 << 17) 995# define R300_PFS_NODE_TEX_END_MASK (31 << 17)
890/*# define R300_PFS_NODE_LAST_NODE (1 << 22) */
891# define R300_PFS_NODE_OUTPUT_COLOR (1 << 22) 996# define R300_PFS_NODE_OUTPUT_COLOR (1 << 22)
892# define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23) 997# define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23)
893 998
894/* TEX 999/* TEX
895// As far as I can tell, texture instructions cannot write into output 1000 * As far as I can tell, texture instructions cannot write into output
896// registers directly. A subsequent ALU instruction is always necessary, 1001 * registers directly. A subsequent ALU instruction is always necessary,
897// even if it's just MAD o0, r0, 1, 0 */ 1002 * even if it's just MAD o0, r0, 1, 0
1003 */
898#define R300_PFS_TEXI_0 0x4620 1004#define R300_PFS_TEXI_0 0x4620
899# define R300_FPITX_SRC_SHIFT 0 1005# define R300_FPITX_SRC_SHIFT 0
900# define R300_FPITX_SRC_MASK (31 << 0) 1006# define R300_FPITX_SRC_MASK (31 << 0)
901# define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */ 1007 /* GUESS */
902# define R300_FPITX_DST_SHIFT 6 1008# define R300_FPITX_SRC_CONST (1 << 5)
903# define R300_FPITX_DST_MASK (31 << 6) 1009# define R300_FPITX_DST_SHIFT 6
904# define R300_FPITX_IMAGE_SHIFT 11 1010# define R300_FPITX_DST_MASK (31 << 6)
905# define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */ 1011# define R300_FPITX_IMAGE_SHIFT 11
1012 /* GUESS based on layout and native limits */
1013# define R300_FPITX_IMAGE_MASK (15 << 11)
906/* Unsure if these are opcodes, or some kind of bitfield, but this is how 1014/* Unsure if these are opcodes, or some kind of bitfield, but this is how
907 * they were set when I checked 1015 * they were set when I checked
908 */ 1016 */
909# define R300_FPITX_OPCODE_SHIFT 15 1017# define R300_FPITX_OPCODE_SHIFT 15
910# define R300_FPITX_OP_TEX 1 1018# define R300_FPITX_OP_TEX 1
911# define R300_FPITX_OP_KIL 2 1019# define R300_FPITX_OP_KIL 2
912# define R300_FPITX_OP_TXP 3 1020# define R300_FPITX_OP_TXP 3
913# define R300_FPITX_OP_TXB 4 1021# define R300_FPITX_OP_TXB 4
1022# define R300_FPITX_OPCODE_MASK (7 << 15)
914 1023
915/* ALU 1024/* ALU
916// The ALU instructions register blocks are enumerated according to the order 1025 * The ALU instructions register blocks are enumerated according to the order
917// in which fglrx. I assume there is space for 64 instructions, since 1026 * in which fglrx. I assume there is space for 64 instructions, since
918// each block has space for a maximum of 64 DWORDs, and this matches reported 1027 * each block has space for a maximum of 64 DWORDs, and this matches reported
919// native limits. 1028 * native limits.
920// 1029 *
921// The basic functional block seems to be one MAD for each color and alpha, 1030 * The basic functional block seems to be one MAD for each color and alpha,
922// and an adder that adds all components after the MUL. 1031 * and an adder that adds all components after the MUL.
923// - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands 1032 * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
924// - DP4: Use OUTC_DP4, OUTA_DP4 1033 * - DP4: Use OUTC_DP4, OUTA_DP4
925// - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands 1034 * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
926// - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands 1035 * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
927// - CMP: If ARG2 < 0, return ARG1, else return ARG0 1036 * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1
928// - FLR: use FRC+MAD 1037 * - CMP: If ARG2 < 0, return ARG1, else return ARG0
929// - XPD: use MAD+MAD 1038 * - FLR: use FRC+MAD
930// - SGE, SLT: use MAD+CMP 1039 * - XPD: use MAD+MAD
931// - RSQ: use ABS modifier for argument 1040 * - SGE, SLT: use MAD+CMP
932// - Use OUTC_REPL_ALPHA to write results of an alpha-only operation (e.g. RCP) 1041 * - RSQ: use ABS modifier for argument
933// into color register 1042 * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation
934// - apparently, there's no quick DST operation 1043 * (e.g. RCP) into color register
935// - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2" 1044 * - apparently, there's no quick DST operation
936// - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0" 1045 * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
937// - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1" 1046 * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
938// 1047 * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
939// Operand selection 1048 *
940// First stage selects three sources from the available registers and 1049 * Operand selection
941// constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha). 1050 * First stage selects three sources from the available registers and
942// fglrx sorts the three source fields: Registers before constants, 1051 * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
943// lower indices before higher indices; I do not know whether this is necessary. 1052 * fglrx sorts the three source fields: Registers before constants,
944// fglrx fills unused sources with "read constant 0" 1053 * lower indices before higher indices; I do not know whether this is
945// According to specs, you cannot select more than two different constants. 1054 * necessary.
946// 1055 *
947// Second stage selects the operands from the sources. This is defined in 1056 * fglrx fills unused sources with "read constant 0"
948// INSTR0 (color) and INSTR2 (alpha). You can also select the special constants 1057 * According to specs, you cannot select more than two different constants.
949// zero and one. 1058 *
950// Swizzling and negation happens in this stage, as well. 1059 * Second stage selects the operands from the sources. This is defined in
951// 1060 * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
952// Important: Color and alpha seem to be mostly separate, i.e. their sources 1061 * zero and one.
953// selection appears to be fully independent (the register storage is probably 1062 * Swizzling and negation happens in this stage, as well.
954// physically split into a color and an alpha section). 1063 *
955// However (because of the apparent physical split), there is some interaction 1064 * Important: Color and alpha seem to be mostly separate, i.e. their sources
956// WRT swizzling. If, for example, you want to load an R component into an 1065 * selection appears to be fully independent (the register storage is probably
957// Alpha operand, this R component is taken from a *color* source, not from 1066 * physically split into a color and an alpha section).
958// an alpha source. The corresponding register doesn't even have to appear in 1067 * However (because of the apparent physical split), there is some interaction
959// the alpha sources list. (I hope this alll makes sense to you) 1068 * WRT swizzling. If, for example, you want to load an R component into an
960// 1069 * Alpha operand, this R component is taken from a *color* source, not from
961// Destination selection 1070 * an alpha source. The corresponding register doesn't even have to appear in
962// The destination register index is in FPI1 (color) and FPI3 (alpha) together 1071 * the alpha sources list. (I hope this all makes sense to you)
963// with enable bits. 1072 *
964// There are separate enable bits for writing into temporary registers 1073 * Destination selection
965// (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* /DSTA_OUTPUT). 1074 * The destination register index is in FPI1 (color) and FPI3 (alpha)
966// You can write to both at once, or not write at all (the same index 1075 * together with enable bits.
967// must be used for both). 1076 * There are separate enable bits for writing into temporary registers
968// 1077 * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_*
969// Note: There is a special form for LRP 1078 * /DSTA_OUTPUT). You can write to both at once, or not write at all (the
970// - Argument order is the same as in ARB_fragment_program. 1079 * same index must be used for both).
971// - Operation is MAD 1080 *
972// - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP 1081 * Note: There is a special form for LRP
973// - Set FPI0/FPI2_SPECIAL_LRP 1082 * - Argument order is the same as in ARB_fragment_program.
974// Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD */ 1083 * - Operation is MAD
1084 * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
1085 * - Set FPI0/FPI2_SPECIAL_LRP
1086 * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD
1087 */
975#define R300_PFS_INSTR1_0 0x46C0 1088#define R300_PFS_INSTR1_0 0x46C0
976# define R300_FPI1_SRC0C_SHIFT 0 1089# define R300_FPI1_SRC0C_SHIFT 0
977# define R300_FPI1_SRC0C_MASK (31 << 0) 1090# define R300_FPI1_SRC0C_MASK (31 << 0)
@@ -982,6 +1095,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
982# define R300_FPI1_SRC2C_SHIFT 12 1095# define R300_FPI1_SRC2C_SHIFT 12
983# define R300_FPI1_SRC2C_MASK (31 << 12) 1096# define R300_FPI1_SRC2C_MASK (31 << 12)
984# define R300_FPI1_SRC2C_CONST (1 << 17) 1097# define R300_FPI1_SRC2C_CONST (1 << 17)
1098# define R300_FPI1_SRC_MASK 0x0003ffff
985# define R300_FPI1_DSTC_SHIFT 18 1099# define R300_FPI1_DSTC_SHIFT 18
986# define R300_FPI1_DSTC_MASK (31 << 18) 1100# define R300_FPI1_DSTC_MASK (31 << 18)
987# define R300_FPI1_DSTC_REG_MASK_SHIFT 23 1101# define R300_FPI1_DSTC_REG_MASK_SHIFT 23
@@ -1003,6 +1117,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1003# define R300_FPI3_SRC2A_SHIFT 12 1117# define R300_FPI3_SRC2A_SHIFT 12
1004# define R300_FPI3_SRC2A_MASK (31 << 12) 1118# define R300_FPI3_SRC2A_MASK (31 << 12)
1005# define R300_FPI3_SRC2A_CONST (1 << 17) 1119# define R300_FPI3_SRC2A_CONST (1 << 17)
1120# define R300_FPI3_SRC_MASK 0x0003ffff
1006# define R300_FPI3_DSTA_SHIFT 18 1121# define R300_FPI3_DSTA_SHIFT 18
1007# define R300_FPI3_DSTA_MASK (31 << 18) 1122# define R300_FPI3_DSTA_MASK (31 << 18)
1008# define R300_FPI3_DSTA_REG (1 << 23) 1123# define R300_FPI3_DSTA_REG (1 << 23)
@@ -1028,7 +1143,8 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1028# define R300_FPI0_ARGC_SRC1C_LRP 15 1143# define R300_FPI0_ARGC_SRC1C_LRP 15
1029# define R300_FPI0_ARGC_ZERO 20 1144# define R300_FPI0_ARGC_ZERO 20
1030# define R300_FPI0_ARGC_ONE 21 1145# define R300_FPI0_ARGC_ONE 21
1031# define R300_FPI0_ARGC_HALF 22 /* GUESS */ 1146 /* GUESS */
1147# define R300_FPI0_ARGC_HALF 22
1032# define R300_FPI0_ARGC_SRC0C_YZX 23 1148# define R300_FPI0_ARGC_SRC0C_YZX 23
1033# define R300_FPI0_ARGC_SRC1C_YZX 24 1149# define R300_FPI0_ARGC_SRC1C_YZX 24
1034# define R300_FPI0_ARGC_SRC2C_YZX 25 1150# define R300_FPI0_ARGC_SRC2C_YZX 25
@@ -1057,6 +1173,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1057# define R300_FPI0_OUTC_DP4 (2 << 23) 1173# define R300_FPI0_OUTC_DP4 (2 << 23)
1058# define R300_FPI0_OUTC_MIN (4 << 23) 1174# define R300_FPI0_OUTC_MIN (4 << 23)
1059# define R300_FPI0_OUTC_MAX (5 << 23) 1175# define R300_FPI0_OUTC_MAX (5 << 23)
1176# define R300_FPI0_OUTC_CMPH (7 << 23)
1060# define R300_FPI0_OUTC_CMP (8 << 23) 1177# define R300_FPI0_OUTC_CMP (8 << 23)
1061# define R300_FPI0_OUTC_FRC (9 << 23) 1178# define R300_FPI0_OUTC_FRC (9 << 23)
1062# define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) 1179# define R300_FPI0_OUTC_REPL_ALPHA (10 << 23)
@@ -1079,20 +1196,23 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1079# define R300_FPI2_ARGA_SRC1A_LRP 15 1196# define R300_FPI2_ARGA_SRC1A_LRP 15
1080# define R300_FPI2_ARGA_ZERO 16 1197# define R300_FPI2_ARGA_ZERO 16
1081# define R300_FPI2_ARGA_ONE 17 1198# define R300_FPI2_ARGA_ONE 17
1082# define R300_FPI2_ARGA_HALF 18 /* GUESS */ 1199 /* GUESS */
1083 1200# define R300_FPI2_ARGA_HALF 18
1084# define R300_FPI2_ARG0A_SHIFT 0 1201# define R300_FPI2_ARG0A_SHIFT 0
1085# define R300_FPI2_ARG0A_MASK (31 << 0) 1202# define R300_FPI2_ARG0A_MASK (31 << 0)
1086# define R300_FPI2_ARG0A_NEG (1 << 5) 1203# define R300_FPI2_ARG0A_NEG (1 << 5)
1087# define R300_FPI2_ARG0A_ABS (1 << 6) /* GUESS */ 1204 /* GUESS */
1205# define R300_FPI2_ARG0A_ABS (1 << 6)
1088# define R300_FPI2_ARG1A_SHIFT 7 1206# define R300_FPI2_ARG1A_SHIFT 7
1089# define R300_FPI2_ARG1A_MASK (31 << 7) 1207# define R300_FPI2_ARG1A_MASK (31 << 7)
1090# define R300_FPI2_ARG1A_NEG (1 << 12) 1208# define R300_FPI2_ARG1A_NEG (1 << 12)
1091# define R300_FPI2_ARG1A_ABS (1 << 13) /* GUESS */ 1209 /* GUESS */
1210# define R300_FPI2_ARG1A_ABS (1 << 13)
1092# define R300_FPI2_ARG2A_SHIFT 14 1211# define R300_FPI2_ARG2A_SHIFT 14
1093# define R300_FPI2_ARG2A_MASK (31 << 14) 1212# define R300_FPI2_ARG2A_MASK (31 << 14)
1094# define R300_FPI2_ARG2A_NEG (1 << 19) 1213# define R300_FPI2_ARG2A_NEG (1 << 19)
1095# define R300_FPI2_ARG2A_ABS (1 << 20) /* GUESS */ 1214 /* GUESS */
1215# define R300_FPI2_ARG2A_ABS (1 << 20)
1096# define R300_FPI2_SPECIAL_LRP (1 << 21) 1216# define R300_FPI2_SPECIAL_LRP (1 << 21)
1097# define R300_FPI2_OUTA_MAD (0 << 23) 1217# define R300_FPI2_OUTA_MAD (0 << 23)
1098# define R300_FPI2_OUTA_DP4 (1 << 23) 1218# define R300_FPI2_OUTA_DP4 (1 << 23)
@@ -1106,9 +1226,19 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1106# define R300_FPI2_OUTA_RSQ (11 << 23) 1226# define R300_FPI2_OUTA_RSQ (11 << 23)
1107# define R300_FPI2_OUTA_SAT (1 << 30) 1227# define R300_FPI2_OUTA_SAT (1 << 30)
1108# define R300_FPI2_UNKNOWN_31 (1 << 31) 1228# define R300_FPI2_UNKNOWN_31 (1 << 31)
1109/* END */ 1229/* END: Fragment program instruction set */
1230
1231/* Fog state and color */
1232#define R300_RE_FOG_STATE 0x4BC0
1233# define R300_FOG_ENABLE (1 << 0)
1234# define R300_FOG_MODE_LINEAR (0 << 1)
1235# define R300_FOG_MODE_EXP (1 << 1)
1236# define R300_FOG_MODE_EXP2 (2 << 1)
1237# define R300_FOG_MODE_MASK (3 << 1)
1238#define R300_FOG_COLOR_R 0x4BC8
1239#define R300_FOG_COLOR_G 0x4BCC
1240#define R300_FOG_COLOR_B 0x4BD0
1110 1241
1111/* gap */
1112#define R300_PP_ALPHA_TEST 0x4BD4 1242#define R300_PP_ALPHA_TEST 0x4BD4
1113# define R300_REF_ALPHA_MASK 0x000000ff 1243# define R300_REF_ALPHA_MASK 0x000000ff
1114# define R300_ALPHA_TEST_FAIL (0 << 8) 1244# define R300_ALPHA_TEST_FAIL (0 << 8)
@@ -1123,6 +1253,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1123# define R300_ALPHA_TEST_ENABLE (1 << 11) 1253# define R300_ALPHA_TEST_ENABLE (1 << 11)
1124 1254
1125/* gap */ 1255/* gap */
1256
1126/* Fragment program parameters in 7.16 floating point */ 1257/* Fragment program parameters in 7.16 floating point */
1127#define R300_PFS_PARAM_0_X 0x4C00 1258#define R300_PFS_PARAM_0_X 0x4C00
1128#define R300_PFS_PARAM_0_Y 0x4C04 1259#define R300_PFS_PARAM_0_Y 0x4C04
@@ -1135,45 +1266,48 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1135#define R300_PFS_PARAM_31_W 0x4DFC 1266#define R300_PFS_PARAM_31_W 0x4DFC
1136 1267
1137/* Notes: 1268/* Notes:
1138// - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in the application 1269 * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in
1139// - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND are set to the same 1270 * the application
1140// function (both registers are always set up completely in any case) 1271 * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND
1141// - Most blend flags are simply copied from R200 and not tested yet */ 1272 * are set to the same
1273 * function (both registers are always set up completely in any case)
1274 * - Most blend flags are simply copied from R200 and not tested yet
1275 */
1142#define R300_RB3D_CBLEND 0x4E04 1276#define R300_RB3D_CBLEND 0x4E04
1143#define R300_RB3D_ABLEND 0x4E08 1277#define R300_RB3D_ABLEND 0x4E08
1144 /* the following only appear in CBLEND */ 1278/* the following only appear in CBLEND */
1145# define R300_BLEND_ENABLE (1 << 0) 1279# define R300_BLEND_ENABLE (1 << 0)
1146# define R300_BLEND_UNKNOWN (3 << 1) 1280# define R300_BLEND_UNKNOWN (3 << 1)
1147# define R300_BLEND_NO_SEPARATE (1 << 3) 1281# define R300_BLEND_NO_SEPARATE (1 << 3)
1148 /* the following are shared between CBLEND and ABLEND */ 1282/* the following are shared between CBLEND and ABLEND */
1149# define R300_FCN_MASK (3 << 12) 1283# define R300_FCN_MASK (3 << 12)
1150# define R300_COMB_FCN_ADD_CLAMP (0 << 12) 1284# define R300_COMB_FCN_ADD_CLAMP (0 << 12)
1151# define R300_COMB_FCN_ADD_NOCLAMP (1 << 12) 1285# define R300_COMB_FCN_ADD_NOCLAMP (1 << 12)
1152# define R300_COMB_FCN_SUB_CLAMP (2 << 12) 1286# define R300_COMB_FCN_SUB_CLAMP (2 << 12)
1153# define R300_COMB_FCN_SUB_NOCLAMP (3 << 12) 1287# define R300_COMB_FCN_SUB_NOCLAMP (3 << 12)
1154# define R300_SRC_BLEND_GL_ZERO (32 << 16) 1288# define R300_COMB_FCN_MIN (4 << 12)
1155# define R300_SRC_BLEND_GL_ONE (33 << 16) 1289# define R300_COMB_FCN_MAX (5 << 12)
1156# define R300_SRC_BLEND_GL_SRC_COLOR (34 << 16) 1290# define R300_COMB_FCN_RSUB_CLAMP (6 << 12)
1157# define R300_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) 1291# define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12)
1158# define R300_SRC_BLEND_GL_DST_COLOR (36 << 16) 1292# define R300_BLEND_GL_ZERO (32)
1159# define R300_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) 1293# define R300_BLEND_GL_ONE (33)
1160# define R300_SRC_BLEND_GL_SRC_ALPHA (38 << 16) 1294# define R300_BLEND_GL_SRC_COLOR (34)
1161# define R300_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) 1295# define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35)
1162# define R300_SRC_BLEND_GL_DST_ALPHA (40 << 16) 1296# define R300_BLEND_GL_DST_COLOR (36)
1163# define R300_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) 1297# define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37)
1164# define R300_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) 1298# define R300_BLEND_GL_SRC_ALPHA (38)
1165# define R300_SRC_BLEND_MASK (63 << 16) 1299# define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39)
1166# define R300_DST_BLEND_GL_ZERO (32 << 24) 1300# define R300_BLEND_GL_DST_ALPHA (40)
1167# define R300_DST_BLEND_GL_ONE (33 << 24) 1301# define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41)
1168# define R300_DST_BLEND_GL_SRC_COLOR (34 << 24) 1302# define R300_BLEND_GL_SRC_ALPHA_SATURATE (42)
1169# define R300_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) 1303# define R300_BLEND_GL_CONST_COLOR (43)
1170# define R300_DST_BLEND_GL_DST_COLOR (36 << 24) 1304# define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44)
1171# define R300_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) 1305# define R300_BLEND_GL_CONST_ALPHA (45)
1172# define R300_DST_BLEND_GL_SRC_ALPHA (38 << 24) 1306# define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46)
1173# define R300_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) 1307# define R300_BLEND_MASK (63)
1174# define R300_DST_BLEND_GL_DST_ALPHA (40 << 24) 1308# define R300_SRC_BLEND_SHIFT (16)
1175# define R300_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) 1309# define R300_DST_BLEND_SHIFT (24)
1176# define R300_DST_BLEND_MASK (63 << 24) 1310#define R300_RB3D_BLEND_COLOR 0x4E10
1177#define R300_RB3D_COLORMASK 0x4E0C 1311#define R300_RB3D_COLORMASK 0x4E0C
1178# define R300_COLORMASK0_B (1<<0) 1312# define R300_COLORMASK0_B (1<<0)
1179# define R300_COLORMASK0_G (1<<1) 1313# define R300_COLORMASK0_G (1<<1)
@@ -1181,41 +1315,49 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1181# define R300_COLORMASK0_A (1<<3) 1315# define R300_COLORMASK0_A (1<<3)
1182 1316
1183/* gap */ 1317/* gap */
1318
1184#define R300_RB3D_COLOROFFSET0 0x4E28 1319#define R300_RB3D_COLOROFFSET0 0x4E28
1185# define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */ 1320# define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */
1186#define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */ 1321#define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */
1187#define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */ 1322#define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */
1188#define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */ 1323#define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */
1324
1189/* gap */ 1325/* gap */
1326
1190/* Bit 16: Larger tiles 1327/* Bit 16: Larger tiles
1191// Bit 17: 4x2 tiles 1328 * Bit 17: 4x2 tiles
1192// Bit 18: Extremely weird tile like, but some pixels duplicated? */ 1329 * Bit 18: Extremely weird tile like, but some pixels duplicated?
1330 */
1193#define R300_RB3D_COLORPITCH0 0x4E38 1331#define R300_RB3D_COLORPITCH0 0x4E38
1194# define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */ 1332# define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */
1195# define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */ 1333# define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */
1196# define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */ 1334# define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */
1197# define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 1335# define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
1198# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 1336# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
1199# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 1337# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
1200# define R300_COLOR_FORMAT_RGB565 (2 << 22) 1338# define R300_COLOR_FORMAT_RGB565 (2 << 22)
1201# define R300_COLOR_FORMAT_ARGB8888 (3 << 22) 1339# define R300_COLOR_FORMAT_ARGB8888 (3 << 22)
1202#define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */ 1340#define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */
1203#define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ 1341#define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */
1204#define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ 1342#define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */
1205 1343
1206/* gap */ 1344/* gap */
1345
1207/* Guess by Vladimir. 1346/* Guess by Vladimir.
1208// Set to 0A before 3D operations, set to 02 afterwards. */ 1347 * Set to 0A before 3D operations, set to 02 afterwards.
1348 */
1209#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C 1349#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C
1210# define R300_RB3D_DSTCACHE_02 0x00000002 1350# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002
1211# define R300_RB3D_DSTCACHE_0A 0x0000000A 1351# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A
1212 1352
1213/* gap */ 1353/* gap */
1214/* There seems to be no "write only" setting, so use Z-test = ALWAYS for this. */ 1354/* There seems to be no "write only" setting, so use Z-test = ALWAYS
1215/* Bit (1<<8) is the "test" bit. so plain write is 6 - vd */ 1355 * for this.
1356 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
1357 */
1216#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 1358#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00
1217# define R300_RB3D_Z_DISABLED_1 0x00000010 /* GUESS */ 1359# define R300_RB3D_Z_DISABLED_1 0x00000010
1218# define R300_RB3D_Z_DISABLED_2 0x00000014 /* GUESS */ 1360# define R300_RB3D_Z_DISABLED_2 0x00000014
1219# define R300_RB3D_Z_TEST 0x00000012 1361# define R300_RB3D_Z_TEST 0x00000012
1220# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 1362# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
1221# define R300_RB3D_Z_WRITE_ONLY 0x00000006 1363# define R300_RB3D_Z_WRITE_ONLY 0x00000006
@@ -1226,7 +1368,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1226# define R300_RB3D_STENCIL_ENABLE 0x00000001 1368# define R300_RB3D_STENCIL_ENABLE 0x00000001
1227 1369
1228#define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04 1370#define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
1229 /* functions */ 1371 /* functions */
1230# define R300_ZS_NEVER 0 1372# define R300_ZS_NEVER 0
1231# define R300_ZS_LESS 1 1373# define R300_ZS_LESS 1
1232# define R300_ZS_LEQUAL 2 1374# define R300_ZS_LEQUAL 2
@@ -1236,7 +1378,7 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1236# define R300_ZS_NOTEQUAL 6 1378# define R300_ZS_NOTEQUAL 6
1237# define R300_ZS_ALWAYS 7 1379# define R300_ZS_ALWAYS 7
1238# define R300_ZS_MASK 7 1380# define R300_ZS_MASK 7
1239 /* operations */ 1381 /* operations */
1240# define R300_ZS_KEEP 0 1382# define R300_ZS_KEEP 0
1241# define R300_ZS_ZERO 1 1383# define R300_ZS_ZERO 1
1242# define R300_ZS_REPLACE 2 1384# define R300_ZS_REPLACE 2
@@ -1245,9 +1387,8 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1245# define R300_ZS_INVERT 5 1387# define R300_ZS_INVERT 5
1246# define R300_ZS_INCR_WRAP 6 1388# define R300_ZS_INCR_WRAP 6
1247# define R300_ZS_DECR_WRAP 7 1389# define R300_ZS_DECR_WRAP 7
1248 1390 /* front and back refer to operations done for front
1249 /* front and back refer to operations done for front 1391 and back faces, i.e. separate stencil function support */
1250 and back faces, i.e. separate stencil function support */
1251# define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0 1392# define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0
1252# define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3 1393# define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3
1253# define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6 1394# define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6
@@ -1269,45 +1410,64 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1269#define R300_RB3D_ZSTENCIL_FORMAT 0x4F10 1410#define R300_RB3D_ZSTENCIL_FORMAT 0x4F10
1270# define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1411# define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
1271# define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1412# define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
1413 /* 16 bit format or some aditional bit ? */
1414# define R300_DEPTH_FORMAT_UNK32 (32 << 0)
1415
1416#define R300_RB3D_EARLY_Z 0x4F14
1417# define R300_EARLY_Z_DISABLE (0 << 0)
1418# define R300_EARLY_Z_ENABLE (1 << 0)
1419
1420/* gap */
1421
1422#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */
1423# define R300_RB3D_ZCACHE_UNKNOWN_01 0x1
1424# define R300_RB3D_ZCACHE_UNKNOWN_03 0x3
1272 1425
1273/* gap */ 1426/* gap */
1427
1274#define R300_RB3D_DEPTHOFFSET 0x4F20 1428#define R300_RB3D_DEPTHOFFSET 0x4F20
1275#define R300_RB3D_DEPTHPITCH 0x4F24 1429#define R300_RB3D_DEPTHPITCH 0x4F24
1276# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ 1430# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */
1277# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ 1431# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */
1278# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ 1432# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */
1279# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 1433# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
1280# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 1434# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
1281# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 1435# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
1282 1436
1283/* BEGIN: Vertex program instruction set 1437/* BEGIN: Vertex program instruction set */
1284// Every instruction is four dwords long: 1438
1285// DWORD 0: output and opcode 1439/* Every instruction is four dwords long:
1286// DWORD 1: first argument 1440 * DWORD 0: output and opcode
1287// DWORD 2: second argument 1441 * DWORD 1: first argument
1288// DWORD 3: third argument 1442 * DWORD 2: second argument
1289// 1443 * DWORD 3: third argument
1290// Notes: 1444 *
1291// - ABS r, a is implemented as MAX r, a, -a 1445 * Notes:
1292// - MOV is implemented as ADD to zero 1446 * - ABS r, a is implemented as MAX r, a, -a
1293// - XPD is implemented as MUL + MAD 1447 * - MOV is implemented as ADD to zero
1294// - FLR is implemented as FRC + ADD 1448 * - XPD is implemented as MUL + MAD
1295// - apparently, fglrx tries to schedule instructions so that there is at least 1449 * - FLR is implemented as FRC + ADD
1296// one instruction between the write to a temporary and the first read 1450 * - apparently, fglrx tries to schedule instructions so that there is at
1297// from said temporary; however, violations of this scheduling are allowed 1451 * least one instruction between the write to a temporary and the first
1298// - register indices seem to be unrelated with OpenGL aliasing to conventional state 1452 * read from said temporary; however, violations of this scheduling are
1299// - only one attribute and one parameter can be loaded at a time; however, the 1453 * allowed
1300// same attribute/parameter can be used for more than one argument 1454 * - register indices seem to be unrelated with OpenGL aliasing to
1301// - the second software argument for POW is the third hardware argument (no idea why) 1455 * conventional state
1302// - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2 1456 * - only one attribute and one parameter can be loaded at a time; however,
1303// 1457 * the same attribute/parameter can be used for more than one argument
1304// There is some magic surrounding LIT: 1458 * - the second software argument for POW is the third hardware argument
1305// The single argument is replicated across all three inputs, but swizzled: 1459 * (no idea why)
1306// First argument: xyzy 1460 * - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2
1307// Second argument: xyzx 1461 *
1308// Third argument: xyzw 1462 * There is some magic surrounding LIT:
1309// Whenever the result is used later in the fragment program, fglrx forces x and w 1463 * The single argument is replicated across all three inputs, but swizzled:
1310// to be 1.0 in the input selection; I don't know whether this is strictly necessary */ 1464 * First argument: xyzy
1465 * Second argument: xyzx
1466 * Third argument: xyzw
1467 * Whenever the result is used later in the fragment program, fglrx forces
1468 * x and w to be 1.0 in the input selection; I don't know whether this is
1469 * strictly necessary
1470 */
1311#define R300_VPI_OUT_OP_DOT (1 << 0) 1471#define R300_VPI_OUT_OP_DOT (1 << 0)
1312#define R300_VPI_OUT_OP_MUL (2 << 0) 1472#define R300_VPI_OUT_OP_MUL (2 << 0)
1313#define R300_VPI_OUT_OP_ADD (3 << 0) 1473#define R300_VPI_OUT_OP_ADD (3 << 0)
@@ -1318,26 +1478,33 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1318#define R300_VPI_OUT_OP_MIN (8 << 0) 1478#define R300_VPI_OUT_OP_MIN (8 << 0)
1319#define R300_VPI_OUT_OP_SGE (9 << 0) 1479#define R300_VPI_OUT_OP_SGE (9 << 0)
1320#define R300_VPI_OUT_OP_SLT (10 << 0) 1480#define R300_VPI_OUT_OP_SLT (10 << 0)
1321#define R300_VPI_OUT_OP_UNK12 (12 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */ 1481 /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */
1482#define R300_VPI_OUT_OP_UNK12 (12 << 0)
1483#define R300_VPI_OUT_OP_ARL (13 << 0)
1322#define R300_VPI_OUT_OP_EXP (65 << 0) 1484#define R300_VPI_OUT_OP_EXP (65 << 0)
1323#define R300_VPI_OUT_OP_LOG (66 << 0) 1485#define R300_VPI_OUT_OP_LOG (66 << 0)
1324#define R300_VPI_OUT_OP_UNK67 (67 << 0) /* Used in fog computations, scalar(scalar) */ 1486 /* Used in fog computations, scalar(scalar) */
1487#define R300_VPI_OUT_OP_UNK67 (67 << 0)
1325#define R300_VPI_OUT_OP_LIT (68 << 0) 1488#define R300_VPI_OUT_OP_LIT (68 << 0)
1326#define R300_VPI_OUT_OP_POW (69 << 0) 1489#define R300_VPI_OUT_OP_POW (69 << 0)
1327#define R300_VPI_OUT_OP_RCP (70 << 0) 1490#define R300_VPI_OUT_OP_RCP (70 << 0)
1328#define R300_VPI_OUT_OP_RSQ (72 << 0) 1491#define R300_VPI_OUT_OP_RSQ (72 << 0)
1329#define R300_VPI_OUT_OP_UNK73 (73 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */ 1492 /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */
1493#define R300_VPI_OUT_OP_UNK73 (73 << 0)
1330#define R300_VPI_OUT_OP_EX2 (75 << 0) 1494#define R300_VPI_OUT_OP_EX2 (75 << 0)
1331#define R300_VPI_OUT_OP_LG2 (76 << 0) 1495#define R300_VPI_OUT_OP_LG2 (76 << 0)
1332#define R300_VPI_OUT_OP_MAD_2 (128 << 0) 1496#define R300_VPI_OUT_OP_MAD_2 (128 << 0)
1333#define R300_VPI_OUT_OP_UNK129 (129 << 0) /* all temps, vector(scalar, vector, vector) */ 1497 /* all temps, vector(scalar, vector, vector) */
1498#define R300_VPI_OUT_OP_UNK129 (129 << 0)
1334 1499
1335#define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8) 1500#define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8)
1501#define R300_VPI_OUT_REG_CLASS_ADDR (1 << 8)
1336#define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8) 1502#define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8)
1337#define R300_VPI_OUT_REG_CLASS_MASK (31 << 8) 1503#define R300_VPI_OUT_REG_CLASS_MASK (31 << 8)
1338 1504
1339#define R300_VPI_OUT_REG_INDEX_SHIFT 13 1505#define R300_VPI_OUT_REG_INDEX_SHIFT 13
1340#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) /* GUESS based on fglrx native limits */ 1506 /* GUESS based on fglrx native limits */
1507#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13)
1341 1508
1342#define R300_VPI_OUT_WRITE_X (1 << 20) 1509#define R300_VPI_OUT_WRITE_X (1 << 20)
1343#define R300_VPI_OUT_WRITE_Y (1 << 21) 1510#define R300_VPI_OUT_WRITE_Y (1 << 21)
@@ -1348,14 +1515,16 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1348#define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0) 1515#define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0)
1349#define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0) 1516#define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0)
1350#define R300_VPI_IN_REG_CLASS_NONE (9 << 0) 1517#define R300_VPI_IN_REG_CLASS_NONE (9 << 0)
1351#define R300_VPI_IN_REG_CLASS_MASK (31 << 0) /* GUESS */ 1518#define R300_VPI_IN_REG_CLASS_MASK (31 << 0)
1352 1519
1353#define R300_VPI_IN_REG_INDEX_SHIFT 5 1520#define R300_VPI_IN_REG_INDEX_SHIFT 5
1354#define R300_VPI_IN_REG_INDEX_MASK (255 << 5) /* GUESS based on fglrx native limits */ 1521 /* GUESS based on fglrx native limits */
1522#define R300_VPI_IN_REG_INDEX_MASK (255 << 5)
1355 1523
1356/* The R300 can select components from the input register arbitrarily. 1524/* The R300 can select components from the input register arbitrarily.
1357// Use the following constants, shifted by the component shift you 1525 * Use the following constants, shifted by the component shift you
1358// want to select */ 1526 * want to select
1527 */
1359#define R300_VPI_IN_SELECT_X 0 1528#define R300_VPI_IN_SELECT_X 0
1360#define R300_VPI_IN_SELECT_Y 1 1529#define R300_VPI_IN_SELECT_Y 1
1361#define R300_VPI_IN_SELECT_Z 2 1530#define R300_VPI_IN_SELECT_Z 2
@@ -1373,11 +1542,11 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1373#define R300_VPI_IN_NEG_Y (1 << 26) 1542#define R300_VPI_IN_NEG_Y (1 << 26)
1374#define R300_VPI_IN_NEG_Z (1 << 27) 1543#define R300_VPI_IN_NEG_Z (1 << 27)
1375#define R300_VPI_IN_NEG_W (1 << 28) 1544#define R300_VPI_IN_NEG_W (1 << 28)
1376/* END */ 1545/* END: Vertex program instruction set */
1377 1546
1378//BEGIN: Packet 3 commands 1547/* BEGIN: Packet 3 commands */
1379 1548
1380// A primitive emission dword. 1549/* A primitive emission dword. */
1381#define R300_PRIM_TYPE_NONE (0 << 0) 1550#define R300_PRIM_TYPE_NONE (0 << 0)
1382#define R300_PRIM_TYPE_POINT (1 << 0) 1551#define R300_PRIM_TYPE_POINT (1 << 0)
1383#define R300_PRIM_TYPE_LINE (2 << 0) 1552#define R300_PRIM_TYPE_LINE (2 << 0)
@@ -1389,7 +1558,8 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1389#define R300_PRIM_TYPE_RECT_LIST (8 << 0) 1558#define R300_PRIM_TYPE_RECT_LIST (8 << 0)
1390#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1559#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1391#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1560#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1392#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) // GUESS (based on r200) 1561 /* GUESS (based on r200) */
1562#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0)
1393#define R300_PRIM_TYPE_LINE_LOOP (12 << 0) 1563#define R300_PRIM_TYPE_LINE_LOOP (12 << 0)
1394#define R300_PRIM_TYPE_QUADS (13 << 0) 1564#define R300_PRIM_TYPE_QUADS (13 << 0)
1395#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) 1565#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0)
@@ -1399,37 +1569,58 @@ I am fairly certain that they are correct unless stated otherwise in comments.
1399#define R300_PRIM_WALK_LIST (2 << 4) 1569#define R300_PRIM_WALK_LIST (2 << 4)
1400#define R300_PRIM_WALK_RING (3 << 4) 1570#define R300_PRIM_WALK_RING (3 << 4)
1401#define R300_PRIM_WALK_MASK (3 << 4) 1571#define R300_PRIM_WALK_MASK (3 << 4)
1402#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) // GUESS (based on r200) 1572 /* GUESS (based on r200) */
1403#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) // GUESS 1573#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6)
1574#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6)
1404#define R300_PRIM_NUM_VERTICES_SHIFT 16 1575#define R300_PRIM_NUM_VERTICES_SHIFT 16
1576#define R300_PRIM_NUM_VERTICES_MASK 0xffff
1405 1577
1406// Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. 1578/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
1407// Two parameter dwords: 1579 * Two parameter dwords:
1408// 0. The first parameter appears to be always 0 1580 * 0. The first parameter appears to be always 0
1409// 1. The second parameter is a standard primitive emission dword. 1581 * 1. The second parameter is a standard primitive emission dword.
1582 */
1410#define R300_PACKET3_3D_DRAW_VBUF 0x00002800 1583#define R300_PACKET3_3D_DRAW_VBUF 0x00002800
1411 1584
1412// Specify the full set of vertex arrays as (address, stride). 1585/* Specify the full set of vertex arrays as (address, stride).
1413// The first parameter is the number of vertex arrays specified. 1586 * The first parameter is the number of vertex arrays specified.
1414// The rest of the command is a variable length list of blocks, where 1587 * The rest of the command is a variable length list of blocks, where
1415// each block is three dwords long and specifies two arrays. 1588 * each block is three dwords long and specifies two arrays.
1416// The first dword of a block is split into two words, the lower significant 1589 * The first dword of a block is split into two words, the lower significant
1417// word refers to the first array, the more significant word to the second 1590 * word refers to the first array, the more significant word to the second
1418// array in the block. 1591 * array in the block.
1419// The low byte of each word contains the size of an array entry in dwords, 1592 * The low byte of each word contains the size of an array entry in dwords,
1420// the high byte contains the stride of the array. 1593 * the high byte contains the stride of the array.
1421// The second dword of a block contains the pointer to the first array, 1594 * The second dword of a block contains the pointer to the first array,
1422// the third dword of a block contains the pointer to the second array. 1595 * the third dword of a block contains the pointer to the second array.
1423// Note that if the total number of arrays is odd, the third dword of 1596 * Note that if the total number of arrays is odd, the third dword of
1424// the last block is omitted. 1597 * the last block is omitted.
1598 */
1425#define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00 1599#define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00
1426 1600
1427#define R300_PACKET3_INDX_BUFFER 0x00003300 1601#define R300_PACKET3_INDX_BUFFER 0x00003300
1428# define R300_EB_UNK1_SHIFT 24 1602# define R300_EB_UNK1_SHIFT 24
1429# define R300_EB_UNK1 (0x80<<24) 1603# define R300_EB_UNK1 (0x80<<24)
1430# define R300_EB_UNK2 0x0810 1604# define R300_EB_UNK2 0x0810
1605#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400
1431#define R300_PACKET3_3D_DRAW_INDX_2 0x00003600 1606#define R300_PACKET3_3D_DRAW_INDX_2 0x00003600
1432 1607
1433//END 1608/* END: Packet 3 commands */
1609
1610
1611/* Color formats for 2d packets
1612 */
1613#define R300_CP_COLOR_FORMAT_CI8 2
1614#define R300_CP_COLOR_FORMAT_ARGB1555 3
1615#define R300_CP_COLOR_FORMAT_RGB565 4
1616#define R300_CP_COLOR_FORMAT_ARGB8888 6
1617#define R300_CP_COLOR_FORMAT_RGB332 7
1618#define R300_CP_COLOR_FORMAT_RGB8 9
1619#define R300_CP_COLOR_FORMAT_ARGB4444 15
1620
1621/*
1622 * CP type-3 packets
1623 */
1624#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00
1434 1625
1435#endif /* _R300_REG_H */ 1626#endif /* _R300_REG_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-18 13:10:56 -0500