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-rw-r--r--arch/mips/au1000/pb1200/Makefile2
-rw-r--r--arch/mips/au1000/pb1200/board_setup.c139
-rw-r--r--arch/mips/au1000/pb1200/init.c18
-rw-r--r--arch/mips/au1000/pb1200/irqmap.c66
-rw-r--r--include/asm-mips/mach-db1x00/db1200.h73
-rw-r--r--include/asm-mips/mach-pb1x00/pb1200.h93
6 files changed, 186 insertions, 205 deletions
diff --git a/arch/mips/au1000/pb1200/Makefile b/arch/mips/au1000/pb1200/Makefile
index 4fe02ea65a60..d678adf7ce85 100644
--- a/arch/mips/au1000/pb1200/Makefile
+++ b/arch/mips/au1000/pb1200/Makefile
@@ -1,5 +1,5 @@
1# 1#
2# Makefile for the Alchemy Semiconductor PB1200 board. 2# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards.
3# 3#
4 4
5lib-y := init.o board_setup.o irqmap.o 5lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c
index 4493a792cc4c..6cb2115059ad 100644
--- a/arch/mips/au1000/pb1200/board_setup.c
+++ b/arch/mips/au1000/pb1200/board_setup.c
@@ -27,16 +27,8 @@
27#include <linux/init.h> 27#include <linux/init.h>
28#include <linux/sched.h> 28#include <linux/sched.h>
29 29
30#include <au1000.h>
31#include <prom.h> 30#include <prom.h>
32 31#include <au1xxx.h>
33#ifdef CONFIG_MIPS_PB1200
34#include <asm/mach-pb1x00/pb1200.h>
35#endif
36
37#ifdef CONFIG_MIPS_DB1200
38#include <asm/mach-db1x00/db1200.h>
39#endif
40 32
41extern void _board_init_irq(void); 33extern void _board_init_irq(void);
42extern void (*board_init_irq)(void); 34extern void (*board_init_irq)(void);
@@ -53,56 +45,57 @@ void __init board_setup(void)
53 45
54#if 0 46#if 0
55 { 47 {
56 u32 pin_func; 48 u32 pin_func;
57 49
58 /* Enable PSC1 SYNC for AC97. Normaly done in audio driver, 50 /*
59 * but it is board specific code, so put it here. 51 * Enable PSC1 SYNC for AC97. Normaly done in audio driver,
60 */ 52 * but it is board specific code, so put it here.
61 pin_func = au_readl(SYS_PINFUNC); 53 */
62 au_sync(); 54 pin_func = au_readl(SYS_PINFUNC);
63 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1; 55 au_sync();
64 au_writel(pin_func, SYS_PINFUNC); 56 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
65 57 au_writel(pin_func, SYS_PINFUNC);
66 au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */ 58
67 au_sync(); 59 au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
60 au_sync();
68 } 61 }
69#endif 62#endif
70 63
71#if defined(CONFIG_I2C_AU1550) 64#if defined(CONFIG_I2C_AU1550)
72 { 65 {
73 u32 freq0, clksrc; 66 u32 freq0, clksrc;
74 u32 pin_func; 67 u32 pin_func;
75 68
76 /* Select SMBUS in CPLD */ 69 /* Select SMBus in CPLD */
77 bcsr->resets &= ~(BCSR_RESETS_PCS0MUX); 70 bcsr->resets &= ~BCSR_RESETS_PCS0MUX;
78 71
79 pin_func = au_readl(SYS_PINFUNC); 72 pin_func = au_readl(SYS_PINFUNC);
80 au_sync(); 73 au_sync();
81 pin_func &= ~(3<<17 | 1<<4); 74 pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
82 /* Set GPIOs correctly */ 75 /* Set GPIOs correctly */
83 pin_func |= 2<<17; 76 pin_func |= 2 << 17;
84 au_writel(pin_func, SYS_PINFUNC); 77 au_writel(pin_func, SYS_PINFUNC);
85 au_sync(); 78 au_sync();
86 79
87 /* The i2c driver depends on 50Mhz clock */ 80 /* The I2C driver depends on 50 MHz clock */
88 freq0 = au_readl(SYS_FREQCTRL0); 81 freq0 = au_readl(SYS_FREQCTRL0);
89 au_sync(); 82 au_sync();
90 freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1); 83 freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
91 freq0 |= (3<<SYS_FC_FRDIV1_BIT); 84 freq0 |= 3 << SYS_FC_FRDIV1_BIT;
92 /* 396Mhz / (3+1)*2 == 49.5Mhz */ 85 /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */
93 au_writel(freq0, SYS_FREQCTRL0); 86 au_writel(freq0, SYS_FREQCTRL0);
94 au_sync(); 87 au_sync();
95 freq0 |= SYS_FC_FE1; 88 freq0 |= SYS_FC_FE1;
96 au_writel(freq0, SYS_FREQCTRL0); 89 au_writel(freq0, SYS_FREQCTRL0);
97 au_sync(); 90 au_sync();
98 91
99 clksrc = au_readl(SYS_CLKSRC); 92 clksrc = au_readl(SYS_CLKSRC);
100 au_sync(); 93 au_sync();
101 clksrc &= ~0x01f00000; 94 clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK);
102 /* bit 22 is EXTCLK0 for PSC0 */ 95 /* Bit 22 is EXTCLK0 for PSC0 */
103 clksrc |= (0x3 << 22); 96 clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT;
104 au_writel(clksrc, SYS_CLKSRC); 97 au_writel(clksrc, SYS_CLKSRC);
105 au_sync(); 98 au_sync();
106 } 99 }
107#endif 100#endif
108 101
@@ -116,27 +109,27 @@ void __init board_setup(void)
116#endif 109#endif
117#endif 110#endif
118 111
119 /* The Pb1200 development board uses external MUX for PSC0 to 112 /*
120 support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI 113 * The Pb1200 development board uses external MUX for PSC0 to
121 */ 114 * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
115 */
122#ifdef CONFIG_I2C_AU1550 116#ifdef CONFIG_I2C_AU1550
123 bcsr->resets &= (~BCSR_RESETS_PCS0MUX); 117 bcsr->resets &= ~BCSR_RESETS_PCS0MUX;
124#endif 118#endif
125 au_sync(); 119 au_sync();
126 120
127#ifdef CONFIG_MIPS_PB1200 121#ifdef CONFIG_MIPS_PB1200
128 printk("AMD Alchemy Pb1200 Board\n"); 122 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
129#endif 123#endif
130#ifdef CONFIG_MIPS_DB1200 124#ifdef CONFIG_MIPS_DB1200
131 printk("AMD Alchemy Db1200 Board\n"); 125 printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
132#endif 126#endif
133 127
134 /* Setup Pb1200 External Interrupt Controller */ 128 /* Setup Pb1200 External Interrupt Controller */
135 board_init_irq = _board_init_irq; 129 board_init_irq = _board_init_irq;
136} 130}
137 131
138int 132int board_au1200fb_panel(void)
139board_au1200fb_panel(void)
140{ 133{
141 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 134 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
142 int p; 135 int p;
@@ -147,23 +140,23 @@ board_au1200fb_panel(void)
147 return p; 140 return p;
148} 141}
149 142
150int 143int board_au1200fb_panel_init(void)
151board_au1200fb_panel_init(void)
152{ 144{
153 /* Apply power */ 145 /* Apply power */
154 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 146 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
155 bcsr->board |= (BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL); 147
156 /*printk("board_au1200fb_panel_init()\n"); */ 148 bcsr->board |= BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL;
149 /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
157 return 0; 150 return 0;
158} 151}
159 152
160int 153int board_au1200fb_panel_shutdown(void)
161board_au1200fb_panel_shutdown(void)
162{ 154{
163 /* Remove power */ 155 /* Remove power */
164 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 156 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
165 bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL); 157
166 /*printk("board_au1200fb_panel_shutdown()\n"); */ 158 bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
159 BCSR_BOARD_LCDBL);
160 /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
167 return 0; 161 return 0;
168} 162}
169
diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/au1000/pb1200/init.c
index 72af5500660b..09fd63b86062 100644
--- a/arch/mips/au1000/pb1200/init.c
+++ b/arch/mips/au1000/pb1200/init.c
@@ -3,9 +3,8 @@
3 * BRIEF MODULE DESCRIPTION 3 * BRIEF MODULE DESCRIPTION
4 * PB1200 board setup 4 * PB1200 board setup
5 * 5 *
6 * Copyright 2001 MontaVista Software Inc. 6 * Copyright 2001, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. 7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * ppopov@mvista.com or source@mvista.com
9 * 8 *
10 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
@@ -45,16 +44,15 @@ void __init prom_init(void)
45 unsigned char *memsize_str; 44 unsigned char *memsize_str;
46 unsigned long memsize; 45 unsigned long memsize;
47 46
48 prom_argc = (int) fw_arg0; 47 prom_argc = (int)fw_arg0;
49 prom_argv = (char **) fw_arg1; 48 prom_argv = (char **)fw_arg1;
50 prom_envp = (char **) fw_arg2; 49 prom_envp = (char **)fw_arg2;
51 50
52 prom_init_cmdline(); 51 prom_init_cmdline();
53 memsize_str = prom_getenv("memsize"); 52 memsize_str = prom_getenv("memsize");
54 if (!memsize_str) { 53 if (!memsize_str)
55 memsize = 0x08000000; 54 memsize = 0x08000000;
56 } else { 55 else
57 memsize = simple_strtol(memsize_str, NULL, 0); 56 memsize = strict_strtol(memsize_str, 0, NULL);
58 }
59 add_memory_region(0, memsize, BOOT_MEM_RAM); 57 add_memory_region(0, memsize, BOOT_MEM_RAM);
60} 58}
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c
index e61eb8e0b76b..2a505ad8715b 100644
--- a/arch/mips/au1000/pb1200/irqmap.c
+++ b/arch/mips/au1000/pb1200/irqmap.c
@@ -39,25 +39,25 @@
39#endif 39#endif
40 40
41struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { 41struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
42 { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade 42 /* This is external interrupt cascade */
43 { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 },
43}; 44};
44 45
45int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); 46int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
46 47
47/* 48/*
48 * Support for External interrupts on the PbAu1200 Development platform. 49 * Support for External interrupts on the Pb1200 Development platform.
49 */ 50 */
50static volatile int pb1200_cascade_en=0; 51static volatile int pb1200_cascade_en;
51 52
52irqreturn_t pb1200_cascade_handler( int irq, void *dev_id) 53irqreturn_t pb1200_cascade_handler(int irq, void *dev_id)
53{ 54{
54 unsigned short bisr = bcsr->int_status; 55 unsigned short bisr = bcsr->int_status;
55 int extirq_nr = 0; 56 int extirq_nr = 0;
56 57
57 /* Clear all the edge interrupts. This has no effect on level */ 58 /* Clear all the edge interrupts. This has no effect on level. */
58 bcsr->int_status = bisr; 59 bcsr->int_status = bisr;
59 for( ; bisr; bisr &= (bisr-1) ) 60 for ( ; bisr; bisr &= bisr - 1) {
60 {
61 extirq_nr = PB1200_INT_BEGIN + __ffs(bisr); 61 extirq_nr = PB1200_INT_BEGIN + __ffs(bisr);
62 /* Ack and dispatch IRQ */ 62 /* Ack and dispatch IRQ */
63 do_IRQ(extirq_nr); 63 do_IRQ(extirq_nr);
@@ -68,26 +68,20 @@ irqreturn_t pb1200_cascade_handler( int irq, void *dev_id)
68 68
69inline void pb1200_enable_irq(unsigned int irq_nr) 69inline void pb1200_enable_irq(unsigned int irq_nr)
70{ 70{
71 bcsr->intset_mask = 1<<(irq_nr - PB1200_INT_BEGIN); 71 bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
72 bcsr->intset = 1<<(irq_nr - PB1200_INT_BEGIN); 72 bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN);
73} 73}
74 74
75inline void pb1200_disable_irq(unsigned int irq_nr) 75inline void pb1200_disable_irq(unsigned int irq_nr)
76{ 76{
77 bcsr->intclr_mask = 1<<(irq_nr - PB1200_INT_BEGIN); 77 bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
78 bcsr->intclr = 1<<(irq_nr - PB1200_INT_BEGIN); 78 bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN);
79} 79}
80 80
81static unsigned int pb1200_setup_cascade(void) 81static unsigned int pb1200_setup_cascade(void)
82{ 82{
83 int err; 83 return request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
84 84 0, "Pb1200 Cascade", &pb1200_cascade_handler);
85 err = request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
86 0, "Pb1200 Cascade", &pb1200_cascade_handler);
87 if (err)
88 return err;
89
90 return 0;
91} 85}
92 86
93static unsigned int pb1200_startup_irq(unsigned int irq) 87static unsigned int pb1200_startup_irq(unsigned int irq)
@@ -132,23 +126,23 @@ void _board_init_irq(void)
132 unsigned int irq; 126 unsigned int irq;
133 127
134#ifdef CONFIG_MIPS_PB1200 128#ifdef CONFIG_MIPS_PB1200
135 /* We have a problem with CPLD rev3. Enable a workaround */ 129 /* We have a problem with CPLD rev 3. */
136 if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) { 130 if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) {
137 printk("\nWARNING!!!\n"); 131 printk(KERN_ERR "WARNING!!!\n");
138 printk("\nWARNING!!!\n"); 132 printk(KERN_ERR "WARNING!!!\n");
139 printk("\nWARNING!!!\n"); 133 printk(KERN_ERR "WARNING!!!\n");
140 printk("\nWARNING!!!\n"); 134 printk(KERN_ERR "WARNING!!!\n");
141 printk("\nWARNING!!!\n"); 135 printk(KERN_ERR "WARNING!!!\n");
142 printk("\nWARNING!!!\n"); 136 printk(KERN_ERR "WARNING!!!\n");
143 printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n"); 137 printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
144 printk("updated to latest revision. This software will not\n"); 138 printk(KERN_ERR "updated to latest revision. This software will\n");
145 printk("work on anything less than CPLD rev4\n"); 139 printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
146 printk("\nWARNING!!!\n"); 140 printk(KERN_ERR "WARNING!!!\n");
147 printk("\nWARNING!!!\n"); 141 printk(KERN_ERR "WARNING!!!\n");
148 printk("\nWARNING!!!\n"); 142 printk(KERN_ERR "WARNING!!!\n");
149 printk("\nWARNING!!!\n"); 143 printk(KERN_ERR "WARNING!!!\n");
150 printk("\nWARNING!!!\n"); 144 printk(KERN_ERR "WARNING!!!\n");
151 printk("\nWARNING!!!\n"); 145 printk(KERN_ERR "WARNING!!!\n");
152 panic("Game over. Your score is 0."); 146 panic("Game over. Your score is 0.");
153 } 147 }
154#endif 148#endif
@@ -161,6 +155,6 @@ void _board_init_irq(void)
161 155
162 /* 156 /*
163 * GPIO_7 can not be hooked here, so it is hooked upon first 157 * GPIO_7 can not be hooked here, so it is hooked upon first
164 * request of any source attached to the cascade 158 * request of any source attached to the cascade.
165 */ 159 */
166} 160}
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
index eedd048a7261..27f26102b1bb 100644
--- a/include/asm-mips/mach-db1x00/db1200.h
+++ b/include/asm-mips/mach-db1x00/db1200.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * AMD Alchemy DB1200 Referrence Board 2 * AMD Alchemy DBAu1200 Reference Board
3 * Board Registers defines. 3 * Board register defines.
4 * 4 *
5 * ######################################################################## 5 * ########################################################################
6 * 6 *
@@ -27,26 +27,25 @@
27#include <linux/types.h> 27#include <linux/types.h>
28#include <asm/mach-au1x00/au1xxx_psc.h> 28#include <asm/mach-au1x00/au1xxx_psc.h>
29 29
30// This is defined in au1000.h with bogus value 30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31#undef AU1X00_EXTERNAL_INT 31#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
32 34
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 35/*
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 36 * SPI and SMB are muxed on the DBAu1200 board.
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX 37 * Refer to board documentation.
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
37
38/* SPI and SMB are muxed on the Pb1200 board.
39 Refer to board documentation.
40 */ 38 */
41#define SPI_PSC_BASE PSC0_BASE_ADDR 39#define SPI_PSC_BASE PSC0_BASE_ADDR
42#define SMBUS_PSC_BASE PSC0_BASE_ADDR 40#define SMBUS_PSC_BASE PSC0_BASE_ADDR
43/* AC97 and I2S are muxed on the Pb1200 board. 41/*
44 Refer to board documentation. 42 * AC'97 and I2S are muxed on the DBAu1200 board.
43 * Refer to board documentation.
45 */ 44 */
46#define AC97_PSC_BASE PSC1_BASE_ADDR 45#define AC97_PSC_BASE PSC1_BASE_ADDR
47#define I2S_PSC_BASE PSC1_BASE_ADDR 46#define I2S_PSC_BASE PSC1_BASE_ADDR
48 47
49#define BCSR_KSEG1_ADDR 0xB9800000 48#define BCSR_KSEG1_ADDR 0xB9800000
50 49
51typedef volatile struct 50typedef volatile struct
52{ 51{
@@ -102,9 +101,9 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
102#define BCSR_STATUS_SWAPBOOT 0x0040 101#define BCSR_STATUS_SWAPBOOT 0x0040
103#define BCSR_STATUS_FLASHBUSY 0x0100 102#define BCSR_STATUS_FLASHBUSY 0x0100
104#define BCSR_STATUS_IDECBLID 0x0200 103#define BCSR_STATUS_IDECBLID 0x0200
105#define BCSR_STATUS_SD0WP 0x0400 104#define BCSR_STATUS_SD0WP 0x0400
106#define BCSR_STATUS_U0RXD 0x1000 105#define BCSR_STATUS_U0RXD 0x1000
107#define BCSR_STATUS_U1RXD 0x2000 106#define BCSR_STATUS_U1RXD 0x2000
108 107
109#define BCSR_SWITCHES_OCTAL 0x00FF 108#define BCSR_SWITCHES_OCTAL 0x00FF
110#define BCSR_SWITCHES_DIP_1 0x0080 109#define BCSR_SWITCHES_DIP_1 0x0080
@@ -122,8 +121,8 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
122#define BCSR_RESETS_DC 0x0004 121#define BCSR_RESETS_DC 0x0004
123#define BCSR_RESETS_IDE 0x0008 122#define BCSR_RESETS_IDE 0x0008
124#define BCSR_RESETS_TV 0x0010 123#define BCSR_RESETS_TV 0x0010
125/* not resets but in the same register */ 124/* Not resets but in the same register */
126#define BCSR_RESETS_PWMR1mUX 0x0800 125#define BCSR_RESETS_PWMR1MUX 0x0800
127#define BCSR_RESETS_PCS0MUX 0x1000 126#define BCSR_RESETS_PCS0MUX 0x1000
128#define BCSR_RESETS_PCS1MUX 0x2000 127#define BCSR_RESETS_PCS1MUX 0x2000
129#define BCSR_RESETS_SPISEL 0x4000 128#define BCSR_RESETS_SPISEL 0x4000
@@ -160,7 +159,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
160#define BCSR_INT_PC0STSCHG 0x0008 159#define BCSR_INT_PC0STSCHG 0x0008
161#define BCSR_INT_PC1 0x0010 160#define BCSR_INT_PC1 0x0010
162#define BCSR_INT_PC1STSCHG 0x0020 161#define BCSR_INT_PC1STSCHG 0x0020
163#define BCSR_INT_DC 0x0040 162#define BCSR_INT_DC 0x0040
164#define BCSR_INT_FLASHBUSY 0x0080 163#define BCSR_INT_FLASHBUSY 0x0080
165#define BCSR_INT_PC0INSERT 0x0100 164#define BCSR_INT_PC0INSERT 0x0100
166#define BCSR_INT_PC0EJECT 0x0200 165#define BCSR_INT_PC0EJECT 0x0200
@@ -179,10 +178,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
179#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 178#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
180#define IDE_RQSIZE 128 179#define IDE_RQSIZE 128
181 180
182#define NAND_PHYS_ADDR 0x20000000 181#define NAND_PHYS_ADDR 0x20000000
183 182
184/* 183/*
185 * External Interrupts for Pb1200 as of 8/6/2004. 184 * External Interrupts for DBAu1200 as of 8/6/2004.
186 * Bit positions in the CPLD registers can be calculated by taking 185 * Bit positions in the CPLD registers can be calculated by taking
187 * the interrupt define and subtracting the DB1200_INT_BEGIN value. 186 * the interrupt define and subtracting the DB1200_INT_BEGIN value.
188 * 187 *
@@ -211,23 +210,21 @@ enum external_pb1200_ints {
211}; 210};
212 211
213 212
214/* For drivers/pcmcia/au1000_db1x00.c */ 213/*
215 214 * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
216/* PCMCIA Db1x00 specific defines */ 215 */
217 216#define PCMCIA_MAX_SOCK 1
218#define PCMCIA_MAX_SOCK 1 217#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
219#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
220 218
221/* VPP/VCC */ 219/* VPP/VCC */
222#define SET_VCC_VPP(VCC, VPP, SLOT)\ 220#define SET_VCC_VPP(VCC, VPP, SLOT) \
223 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 221 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
224 222
225#define BOARD_PC0_INT DB1200_PC0_INT 223#define BOARD_PC0_INT DB1200_PC0_INT
226#define BOARD_PC1_INT DB1200_PC1_INT 224#define BOARD_PC1_INT DB1200_PC1_INT
227#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) 225#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
228 226
229/* Nand chip select */ 227/* NAND chip select */
230#define NAND_CS 1 228#define NAND_CS 1
231 229
232#endif /* __ASM_DB1200_H */ 230#endif /* __ASM_DB1200_H */
233
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
index e2c6bcac3b42..c8618df88cb5 100644
--- a/include/asm-mips/mach-pb1x00/pb1200.h
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * AMD Alchemy PB1200 Referrence Board 2 * AMD Alchemy Pb1200 Referrence Board
3 * Board Registers defines. 3 * Board Registers defines.
4 * 4 *
5 * ######################################################################## 5 * ########################################################################
@@ -27,21 +27,20 @@
27#include <linux/types.h> 27#include <linux/types.h>
28#include <asm/mach-au1x00/au1xxx_psc.h> 28#include <asm/mach-au1x00/au1xxx_psc.h>
29 29
30// This is defined in au1000.h with bogus value 30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31#undef AU1X00_EXTERNAL_INT 31#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
32 34
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 35/*
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 36 * SPI and SMB are muxed on the Pb1200 board.
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX 37 * Refer to board documentation.
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
37
38/* SPI and SMB are muxed on the Pb1200 board.
39 Refer to board documentation.
40 */ 38 */
41#define SPI_PSC_BASE PSC0_BASE_ADDR 39#define SPI_PSC_BASE PSC0_BASE_ADDR
42#define SMBUS_PSC_BASE PSC0_BASE_ADDR 40#define SMBUS_PSC_BASE PSC0_BASE_ADDR
43/* AC97 and I2S are muxed on the Pb1200 board. 41/*
44 Refer to board documentation. 42 * AC97 and I2S are muxed on the Pb1200 board.
43 * Refer to board documentation.
45 */ 44 */
46#define AC97_PSC_BASE PSC1_BASE_ADDR 45#define AC97_PSC_BASE PSC1_BASE_ADDR
47#define I2S_PSC_BASE PSC1_BASE_ADDR 46#define I2S_PSC_BASE PSC1_BASE_ADDR
@@ -102,10 +101,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
102#define BCSR_STATUS_SWAPBOOT 0x0040 101#define BCSR_STATUS_SWAPBOOT 0x0040
103#define BCSR_STATUS_FLASHBUSY 0x0100 102#define BCSR_STATUS_FLASHBUSY 0x0100
104#define BCSR_STATUS_IDECBLID 0x0200 103#define BCSR_STATUS_IDECBLID 0x0200
105#define BCSR_STATUS_SD0WP 0x0400 104#define BCSR_STATUS_SD0WP 0x0400
106#define BCSR_STATUS_SD1WP 0x0800 105#define BCSR_STATUS_SD1WP 0x0800
107#define BCSR_STATUS_U0RXD 0x1000 106#define BCSR_STATUS_U0RXD 0x1000
108#define BCSR_STATUS_U1RXD 0x2000 107#define BCSR_STATUS_U1RXD 0x2000
109 108
110#define BCSR_SWITCHES_OCTAL 0x00FF 109#define BCSR_SWITCHES_OCTAL 0x00FF
111#define BCSR_SWITCHES_DIP_1 0x0080 110#define BCSR_SWITCHES_DIP_1 0x0080
@@ -123,11 +122,11 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
123#define BCSR_RESETS_DC 0x0004 122#define BCSR_RESETS_DC 0x0004
124#define BCSR_RESETS_IDE 0x0008 123#define BCSR_RESETS_IDE 0x0008
125/* not resets but in the same register */ 124/* not resets but in the same register */
126#define BCSR_RESETS_WSCFSM 0x0800 125#define BCSR_RESETS_WSCFSM 0x0800
127#define BCSR_RESETS_PCS0MUX 0x1000 126#define BCSR_RESETS_PCS0MUX 0x1000
128#define BCSR_RESETS_PCS1MUX 0x2000 127#define BCSR_RESETS_PCS1MUX 0x2000
129#define BCSR_RESETS_SPISEL 0x4000 128#define BCSR_RESETS_SPISEL 0x4000
130#define BCSR_RESETS_SD1MUX 0x8000 129#define BCSR_RESETS_SD1MUX 0x8000
131 130
132#define BCSR_PCMCIA_PC0VPP 0x0003 131#define BCSR_PCMCIA_PC0VPP 0x0003
133#define BCSR_PCMCIA_PC0VCC 0x000C 132#define BCSR_PCMCIA_PC0VCC 0x000C
@@ -163,7 +162,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
163#define BCSR_INT_PC0STSCHG 0x0008 162#define BCSR_INT_PC0STSCHG 0x0008
164#define BCSR_INT_PC1 0x0010 163#define BCSR_INT_PC1 0x0010
165#define BCSR_INT_PC1STSCHG 0x0020 164#define BCSR_INT_PC1STSCHG 0x0020
166#define BCSR_INT_DC 0x0040 165#define BCSR_INT_DC 0x0040
167#define BCSR_INT_FLASHBUSY 0x0080 166#define BCSR_INT_FLASHBUSY 0x0080
168#define BCSR_INT_PC0INSERT 0x0100 167#define BCSR_INT_PC0INSERT 0x0100
169#define BCSR_INT_PC0EJECT 0x0200 168#define BCSR_INT_PC0EJECT 0x0200
@@ -174,14 +173,6 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
174#define BCSR_INT_SD1INSERT 0x4000 173#define BCSR_INT_SD1INSERT 0x4000
175#define BCSR_INT_SD1EJECT 0x8000 174#define BCSR_INT_SD1EJECT 0x8000
176 175
177/* PCMCIA Db1x00 specific defines */
178#define PCMCIA_MAX_SOCK 1
179#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
180
181/* VPP/VCC */
182#define SET_VCC_VPP(VCC, VPP, SLOT)\
183 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
184
185#define SMC91C111_PHYS_ADDR 0x0D000300 176#define SMC91C111_PHYS_ADDR 0x0D000300
186#define SMC91C111_INT PB1200_ETH_INT 177#define SMC91C111_INT PB1200_ETH_INT
187 178
@@ -192,18 +183,19 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
192#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 183#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
193#define IDE_RQSIZE 128 184#define IDE_RQSIZE 128
194 185
195#define NAND_PHYS_ADDR 0x1C000000 186#define NAND_PHYS_ADDR 0x1C000000
196 187
197/* Timing values as described in databook, * ns value stripped of 188/*
189 * Timing values as described in databook, * ns value stripped of
198 * lower 2 bits. 190 * lower 2 bits.
199 * These defines are here rather than an SOC1200 generic file because 191 * These defines are here rather than an Au1200 generic file because
200 * the parts chosen on another board may be different and may require 192 * the parts chosen on another board may be different and may require
201 * different timings. 193 * different timings.
202 */ 194 */
203#define NAND_T_H (18 >> 2) 195#define NAND_T_H (18 >> 2)
204#define NAND_T_PUL (30 >> 2) 196#define NAND_T_PUL (30 >> 2)
205#define NAND_T_SU (30 >> 2) 197#define NAND_T_SU (30 >> 2)
206#define NAND_T_WH (30 >> 2) 198#define NAND_T_WH (30 >> 2)
207 199
208/* Bitfield shift amounts */ 200/* Bitfield shift amounts */
209#define NAND_T_H_SHIFT 0 201#define NAND_T_H_SHIFT 0
@@ -211,11 +203,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
211#define NAND_T_SU_SHIFT 8 203#define NAND_T_SU_SHIFT 8
212#define NAND_T_WH_SHIFT 12 204#define NAND_T_WH_SHIFT 12
213 205
214#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 206#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
215 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 207 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
216 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 208 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
217 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) 209 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
218
219 210
220/* 211/*
221 * External Interrupts for Pb1200 as of 8/6/2004. 212 * External Interrupts for Pb1200 as of 8/6/2004.
@@ -248,13 +239,21 @@ enum external_pb1200_ints {
248 PB1200_INT_END = PB1200_INT_BEGIN + 15 239 PB1200_INT_END = PB1200_INT_BEGIN + 15
249}; 240};
250 241
251/* For drivers/pcmcia/au1000_db1x00.c */ 242/*
252#define BOARD_PC0_INT PB1200_PC0_INT 243 * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
253#define BOARD_PC1_INT PB1200_PC1_INT 244 */
254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) 245#define PCMCIA_MAX_SOCK 1
246#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
255 247
256/* Nand chip select */ 248/* VPP/VCC */
249#define SET_VCC_VPP(VCC, VPP, SLOT) \
250 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
251
252#define BOARD_PC0_INT PB1200_PC0_INT
253#define BOARD_PC1_INT PB1200_PC1_INT
254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
255
256/* NAND chip select */
257#define NAND_CS 1 257#define NAND_CS 1
258 258
259#endif /* __ASM_PB1200_H */ 259#endif /* __ASM_PB1200_H */
260
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