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-rw-r--r--arch/avr32/Kconfig5
-rw-r--r--arch/avr32/kernel/entry-avr32b.S20
-rw-r--r--arch/avr32/kernel/process.c6
-rw-r--r--arch/avr32/kernel/time.c248
-rw-r--r--arch/avr32/mach-at32ap/Makefile3
-rw-r--r--arch/avr32/mach-at32ap/at32ap700x.c243
-rw-r--r--arch/avr32/mach-at32ap/intc.c1
-rw-r--r--arch/avr32/mach-at32ap/pm-at32ap700x.S66
-rw-r--r--arch/avr32/mach-at32ap/time-tc.c218
-rw-r--r--arch/avr32/mm/init.c3
-rw-r--r--arch/avr32/oprofile/op_model_avr32.c1
-rw-r--r--drivers/char/Kconfig4
-rw-r--r--drivers/char/keyboard.c3
-rw-r--r--drivers/clocksource/Makefile1
-rw-r--r--drivers/clocksource/tcb_clksrc.c302
-rw-r--r--drivers/misc/Kconfig33
-rw-r--r--drivers/misc/Makefile1
-rw-r--r--drivers/misc/atmel_tclib.c161
-rw-r--r--drivers/parport/Kconfig2
-rw-r--r--drivers/usb/gadget/Kconfig4
-rw-r--r--drivers/usb/gadget/atmel_usba_udc.c156
-rw-r--r--drivers/usb/gadget/atmel_usba_udc.h9
-rw-r--r--include/asm-avr32/arch-at32ap/board.h9
-rw-r--r--include/asm-avr32/arch-at32ap/pm.h48
-rw-r--r--include/asm-avr32/arch-at32ap/time.h112
-rw-r--r--include/asm-avr32/asm.h8
-rw-r--r--include/asm-avr32/intc.h128
-rw-r--r--include/asm-avr32/irq.h5
-rw-r--r--include/asm-avr32/page.h8
-rw-r--r--include/asm-avr32/serial.h13
-rw-r--r--include/asm-avr32/xor.h6
-rw-r--r--include/linux/atmel_tc.h252
-rw-r--r--include/linux/usb/atmel_usba_udc.h22
33 files changed, 1329 insertions, 772 deletions
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index 28e0caf4156c..09ad7995080c 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -47,6 +47,9 @@ config RWSEM_GENERIC_SPINLOCK
47config GENERIC_TIME 47config GENERIC_TIME
48 def_bool y 48 def_bool y
49 49
50config GENERIC_CLOCKEVENTS
51 def_bool y
52
50config RWSEM_XCHGADD_ALGORITHM 53config RWSEM_XCHGADD_ALGORITHM
51 def_bool n 54 def_bool n
52 55
@@ -70,6 +73,8 @@ source "init/Kconfig"
70 73
71menu "System Type and features" 74menu "System Type and features"
72 75
76source "kernel/time/Kconfig"
77
73config SUBARCH_AVR32B 78config SUBARCH_AVR32B
74 bool 79 bool
75config MMU 80config MMU
diff --git a/arch/avr32/kernel/entry-avr32b.S b/arch/avr32/kernel/entry-avr32b.S
index 8cf16d7a7040..5f31702d6b1c 100644
--- a/arch/avr32/kernel/entry-avr32b.S
+++ b/arch/avr32/kernel/entry-avr32b.S
@@ -741,26 +741,6 @@ irq_level\level:
741 741
742 .section .irq.text,"ax",@progbits 742 .section .irq.text,"ax",@progbits
743 743
744.global cpu_idle_sleep
745cpu_idle_sleep:
746 mask_interrupts
747 get_thread_info r8
748 ld.w r9, r8[TI_flags]
749 bld r9, TIF_NEED_RESCHED
750 brcs cpu_idle_enable_int_and_exit
751 sbr r9, TIF_CPU_GOING_TO_SLEEP
752 st.w r8[TI_flags], r9
753 unmask_interrupts
754 sleep 0
755cpu_idle_skip_sleep:
756 mask_interrupts
757 ld.w r9, r8[TI_flags]
758 cbr r9, TIF_CPU_GOING_TO_SLEEP
759 st.w r8[TI_flags], r9
760cpu_idle_enable_int_and_exit:
761 unmask_interrupts
762 retal r12
763
764 .global irq_level0 744 .global irq_level0
765 .global irq_level1 745 .global irq_level1
766 .global irq_level2 746 .global irq_level2
diff --git a/arch/avr32/kernel/process.c b/arch/avr32/kernel/process.c
index 7f4af0b1e111..6cf9df176274 100644
--- a/arch/avr32/kernel/process.c
+++ b/arch/avr32/kernel/process.c
@@ -18,11 +18,11 @@
18#include <asm/sysreg.h> 18#include <asm/sysreg.h>
19#include <asm/ocd.h> 19#include <asm/ocd.h>
20 20
21#include <asm/arch/pm.h>
22
21void (*pm_power_off)(void) = NULL; 23void (*pm_power_off)(void) = NULL;
22EXPORT_SYMBOL(pm_power_off); 24EXPORT_SYMBOL(pm_power_off);
23 25
24extern void cpu_idle_sleep(void);
25
26/* 26/*
27 * This file handles the architecture-dependent parts of process handling.. 27 * This file handles the architecture-dependent parts of process handling..
28 */ 28 */
@@ -54,6 +54,8 @@ void machine_halt(void)
54 54
55void machine_power_off(void) 55void machine_power_off(void)
56{ 56{
57 if (pm_power_off)
58 pm_power_off();
57} 59}
58 60
59void machine_restart(char *cmd) 61void machine_restart(char *cmd)
diff --git a/arch/avr32/kernel/time.c b/arch/avr32/kernel/time.c
index 36a46c3ae308..00a9862380ff 100644
--- a/arch/avr32/kernel/time.c
+++ b/arch/avr32/kernel/time.c
@@ -1,16 +1,12 @@
1/* 1/*
2 * Copyright (C) 2004-2007 Atmel Corporation 2 * Copyright (C) 2004-2007 Atmel Corporation
3 * 3 *
4 * Based on MIPS implementation arch/mips/kernel/time.c
5 * Copyright 2001 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
10 */ 7 */
11
12#include <linux/clk.h> 8#include <linux/clk.h>
13#include <linux/clocksource.h> 9#include <linux/clockchips.h>
14#include <linux/time.h> 10#include <linux/time.h>
15#include <linux/module.h> 11#include <linux/module.h>
16#include <linux/interrupt.h> 12#include <linux/interrupt.h>
@@ -27,207 +23,133 @@
27#include <asm/io.h> 23#include <asm/io.h>
28#include <asm/sections.h> 24#include <asm/sections.h>
29 25
30/* how many counter cycles in a jiffy? */ 26#include <asm/arch/pm.h>
31static u32 cycles_per_jiffy;
32 27
33/* the count value for the next timer interrupt */
34static u32 expirelo;
35 28
36cycle_t __weak read_cycle_count(void) 29static cycle_t read_cycle_count(void)
37{ 30{
38 return (cycle_t)sysreg_read(COUNT); 31 return (cycle_t)sysreg_read(COUNT);
39} 32}
40 33
41struct clocksource __weak clocksource_avr32 = { 34/*
42 .name = "avr32", 35 * The architectural cycle count registers are a fine clocksource unless
43 .rating = 350, 36 * the system idle loop use sleep states like "idle": the CPU cycles
37 * measured by COUNT (and COMPARE) don't happen during sleep states.
38 * Their duration also changes if cpufreq changes the CPU clock rate.
39 * So we rate the clocksource using COUNT as very low quality.
40 */
41static struct clocksource counter = {
42 .name = "avr32_counter",
43 .rating = 50,
44 .read = read_cycle_count, 44 .read = read_cycle_count,
45 .mask = CLOCKSOURCE_MASK(32), 45 .mask = CLOCKSOURCE_MASK(32),
46 .shift = 16, 46 .shift = 16,
47 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 47 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
48}; 48};
49 49
50irqreturn_t __weak timer_interrupt(int irq, void *dev_id); 50static irqreturn_t timer_interrupt(int irq, void *dev_id)
51
52struct irqaction timer_irqaction = {
53 .handler = timer_interrupt,
54 .flags = IRQF_DISABLED,
55 .name = "timer",
56};
57
58/*
59 * By default we provide the null RTC ops
60 */
61static unsigned long null_rtc_get_time(void)
62{ 51{
63 return mktime(2007, 1, 1, 0, 0, 0); 52 struct clock_event_device *evdev = dev_id;
64}
65
66static int null_rtc_set_time(unsigned long sec)
67{
68 return 0;
69}
70 53
71static unsigned long (*rtc_get_time)(void) = null_rtc_get_time; 54 /*
72static int (*rtc_set_time)(unsigned long) = null_rtc_set_time; 55 * Disable the interrupt until the clockevent subsystem
73 56 * reprograms it.
74static void avr32_timer_ack(void) 57 */
75{ 58 sysreg_write(COMPARE, 0);
76 u32 count;
77
78 /* Ack this timer interrupt and set the next one */
79 expirelo += cycles_per_jiffy;
80 /* setting COMPARE to 0 stops the COUNT-COMPARE */
81 if (expirelo == 0) {
82 sysreg_write(COMPARE, expirelo + 1);
83 } else {
84 sysreg_write(COMPARE, expirelo);
85 }
86 59
87 /* Check to see if we have missed any timer interrupts */ 60 evdev->event_handler(evdev);
88 count = sysreg_read(COUNT); 61 return IRQ_HANDLED;
89 if ((count - expirelo) < 0x7fffffff) {
90 expirelo = count + cycles_per_jiffy;
91 sysreg_write(COMPARE, expirelo);
92 }
93} 62}
94 63
95int __weak avr32_hpt_init(void) 64static struct irqaction timer_irqaction = {
96{ 65 .handler = timer_interrupt,
97 int ret; 66 .flags = IRQF_TIMER | IRQF_DISABLED,
98 unsigned long mult, shift, count_hz; 67 .name = "avr32_comparator",
99 68};
100 count_hz = clk_get_rate(boot_cpu_data.clk);
101 shift = clocksource_avr32.shift;
102 mult = clocksource_hz2mult(count_hz, shift);
103 clocksource_avr32.mult = mult;
104
105 {
106 u64 tmp;
107
108 tmp = TICK_NSEC;
109 tmp <<= shift;
110 tmp += mult / 2;
111 do_div(tmp, mult);
112
113 cycles_per_jiffy = tmp;
114 }
115 69
116 ret = setup_irq(0, &timer_irqaction); 70static int comparator_next_event(unsigned long delta,
117 if (ret) { 71 struct clock_event_device *evdev)
118 pr_debug("timer: could not request IRQ 0: %d\n", ret); 72{
119 return -ENODEV; 73 unsigned long flags;
120 }
121 74
122 printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, " 75 raw_local_irq_save(flags);
123 "%lu.%03lu MHz\n",
124 ((count_hz + 500) / 1000) / 1000,
125 ((count_hz + 500) / 1000) % 1000);
126 76
127 return 0; 77 /* The time to read COUNT then update COMPARE must be less
128} 78 * than the min_delta_ns value for this clockevent source.
79 */
80 sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);
129 81
130/* 82 raw_local_irq_restore(flags);
131 * Taken from MIPS c0_hpt_timer_init().
132 *
133 * The reason COUNT is written twice is probably to make sure we don't get any
134 * timer interrupts while we are messing with the counter.
135 */
136int __weak avr32_hpt_start(void)
137{
138 u32 count = sysreg_read(COUNT);
139 expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
140 sysreg_write(COUNT, expirelo - cycles_per_jiffy);
141 sysreg_write(COMPARE, expirelo);
142 sysreg_write(COUNT, count);
143 83
144 return 0; 84 return 0;
145} 85}
146 86
147/* 87static void comparator_mode(enum clock_event_mode mode,
148 * local_timer_interrupt() does profiling and process accounting on a 88 struct clock_event_device *evdev)
149 * per-CPU basis.
150 *
151 * In UP mode, it is invoked from the (global) timer_interrupt.
152 */
153void local_timer_interrupt(int irq, void *dev_id)
154{ 89{
155 if (current->pid) 90 switch (mode) {
156 profile_tick(CPU_PROFILING); 91 case CLOCK_EVT_MODE_ONESHOT:
157 update_process_times(user_mode(get_irq_regs())); 92 pr_debug("%s: start\n", evdev->name);
93 /* FALLTHROUGH */
94 case CLOCK_EVT_MODE_RESUME:
95 cpu_disable_idle_sleep();
96 break;
97 case CLOCK_EVT_MODE_UNUSED:
98 case CLOCK_EVT_MODE_SHUTDOWN:
99 sysreg_write(COMPARE, 0);
100 pr_debug("%s: stop\n", evdev->name);
101 cpu_enable_idle_sleep();
102 break;
103 default:
104 BUG();
105 }
158} 106}
159 107
160irqreturn_t __weak timer_interrupt(int irq, void *dev_id) 108static struct clock_event_device comparator = {
161{ 109 .name = "avr32_comparator",
162 /* ack timer interrupt and try to set next interrupt */ 110 .features = CLOCK_EVT_FEAT_ONESHOT,
163 avr32_timer_ack(); 111 .shift = 16,
164 112 .rating = 50,
165 /* 113 .cpumask = CPU_MASK_CPU0,
166 * Call the generic timer interrupt handler 114 .set_next_event = comparator_next_event,
167 */ 115 .set_mode = comparator_mode,
168 write_seqlock(&xtime_lock); 116};
169 do_timer(1);
170 write_sequnlock(&xtime_lock);
171
172 /*
173 * In UP mode, we call local_timer_interrupt() to do profiling
174 * and process accounting.
175 *
176 * SMP is not supported yet.
177 */
178 local_timer_interrupt(irq, dev_id);
179
180 return IRQ_HANDLED;
181}
182 117
183void __init time_init(void) 118void __init time_init(void)
184{ 119{
120 unsigned long counter_hz;
185 int ret; 121 int ret;
186 122
187 /* 123 xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
188 * Make sure we don't get any COMPARE interrupts before we can
189 * handle them.
190 */
191 sysreg_write(COMPARE, 0);
192
193 xtime.tv_sec = rtc_get_time();
194 xtime.tv_nsec = 0; 124 xtime.tv_nsec = 0;
195 125
196 set_normalized_timespec(&wall_to_monotonic, 126 set_normalized_timespec(&wall_to_monotonic,
197 -xtime.tv_sec, -xtime.tv_nsec); 127 -xtime.tv_sec, -xtime.tv_nsec);
198 128
199 ret = avr32_hpt_init(); 129 /* figure rate for counter */
200 if (ret) { 130 counter_hz = clk_get_rate(boot_cpu_data.clk);
201 pr_debug("timer: failed setup: %d\n", ret); 131 counter.mult = clocksource_hz2mult(counter_hz, counter.shift);
202 return;
203 }
204 132
205 ret = clocksource_register(&clocksource_avr32); 133 ret = clocksource_register(&counter);
206 if (ret) 134 if (ret)
207 pr_debug("timer: could not register clocksource: %d\n", ret); 135 pr_debug("timer: could not register clocksource: %d\n", ret);
208 136
209 ret = avr32_hpt_start(); 137 /* setup COMPARE clockevent */
210 if (ret) { 138 comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
211 pr_debug("timer: failed starting: %d\n", ret); 139 comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
212 return; 140 comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
213 }
214}
215 141
216static struct sysdev_class timer_class = { 142 sysreg_write(COMPARE, 0);
217 .name = "timer", 143 timer_irqaction.dev_id = &comparator;
218};
219 144
220static struct sys_device timer_device = { 145 ret = setup_irq(0, &timer_irqaction);
221 .id = 0, 146 if (ret)
222 .cls = &timer_class, 147 pr_debug("timer: could not request IRQ 0: %d\n", ret);
223}; 148 else {
149 clockevents_register_device(&comparator);
224 150
225static int __init init_timer_sysfs(void) 151 pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,
226{ 152 ((counter_hz + 500) / 1000) / 1000,
227 int err = sysdev_class_register(&timer_class); 153 ((counter_hz + 500) / 1000) % 1000);
228 if (!err) 154 }
229 err = sysdev_register(&timer_device);
230 return err;
231} 155}
232
233device_initcall(init_timer_sysfs);
diff --git a/arch/avr32/mach-at32ap/Makefile b/arch/avr32/mach-at32ap/Makefile
index 5e9f8217befc..e89009439e4a 100644
--- a/arch/avr32/mach-at32ap/Makefile
+++ b/arch/avr32/mach-at32ap/Makefile
@@ -1,4 +1,3 @@
1obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o 1obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
2obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o 2obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o
3obj-$(CONFIG_CPU_AT32AP700X) += time-tc.o
4obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o 3obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 7678fee9a885..0f24b4f85c17 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -6,11 +6,13 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8#include <linux/clk.h> 8#include <linux/clk.h>
9#include <linux/delay.h>
9#include <linux/fb.h> 10#include <linux/fb.h>
10#include <linux/init.h> 11#include <linux/init.h>
11#include <linux/platform_device.h> 12#include <linux/platform_device.h>
12#include <linux/dma-mapping.h> 13#include <linux/dma-mapping.h>
13#include <linux/spi/spi.h> 14#include <linux/spi/spi.h>
15#include <linux/usb/atmel_usba_udc.h>
14 16
15#include <asm/io.h> 17#include <asm/io.h>
16#include <asm/irq.h> 18#include <asm/irq.h>
@@ -98,6 +100,9 @@ unsigned long at32ap7000_osc_rates[3] = {
98 [2] = 12000000, 100 [2] = 12000000,
99}; 101};
100 102
103static struct clk osc0;
104static struct clk osc1;
105
101static unsigned long osc_get_rate(struct clk *clk) 106static unsigned long osc_get_rate(struct clk *clk)
102{ 107{
103 return at32ap7000_osc_rates[clk->index]; 108 return at32ap7000_osc_rates[clk->index];
@@ -107,9 +112,6 @@ static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
107{ 112{
108 unsigned long div, mul, rate; 113 unsigned long div, mul, rate;
109 114
110 if (!(control & PM_BIT(PLLEN)))
111 return 0;
112
113 div = PM_BFEXT(PLLDIV, control) + 1; 115 div = PM_BFEXT(PLLDIV, control) + 1;
114 mul = PM_BFEXT(PLLMUL, control) + 1; 116 mul = PM_BFEXT(PLLMUL, control) + 1;
115 117
@@ -120,6 +122,71 @@ static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
120 return rate; 122 return rate;
121} 123}
122 124
125static long pll_set_rate(struct clk *clk, unsigned long rate,
126 u32 *pll_ctrl)
127{
128 unsigned long mul;
129 unsigned long mul_best_fit = 0;
130 unsigned long div;
131 unsigned long div_min;
132 unsigned long div_max;
133 unsigned long div_best_fit = 0;
134 unsigned long base;
135 unsigned long pll_in;
136 unsigned long actual = 0;
137 unsigned long rate_error;
138 unsigned long rate_error_prev = ~0UL;
139 u32 ctrl;
140
141 /* Rate must be between 80 MHz and 200 Mhz. */
142 if (rate < 80000000UL || rate > 200000000UL)
143 return -EINVAL;
144
145 ctrl = PM_BF(PLLOPT, 4);
146 base = clk->parent->get_rate(clk->parent);
147
148 /* PLL input frequency must be between 6 MHz and 32 MHz. */
149 div_min = DIV_ROUND_UP(base, 32000000UL);
150 div_max = base / 6000000UL;
151
152 if (div_max < div_min)
153 return -EINVAL;
154
155 for (div = div_min; div <= div_max; div++) {
156 pll_in = (base + div / 2) / div;
157 mul = (rate + pll_in / 2) / pll_in;
158
159 if (mul == 0)
160 continue;
161
162 actual = pll_in * mul;
163 rate_error = abs(actual - rate);
164
165 if (rate_error < rate_error_prev) {
166 mul_best_fit = mul;
167 div_best_fit = div;
168 rate_error_prev = rate_error;
169 }
170
171 if (rate_error == 0)
172 break;
173 }
174
175 if (div_best_fit == 0)
176 return -EINVAL;
177
178 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
179 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
180 ctrl |= PM_BF(PLLCOUNT, 16);
181
182 if (clk->parent == &osc1)
183 ctrl |= PM_BIT(PLLOSC);
184
185 *pll_ctrl = ctrl;
186
187 return actual;
188}
189
123static unsigned long pll0_get_rate(struct clk *clk) 190static unsigned long pll0_get_rate(struct clk *clk)
124{ 191{
125 u32 control; 192 u32 control;
@@ -129,6 +196,41 @@ static unsigned long pll0_get_rate(struct clk *clk)
129 return pll_get_rate(clk, control); 196 return pll_get_rate(clk, control);
130} 197}
131 198
199static void pll1_mode(struct clk *clk, int enabled)
200{
201 unsigned long timeout;
202 u32 status;
203 u32 ctrl;
204
205 ctrl = pm_readl(PLL1);
206
207 if (enabled) {
208 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
209 pr_debug("clk %s: failed to enable, rate not set\n",
210 clk->name);
211 return;
212 }
213
214 ctrl |= PM_BIT(PLLEN);
215 pm_writel(PLL1, ctrl);
216
217 /* Wait for PLL lock. */
218 for (timeout = 10000; timeout; timeout--) {
219 status = pm_readl(ISR);
220 if (status & PM_BIT(LOCK1))
221 break;
222 udelay(10);
223 }
224
225 if (!(status & PM_BIT(LOCK1)))
226 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
227 clk->name);
228 } else {
229 ctrl &= ~PM_BIT(PLLEN);
230 pm_writel(PLL1, ctrl);
231 }
232}
233
132static unsigned long pll1_get_rate(struct clk *clk) 234static unsigned long pll1_get_rate(struct clk *clk)
133{ 235{
134 u32 control; 236 u32 control;
@@ -138,6 +240,49 @@ static unsigned long pll1_get_rate(struct clk *clk)
138 return pll_get_rate(clk, control); 240 return pll_get_rate(clk, control);
139} 241}
140 242
243static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
244{
245 u32 ctrl = 0;
246 unsigned long actual_rate;
247
248 actual_rate = pll_set_rate(clk, rate, &ctrl);
249
250 if (apply) {
251 if (actual_rate != rate)
252 return -EINVAL;
253 if (clk->users > 0)
254 return -EBUSY;
255 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
256 clk->name, rate, actual_rate);
257 pm_writel(PLL1, ctrl);
258 }
259
260 return actual_rate;
261}
262
263static int pll1_set_parent(struct clk *clk, struct clk *parent)
264{
265 u32 ctrl;
266
267 if (clk->users > 0)
268 return -EBUSY;
269
270 ctrl = pm_readl(PLL1);
271 WARN_ON(ctrl & PM_BIT(PLLEN));
272
273 if (parent == &osc0)
274 ctrl &= ~PM_BIT(PLLOSC);
275 else if (parent == &osc1)
276 ctrl |= PM_BIT(PLLOSC);
277 else
278 return -EINVAL;
279
280 pm_writel(PLL1, ctrl);
281 clk->parent = parent;
282
283 return 0;
284}
285
141/* 286/*
142 * The AT32AP7000 has five primary clock sources: One 32kHz 287 * The AT32AP7000 has five primary clock sources: One 32kHz
143 * oscillator, two crystal oscillators and two PLLs. 288 * oscillator, two crystal oscillators and two PLLs.
@@ -166,7 +311,10 @@ static struct clk pll0 = {
166}; 311};
167static struct clk pll1 = { 312static struct clk pll1 = {
168 .name = "pll1", 313 .name = "pll1",
314 .mode = pll1_mode,
169 .get_rate = pll1_get_rate, 315 .get_rate = pll1_get_rate,
316 .set_rate = pll1_set_rate,
317 .set_parent = pll1_set_parent,
170 .parent = &osc0, 318 .parent = &osc0,
171}; 319};
172 320
@@ -605,19 +753,32 @@ static inline void set_ebi_sfr_bits(u32 mask)
605} 753}
606 754
607/* -------------------------------------------------------------------- 755/* --------------------------------------------------------------------
608 * System Timer/Counter (TC) 756 * Timer/Counter (TC)
609 * -------------------------------------------------------------------- */ 757 * -------------------------------------------------------------------- */
610static struct resource at32_systc0_resource[] = { 758
759static struct resource at32_tcb0_resource[] = {
611 PBMEM(0xfff00c00), 760 PBMEM(0xfff00c00),
612 IRQ(22), 761 IRQ(22),
613}; 762};
614struct platform_device at32_systc0_device = { 763static struct platform_device at32_tcb0_device = {
615 .name = "systc", 764 .name = "atmel_tcb",
616 .id = 0, 765 .id = 0,
617 .resource = at32_systc0_resource, 766 .resource = at32_tcb0_resource,
618 .num_resources = ARRAY_SIZE(at32_systc0_resource), 767 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
619}; 768};
620DEV_CLK(pclk, at32_systc0, pbb, 3); 769DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
770
771static struct resource at32_tcb1_resource[] = {
772 PBMEM(0xfff01000),
773 IRQ(23),
774};
775static struct platform_device at32_tcb1_device = {
776 .name = "atmel_tcb",
777 .id = 1,
778 .resource = at32_tcb1_resource,
779 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
780};
781DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
621 782
622/* -------------------------------------------------------------------- 783/* --------------------------------------------------------------------
623 * PIO 784 * PIO
@@ -669,7 +830,8 @@ void __init at32_add_system_devices(void)
669 platform_device_register(&pdc_device); 830 platform_device_register(&pdc_device);
670 platform_device_register(&dmaca0_device); 831 platform_device_register(&dmaca0_device);
671 832
672 platform_device_register(&at32_systc0_device); 833 platform_device_register(&at32_tcb0_device);
834 platform_device_register(&at32_tcb1_device);
673 835
674 platform_device_register(&pio0_device); 836 platform_device_register(&pio0_device);
675 platform_device_register(&pio1_device); 837 platform_device_register(&pio1_device);
@@ -989,7 +1151,9 @@ static struct clk atmel_twi0_pclk = {
989 .index = 2, 1151 .index = 2,
990}; 1152};
991 1153
992struct platform_device *__init at32_add_device_twi(unsigned int id) 1154struct platform_device *__init at32_add_device_twi(unsigned int id,
1155 struct i2c_board_info *b,
1156 unsigned int n)
993{ 1157{
994 struct platform_device *pdev; 1158 struct platform_device *pdev;
995 1159
@@ -1009,6 +1173,9 @@ struct platform_device *__init at32_add_device_twi(unsigned int id)
1009 1173
1010 atmel_twi0_pclk.dev = &pdev->dev; 1174 atmel_twi0_pclk.dev = &pdev->dev;
1011 1175
1176 if (b)
1177 i2c_register_board_info(id, b, n);
1178
1012 platform_device_add(pdev); 1179 platform_device_add(pdev);
1013 return pdev; 1180 return pdev;
1014 1181
@@ -1351,9 +1518,39 @@ static struct clk usba0_hclk = {
1351 .index = 6, 1518 .index = 6,
1352}; 1519};
1353 1520
1521#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1522 [idx] = { \
1523 .name = nam, \
1524 .index = idx, \
1525 .fifo_size = maxpkt, \
1526 .nr_banks = maxbk, \
1527 .can_dma = dma, \
1528 .can_isoc = isoc, \
1529 }
1530
1531static struct usba_ep_data at32_usba_ep[] __initdata = {
1532 EP("ep0", 0, 64, 1, 0, 0),
1533 EP("ep1", 1, 512, 2, 1, 1),
1534 EP("ep2", 2, 512, 2, 1, 1),
1535 EP("ep3-int", 3, 64, 3, 1, 0),
1536 EP("ep4-int", 4, 64, 3, 1, 0),
1537 EP("ep5", 5, 1024, 3, 1, 1),
1538 EP("ep6", 6, 1024, 3, 1, 1),
1539};
1540
1541#undef EP
1542
1354struct platform_device *__init 1543struct platform_device *__init
1355at32_add_device_usba(unsigned int id, struct usba_platform_data *data) 1544at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1356{ 1545{
1546 /*
1547 * pdata doesn't have room for any endpoints, so we need to
1548 * append room for the ones we need right after it.
1549 */
1550 struct {
1551 struct usba_platform_data pdata;
1552 struct usba_ep_data ep[7];
1553 } usba_data;
1357 struct platform_device *pdev; 1554 struct platform_device *pdev;
1358 1555
1359 if (id != 0) 1556 if (id != 0)
@@ -1367,13 +1564,20 @@ at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1367 ARRAY_SIZE(usba0_resource))) 1564 ARRAY_SIZE(usba0_resource)))
1368 goto out_free_pdev; 1565 goto out_free_pdev;
1369 1566
1370 if (data) { 1567 if (data)
1371 if (platform_device_add_data(pdev, data, sizeof(*data))) 1568 usba_data.pdata.vbus_pin = data->vbus_pin;
1372 goto out_free_pdev; 1569 else
1570 usba_data.pdata.vbus_pin = -EINVAL;
1571
1572 data = &usba_data.pdata;
1573 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1574 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1373 1575
1374 if (data->vbus_pin != GPIO_PIN_NONE) 1576 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1375 at32_select_gpio(data->vbus_pin, 0); 1577 goto out_free_pdev;
1376 } 1578
1579 if (data->vbus_pin >= 0)
1580 at32_select_gpio(data->vbus_pin, 0);
1377 1581
1378 usba0_pclk.dev = &pdev->dev; 1582 usba0_pclk.dev = &pdev->dev;
1379 usba0_hclk.dev = &pdev->dev; 1583 usba0_hclk.dev = &pdev->dev;
@@ -1694,7 +1898,8 @@ struct clk *at32_clock_list[] = {
1694 &pio2_mck, 1898 &pio2_mck,
1695 &pio3_mck, 1899 &pio3_mck,
1696 &pio4_mck, 1900 &pio4_mck,
1697 &at32_systc0_pclk, 1901 &at32_tcb0_t0_clk,
1902 &at32_tcb1_t0_clk,
1698 &atmel_usart0_usart, 1903 &atmel_usart0_usart,
1699 &atmel_usart1_usart, 1904 &atmel_usart1_usart,
1700 &atmel_usart2_usart, 1905 &atmel_usart2_usart,
diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c
index 0b286cd53028..097cf4e84052 100644
--- a/arch/avr32/mach-at32ap/intc.c
+++ b/arch/avr32/mach-at32ap/intc.c
@@ -13,7 +13,6 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15 15
16#include <asm/intc.h>
17#include <asm/io.h> 16#include <asm/io.h>
18 17
19#include "intc.h" 18#include "intc.h"
diff --git a/arch/avr32/mach-at32ap/pm-at32ap700x.S b/arch/avr32/mach-at32ap/pm-at32ap700x.S
new file mode 100644
index 000000000000..949e2485e278
--- /dev/null
+++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
@@ -0,0 +1,66 @@
1/*
2 * Low-level Power Management code.
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <asm/asm.h>
11#include <asm/asm-offsets.h>
12#include <asm/thread_info.h>
13#include <asm/arch/pm.h>
14
15 .section .bss, "wa", @nobits
16 .global disable_idle_sleep
17 .type disable_idle_sleep, @object
18disable_idle_sleep:
19 .int 4
20 .size disable_idle_sleep, . - disable_idle_sleep
21
22 /* Keep this close to the irq handlers */
23 .section .irq.text, "ax", @progbits
24
25 /*
26 * void cpu_enter_idle(void)
27 *
28 * Put the CPU into "idle" mode, in which it will consume
29 * significantly less power.
30 *
31 * If an interrupt comes along in the window between
32 * unmask_interrupts and the sleep instruction below, the
33 * interrupt code will adjust the return address so that we
34 * never execute the sleep instruction. This is required
35 * because the AP7000 doesn't unmask interrupts when entering
36 * sleep modes; later CPUs may not need this workaround.
37 */
38 .global cpu_enter_idle
39 .type cpu_enter_idle, @function
40cpu_enter_idle:
41 mask_interrupts
42 get_thread_info r8
43 ld.w r9, r8[TI_flags]
44 bld r9, TIF_NEED_RESCHED
45 brcs .Lret_from_sleep
46 sbr r9, TIF_CPU_GOING_TO_SLEEP
47 st.w r8[TI_flags], r9
48 unmask_interrupts
49 sleep CPU_SLEEP_IDLE
50 .size cpu_idle_sleep, . - cpu_idle_sleep
51
52 /*
53 * Common return path for PM functions that don't run from
54 * SRAM.
55 */
56 .global cpu_idle_skip_sleep
57 .type cpu_idle_skip_sleep, @function
58cpu_idle_skip_sleep:
59 mask_interrupts
60 ld.w r9, r8[TI_flags]
61 cbr r9, TIF_CPU_GOING_TO_SLEEP
62 st.w r8[TI_flags], r9
63.Lret_from_sleep:
64 unmask_interrupts
65 retal r12
66 .size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
diff --git a/arch/avr32/mach-at32ap/time-tc.c b/arch/avr32/mach-at32ap/time-tc.c
deleted file mode 100644
index 10265863c982..000000000000
--- a/arch/avr32/mach-at32ap/time-tc.c
+++ /dev/null
@@ -1,218 +0,0 @@
1/*
2 * Copyright (C) 2004-2007 Atmel Corporation
3 *
4 * Based on MIPS implementation arch/mips/kernel/time.c
5 * Copyright 2001 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/clk.h>
13#include <linux/clocksource.h>
14#include <linux/time.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/kernel_stat.h>
19#include <linux/errno.h>
20#include <linux/init.h>
21#include <linux/profile.h>
22#include <linux/sysdev.h>
23#include <linux/err.h>
24
25#include <asm/div64.h>
26#include <asm/sysreg.h>
27#include <asm/io.h>
28#include <asm/sections.h>
29
30#include <asm/arch/time.h>
31
32/* how many counter cycles in a jiffy? */
33static u32 cycles_per_jiffy;
34
35/* the count value for the next timer interrupt */
36static u32 expirelo;
37
38/* the I/O registers of the TC module */
39static void __iomem *ioregs;
40
41cycle_t read_cycle_count(void)
42{
43 return (cycle_t)timer_read(ioregs, 0, CV);
44}
45
46struct clocksource clocksource_avr32 = {
47 .name = "avr32",
48 .rating = 342,
49 .read = read_cycle_count,
50 .mask = CLOCKSOURCE_MASK(16),
51 .shift = 16,
52 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
53};
54
55static void avr32_timer_ack(void)
56{
57 u16 count = expirelo;
58
59 /* Ack this timer interrupt and set the next one, use a u16
60 * variable so it will wrap around correctly */
61 count += cycles_per_jiffy;
62 expirelo = count;
63 timer_write(ioregs, 0, RC, expirelo);
64
65 /* Check to see if we have missed any timer interrupts */
66 count = timer_read(ioregs, 0, CV);
67 if ((count - expirelo) < 0x7fff) {
68 expirelo = count + cycles_per_jiffy;
69 timer_write(ioregs, 0, RC, expirelo);
70 }
71}
72
73u32 avr32_hpt_read(void)
74{
75 return timer_read(ioregs, 0, CV);
76}
77
78static int avr32_timer_calc_div_and_set_jiffies(struct clk *pclk)
79{
80 unsigned int cycles_max = (clocksource_avr32.mask + 1) / 2;
81 unsigned int divs[] = { 4, 8, 16, 32 };
82 int divs_size = ARRAY_SIZE(divs);
83 int i = 0;
84 unsigned long count_hz;
85 unsigned long shift;
86 unsigned long mult;
87 int clock_div = -1;
88 u64 tmp;
89
90 shift = clocksource_avr32.shift;
91
92 do {
93 count_hz = clk_get_rate(pclk) / divs[i];
94 mult = clocksource_hz2mult(count_hz, shift);
95 clocksource_avr32.mult = mult;
96
97 tmp = TICK_NSEC;
98 tmp <<= shift;
99 tmp += mult / 2;
100 do_div(tmp, mult);
101
102 cycles_per_jiffy = tmp;
103 } while (cycles_per_jiffy > cycles_max && ++i < divs_size);
104
105 clock_div = i + 1;
106
107 if (clock_div > divs_size) {
108 pr_debug("timer: could not calculate clock divider\n");
109 return -EFAULT;
110 }
111
112 /* Set the clock divider */
113 timer_write(ioregs, 0, CMR, TIMER_BF(CMR_TCCLKS, clock_div));
114
115 return 0;
116}
117
118int avr32_hpt_init(unsigned int count)
119{
120 struct resource *regs;
121 struct clk *pclk;
122 int irq = -1;
123 int ret = 0;
124
125 ret = -ENXIO;
126
127 irq = platform_get_irq(&at32_systc0_device, 0);
128 if (irq < 0) {
129 pr_debug("timer: could not get irq\n");
130 goto out_error;
131 }
132
133 pclk = clk_get(&at32_systc0_device.dev, "pclk");
134 if (IS_ERR(pclk)) {
135 pr_debug("timer: could not get clk: %ld\n", PTR_ERR(pclk));
136 goto out_error;
137 }
138 clk_enable(pclk);
139
140 regs = platform_get_resource(&at32_systc0_device, IORESOURCE_MEM, 0);
141 if (!regs) {
142 pr_debug("timer: could not get resource\n");
143 goto out_error_clk;
144 }
145
146 ioregs = ioremap(regs->start, regs->end - regs->start + 1);
147 if (!ioregs) {
148 pr_debug("timer: could not get ioregs\n");
149 goto out_error_clk;
150 }
151
152 ret = avr32_timer_calc_div_and_set_jiffies(pclk);
153 if (ret)
154 goto out_error_io;
155
156 ret = setup_irq(irq, &timer_irqaction);
157 if (ret) {
158 pr_debug("timer: could not request irq %d: %d\n",
159 irq, ret);
160 goto out_error_io;
161 }
162
163 expirelo = (timer_read(ioregs, 0, CV) / cycles_per_jiffy + 1)
164 * cycles_per_jiffy;
165
166 /* Enable clock and interrupts on RC compare */
167 timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_CLKEN));
168 timer_write(ioregs, 0, IER, TIMER_BIT(IER_CPCS));
169 /* Set cycles to first interrupt */
170 timer_write(ioregs, 0, RC, expirelo);
171
172 printk(KERN_INFO "timer: AT32AP system timer/counter at 0x%p irq %d\n",
173 ioregs, irq);
174
175 return 0;
176
177out_error_io:
178 iounmap(ioregs);
179out_error_clk:
180 clk_put(pclk);
181out_error:
182 return ret;
183}
184
185int avr32_hpt_start(void)
186{
187 timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_SWTRG));
188 return 0;
189}
190
191irqreturn_t timer_interrupt(int irq, void *dev_id)
192{
193 unsigned int sr = timer_read(ioregs, 0, SR);
194
195 if (sr & TIMER_BIT(SR_CPCS)) {
196 /* ack timer interrupt and try to set next interrupt */
197 avr32_timer_ack();
198
199 /*
200 * Call the generic timer interrupt handler
201 */
202 write_seqlock(&xtime_lock);
203 do_timer(1);
204 write_sequnlock(&xtime_lock);
205
206 /*
207 * In UP mode, we call local_timer_interrupt() to do profiling
208 * and process accounting.
209 *
210 * SMP is not supported yet.
211 */
212 local_timer_interrupt(irq, dev_id);
213
214 return IRQ_HANDLED;
215 }
216
217 return IRQ_NONE;
218}
diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
index 480760bde63f..0e64ddc45e37 100644
--- a/arch/avr32/mm/init.c
+++ b/arch/avr32/mm/init.c
@@ -34,9 +34,6 @@ struct page *empty_zero_page;
34 */ 34 */
35unsigned long mmu_context_cache = NO_CONTEXT; 35unsigned long mmu_context_cache = NO_CONTEXT;
36 36
37#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
38#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
39
40void show_mem(void) 37void show_mem(void)
41{ 38{
42 int total = 0, reserved = 0, cached = 0; 39 int total = 0, reserved = 0, cached = 0;
diff --git a/arch/avr32/oprofile/op_model_avr32.c b/arch/avr32/oprofile/op_model_avr32.c
index e2f876bfc86b..df42325c7f81 100644
--- a/arch/avr32/oprofile/op_model_avr32.c
+++ b/arch/avr32/oprofile/op_model_avr32.c
@@ -16,7 +16,6 @@
16#include <linux/sched.h> 16#include <linux/sched.h>
17#include <linux/types.h> 17#include <linux/types.h>
18 18
19#include <asm/intc.h>
20#include <asm/sysreg.h> 19#include <asm/sysreg.h>
21#include <asm/system.h> 20#include <asm/system.h>
22 21
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 47c6be84fc84..a87b89db08e9 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -706,7 +706,7 @@ config NVRAM
706 706
707config RTC 707config RTC
708 tristate "Enhanced Real Time Clock Support" 708 tristate "Enhanced Real Time Clock Support"
709 depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV && !ARM && !SUPERH && !S390 709 depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV && !ARM && !SUPERH && !S390 && !AVR32
710 ---help--- 710 ---help---
711 If you say Y here and create a character special file /dev/rtc with 711 If you say Y here and create a character special file /dev/rtc with
712 major number 10 and minor number 135 using mknod ("man mknod"), you 712 major number 10 and minor number 135 using mknod ("man mknod"), you
@@ -776,7 +776,7 @@ config SGI_IP27_RTC
776 776
777config GEN_RTC 777config GEN_RTC
778 tristate "Generic /dev/rtc emulation" 778 tristate "Generic /dev/rtc emulation"
779 depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH 779 depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH && !AVR32
780 ---help--- 780 ---help---
781 If you say Y here and create a character special file /dev/rtc with 781 If you say Y here and create a character special file /dev/rtc with
782 major number 10 and minor number 135 using mknod ("man mknod"), you 782 major number 10 and minor number 135 using mknod ("man mknod"), you
diff --git a/drivers/char/keyboard.c b/drivers/char/keyboard.c
index 4dbd3425e928..9769bf8279a6 100644
--- a/drivers/char/keyboard.c
+++ b/drivers/char/keyboard.c
@@ -1033,7 +1033,8 @@ DECLARE_TASKLET_DISABLED(keyboard_tasklet, kbd_bh, 0);
1033#if defined(CONFIG_X86) || defined(CONFIG_IA64) || defined(CONFIG_ALPHA) ||\ 1033#if defined(CONFIG_X86) || defined(CONFIG_IA64) || defined(CONFIG_ALPHA) ||\
1034 defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_SPARC) ||\ 1034 defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_SPARC) ||\
1035 defined(CONFIG_PARISC) || defined(CONFIG_SUPERH) ||\ 1035 defined(CONFIG_PARISC) || defined(CONFIG_SUPERH) ||\
1036 (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD) && !defined(CONFIG_ARCH_RPC)) 1036 (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD) && !defined(CONFIG_ARCH_RPC)) ||\
1037 defined(CONFIG_AVR32)
1037 1038
1038#define HW_RAW(dev) (test_bit(EV_MSC, dev->evbit) && test_bit(MSC_RAW, dev->mscbit) &&\ 1039#define HW_RAW(dev) (test_bit(EV_MSC, dev->evbit) && test_bit(MSC_RAW, dev->mscbit) &&\
1039 ((dev)->id.bustype == BUS_I8042) && ((dev)->id.vendor == 0x0001) && ((dev)->id.product == 0x0001)) 1040 ((dev)->id.bustype == BUS_I8042) && ((dev)->id.vendor == 0x0001) && ((dev)->id.product == 0x0001))
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index a52225470225..1525882190fd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -1,3 +1,4 @@
1obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
1obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o 2obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
2obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o 3obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
3obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o 4obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
new file mode 100644
index 000000000000..f450588e5858
--- /dev/null
+++ b/drivers/clocksource/tcb_clksrc.c
@@ -0,0 +1,302 @@
1#include <linux/init.h>
2#include <linux/clocksource.h>
3#include <linux/clockchips.h>
4#include <linux/interrupt.h>
5#include <linux/irq.h>
6
7#include <linux/clk.h>
8#include <linux/err.h>
9#include <linux/ioport.h>
10#include <linux/io.h>
11#include <linux/platform_device.h>
12#include <linux/atmel_tc.h>
13
14
15/*
16 * We're configured to use a specific TC block, one that's not hooked
17 * up to external hardware, to provide a time solution:
18 *
19 * - Two channels combine to create a free-running 32 bit counter
20 * with a base rate of 5+ MHz, packaged as a clocksource (with
21 * resolution better than 200 nsec).
22 *
23 * - The third channel may be used to provide a 16-bit clockevent
24 * source, used in either periodic or oneshot mode. This runs
25 * at 32 KiHZ, and can handle delays of up to two seconds.
26 *
27 * A boot clocksource and clockevent source are also currently needed,
28 * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
29 * this code can be used when init_timers() is called, well before most
30 * devices are set up. (Some low end AT91 parts, which can run uClinux,
31 * have only the timers in one TC block... they currently don't support
32 * the tclib code, because of that initialization issue.)
33 *
34 * REVISIT behavior during system suspend states... we should disable
35 * all clocks and save the power. Easily done for clockevent devices,
36 * but clocksources won't necessarily get the needed notifications.
37 * For deeper system sleep states, this will be mandatory...
38 */
39
40static void __iomem *tcaddr;
41
42static cycle_t tc_get_cycles(void)
43{
44 unsigned long flags;
45 u32 lower, upper;
46
47 raw_local_irq_save(flags);
48 do {
49 upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
50 lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
51 } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
52
53 raw_local_irq_restore(flags);
54 return (upper << 16) | lower;
55}
56
57static struct clocksource clksrc = {
58 .name = "tcb_clksrc",
59 .rating = 200,
60 .read = tc_get_cycles,
61 .mask = CLOCKSOURCE_MASK(32),
62 .shift = 18,
63 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
64};
65
66#ifdef CONFIG_GENERIC_CLOCKEVENTS
67
68struct tc_clkevt_device {
69 struct clock_event_device clkevt;
70 struct clk *clk;
71 void __iomem *regs;
72};
73
74static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
75{
76 return container_of(clkevt, struct tc_clkevt_device, clkevt);
77}
78
79/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
80 * because using one of the divided clocks would usually mean the
81 * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
82 *
83 * A divided clock could be good for high resolution timers, since
84 * 30.5 usec resolution can seem "low".
85 */
86static u32 timer_clock;
87
88static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
89{
90 struct tc_clkevt_device *tcd = to_tc_clkevt(d);
91 void __iomem *regs = tcd->regs;
92
93 if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
94 || tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
95 __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
96 __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
97 clk_disable(tcd->clk);
98 }
99
100 switch (m) {
101
102 /* By not making the gentime core emulate periodic mode on top
103 * of oneshot, we get lower overhead and improved accuracy.
104 */
105 case CLOCK_EVT_MODE_PERIODIC:
106 clk_enable(tcd->clk);
107
108 /* slow clock, count up to RC, then irq and restart */
109 __raw_writel(timer_clock
110 | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
111 regs + ATMEL_TC_REG(2, CMR));
112 __raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
113
114 /* Enable clock and interrupts on RC compare */
115 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
116
117 /* go go gadget! */
118 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
119 regs + ATMEL_TC_REG(2, CCR));
120 break;
121
122 case CLOCK_EVT_MODE_ONESHOT:
123 clk_enable(tcd->clk);
124
125 /* slow clock, count up to RC, then irq and stop */
126 __raw_writel(timer_clock | ATMEL_TC_CPCSTOP
127 | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
128 regs + ATMEL_TC_REG(2, CMR));
129 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
130
131 /* set_next_event() configures and starts the timer */
132 break;
133
134 default:
135 break;
136 }
137}
138
139static int tc_next_event(unsigned long delta, struct clock_event_device *d)
140{
141 __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
142
143 /* go go gadget! */
144 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
145 tcaddr + ATMEL_TC_REG(2, CCR));
146 return 0;
147}
148
149static struct tc_clkevt_device clkevt = {
150 .clkevt = {
151 .name = "tc_clkevt",
152 .features = CLOCK_EVT_FEAT_PERIODIC
153 | CLOCK_EVT_FEAT_ONESHOT,
154 .shift = 32,
155 /* Should be lower than at91rm9200's system timer */
156 .rating = 125,
157 .cpumask = CPU_MASK_CPU0,
158 .set_next_event = tc_next_event,
159 .set_mode = tc_mode,
160 },
161};
162
163static irqreturn_t ch2_irq(int irq, void *handle)
164{
165 struct tc_clkevt_device *dev = handle;
166 unsigned int sr;
167
168 sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
169 if (sr & ATMEL_TC_CPCS) {
170 dev->clkevt.event_handler(&dev->clkevt);
171 return IRQ_HANDLED;
172 }
173
174 return IRQ_NONE;
175}
176
177static struct irqaction tc_irqaction = {
178 .name = "tc_clkevt",
179 .flags = IRQF_TIMER | IRQF_DISABLED,
180 .handler = ch2_irq,
181};
182
183static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
184{
185 struct clk *t2_clk = tc->clk[2];
186 int irq = tc->irq[2];
187
188 clkevt.regs = tc->regs;
189 clkevt.clk = t2_clk;
190 tc_irqaction.dev_id = &clkevt;
191
192 timer_clock = clk32k_divisor_idx;
193
194 clkevt.clkevt.mult = div_sc(32768, NSEC_PER_SEC, clkevt.clkevt.shift);
195 clkevt.clkevt.max_delta_ns
196 = clockevent_delta2ns(0xffff, &clkevt.clkevt);
197 clkevt.clkevt.min_delta_ns = clockevent_delta2ns(1, &clkevt.clkevt) + 1;
198
199 setup_irq(irq, &tc_irqaction);
200
201 clockevents_register_device(&clkevt.clkevt);
202}
203
204#else /* !CONFIG_GENERIC_CLOCKEVENTS */
205
206static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
207{
208 /* NOTHING */
209}
210
211#endif
212
213static int __init tcb_clksrc_init(void)
214{
215 static char bootinfo[] __initdata
216 = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
217
218 struct platform_device *pdev;
219 struct atmel_tc *tc;
220 struct clk *t0_clk;
221 u32 rate, divided_rate = 0;
222 int best_divisor_idx = -1;
223 int clk32k_divisor_idx = -1;
224 int i;
225
226 tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name);
227 if (!tc) {
228 pr_debug("can't alloc TC for clocksource\n");
229 return -ENODEV;
230 }
231 tcaddr = tc->regs;
232 pdev = tc->pdev;
233
234 t0_clk = tc->clk[0];
235 clk_enable(t0_clk);
236
237 /* How fast will we be counting? Pick something over 5 MHz. */
238 rate = (u32) clk_get_rate(t0_clk);
239 for (i = 0; i < 5; i++) {
240 unsigned divisor = atmel_tc_divisors[i];
241 unsigned tmp;
242
243 /* remember 32 KiHz clock for later */
244 if (!divisor) {
245 clk32k_divisor_idx = i;
246 continue;
247 }
248
249 tmp = rate / divisor;
250 pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
251 if (best_divisor_idx > 0) {
252 if (tmp < 5 * 1000 * 1000)
253 continue;
254 }
255 divided_rate = tmp;
256 best_divisor_idx = i;
257 }
258
259 clksrc.mult = clocksource_hz2mult(divided_rate, clksrc.shift);
260
261 printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
262 divided_rate / 1000000,
263 ((divided_rate + 500000) % 1000000) / 1000);
264
265 /* tclib will give us three clocks no matter what the
266 * underlying platform supports.
267 */
268 clk_enable(tc->clk[1]);
269
270 /* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
271 __raw_writel(best_divisor_idx /* likely divide-by-8 */
272 | ATMEL_TC_WAVE
273 | ATMEL_TC_WAVESEL_UP /* free-run */
274 | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
275 | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
276 tcaddr + ATMEL_TC_REG(0, CMR));
277 __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
278 __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
279 __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
280 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
281
282 /* channel 1: waveform mode, input TIOA0 */
283 __raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */
284 | ATMEL_TC_WAVE
285 | ATMEL_TC_WAVESEL_UP, /* free-run */
286 tcaddr + ATMEL_TC_REG(1, CMR));
287 __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
288 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
289
290 /* chain channel 0 to channel 1, then reset all the timers */
291 __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
292 __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
293
294 /* and away we go! */
295 clocksource_register(&clksrc);
296
297 /* channel 2: periodic and oneshot timer support */
298 setup_clkevents(tc, clk32k_divisor_idx);
299
300 return 0;
301}
302arch_initcall(tcb_clksrc_init);
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 962817e49fba..bb94ce78a6d0 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -22,6 +22,39 @@ config ATMEL_PWM
22 purposes including software controlled power-efficent backlights 22 purposes including software controlled power-efficent backlights
23 on LCD displays, motor control, and waveform generation. 23 on LCD displays, motor control, and waveform generation.
24 24
25config ATMEL_TCLIB
26 bool "Atmel AT32/AT91 Timer/Counter Library"
27 depends on (AVR32 || ARCH_AT91)
28 help
29 Select this if you want a library to allocate the Timer/Counter
30 blocks found on many Atmel processors. This facilitates using
31 these blocks by different drivers despite processor differences.
32
33config ATMEL_TCB_CLKSRC
34 bool "TC Block Clocksource"
35 depends on ATMEL_TCLIB && GENERIC_TIME
36 default y
37 help
38 Select this to get a high precision clocksource based on a
39 TC block with a 5+ MHz base clock rate. Two timer channels
40 are combined to make a single 32-bit timer.
41
42 When GENERIC_CLOCKEVENTS is defined, the third timer channel
43 may be used as a clock event device supporting oneshot mode
44 (delays of up to two seconds) based on the 32 KiHz clock.
45
46config ATMEL_TCB_CLKSRC_BLOCK
47 int
48 depends on ATMEL_TCB_CLKSRC
49 prompt "TC Block" if ARCH_AT91RM9200 || ARCH_AT91SAM9260 || CPU_AT32AP700X
50 default 0
51 range 0 1
52 help
53 Some chips provide more than one TC block, so you have the
54 choice of which one to use for the clock framework. The other
55 TC can be used for other purposes, such as PWM generation and
56 interval timing.
57
25config IBM_ASM 58config IBM_ASM
26 tristate "Device driver for IBM RSA service processor" 59 tristate "Device driver for IBM RSA service processor"
27 depends on X86 && PCI && INPUT && EXPERIMENTAL 60 depends on X86 && PCI && INPUT && EXPERIMENTAL
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index bbc69fdd1b9d..4581b2533111 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ACER_WMI) += acer-wmi.o
10obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o 10obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o
11obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o 11obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
12obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o 12obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
13obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
13obj-$(CONFIG_TC1100_WMI) += tc1100-wmi.o 14obj-$(CONFIG_TC1100_WMI) += tc1100-wmi.o
14obj-$(CONFIG_LKDTM) += lkdtm.o 15obj-$(CONFIG_LKDTM) += lkdtm.o
15obj-$(CONFIG_TIFM_CORE) += tifm_core.o 16obj-$(CONFIG_TIFM_CORE) += tifm_core.o
diff --git a/drivers/misc/atmel_tclib.c b/drivers/misc/atmel_tclib.c
new file mode 100644
index 000000000000..05dc8a31f280
--- /dev/null
+++ b/drivers/misc/atmel_tclib.c
@@ -0,0 +1,161 @@
1#include <linux/atmel_tc.h>
2#include <linux/clk.h>
3#include <linux/err.h>
4#include <linux/init.h>
5#include <linux/io.h>
6#include <linux/ioport.h>
7#include <linux/kernel.h>
8#include <linux/platform_device.h>
9
10/* Number of bytes to reserve for the iomem resource */
11#define ATMEL_TC_IOMEM_SIZE 256
12
13
14/*
15 * This is a thin library to solve the problem of how to portably allocate
16 * one of the TC blocks. For simplicity, it doesn't currently expect to
17 * share individual timers between different drivers.
18 */
19
20#if defined(CONFIG_AVR32)
21/* AVR32 has these divide PBB */
22const u8 atmel_tc_divisors[5] = { 0, 4, 8, 16, 32, };
23EXPORT_SYMBOL(atmel_tc_divisors);
24
25#elif defined(CONFIG_ARCH_AT91)
26/* AT91 has these divide MCK */
27const u8 atmel_tc_divisors[5] = { 2, 8, 32, 128, 0, };
28EXPORT_SYMBOL(atmel_tc_divisors);
29
30#endif
31
32static DEFINE_SPINLOCK(tc_list_lock);
33static LIST_HEAD(tc_list);
34
35/**
36 * atmel_tc_alloc - allocate a specified TC block
37 * @block: which block to allocate
38 * @name: name to be associated with the iomem resource
39 *
40 * Caller allocates a block. If it is available, a pointer to a
41 * pre-initialized struct atmel_tc is returned. The caller can access
42 * the registers directly through the "regs" field.
43 */
44struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name)
45{
46 struct atmel_tc *tc;
47 struct platform_device *pdev = NULL;
48 struct resource *r;
49
50 spin_lock(&tc_list_lock);
51 list_for_each_entry(tc, &tc_list, node) {
52 if (tc->pdev->id == block) {
53 pdev = tc->pdev;
54 break;
55 }
56 }
57
58 if (!pdev || tc->iomem)
59 goto fail;
60
61 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
62 r = request_mem_region(r->start, ATMEL_TC_IOMEM_SIZE, name);
63 if (!r)
64 goto fail;
65
66 tc->regs = ioremap(r->start, ATMEL_TC_IOMEM_SIZE);
67 if (!tc->regs)
68 goto fail_ioremap;
69
70 tc->iomem = r;
71
72out:
73 spin_unlock(&tc_list_lock);
74 return tc;
75
76fail_ioremap:
77 release_resource(r);
78fail:
79 tc = NULL;
80 goto out;
81}
82EXPORT_SYMBOL_GPL(atmel_tc_alloc);
83
84/**
85 * atmel_tc_free - release a specified TC block
86 * @tc: Timer/counter block that was returned by atmel_tc_alloc()
87 *
88 * This reverses the effect of atmel_tc_alloc(), unmapping the I/O
89 * registers, invalidating the resource returned by that routine and
90 * making the TC available to other drivers.
91 */
92void atmel_tc_free(struct atmel_tc *tc)
93{
94 spin_lock(&tc_list_lock);
95 if (tc->regs) {
96 iounmap(tc->regs);
97 release_resource(tc->iomem);
98 tc->regs = NULL;
99 tc->iomem = NULL;
100 }
101 spin_unlock(&tc_list_lock);
102}
103EXPORT_SYMBOL_GPL(atmel_tc_free);
104
105static int __init tc_probe(struct platform_device *pdev)
106{
107 struct atmel_tc *tc;
108 struct clk *clk;
109 int irq;
110
111 if (!platform_get_resource(pdev, IORESOURCE_MEM, 0))
112 return -EINVAL;
113
114 irq = platform_get_irq(pdev, 0);
115 if (irq < 0)
116 return -EINVAL;
117
118 tc = kzalloc(sizeof(struct atmel_tc), GFP_KERNEL);
119 if (!tc)
120 return -ENOMEM;
121
122 tc->pdev = pdev;
123
124 clk = clk_get(&pdev->dev, "t0_clk");
125 if (IS_ERR(clk)) {
126 kfree(tc);
127 return -EINVAL;
128 }
129
130 tc->clk[0] = clk;
131 tc->clk[1] = clk_get(&pdev->dev, "t1_clk");
132 if (IS_ERR(tc->clk[1]))
133 tc->clk[1] = clk;
134 tc->clk[2] = clk_get(&pdev->dev, "t2_clk");
135 if (IS_ERR(tc->clk[2]))
136 tc->clk[2] = clk;
137
138 tc->irq[0] = irq;
139 tc->irq[1] = platform_get_irq(pdev, 1);
140 if (tc->irq[1] < 0)
141 tc->irq[1] = irq;
142 tc->irq[2] = platform_get_irq(pdev, 2);
143 if (tc->irq[2] < 0)
144 tc->irq[2] = irq;
145
146 spin_lock(&tc_list_lock);
147 list_add_tail(&tc->node, &tc_list);
148 spin_unlock(&tc_list_lock);
149
150 return 0;
151}
152
153static struct platform_driver tc_driver = {
154 .driver.name = "atmel_tcb",
155};
156
157static int __init tc_init(void)
158{
159 return platform_driver_probe(&tc_driver, tc_probe);
160}
161arch_initcall(tc_init);
diff --git a/drivers/parport/Kconfig b/drivers/parport/Kconfig
index b7bcdcc5c724..209b4a464bcf 100644
--- a/drivers/parport/Kconfig
+++ b/drivers/parport/Kconfig
@@ -36,7 +36,7 @@ if PARPORT
36config PARPORT_PC 36config PARPORT_PC
37 tristate "PC-style hardware" 37 tristate "PC-style hardware"
38 depends on (!SPARC64 || PCI) && !SPARC32 && !M32R && !FRV && \ 38 depends on (!SPARC64 || PCI) && !SPARC32 && !M32R && !FRV && \
39 (!M68K || ISA) && !MN10300 39 (!M68K || ISA) && !MN10300 && !AVR32
40 ---help--- 40 ---help---
41 You should say Y here if you have a PC-style parallel port. All 41 You should say Y here if you have a PC-style parallel port. All
42 IBM PC compatible computers and some Alphas have PC-style 42 IBM PC compatible computers and some Alphas have PC-style
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 6f45dd669b33..d681bb27fa58 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -118,10 +118,10 @@ config USB_AMD5536UDC
118config USB_GADGET_ATMEL_USBA 118config USB_GADGET_ATMEL_USBA
119 boolean "Atmel USBA" 119 boolean "Atmel USBA"
120 select USB_GADGET_DUALSPEED 120 select USB_GADGET_DUALSPEED
121 depends on AVR32 121 depends on AVR32 || ARCH_AT91CAP9
122 help 122 help
123 USBA is the integrated high-speed USB Device controller on 123 USBA is the integrated high-speed USB Device controller on
124 the AT32AP700x processors from Atmel. 124 the AT32AP700x and AT91CAP9 processors from Atmel.
125 125
126config USB_ATMEL_USBA 126config USB_ATMEL_USBA
127 tristate 127 tristate
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index b0db4c31d018..e756023362c2 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -18,6 +18,7 @@
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/usb/ch9.h> 19#include <linux/usb/ch9.h>
20#include <linux/usb/gadget.h> 20#include <linux/usb/gadget.h>
21#include <linux/usb/atmel_usba_udc.h>
21#include <linux/delay.h> 22#include <linux/delay.h>
22 23
23#include <asm/gpio.h> 24#include <asm/gpio.h>
@@ -27,6 +28,7 @@
27 28
28 29
29static struct usba_udc the_udc; 30static struct usba_udc the_udc;
31static struct usba_ep *usba_ep;
30 32
31#ifdef CONFIG_USB_GADGET_DEBUG_FS 33#ifdef CONFIG_USB_GADGET_DEBUG_FS
32#include <linux/debugfs.h> 34#include <linux/debugfs.h>
@@ -324,53 +326,28 @@ static int vbus_is_present(struct usba_udc *udc)
324 return 1; 326 return 1;
325} 327}
326 328
327static void copy_to_fifo(void __iomem *fifo, const void *buf, int len) 329#if defined(CONFIG_AVR32)
330
331static void toggle_bias(int is_on)
328{ 332{
329 unsigned long tmp;
330
331 DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
332 for (; len > 0; len -= 4, buf += 4, fifo += 4) {
333 tmp = *(unsigned long *)buf;
334 if (len >= 4) {
335 DBG(DBG_FIFO, " -> %08lx\n", tmp);
336 __raw_writel(tmp, fifo);
337 } else {
338 do {
339 DBG(DBG_FIFO, " -> %02lx\n", tmp >> 24);
340 __raw_writeb(tmp >> 24, fifo);
341 fifo++;
342 tmp <<= 8;
343 } while (--len);
344 break;
345 }
346 }
347} 333}
348 334
349static void copy_from_fifo(void *buf, void __iomem *fifo, int len) 335#elif defined(CONFIG_ARCH_AT91)
336
337#include <asm/arch/at91_pmc.h>
338
339static void toggle_bias(int is_on)
350{ 340{
351 union { 341 unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
352 unsigned long *w; 342
353 unsigned char *b; 343 if (is_on)
354 } p; 344 at91_sys_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
355 unsigned long tmp; 345 else
356 346 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
357 DBG(DBG_FIFO, "copy from FIFO (len %d):\n", len);
358 for (p.w = buf; len > 0; len -= 4, p.w++, fifo += 4) {
359 if (len >= 4) {
360 tmp = __raw_readl(fifo);
361 *p.w = tmp;
362 DBG(DBG_FIFO, " -> %08lx\n", tmp);
363 } else {
364 do {
365 tmp = __raw_readb(fifo);
366 *p.b = tmp;
367 DBG(DBG_FIFO, " -> %02lx\n", tmp);
368 fifo++, p.b++;
369 } while (--len);
370 }
371 }
372} 347}
373 348
349#endif /* CONFIG_ARCH_AT91 */
350
374static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req) 351static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
375{ 352{
376 unsigned int transaction_len; 353 unsigned int transaction_len;
@@ -387,7 +364,7 @@ static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
387 ep->ep.name, req, transaction_len, 364 ep->ep.name, req, transaction_len,
388 req->last_transaction ? ", done" : ""); 365 req->last_transaction ? ", done" : "");
389 366
390 copy_to_fifo(ep->fifo, req->req.buf + req->req.actual, transaction_len); 367 memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
391 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); 368 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
392 req->req.actual += transaction_len; 369 req->req.actual += transaction_len;
393} 370}
@@ -476,7 +453,7 @@ static void receive_data(struct usba_ep *ep)
476 bytecount = req->req.length - req->req.actual; 453 bytecount = req->req.length - req->req.actual;
477 } 454 }
478 455
479 copy_from_fifo(req->req.buf + req->req.actual, 456 memcpy_fromio(req->req.buf + req->req.actual,
480 ep->fifo, bytecount); 457 ep->fifo, bytecount);
481 req->req.actual += bytecount; 458 req->req.actual += bytecount;
482 459
@@ -1029,33 +1006,6 @@ static const struct usb_gadget_ops usba_udc_ops = {
1029 .set_selfpowered = usba_udc_set_selfpowered, 1006 .set_selfpowered = usba_udc_set_selfpowered,
1030}; 1007};
1031 1008
1032#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1033{ \
1034 .ep = { \
1035 .ops = &usba_ep_ops, \
1036 .name = nam, \
1037 .maxpacket = maxpkt, \
1038 }, \
1039 .udc = &the_udc, \
1040 .queue = LIST_HEAD_INIT(usba_ep[idx].queue), \
1041 .fifo_size = maxpkt, \
1042 .nr_banks = maxbk, \
1043 .index = idx, \
1044 .can_dma = dma, \
1045 .can_isoc = isoc, \
1046}
1047
1048static struct usba_ep usba_ep[] = {
1049 EP("ep0", 0, 64, 1, 0, 0),
1050 EP("ep1in-bulk", 1, 512, 2, 1, 1),
1051 EP("ep2out-bulk", 2, 512, 2, 1, 1),
1052 EP("ep3in-int", 3, 64, 3, 1, 0),
1053 EP("ep4out-int", 4, 64, 3, 1, 0),
1054 EP("ep5in-iso", 5, 1024, 3, 1, 1),
1055 EP("ep6out-iso", 6, 1024, 3, 1, 1),
1056};
1057#undef EP
1058
1059static struct usb_endpoint_descriptor usba_ep0_desc = { 1009static struct usb_endpoint_descriptor usba_ep0_desc = {
1060 .bLength = USB_DT_ENDPOINT_SIZE, 1010 .bLength = USB_DT_ENDPOINT_SIZE,
1061 .bDescriptorType = USB_DT_ENDPOINT, 1011 .bDescriptorType = USB_DT_ENDPOINT,
@@ -1074,7 +1024,6 @@ static void nop_release(struct device *dev)
1074static struct usba_udc the_udc = { 1024static struct usba_udc the_udc = {
1075 .gadget = { 1025 .gadget = {
1076 .ops = &usba_udc_ops, 1026 .ops = &usba_udc_ops,
1077 .ep0 = &usba_ep[0].ep,
1078 .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list), 1027 .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
1079 .is_dualspeed = 1, 1028 .is_dualspeed = 1,
1080 .name = "atmel_usba_udc", 1029 .name = "atmel_usba_udc",
@@ -1231,7 +1180,7 @@ static int do_test_mode(struct usba_udc *udc)
1231 } else { 1180 } else {
1232 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE); 1181 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
1233 usba_writel(udc, TST, USBA_TST_PKT_MODE); 1182 usba_writel(udc, TST, USBA_TST_PKT_MODE);
1234 copy_to_fifo(ep->fifo, test_packet_buffer, 1183 memcpy_toio(ep->fifo, test_packet_buffer,
1235 sizeof(test_packet_buffer)); 1184 sizeof(test_packet_buffer));
1236 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); 1185 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
1237 dev_info(dev, "Entering Test_Packet mode...\n"); 1186 dev_info(dev, "Entering Test_Packet mode...\n");
@@ -1530,13 +1479,13 @@ restart:
1530 DBG(DBG_HW, "Packet length: %u\n", pkt_len); 1479 DBG(DBG_HW, "Packet length: %u\n", pkt_len);
1531 if (pkt_len != sizeof(crq)) { 1480 if (pkt_len != sizeof(crq)) {
1532 pr_warning("udc: Invalid packet length %u " 1481 pr_warning("udc: Invalid packet length %u "
1533 "(expected %lu)\n", pkt_len, sizeof(crq)); 1482 "(expected %zu)\n", pkt_len, sizeof(crq));
1534 set_protocol_stall(udc, ep); 1483 set_protocol_stall(udc, ep);
1535 return; 1484 return;
1536 } 1485 }
1537 1486
1538 DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo); 1487 DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
1539 copy_from_fifo(crq.data, ep->fifo, sizeof(crq)); 1488 memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
1540 1489
1541 /* Free up one bank in the FIFO so that we can 1490 /* Free up one bank in the FIFO so that we can
1542 * generate or receive a reply right away. */ 1491 * generate or receive a reply right away. */
@@ -1688,6 +1637,7 @@ static irqreturn_t usba_udc_irq(int irq, void *devid)
1688 DBG(DBG_INT, "irq, status=%#08x\n", status); 1637 DBG(DBG_INT, "irq, status=%#08x\n", status);
1689 1638
1690 if (status & USBA_DET_SUSPEND) { 1639 if (status & USBA_DET_SUSPEND) {
1640 toggle_bias(0);
1691 usba_writel(udc, INT_CLR, USBA_DET_SUSPEND); 1641 usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
1692 DBG(DBG_BUS, "Suspend detected\n"); 1642 DBG(DBG_BUS, "Suspend detected\n");
1693 if (udc->gadget.speed != USB_SPEED_UNKNOWN 1643 if (udc->gadget.speed != USB_SPEED_UNKNOWN
@@ -1699,6 +1649,7 @@ static irqreturn_t usba_udc_irq(int irq, void *devid)
1699 } 1649 }
1700 1650
1701 if (status & USBA_WAKE_UP) { 1651 if (status & USBA_WAKE_UP) {
1652 toggle_bias(1);
1702 usba_writel(udc, INT_CLR, USBA_WAKE_UP); 1653 usba_writel(udc, INT_CLR, USBA_WAKE_UP);
1703 DBG(DBG_BUS, "Wake Up CPU detected\n"); 1654 DBG(DBG_BUS, "Wake Up CPU detected\n");
1704 } 1655 }
@@ -1792,12 +1743,14 @@ static irqreturn_t usba_vbus_irq(int irq, void *devid)
1792 vbus = gpio_get_value(udc->vbus_pin); 1743 vbus = gpio_get_value(udc->vbus_pin);
1793 if (vbus != udc->vbus_prev) { 1744 if (vbus != udc->vbus_prev) {
1794 if (vbus) { 1745 if (vbus) {
1795 usba_writel(udc, CTRL, USBA_EN_USBA); 1746 toggle_bias(1);
1747 usba_writel(udc, CTRL, USBA_ENABLE_MASK);
1796 usba_writel(udc, INT_ENB, USBA_END_OF_RESET); 1748 usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
1797 } else { 1749 } else {
1798 udc->gadget.speed = USB_SPEED_UNKNOWN; 1750 udc->gadget.speed = USB_SPEED_UNKNOWN;
1799 reset_all_endpoints(udc); 1751 reset_all_endpoints(udc);
1800 usba_writel(udc, CTRL, 0); 1752 toggle_bias(0);
1753 usba_writel(udc, CTRL, USBA_DISABLE_MASK);
1801 spin_unlock(&udc->lock); 1754 spin_unlock(&udc->lock);
1802 udc->driver->disconnect(&udc->gadget); 1755 udc->driver->disconnect(&udc->gadget);
1803 spin_lock(&udc->lock); 1756 spin_lock(&udc->lock);
@@ -1850,7 +1803,8 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1850 /* If Vbus is present, enable the controller and wait for reset */ 1803 /* If Vbus is present, enable the controller and wait for reset */
1851 spin_lock_irqsave(&udc->lock, flags); 1804 spin_lock_irqsave(&udc->lock, flags);
1852 if (vbus_is_present(udc) && udc->vbus_prev == 0) { 1805 if (vbus_is_present(udc) && udc->vbus_prev == 0) {
1853 usba_writel(udc, CTRL, USBA_EN_USBA); 1806 toggle_bias(1);
1807 usba_writel(udc, CTRL, USBA_ENABLE_MASK);
1854 usba_writel(udc, INT_ENB, USBA_END_OF_RESET); 1808 usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
1855 } 1809 }
1856 spin_unlock_irqrestore(&udc->lock, flags); 1810 spin_unlock_irqrestore(&udc->lock, flags);
@@ -1883,7 +1837,8 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1883 spin_unlock_irqrestore(&udc->lock, flags); 1837 spin_unlock_irqrestore(&udc->lock, flags);
1884 1838
1885 /* This will also disable the DP pullup */ 1839 /* This will also disable the DP pullup */
1886 usba_writel(udc, CTRL, 0); 1840 toggle_bias(0);
1841 usba_writel(udc, CTRL, USBA_DISABLE_MASK);
1887 1842
1888 driver->unbind(&udc->gadget); 1843 driver->unbind(&udc->gadget);
1889 udc->gadget.dev.driver = NULL; 1844 udc->gadget.dev.driver = NULL;
@@ -1908,7 +1863,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
1908 1863
1909 regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID); 1864 regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
1910 fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID); 1865 fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
1911 if (!regs || !fifo) 1866 if (!regs || !fifo || !pdata)
1912 return -ENXIO; 1867 return -ENXIO;
1913 1868
1914 irq = platform_get_irq(pdev, 0); 1869 irq = platform_get_irq(pdev, 0);
@@ -1953,19 +1908,48 @@ static int __init usba_udc_probe(struct platform_device *pdev)
1953 1908
1954 /* Make sure we start from a clean slate */ 1909 /* Make sure we start from a clean slate */
1955 clk_enable(pclk); 1910 clk_enable(pclk);
1956 usba_writel(udc, CTRL, 0); 1911 toggle_bias(0);
1912 usba_writel(udc, CTRL, USBA_DISABLE_MASK);
1957 clk_disable(pclk); 1913 clk_disable(pclk);
1958 1914
1915 usba_ep = kmalloc(sizeof(struct usba_ep) * pdata->num_ep,
1916 GFP_KERNEL);
1917 if (!usba_ep)
1918 goto err_alloc_ep;
1919
1920 the_udc.gadget.ep0 = &usba_ep[0].ep;
1921
1959 INIT_LIST_HEAD(&usba_ep[0].ep.ep_list); 1922 INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
1960 usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0); 1923 usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
1961 usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0); 1924 usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
1962 usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0); 1925 usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
1963 for (i = 1; i < ARRAY_SIZE(usba_ep); i++) { 1926 usba_ep[0].ep.ops = &usba_ep_ops;
1927 usba_ep[0].ep.name = pdata->ep[0].name;
1928 usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
1929 usba_ep[0].udc = &the_udc;
1930 INIT_LIST_HEAD(&usba_ep[0].queue);
1931 usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
1932 usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
1933 usba_ep[0].index = pdata->ep[0].index;
1934 usba_ep[0].can_dma = pdata->ep[0].can_dma;
1935 usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
1936
1937 for (i = 1; i < pdata->num_ep; i++) {
1964 struct usba_ep *ep = &usba_ep[i]; 1938 struct usba_ep *ep = &usba_ep[i];
1965 1939
1966 ep->ep_regs = udc->regs + USBA_EPT_BASE(i); 1940 ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
1967 ep->dma_regs = udc->regs + USBA_DMA_BASE(i); 1941 ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
1968 ep->fifo = udc->fifo + USBA_FIFO_BASE(i); 1942 ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
1943 ep->ep.ops = &usba_ep_ops;
1944 ep->ep.name = pdata->ep[i].name;
1945 ep->ep.maxpacket = pdata->ep[i].fifo_size;
1946 ep->udc = &the_udc;
1947 INIT_LIST_HEAD(&ep->queue);
1948 ep->fifo_size = pdata->ep[i].fifo_size;
1949 ep->nr_banks = pdata->ep[i].nr_banks;
1950 ep->index = pdata->ep[i].index;
1951 ep->can_dma = pdata->ep[i].can_dma;
1952 ep->can_isoc = pdata->ep[i].can_isoc;
1969 1953
1970 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 1954 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1971 } 1955 }
@@ -1984,7 +1968,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
1984 goto err_device_add; 1968 goto err_device_add;
1985 } 1969 }
1986 1970
1987 if (pdata && pdata->vbus_pin != GPIO_PIN_NONE) { 1971 if (pdata->vbus_pin >= 0) {
1988 if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) { 1972 if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
1989 udc->vbus_pin = pdata->vbus_pin; 1973 udc->vbus_pin = pdata->vbus_pin;
1990 1974
@@ -2004,7 +1988,7 @@ static int __init usba_udc_probe(struct platform_device *pdev)
2004 } 1988 }
2005 1989
2006 usba_init_debugfs(udc); 1990 usba_init_debugfs(udc);
2007 for (i = 1; i < ARRAY_SIZE(usba_ep); i++) 1991 for (i = 1; i < pdata->num_ep; i++)
2008 usba_ep_init_debugfs(udc, &usba_ep[i]); 1992 usba_ep_init_debugfs(udc, &usba_ep[i]);
2009 1993
2010 return 0; 1994 return 0;
@@ -2012,6 +1996,8 @@ static int __init usba_udc_probe(struct platform_device *pdev)
2012err_device_add: 1996err_device_add:
2013 free_irq(irq, udc); 1997 free_irq(irq, udc);
2014err_request_irq: 1998err_request_irq:
1999 kfree(usba_ep);
2000err_alloc_ep:
2015 iounmap(udc->fifo); 2001 iounmap(udc->fifo);
2016err_map_fifo: 2002err_map_fifo:
2017 iounmap(udc->regs); 2003 iounmap(udc->regs);
@@ -2029,10 +2015,11 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
2029{ 2015{
2030 struct usba_udc *udc; 2016 struct usba_udc *udc;
2031 int i; 2017 int i;
2018 struct usba_platform_data *pdata = pdev->dev.platform_data;
2032 2019
2033 udc = platform_get_drvdata(pdev); 2020 udc = platform_get_drvdata(pdev);
2034 2021
2035 for (i = 1; i < ARRAY_SIZE(usba_ep); i++) 2022 for (i = 1; i < pdata->num_ep; i++)
2036 usba_ep_cleanup_debugfs(&usba_ep[i]); 2023 usba_ep_cleanup_debugfs(&usba_ep[i]);
2037 usba_cleanup_debugfs(udc); 2024 usba_cleanup_debugfs(udc);
2038 2025
@@ -2040,6 +2027,7 @@ static int __exit usba_udc_remove(struct platform_device *pdev)
2040 gpio_free(udc->vbus_pin); 2027 gpio_free(udc->vbus_pin);
2041 2028
2042 free_irq(udc->irq, udc); 2029 free_irq(udc->irq, udc);
2030 kfree(usba_ep);
2043 iounmap(udc->fifo); 2031 iounmap(udc->fifo);
2044 iounmap(udc->regs); 2032 iounmap(udc->regs);
2045 clk_put(udc->hclk); 2033 clk_put(udc->hclk);
diff --git a/drivers/usb/gadget/atmel_usba_udc.h b/drivers/usb/gadget/atmel_usba_udc.h
index 08bf6f9aaf7e..f7baea307f0d 100644
--- a/drivers/usb/gadget/atmel_usba_udc.h
+++ b/drivers/usb/gadget/atmel_usba_udc.h
@@ -41,6 +41,15 @@
41#define USBA_EN_USBA (1 << 8) 41#define USBA_EN_USBA (1 << 8)
42#define USBA_DETACH (1 << 9) 42#define USBA_DETACH (1 << 9)
43#define USBA_REMOTE_WAKE_UP (1 << 10) 43#define USBA_REMOTE_WAKE_UP (1 << 10)
44#define USBA_PULLD_DIS (1 << 11)
45
46#if defined(CONFIG_AVR32)
47#define USBA_ENABLE_MASK USBA_EN_USBA
48#define USBA_DISABLE_MASK 0
49#elif defined(CONFIG_ARCH_AT91)
50#define USBA_ENABLE_MASK (USBA_EN_USBA | USBA_PULLD_DIS)
51#define USBA_DISABLE_MASK USBA_DETACH
52#endif /* CONFIG_ARCH_AT91 */
44 53
45/* Bitfields in FNUM */ 54/* Bitfields in FNUM */
46#define USBA_MICRO_FRAME_NUM_OFFSET 0 55#define USBA_MICRO_FRAME_NUM_OFFSET 0
diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h
index 7597b0bd2f01..a4e2d28bfb58 100644
--- a/include/asm-avr32/arch-at32ap/board.h
+++ b/include/asm-avr32/arch-at32ap/board.h
@@ -38,9 +38,7 @@ struct platform_device *
38at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, 38at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
39 unsigned long fbmem_start, unsigned long fbmem_len); 39 unsigned long fbmem_start, unsigned long fbmem_len);
40 40
41struct usba_platform_data { 41struct usba_platform_data;
42 int vbus_pin;
43};
44struct platform_device * 42struct platform_device *
45at32_add_device_usba(unsigned int id, struct usba_platform_data *data); 43at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
46 44
@@ -68,7 +66,10 @@ struct platform_device *at32_add_device_pwm(u32 mask);
68struct platform_device * 66struct platform_device *
69at32_add_device_ssc(unsigned int id, unsigned int flags); 67at32_add_device_ssc(unsigned int id, unsigned int flags);
70 68
71struct platform_device *at32_add_device_twi(unsigned int id); 69struct i2c_board_info;
70struct platform_device *at32_add_device_twi(unsigned int id,
71 struct i2c_board_info *b,
72 unsigned int n);
72struct platform_device *at32_add_device_mci(unsigned int id); 73struct platform_device *at32_add_device_mci(unsigned int id);
73struct platform_device *at32_add_device_ac97c(unsigned int id); 74struct platform_device *at32_add_device_ac97c(unsigned int id);
74struct platform_device *at32_add_device_abdac(unsigned int id); 75struct platform_device *at32_add_device_abdac(unsigned int id);
diff --git a/include/asm-avr32/arch-at32ap/pm.h b/include/asm-avr32/arch-at32ap/pm.h
new file mode 100644
index 000000000000..356e43064903
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap/pm.h
@@ -0,0 +1,48 @@
1/*
2 * AVR32 AP Power Management.
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_AVR32_ARCH_PM_H
11#define __ASM_AVR32_ARCH_PM_H
12
13/* Possible arguments to the "sleep" instruction */
14#define CPU_SLEEP_IDLE 0
15#define CPU_SLEEP_FROZEN 1
16#define CPU_SLEEP_STANDBY 2
17#define CPU_SLEEP_STOP 3
18#define CPU_SLEEP_STATIC 5
19
20#ifndef __ASSEMBLY__
21extern void cpu_enter_idle(void);
22
23extern bool disable_idle_sleep;
24
25static inline void cpu_disable_idle_sleep(void)
26{
27 disable_idle_sleep = true;
28}
29
30static inline void cpu_enable_idle_sleep(void)
31{
32 disable_idle_sleep = false;
33}
34
35static inline void cpu_idle_sleep(void)
36{
37 /*
38 * If we're using the COUNT and COMPARE registers for
39 * timekeeping, we can't use the IDLE state.
40 */
41 if (disable_idle_sleep)
42 cpu_relax();
43 else
44 cpu_enter_idle();
45}
46#endif
47
48#endif /* __ASM_AVR32_ARCH_PM_H */
diff --git a/include/asm-avr32/arch-at32ap/time.h b/include/asm-avr32/arch-at32ap/time.h
deleted file mode 100644
index cc8a43418a4d..000000000000
--- a/include/asm-avr32/arch-at32ap/time.h
+++ /dev/null
@@ -1,112 +0,0 @@
1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H
10#define _ASM_AVR32_ARCH_AT32AP_TIME_H
11
12#include <linux/platform_device.h>
13
14extern struct irqaction timer_irqaction;
15extern struct platform_device at32_systc0_device;
16extern void local_timer_interrupt(int irq, void *dev_id);
17
18#define TIMER_BCR 0x000000c0
19#define TIMER_BCR_SYNC 0
20#define TIMER_BMR 0x000000c4
21#define TIMER_BMR_TC0XC0S 0
22#define TIMER_BMR_TC1XC1S 2
23#define TIMER_BMR_TC2XC2S 4
24#define TIMER_CCR 0x00000000
25#define TIMER_CCR_CLKDIS 1
26#define TIMER_CCR_CLKEN 0
27#define TIMER_CCR_SWTRG 2
28#define TIMER_CMR 0x00000004
29#define TIMER_CMR_ABETRG 10
30#define TIMER_CMR_ACPA 16
31#define TIMER_CMR_ACPC 18
32#define TIMER_CMR_AEEVT 20
33#define TIMER_CMR_ASWTRG 22
34#define TIMER_CMR_BCPB 24
35#define TIMER_CMR_BCPC 26
36#define TIMER_CMR_BEEVT 28
37#define TIMER_CMR_BSWTRG 30
38#define TIMER_CMR_BURST 4
39#define TIMER_CMR_CLKI 3
40#define TIMER_CMR_CPCDIS 7
41#define TIMER_CMR_CPCSTOP 6
42#define TIMER_CMR_CPCTRG 14
43#define TIMER_CMR_EEVT 10
44#define TIMER_CMR_EEVTEDG 8
45#define TIMER_CMR_ENETRG 12
46#define TIMER_CMR_ETRGEDG 8
47#define TIMER_CMR_LDBDIS 7
48#define TIMER_CMR_LDBSTOP 6
49#define TIMER_CMR_LDRA 16
50#define TIMER_CMR_LDRB 18
51#define TIMER_CMR_TCCLKS 0
52#define TIMER_CMR_WAVE 15
53#define TIMER_CMR_WAVSEL 13
54#define TIMER_CV 0x00000010
55#define TIMER_CV_CV 0
56#define TIMER_IDR 0x00000028
57#define TIMER_IDR_COVFS 0
58#define TIMER_IDR_CPAS 2
59#define TIMER_IDR_CPBS 3
60#define TIMER_IDR_CPCS 4
61#define TIMER_IDR_ETRGS 7
62#define TIMER_IDR_LDRAS 5
63#define TIMER_IDR_LDRBS 6
64#define TIMER_IDR_LOVRS 1
65#define TIMER_IER 0x00000024
66#define TIMER_IER_COVFS 0
67#define TIMER_IER_CPAS 2
68#define TIMER_IER_CPBS 3
69#define TIMER_IER_CPCS 4
70#define TIMER_IER_ETRGS 7
71#define TIMER_IER_LDRAS 5
72#define TIMER_IER_LDRBS 6
73#define TIMER_IER_LOVRS 1
74#define TIMER_IMR 0x0000002c
75#define TIMER_IMR_COVFS 0
76#define TIMER_IMR_CPAS 2
77#define TIMER_IMR_CPBS 3
78#define TIMER_IMR_CPCS 4
79#define TIMER_IMR_ETRGS 7
80#define TIMER_IMR_LDRAS 5
81#define TIMER_IMR_LDRBS 6
82#define TIMER_IMR_LOVRS 1
83#define TIMER_RA 0x00000014
84#define TIMER_RA_RA 0
85#define TIMER_RB 0x00000018
86#define TIMER_RB_RB 0
87#define TIMER_RC 0x0000001c
88#define TIMER_RC_RC 0
89#define TIMER_SR 0x00000020
90#define TIMER_SR_CLKSTA 16
91#define TIMER_SR_COVFS 0
92#define TIMER_SR_CPAS 2
93#define TIMER_SR_CPBS 3
94#define TIMER_SR_CPCS 4
95#define TIMER_SR_ETRGS 7
96#define TIMER_SR_LDRAS 5
97#define TIMER_SR_LDRBS 6
98#define TIMER_SR_LOVRS 1
99#define TIMER_SR_MTIOA 17
100#define TIMER_SR_MTIOB 18
101
102/* Bit manipulation macros */
103#define TIMER_BIT(name) (1 << TIMER_##name)
104#define TIMER_BF(name,value) ((value) << TIMER_##name)
105
106/* Register access macros */
107#define timer_read(port,instance,reg) \
108 __raw_readl(port + (0x40 * instance) + TIMER_##reg)
109#define timer_write(port,instance,reg,value) \
110 __raw_writel((value), port + (0x40 * instance) + TIMER_##reg)
111
112#endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */
diff --git a/include/asm-avr32/asm.h b/include/asm-avr32/asm.h
index 515c7618952b..a2c64f404b98 100644
--- a/include/asm-avr32/asm.h
+++ b/include/asm-avr32/asm.h
@@ -12,10 +12,10 @@
12#include <asm/asm-offsets.h> 12#include <asm/asm-offsets.h>
13#include <asm/thread_info.h> 13#include <asm/thread_info.h>
14 14
15#define mask_interrupts ssrf SR_GM_BIT 15#define mask_interrupts ssrf SYSREG_GM_OFFSET
16#define mask_exceptions ssrf SR_EM_BIT 16#define mask_exceptions ssrf SYSREG_EM_OFFSET
17#define unmask_interrupts csrf SR_GM_BIT 17#define unmask_interrupts csrf SYSREG_GM_OFFSET
18#define unmask_exceptions csrf SR_EM_BIT 18#define unmask_exceptions csrf SYSREG_EM_OFFSET
19 19
20#ifdef CONFIG_FRAME_POINTER 20#ifdef CONFIG_FRAME_POINTER
21 .macro save_fp 21 .macro save_fp
diff --git a/include/asm-avr32/intc.h b/include/asm-avr32/intc.h
deleted file mode 100644
index 1ac9ca75e8fd..000000000000
--- a/include/asm-avr32/intc.h
+++ /dev/null
@@ -1,128 +0,0 @@
1#ifndef __ASM_AVR32_INTC_H
2#define __ASM_AVR32_INTC_H
3
4#include <linux/sysdev.h>
5#include <linux/interrupt.h>
6
7struct irq_controller;
8struct irqaction;
9struct pt_regs;
10
11struct platform_device;
12
13/* Information about the internal interrupt controller */
14struct intc_device {
15 /* ioremapped address of configuration block */
16 void __iomem *regs;
17
18 /* the physical device */
19 struct platform_device *pdev;
20
21 /* Number of interrupt lines per group. */
22 unsigned int irqs_per_group;
23
24 /* The highest group ID + 1 */
25 unsigned int nr_groups;
26
27 /*
28 * Bitfield indicating which groups are actually in use. The
29 * size of the array is
30 * ceil(group_max / (8 * sizeof(unsigned int))).
31 */
32 unsigned int group_mask[];
33};
34
35struct irq_controller_class {
36 /*
37 * A short name identifying this kind of controller.
38 */
39 const char *typename;
40 /*
41 * Handle the IRQ. Must do any necessary acking and masking.
42 */
43 irqreturn_t (*handle)(int irq, void *dev_id, struct pt_regs *regs);
44 /*
45 * Register a new IRQ handler.
46 */
47 int (*setup)(struct irq_controller *ctrl, unsigned int irq,
48 struct irqaction *action);
49 /*
50 * Unregister a IRQ handler.
51 */
52 void (*free)(struct irq_controller *ctrl, unsigned int irq,
53 void *dev_id);
54 /*
55 * Mask the IRQ in the interrupt controller.
56 */
57 void (*mask)(struct irq_controller *ctrl, unsigned int irq);
58 /*
59 * Unmask the IRQ in the interrupt controller.
60 */
61 void (*unmask)(struct irq_controller *ctrl, unsigned int irq);
62 /*
63 * Set the type of the IRQ. See below for possible types.
64 * Return -EINVAL if a given type is not supported
65 */
66 int (*set_type)(struct irq_controller *ctrl, unsigned int irq,
67 unsigned int type);
68 /*
69 * Return the IRQ type currently set
70 */
71 unsigned int (*get_type)(struct irq_controller *ctrl, unsigned int irq);
72};
73
74struct irq_controller {
75 struct irq_controller_class *class;
76 unsigned int irq_group;
77 unsigned int first_irq;
78 unsigned int nr_irqs;
79 struct list_head list;
80};
81
82struct intc_group_desc {
83 struct irq_controller *ctrl;
84 irqreturn_t (*handle)(int, void *, struct pt_regs *);
85 unsigned long flags;
86 void *dev_id;
87 const char *devname;
88};
89
90/*
91 * The internal interrupt controller. Defined in board/part-specific
92 * devices.c.
93 * TODO: Should probably be defined per-cpu.
94 */
95extern struct intc_device intc;
96
97extern int request_internal_irq(unsigned int irq,
98 irqreturn_t (*handler)(int, void *, struct pt_regs *),
99 unsigned long irqflags,
100 const char *devname, void *dev_id);
101extern void free_internal_irq(unsigned int irq);
102
103/* Only used by time_init() */
104extern int setup_internal_irq(unsigned int irq, struct intc_group_desc *desc);
105
106/*
107 * Set interrupt priority for a given group. `group' can be found by
108 * using irq_to_group(irq). Priority can be from 0 (lowest) to 3
109 * (highest). Higher-priority interrupts will preempt lower-priority
110 * interrupts (unless interrupts are masked globally).
111 *
112 * This function does not check for conflicts within a group.
113 */
114extern int intc_set_priority(unsigned int group,
115 unsigned int priority);
116
117/*
118 * Returns a bitmask of pending interrupts in a group.
119 */
120extern unsigned long intc_get_pending(unsigned int group);
121
122/*
123 * Register a new external interrupt controller. Returns the first
124 * external IRQ number that is assigned to the new controller.
125 */
126extern int intc_register_controller(struct irq_controller *ctrl);
127
128#endif /* __ASM_AVR32_INTC_H */
diff --git a/include/asm-avr32/irq.h b/include/asm-avr32/irq.h
index 9315724c0596..c563b7720c1a 100644
--- a/include/asm-avr32/irq.h
+++ b/include/asm-avr32/irq.h
@@ -14,6 +14,11 @@
14#ifndef __ASSEMBLER__ 14#ifndef __ASSEMBLER__
15int nmi_enable(void); 15int nmi_enable(void);
16void nmi_disable(void); 16void nmi_disable(void);
17
18/*
19 * Returns a bitmask of pending interrupts in a group.
20 */
21extern unsigned long intc_get_pending(unsigned int group);
17#endif 22#endif
18 23
19#endif /* __ASM_AVR32_IOCTLS_H */ 24#endif /* __ASM_AVR32_IOCTLS_H */
diff --git a/include/asm-avr32/page.h b/include/asm-avr32/page.h
index 5582968feee8..cbbc5ca9728b 100644
--- a/include/asm-avr32/page.h
+++ b/include/asm-avr32/page.h
@@ -8,13 +8,11 @@
8#ifndef __ASM_AVR32_PAGE_H 8#ifndef __ASM_AVR32_PAGE_H
9#define __ASM_AVR32_PAGE_H 9#define __ASM_AVR32_PAGE_H
10 10
11#include <linux/const.h>
12
11/* PAGE_SHIFT determines the page size */ 13/* PAGE_SHIFT determines the page size */
12#define PAGE_SHIFT 12 14#define PAGE_SHIFT 12
13#ifdef __ASSEMBLY__ 15#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
14#define PAGE_SIZE (1 << PAGE_SHIFT)
15#else
16#define PAGE_SIZE (1UL << PAGE_SHIFT)
17#endif
18#define PAGE_MASK (~(PAGE_SIZE-1)) 16#define PAGE_MASK (~(PAGE_SIZE-1))
19#define PTE_MASK PAGE_MASK 17#define PTE_MASK PAGE_MASK
20 18
diff --git a/include/asm-avr32/serial.h b/include/asm-avr32/serial.h
new file mode 100644
index 000000000000..5ecaebc22b02
--- /dev/null
+++ b/include/asm-avr32/serial.h
@@ -0,0 +1,13 @@
1#ifndef _ASM_SERIAL_H
2#define _ASM_SERIAL_H
3
4/*
5 * This assumes you have a 1.8432 MHz clock for your UART.
6 *
7 * It'd be nice if someone built a serial card with a 24.576 MHz
8 * clock, since the 16550A is capable of handling a top speed of 1.5
9 * megabits/second; but this requires the faster clock.
10 */
11#define BASE_BAUD (1843200 / 16)
12
13#endif /* _ASM_SERIAL_H */
diff --git a/include/asm-avr32/xor.h b/include/asm-avr32/xor.h
new file mode 100644
index 000000000000..99c87aa0af4f
--- /dev/null
+++ b/include/asm-avr32/xor.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_XOR_H
2#define _ASM_XOR_H
3
4#include <asm-generic/xor.h>
5
6#endif
diff --git a/include/linux/atmel_tc.h b/include/linux/atmel_tc.h
new file mode 100644
index 000000000000..53ba65e30caa
--- /dev/null
+++ b/include/linux/atmel_tc.h
@@ -0,0 +1,252 @@
1/*
2 * Timer/Counter Unit (TC) registers.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef ATMEL_TC_H
11#define ATMEL_TC_H
12
13#include <linux/compiler.h>
14#include <linux/list.h>
15
16/*
17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
19 * Depending on the SOC, each timer may have its own clock and IRQ, or those
20 * may be shared by the whole TC block.
21 *
22 * These TC blocks may have up to nine external pins: TCLK0..2 signals for
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
24 * or triggering. Those pins need to be set up for use with the TC block,
25 * else they will be used as GPIOs or for a different controller.
26 *
27 * Although we expect each TC block to have a platform_device node, those
28 * nodes are not what drivers bind to. Instead, they ask for a specific
29 * TC block, by number ... which is a common approach on systems with many
30 * timers. Then they use clk_get() and platform_get_irq() to get clock and
31 * IRQ resources.
32 */
33
34struct clk;
35
36/**
37 * struct atmel_tc - information about a Timer/Counter Block
38 * @pdev: physical device
39 * @iomem: resource associated with the I/O register
40 * @regs: mapping through which the I/O registers can be accessed
41 * @irq: irq for each of the three channels
42 * @clk: internal clock source for each of the three channels
43 * @node: list node, for tclib internal use
44 *
45 * On some platforms, each TC channel has its own clocks and IRQs,
46 * while on others, all TC channels share the same clock and IRQ.
47 * Drivers should clk_enable() all the clocks they need even though
48 * all the entries in @clk may point to the same physical clock.
49 * Likewise, drivers should request irqs independently for each
50 * channel, but they must use IRQF_SHARED in case some of the entries
51 * in @irq are actually the same IRQ.
52 */
53struct atmel_tc {
54 struct platform_device *pdev;
55 struct resource *iomem;
56 void __iomem *regs;
57 int irq[3];
58 struct clk *clk[3];
59 struct list_head node;
60};
61
62extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name);
63extern void atmel_tc_free(struct atmel_tc *tc);
64
65/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
66extern const u8 atmel_tc_divisors[5];
67
68
69/*
70 * Two registers have block-wide controls. These are: configuring the three
71 * "external" clocks (or event sources) used by the timer channels; and
72 * synchronizing the timers by resetting them all at once.
73 *
74 * "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
75 * signals. Or, it can mean "external to timer", using the TIOA output from
76 * one of the other two timers that's being run in waveform mode.
77 */
78
79#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
80#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
81
82#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
83#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
84#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
85#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
86#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
87#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
88#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
89#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
90#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
91#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
92#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
93#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
94#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
95#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
96#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
97#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
98
99
100/*
101 * Each TC block has three "channels", each with one counter and controls.
102 *
103 * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
104 * when it's not "external") is silicon-specific. AT91 platforms use one
105 * set of definitions; AVR32 platforms use a different set. Don't hard-wire
106 * such knowledge into your code, use the global "atmel_tc_divisors" ...
107 * where index N is the divisor for clock N+1, else zero to indicate it uses
108 * the 32 KiHz clock.
109 *
110 * The timers can be chained in various ways, and operated in "waveform"
111 * generation mode (including PWM) or "capture" mode (to time events). In
112 * both modes, behavior can be configured in many ways.
113 *
114 * Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
115 * PWM output, and TIOB as either another PWM or as a trigger. Capture mode
116 * uses them only as inputs.
117 */
118#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
119#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
120
121#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
122#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
123#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
124#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
125
126#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
127
128/* Both modes share some CMR bits */
129#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
130#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
131#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
132#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
133#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
134#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
135#define ATMEL_TC_XC0 (5 << 0)
136#define ATMEL_TC_XC1 (6 << 0)
137#define ATMEL_TC_XC2 (7 << 0)
138#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
139#define ATMEL_TC_BURST (3 << 4) /* clock gating */
140#define ATMEL_TC_GATE_NONE (0 << 4)
141#define ATMEL_TC_GATE_XC0 (1 << 4)
142#define ATMEL_TC_GATE_XC1 (2 << 4)
143#define ATMEL_TC_GATE_XC2 (3 << 4)
144#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
145
146/* CAPTURE mode CMR bits */
147#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
148#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
149#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
150#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
151#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
152#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
153#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
154#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
155#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
156#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
157#define ATMEL_TC_LDRA_NONE (0 << 16)
158#define ATMEL_TC_LDRA_RISING (1 << 16)
159#define ATMEL_TC_LDRA_FALLING (2 << 16)
160#define ATMEL_TC_LDRA_BOTH (3 << 16)
161#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
162#define ATMEL_TC_LDRB_NONE (0 << 18)
163#define ATMEL_TC_LDRB_RISING (1 << 18)
164#define ATMEL_TC_LDRB_FALLING (2 << 18)
165#define ATMEL_TC_LDRB_BOTH (3 << 18)
166
167/* WAVEFORM mode CMR bits */
168#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
169#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
170#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
171#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
172#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
173#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
174#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
175#define ATMEL_TC_EEVT (3 << 10) /* external event source */
176#define ATMEL_TC_EEVT_TIOB (0 << 10)
177#define ATMEL_TC_EEVT_XC0 (1 << 10)
178#define ATMEL_TC_EEVT_XC1 (2 << 10)
179#define ATMEL_TC_EEVT_XC2 (3 << 10)
180#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
181#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
182#define ATMEL_TC_WAVESEL_UP (0 << 13)
183#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
184#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
185#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
186#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
187#define ATMEL_TC_ACPA_NONE (0 << 16)
188#define ATMEL_TC_ACPA_SET (1 << 16)
189#define ATMEL_TC_ACPA_CLEAR (2 << 16)
190#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
191#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
192#define ATMEL_TC_ACPC_NONE (0 << 18)
193#define ATMEL_TC_ACPC_SET (1 << 18)
194#define ATMEL_TC_ACPC_CLEAR (2 << 18)
195#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
196#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
197#define ATMEL_TC_AEEVT_NONE (0 << 20)
198#define ATMEL_TC_AEEVT_SET (1 << 20)
199#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
200#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
201#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
202#define ATMEL_TC_ASWTRG_NONE (0 << 22)
203#define ATMEL_TC_ASWTRG_SET (1 << 22)
204#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
205#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
206#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
207#define ATMEL_TC_BCPB_NONE (0 << 24)
208#define ATMEL_TC_BCPB_SET (1 << 24)
209#define ATMEL_TC_BCPB_CLEAR (2 << 24)
210#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
211#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
212#define ATMEL_TC_BCPC_NONE (0 << 26)
213#define ATMEL_TC_BCPC_SET (1 << 26)
214#define ATMEL_TC_BCPC_CLEAR (2 << 26)
215#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
216#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
217#define ATMEL_TC_BEEVT_NONE (0 << 28)
218#define ATMEL_TC_BEEVT_SET (1 << 28)
219#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
220#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
221#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
222#define ATMEL_TC_BSWTRG_NONE (0 << 30)
223#define ATMEL_TC_BSWTRG_SET (1 << 30)
224#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
225#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
226
227#define ATMEL_TC_CV 0x10 /* counter Value */
228#define ATMEL_TC_RA 0x14 /* register A */
229#define ATMEL_TC_RB 0x18 /* register B */
230#define ATMEL_TC_RC 0x1c /* register C */
231
232#define ATMEL_TC_SR 0x20 /* status (read-only) */
233/* Status-only flags */
234#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
235#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
236#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
237
238#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
239#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
240#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
241
242/* Status and IRQ flags */
243#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
244#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
245#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
246#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
247#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
248#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
249#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
250#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
251
252#endif
diff --git a/include/linux/usb/atmel_usba_udc.h b/include/linux/usb/atmel_usba_udc.h
new file mode 100644
index 000000000000..6311fa2d9f82
--- /dev/null
+++ b/include/linux/usb/atmel_usba_udc.h
@@ -0,0 +1,22 @@
1/*
2 * Platform data definitions for Atmel USBA gadget driver.
3 */
4#ifndef __LINUX_USB_USBA_H
5#define __LINUX_USB_USBA_H
6
7struct usba_ep_data {
8 char *name;
9 int index;
10 int fifo_size;
11 int nr_banks;
12 int can_dma;
13 int can_isoc;
14};
15
16struct usba_platform_data {
17 int vbus_pin;
18 int num_ep;
19 struct usba_ep_data ep[0];
20};
21
22#endif /* __LINUX_USB_USBA_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-17 22:00:36 -0500