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-rw-r--r--Documentation/serial/driver4
-rw-r--r--arch/arm/kernel/armksyms.c6
-rw-r--r--arch/arm/kernel/setup.c3
-rw-r--r--arch/arm/kernel/smp.c123
-rw-r--r--arch/arm/lib/Makefile2
-rw-r--r--arch/arm/lib/longlong.h183
-rw-r--r--arch/arm/lib/udivdi3.c222
-rw-r--r--arch/arm/mach-integrator/core.c41
-rw-r--r--arch/arm/mach-omap/pm.c16
-rw-r--r--arch/arm/mach-omap/time.c44
-rw-r--r--arch/arm/mach-s3c2410/Kconfig5
-rw-r--r--arch/arm/mach-s3c2410/Makefile1
-rw-r--r--arch/arm/mach-s3c2410/devs.c4
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c39
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c8
-rw-r--r--arch/arm/mach-s3c2410/pm-simtec.c65
-rw-r--r--arch/arm/mach-versatile/core.c61
-rw-r--r--arch/arm/mm/init.c2
-rw-r--r--arch/arm/mm/mm-armv.c2
-rw-r--r--arch/arm/vfp/vfp.h15
-rw-r--r--arch/arm/vfp/vfpdouble.c2
-rw-r--r--arch/arm/vfp/vfpmodule.c2
-rw-r--r--arch/arm/vfp/vfpsingle.c14
-rw-r--r--arch/ia64/configs/sn2_defconfig4
-rw-r--r--arch/ia64/configs/tiger_defconfig39
-rw-r--r--arch/ia64/configs/zx1_defconfig166
-rw-r--r--arch/ia64/hp/common/sba_iommu.c4
-rw-r--r--arch/ia64/hp/sim/simserial.c16
-rw-r--r--arch/ia64/kernel/entry.S110
-rw-r--r--arch/ia64/kernel/fsys.S147
-rw-r--r--arch/ia64/kernel/gate.S62
-rw-r--r--arch/ia64/kernel/ia64_ksyms.c3
-rw-r--r--arch/ia64/kernel/ivt.S198
-rw-r--r--arch/ia64/kernel/ptrace.c22
-rw-r--r--arch/ia64/kernel/setup.c12
-rw-r--r--arch/ia64/kernel/smp.c3
-rw-r--r--arch/ia64/sn/kernel/io_init.c2
-rw-r--r--arch/ia64/sn/kernel/iomv.c6
-rw-r--r--arch/ia64/sn/kernel/setup.c43
-rw-r--r--arch/ia64/sn/kernel/sn2/ptc_deadlock.S1
-rw-r--r--arch/ia64/sn/kernel/tiocx.c14
-rw-r--r--arch/ia64/sn/pci/tioca_provider.c8
-rw-r--r--arch/parisc/configs/712_defconfig2
-rw-r--r--arch/parisc/configs/a500_defconfig2
-rw-r--r--arch/parisc/configs/b180_defconfig2
-rw-r--r--arch/parisc/configs/c3000_defconfig2
-rw-r--r--arch/parisc/defconfig2
-rw-r--r--drivers/firmware/pcdp.c24
-rw-r--r--drivers/firmware/pcdp.h33
-rw-r--r--drivers/i2c/chips/atxp1.c2
-rw-r--r--drivers/net/arm/etherh.c16
-rw-r--r--drivers/serial/8250.c33
-rw-r--r--drivers/serial/Kconfig2
-rw-r--r--drivers/serial/au1x00_uart.c3
-rw-r--r--drivers/serial/ip22zilog.c13
-rw-r--r--drivers/serial/mpsc.c3
-rw-r--r--drivers/serial/pmac_zilog.c4
-rw-r--r--drivers/serial/pxa.c3
-rw-r--r--drivers/serial/serial_core.c28
-rw-r--r--drivers/serial/serial_txx9.c3
-rw-r--r--drivers/serial/sunsab.c7
-rw-r--r--drivers/serial/sunsu.c3
-rw-r--r--drivers/serial/sunzilog.c13
-rw-r--r--fs/reiserfs/ioctl.c6
-rw-r--r--fs/reiserfs/super.c2
-rw-r--r--include/asm-alpha/serial.h47
-rw-r--r--include/asm-arm/arch-pxa/debug-macro.S2
-rw-r--r--include/asm-arm/hardware/arm_timer.h21
-rw-r--r--include/asm-arm/system.h12
-rw-r--r--include/asm-arm/tlbflush.h28
-rw-r--r--include/asm-arm26/serial.h22
-rw-r--r--include/asm-i386/serial.h102
-rw-r--r--include/asm-ia64/mmu_context.h3
-rw-r--r--include/asm-ia64/sn/addrs.h17
-rw-r--r--include/asm-ia64/sn/l1.h1
-rw-r--r--include/asm-ia64/sn/shub_mmr.h346
-rw-r--r--include/asm-ia64/sn/simulator.h13
-rw-r--r--include/asm-ia64/sn/sn2/sn_hwperf.h2
-rw-r--r--include/asm-ia64/sn/sn_sal.h10
-rw-r--r--include/asm-ia64/sn/tioca_provider.h1
-rw-r--r--include/asm-ia64/vga.h5
-rw-r--r--include/asm-m68k/serial.h47
-rw-r--r--include/asm-mips/serial.h84
-rw-r--r--include/asm-parisc/serial.h16
-rw-r--r--include/asm-ppc/pc_serial.h86
-rw-r--r--include/asm-sh/bigsur/serial.h5
-rw-r--r--include/asm-sh/ec3104/serial.h4
-rw-r--r--include/asm-sh/serial.h6
-rw-r--r--include/asm-sh64/serial.h4
-rw-r--r--include/asm-x86_64/serial.h102
90 files changed, 1289 insertions, 1629 deletions
diff --git a/Documentation/serial/driver b/Documentation/serial/driver
index e9c0178cd202..ac7eabbf662a 100644
--- a/Documentation/serial/driver
+++ b/Documentation/serial/driver
@@ -107,8 +107,8 @@ hardware.
107 indicate that the signal is permanently active. If RI is 107 indicate that the signal is permanently active. If RI is
108 not available, the signal should not be indicated as active. 108 not available, the signal should not be indicated as active.
109 109
110 Locking: none. 110 Locking: port->lock taken.
111 Interrupts: caller dependent. 111 Interrupts: locally disabled.
112 This call must not sleep 112 This call must not sleep
113 113
114 stop_tx(port,tty_stop) 114 stop_tx(port,tty_stop)
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 4c38bd8bc298..b713c44c6fb4 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -30,9 +30,6 @@ extern void __lshrdi3(void);
30extern void __modsi3(void); 30extern void __modsi3(void);
31extern void __muldi3(void); 31extern void __muldi3(void);
32extern void __ucmpdi2(void); 32extern void __ucmpdi2(void);
33extern void __udivdi3(void);
34extern void __umoddi3(void);
35extern void __udivmoddi4(void);
36extern void __udivsi3(void); 33extern void __udivsi3(void);
37extern void __umodsi3(void); 34extern void __umodsi3(void);
38extern void __do_div64(void); 35extern void __do_div64(void);
@@ -134,9 +131,6 @@ EXPORT_SYMBOL(__lshrdi3);
134EXPORT_SYMBOL(__modsi3); 131EXPORT_SYMBOL(__modsi3);
135EXPORT_SYMBOL(__muldi3); 132EXPORT_SYMBOL(__muldi3);
136EXPORT_SYMBOL(__ucmpdi2); 133EXPORT_SYMBOL(__ucmpdi2);
137EXPORT_SYMBOL(__udivdi3);
138EXPORT_SYMBOL(__umoddi3);
139EXPORT_SYMBOL(__udivmoddi4);
140EXPORT_SYMBOL(__udivsi3); 134EXPORT_SYMBOL(__udivsi3);
141EXPORT_SYMBOL(__umodsi3); 135EXPORT_SYMBOL(__umodsi3);
142EXPORT_SYMBOL(__do_div64); 136EXPORT_SYMBOL(__do_div64);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 8cf733daa800..35b7273cfdb4 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -359,7 +359,8 @@ void cpu_init(void)
359 "I" (offsetof(struct stack, abt[0])), 359 "I" (offsetof(struct stack, abt[0])),
360 "I" (PSR_F_BIT | PSR_I_BIT | UND_MODE), 360 "I" (PSR_F_BIT | PSR_I_BIT | UND_MODE),
361 "I" (offsetof(struct stack, und[0])), 361 "I" (offsetof(struct stack, und[0])),
362 "I" (PSR_F_BIT | PSR_I_BIT | SVC_MODE)); 362 "I" (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
363 : "r14");
363} 364}
364 365
365static struct machine_desc * __init setup_machine(unsigned int nr) 366static struct machine_desc * __init setup_machine(unsigned int nr)
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 34892758f098..a931409c8fe4 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -502,3 +502,126 @@ int __init setup_profiling_timer(unsigned int multiplier)
502{ 502{
503 return -EINVAL; 503 return -EINVAL;
504} 504}
505
506static int
507on_each_cpu_mask(void (*func)(void *), void *info, int retry, int wait,
508 cpumask_t mask)
509{
510 int ret = 0;
511
512 preempt_disable();
513
514 ret = smp_call_function_on_cpu(func, info, retry, wait, mask);
515 if (cpu_isset(smp_processor_id(), mask))
516 func(info);
517
518 preempt_enable();
519
520 return ret;
521}
522
523/**********************************************************************/
524
525/*
526 * TLB operations
527 */
528struct tlb_args {
529 struct vm_area_struct *ta_vma;
530 unsigned long ta_start;
531 unsigned long ta_end;
532};
533
534static inline void ipi_flush_tlb_all(void *ignored)
535{
536 local_flush_tlb_all();
537}
538
539static inline void ipi_flush_tlb_mm(void *arg)
540{
541 struct mm_struct *mm = (struct mm_struct *)arg;
542
543 local_flush_tlb_mm(mm);
544}
545
546static inline void ipi_flush_tlb_page(void *arg)
547{
548 struct tlb_args *ta = (struct tlb_args *)arg;
549
550 local_flush_tlb_page(ta->ta_vma, ta->ta_start);
551}
552
553static inline void ipi_flush_tlb_kernel_page(void *arg)
554{
555 struct tlb_args *ta = (struct tlb_args *)arg;
556
557 local_flush_tlb_kernel_page(ta->ta_start);
558}
559
560static inline void ipi_flush_tlb_range(void *arg)
561{
562 struct tlb_args *ta = (struct tlb_args *)arg;
563
564 local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
565}
566
567static inline void ipi_flush_tlb_kernel_range(void *arg)
568{
569 struct tlb_args *ta = (struct tlb_args *)arg;
570
571 local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
572}
573
574void flush_tlb_all(void)
575{
576 on_each_cpu(ipi_flush_tlb_all, NULL, 1, 1);
577}
578
579void flush_tlb_mm(struct mm_struct *mm)
580{
581 cpumask_t mask = mm->cpu_vm_mask;
582
583 on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, 1, mask);
584}
585
586void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
587{
588 cpumask_t mask = vma->vm_mm->cpu_vm_mask;
589 struct tlb_args ta;
590
591 ta.ta_vma = vma;
592 ta.ta_start = uaddr;
593
594 on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, 1, mask);
595}
596
597void flush_tlb_kernel_page(unsigned long kaddr)
598{
599 struct tlb_args ta;
600
601 ta.ta_start = kaddr;
602
603 on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1, 1);
604}
605
606void flush_tlb_range(struct vm_area_struct *vma,
607 unsigned long start, unsigned long end)
608{
609 cpumask_t mask = vma->vm_mm->cpu_vm_mask;
610 struct tlb_args ta;
611
612 ta.ta_vma = vma;
613 ta.ta_start = start;
614 ta.ta_end = end;
615
616 on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, 1, mask);
617}
618
619void flush_tlb_kernel_range(unsigned long start, unsigned long end)
620{
621 struct tlb_args ta;
622
623 ta.ta_start = start;
624 ta.ta_end = end;
625
626 on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1, 1);
627}
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index c0e65833ffc4..8725d63e4219 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -11,7 +11,7 @@ lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
11 strnlen_user.o strchr.o strrchr.o testchangebit.o \ 11 strnlen_user.o strchr.o strrchr.o testchangebit.o \
12 testclearbit.o testsetbit.o uaccess.o getuser.o \ 12 testclearbit.o testsetbit.o uaccess.o getuser.o \
13 putuser.o ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ 13 putuser.o ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
14 ucmpdi2.o udivdi3.o lib1funcs.o div64.o \ 14 ucmpdi2.o lib1funcs.o div64.o \
15 io-readsb.o io-writesb.o io-readsl.o io-writesl.o 15 io-readsb.o io-writesb.o io-readsl.o io-writesl.o
16 16
17ifeq ($(CONFIG_CPU_32v3),y) 17ifeq ($(CONFIG_CPU_32v3),y)
diff --git a/arch/arm/lib/longlong.h b/arch/arm/lib/longlong.h
deleted file mode 100644
index 90ae647e4d76..000000000000
--- a/arch/arm/lib/longlong.h
+++ /dev/null
@@ -1,183 +0,0 @@
1/* longlong.h -- based on code from gcc-2.95.3
2
3 definitions for mixed size 32/64 bit arithmetic.
4 Copyright (C) 1991, 92, 94, 95, 96, 1997, 1998 Free Software Foundation, Inc.
5
6 This definition file is free software; you can redistribute it
7 and/or modify it under the terms of the GNU General Public
8 License as published by the Free Software Foundation; either
9 version 2, or (at your option) any later version.
10
11 This definition file is distributed in the hope that it will be
12 useful, but WITHOUT ANY WARRANTY; without even the implied
13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 See the GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
20
21/* Borrowed from GCC 2.95.3, I Molton 29/07/01 */
22
23#ifndef SI_TYPE_SIZE
24#define SI_TYPE_SIZE 32
25#endif
26
27#define __BITS4 (SI_TYPE_SIZE / 4)
28#define __ll_B (1L << (SI_TYPE_SIZE / 2))
29#define __ll_lowpart(t) ((u32) (t) % __ll_B)
30#define __ll_highpart(t) ((u32) (t) / __ll_B)
31
32/* Define auxiliary asm macros.
33
34 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand)
35 multiplies two u32 integers MULTIPLER and MULTIPLICAND,
36 and generates a two-part u32 product in HIGH_PROD and
37 LOW_PROD.
38
39 2) __umulsidi3(a,b) multiplies two u32 integers A and B,
40 and returns a u64 product. This is just a variant of umul_ppmm.
41
42 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
43 denominator) divides a two-word unsigned integer, composed by the
44 integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and
45 places the quotient in QUOTIENT and the remainder in REMAINDER.
46 HIGH_NUMERATOR must be less than DENOMINATOR for correct operation.
47 If, in addition, the most significant bit of DENOMINATOR must be 1,
48 then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1.
49
50 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
51 denominator). Like udiv_qrnnd but the numbers are signed. The
52 quotient is rounded towards 0.
53
54 5) count_leading_zeros(count, x) counts the number of zero-bits from
55 the msb to the first non-zero bit. This is the number of steps X
56 needs to be shifted left to set the msb. Undefined for X == 0.
57
58 6) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
59 high_addend_2, low_addend_2) adds two two-word unsigned integers,
60 composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and
61 LOW_ADDEND_2 respectively. The result is placed in HIGH_SUM and
62 LOW_SUM. Overflow (i.e. carry out) is not stored anywhere, and is
63 lost.
64
65 7) sub_ddmmss(high_difference, low_difference, high_minuend,
66 low_minuend, high_subtrahend, low_subtrahend) subtracts two
67 two-word unsigned integers, composed by HIGH_MINUEND_1 and
68 LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2
69 respectively. The result is placed in HIGH_DIFFERENCE and
70 LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
71 and is lost.
72
73 If any of these macros are left undefined for a particular CPU,
74 C macros are used. */
75
76#if defined (__arm__)
77#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
78 __asm__ ("adds %1, %4, %5 \n\
79 adc %0, %2, %3" \
80 : "=r" ((u32) (sh)), \
81 "=&r" ((u32) (sl)) \
82 : "%r" ((u32) (ah)), \
83 "rI" ((u32) (bh)), \
84 "%r" ((u32) (al)), \
85 "rI" ((u32) (bl)))
86#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
87 __asm__ ("subs %1, %4, %5 \n\
88 sbc %0, %2, %3" \
89 : "=r" ((u32) (sh)), \
90 "=&r" ((u32) (sl)) \
91 : "r" ((u32) (ah)), \
92 "rI" ((u32) (bh)), \
93 "r" ((u32) (al)), \
94 "rI" ((u32) (bl)))
95#define umul_ppmm(xh, xl, a, b) \
96{register u32 __t0, __t1, __t2; \
97 __asm__ ("%@ Inlined umul_ppmm \n\
98 mov %2, %5, lsr #16 \n\
99 mov %0, %6, lsr #16 \n\
100 bic %3, %5, %2, lsl #16 \n\
101 bic %4, %6, %0, lsl #16 \n\
102 mul %1, %3, %4 \n\
103 mul %4, %2, %4 \n\
104 mul %3, %0, %3 \n\
105 mul %0, %2, %0 \n\
106 adds %3, %4, %3 \n\
107 addcs %0, %0, #65536 \n\
108 adds %1, %1, %3, lsl #16 \n\
109 adc %0, %0, %3, lsr #16" \
110 : "=&r" ((u32) (xh)), \
111 "=r" ((u32) (xl)), \
112 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
113 : "r" ((u32) (a)), \
114 "r" ((u32) (b)));}
115#define UMUL_TIME 20
116#define UDIV_TIME 100
117#endif /* __arm__ */
118
119#define __umulsidi3(u, v) \
120 ({DIunion __w; \
121 umul_ppmm (__w.s.high, __w.s.low, u, v); \
122 __w.ll; })
123
124#define __udiv_qrnnd_c(q, r, n1, n0, d) \
125 do { \
126 u32 __d1, __d0, __q1, __q0; \
127 u32 __r1, __r0, __m; \
128 __d1 = __ll_highpart (d); \
129 __d0 = __ll_lowpart (d); \
130 \
131 __r1 = (n1) % __d1; \
132 __q1 = (n1) / __d1; \
133 __m = (u32) __q1 * __d0; \
134 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
135 if (__r1 < __m) \
136 { \
137 __q1--, __r1 += (d); \
138 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
139 if (__r1 < __m) \
140 __q1--, __r1 += (d); \
141 } \
142 __r1 -= __m; \
143 \
144 __r0 = __r1 % __d1; \
145 __q0 = __r1 / __d1; \
146 __m = (u32) __q0 * __d0; \
147 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
148 if (__r0 < __m) \
149 { \
150 __q0--, __r0 += (d); \
151 if (__r0 >= (d)) \
152 if (__r0 < __m) \
153 __q0--, __r0 += (d); \
154 } \
155 __r0 -= __m; \
156 \
157 (q) = (u32) __q1 * __ll_B | __q0; \
158 (r) = __r0; \
159 } while (0)
160
161#define UDIV_NEEDS_NORMALIZATION 1
162#define udiv_qrnnd __udiv_qrnnd_c
163
164#define count_leading_zeros(count, x) \
165 do { \
166 u32 __xr = (x); \
167 u32 __a; \
168 \
169 if (SI_TYPE_SIZE <= 32) \
170 { \
171 __a = __xr < ((u32)1<<2*__BITS4) \
172 ? (__xr < ((u32)1<<__BITS4) ? 0 : __BITS4) \
173 : (__xr < ((u32)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
174 } \
175 else \
176 { \
177 for (__a = SI_TYPE_SIZE - 8; __a > 0; __a -= 8) \
178 if (((__xr >> __a) & 0xff) != 0) \
179 break; \
180 } \
181 \
182 (count) = SI_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
183 } while (0)
diff --git a/arch/arm/lib/udivdi3.c b/arch/arm/lib/udivdi3.c
deleted file mode 100644
index e343be4c6642..000000000000
--- a/arch/arm/lib/udivdi3.c
+++ /dev/null
@@ -1,222 +0,0 @@
1/* More subroutines needed by GCC output code on some machines. */
2/* Compile this one with gcc. */
3/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc.
4
5This file is part of GNU CC.
6
7GNU CC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12GNU CC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GNU CC; see the file COPYING. If not, write to
19the Free Software Foundation, 59 Temple Place - Suite 330,
20Boston, MA 02111-1307, USA. */
21
22/* As a special exception, if you link this library with other files,
23 some of which are compiled with GCC, to produce an executable,
24 this library does not by itself cause the resulting executable
25 to be covered by the GNU General Public License.
26 This exception does not however invalidate any other reasons why
27 the executable file might be covered by the GNU General Public License.
28 */
29/* support functions required by the kernel. based on code from gcc-2.95.3 */
30/* I Molton 29/07/01 */
31
32#include "gcclib.h"
33#include "longlong.h"
34
35static const u8 __clz_tab[] = {
36 0, 1, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5,
37 5, 5, 5, 5, 5, 5, 5, 5,
38 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
39 6, 6, 6, 6, 6, 6, 6, 6,
40 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
41 7, 7, 7, 7, 7, 7, 7, 7,
42 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
43 7, 7, 7, 7, 7, 7, 7, 7,
44 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
45 8, 8, 8, 8, 8, 8, 8, 8,
46 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
47 8, 8, 8, 8, 8, 8, 8, 8,
48 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
49 8, 8, 8, 8, 8, 8, 8, 8,
50 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
51 8, 8, 8, 8, 8, 8, 8, 8,
52};
53
54u64 __udivmoddi4(u64 n, u64 d, u64 * rp)
55{
56 DIunion ww;
57 DIunion nn, dd;
58 DIunion rr;
59 u32 d0, d1, n0, n1, n2;
60 u32 q0, q1;
61 u32 b, bm;
62
63 nn.ll = n;
64 dd.ll = d;
65
66 d0 = dd.s.low;
67 d1 = dd.s.high;
68 n0 = nn.s.low;
69 n1 = nn.s.high;
70
71 if (d1 == 0) {
72 if (d0 > n1) {
73 /* 0q = nn / 0D */
74
75 count_leading_zeros(bm, d0);
76
77 if (bm != 0) {
78 /* Normalize, i.e. make the most significant bit of the
79 denominator set. */
80
81 d0 = d0 << bm;
82 n1 = (n1 << bm) | (n0 >> (SI_TYPE_SIZE - bm));
83 n0 = n0 << bm;
84 }
85
86 udiv_qrnnd(q0, n0, n1, n0, d0);
87 q1 = 0;
88
89 /* Remainder in n0 >> bm. */
90 } else {
91 /* qq = NN / 0d */
92
93 if (d0 == 0)
94 d0 = 1 / d0; /* Divide intentionally by zero. */
95
96 count_leading_zeros(bm, d0);
97
98 if (bm == 0) {
99 /* From (n1 >= d0) /\ (the most significant bit of d0 is set),
100 conclude (the most significant bit of n1 is set) /\ (the
101 leading quotient digit q1 = 1).
102
103 This special case is necessary, not an optimization.
104 (Shifts counts of SI_TYPE_SIZE are undefined.) */
105
106 n1 -= d0;
107 q1 = 1;
108 } else {
109 /* Normalize. */
110
111 b = SI_TYPE_SIZE - bm;
112
113 d0 = d0 << bm;
114 n2 = n1 >> b;
115 n1 = (n1 << bm) | (n0 >> b);
116 n0 = n0 << bm;
117
118 udiv_qrnnd(q1, n1, n2, n1, d0);
119 }
120
121 /* n1 != d0... */
122
123 udiv_qrnnd(q0, n0, n1, n0, d0);
124
125 /* Remainder in n0 >> bm. */
126 }
127
128 if (rp != 0) {
129 rr.s.low = n0 >> bm;
130 rr.s.high = 0;
131 *rp = rr.ll;
132 }
133 } else {
134 if (d1 > n1) {
135 /* 00 = nn / DD */
136
137 q0 = 0;
138 q1 = 0;
139
140 /* Remainder in n1n0. */
141 if (rp != 0) {
142 rr.s.low = n0;
143 rr.s.high = n1;
144 *rp = rr.ll;
145 }
146 } else {
147 /* 0q = NN / dd */
148
149 count_leading_zeros(bm, d1);
150 if (bm == 0) {
151 /* From (n1 >= d1) /\ (the most significant bit of d1 is set),
152 conclude (the most significant bit of n1 is set) /\ (the
153 quotient digit q0 = 0 or 1).
154
155 This special case is necessary, not an optimization. */
156
157 /* The condition on the next line takes advantage of that
158 n1 >= d1 (true due to program flow). */
159 if (n1 > d1 || n0 >= d0) {
160 q0 = 1;
161 sub_ddmmss(n1, n0, n1, n0, d1, d0);
162 } else
163 q0 = 0;
164
165 q1 = 0;
166
167 if (rp != 0) {
168 rr.s.low = n0;
169 rr.s.high = n1;
170 *rp = rr.ll;
171 }
172 } else {
173 u32 m1, m0;
174 /* Normalize. */
175
176 b = SI_TYPE_SIZE - bm;
177
178 d1 = (d1 << bm) | (d0 >> b);
179 d0 = d0 << bm;
180 n2 = n1 >> b;
181 n1 = (n1 << bm) | (n0 >> b);
182 n0 = n0 << bm;
183
184 udiv_qrnnd(q0, n1, n2, n1, d1);
185 umul_ppmm(m1, m0, q0, d0);
186
187 if (m1 > n1 || (m1 == n1 && m0 > n0)) {
188 q0--;
189 sub_ddmmss(m1, m0, m1, m0, d1, d0);
190 }
191
192 q1 = 0;
193
194 /* Remainder in (n1n0 - m1m0) >> bm. */
195 if (rp != 0) {
196 sub_ddmmss(n1, n0, n1, n0, m1, m0);
197 rr.s.low = (n1 << b) | (n0 >> bm);
198 rr.s.high = n1 >> bm;
199 *rp = rr.ll;
200 }
201 }
202 }
203 }
204
205 ww.s.low = q0;
206 ww.s.high = q1;
207 return ww.ll;
208}
209
210u64 __udivdi3(u64 n, u64 d)
211{
212 return __udivmoddi4(n, d, (u64 *) 0);
213}
214
215u64 __umoddi3(u64 u, u64 v)
216{
217 u64 w;
218
219 (void)__udivmoddi4(u, v, &w);
220
221 return w;
222}
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 9222e57bd872..dacbf504dae2 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -20,6 +20,7 @@
20#include <asm/irq.h> 20#include <asm/irq.h>
21#include <asm/io.h> 21#include <asm/io.h>
22#include <asm/hardware/amba.h> 22#include <asm/hardware/amba.h>
23#include <asm/hardware/arm_timer.h>
23#include <asm/arch/cm.h> 24#include <asm/arch/cm.h>
24#include <asm/system.h> 25#include <asm/system.h>
25#include <asm/leds.h> 26#include <asm/leds.h>
@@ -156,16 +157,6 @@ EXPORT_SYMBOL(cm_control);
156#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) 157#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
157#endif 158#endif
158 159
159/*
160 * What does it look like?
161 */
162typedef struct TimerStruct {
163 unsigned long TimerLoad;
164 unsigned long TimerValue;
165 unsigned long TimerControl;
166 unsigned long TimerClear;
167} TimerStruct_t;
168
169static unsigned long timer_reload; 160static unsigned long timer_reload;
170 161
171/* 162/*
@@ -174,7 +165,6 @@ static unsigned long timer_reload;
174 */ 165 */
175unsigned long integrator_gettimeoffset(void) 166unsigned long integrator_gettimeoffset(void)
176{ 167{
177 volatile TimerStruct_t *timer1 = (TimerStruct_t *)TIMER1_VA_BASE;
178 unsigned long ticks1, ticks2, status; 168 unsigned long ticks1, ticks2, status;
179 169
180 /* 170 /*
@@ -183,11 +173,11 @@ unsigned long integrator_gettimeoffset(void)
183 * an interrupt. We get around this by ensuring that the 173 * an interrupt. We get around this by ensuring that the
184 * counter has not reloaded between our two reads. 174 * counter has not reloaded between our two reads.
185 */ 175 */
186 ticks2 = timer1->TimerValue & 0xffff; 176 ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff;
187 do { 177 do {
188 ticks1 = ticks2; 178 ticks1 = ticks2;
189 status = __raw_readl(VA_IC_BASE + IRQ_RAW_STATUS); 179 status = __raw_readl(VA_IC_BASE + IRQ_RAW_STATUS);
190 ticks2 = timer1->TimerValue & 0xffff; 180 ticks2 = readl(TIMER1_VA_BASE + TIMER_VALUE) & 0xffff;
191 } while (ticks2 > ticks1); 181 } while (ticks2 > ticks1);
192 182
193 /* 183 /*
@@ -213,14 +203,12 @@ unsigned long integrator_gettimeoffset(void)
213static irqreturn_t 203static irqreturn_t
214integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 204integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
215{ 205{
216 volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE;
217
218 write_seqlock(&xtime_lock); 206 write_seqlock(&xtime_lock);
219 207
220 /* 208 /*
221 * clear the interrupt 209 * clear the interrupt
222 */ 210 */
223 timer1->TimerClear = 1; 211 writel(1, TIMER1_VA_BASE + TIMER_INTCLR);
224 212
225 /* 213 /*
226 * the clock tick routines are only processed on the 214 * the clock tick routines are only processed on the
@@ -256,32 +244,29 @@ static struct irqaction integrator_timer_irq = {
256 */ 244 */
257void __init integrator_time_init(unsigned long reload, unsigned int ctrl) 245void __init integrator_time_init(unsigned long reload, unsigned int ctrl)
258{ 246{
259 volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE; 247 unsigned int timer_ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
260 volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE;
261 volatile TimerStruct_t *timer2 = (volatile TimerStruct_t *)TIMER2_VA_BASE;
262 unsigned int timer_ctrl = 0x80 | 0x40; /* periodic */
263 248
264 timer_reload = reload; 249 timer_reload = reload;
265 timer_ctrl |= ctrl; 250 timer_ctrl |= ctrl;
266 251
267 if (timer_reload > 0x100000) { 252 if (timer_reload > 0x100000) {
268 timer_reload >>= 8; 253 timer_reload >>= 8;
269 timer_ctrl |= 0x08; /* /256 */ 254 timer_ctrl |= TIMER_CTRL_DIV256;
270 } else if (timer_reload > 0x010000) { 255 } else if (timer_reload > 0x010000) {
271 timer_reload >>= 4; 256 timer_reload >>= 4;
272 timer_ctrl |= 0x04; /* /16 */ 257 timer_ctrl |= TIMER_CTRL_DIV16;
273 } 258 }
274 259
275 /* 260 /*
276 * Initialise to a known state (all timers off) 261 * Initialise to a known state (all timers off)
277 */ 262 */
278 timer0->TimerControl = 0; 263 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
279 timer1->TimerControl = 0; 264 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
280 timer2->TimerControl = 0; 265 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
281 266
282 timer1->TimerLoad = timer_reload; 267 writel(timer_reload, TIMER1_VA_BASE + TIMER_LOAD);
283 timer1->TimerValue = timer_reload; 268 writel(timer_reload, TIMER1_VA_BASE + TIMER_VALUE);
284 timer1->TimerControl = timer_ctrl; 269 writel(timer_ctrl, TIMER1_VA_BASE + TIMER_CTRL);
285 270
286 /* 271 /*
287 * Make irqs happen for the system timer 272 * Make irqs happen for the system timer
diff --git a/arch/arm/mach-omap/pm.c b/arch/arm/mach-omap/pm.c
index 00fac155df2a..6b03ccdc1e92 100644
--- a/arch/arm/mach-omap/pm.c
+++ b/arch/arm/mach-omap/pm.c
@@ -41,7 +41,9 @@
41#include <linux/pm.h> 41#include <linux/pm.h>
42 42
43#include <asm/io.h> 43#include <asm/io.h>
44#include <asm/mach/time.h>
44#include <asm/mach-types.h> 45#include <asm/mach-types.h>
46
45#include <asm/arch/omap16xx.h> 47#include <asm/arch/omap16xx.h>
46#include <asm/arch/pm.h> 48#include <asm/arch/pm.h>
47#include <asm/arch/mux.h> 49#include <asm/arch/mux.h>
@@ -80,13 +82,13 @@ void omap_pm_idle(void)
80 return; 82 return;
81 } 83 }
82 mask32 = omap_readl(ARM_SYSST); 84 mask32 = omap_readl(ARM_SYSST);
83 local_fiq_enable();
84 local_irq_enable();
85 85
86#if defined(CONFIG_OMAP_32K_TIMER) && defined(CONFIG_NO_IDLE_HZ) 86 /*
87 /* Override timer to use VST for the next cycle */ 87 * Since an interrupt may set up a timer, we don't want to
88 omap_32k_timer_next_vst_interrupt(); 88 * reprogram the hardware timer with interrupts enabled.
89#endif 89 * Re-enable interrupts only after returning from idle.
90 */
91 timer_dyn_reprogram();
90 92
91 if ((mask32 & DSP_IDLE) == 0) { 93 if ((mask32 & DSP_IDLE) == 0) {
92 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4"); 94 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
@@ -102,6 +104,8 @@ void omap_pm_idle(void)
102 104
103 func_ptr(); 105 func_ptr();
104 } 106 }
107 local_fiq_enable();
108 local_irq_enable();
105} 109}
106 110
107/* 111/*
diff --git a/arch/arm/mach-omap/time.c b/arch/arm/mach-omap/time.c
index 589e8b2740dd..dd34e9f4c413 100644
--- a/arch/arm/mach-omap/time.c
+++ b/arch/arm/mach-omap/time.c
@@ -4,7 +4,7 @@
4 * OMAP Timers 4 * OMAP Timers
5 * 5 *
6 * Copyright (C) 2004 Nokia Corporation 6 * Copyright (C) 2004 Nokia Corporation
7 * Partial timer rewrite and additional VST timer support by 7 * Partial timer rewrite and additional dynamic tick timer support by
8 * Tony Lindgen <tony@atomide.com> and 8 * Tony Lindgen <tony@atomide.com> and
9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * 10 *
@@ -261,7 +261,6 @@ unsigned long long sched_clock(void)
261 * so with HZ = 100, TVR = 327.68. 261 * so with HZ = 100, TVR = 327.68.
262 */ 262 */
263#define OMAP_32K_TIMER_TICK_PERIOD ((32768 / HZ) - 1) 263#define OMAP_32K_TIMER_TICK_PERIOD ((32768 / HZ) - 1)
264#define MAX_SKIP_JIFFIES 25
265#define TIMER_32K_SYNCHRONIZED 0xfffbc410 264#define TIMER_32K_SYNCHRONIZED 0xfffbc410
266 265
267#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ 266#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
@@ -347,6 +346,42 @@ static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
347 return IRQ_HANDLED; 346 return IRQ_HANDLED;
348} 347}
349 348
349#ifdef CONFIG_NO_IDLE_HZ
350/*
351 * Programs the next timer interrupt needed. Called when dynamic tick is
352 * enabled, and to reprogram the ticks to skip from pm_idle. Note that
353 * we can keep the timer continuous, and don't need to set it to run in
354 * one-shot mode. This is because the timer will get reprogrammed again
355 * after next interrupt.
356 */
357void omap_32k_timer_reprogram(unsigned long next_tick)
358{
359 omap_32k_timer_start(JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1);
360}
361
362static struct irqaction omap_32k_timer_irq;
363extern struct timer_update_handler timer_update;
364
365static int omap_32k_timer_enable_dyn_tick(void)
366{
367 /* No need to reprogram timer, just use the next interrupt */
368 return 0;
369}
370
371static int omap_32k_timer_disable_dyn_tick(void)
372{
373 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
374 return 0;
375}
376
377static struct dyn_tick_timer omap_dyn_tick_timer = {
378 .enable = omap_32k_timer_enable_dyn_tick,
379 .disable = omap_32k_timer_disable_dyn_tick,
380 .reprogram = omap_32k_timer_reprogram,
381 .handler = omap_32k_timer_interrupt,
382};
383#endif /* CONFIG_NO_IDLE_HZ */
384
350static struct irqaction omap_32k_timer_irq = { 385static struct irqaction omap_32k_timer_irq = {
351 .name = "32KHz timer", 386 .name = "32KHz timer",
352 .flags = SA_INTERRUPT | SA_TIMER, 387 .flags = SA_INTERRUPT | SA_TIMER,
@@ -355,6 +390,11 @@ static struct irqaction omap_32k_timer_irq = {
355 390
356static __init void omap_init_32k_timer(void) 391static __init void omap_init_32k_timer(void)
357{ 392{
393
394#ifdef CONFIG_NO_IDLE_HZ
395 omap_timer.dyn_tick = &omap_dyn_tick_timer;
396#endif
397
358 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); 398 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
359 omap_timer.offset = omap_32k_timer_gettimeoffset; 399 omap_timer.offset = omap_32k_timer_gettimeoffset;
360 omap_32k_last_tick = omap_32k_sync_timer_read(); 400 omap_32k_last_tick = omap_32k_sync_timer_read();
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 534df0c6c770..d4d03d0daaec 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -154,6 +154,11 @@ config S3C2410_PM_CHECK_CHUNKSIZE
154 the CRC data block will take more memory, but wil identify any 154 the CRC data block will take more memory, but wil identify any
155 faults with better precision. 155 faults with better precision.
156 156
157config PM_SIMTEC
158 bool
159 depends on PM && (ARCH_BAST || MACH_VR1000)
160 default y
161
157config S3C2410_LOWLEVEL_UART_PORT 162config S3C2410_LOWLEVEL_UART_PORT
158 int "S3C2410 UART to use for low-level messages" 163 int "S3C2410 UART to use for low-level messages"
159 default 0 164 default 0
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 7c379aad5d62..f99b689e4392 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_S3C2410_DMA) += dma.o
18# Power Management support 18# Power Management support
19 19
20obj-$(CONFIG_PM) += pm.o sleep.o 20obj-$(CONFIG_PM) += pm.o sleep.o
21obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
21 22
22# S3C2440 support 23# S3C2440 support
23 24
diff --git a/arch/arm/mach-s3c2410/devs.c b/arch/arm/mach-s3c2410/devs.c
index 64792f678668..4664bd11adc1 100644
--- a/arch/arm/mach-s3c2410/devs.c
+++ b/arch/arm/mach-s3c2410/devs.c
@@ -96,8 +96,8 @@ struct platform_device s3c_device_lcd = {
96 .num_resources = ARRAY_SIZE(s3c_lcd_resource), 96 .num_resources = ARRAY_SIZE(s3c_lcd_resource),
97 .resource = s3c_lcd_resource, 97 .resource = s3c_lcd_resource,
98 .dev = { 98 .dev = {
99 .dma_mask = &s3c_device_lcd_dmamask, 99 .dma_mask = &s3c_device_lcd_dmamask,
100 .coherent_dma_mask = 0xffffffffUL 100 .coherent_dma_mask = 0xffffffffUL
101 } 101 }
102}; 102};
103 103
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index f3e970039b65..549bcb1f32c0 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -27,6 +27,7 @@
27 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA 27 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
28 * 14-Mar-2006 BJD Updated for __iomem changes 28 * 14-Mar-2006 BJD Updated for __iomem changes
29 * 22-Jun-2006 BJD Added DM9000 platform information 29 * 22-Jun-2006 BJD Added DM9000 platform information
30 * 28-Jun-2006 BJD Moved pm functionality out to common code
30*/ 31*/
31 32
32#include <linux/kernel.h> 33#include <linux/kernel.h>
@@ -67,7 +68,6 @@
67#include "devs.h" 68#include "devs.h"
68#include "cpu.h" 69#include "cpu.h"
69#include "usb-simtec.h" 70#include "usb-simtec.h"
70#include "pm.h"
71 71
72#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics" 72#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
73 73
@@ -405,44 +405,13 @@ void __init bast_map_io(void)
405 usb_simtec_init(); 405 usb_simtec_init();
406} 406}
407 407
408void __init bast_init_irq(void)
409{
410 s3c24xx_init_irq();
411}
412
413#ifdef CONFIG_PM
414
415/* bast_init_machine
416 *
417 * enable the power management functions for the EB2410ITX
418*/
419
420static __init void bast_init_machine(void)
421{
422 unsigned long gstatus4;
423
424 printk(KERN_INFO "BAST Power Manangement" COPYRIGHT "\n");
425
426 gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30;
427 gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28;
428 gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK);
429
430 __raw_writel(gstatus4, S3C2410_GSTATUS4);
431
432 s3c2410_pm_init();
433}
434
435#else
436#define bast_init_machine NULL
437#endif
438
439 408
440MACHINE_START(BAST, "Simtec-BAST") 409MACHINE_START(BAST, "Simtec-BAST")
441 MAINTAINER("Ben Dooks <ben@simtec.co.uk>") 410 MAINTAINER("Ben Dooks <ben@simtec.co.uk>")
442 BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, (u32)S3C24XX_VA_UART) 411 BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, (u32)S3C24XX_VA_UART)
443 BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100) 412 BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
444 MAPIO(bast_map_io) 413
445 INITIRQ(bast_init_irq) 414 .map_io = bast_map_io,
446 .init_machine = bast_init_machine, 415 .init_irq = s3c24xx_init_irq,
447 .timer = &s3c24xx_timer, 416 .timer = &s3c24xx_timer,
448MACHINE_END 417MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 76be074944a0..1db2855e3e56 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -371,16 +371,12 @@ void __init vr1000_map_io(void)
371 usb_simtec_init(); 371 usb_simtec_init();
372} 372}
373 373
374void __init vr1000_init_irq(void)
375{
376 s3c24xx_init_irq();
377}
378 374
379MACHINE_START(VR1000, "Thorcom-VR1000") 375MACHINE_START(VR1000, "Thorcom-VR1000")
380 MAINTAINER("Ben Dooks <ben@simtec.co.uk>") 376 MAINTAINER("Ben Dooks <ben@simtec.co.uk>")
381 BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, (u32)S3C24XX_VA_UART) 377 BOOT_MEM(S3C2410_SDRAM_PA, S3C2410_PA_UART, (u32)S3C24XX_VA_UART)
382 BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100) 378 BOOT_PARAMS(S3C2410_SDRAM_PA + 0x100)
383 MAPIO(vr1000_map_io) 379 .map_io = vr1000_map_io,
384 INITIRQ(vr1000_init_irq) 380 .init_irq = s3c24xx_init_irq,
385 .timer = &s3c24xx_timer, 381 .timer = &s3c24xx_timer,
386MACHINE_END 382MACHINE_END
diff --git a/arch/arm/mach-s3c2410/pm-simtec.c b/arch/arm/mach-s3c2410/pm-simtec.c
new file mode 100644
index 000000000000..2cb798832223
--- /dev/null
+++ b/arch/arm/mach-s3c2410/pm-simtec.c
@@ -0,0 +1,65 @@
1/* linux/arch/arm/mach-s3c2410/pm-simtec.c
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/
7 *
8 * Power Management helpers for Simtec S3C24XX implementations
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/device.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25
26#include <asm/hardware.h>
27#include <asm/io.h>
28
29#include <asm/arch/map.h>
30#include <asm/arch/regs-serial.h>
31#include <asm/arch/regs-gpio.h>
32#include <asm/arch/regs-mem.h>
33
34#include <asm/mach-types.h>
35
36#include "pm.h"
37
38#define COPYRIGHT ", (c) 2005 Simtec Electronics"
39
40/* pm_simtec_init
41 *
42 * enable the power management functions
43*/
44
45static __init int pm_simtec_init(void)
46{
47 unsigned long gstatus4;
48
49 /* check which machine we are running on */
50
51 if (!machine_is_bast() && !machine_is_vr1000())
52 return 0;
53
54 printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n");
55
56 gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30;
57 gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28;
58 gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK);
59
60 __raw_writel(gstatus4, S3C2410_GSTATUS4);
61
62 return s3c2410_pm_init();
63}
64
65arch_initcall(pm_simtec_init);
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 9d1f2253e987..f01c0f8a2bb3 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -33,6 +33,7 @@
33#include <asm/mach-types.h> 33#include <asm/mach-types.h>
34#include <asm/hardware/amba.h> 34#include <asm/hardware/amba.h>
35#include <asm/hardware/amba_clcd.h> 35#include <asm/hardware/amba_clcd.h>
36#include <asm/hardware/arm_timer.h>
36#include <asm/hardware/icst307.h> 37#include <asm/hardware/icst307.h>
37 38
38#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
@@ -788,38 +789,25 @@ void __init versatile_init(void)
788 */ 789 */
789#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) 790#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
790#if TIMER_INTERVAL >= 0x100000 791#if TIMER_INTERVAL >= 0x100000
791#define TIMER_RELOAD (TIMER_INTERVAL >> 8) /* Divide by 256 */ 792#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
792#define TIMER_CTRL 0x88 /* Enable, Clock / 256 */ 793#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
793#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) 794#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
794#elif TIMER_INTERVAL >= 0x10000 795#elif TIMER_INTERVAL >= 0x10000
795#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */ 796#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
796#define TIMER_CTRL 0x84 /* Enable, Clock / 16 */ 797#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
797#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) 798#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
798#else 799#else
799#define TIMER_RELOAD (TIMER_INTERVAL) 800#define TIMER_RELOAD (TIMER_INTERVAL)
800#define TIMER_CTRL 0x80 /* Enable */ 801#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
801#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) 802#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
802#endif 803#endif
803 804
804#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable */
805
806/*
807 * What does it look like?
808 */
809typedef struct TimerStruct {
810 unsigned long TimerLoad;
811 unsigned long TimerValue;
812 unsigned long TimerControl;
813 unsigned long TimerClear;
814} TimerStruct_t;
815
816/* 805/*
817 * Returns number of ms since last clock interrupt. Note that interrupts 806 * Returns number of ms since last clock interrupt. Note that interrupts
818 * will have been disabled by do_gettimeoffset() 807 * will have been disabled by do_gettimeoffset()
819 */ 808 */
820static unsigned long versatile_gettimeoffset(void) 809static unsigned long versatile_gettimeoffset(void)
821{ 810{
822 volatile TimerStruct_t *timer0 = (TimerStruct_t *)TIMER0_VA_BASE;
823 unsigned long ticks1, ticks2, status; 811 unsigned long ticks1, ticks2, status;
824 812
825 /* 813 /*
@@ -828,11 +816,11 @@ static unsigned long versatile_gettimeoffset(void)
828 * an interrupt. We get around this by ensuring that the 816 * an interrupt. We get around this by ensuring that the
829 * counter has not reloaded between our two reads. 817 * counter has not reloaded between our two reads.
830 */ 818 */
831 ticks2 = timer0->TimerValue & 0xffff; 819 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
832 do { 820 do {
833 ticks1 = ticks2; 821 ticks1 = ticks2;
834 status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS); 822 status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
835 ticks2 = timer0->TimerValue & 0xffff; 823 ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
836 } while (ticks2 > ticks1); 824 } while (ticks2 > ticks1);
837 825
838 /* 826 /*
@@ -859,12 +847,10 @@ static unsigned long versatile_gettimeoffset(void)
859 */ 847 */
860static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 848static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
861{ 849{
862 volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE;
863
864 write_seqlock(&xtime_lock); 850 write_seqlock(&xtime_lock);
865 851
866 // ...clear the interrupt 852 // ...clear the interrupt
867 timer0->TimerClear = 1; 853 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
868 854
869 timer_tick(regs); 855 timer_tick(regs);
870 856
@@ -884,31 +870,32 @@ static struct irqaction versatile_timer_irq = {
884 */ 870 */
885static void __init versatile_timer_init(void) 871static void __init versatile_timer_init(void)
886{ 872{
887 volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE; 873 u32 val;
888 volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE;
889 volatile TimerStruct_t *timer2 = (volatile TimerStruct_t *)TIMER2_VA_BASE;
890 volatile TimerStruct_t *timer3 = (volatile TimerStruct_t *)TIMER3_VA_BASE;
891 874
892 /* 875 /*
893 * set clock frequency: 876 * set clock frequency:
894 * VERSATILE_REFCLK is 32KHz 877 * VERSATILE_REFCLK is 32KHz
895 * VERSATILE_TIMCLK is 1MHz 878 * VERSATILE_TIMCLK is 1MHz
896 */ 879 */
897 *(volatile unsigned int *)IO_ADDRESS(VERSATILE_SCTL_BASE) |= 880 val = readl(IO_ADDRESS(VERSATILE_SCTL_BASE));
898 ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) | 881 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
899 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel)); 882 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
883 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
884 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
885 IO_ADDRESS(VERSATILE_SCTL_BASE));
900 886
901 /* 887 /*
902 * Initialise to a known state (all timers off) 888 * Initialise to a known state (all timers off)
903 */ 889 */
904 timer0->TimerControl = 0; 890 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
905 timer1->TimerControl = 0; 891 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
906 timer2->TimerControl = 0; 892 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
907 timer3->TimerControl = 0; 893 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
908 894
909 timer0->TimerLoad = TIMER_RELOAD; 895 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
910 timer0->TimerValue = TIMER_RELOAD; 896 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_VALUE);
911 timer0->TimerControl = TIMER_CTRL | 0x40 | TIMER_CTRL_IE; /* periodic + IE */ 897 writel(TIMER_DIVISOR | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC |
898 TIMER_CTRL_IE, TIMER0_VA_BASE + TIMER_CTRL);
912 899
913 /* 900 /*
914 * Make irqs happen for the system timer 901 * Make irqs happen for the system timer
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 6dcb23d64bf5..edffa47a4b2a 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -437,7 +437,7 @@ void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
437 memtable_init(mi); 437 memtable_init(mi);
438 if (mdesc->map_io) 438 if (mdesc->map_io)
439 mdesc->map_io(); 439 mdesc->map_io();
440 flush_tlb_all(); 440 local_flush_tlb_all();
441 441
442 /* 442 /*
443 * initialise the zones within each node 443 * initialise the zones within each node
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index 052ab443ec4e..c3bd503b43a2 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -682,7 +682,7 @@ void __init memtable_init(struct meminfo *mi)
682 } 682 }
683 683
684 flush_cache_all(); 684 flush_cache_all();
685 flush_tlb_all(); 685 local_flush_tlb_all();
686 686
687 top_pmd = pmd_off_k(0xffff0000); 687 top_pmd = pmd_off_k(0xffff0000);
688} 688}
diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h
index 55a02bc994a3..4b97950984e9 100644
--- a/arch/arm/vfp/vfp.h
+++ b/arch/arm/vfp/vfp.h
@@ -117,7 +117,13 @@ static inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m)
117 if (nh >= m) 117 if (nh >= m)
118 return ~0ULL; 118 return ~0ULL;
119 mh = m >> 32; 119 mh = m >> 32;
120 z = (mh << 32 <= nh) ? 0xffffffff00000000ULL : (nh / mh) << 32; 120 if (mh << 32 <= nh) {
121 z = 0xffffffff00000000ULL;
122 } else {
123 z = nh;
124 do_div(z, mh);
125 z <<= 32;
126 }
121 mul64to128(&termh, &terml, m, z); 127 mul64to128(&termh, &terml, m, z);
122 sub128(&remh, &reml, nh, nl, termh, terml); 128 sub128(&remh, &reml, nh, nl, termh, terml);
123 ml = m << 32; 129 ml = m << 32;
@@ -126,7 +132,12 @@ static inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m)
126 add128(&remh, &reml, remh, reml, mh, ml); 132 add128(&remh, &reml, remh, reml, mh, ml);
127 } 133 }
128 remh = (remh << 32) | (reml >> 32); 134 remh = (remh << 32) | (reml >> 32);
129 z |= (mh << 32 <= remh) ? 0xffffffff : remh / mh; 135 if (mh << 32 <= remh) {
136 z |= 0xffffffff;
137 } else {
138 do_div(remh, mh);
139 z |= remh;
140 }
130 return z; 141 return z;
131} 142}
132 143
diff --git a/arch/arm/vfp/vfpdouble.c b/arch/arm/vfp/vfpdouble.c
index fa3053e84db5..b801cd66b6ea 100644
--- a/arch/arm/vfp/vfpdouble.c
+++ b/arch/arm/vfp/vfpdouble.c
@@ -32,6 +32,8 @@
32 */ 32 */
33#include <linux/kernel.h> 33#include <linux/kernel.h>
34#include <linux/bitops.h> 34#include <linux/bitops.h>
35
36#include <asm/div64.h>
35#include <asm/ptrace.h> 37#include <asm/ptrace.h>
36#include <asm/vfp.h> 38#include <asm/vfp.h>
37 39
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 3aeedd2afc70..22f3da4e0829 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -89,7 +89,7 @@ void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs)
89 current->thread.error_code = 0; 89 current->thread.error_code = 0;
90 current->thread.trap_no = 6; 90 current->thread.trap_no = 6;
91 91
92 force_sig_info(SIGFPE, &info, current); 92 send_sig_info(SIGFPE, &info, current);
93} 93}
94 94
95static void vfp_panic(char *reason) 95static void vfp_panic(char *reason)
diff --git a/arch/arm/vfp/vfpsingle.c b/arch/arm/vfp/vfpsingle.c
index 6849fe35cb2e..14dd696ddeb1 100644
--- a/arch/arm/vfp/vfpsingle.c
+++ b/arch/arm/vfp/vfpsingle.c
@@ -32,6 +32,8 @@
32 */ 32 */
33#include <linux/kernel.h> 33#include <linux/kernel.h>
34#include <linux/bitops.h> 34#include <linux/bitops.h>
35
36#include <asm/div64.h>
35#include <asm/ptrace.h> 37#include <asm/ptrace.h>
36#include <asm/vfp.h> 38#include <asm/vfp.h>
37 39
@@ -303,7 +305,11 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand)
303 if (z <= a) 305 if (z <= a)
304 return (s32)a >> 1; 306 return (s32)a >> 1;
305 } 307 }
306 return (u32)(((u64)a << 31) / z) + (z >> 1); 308 {
309 u64 v = (u64)a << 31;
310 do_div(v, z);
311 return v + (z >> 1);
312 }
307} 313}
308 314
309static u32 vfp_single_fsqrt(int sd, int unused, s32 m, u32 fpscr) 315static u32 vfp_single_fsqrt(int sd, int unused, s32 m, u32 fpscr)
@@ -1107,7 +1113,11 @@ static u32 vfp_single_fdiv(int sd, int sn, s32 m, u32 fpscr)
1107 vsn.significand >>= 1; 1113 vsn.significand >>= 1;
1108 vsd.exponent++; 1114 vsd.exponent++;
1109 } 1115 }
1110 vsd.significand = ((u64)vsn.significand << 32) / vsm.significand; 1116 {
1117 u64 significand = (u64)vsn.significand << 32;
1118 do_div(significand, vsm.significand);
1119 vsd.significand = significand;
1120 }
1111 if ((vsd.significand & 0x3f) == 0) 1121 if ((vsd.significand & 0x3f) == 0)
1112 vsd.significand |= ((u64)vsm.significand * vsd.significand != (u64)vsn.significand << 32); 1122 vsd.significand |= ((u64)vsm.significand * vsd.significand != (u64)vsn.significand << 32);
1113 1123
diff --git a/arch/ia64/configs/sn2_defconfig b/arch/ia64/configs/sn2_defconfig
index 487d2e36b0a6..c05613980300 100644
--- a/arch/ia64/configs/sn2_defconfig
+++ b/arch/ia64/configs/sn2_defconfig
@@ -99,7 +99,7 @@ CONFIG_ACPI_DEALLOCATE_IRQ=y
99# Firmware Drivers 99# Firmware Drivers
100# 100#
101CONFIG_EFI_VARS=y 101CONFIG_EFI_VARS=y
102# CONFIG_EFI_PCDP is not set 102CONFIG_EFI_PCDP=y
103CONFIG_BINFMT_ELF=y 103CONFIG_BINFMT_ELF=y
104# CONFIG_BINFMT_MISC is not set 104# CONFIG_BINFMT_MISC is not set
105 105
@@ -650,7 +650,7 @@ CONFIG_MMTIMER=y
650# 650#
651# Console display driver support 651# Console display driver support
652# 652#
653# CONFIG_VGA_CONSOLE is not set 653CONFIG_VGA_CONSOLE=y
654CONFIG_DUMMY_CONSOLE=y 654CONFIG_DUMMY_CONSOLE=y
655 655
656# 656#
diff --git a/arch/ia64/configs/tiger_defconfig b/arch/ia64/configs/tiger_defconfig
index 47f45341ac62..73454eee26f1 100644
--- a/arch/ia64/configs/tiger_defconfig
+++ b/arch/ia64/configs/tiger_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-20050621 3# Linux kernel version: 2.6.13-rc1-20050629
4# Tue Jun 21 14:03:24 2005 4# Wed Jun 29 15:28:12 2005
5# 5#
6 6
7# 7#
@@ -80,18 +80,29 @@ CONFIG_MCKINLEY=y
80# CONFIG_IA64_PAGE_SIZE_8KB is not set 80# CONFIG_IA64_PAGE_SIZE_8KB is not set
81CONFIG_IA64_PAGE_SIZE_16KB=y 81CONFIG_IA64_PAGE_SIZE_16KB=y
82# CONFIG_IA64_PAGE_SIZE_64KB is not set 82# CONFIG_IA64_PAGE_SIZE_64KB is not set
83# CONFIG_HZ_100 is not set
84CONFIG_HZ_250=y
85# CONFIG_HZ_1000 is not set
86CONFIG_HZ=250
83CONFIG_IA64_L1_CACHE_SHIFT=7 87CONFIG_IA64_L1_CACHE_SHIFT=7
84# CONFIG_NUMA is not set 88# CONFIG_NUMA is not set
85CONFIG_VIRTUAL_MEM_MAP=y 89CONFIG_VIRTUAL_MEM_MAP=y
86CONFIG_HOLES_IN_ZONE=y 90CONFIG_HOLES_IN_ZONE=y
87CONFIG_IA64_CYCLONE=y 91CONFIG_IA64_CYCLONE=y
88CONFIG_IOSAPIC=y 92CONFIG_IOSAPIC=y
93# CONFIG_IA64_SGI_SN_XP is not set
89CONFIG_FORCE_MAX_ZONEORDER=18 94CONFIG_FORCE_MAX_ZONEORDER=18
90CONFIG_SMP=y 95CONFIG_SMP=y
91CONFIG_NR_CPUS=4 96CONFIG_NR_CPUS=4
92CONFIG_HOTPLUG_CPU=y 97CONFIG_HOTPLUG_CPU=y
93# CONFIG_SCHED_SMT is not set 98# CONFIG_SCHED_SMT is not set
94# CONFIG_PREEMPT is not set 99# CONFIG_PREEMPT is not set
100CONFIG_SELECT_MEMORY_MODEL=y
101CONFIG_FLATMEM_MANUAL=y
102# CONFIG_DISCONTIGMEM_MANUAL is not set
103# CONFIG_SPARSEMEM_MANUAL is not set
104CONFIG_FLATMEM=y
105CONFIG_FLAT_NODE_MEM_MAP=y
95CONFIG_HAVE_DEC_LOCK=y 106CONFIG_HAVE_DEC_LOCK=y
96CONFIG_IA32_SUPPORT=y 107CONFIG_IA32_SUPPORT=y
97CONFIG_COMPAT=y 108CONFIG_COMPAT=y
@@ -257,6 +268,7 @@ CONFIG_BLK_DEV_CMD64X=y
257# CONFIG_BLK_DEV_HPT366 is not set 268# CONFIG_BLK_DEV_HPT366 is not set
258# CONFIG_BLK_DEV_SC1200 is not set 269# CONFIG_BLK_DEV_SC1200 is not set
259CONFIG_BLK_DEV_PIIX=y 270CONFIG_BLK_DEV_PIIX=y
271# CONFIG_BLK_DEV_IT821X is not set
260# CONFIG_BLK_DEV_NS87415 is not set 272# CONFIG_BLK_DEV_NS87415 is not set
261# CONFIG_BLK_DEV_PDC202XX_OLD is not set 273# CONFIG_BLK_DEV_PDC202XX_OLD is not set
262# CONFIG_BLK_DEV_PDC202XX_NEW is not set 274# CONFIG_BLK_DEV_PDC202XX_NEW is not set
@@ -395,6 +407,7 @@ CONFIG_UNIX=y
395CONFIG_INET=y 407CONFIG_INET=y
396CONFIG_IP_MULTICAST=y 408CONFIG_IP_MULTICAST=y
397# CONFIG_IP_ADVANCED_ROUTER is not set 409# CONFIG_IP_ADVANCED_ROUTER is not set
410CONFIG_IP_FIB_HASH=y
398# CONFIG_IP_PNP is not set 411# CONFIG_IP_PNP is not set
399# CONFIG_NET_IPIP is not set 412# CONFIG_NET_IPIP is not set
400# CONFIG_NET_IPGRE is not set 413# CONFIG_NET_IPGRE is not set
@@ -407,6 +420,8 @@ CONFIG_SYN_COOKIES=y
407# CONFIG_INET_TUNNEL is not set 420# CONFIG_INET_TUNNEL is not set
408CONFIG_IP_TCPDIAG=y 421CONFIG_IP_TCPDIAG=y
409# CONFIG_IP_TCPDIAG_IPV6 is not set 422# CONFIG_IP_TCPDIAG_IPV6 is not set
423# CONFIG_TCP_CONG_ADVANCED is not set
424CONFIG_TCP_CONG_BIC=y
410# CONFIG_IPV6 is not set 425# CONFIG_IPV6 is not set
411# CONFIG_NETFILTER is not set 426# CONFIG_NETFILTER is not set
412 427
@@ -598,9 +613,7 @@ CONFIG_GAMEPORT=m
598# CONFIG_GAMEPORT_NS558 is not set 613# CONFIG_GAMEPORT_NS558 is not set
599# CONFIG_GAMEPORT_L4 is not set 614# CONFIG_GAMEPORT_L4 is not set
600# CONFIG_GAMEPORT_EMU10K1 is not set 615# CONFIG_GAMEPORT_EMU10K1 is not set
601# CONFIG_GAMEPORT_VORTEX is not set
602# CONFIG_GAMEPORT_FM801 is not set 616# CONFIG_GAMEPORT_FM801 is not set
603# CONFIG_GAMEPORT_CS461X is not set
604 617
605# 618#
606# Character devices 619# Character devices
@@ -629,7 +642,6 @@ CONFIG_SERIAL_8250_NR_UARTS=6
629CONFIG_SERIAL_8250_EXTENDED=y 642CONFIG_SERIAL_8250_EXTENDED=y
630CONFIG_SERIAL_8250_SHARE_IRQ=y 643CONFIG_SERIAL_8250_SHARE_IRQ=y
631# CONFIG_SERIAL_8250_DETECT_IRQ is not set 644# CONFIG_SERIAL_8250_DETECT_IRQ is not set
632# CONFIG_SERIAL_8250_MULTIPORT is not set
633# CONFIG_SERIAL_8250_RSA is not set 645# CONFIG_SERIAL_8250_RSA is not set
634 646
635# 647#
@@ -743,6 +755,7 @@ CONFIG_USB_DEVICEFS=y
743CONFIG_USB_EHCI_HCD=m 755CONFIG_USB_EHCI_HCD=m
744# CONFIG_USB_EHCI_SPLIT_ISO is not set 756# CONFIG_USB_EHCI_SPLIT_ISO is not set
745# CONFIG_USB_EHCI_ROOT_HUB_TT is not set 757# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
758# CONFIG_USB_ISP116X_HCD is not set
746CONFIG_USB_OHCI_HCD=m 759CONFIG_USB_OHCI_HCD=m
747# CONFIG_USB_OHCI_BIG_ENDIAN is not set 760# CONFIG_USB_OHCI_BIG_ENDIAN is not set
748CONFIG_USB_OHCI_LITTLE_ENDIAN=y 761CONFIG_USB_OHCI_LITTLE_ENDIAN=y
@@ -779,9 +792,11 @@ CONFIG_USB_HIDINPUT=y
779# CONFIG_USB_HIDDEV is not set 792# CONFIG_USB_HIDDEV is not set
780# CONFIG_USB_AIPTEK is not set 793# CONFIG_USB_AIPTEK is not set
781# CONFIG_USB_WACOM is not set 794# CONFIG_USB_WACOM is not set
795# CONFIG_USB_ACECAD is not set
782# CONFIG_USB_KBTAB is not set 796# CONFIG_USB_KBTAB is not set
783# CONFIG_USB_POWERMATE is not set 797# CONFIG_USB_POWERMATE is not set
784# CONFIG_USB_MTOUCH is not set 798# CONFIG_USB_MTOUCH is not set
799# CONFIG_USB_ITMTOUCH is not set
785# CONFIG_USB_EGALAX is not set 800# CONFIG_USB_EGALAX is not set
786# CONFIG_USB_XPAD is not set 801# CONFIG_USB_XPAD is not set
787# CONFIG_USB_ATI_REMOTE is not set 802# CONFIG_USB_ATI_REMOTE is not set
@@ -838,7 +853,7 @@ CONFIG_USB_HIDINPUT=y
838# CONFIG_USB_TEST is not set 853# CONFIG_USB_TEST is not set
839 854
840# 855#
841# USB ATM/DSL drivers 856# USB DSL modem support
842# 857#
843 858
844# 859#
@@ -857,12 +872,17 @@ CONFIG_USB_HIDINPUT=y
857# CONFIG_INFINIBAND is not set 872# CONFIG_INFINIBAND is not set
858 873
859# 874#
875# SN Devices
876#
877
878#
860# File systems 879# File systems
861# 880#
862CONFIG_EXT2_FS=y 881CONFIG_EXT2_FS=y
863CONFIG_EXT2_FS_XATTR=y 882CONFIG_EXT2_FS_XATTR=y
864CONFIG_EXT2_FS_POSIX_ACL=y 883CONFIG_EXT2_FS_POSIX_ACL=y
865CONFIG_EXT2_FS_SECURITY=y 884CONFIG_EXT2_FS_SECURITY=y
885# CONFIG_EXT2_FS_XIP is not set
866CONFIG_EXT3_FS=y 886CONFIG_EXT3_FS=y
867CONFIG_EXT3_FS_XATTR=y 887CONFIG_EXT3_FS_XATTR=y
868CONFIG_EXT3_FS_POSIX_ACL=y 888CONFIG_EXT3_FS_POSIX_ACL=y
@@ -922,7 +942,6 @@ CONFIG_NTFS_FS=m
922CONFIG_PROC_FS=y 942CONFIG_PROC_FS=y
923CONFIG_PROC_KCORE=y 943CONFIG_PROC_KCORE=y
924CONFIG_SYSFS=y 944CONFIG_SYSFS=y
925# CONFIG_DEVFS_FS is not set
926# CONFIG_DEVPTS_FS_XATTR is not set 945# CONFIG_DEVPTS_FS_XATTR is not set
927CONFIG_TMPFS=y 946CONFIG_TMPFS=y
928CONFIG_TMPFS_XATTR=y 947CONFIG_TMPFS_XATTR=y
@@ -953,15 +972,18 @@ CONFIG_RAMFS=y
953# 972#
954CONFIG_NFS_FS=m 973CONFIG_NFS_FS=m
955CONFIG_NFS_V3=y 974CONFIG_NFS_V3=y
975# CONFIG_NFS_V3_ACL is not set
956CONFIG_NFS_V4=y 976CONFIG_NFS_V4=y
957CONFIG_NFS_DIRECTIO=y 977CONFIG_NFS_DIRECTIO=y
958CONFIG_NFSD=m 978CONFIG_NFSD=m
959CONFIG_NFSD_V3=y 979CONFIG_NFSD_V3=y
980# CONFIG_NFSD_V3_ACL is not set
960CONFIG_NFSD_V4=y 981CONFIG_NFSD_V4=y
961CONFIG_NFSD_TCP=y 982CONFIG_NFSD_TCP=y
962CONFIG_LOCKD=m 983CONFIG_LOCKD=m
963CONFIG_LOCKD_V4=y 984CONFIG_LOCKD_V4=y
964CONFIG_EXPORTFS=y 985CONFIG_EXPORTFS=y
986CONFIG_NFS_COMMON=y
965CONFIG_SUNRPC=m 987CONFIG_SUNRPC=m
966CONFIG_SUNRPC_GSS=m 988CONFIG_SUNRPC_GSS=m
967CONFIG_RPCSEC_GSS_KRB5=m 989CONFIG_RPCSEC_GSS_KRB5=m
@@ -1069,6 +1091,7 @@ CONFIG_LOG_BUF_SHIFT=20
1069# CONFIG_DEBUG_KOBJECT is not set 1091# CONFIG_DEBUG_KOBJECT is not set
1070# CONFIG_DEBUG_INFO is not set 1092# CONFIG_DEBUG_INFO is not set
1071# CONFIG_DEBUG_FS is not set 1093# CONFIG_DEBUG_FS is not set
1094# CONFIG_KPROBES is not set
1072CONFIG_IA64_GRANULE_16MB=y 1095CONFIG_IA64_GRANULE_16MB=y
1073# CONFIG_IA64_GRANULE_64MB is not set 1096# CONFIG_IA64_GRANULE_64MB is not set
1074# CONFIG_IA64_PRINT_HAZARDS is not set 1097# CONFIG_IA64_PRINT_HAZARDS is not set
@@ -1090,7 +1113,7 @@ CONFIG_CRYPTO=y
1090# CONFIG_CRYPTO_HMAC is not set 1113# CONFIG_CRYPTO_HMAC is not set
1091# CONFIG_CRYPTO_NULL is not set 1114# CONFIG_CRYPTO_NULL is not set
1092# CONFIG_CRYPTO_MD4 is not set 1115# CONFIG_CRYPTO_MD4 is not set
1093CONFIG_CRYPTO_MD5=m 1116CONFIG_CRYPTO_MD5=y
1094# CONFIG_CRYPTO_SHA1 is not set 1117# CONFIG_CRYPTO_SHA1 is not set
1095# CONFIG_CRYPTO_SHA256 is not set 1118# CONFIG_CRYPTO_SHA256 is not set
1096# CONFIG_CRYPTO_SHA512 is not set 1119# CONFIG_CRYPTO_SHA512 is not set
diff --git a/arch/ia64/configs/zx1_defconfig b/arch/ia64/configs/zx1_defconfig
index 21d6f9bab5e9..b7755e4436d2 100644
--- a/arch/ia64/configs/zx1_defconfig
+++ b/arch/ia64/configs/zx1_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.10 3# Linux kernel version: 2.6.13-rc1-20050629
4# Wed Dec 29 09:05:48 2004 4# Wed Jun 29 15:31:11 2005
5# 5#
6 6
7# 7#
@@ -12,6 +12,7 @@ CONFIG_EXPERIMENTAL=y
12CONFIG_BROKEN=y 12CONFIG_BROKEN=y
13CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_LOCK_KERNEL=y 14CONFIG_LOCK_KERNEL=y
15CONFIG_INIT_ENV_ARG_LIMIT=32
15 16
16# 17#
17# General setup 18# General setup
@@ -24,23 +25,26 @@ CONFIG_BSD_PROCESS_ACCT=y
24# CONFIG_BSD_PROCESS_ACCT_V3 is not set 25# CONFIG_BSD_PROCESS_ACCT_V3 is not set
25CONFIG_SYSCTL=y 26CONFIG_SYSCTL=y
26# CONFIG_AUDIT is not set 27# CONFIG_AUDIT is not set
27CONFIG_LOG_BUF_SHIFT=17
28CONFIG_HOTPLUG=y 28CONFIG_HOTPLUG=y
29CONFIG_KOBJECT_UEVENT=y 29CONFIG_KOBJECT_UEVENT=y
30# CONFIG_IKCONFIG is not set 30# CONFIG_IKCONFIG is not set
31# CONFIG_CPUSETS is not set
31# CONFIG_EMBEDDED is not set 32# CONFIG_EMBEDDED is not set
32CONFIG_KALLSYMS=y 33CONFIG_KALLSYMS=y
33# CONFIG_KALLSYMS_ALL is not set 34# CONFIG_KALLSYMS_ALL is not set
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 35# CONFIG_KALLSYMS_EXTRA_PASS is not set
36CONFIG_PRINTK=y
37CONFIG_BUG=y
38CONFIG_BASE_FULL=y
35CONFIG_FUTEX=y 39CONFIG_FUTEX=y
36CONFIG_EPOLL=y 40CONFIG_EPOLL=y
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
38CONFIG_SHMEM=y 41CONFIG_SHMEM=y
39CONFIG_CC_ALIGN_FUNCTIONS=0 42CONFIG_CC_ALIGN_FUNCTIONS=0
40CONFIG_CC_ALIGN_LABELS=0 43CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 44CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 45CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 46# CONFIG_TINY_SHMEM is not set
47CONFIG_BASE_SMALL=0
44 48
45# 49#
46# Loadable module support 50# Loadable module support
@@ -59,12 +63,15 @@ CONFIG_IA64=y
59CONFIG_64BIT=y 63CONFIG_64BIT=y
60CONFIG_MMU=y 64CONFIG_MMU=y
61CONFIG_RWSEM_XCHGADD_ALGORITHM=y 65CONFIG_RWSEM_XCHGADD_ALGORITHM=y
66CONFIG_GENERIC_CALIBRATE_DELAY=y
62CONFIG_TIME_INTERPOLATION=y 67CONFIG_TIME_INTERPOLATION=y
63CONFIG_EFI=y 68CONFIG_EFI=y
64CONFIG_GENERIC_IOMAP=y 69CONFIG_GENERIC_IOMAP=y
70CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
65# CONFIG_IA64_GENERIC is not set 71# CONFIG_IA64_GENERIC is not set
66# CONFIG_IA64_DIG is not set 72# CONFIG_IA64_DIG is not set
67CONFIG_IA64_HP_ZX1=y 73CONFIG_IA64_HP_ZX1=y
74# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
68# CONFIG_IA64_SGI_SN2 is not set 75# CONFIG_IA64_SGI_SN2 is not set
69# CONFIG_IA64_HP_SIM is not set 76# CONFIG_IA64_HP_SIM is not set
70# CONFIG_ITANIUM is not set 77# CONFIG_ITANIUM is not set
@@ -73,22 +80,36 @@ CONFIG_MCKINLEY=y
73# CONFIG_IA64_PAGE_SIZE_8KB is not set 80# CONFIG_IA64_PAGE_SIZE_8KB is not set
74CONFIG_IA64_PAGE_SIZE_16KB=y 81CONFIG_IA64_PAGE_SIZE_16KB=y
75# CONFIG_IA64_PAGE_SIZE_64KB is not set 82# CONFIG_IA64_PAGE_SIZE_64KB is not set
83# CONFIG_HZ_100 is not set
84CONFIG_HZ_250=y
85# CONFIG_HZ_1000 is not set
86CONFIG_HZ=250
76CONFIG_IA64_L1_CACHE_SHIFT=7 87CONFIG_IA64_L1_CACHE_SHIFT=7
77# CONFIG_NUMA is not set 88# CONFIG_NUMA is not set
78CONFIG_VIRTUAL_MEM_MAP=y 89CONFIG_VIRTUAL_MEM_MAP=y
90CONFIG_HOLES_IN_ZONE=y
79# CONFIG_IA64_CYCLONE is not set 91# CONFIG_IA64_CYCLONE is not set
80CONFIG_IOSAPIC=y 92CONFIG_IOSAPIC=y
93# CONFIG_IA64_SGI_SN_XP is not set
81CONFIG_FORCE_MAX_ZONEORDER=18 94CONFIG_FORCE_MAX_ZONEORDER=18
82CONFIG_SMP=y 95CONFIG_SMP=y
83CONFIG_NR_CPUS=16 96CONFIG_NR_CPUS=16
84# CONFIG_HOTPLUG_CPU is not set 97# CONFIG_HOTPLUG_CPU is not set
98# CONFIG_SCHED_SMT is not set
85# CONFIG_PREEMPT is not set 99# CONFIG_PREEMPT is not set
100CONFIG_SELECT_MEMORY_MODEL=y
101CONFIG_FLATMEM_MANUAL=y
102# CONFIG_DISCONTIGMEM_MANUAL is not set
103# CONFIG_SPARSEMEM_MANUAL is not set
104CONFIG_FLATMEM=y
105CONFIG_FLAT_NODE_MEM_MAP=y
86CONFIG_HAVE_DEC_LOCK=y 106CONFIG_HAVE_DEC_LOCK=y
87CONFIG_IA32_SUPPORT=y 107CONFIG_IA32_SUPPORT=y
88CONFIG_COMPAT=y 108CONFIG_COMPAT=y
89CONFIG_IA64_MCA_RECOVERY=y 109CONFIG_IA64_MCA_RECOVERY=y
90CONFIG_PERFMON=y 110CONFIG_PERFMON=y
91CONFIG_IA64_PALINFO=y 111CONFIG_IA64_PALINFO=y
112CONFIG_ACPI_DEALLOCATE_IRQ=y
92 113
93# 114#
94# Firmware Drivers 115# Firmware Drivers
@@ -120,6 +141,7 @@ CONFIG_ACPI_BUS=y
120CONFIG_ACPI_POWER=y 141CONFIG_ACPI_POWER=y
121CONFIG_ACPI_PCI=y 142CONFIG_ACPI_PCI=y
122CONFIG_ACPI_SYSTEM=y 143CONFIG_ACPI_SYSTEM=y
144# CONFIG_ACPI_CONTAINER is not set
123 145
124# 146#
125# Bus options (PCI, PCMCIA) 147# Bus options (PCI, PCMCIA)
@@ -129,6 +151,7 @@ CONFIG_PCI_DOMAINS=y
129# CONFIG_PCI_MSI is not set 151# CONFIG_PCI_MSI is not set
130CONFIG_PCI_LEGACY_PROC=y 152CONFIG_PCI_LEGACY_PROC=y
131CONFIG_PCI_NAMES=y 153CONFIG_PCI_NAMES=y
154# CONFIG_PCI_DEBUG is not set
132 155
133# 156#
134# PCI Hotplug Support 157# PCI Hotplug Support
@@ -138,7 +161,6 @@ CONFIG_HOTPLUG_PCI=y
138CONFIG_HOTPLUG_PCI_ACPI=y 161CONFIG_HOTPLUG_PCI_ACPI=y
139# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set 162# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
140# CONFIG_HOTPLUG_PCI_CPCI is not set 163# CONFIG_HOTPLUG_PCI_CPCI is not set
141# CONFIG_HOTPLUG_PCI_PCIE is not set
142# CONFIG_HOTPLUG_PCI_SHPC is not set 164# CONFIG_HOTPLUG_PCI_SHPC is not set
143 165
144# 166#
@@ -147,10 +169,6 @@ CONFIG_HOTPLUG_PCI_ACPI=y
147# CONFIG_PCCARD is not set 169# CONFIG_PCCARD is not set
148 170
149# 171#
150# PC-card bridges
151#
152
153#
154# Device Drivers 172# Device Drivers
155# 173#
156 174
@@ -184,6 +202,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
184# CONFIG_BLK_CPQ_CISS_DA is not set 202# CONFIG_BLK_CPQ_CISS_DA is not set
185# CONFIG_BLK_DEV_DAC960 is not set 203# CONFIG_BLK_DEV_DAC960 is not set
186# CONFIG_BLK_DEV_UMEM is not set 204# CONFIG_BLK_DEV_UMEM is not set
205# CONFIG_BLK_DEV_COW_COMMON is not set
187CONFIG_BLK_DEV_LOOP=y 206CONFIG_BLK_DEV_LOOP=y
188# CONFIG_BLK_DEV_CRYPTOLOOP is not set 207# CONFIG_BLK_DEV_CRYPTOLOOP is not set
189# CONFIG_BLK_DEV_NBD is not set 208# CONFIG_BLK_DEV_NBD is not set
@@ -203,6 +222,7 @@ CONFIG_IOSCHED_NOOP=y
203CONFIG_IOSCHED_AS=y 222CONFIG_IOSCHED_AS=y
204CONFIG_IOSCHED_DEADLINE=y 223CONFIG_IOSCHED_DEADLINE=y
205CONFIG_IOSCHED_CFQ=y 224CONFIG_IOSCHED_CFQ=y
225# CONFIG_ATA_OVER_ETH is not set
206 226
207# 227#
208# ATA/ATAPI/MFM/RLL support 228# ATA/ATAPI/MFM/RLL support
@@ -246,6 +266,7 @@ CONFIG_BLK_DEV_CMD64X=y
246# CONFIG_BLK_DEV_HPT366 is not set 266# CONFIG_BLK_DEV_HPT366 is not set
247# CONFIG_BLK_DEV_SC1200 is not set 267# CONFIG_BLK_DEV_SC1200 is not set
248# CONFIG_BLK_DEV_PIIX is not set 268# CONFIG_BLK_DEV_PIIX is not set
269# CONFIG_BLK_DEV_IT821X is not set
249# CONFIG_BLK_DEV_NS87415 is not set 270# CONFIG_BLK_DEV_NS87415 is not set
250# CONFIG_BLK_DEV_PDC202XX_OLD is not set 271# CONFIG_BLK_DEV_PDC202XX_OLD is not set
251# CONFIG_BLK_DEV_PDC202XX_NEW is not set 272# CONFIG_BLK_DEV_PDC202XX_NEW is not set
@@ -275,6 +296,7 @@ CONFIG_CHR_DEV_OSST=y
275CONFIG_BLK_DEV_SR=y 296CONFIG_BLK_DEV_SR=y
276CONFIG_BLK_DEV_SR_VENDOR=y 297CONFIG_BLK_DEV_SR_VENDOR=y
277CONFIG_CHR_DEV_SG=y 298CONFIG_CHR_DEV_SG=y
299# CONFIG_CHR_DEV_SCH is not set
278 300
279# 301#
280# Some SCSI devices (e.g. CD jukebox) support multiple LUNs 302# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -288,6 +310,7 @@ CONFIG_SCSI_LOGGING=y
288# 310#
289CONFIG_SCSI_SPI_ATTRS=y 311CONFIG_SCSI_SPI_ATTRS=y
290# CONFIG_SCSI_FC_ATTRS is not set 312# CONFIG_SCSI_FC_ATTRS is not set
313# CONFIG_SCSI_ISCSI_ATTRS is not set
291 314
292# 315#
293# SCSI low-level drivers 316# SCSI low-level drivers
@@ -303,13 +326,10 @@ CONFIG_SCSI_SPI_ATTRS=y
303# CONFIG_MEGARAID_NEWGEN is not set 326# CONFIG_MEGARAID_NEWGEN is not set
304# CONFIG_MEGARAID_LEGACY is not set 327# CONFIG_MEGARAID_LEGACY is not set
305# CONFIG_SCSI_SATA is not set 328# CONFIG_SCSI_SATA is not set
306# CONFIG_SCSI_BUSLOGIC is not set
307# CONFIG_SCSI_CPQFCTS is not set 329# CONFIG_SCSI_CPQFCTS is not set
308# CONFIG_SCSI_DMX3191D is not set 330# CONFIG_SCSI_DMX3191D is not set
309# CONFIG_SCSI_EATA is not set
310# CONFIG_SCSI_EATA_PIO is not set 331# CONFIG_SCSI_EATA_PIO is not set
311# CONFIG_SCSI_FUTURE_DOMAIN is not set 332# CONFIG_SCSI_FUTURE_DOMAIN is not set
312# CONFIG_SCSI_GDTH is not set
313# CONFIG_SCSI_IPS is not set 333# CONFIG_SCSI_IPS is not set
314# CONFIG_SCSI_INITIO is not set 334# CONFIG_SCSI_INITIO is not set
315# CONFIG_SCSI_INIA100 is not set 335# CONFIG_SCSI_INIA100 is not set
@@ -319,8 +339,6 @@ CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
319CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 339CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
320# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set 340# CONFIG_SCSI_SYM53C8XX_IOMAPPED is not set
321# CONFIG_SCSI_IPR is not set 341# CONFIG_SCSI_IPR is not set
322# CONFIG_SCSI_PCI2000 is not set
323# CONFIG_SCSI_PCI2220I is not set
324# CONFIG_SCSI_QLOGIC_ISP is not set 342# CONFIG_SCSI_QLOGIC_ISP is not set
325# CONFIG_SCSI_QLOGIC_FC is not set 343# CONFIG_SCSI_QLOGIC_FC is not set
326CONFIG_SCSI_QLOGIC_1280=y 344CONFIG_SCSI_QLOGIC_1280=y
@@ -331,7 +349,7 @@ CONFIG_SCSI_QLA2XXX=y
331# CONFIG_SCSI_QLA2300 is not set 349# CONFIG_SCSI_QLA2300 is not set
332# CONFIG_SCSI_QLA2322 is not set 350# CONFIG_SCSI_QLA2322 is not set
333# CONFIG_SCSI_QLA6312 is not set 351# CONFIG_SCSI_QLA6312 is not set
334# CONFIG_SCSI_QLA6322 is not set 352# CONFIG_SCSI_LPFC is not set
335# CONFIG_SCSI_DC395x is not set 353# CONFIG_SCSI_DC395x is not set
336# CONFIG_SCSI_DC390T is not set 354# CONFIG_SCSI_DC390T is not set
337# CONFIG_SCSI_DEBUG is not set 355# CONFIG_SCSI_DEBUG is not set
@@ -344,9 +362,9 @@ CONFIG_SCSI_QLA2XXX=y
344# 362#
345# Fusion MPT device support 363# Fusion MPT device support
346# 364#
347CONFIG_FUSION=y 365# CONFIG_FUSION is not set
348CONFIG_FUSION_MAX_SGE=40 366# CONFIG_FUSION_SPI is not set
349# CONFIG_FUSION_CTL is not set 367# CONFIG_FUSION_FC is not set
350 368
351# 369#
352# IEEE 1394 (FireWire) support 370# IEEE 1394 (FireWire) support
@@ -368,12 +386,12 @@ CONFIG_NET=y
368# 386#
369CONFIG_PACKET=y 387CONFIG_PACKET=y
370# CONFIG_PACKET_MMAP is not set 388# CONFIG_PACKET_MMAP is not set
371# CONFIG_NETLINK_DEV is not set
372CONFIG_UNIX=y 389CONFIG_UNIX=y
373# CONFIG_NET_KEY is not set 390# CONFIG_NET_KEY is not set
374CONFIG_INET=y 391CONFIG_INET=y
375CONFIG_IP_MULTICAST=y 392CONFIG_IP_MULTICAST=y
376# CONFIG_IP_ADVANCED_ROUTER is not set 393# CONFIG_IP_ADVANCED_ROUTER is not set
394CONFIG_IP_FIB_HASH=y
377# CONFIG_IP_PNP is not set 395# CONFIG_IP_PNP is not set
378# CONFIG_NET_IPIP is not set 396# CONFIG_NET_IPIP is not set
379# CONFIG_NET_IPGRE is not set 397# CONFIG_NET_IPGRE is not set
@@ -386,6 +404,8 @@ CONFIG_IP_MULTICAST=y
386# CONFIG_INET_TUNNEL is not set 404# CONFIG_INET_TUNNEL is not set
387# CONFIG_IP_TCPDIAG is not set 405# CONFIG_IP_TCPDIAG is not set
388# CONFIG_IP_TCPDIAG_IPV6 is not set 406# CONFIG_IP_TCPDIAG_IPV6 is not set
407# CONFIG_TCP_CONG_ADVANCED is not set
408CONFIG_TCP_CONG_BIC=y
389 409
390# 410#
391# IP: Virtual Server Configuration 411# IP: Virtual Server Configuration
@@ -405,8 +425,6 @@ CONFIG_NETFILTER=y
405CONFIG_IP_NF_ARPTABLES=y 425CONFIG_IP_NF_ARPTABLES=y
406# CONFIG_IP_NF_ARPFILTER is not set 426# CONFIG_IP_NF_ARPFILTER is not set
407# CONFIG_IP_NF_ARP_MANGLE is not set 427# CONFIG_IP_NF_ARP_MANGLE is not set
408# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
409# CONFIG_IP_NF_COMPAT_IPFWADM is not set
410 428
411# 429#
412# SCTP Configuration (EXPERIMENTAL) 430# SCTP Configuration (EXPERIMENTAL)
@@ -483,7 +501,6 @@ CONFIG_NET_PCI=y
483# CONFIG_DGRS is not set 501# CONFIG_DGRS is not set
484# CONFIG_EEPRO100 is not set 502# CONFIG_EEPRO100 is not set
485CONFIG_E100=y 503CONFIG_E100=y
486# CONFIG_E100_NAPI is not set
487# CONFIG_FEALNX is not set 504# CONFIG_FEALNX is not set
488# CONFIG_NATSEMI is not set 505# CONFIG_NATSEMI is not set
489# CONFIG_NE2K_PCI is not set 506# CONFIG_NE2K_PCI is not set
@@ -505,9 +522,11 @@ CONFIG_E1000=y
505# CONFIG_HAMACHI is not set 522# CONFIG_HAMACHI is not set
506# CONFIG_YELLOWFIN is not set 523# CONFIG_YELLOWFIN is not set
507# CONFIG_R8169 is not set 524# CONFIG_R8169 is not set
525# CONFIG_SKGE is not set
508# CONFIG_SK98LIN is not set 526# CONFIG_SK98LIN is not set
509# CONFIG_VIA_VELOCITY is not set 527# CONFIG_VIA_VELOCITY is not set
510CONFIG_TIGON3=y 528CONFIG_TIGON3=y
529# CONFIG_BNX2 is not set
511 530
512# 531#
513# Ethernet (10000 Mbit) 532# Ethernet (10000 Mbit)
@@ -565,18 +584,6 @@ CONFIG_INPUT_EVDEV=y
565# CONFIG_INPUT_EVBUG is not set 584# CONFIG_INPUT_EVBUG is not set
566 585
567# 586#
568# Input I/O drivers
569#
570# CONFIG_GAMEPORT is not set
571CONFIG_SOUND_GAMEPORT=y
572CONFIG_SERIO=y
573# CONFIG_SERIO_I8042 is not set
574# CONFIG_SERIO_SERPORT is not set
575# CONFIG_SERIO_CT82C710 is not set
576# CONFIG_SERIO_PCIPS2 is not set
577# CONFIG_SERIO_RAW is not set
578
579#
580# Input Device Drivers 587# Input Device Drivers
581# 588#
582# CONFIG_INPUT_KEYBOARD is not set 589# CONFIG_INPUT_KEYBOARD is not set
@@ -586,6 +593,16 @@ CONFIG_SERIO=y
586# CONFIG_INPUT_MISC is not set 593# CONFIG_INPUT_MISC is not set
587 594
588# 595#
596# Hardware I/O ports
597#
598CONFIG_SERIO=y
599# CONFIG_SERIO_I8042 is not set
600# CONFIG_SERIO_SERPORT is not set
601# CONFIG_SERIO_PCIPS2 is not set
602# CONFIG_SERIO_RAW is not set
603# CONFIG_GAMEPORT is not set
604
605#
589# Character devices 606# Character devices
590# 607#
591CONFIG_VT=y 608CONFIG_VT=y
@@ -603,7 +620,6 @@ CONFIG_SERIAL_8250_NR_UARTS=8
603CONFIG_SERIAL_8250_EXTENDED=y 620CONFIG_SERIAL_8250_EXTENDED=y
604CONFIG_SERIAL_8250_SHARE_IRQ=y 621CONFIG_SERIAL_8250_SHARE_IRQ=y
605# CONFIG_SERIAL_8250_DETECT_IRQ is not set 622# CONFIG_SERIAL_8250_DETECT_IRQ is not set
606# CONFIG_SERIAL_8250_MULTIPORT is not set
607# CONFIG_SERIAL_8250_RSA is not set 623# CONFIG_SERIAL_8250_RSA is not set
608 624
609# 625#
@@ -611,6 +627,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
611# 627#
612CONFIG_SERIAL_CORE=y 628CONFIG_SERIAL_CORE=y
613CONFIG_SERIAL_CORE_CONSOLE=y 629CONFIG_SERIAL_CORE_CONSOLE=y
630# CONFIG_SERIAL_JSM is not set
614CONFIG_UNIX98_PTYS=y 631CONFIG_UNIX98_PTYS=y
615CONFIG_LEGACY_PTYS=y 632CONFIG_LEGACY_PTYS=y
616CONFIG_LEGACY_PTY_COUNT=256 633CONFIG_LEGACY_PTY_COUNT=256
@@ -644,6 +661,12 @@ CONFIG_DRM_RADEON=y
644# CONFIG_DRM_SIS is not set 661# CONFIG_DRM_SIS is not set
645# CONFIG_RAW_DRIVER is not set 662# CONFIG_RAW_DRIVER is not set
646# CONFIG_HPET is not set 663# CONFIG_HPET is not set
664# CONFIG_HANGCHECK_TIMER is not set
665
666#
667# TPM devices
668#
669# CONFIG_TCG_TPM is not set
647 670
648# 671#
649# I2C support 672# I2C support
@@ -668,6 +691,7 @@ CONFIG_I2C_ALGOPCF=y
668# CONFIG_I2C_AMD8111 is not set 691# CONFIG_I2C_AMD8111 is not set
669# CONFIG_I2C_I801 is not set 692# CONFIG_I2C_I801 is not set
670# CONFIG_I2C_I810 is not set 693# CONFIG_I2C_I810 is not set
694# CONFIG_I2C_PIIX4 is not set
671# CONFIG_I2C_ISA is not set 695# CONFIG_I2C_ISA is not set
672# CONFIG_I2C_NFORCE2 is not set 696# CONFIG_I2C_NFORCE2 is not set
673# CONFIG_I2C_PARPORT_LIGHT is not set 697# CONFIG_I2C_PARPORT_LIGHT is not set
@@ -691,10 +715,14 @@ CONFIG_I2C_ALGOPCF=y
691# CONFIG_SENSORS_ADM1025 is not set 715# CONFIG_SENSORS_ADM1025 is not set
692# CONFIG_SENSORS_ADM1026 is not set 716# CONFIG_SENSORS_ADM1026 is not set
693# CONFIG_SENSORS_ADM1031 is not set 717# CONFIG_SENSORS_ADM1031 is not set
718# CONFIG_SENSORS_ADM9240 is not set
694# CONFIG_SENSORS_ASB100 is not set 719# CONFIG_SENSORS_ASB100 is not set
720# CONFIG_SENSORS_ATXP1 is not set
695# CONFIG_SENSORS_DS1621 is not set 721# CONFIG_SENSORS_DS1621 is not set
696# CONFIG_SENSORS_FSCHER is not set 722# CONFIG_SENSORS_FSCHER is not set
723# CONFIG_SENSORS_FSCPOS is not set
697# CONFIG_SENSORS_GL518SM is not set 724# CONFIG_SENSORS_GL518SM is not set
725# CONFIG_SENSORS_GL520SM is not set
698# CONFIG_SENSORS_IT87 is not set 726# CONFIG_SENSORS_IT87 is not set
699# CONFIG_SENSORS_LM63 is not set 727# CONFIG_SENSORS_LM63 is not set
700# CONFIG_SENSORS_LM75 is not set 728# CONFIG_SENSORS_LM75 is not set
@@ -705,21 +733,29 @@ CONFIG_I2C_ALGOPCF=y
705# CONFIG_SENSORS_LM85 is not set 733# CONFIG_SENSORS_LM85 is not set
706# CONFIG_SENSORS_LM87 is not set 734# CONFIG_SENSORS_LM87 is not set
707# CONFIG_SENSORS_LM90 is not set 735# CONFIG_SENSORS_LM90 is not set
736# CONFIG_SENSORS_LM92 is not set
708# CONFIG_SENSORS_MAX1619 is not set 737# CONFIG_SENSORS_MAX1619 is not set
709# CONFIG_SENSORS_PC87360 is not set 738# CONFIG_SENSORS_PC87360 is not set
739# CONFIG_SENSORS_SMSC47B397 is not set
740# CONFIG_SENSORS_SIS5595 is not set
710# CONFIG_SENSORS_SMSC47M1 is not set 741# CONFIG_SENSORS_SMSC47M1 is not set
711# CONFIG_SENSORS_VIA686A is not set 742# CONFIG_SENSORS_VIA686A is not set
712# CONFIG_SENSORS_W83781D is not set 743# CONFIG_SENSORS_W83781D is not set
713# CONFIG_SENSORS_W83L785TS is not set 744# CONFIG_SENSORS_W83L785TS is not set
714# CONFIG_SENSORS_W83627HF is not set 745# CONFIG_SENSORS_W83627HF is not set
746# CONFIG_SENSORS_W83627EHF is not set
715 747
716# 748#
717# Other I2C Chip support 749# Other I2C Chip support
718# 750#
751# CONFIG_SENSORS_DS1337 is not set
752# CONFIG_SENSORS_DS1374 is not set
719# CONFIG_SENSORS_EEPROM is not set 753# CONFIG_SENSORS_EEPROM is not set
720# CONFIG_SENSORS_PCF8574 is not set 754# CONFIG_SENSORS_PCF8574 is not set
755# CONFIG_SENSORS_PCA9539 is not set
721# CONFIG_SENSORS_PCF8591 is not set 756# CONFIG_SENSORS_PCF8591 is not set
722# CONFIG_SENSORS_RTC8564 is not set 757# CONFIG_SENSORS_RTC8564 is not set
758# CONFIG_SENSORS_MAX6875 is not set
723# CONFIG_I2C_DEBUG_CORE is not set 759# CONFIG_I2C_DEBUG_CORE is not set
724# CONFIG_I2C_DEBUG_ALGO is not set 760# CONFIG_I2C_DEBUG_ALGO is not set
725# CONFIG_I2C_DEBUG_BUS is not set 761# CONFIG_I2C_DEBUG_BUS is not set
@@ -746,6 +782,7 @@ CONFIG_VIDEO_DEV=y
746# 782#
747# Video Adapters 783# Video Adapters
748# 784#
785# CONFIG_TUNER_MULTI_I2C is not set
749# CONFIG_VIDEO_BT848 is not set 786# CONFIG_VIDEO_BT848 is not set
750# CONFIG_VIDEO_CPIA is not set 787# CONFIG_VIDEO_CPIA is not set
751# CONFIG_VIDEO_SAA5246A is not set 788# CONFIG_VIDEO_SAA5246A is not set
@@ -778,6 +815,11 @@ CONFIG_VIDEO_DEV=y
778# Graphics support 815# Graphics support
779# 816#
780CONFIG_FB=y 817CONFIG_FB=y
818CONFIG_FB_CFB_FILLRECT=y
819CONFIG_FB_CFB_COPYAREA=y
820CONFIG_FB_CFB_IMAGEBLIT=y
821CONFIG_FB_SOFT_CURSOR=y
822# CONFIG_FB_MACMODES is not set
781CONFIG_FB_MODE_HELPERS=y 823CONFIG_FB_MODE_HELPERS=y
782# CONFIG_FB_TILEBLITTING is not set 824# CONFIG_FB_TILEBLITTING is not set
783# CONFIG_FB_CIRRUS is not set 825# CONFIG_FB_CIRRUS is not set
@@ -785,6 +827,7 @@ CONFIG_FB_MODE_HELPERS=y
785# CONFIG_FB_CYBER2000 is not set 827# CONFIG_FB_CYBER2000 is not set
786# CONFIG_FB_ASILIANT is not set 828# CONFIG_FB_ASILIANT is not set
787# CONFIG_FB_IMSTT is not set 829# CONFIG_FB_IMSTT is not set
830# CONFIG_FB_NVIDIA is not set
788# CONFIG_FB_RIVA is not set 831# CONFIG_FB_RIVA is not set
789# CONFIG_FB_MATROX is not set 832# CONFIG_FB_MATROX is not set
790# CONFIG_FB_RADEON_OLD is not set 833# CONFIG_FB_RADEON_OLD is not set
@@ -801,6 +844,7 @@ CONFIG_FB_RADEON_DEBUG=y
801# CONFIG_FB_VOODOO1 is not set 844# CONFIG_FB_VOODOO1 is not set
802# CONFIG_FB_TRIDENT is not set 845# CONFIG_FB_TRIDENT is not set
803# CONFIG_FB_PM3 is not set 846# CONFIG_FB_PM3 is not set
847# CONFIG_FB_S1D13XXX is not set
804# CONFIG_FB_VIRTUAL is not set 848# CONFIG_FB_VIRTUAL is not set
805 849
806# 850#
@@ -820,6 +864,7 @@ CONFIG_LOGO=y
820# CONFIG_LOGO_LINUX_MONO is not set 864# CONFIG_LOGO_LINUX_MONO is not set
821# CONFIG_LOGO_LINUX_VGA16 is not set 865# CONFIG_LOGO_LINUX_VGA16 is not set
822CONFIG_LOGO_LINUX_CLUT224=y 866CONFIG_LOGO_LINUX_CLUT224=y
867# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
823 868
824# 869#
825# Sound 870# Sound
@@ -869,6 +914,8 @@ CONFIG_SND_AC97_CODEC=y
869# CONFIG_SND_CS46XX is not set 914# CONFIG_SND_CS46XX is not set
870# CONFIG_SND_CS4281 is not set 915# CONFIG_SND_CS4281 is not set
871# CONFIG_SND_EMU10K1 is not set 916# CONFIG_SND_EMU10K1 is not set
917# CONFIG_SND_EMU10K1X is not set
918# CONFIG_SND_CA0106 is not set
872# CONFIG_SND_KORG1212 is not set 919# CONFIG_SND_KORG1212 is not set
873# CONFIG_SND_MIXART is not set 920# CONFIG_SND_MIXART is not set
874# CONFIG_SND_NM256 is not set 921# CONFIG_SND_NM256 is not set
@@ -876,6 +923,7 @@ CONFIG_SND_AC97_CODEC=y
876# CONFIG_SND_RME96 is not set 923# CONFIG_SND_RME96 is not set
877# CONFIG_SND_RME9652 is not set 924# CONFIG_SND_RME9652 is not set
878# CONFIG_SND_HDSP is not set 925# CONFIG_SND_HDSP is not set
926# CONFIG_SND_HDSPM is not set
879# CONFIG_SND_TRIDENT is not set 927# CONFIG_SND_TRIDENT is not set
880# CONFIG_SND_YMFPCI is not set 928# CONFIG_SND_YMFPCI is not set
881# CONFIG_SND_ALS4000 is not set 929# CONFIG_SND_ALS4000 is not set
@@ -893,13 +941,14 @@ CONFIG_SND_FM801_TEA575X=y
893# CONFIG_SND_INTEL8X0M is not set 941# CONFIG_SND_INTEL8X0M is not set
894# CONFIG_SND_SONICVIBES is not set 942# CONFIG_SND_SONICVIBES is not set
895# CONFIG_SND_VIA82XX is not set 943# CONFIG_SND_VIA82XX is not set
944# CONFIG_SND_VIA82XX_MODEM is not set
896# CONFIG_SND_VX222 is not set 945# CONFIG_SND_VX222 is not set
946# CONFIG_SND_HDA_INTEL is not set
897 947
898# 948#
899# USB devices 949# USB devices
900# 950#
901# CONFIG_SND_USB_AUDIO is not set 951# CONFIG_SND_USB_AUDIO is not set
902# CONFIG_SND_USB_USX2Y is not set
903 952
904# 953#
905# Open Sound System 954# Open Sound System
@@ -909,6 +958,8 @@ CONFIG_SND_FM801_TEA575X=y
909# 958#
910# USB support 959# USB support
911# 960#
961CONFIG_USB_ARCH_HAS_HCD=y
962CONFIG_USB_ARCH_HAS_OHCI=y
912CONFIG_USB=y 963CONFIG_USB=y
913# CONFIG_USB_DEBUG is not set 964# CONFIG_USB_DEBUG is not set
914 965
@@ -920,8 +971,6 @@ CONFIG_USB_BANDWIDTH=y
920# CONFIG_USB_DYNAMIC_MINORS is not set 971# CONFIG_USB_DYNAMIC_MINORS is not set
921# CONFIG_USB_SUSPEND is not set 972# CONFIG_USB_SUSPEND is not set
922# CONFIG_USB_OTG is not set 973# CONFIG_USB_OTG is not set
923CONFIG_USB_ARCH_HAS_HCD=y
924CONFIG_USB_ARCH_HAS_OHCI=y
925 974
926# 975#
927# USB Host Controller Drivers 976# USB Host Controller Drivers
@@ -929,7 +978,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y
929CONFIG_USB_EHCI_HCD=y 978CONFIG_USB_EHCI_HCD=y
930# CONFIG_USB_EHCI_SPLIT_ISO is not set 979# CONFIG_USB_EHCI_SPLIT_ISO is not set
931# CONFIG_USB_EHCI_ROOT_HUB_TT is not set 980# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
981# CONFIG_USB_ISP116X_HCD is not set
932CONFIG_USB_OHCI_HCD=y 982CONFIG_USB_OHCI_HCD=y
983# CONFIG_USB_OHCI_BIG_ENDIAN is not set
984CONFIG_USB_OHCI_LITTLE_ENDIAN=y
933CONFIG_USB_UHCI_HCD=y 985CONFIG_USB_UHCI_HCD=y
934# CONFIG_USB_SL811_HCD is not set 986# CONFIG_USB_SL811_HCD is not set
935 987
@@ -947,12 +999,11 @@ CONFIG_USB_UHCI_HCD=y
947# 999#
948CONFIG_USB_STORAGE=y 1000CONFIG_USB_STORAGE=y
949# CONFIG_USB_STORAGE_DEBUG is not set 1001# CONFIG_USB_STORAGE_DEBUG is not set
950# CONFIG_USB_STORAGE_RW_DETECT is not set
951# CONFIG_USB_STORAGE_DATAFAB is not set 1002# CONFIG_USB_STORAGE_DATAFAB is not set
952# CONFIG_USB_STORAGE_FREECOM is not set 1003# CONFIG_USB_STORAGE_FREECOM is not set
953# CONFIG_USB_STORAGE_ISD200 is not set 1004# CONFIG_USB_STORAGE_ISD200 is not set
954# CONFIG_USB_STORAGE_DPCM is not set 1005# CONFIG_USB_STORAGE_DPCM is not set
955# CONFIG_USB_STORAGE_HP8200e is not set 1006# CONFIG_USB_STORAGE_USBAT is not set
956# CONFIG_USB_STORAGE_SDDR09 is not set 1007# CONFIG_USB_STORAGE_SDDR09 is not set
957# CONFIG_USB_STORAGE_SDDR55 is not set 1008# CONFIG_USB_STORAGE_SDDR55 is not set
958# CONFIG_USB_STORAGE_JUMPSHOT is not set 1009# CONFIG_USB_STORAGE_JUMPSHOT is not set
@@ -966,9 +1017,11 @@ CONFIG_USB_HIDINPUT=y
966CONFIG_USB_HIDDEV=y 1017CONFIG_USB_HIDDEV=y
967# CONFIG_USB_AIPTEK is not set 1018# CONFIG_USB_AIPTEK is not set
968# CONFIG_USB_WACOM is not set 1019# CONFIG_USB_WACOM is not set
1020# CONFIG_USB_ACECAD is not set
969# CONFIG_USB_KBTAB is not set 1021# CONFIG_USB_KBTAB is not set
970# CONFIG_USB_POWERMATE is not set 1022# CONFIG_USB_POWERMATE is not set
971# CONFIG_USB_MTOUCH is not set 1023# CONFIG_USB_MTOUCH is not set
1024# CONFIG_USB_ITMTOUCH is not set
972# CONFIG_USB_EGALAX is not set 1025# CONFIG_USB_EGALAX is not set
973# CONFIG_USB_XPAD is not set 1026# CONFIG_USB_XPAD is not set
974# CONFIG_USB_ATI_REMOTE is not set 1027# CONFIG_USB_ATI_REMOTE is not set
@@ -978,7 +1031,6 @@ CONFIG_USB_HIDDEV=y
978# 1031#
979# CONFIG_USB_MDC800 is not set 1032# CONFIG_USB_MDC800 is not set
980# CONFIG_USB_MICROTEK is not set 1033# CONFIG_USB_MICROTEK is not set
981# CONFIG_USB_HPUSBSCSI is not set
982 1034
983# 1035#
984# USB Multimedia devices 1036# USB Multimedia devices
@@ -992,6 +1044,7 @@ CONFIG_USB_HIDDEV=y
992# CONFIG_USB_SE401 is not set 1044# CONFIG_USB_SE401 is not set
993# CONFIG_USB_SN9C102 is not set 1045# CONFIG_USB_SN9C102 is not set
994# CONFIG_USB_STV680 is not set 1046# CONFIG_USB_STV680 is not set
1047# CONFIG_USB_PWC is not set
995 1048
996# 1049#
997# USB Network Adapters 1050# USB Network Adapters
@@ -1001,6 +1054,7 @@ CONFIG_USB_HIDDEV=y
1001# CONFIG_USB_PEGASUS is not set 1054# CONFIG_USB_PEGASUS is not set
1002# CONFIG_USB_RTL8150 is not set 1055# CONFIG_USB_RTL8150 is not set
1003# CONFIG_USB_USBNET is not set 1056# CONFIG_USB_USBNET is not set
1057CONFIG_USB_MON=y
1004 1058
1005# 1059#
1006# USB port drivers 1060# USB port drivers
@@ -1016,7 +1070,6 @@ CONFIG_USB_HIDDEV=y
1016# 1070#
1017# CONFIG_USB_EMI62 is not set 1071# CONFIG_USB_EMI62 is not set
1018# CONFIG_USB_EMI26 is not set 1072# CONFIG_USB_EMI26 is not set
1019# CONFIG_USB_TIGL is not set
1020# CONFIG_USB_AUERSWALD is not set 1073# CONFIG_USB_AUERSWALD is not set
1021# CONFIG_USB_RIO500 is not set 1074# CONFIG_USB_RIO500 is not set
1022# CONFIG_USB_LEGOTOWER is not set 1075# CONFIG_USB_LEGOTOWER is not set
@@ -1025,9 +1078,11 @@ CONFIG_USB_HIDDEV=y
1025# CONFIG_USB_CYTHERM is not set 1078# CONFIG_USB_CYTHERM is not set
1026# CONFIG_USB_PHIDGETKIT is not set 1079# CONFIG_USB_PHIDGETKIT is not set
1027# CONFIG_USB_PHIDGETSERVO is not set 1080# CONFIG_USB_PHIDGETSERVO is not set
1081# CONFIG_USB_IDMOUSE is not set
1082# CONFIG_USB_SISUSBVGA is not set
1028 1083
1029# 1084#
1030# USB ATM/DSL drivers 1085# USB DSL modem support
1031# 1086#
1032 1087
1033# 1088#
@@ -1041,12 +1096,22 @@ CONFIG_USB_HIDDEV=y
1041# CONFIG_MMC is not set 1096# CONFIG_MMC is not set
1042 1097
1043# 1098#
1099# InfiniBand support
1100#
1101# CONFIG_INFINIBAND is not set
1102
1103#
1104# SN Devices
1105#
1106
1107#
1044# File systems 1108# File systems
1045# 1109#
1046CONFIG_EXT2_FS=y 1110CONFIG_EXT2_FS=y
1047CONFIG_EXT2_FS_XATTR=y 1111CONFIG_EXT2_FS_XATTR=y
1048# CONFIG_EXT2_FS_POSIX_ACL is not set 1112# CONFIG_EXT2_FS_POSIX_ACL is not set
1049# CONFIG_EXT2_FS_SECURITY is not set 1113# CONFIG_EXT2_FS_SECURITY is not set
1114# CONFIG_EXT2_FS_XIP is not set
1050CONFIG_EXT3_FS=y 1115CONFIG_EXT3_FS=y
1051CONFIG_EXT3_FS_XATTR=y 1116CONFIG_EXT3_FS_XATTR=y
1052# CONFIG_EXT3_FS_POSIX_ACL is not set 1117# CONFIG_EXT3_FS_POSIX_ACL is not set
@@ -1056,6 +1121,10 @@ CONFIG_JBD=y
1056CONFIG_FS_MBCACHE=y 1121CONFIG_FS_MBCACHE=y
1057# CONFIG_REISERFS_FS is not set 1122# CONFIG_REISERFS_FS is not set
1058# CONFIG_JFS_FS is not set 1123# CONFIG_JFS_FS is not set
1124
1125#
1126# XFS support
1127#
1059# CONFIG_XFS_FS is not set 1128# CONFIG_XFS_FS is not set
1060# CONFIG_MINIX_FS is not set 1129# CONFIG_MINIX_FS is not set
1061# CONFIG_ROMFS_FS is not set 1130# CONFIG_ROMFS_FS is not set
@@ -1089,7 +1158,6 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1089CONFIG_PROC_FS=y 1158CONFIG_PROC_FS=y
1090CONFIG_PROC_KCORE=y 1159CONFIG_PROC_KCORE=y
1091CONFIG_SYSFS=y 1160CONFIG_SYSFS=y
1092# CONFIG_DEVFS_FS is not set
1093# CONFIG_DEVPTS_FS_XATTR is not set 1161# CONFIG_DEVPTS_FS_XATTR is not set
1094CONFIG_TMPFS=y 1162CONFIG_TMPFS=y
1095CONFIG_TMPFS_XATTR=y 1163CONFIG_TMPFS_XATTR=y
@@ -1120,15 +1188,18 @@ CONFIG_RAMFS=y
1120# 1188#
1121CONFIG_NFS_FS=y 1189CONFIG_NFS_FS=y
1122CONFIG_NFS_V3=y 1190CONFIG_NFS_V3=y
1191# CONFIG_NFS_V3_ACL is not set
1123CONFIG_NFS_V4=y 1192CONFIG_NFS_V4=y
1124# CONFIG_NFS_DIRECTIO is not set 1193# CONFIG_NFS_DIRECTIO is not set
1125CONFIG_NFSD=y 1194CONFIG_NFSD=y
1126CONFIG_NFSD_V3=y 1195CONFIG_NFSD_V3=y
1196# CONFIG_NFSD_V3_ACL is not set
1127# CONFIG_NFSD_V4 is not set 1197# CONFIG_NFSD_V4 is not set
1128# CONFIG_NFSD_TCP is not set 1198# CONFIG_NFSD_TCP is not set
1129CONFIG_LOCKD=y 1199CONFIG_LOCKD=y
1130CONFIG_LOCKD_V4=y 1200CONFIG_LOCKD_V4=y
1131CONFIG_EXPORTFS=y 1201CONFIG_EXPORTFS=y
1202CONFIG_NFS_COMMON=y
1132CONFIG_SUNRPC=y 1203CONFIG_SUNRPC=y
1133CONFIG_SUNRPC_GSS=y 1204CONFIG_SUNRPC_GSS=y
1134CONFIG_RPCSEC_GSS_KRB5=y 1205CONFIG_RPCSEC_GSS_KRB5=y
@@ -1209,6 +1280,8 @@ CONFIG_NLS_UTF8=y
1209# CONFIG_CRC_CCITT is not set 1280# CONFIG_CRC_CCITT is not set
1210CONFIG_CRC32=y 1281CONFIG_CRC32=y
1211# CONFIG_LIBCRC32C is not set 1282# CONFIG_LIBCRC32C is not set
1283CONFIG_GENERIC_HARDIRQS=y
1284CONFIG_GENERIC_IRQ_PROBE=y
1212 1285
1213# 1286#
1214# Profiling support 1287# Profiling support
@@ -1218,14 +1291,18 @@ CONFIG_CRC32=y
1218# 1291#
1219# Kernel hacking 1292# Kernel hacking
1220# 1293#
1294# CONFIG_PRINTK_TIME is not set
1221CONFIG_DEBUG_KERNEL=y 1295CONFIG_DEBUG_KERNEL=y
1222CONFIG_MAGIC_SYSRQ=y 1296CONFIG_MAGIC_SYSRQ=y
1297CONFIG_LOG_BUF_SHIFT=17
1223# CONFIG_SCHEDSTATS is not set 1298# CONFIG_SCHEDSTATS is not set
1224# CONFIG_DEBUG_SLAB is not set 1299# CONFIG_DEBUG_SLAB is not set
1225# CONFIG_DEBUG_SPINLOCK is not set 1300# CONFIG_DEBUG_SPINLOCK is not set
1226# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1301# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1227# CONFIG_DEBUG_KOBJECT is not set 1302# CONFIG_DEBUG_KOBJECT is not set
1228# CONFIG_DEBUG_INFO is not set 1303# CONFIG_DEBUG_INFO is not set
1304# CONFIG_DEBUG_FS is not set
1305CONFIG_KPROBES=y
1229CONFIG_IA64_GRANULE_16MB=y 1306CONFIG_IA64_GRANULE_16MB=y
1230# CONFIG_IA64_GRANULE_64MB is not set 1307# CONFIG_IA64_GRANULE_64MB is not set
1231CONFIG_IA64_PRINT_HAZARDS=y 1308CONFIG_IA64_PRINT_HAZARDS=y
@@ -1252,6 +1329,7 @@ CONFIG_CRYPTO_MD5=y
1252# CONFIG_CRYPTO_SHA256 is not set 1329# CONFIG_CRYPTO_SHA256 is not set
1253# CONFIG_CRYPTO_SHA512 is not set 1330# CONFIG_CRYPTO_SHA512 is not set
1254# CONFIG_CRYPTO_WP512 is not set 1331# CONFIG_CRYPTO_WP512 is not set
1332# CONFIG_CRYPTO_TGR192 is not set
1255CONFIG_CRYPTO_DES=y 1333CONFIG_CRYPTO_DES=y
1256# CONFIG_CRYPTO_BLOWFISH is not set 1334# CONFIG_CRYPTO_BLOWFISH is not set
1257# CONFIG_CRYPTO_TWOFISH is not set 1335# CONFIG_CRYPTO_TWOFISH is not set
diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c
index b8db6e3e5e81..11957598a8b9 100644
--- a/arch/ia64/hp/common/sba_iommu.c
+++ b/arch/ia64/hp/common/sba_iommu.c
@@ -156,10 +156,13 @@
156*/ 156*/
157#define DELAYED_RESOURCE_CNT 64 157#define DELAYED_RESOURCE_CNT 64
158 158
159#define PCI_DEVICE_ID_HP_SX2000_IOC 0x12ec
160
159#define ZX1_IOC_ID ((PCI_DEVICE_ID_HP_ZX1_IOC << 16) | PCI_VENDOR_ID_HP) 161#define ZX1_IOC_ID ((PCI_DEVICE_ID_HP_ZX1_IOC << 16) | PCI_VENDOR_ID_HP)
160#define ZX2_IOC_ID ((PCI_DEVICE_ID_HP_ZX2_IOC << 16) | PCI_VENDOR_ID_HP) 162#define ZX2_IOC_ID ((PCI_DEVICE_ID_HP_ZX2_IOC << 16) | PCI_VENDOR_ID_HP)
161#define REO_IOC_ID ((PCI_DEVICE_ID_HP_REO_IOC << 16) | PCI_VENDOR_ID_HP) 163#define REO_IOC_ID ((PCI_DEVICE_ID_HP_REO_IOC << 16) | PCI_VENDOR_ID_HP)
162#define SX1000_IOC_ID ((PCI_DEVICE_ID_HP_SX1000_IOC << 16) | PCI_VENDOR_ID_HP) 164#define SX1000_IOC_ID ((PCI_DEVICE_ID_HP_SX1000_IOC << 16) | PCI_VENDOR_ID_HP)
165#define SX2000_IOC_ID ((PCI_DEVICE_ID_HP_SX2000_IOC << 16) | PCI_VENDOR_ID_HP)
163 166
164#define ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */ 167#define ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */
165 168
@@ -1726,6 +1729,7 @@ static struct ioc_iommu ioc_iommu_info[] __initdata = {
1726 { ZX1_IOC_ID, "zx1", ioc_zx1_init }, 1729 { ZX1_IOC_ID, "zx1", ioc_zx1_init },
1727 { ZX2_IOC_ID, "zx2", NULL }, 1730 { ZX2_IOC_ID, "zx2", NULL },
1728 { SX1000_IOC_ID, "sx1000", NULL }, 1731 { SX1000_IOC_ID, "sx1000", NULL },
1732 { SX2000_IOC_ID, "sx2000", NULL },
1729}; 1733};
1730 1734
1731static struct ioc * __init 1735static struct ioc * __init
diff --git a/arch/ia64/hp/sim/simserial.c b/arch/ia64/hp/sim/simserial.c
index 786e70718ce4..7a8ae0f4b387 100644
--- a/arch/ia64/hp/sim/simserial.c
+++ b/arch/ia64/hp/sim/simserial.c
@@ -30,6 +30,7 @@
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/serial.h> 31#include <linux/serial.h>
32#include <linux/serialP.h> 32#include <linux/serialP.h>
33#include <linux/sysrq.h>
33 34
34#include <asm/irq.h> 35#include <asm/irq.h>
35#include <asm/hw_irq.h> 36#include <asm/hw_irq.h>
@@ -149,12 +150,17 @@ static void receive_chars(struct tty_struct *tty, struct pt_regs *regs)
149 seen_esc = 2; 150 seen_esc = 2;
150 continue; 151 continue;
151 } else if ( seen_esc == 2 ) { 152 } else if ( seen_esc == 2 ) {
152 if ( ch == 'P' ) show_state(); /* F1 key */ 153 if ( ch == 'P' ) /* F1 */
153#ifdef CONFIG_KDB 154 show_state();
154 if ( ch == 'S' ) 155#ifdef CONFIG_MAGIC_SYSRQ
155 kdb(KDB_REASON_KEYBOARD, 0, (kdb_eframe_t) regs); 156 if ( ch == 'S' ) { /* F4 */
157 do
158 ch = ia64_ssc(0, 0, 0, 0,
159 SSC_GETCHAR);
160 while (!ch);
161 handle_sysrq(ch, regs, NULL);
162 }
156#endif 163#endif
157
158 seen_esc = 0; 164 seen_esc = 0;
159 continue; 165 continue;
160 } 166 }
diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S
index 785a51b0ad8e..69f88d561d62 100644
--- a/arch/ia64/kernel/entry.S
+++ b/arch/ia64/kernel/entry.S
@@ -470,18 +470,6 @@ ENTRY(load_switch_stack)
470 br.cond.sptk.many b7 470 br.cond.sptk.many b7
471END(load_switch_stack) 471END(load_switch_stack)
472 472
473GLOBAL_ENTRY(__ia64_syscall)
474 .regstk 6,0,0,0
475 mov r15=in5 // put syscall number in place
476 break __BREAK_SYSCALL
477 movl r2=errno
478 cmp.eq p6,p7=-1,r10
479 ;;
480(p6) st4 [r2]=r8
481(p6) mov r8=-1
482 br.ret.sptk.many rp
483END(__ia64_syscall)
484
485GLOBAL_ENTRY(execve) 473GLOBAL_ENTRY(execve)
486 mov r15=__NR_execve // put syscall number in place 474 mov r15=__NR_execve // put syscall number in place
487 break __BREAK_SYSCALL 475 break __BREAK_SYSCALL
@@ -637,7 +625,7 @@ END(ia64_ret_from_syscall)
637 * r8-r11: restored (syscall return value(s)) 625 * r8-r11: restored (syscall return value(s))
638 * r12: restored (user-level stack pointer) 626 * r12: restored (user-level stack pointer)
639 * r13: restored (user-level thread pointer) 627 * r13: restored (user-level thread pointer)
640 * r14: cleared 628 * r14: set to __kernel_syscall_via_epc
641 * r15: restored (syscall #) 629 * r15: restored (syscall #)
642 * r16-r17: cleared 630 * r16-r17: cleared
643 * r18: user-level b6 631 * r18: user-level b6
@@ -658,7 +646,7 @@ END(ia64_ret_from_syscall)
658 * pr: restored (user-level pr) 646 * pr: restored (user-level pr)
659 * b0: restored (user-level rp) 647 * b0: restored (user-level rp)
660 * b6: restored 648 * b6: restored
661 * b7: cleared 649 * b7: set to __kernel_syscall_via_epc
662 * ar.unat: restored (user-level ar.unat) 650 * ar.unat: restored (user-level ar.unat)
663 * ar.pfs: restored (user-level ar.pfs) 651 * ar.pfs: restored (user-level ar.pfs)
664 * ar.rsc: restored (user-level ar.rsc) 652 * ar.rsc: restored (user-level ar.rsc)
@@ -704,72 +692,79 @@ ENTRY(ia64_leave_syscall)
704 ;; 692 ;;
705(p6) ld4 r31=[r18] // load current_thread_info()->flags 693(p6) ld4 r31=[r18] // load current_thread_info()->flags
706 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs" 694 ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
707 mov b7=r0 // clear b7 695 nop.i 0
708 ;; 696 ;;
709 ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage) 697 mov r16=ar.bsp // M2 get existing backing store pointer
710 ld8 r18=[r2],PT(R9)-PT(B6) // load b6 698 ld8 r18=[r2],PT(R9)-PT(B6) // load b6
711(p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE? 699(p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
712 ;; 700 ;;
713 mov r16=ar.bsp // M2 get existing backing store pointer 701 ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
714(p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending? 702(p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending?
715(p6) br.cond.spnt .work_pending_syscall 703(p6) br.cond.spnt .work_pending_syscall
716 ;; 704 ;;
717 // start restoring the state saved on the kernel stack (struct pt_regs): 705 // start restoring the state saved on the kernel stack (struct pt_regs):
718 ld8 r9=[r2],PT(CR_IPSR)-PT(R9) 706 ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
719 ld8 r11=[r3],PT(CR_IIP)-PT(R11) 707 ld8 r11=[r3],PT(CR_IIP)-PT(R11)
720 mov f6=f0 // clear f6 708(pNonSys) break 0 // bug check: we shouldn't be here if pNonSys is TRUE!
721 ;; 709 ;;
722 invala // M0|1 invalidate ALAT 710 invala // M0|1 invalidate ALAT
723 rsm psr.i | psr.ic // M2 initiate turning off of interrupt and interruption collection 711 rsm psr.i | psr.ic // M2 turn off interrupts and interruption collection
724 mov f9=f0 // clear f9 712 cmp.eq p9,p0=r0,r0 // A set p9 to indicate that we should restore cr.ifs
725 713
726 ld8 r29=[r2],16 // load cr.ipsr 714 ld8 r29=[r2],16 // M0|1 load cr.ipsr
727 ld8 r28=[r3],16 // load cr.iip 715 ld8 r28=[r3],16 // M0|1 load cr.iip
728 mov f8=f0 // clear f8 716 mov r22=r0 // A clear r22
729 ;; 717 ;;
730 ld8 r30=[r2],16 // M0|1 load cr.ifs 718 ld8 r30=[r2],16 // M0|1 load cr.ifs
731 ld8 r25=[r3],16 // M0|1 load ar.unat 719 ld8 r25=[r3],16 // M0|1 load ar.unat
732 cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs 720(pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
733 ;; 721 ;;
734 ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs 722 ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs
735(pKStk) mov r22=psr // M2 read PSR now that interrupts are disabled 723(pKStk) mov r22=psr // M2 read PSR now that interrupts are disabled
736 mov f10=f0 // clear f10 724 nop 0
737 ;; 725 ;;
738 ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // load b0 726 ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // M0|1 load b0
739 ld8 r27=[r3],PT(PR)-PT(AR_RSC) // load ar.rsc 727 ld8 r27=[r3],PT(PR)-PT(AR_RSC) // M0|1 load ar.rsc
740 mov f11=f0 // clear f11 728 mov f6=f0 // F clear f6
741 ;; 729 ;;
742 ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT) // load ar.rnat (may be garbage) 730 ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT) // M0|1 load ar.rnat (may be garbage)
743 ld8 r31=[r3],PT(R1)-PT(PR) // load predicates 731 ld8 r31=[r3],PT(R1)-PT(PR) // M0|1 load predicates
744(pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13 732 mov f7=f0 // F clear f7
745 ;; 733 ;;
746 ld8 r20=[r2],PT(R12)-PT(AR_FPSR) // load ar.fpsr 734 ld8 r20=[r2],PT(R12)-PT(AR_FPSR) // M0|1 load ar.fpsr
747 ld8.fill r1=[r3],16 // load r1 735 ld8.fill r1=[r3],16 // M0|1 load r1
748(pUStk) mov r17=1 736(pUStk) mov r17=1 // A
749 ;; 737 ;;
750 srlz.d // M0 ensure interruption collection is off 738(pUStk) st1 [r14]=r17 // M2|3
751 ld8.fill r13=[r3],16 739 ld8.fill r13=[r3],16 // M0|1
752 mov f7=f0 // clear f7 740 mov f8=f0 // F clear f8
753 ;; 741 ;;
754 ld8.fill r12=[r2] // restore r12 (sp) 742 ld8.fill r12=[r2] // M0|1 restore r12 (sp)
755 mov.m ar.ssd=r0 // M2 clear ar.ssd 743 ld8.fill r15=[r3] // M0|1 restore r15
756 mov r22=r0 // clear r22 744 mov b6=r18 // I0 restore b6
757 745
758 ld8.fill r15=[r3] // restore r15 746 addl r17=THIS_CPU(ia64_phys_stacked_size_p8),r0 // A
759(pUStk) st1 [r14]=r17 747 mov f9=f0 // F clear f9
760 addl r3=THIS_CPU(ia64_phys_stacked_size_p8),r0 748(pKStk) br.cond.dpnt.many skip_rbs_switch // B
749
750 srlz.d // M0 ensure interruption collection is off (for cover)
751 shr.u r18=r19,16 // I0|1 get byte size of existing "dirty" partition
752 cover // B add current frame into dirty partition & set cr.ifs
761 ;; 753 ;;
762(pUStk) ld4 r17=[r3] // r17 = cpu_data->phys_stacked_size_p8 754(pUStk) ld4 r17=[r17] // M0|1 r17 = cpu_data->phys_stacked_size_p8
763 mov.m ar.csd=r0 // M2 clear ar.csd 755 mov r19=ar.bsp // M2 get new backing store pointer
764 mov b6=r18 // I0 restore b6 756 mov f10=f0 // F clear f10
757
758 nop.m 0
759 movl r14=__kernel_syscall_via_epc // X
765 ;; 760 ;;
766 mov r14=r0 // clear r14 761 mov.m ar.csd=r0 // M2 clear ar.csd
767 shr.u r18=r19,16 // I0|1 get byte size of existing "dirty" partition 762 mov.m ar.ccv=r0 // M2 clear ar.ccv
768(pKStk) br.cond.dpnt.many skip_rbs_switch 763 mov b7=r14 // I0 clear b7 (hint with __kernel_syscall_via_epc)
769 764
770 mov.m ar.ccv=r0 // clear ar.ccv 765 mov.m ar.ssd=r0 // M2 clear ar.ssd
771(pNonSys) br.cond.dpnt.many dont_preserve_current_frame 766 mov f11=f0 // F clear f11
772 br.cond.sptk.many rbs_switch 767 br.cond.sptk.many rbs_switch // B
773END(ia64_leave_syscall) 768END(ia64_leave_syscall)
774 769
775#ifdef CONFIG_IA32_SUPPORT 770#ifdef CONFIG_IA32_SUPPORT
@@ -885,7 +880,7 @@ GLOBAL_ENTRY(ia64_leave_kernel)
885 ldf.fill f7=[r2],PT(F11)-PT(F7) 880 ldf.fill f7=[r2],PT(F11)-PT(F7)
886 ldf.fill f8=[r3],32 881 ldf.fill f8=[r3],32
887 ;; 882 ;;
888 srlz.i // ensure interruption collection is off 883 srlz.d // ensure that inter. collection is off (VHPT is don't care, since text is pinned)
889 mov ar.ccv=r15 884 mov ar.ccv=r15
890 ;; 885 ;;
891 ldf.fill f11=[r2] 886 ldf.fill f11=[r2]
@@ -945,11 +940,10 @@ GLOBAL_ENTRY(ia64_leave_kernel)
945 * NOTE: alloc, loadrs, and cover can't be predicated. 940 * NOTE: alloc, loadrs, and cover can't be predicated.
946 */ 941 */
947(pNonSys) br.cond.dpnt dont_preserve_current_frame 942(pNonSys) br.cond.dpnt dont_preserve_current_frame
948
949rbs_switch:
950 cover // add current frame into dirty partition and set cr.ifs 943 cover // add current frame into dirty partition and set cr.ifs
951 ;; 944 ;;
952 mov r19=ar.bsp // get new backing store pointer 945 mov r19=ar.bsp // get new backing store pointer
946rbs_switch:
953 sub r16=r16,r18 // krbs = old bsp - size of dirty partition 947 sub r16=r16,r18 // krbs = old bsp - size of dirty partition
954 cmp.ne p9,p0=r0,r0 // clear p9 to skip restore of cr.ifs 948 cmp.ne p9,p0=r0,r0 // clear p9 to skip restore of cr.ifs
955 ;; 949 ;;
@@ -1024,14 +1018,14 @@ rse_clear_invalid:
1024 mov loc5=0 1018 mov loc5=0
1025 mov loc6=0 1019 mov loc6=0
1026 mov loc7=0 1020 mov loc7=0
1027(pRecurse) br.call.sptk.few b0=rse_clear_invalid 1021(pRecurse) br.call.dptk.few b0=rse_clear_invalid
1028 ;; 1022 ;;
1029 mov loc8=0 1023 mov loc8=0
1030 mov loc9=0 1024 mov loc9=0
1031 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret 1025 cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
1032 mov loc10=0 1026 mov loc10=0
1033 mov loc11=0 1027 mov loc11=0
1034(pReturn) br.ret.sptk.many b0 1028(pReturn) br.ret.dptk.many b0
1035#endif /* !CONFIG_ITANIUM */ 1029#endif /* !CONFIG_ITANIUM */
1036# undef pRecurse 1030# undef pRecurse
1037# undef pReturn 1031# undef pReturn
diff --git a/arch/ia64/kernel/fsys.S b/arch/ia64/kernel/fsys.S
index 962b6c4e32b5..7d7684a369d3 100644
--- a/arch/ia64/kernel/fsys.S
+++ b/arch/ia64/kernel/fsys.S
@@ -531,93 +531,114 @@ GLOBAL_ENTRY(fsys_bubble_down)
531 .altrp b6 531 .altrp b6
532 .body 532 .body
533 /* 533 /*
534 * We get here for syscalls that don't have a lightweight handler. For those, we 534 * We get here for syscalls that don't have a lightweight
535 * need to bubble down into the kernel and that requires setting up a minimal 535 * handler. For those, we need to bubble down into the kernel
536 * pt_regs structure, and initializing the CPU state more or less as if an 536 * and that requires setting up a minimal pt_regs structure,
537 * interruption had occurred. To make syscall-restarts work, we setup pt_regs 537 * and initializing the CPU state more or less as if an
538 * such that cr_iip points to the second instruction in syscall_via_break. 538 * interruption had occurred. To make syscall-restarts work,
539 * Decrementing the IP hence will restart the syscall via break and not 539 * we setup pt_regs such that cr_iip points to the second
540 * decrementing IP will return us to the caller, as usual. Note that we preserve 540 * instruction in syscall_via_break. Decrementing the IP
541 * the value of psr.pp rather than initializing it from dcr.pp. This makes it 541 * hence will restart the syscall via break and not
542 * possible to distinguish fsyscall execution from other privileged execution. 542 * decrementing IP will return us to the caller, as usual.
543 * Note that we preserve the value of psr.pp rather than
544 * initializing it from dcr.pp. This makes it possible to
545 * distinguish fsyscall execution from other privileged
546 * execution.
543 * 547 *
544 * On entry: 548 * On entry:
545 * - normal fsyscall handler register usage, except that we also have: 549 * - normal fsyscall handler register usage, except
550 * that we also have:
546 * - r18: address of syscall entry point 551 * - r18: address of syscall entry point
547 * - r21: ar.fpsr 552 * - r21: ar.fpsr
548 * - r26: ar.pfs 553 * - r26: ar.pfs
549 * - r27: ar.rsc 554 * - r27: ar.rsc
550 * - r29: psr 555 * - r29: psr
556 *
557 * We used to clear some PSR bits here but that requires slow
558 * serialization. Fortuntely, that isn't really necessary.
559 * The rationale is as follows: we used to clear bits
560 * ~PSR_PRESERVED_BITS in PSR.L. Since
561 * PSR_PRESERVED_BITS==PSR.{UP,MFL,MFH,PK,DT,PP,SP,RT,IC}, we
562 * ended up clearing PSR.{BE,AC,I,DFL,DFH,DI,DB,SI,TB}.
563 * However,
564 *
565 * PSR.BE : already is turned off in __kernel_syscall_via_epc()
566 * PSR.AC : don't care (kernel normally turns PSR.AC on)
567 * PSR.I : already turned off by the time fsys_bubble_down gets
568 * invoked
569 * PSR.DFL: always 0 (kernel never turns it on)
570 * PSR.DFH: don't care --- kernel never touches f32-f127 on its own
571 * initiative
572 * PSR.DI : always 0 (kernel never turns it on)
573 * PSR.SI : always 0 (kernel never turns it on)
574 * PSR.DB : don't care --- kernel never enables kernel-level
575 * breakpoints
576 * PSR.TB : must be 0 already; if it wasn't zero on entry to
577 * __kernel_syscall_via_epc, the branch to fsys_bubble_down
578 * will trigger a taken branch; the taken-trap-handler then
579 * converts the syscall into a break-based system-call.
551 */ 580 */
552# define PSR_PRESERVED_BITS (IA64_PSR_UP | IA64_PSR_MFL | IA64_PSR_MFH | IA64_PSR_PK \
553 | IA64_PSR_DT | IA64_PSR_PP | IA64_PSR_SP | IA64_PSR_RT \
554 | IA64_PSR_IC)
555 /* 581 /*
556 * Reading psr.l gives us only bits 0-31, psr.it, and psr.mc. The rest we have 582 * Reading psr.l gives us only bits 0-31, psr.it, and psr.mc.
557 * to synthesize. 583 * The rest we have to synthesize.
558 */ 584 */
559# define PSR_ONE_BITS ((3 << IA64_PSR_CPL0_BIT) | (0x1 << IA64_PSR_RI_BIT) \ 585# define PSR_ONE_BITS ((3 << IA64_PSR_CPL0_BIT) \
586 | (0x1 << IA64_PSR_RI_BIT) \
560 | IA64_PSR_BN | IA64_PSR_I) 587 | IA64_PSR_BN | IA64_PSR_I)
561 588
562 invala 589 invala // M0|1
563 movl r8=PSR_ONE_BITS 590 movl r14=ia64_ret_from_syscall // X
564 591
565 mov r25=ar.unat // save ar.unat (5 cyc) 592 nop.m 0
566 movl r9=PSR_PRESERVED_BITS 593 movl r28=__kernel_syscall_via_break // X create cr.iip
594 ;;
567 595
568 mov ar.rsc=0 // set enforced lazy mode, pl 0, little-endian, loadrs=0 596 mov r2=r16 // A get task addr to addl-addressable register
569 movl r28=__kernel_syscall_via_break 597 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // A
598 mov r31=pr // I0 save pr (2 cyc)
570 ;; 599 ;;
571 mov r23=ar.bspstore // save ar.bspstore (12 cyc) 600 st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag
572 mov r31=pr // save pr (2 cyc) 601 addl r22=IA64_RBS_OFFSET,r2 // A compute base of RBS
573 mov r20=r1 // save caller's gp in r20 602 add r3=TI_FLAGS+IA64_TASK_SIZE,r2 // A
574 ;; 603 ;;
575 mov r2=r16 // copy current task addr to addl-addressable register 604 ld4 r3=[r3] // M0|1 r3 = current_thread_info()->flags
576 and r9=r9,r29 605 lfetch.fault.excl.nt1 [r22] // M0|1 prefetch register backing-store
577 mov r19=b6 // save b6 (2 cyc) 606 nop.i 0
578 ;; 607 ;;
579 mov psr.l=r9 // slam the door (17 cyc to srlz.i) 608 mov ar.rsc=0 // M2 set enforced lazy mode, pl 0, LE, loadrs=0
580 or r29=r8,r29 // construct cr.ipsr value to save 609 nop.m 0
581 addl r22=IA64_RBS_OFFSET,r2 // compute base of RBS 610 nop.i 0
582 ;; 611 ;;
583 // GAS reports a spurious RAW hazard on the read of ar.rnat because it thinks 612 mov r23=ar.bspstore // M2 (12 cyc) save ar.bspstore
584 // we may be reading ar.itc after writing to psr.l. Avoid that message with 613 mov.m r24=ar.rnat // M2 (5 cyc) read ar.rnat (dual-issues!)
585 // this directive: 614 nop.i 0
586 dv_serialize_data
587 mov.m r24=ar.rnat // read ar.rnat (5 cyc lat)
588 lfetch.fault.excl.nt1 [r22]
589 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r2
590
591 // ensure previous insn group is issued before we stall for srlz.i:
592 ;; 615 ;;
593 srlz.i // ensure new psr.l has been established 616 mov ar.bspstore=r22 // M2 (6 cyc) switch to kernel RBS
594 ///////////////////////////////////////////////////////////////////////////// 617 movl r8=PSR_ONE_BITS // X
595 ////////// from this point on, execution is not interruptible anymore
596 /////////////////////////////////////////////////////////////////////////////
597 addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r2 // compute base of memory stack
598 cmp.ne pKStk,pUStk=r0,r0 // set pKStk <- 0, pUStk <- 1
599 ;; 618 ;;
600 st1 [r16]=r0 // clear current->thread.on_ustack flag 619 mov r25=ar.unat // M2 (5 cyc) save ar.unat
601 mov ar.bspstore=r22 // switch to kernel RBS 620 mov r19=b6 // I0 save b6 (2 cyc)
602 mov b6=r18 // copy syscall entry-point to b6 (7 cyc) 621 mov r20=r1 // A save caller's gp in r20
603 add r3=TI_FLAGS+IA64_TASK_SIZE,r2
604 ;; 622 ;;
605 ld4 r3=[r3] // r2 = current_thread_info()->flags 623 or r29=r8,r29 // A construct cr.ipsr value to save
606 mov r18=ar.bsp // save (kernel) ar.bsp (12 cyc) 624 mov b6=r18 // I0 copy syscall entry-point to b6 (7 cyc)
607 mov ar.rsc=0x3 // set eager mode, pl 0, little-endian, loadrs=0 625 addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r2 // A compute base of memory stack
608 br.call.sptk.many b7=ia64_syscall_setup 626
609 ;; 627 mov r18=ar.bsp // M2 save (kernel) ar.bsp (12 cyc)
610 ssm psr.i 628 cmp.ne pKStk,pUStk=r0,r0 // A set pKStk <- 0, pUStk <- 1
611 movl r2=ia64_ret_from_syscall 629 br.call.sptk.many b7=ia64_syscall_setup // B
612 ;; 630 ;;
613 mov rp=r2 // set the real return addr 631 mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0
614 and r3=_TIF_SYSCALL_TRACEAUDIT,r3 632 mov rp=r14 // I0 set the real return addr
633 and r3=_TIF_SYSCALL_TRACEAUDIT,r3 // A
615 ;; 634 ;;
616 cmp.eq p8,p0=r3,r0 635 ssm psr.i // M2 we're on kernel stacks now, reenable irqs
636 cmp.eq p8,p0=r3,r0 // A
637(p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT
617 638
618(p10) br.cond.spnt.many ia64_ret_from_syscall // p10==true means out registers are more than 8 639 nop.m 0
619(p8) br.call.sptk.many b6=b6 // ignore this return addr 640(p8) br.call.sptk.many b6=b6 // B (ignore return address)
620 br.cond.sptk ia64_trace_syscall 641 br.cond.spnt ia64_trace_syscall // B
621END(fsys_bubble_down) 642END(fsys_bubble_down)
622 643
623 .rodata 644 .rodata
diff --git a/arch/ia64/kernel/gate.S b/arch/ia64/kernel/gate.S
index facf75acdc85..86948ce63e43 100644
--- a/arch/ia64/kernel/gate.S
+++ b/arch/ia64/kernel/gate.S
@@ -72,38 +72,40 @@ GLOBAL_ENTRY(__kernel_syscall_via_epc)
72 * bundle get executed. The remaining code must be safe even if 72 * bundle get executed. The remaining code must be safe even if
73 * they do not get executed. 73 * they do not get executed.
74 */ 74 */
75 adds r17=-1024,r15 75 adds r17=-1024,r15 // A
76 mov r10=0 // default to successful syscall execution 76 mov r10=0 // A default to successful syscall execution
77 epc 77 epc // B causes split-issue
78} 78}
79 ;; 79 ;;
80 rsm psr.be // note: on McKinley "rsm psr.be/srlz.d" is slightly faster than "rum psr.be" 80 rsm psr.be | psr.i // M2 (5 cyc to srlz.d)
81 LOAD_FSYSCALL_TABLE(r14) 81 LOAD_FSYSCALL_TABLE(r14) // X
82
83 mov r16=IA64_KR(CURRENT) // 12 cycle read latency
84 tnat.nz p10,p9=r15
85 mov r19=NR_syscalls-1
86 ;; 82 ;;
87 shladd r18=r17,3,r14 83 mov r16=IA64_KR(CURRENT) // M2 (12 cyc)
88 84 shladd r18=r17,3,r14 // A
89 srlz.d 85 mov r19=NR_syscalls-1 // A
90 cmp.ne p8,p0=r0,r0 // p8 <- FALSE 86 ;;
91 /* Note: if r17 is a NaT, p6 will be set to zero. */ 87 lfetch [r18] // M0|1
92 cmp.geu p6,p7=r19,r17 // (syscall > 0 && syscall < 1024+NR_syscalls)? 88 mov r29=psr // M2 (12 cyc)
93 ;; 89 // If r17 is a NaT, p6 will be zero
94(p6) ld8 r18=[r18] 90 cmp.geu p6,p7=r19,r17 // A (sysnr > 0 && sysnr < 1024+NR_syscalls)?
95 mov r21=ar.fpsr 91 ;;
96 add r14=-8,r14 // r14 <- addr of fsys_bubble_down entry 92 mov r21=ar.fpsr // M2 (12 cyc)
97 ;; 93 tnat.nz p10,p9=r15 // I0
98(p6) mov b7=r18 94 mov.i r26=ar.pfs // I0 (would stall anyhow due to srlz.d...)
99(p6) tbit.z p8,p0=r18,0 95 ;;
100(p8) br.dptk.many b7 96 srlz.d // M0 (forces split-issue) ensure PSR.BE==0
101 97(p6) ld8 r18=[r18] // M0|1
102(p6) rsm psr.i 98 nop.i 0
103 mov r27=ar.rsc 99 ;;
104 mov r26=ar.pfs 100 nop.m 0
101(p6) tbit.z.unc p8,p0=r18,0 // I0 (dual-issues with "mov b7=r18"!)
102 nop.i 0
105 ;; 103 ;;
106 mov r29=psr // read psr (12 cyc load latency) 104(p8) ssm psr.i
105(p6) mov b7=r18 // I0
106(p8) br.dptk.many b7 // B
107
108 mov r27=ar.rsc // M2 (12 cyc)
107/* 109/*
108 * brl.cond doesn't work as intended because the linker would convert this branch 110 * brl.cond doesn't work as intended because the linker would convert this branch
109 * into a branch to a PLT. Perhaps there will be a way to avoid this with some 111 * into a branch to a PLT. Perhaps there will be a way to avoid this with some
@@ -111,6 +113,8 @@ GLOBAL_ENTRY(__kernel_syscall_via_epc)
111 * instead. 113 * instead.
112 */ 114 */
113#ifdef CONFIG_ITANIUM 115#ifdef CONFIG_ITANIUM
116(p6) add r14=-8,r14 // r14 <- addr of fsys_bubble_down entry
117 ;;
114(p6) ld8 r14=[r14] // r14 <- fsys_bubble_down 118(p6) ld8 r14=[r14] // r14 <- fsys_bubble_down
115 ;; 119 ;;
116(p6) mov b7=r14 120(p6) mov b7=r14
@@ -118,7 +122,7 @@ GLOBAL_ENTRY(__kernel_syscall_via_epc)
118#else 122#else
119 BRL_COND_FSYS_BUBBLE_DOWN(p6) 123 BRL_COND_FSYS_BUBBLE_DOWN(p6)
120#endif 124#endif
121 125 ssm psr.i
122 mov r10=-1 126 mov r10=-1
123(p10) mov r8=EINVAL 127(p10) mov r8=EINVAL
124(p9) mov r8=ENOSYS 128(p9) mov r8=ENOSYS
diff --git a/arch/ia64/kernel/ia64_ksyms.c b/arch/ia64/kernel/ia64_ksyms.c
index 7bbf019c9867..01572814abe4 100644
--- a/arch/ia64/kernel/ia64_ksyms.c
+++ b/arch/ia64/kernel/ia64_ksyms.c
@@ -58,9 +58,6 @@ EXPORT_SYMBOL(__strlen_user);
58EXPORT_SYMBOL(__strncpy_from_user); 58EXPORT_SYMBOL(__strncpy_from_user);
59EXPORT_SYMBOL(__strnlen_user); 59EXPORT_SYMBOL(__strnlen_user);
60 60
61#include <asm/unistd.h>
62EXPORT_SYMBOL(__ia64_syscall);
63
64/* from arch/ia64/lib */ 61/* from arch/ia64/lib */
65extern void __divsi3(void); 62extern void __divsi3(void);
66extern void __udivsi3(void); 63extern void __udivsi3(void);
diff --git a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S
index 2bc085a73e30..3bb3a13c4047 100644
--- a/arch/ia64/kernel/ivt.S
+++ b/arch/ia64/kernel/ivt.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/ia64/kernel/ivt.S 2 * arch/ia64/kernel/ivt.S
3 * 3 *
4 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co 4 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com> 5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger <davidm@hpl.hp.com> 6 * David Mosberger <davidm@hpl.hp.com>
7 * Copyright (C) 2000, 2002-2003 Intel Co 7 * Copyright (C) 2000, 2002-2003 Intel Co
@@ -692,82 +692,118 @@ ENTRY(break_fault)
692 * to prevent leaking bits from kernel to user level. 692 * to prevent leaking bits from kernel to user level.
693 */ 693 */
694 DBG_FAULT(11) 694 DBG_FAULT(11)
695 mov r16=IA64_KR(CURRENT) // r16 = current task; 12 cycle read lat. 695 mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current task (12 cyc)
696 mov r17=cr.iim 696 mov r29=cr.ipsr // M2 (12 cyc)
697 mov r18=__IA64_BREAK_SYSCALL 697 mov r31=pr // I0 (2 cyc)
698 mov r21=ar.fpsr 698
699 mov r29=cr.ipsr 699 mov r17=cr.iim // M2 (2 cyc)
700 mov r19=b6 700 mov.m r27=ar.rsc // M2 (12 cyc)
701 mov r25=ar.unat 701 mov r18=__IA64_BREAK_SYSCALL // A
702 mov r27=ar.rsc 702
703 mov r26=ar.pfs 703 mov.m ar.rsc=0 // M2
704 mov r28=cr.iip 704 mov.m r21=ar.fpsr // M2 (12 cyc)
705 mov r31=pr // prepare to save predicates 705 mov r19=b6 // I0 (2 cyc)
706 mov r20=r1 706 ;;
707 ;; 707 mov.m r23=ar.bspstore // M2 (12 cyc)
708 mov.m r24=ar.rnat // M2 (5 cyc)
709 mov.i r26=ar.pfs // I0 (2 cyc)
710
711 invala // M0|1
712 nop.m 0 // M
713 mov r20=r1 // A save r1
714
715 nop.m 0
716 movl r30=sys_call_table // X
717
718 mov r28=cr.iip // M2 (2 cyc)
719 cmp.eq p0,p7=r18,r17 // I0 is this a system call?
720(p7) br.cond.spnt non_syscall // B no ->
721 //
722 // From this point on, we are definitely on the syscall-path
723 // and we can use (non-banked) scratch registers.
724 //
725///////////////////////////////////////////////////////////////////////
726 mov r1=r16 // A move task-pointer to "addl"-addressable reg
727 mov r2=r16 // A setup r2 for ia64_syscall_setup
728 add r9=TI_FLAGS+IA64_TASK_SIZE,r16 // A r9 = &current_thread_info()->flags
729
708 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 730 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
709 cmp.eq p0,p7=r18,r17 // is this a system call? (p7 <- false, if so) 731 adds r15=-1024,r15 // A subtract 1024 from syscall number
710(p7) br.cond.spnt non_syscall 732 mov r3=NR_syscalls - 1
711 ;; 733 ;;
712 ld1 r17=[r16] // load current->thread.on_ustack flag 734 ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag
713 st1 [r16]=r0 // clear current->thread.on_ustack flag 735 ld4 r9=[r9] // M0|1 r9 = current_thread_info()->flags
714 add r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // set r1 for MINSTATE_START_SAVE_MIN_VIRT 736 extr.u r8=r29,41,2 // I0 extract ei field from cr.ipsr
737
738 shladd r30=r15,3,r30 // A r30 = sys_call_table + 8*(syscall-1024)
739 addl r22=IA64_RBS_OFFSET,r1 // A compute base of RBS
740 cmp.leu p6,p7=r15,r3 // A syscall number in range?
715 ;; 741 ;;
716 invala
717 742
718 /* adjust return address so we skip over the break instruction: */ 743 lfetch.fault.excl.nt1 [r22] // M0|1 prefetch RBS
744(p6) ld8 r30=[r30] // M0|1 load address of syscall entry point
745 tnat.nz.or p7,p0=r15 // I0 is syscall nr a NaT?
719 746
720 extr.u r8=r29,41,2 // extract ei field from cr.ipsr 747 mov.m ar.bspstore=r22 // M2 switch to kernel RBS
721 ;; 748 cmp.eq p8,p9=2,r8 // A isr.ei==2?
722 cmp.eq p6,p7=2,r8 // isr.ei==2?
723 mov r2=r1 // setup r2 for ia64_syscall_setup
724 ;;
725(p6) mov r8=0 // clear ei to 0
726(p6) adds r28=16,r28 // switch cr.iip to next bundle cr.ipsr.ei wrapped
727(p7) adds r8=1,r8 // increment ei to next slot
728 ;;
729 cmp.eq pKStk,pUStk=r0,r17 // are we in kernel mode already?
730 dep r29=r8,r29,41,2 // insert new ei into cr.ipsr
731 ;; 749 ;;
732 750
733 // switch from user to kernel RBS: 751(p8) mov r8=0 // A clear ei to 0
734 MINSTATE_START_SAVE_MIN_VIRT 752(p7) movl r30=sys_ni_syscall // X
735 br.call.sptk.many b7=ia64_syscall_setup
736 ;;
737 MINSTATE_END_SAVE_MIN_VIRT // switch to bank 1
738 ssm psr.ic | PSR_DEFAULT_BITS
739 ;;
740 srlz.i // guarantee that interruption collection is on
741 mov r3=NR_syscalls - 1
742 ;;
743(p15) ssm psr.i // restore psr.i
744 // p10==true means out registers are more than 8 or r15's Nat is true
745(p10) br.cond.spnt.many ia64_ret_from_syscall
746 ;;
747 movl r16=sys_call_table
748 753
749 adds r15=-1024,r15 // r15 contains the syscall number---subtract 1024 754(p8) adds r28=16,r28 // A switch cr.iip to next bundle
750 movl r2=ia64_ret_from_syscall 755(p9) adds r8=1,r8 // A increment ei to next slot
751 ;; 756 nop.i 0
752 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
753 cmp.leu p6,p7=r15,r3 // (syscall > 0 && syscall < 1024 + NR_syscalls) ?
754 mov rp=r2 // set the real return addr
755 ;; 757 ;;
756(p6) ld8 r20=[r20] // load address of syscall entry point
757(p7) movl r20=sys_ni_syscall
758 758
759 add r2=TI_FLAGS+IA64_TASK_SIZE,r13 759 mov.m r25=ar.unat // M2 (5 cyc)
760 ;; 760 dep r29=r8,r29,41,2 // I0 insert new ei into cr.ipsr
761 ld4 r2=[r2] // r2 = current_thread_info()->flags 761 adds r15=1024,r15 // A restore original syscall number
762 ;; 762 //
763 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit 763 // If any of the above loads miss in L1D, we'll stall here until
764 // the data arrives.
765 //
766///////////////////////////////////////////////////////////////////////
767 st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag
768 mov b6=r30 // I0 setup syscall handler branch reg early
769 cmp.eq pKStk,pUStk=r0,r17 // A were we on kernel stacks already?
770
771 and r9=_TIF_SYSCALL_TRACEAUDIT,r9 // A mask trace or audit
772 mov r18=ar.bsp // M2 (12 cyc)
773(pKStk) br.cond.spnt .break_fixup // B we're already in kernel-mode -- fix up RBS
774 ;;
775.back_from_break_fixup:
776(pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1 // A compute base of memory stack
777 cmp.eq p14,p0=r9,r0 // A are syscalls being traced/audited?
778 br.call.sptk.many b7=ia64_syscall_setup // B
7791:
780 mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0
781 nop 0
782 bsw.1 // B (6 cyc) regs are saved, switch to bank 1
764 ;; 783 ;;
765 cmp.eq p8,p0=r2,r0 784
766 mov b6=r20 785 ssm psr.ic | PSR_DEFAULT_BITS // M2 now it's safe to re-enable intr.-collection
786 movl r3=ia64_ret_from_syscall // X
767 ;; 787 ;;
768(p8) br.call.sptk.many b6=b6 // ignore this return addr 788
769 br.cond.sptk ia64_trace_syscall 789 srlz.i // M0 ensure interruption collection is on
790 mov rp=r3 // I0 set the real return addr
791(p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT
792
793(p15) ssm psr.i // M2 restore psr.i
794(p14) br.call.sptk.many b6=b6 // B invoke syscall-handker (ignore return addr)
795 br.cond.spnt.many ia64_trace_syscall // B do syscall-tracing thingamagic
770 // NOT REACHED 796 // NOT REACHED
797///////////////////////////////////////////////////////////////////////
798 // On entry, we optimistically assumed that we're coming from user-space.
799 // For the rare cases where a system-call is done from within the kernel,
800 // we fix things up at this point:
801.break_fixup:
802 add r1=-IA64_PT_REGS_SIZE,sp // A allocate space for pt_regs structure
803 mov ar.rnat=r24 // M2 restore kernel's AR.RNAT
804 ;;
805 mov ar.bspstore=r23 // M2 restore kernel's AR.BSPSTORE
806 br.cond.sptk .back_from_break_fixup
771END(break_fault) 807END(break_fault)
772 808
773 .org ia64_ivt+0x3000 809 .org ia64_ivt+0x3000
@@ -842,8 +878,6 @@ END(interrupt)
842 * - r31: saved pr 878 * - r31: saved pr
843 * - b0: original contents (to be saved) 879 * - b0: original contents (to be saved)
844 * On exit: 880 * On exit:
845 * - executing on bank 1 registers
846 * - psr.ic enabled, interrupts restored
847 * - p10: TRUE if syscall is invoked with more than 8 out 881 * - p10: TRUE if syscall is invoked with more than 8 out
848 * registers or r15's Nat is true 882 * registers or r15's Nat is true
849 * - r1: kernel's gp 883 * - r1: kernel's gp
@@ -851,8 +885,11 @@ END(interrupt)
851 * - r8: -EINVAL if p10 is true 885 * - r8: -EINVAL if p10 is true
852 * - r12: points to kernel stack 886 * - r12: points to kernel stack
853 * - r13: points to current task 887 * - r13: points to current task
888 * - r14: preserved (same as on entry)
889 * - p13: preserved
854 * - p15: TRUE if interrupts need to be re-enabled 890 * - p15: TRUE if interrupts need to be re-enabled
855 * - ar.fpsr: set to kernel settings 891 * - ar.fpsr: set to kernel settings
892 * - b6: preserved (same as on entry)
856 */ 893 */
857GLOBAL_ENTRY(ia64_syscall_setup) 894GLOBAL_ENTRY(ia64_syscall_setup)
858#if PT(B6) != 0 895#if PT(B6) != 0
@@ -920,10 +957,10 @@ GLOBAL_ENTRY(ia64_syscall_setup)
920(p13) mov in5=-1 957(p13) mov in5=-1
921 ;; 958 ;;
922 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr 959 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
923 tnat.nz p14,p0=in6 960 tnat.nz p13,p0=in6
924 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8 961 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8
925 ;; 962 ;;
926 stf8 [r16]=f1 // ensure pt_regs.r8 != 0 (see handle_syscall_error) 963 mov r8=1
927(p9) tnat.nz p10,p0=r15 964(p9) tnat.nz p10,p0=r15
928 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch) 965 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
929 966
@@ -934,9 +971,9 @@ GLOBAL_ENTRY(ia64_syscall_setup)
934 mov r13=r2 // establish `current' 971 mov r13=r2 // establish `current'
935 movl r1=__gp // establish kernel global pointer 972 movl r1=__gp // establish kernel global pointer
936 ;; 973 ;;
937(p14) mov in6=-1 974 st8 [r16]=r8 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
975(p13) mov in6=-1
938(p8) mov in7=-1 976(p8) mov in7=-1
939 nop.i 0
940 977
941 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0 978 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
942 movl r17=FPSR_DEFAULT 979 movl r17=FPSR_DEFAULT
@@ -1007,6 +1044,8 @@ END(dispatch_illegal_op_fault)
1007 FAULT(17) 1044 FAULT(17)
1008 1045
1009ENTRY(non_syscall) 1046ENTRY(non_syscall)
1047 mov ar.rsc=r27 // restore ar.rsc before SAVE_MIN_WITH_COVER
1048 ;;
1010 SAVE_MIN_WITH_COVER 1049 SAVE_MIN_WITH_COVER
1011 1050
1012 // There is no particular reason for this code to be here, other than that 1051 // There is no particular reason for this code to be here, other than that
@@ -1204,6 +1243,25 @@ END(disabled_fp_reg)
1204// 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50) 1243// 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1205ENTRY(nat_consumption) 1244ENTRY(nat_consumption)
1206 DBG_FAULT(26) 1245 DBG_FAULT(26)
1246
1247 mov r16=cr.ipsr
1248 mov r17=cr.isr
1249 mov r31=pr // save PR
1250 ;;
1251 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0}
1252 tbit.z p6,p0=r17,IA64_ISR_NA_BIT
1253 ;;
1254 cmp.ne.or p6,p0=IA64_ISR_CODE_LFETCH,r18
1255 dep r16=-1,r16,IA64_PSR_ED_BIT,1
1256(p6) br.cond.spnt 1f // branch if (cr.ispr.na == 0 || cr.ipsr.code{3:0} != LFETCH)
1257 ;;
1258 mov cr.ipsr=r16 // set cr.ipsr.na
1259 mov pr=r31,-1
1260 ;;
1261 rfi
1262
12631: mov pr=r31,-1
1264 ;;
1207 FAULT(26) 1265 FAULT(26)
1208END(nat_consumption) 1266END(nat_consumption)
1209 1267
diff --git a/arch/ia64/kernel/ptrace.c b/arch/ia64/kernel/ptrace.c
index 6d57aebad485..bbb8bc7c0552 100644
--- a/arch/ia64/kernel/ptrace.c
+++ b/arch/ia64/kernel/ptrace.c
@@ -725,12 +725,32 @@ convert_to_non_syscall (struct task_struct *child, struct pt_regs *pt,
725 break; 725 break;
726 } 726 }
727 727
728 /*
729 * Note: at the time of this call, the target task is blocked
730 * in notify_resume_user() and by clearling PRED_LEAVE_SYSCALL
731 * (aka, "pLvSys") we redirect execution from
732 * .work_pending_syscall_end to .work_processed_kernel.
733 */
728 unw_get_pr(&prev_info, &pr); 734 unw_get_pr(&prev_info, &pr);
729 pr &= ~(1UL << PRED_SYSCALL); 735 pr &= ~((1UL << PRED_SYSCALL) | (1UL << PRED_LEAVE_SYSCALL));
730 pr |= (1UL << PRED_NON_SYSCALL); 736 pr |= (1UL << PRED_NON_SYSCALL);
731 unw_set_pr(&prev_info, pr); 737 unw_set_pr(&prev_info, pr);
732 738
733 pt->cr_ifs = (1UL << 63) | cfm; 739 pt->cr_ifs = (1UL << 63) | cfm;
740 /*
741 * Clear the memory that is NOT written on syscall-entry to
742 * ensure we do not leak kernel-state to user when execution
743 * resumes.
744 */
745 pt->r2 = 0;
746 pt->r3 = 0;
747 pt->r14 = 0;
748 memset(&pt->r16, 0, 16*8); /* clear r16-r31 */
749 memset(&pt->f6, 0, 6*16); /* clear f6-f11 */
750 pt->b7 = 0;
751 pt->ar_ccv = 0;
752 pt->ar_csd = 0;
753 pt->ar_ssd = 0;
734} 754}
735 755
736static int 756static int
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index d14692e0920a..2693e1522d7c 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -72,6 +72,8 @@ DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
72unsigned long ia64_cycles_per_usec; 72unsigned long ia64_cycles_per_usec;
73struct ia64_boot_param *ia64_boot_param; 73struct ia64_boot_param *ia64_boot_param;
74struct screen_info screen_info; 74struct screen_info screen_info;
75unsigned long vga_console_iobase;
76unsigned long vga_console_membase;
75 77
76unsigned long ia64_max_cacheline_size; 78unsigned long ia64_max_cacheline_size;
77unsigned long ia64_iobase; /* virtual address for I/O accesses */ 79unsigned long ia64_iobase; /* virtual address for I/O accesses */
@@ -273,23 +275,25 @@ io_port_init (void)
273static inline int __init 275static inline int __init
274early_console_setup (char *cmdline) 276early_console_setup (char *cmdline)
275{ 277{
278 int earlycons = 0;
279
276#ifdef CONFIG_SERIAL_SGI_L1_CONSOLE 280#ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
277 { 281 {
278 extern int sn_serial_console_early_setup(void); 282 extern int sn_serial_console_early_setup(void);
279 if (!sn_serial_console_early_setup()) 283 if (!sn_serial_console_early_setup())
280 return 0; 284 earlycons++;
281 } 285 }
282#endif 286#endif
283#ifdef CONFIG_EFI_PCDP 287#ifdef CONFIG_EFI_PCDP
284 if (!efi_setup_pcdp_console(cmdline)) 288 if (!efi_setup_pcdp_console(cmdline))
285 return 0; 289 earlycons++;
286#endif 290#endif
287#ifdef CONFIG_SERIAL_8250_CONSOLE 291#ifdef CONFIG_SERIAL_8250_CONSOLE
288 if (!early_serial_console_init(cmdline)) 292 if (!early_serial_console_init(cmdline))
289 return 0; 293 earlycons++;
290#endif 294#endif
291 295
292 return -1; 296 return (earlycons) ? 0 : -1;
293} 297}
294 298
295static inline void 299static inline void
diff --git a/arch/ia64/kernel/smp.c b/arch/ia64/kernel/smp.c
index b49d4ddaab93..0166a9847095 100644
--- a/arch/ia64/kernel/smp.c
+++ b/arch/ia64/kernel/smp.c
@@ -231,13 +231,16 @@ smp_flush_tlb_all (void)
231void 231void
232smp_flush_tlb_mm (struct mm_struct *mm) 232smp_flush_tlb_mm (struct mm_struct *mm)
233{ 233{
234 preempt_disable();
234 /* this happens for the common case of a single-threaded fork(): */ 235 /* this happens for the common case of a single-threaded fork(): */
235 if (likely(mm == current->active_mm && atomic_read(&mm->mm_users) == 1)) 236 if (likely(mm == current->active_mm && atomic_read(&mm->mm_users) == 1))
236 { 237 {
237 local_finish_flush_tlb_mm(mm); 238 local_finish_flush_tlb_mm(mm);
239 preempt_enable();
238 return; 240 return;
239 } 241 }
240 242
243 preempt_enable();
241 /* 244 /*
242 * We could optimize this further by using mm->cpu_vm_mask to track which CPUs 245 * We could optimize this further by using mm->cpu_vm_mask to track which CPUs
243 * have been running in the address space. It's not clear that this is worth the 246 * have been running in the address space. It's not clear that this is worth the
diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
index 9e07f5463f21..783eb4323847 100644
--- a/arch/ia64/sn/kernel/io_init.c
+++ b/arch/ia64/sn/kernel/io_init.c
@@ -384,7 +384,7 @@ static int __init sn_pci_init(void)
384 extern void register_sn_procfs(void); 384 extern void register_sn_procfs(void);
385#endif 385#endif
386 386
387 if (!ia64_platform_is("sn2") || IS_RUNNING_ON_SIMULATOR()) 387 if (!ia64_platform_is("sn2") || IS_RUNNING_ON_FAKE_PROM())
388 return 0; 388 return 0;
389 389
390 /* 390 /*
diff --git a/arch/ia64/sn/kernel/iomv.c b/arch/ia64/sn/kernel/iomv.c
index fec6d8b8237b..7ce3cdad627b 100644
--- a/arch/ia64/sn/kernel/iomv.c
+++ b/arch/ia64/sn/kernel/iomv.c
@@ -9,12 +9,16 @@
9#include <linux/module.h> 9#include <linux/module.h>
10#include <asm/io.h> 10#include <asm/io.h>
11#include <asm/delay.h> 11#include <asm/delay.h>
12#include <asm/vga.h>
12#include <asm/sn/nodepda.h> 13#include <asm/sn/nodepda.h>
13#include <asm/sn/simulator.h> 14#include <asm/sn/simulator.h>
14#include <asm/sn/pda.h> 15#include <asm/sn/pda.h>
15#include <asm/sn/sn_cpuid.h> 16#include <asm/sn/sn_cpuid.h>
16#include <asm/sn/shub_mmr.h> 17#include <asm/sn/shub_mmr.h>
17 18
19#define IS_LEGACY_VGA_IOPORT(p) \
20 (((p) >= 0x3b0 && (p) <= 0x3bb) || ((p) >= 0x3c0 && (p) <= 0x3df))
21
18/** 22/**
19 * sn_io_addr - convert an in/out port to an i/o address 23 * sn_io_addr - convert an in/out port to an i/o address
20 * @port: port to convert 24 * @port: port to convert
@@ -26,6 +30,8 @@
26void *sn_io_addr(unsigned long port) 30void *sn_io_addr(unsigned long port)
27{ 31{
28 if (!IS_RUNNING_ON_SIMULATOR()) { 32 if (!IS_RUNNING_ON_SIMULATOR()) {
33 if (IS_LEGACY_VGA_IOPORT(port))
34 port += vga_console_iobase;
29 /* On sn2, legacy I/O ports don't point at anything */ 35 /* On sn2, legacy I/O ports don't point at anything */
30 if (port < (64 * 1024)) 36 if (port < (64 * 1024))
31 return NULL; 37 return NULL;
diff --git a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c
index 44bfc7f318cb..22e10d282c7f 100644
--- a/arch/ia64/sn/kernel/setup.c
+++ b/arch/ia64/sn/kernel/setup.c
@@ -36,6 +36,7 @@
36#include <asm/machvec.h> 36#include <asm/machvec.h>
37#include <asm/system.h> 37#include <asm/system.h>
38#include <asm/processor.h> 38#include <asm/processor.h>
39#include <asm/vga.h>
39#include <asm/sn/arch.h> 40#include <asm/sn/arch.h>
40#include <asm/sn/addrs.h> 41#include <asm/sn/addrs.h>
41#include <asm/sn/pda.h> 42#include <asm/sn/pda.h>
@@ -95,6 +96,7 @@ u8 sn_coherency_id;
95EXPORT_SYMBOL(sn_coherency_id); 96EXPORT_SYMBOL(sn_coherency_id);
96u8 sn_region_size; 97u8 sn_region_size;
97EXPORT_SYMBOL(sn_region_size); 98EXPORT_SYMBOL(sn_region_size);
99int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
98 100
99short physical_node_map[MAX_PHYSNODE_ID]; 101short physical_node_map[MAX_PHYSNODE_ID];
100 102
@@ -273,14 +275,17 @@ void __init sn_setup(char **cmdline_p)
273 275
274 ia64_sn_plat_set_error_handling_features(); 276 ia64_sn_plat_set_error_handling_features();
275 277
278#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
276 /* 279 /*
277 * If the generic code has enabled vga console support - lets 280 * If there was a primary vga adapter identified through the
278 * get rid of it again. This is a kludge for the fact that ACPI 281 * EFI PCDP table, make it the preferred console. Otherwise
279 * currtently has no way of informing us if legacy VGA is available 282 * zero out conswitchp.
280 * or not.
281 */ 283 */
282#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 284
283 if (conswitchp == &vga_con) { 285 if (vga_console_membase) {
286 /* usable vga ... make tty0 the preferred default console */
287 add_preferred_console("tty", 0, NULL);
288 } else {
284 printk(KERN_DEBUG "SGI: Disabling VGA console\n"); 289 printk(KERN_DEBUG "SGI: Disabling VGA console\n");
285#ifdef CONFIG_DUMMY_CONSOLE 290#ifdef CONFIG_DUMMY_CONSOLE
286 conswitchp = &dummy_con; 291 conswitchp = &dummy_con;
@@ -350,7 +355,7 @@ void __init sn_setup(char **cmdline_p)
350 355
351 ia64_mark_idle = &snidle; 356 ia64_mark_idle = &snidle;
352 357
353 /* 358 /*
354 * For the bootcpu, we do this here. All other cpus will make the 359 * For the bootcpu, we do this here. All other cpus will make the
355 * call as part of cpu_init in slave cpu initialization. 360 * call as part of cpu_init in slave cpu initialization.
356 */ 361 */
@@ -397,7 +402,7 @@ static void __init sn_init_pdas(char **cmdline_p)
397 nodepdaindr[cnode] = 402 nodepdaindr[cnode] =
398 alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t)); 403 alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t));
399 memset(nodepdaindr[cnode], 0, sizeof(nodepda_t)); 404 memset(nodepdaindr[cnode], 0, sizeof(nodepda_t));
400 memset(nodepdaindr[cnode]->phys_cpuid, -1, 405 memset(nodepdaindr[cnode]->phys_cpuid, -1,
401 sizeof(nodepdaindr[cnode]->phys_cpuid)); 406 sizeof(nodepdaindr[cnode]->phys_cpuid));
402 } 407 }
403 408
@@ -427,7 +432,7 @@ static void __init sn_init_pdas(char **cmdline_p)
427 } 432 }
428 433
429 /* 434 /*
430 * Initialize the per node hubdev. This includes IO Nodes and 435 * Initialize the per node hubdev. This includes IO Nodes and
431 * headless/memless nodes. 436 * headless/memless nodes.
432 */ 437 */
433 for (cnode = 0; cnode < numionodes; cnode++) { 438 for (cnode = 0; cnode < numionodes; cnode++) {
@@ -455,6 +460,14 @@ void __init sn_cpu_init(void)
455 int i; 460 int i;
456 static int wars_have_been_checked; 461 static int wars_have_been_checked;
457 462
463 if (smp_processor_id() == 0 && IS_MEDUSA()) {
464 if (ia64_sn_is_fake_prom())
465 sn_prom_type = 2;
466 else
467 sn_prom_type = 1;
468 printk("Running on medusa with %s PROM\n", (sn_prom_type == 1) ? "real" : "fake");
469 }
470
458 memset(pda, 0, sizeof(pda)); 471 memset(pda, 0, sizeof(pda));
459 if (ia64_sn_get_sn_info(0, &sn_hub_info->shub2, &sn_hub_info->nasid_bitmask, &sn_hub_info->nasid_shift, 472 if (ia64_sn_get_sn_info(0, &sn_hub_info->shub2, &sn_hub_info->nasid_bitmask, &sn_hub_info->nasid_shift,
460 &sn_system_size, &sn_sharing_domain_size, &sn_partition_id, 473 &sn_system_size, &sn_sharing_domain_size, &sn_partition_id,
@@ -520,7 +533,7 @@ void __init sn_cpu_init(void)
520 */ 533 */
521 { 534 {
522 u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0}; 535 u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0};
523 u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_1, 536 u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_1,
524 SH2_PIO_WRITE_STATUS_2, SH2_PIO_WRITE_STATUS_3}; 537 SH2_PIO_WRITE_STATUS_2, SH2_PIO_WRITE_STATUS_3};
525 u64 *pio; 538 u64 *pio;
526 pio = is_shub1() ? pio1 : pio2; 539 pio = is_shub1() ? pio1 : pio2;
@@ -552,6 +565,10 @@ static void __init scan_for_ionodes(void)
552 int nasid = 0; 565 int nasid = 0;
553 lboard_t *brd; 566 lboard_t *brd;
554 567
568 /* fakeprom does not support klgraph */
569 if (IS_RUNNING_ON_FAKE_PROM())
570 return;
571
555 /* Setup ionodes with memory */ 572 /* Setup ionodes with memory */
556 for (nasid = 0; nasid < MAX_PHYSNODE_ID; nasid += 2) { 573 for (nasid = 0; nasid < MAX_PHYSNODE_ID; nasid += 2) {
557 char *klgraph_header; 574 char *klgraph_header;
@@ -563,8 +580,6 @@ static void __init scan_for_ionodes(void)
563 cnodeid = -1; 580 cnodeid = -1;
564 klgraph_header = __va(ia64_sn_get_klconfig_addr(nasid)); 581 klgraph_header = __va(ia64_sn_get_klconfig_addr(nasid));
565 if (!klgraph_header) { 582 if (!klgraph_header) {
566 if (IS_RUNNING_ON_SIMULATOR())
567 continue;
568 BUG(); /* All nodes must have klconfig tables! */ 583 BUG(); /* All nodes must have klconfig tables! */
569 } 584 }
570 cnodeid = nasid_to_cnodeid(nasid); 585 cnodeid = nasid_to_cnodeid(nasid);
@@ -630,8 +645,8 @@ int
630nasid_slice_to_cpuid(int nasid, int slice) 645nasid_slice_to_cpuid(int nasid, int slice)
631{ 646{
632 long cpu; 647 long cpu;
633 648
634 for (cpu=0; cpu < NR_CPUS; cpu++) 649 for (cpu=0; cpu < NR_CPUS; cpu++)
635 if (cpuid_to_nasid(cpu) == nasid && 650 if (cpuid_to_nasid(cpu) == nasid &&
636 cpuid_to_slice(cpu) == slice) 651 cpuid_to_slice(cpu) == slice)
637 return cpu; 652 return cpu;
diff --git a/arch/ia64/sn/kernel/sn2/ptc_deadlock.S b/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
index 7947312801ec..96cb71d15682 100644
--- a/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
+++ b/arch/ia64/sn/kernel/sn2/ptc_deadlock.S
@@ -6,6 +6,7 @@
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8 8
9#include <asm/types.h>
9#include <asm/sn/shub_mmr.h> 10#include <asm/sn/shub_mmr.h>
10 11
11#define DEADLOCKBIT SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 12#define DEADLOCKBIT SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT
diff --git a/arch/ia64/sn/kernel/tiocx.c b/arch/ia64/sn/kernel/tiocx.c
index a087b274847e..8716f4d5314b 100644
--- a/arch/ia64/sn/kernel/tiocx.c
+++ b/arch/ia64/sn/kernel/tiocx.c
@@ -204,8 +204,8 @@ cx_device_register(nasid_t nasid, int part_num, int mfg_num,
204 cx_dev->dev.parent = NULL; 204 cx_dev->dev.parent = NULL;
205 cx_dev->dev.bus = &tiocx_bus_type; 205 cx_dev->dev.bus = &tiocx_bus_type;
206 cx_dev->dev.release = tiocx_bus_release; 206 cx_dev->dev.release = tiocx_bus_release;
207 snprintf(cx_dev->dev.bus_id, BUS_ID_SIZE, "%d.0x%x", 207 snprintf(cx_dev->dev.bus_id, BUS_ID_SIZE, "%d",
208 cx_dev->cx_id.nasid, cx_dev->cx_id.part_num); 208 cx_dev->cx_id.nasid);
209 device_register(&cx_dev->dev); 209 device_register(&cx_dev->dev);
210 get_device(&cx_dev->dev); 210 get_device(&cx_dev->dev);
211 211
@@ -236,7 +236,6 @@ int cx_device_unregister(struct cx_dev *cx_dev)
236 */ 236 */
237static int cx_device_reload(struct cx_dev *cx_dev) 237static int cx_device_reload(struct cx_dev *cx_dev)
238{ 238{
239 device_remove_file(&cx_dev->dev, &dev_attr_cxdev_control);
240 cx_device_unregister(cx_dev); 239 cx_device_unregister(cx_dev);
241 return cx_device_register(cx_dev->cx_id.nasid, cx_dev->cx_id.part_num, 240 return cx_device_register(cx_dev->cx_id.nasid, cx_dev->cx_id.part_num,
242 cx_dev->cx_id.mfg_num, cx_dev->hubdev); 241 cx_dev->cx_id.mfg_num, cx_dev->hubdev);
@@ -383,6 +382,7 @@ static int is_fpga_brick(int nasid)
383 switch (tiocx_btchar_get(nasid)) { 382 switch (tiocx_btchar_get(nasid)) {
384 case L1_BRICKTYPE_SA: 383 case L1_BRICKTYPE_SA:
385 case L1_BRICKTYPE_ATHENA: 384 case L1_BRICKTYPE_ATHENA:
385 case L1_BRICKTYPE_DAYTONA:
386 return 1; 386 return 1;
387 } 387 }
388 return 0; 388 return 0;
@@ -409,7 +409,7 @@ static int tiocx_reload(struct cx_dev *cx_dev)
409 uint64_t cx_id; 409 uint64_t cx_id;
410 410
411 cx_id = 411 cx_id =
412 *(volatile int32_t *)(TIO_SWIN_BASE(nasid, TIOCX_CORELET) + 412 *(volatile uint64_t *)(TIO_SWIN_BASE(nasid, TIOCX_CORELET) +
413 WIDGET_ID); 413 WIDGET_ID);
414 part_num = XWIDGET_PART_NUM(cx_id); 414 part_num = XWIDGET_PART_NUM(cx_id);
415 mfg_num = XWIDGET_MFG_NUM(cx_id); 415 mfg_num = XWIDGET_MFG_NUM(cx_id);
@@ -458,6 +458,10 @@ static ssize_t store_cxdev_control(struct device *dev, struct device_attribute *
458 458
459 switch (n) { 459 switch (n) {
460 case 1: 460 case 1:
461 tio_corelet_reset(cx_dev->cx_id.nasid, TIOCX_CORELET);
462 tiocx_reload(cx_dev);
463 break;
464 case 2:
461 tiocx_reload(cx_dev); 465 tiocx_reload(cx_dev);
462 break; 466 break;
463 case 3: 467 case 3:
@@ -537,7 +541,7 @@ static void __exit tiocx_exit(void)
537 bus_unregister(&tiocx_bus_type); 541 bus_unregister(&tiocx_bus_type);
538} 542}
539 543
540module_init(tiocx_init); 544subsys_initcall(tiocx_init);
541module_exit(tiocx_exit); 545module_exit(tiocx_exit);
542 546
543/************************************************************************ 547/************************************************************************
diff --git a/arch/ia64/sn/pci/tioca_provider.c b/arch/ia64/sn/pci/tioca_provider.c
index 8dae9eb45456..05aa8c2fe9bb 100644
--- a/arch/ia64/sn/pci/tioca_provider.c
+++ b/arch/ia64/sn/pci/tioca_provider.c
@@ -336,7 +336,7 @@ tioca_dma_d48(struct pci_dev *pdev, uint64_t paddr)
336 if (!ct_addr) 336 if (!ct_addr)
337 return 0; 337 return 0;
338 338
339 bus_addr = (dma_addr_t) (ct_addr & 0xffffffffffff); 339 bus_addr = (dma_addr_t) (ct_addr & 0xffffffffffffUL);
340 node_upper = ct_addr >> 48; 340 node_upper = ct_addr >> 48;
341 341
342 if (node_upper > 64) { 342 if (node_upper > 64) {
@@ -464,7 +464,7 @@ map_return:
464 * For mappings created using the direct modes (64 or 48) there are no 464 * For mappings created using the direct modes (64 or 48) there are no
465 * resources to release. 465 * resources to release.
466 */ 466 */
467void 467static void
468tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir) 468tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
469{ 469{
470 int i, entry; 470 int i, entry;
@@ -514,7 +514,7 @@ tioca_dma_unmap(struct pci_dev *pdev, dma_addr_t bus_addr, int dir)
514 * The mapping mode used is based on the devices dma_mask. As a last resort 514 * The mapping mode used is based on the devices dma_mask. As a last resort
515 * use the GART mapped mode. 515 * use the GART mapped mode.
516 */ 516 */
517uint64_t 517static uint64_t
518tioca_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count) 518tioca_dma_map(struct pci_dev *pdev, uint64_t paddr, size_t byte_count)
519{ 519{
520 uint64_t mapaddr; 520 uint64_t mapaddr;
@@ -580,7 +580,7 @@ tioca_error_intr_handler(int irq, void *arg, struct pt_regs *pt)
580 * On successful setup, returns the kernel version of tioca_common back to 580 * On successful setup, returns the kernel version of tioca_common back to
581 * the caller. 581 * the caller.
582 */ 582 */
583void * 583static void *
584tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft) 584tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft)
585{ 585{
586 struct tioca_common *tioca_common; 586 struct tioca_common *tioca_common;
diff --git a/arch/parisc/configs/712_defconfig b/arch/parisc/configs/712_defconfig
index 872085dea8a8..6efaa9293eef 100644
--- a/arch/parisc/configs/712_defconfig
+++ b/arch/parisc/configs/712_defconfig
@@ -506,7 +506,7 @@ CONFIG_HW_CONSOLE=y
506# 506#
507CONFIG_SERIAL_8250=y 507CONFIG_SERIAL_8250=y
508CONFIG_SERIAL_8250_CONSOLE=y 508CONFIG_SERIAL_8250_CONSOLE=y
509CONFIG_SERIAL_8250_NR_UARTS=8 509CONFIG_SERIAL_8250_NR_UARTS=17
510CONFIG_SERIAL_8250_EXTENDED=y 510CONFIG_SERIAL_8250_EXTENDED=y
511CONFIG_SERIAL_8250_MANY_PORTS=y 511CONFIG_SERIAL_8250_MANY_PORTS=y
512CONFIG_SERIAL_8250_SHARE_IRQ=y 512CONFIG_SERIAL_8250_SHARE_IRQ=y
diff --git a/arch/parisc/configs/a500_defconfig b/arch/parisc/configs/a500_defconfig
index d28ebfa1070d..30fc03ed0cfb 100644
--- a/arch/parisc/configs/a500_defconfig
+++ b/arch/parisc/configs/a500_defconfig
@@ -662,7 +662,7 @@ CONFIG_HW_CONSOLE=y
662CONFIG_SERIAL_8250=y 662CONFIG_SERIAL_8250=y
663CONFIG_SERIAL_8250_CONSOLE=y 663CONFIG_SERIAL_8250_CONSOLE=y
664CONFIG_SERIAL_8250_CS=m 664CONFIG_SERIAL_8250_CS=m
665CONFIG_SERIAL_8250_NR_UARTS=8 665CONFIG_SERIAL_8250_NR_UARTS=17
666CONFIG_SERIAL_8250_EXTENDED=y 666CONFIG_SERIAL_8250_EXTENDED=y
667CONFIG_SERIAL_8250_MANY_PORTS=y 667CONFIG_SERIAL_8250_MANY_PORTS=y
668CONFIG_SERIAL_8250_SHARE_IRQ=y 668CONFIG_SERIAL_8250_SHARE_IRQ=y
diff --git a/arch/parisc/configs/b180_defconfig b/arch/parisc/configs/b180_defconfig
index 1700d7aec686..46c9511f3229 100644
--- a/arch/parisc/configs/b180_defconfig
+++ b/arch/parisc/configs/b180_defconfig
@@ -514,7 +514,7 @@ CONFIG_HW_CONSOLE=y
514# 514#
515CONFIG_SERIAL_8250=y 515CONFIG_SERIAL_8250=y
516CONFIG_SERIAL_8250_CONSOLE=y 516CONFIG_SERIAL_8250_CONSOLE=y
517CONFIG_SERIAL_8250_NR_UARTS=4 517CONFIG_SERIAL_8250_NR_UARTS=13
518CONFIG_SERIAL_8250_EXTENDED=y 518CONFIG_SERIAL_8250_EXTENDED=y
519CONFIG_SERIAL_8250_MANY_PORTS=y 519CONFIG_SERIAL_8250_MANY_PORTS=y
520CONFIG_SERIAL_8250_SHARE_IRQ=y 520CONFIG_SERIAL_8250_SHARE_IRQ=y
diff --git a/arch/parisc/configs/c3000_defconfig b/arch/parisc/configs/c3000_defconfig
index b27980161c31..67aca6ccc9b0 100644
--- a/arch/parisc/configs/c3000_defconfig
+++ b/arch/parisc/configs/c3000_defconfig
@@ -661,7 +661,7 @@ CONFIG_HW_CONSOLE=y
661# 661#
662CONFIG_SERIAL_8250=y 662CONFIG_SERIAL_8250=y
663CONFIG_SERIAL_8250_CONSOLE=y 663CONFIG_SERIAL_8250_CONSOLE=y
664CONFIG_SERIAL_8250_NR_UARTS=4 664CONFIG_SERIAL_8250_NR_UARTS=13
665CONFIG_SERIAL_8250_EXTENDED=y 665CONFIG_SERIAL_8250_EXTENDED=y
666CONFIG_SERIAL_8250_MANY_PORTS=y 666CONFIG_SERIAL_8250_MANY_PORTS=y
667CONFIG_SERIAL_8250_SHARE_IRQ=y 667CONFIG_SERIAL_8250_SHARE_IRQ=y
diff --git a/arch/parisc/defconfig b/arch/parisc/defconfig
index ebd6301aa599..fdae21c503d7 100644
--- a/arch/parisc/defconfig
+++ b/arch/parisc/defconfig
@@ -517,7 +517,7 @@ CONFIG_HW_CONSOLE=y
517# 517#
518CONFIG_SERIAL_8250=y 518CONFIG_SERIAL_8250=y
519CONFIG_SERIAL_8250_CONSOLE=y 519CONFIG_SERIAL_8250_CONSOLE=y
520CONFIG_SERIAL_8250_NR_UARTS=4 520CONFIG_SERIAL_8250_NR_UARTS=13
521CONFIG_SERIAL_8250_EXTENDED=y 521CONFIG_SERIAL_8250_EXTENDED=y
522CONFIG_SERIAL_8250_MANY_PORTS=y 522CONFIG_SERIAL_8250_MANY_PORTS=y
523CONFIG_SERIAL_8250_SHARE_IRQ=y 523CONFIG_SERIAL_8250_SHARE_IRQ=y
diff --git a/drivers/firmware/pcdp.c b/drivers/firmware/pcdp.c
index 839b44a7e08b..53c95c0bbf46 100644
--- a/drivers/firmware/pcdp.c
+++ b/drivers/firmware/pcdp.c
@@ -16,6 +16,7 @@
16#include <linux/console.h> 16#include <linux/console.h>
17#include <linux/efi.h> 17#include <linux/efi.h>
18#include <linux/serial.h> 18#include <linux/serial.h>
19#include <asm/vga.h>
19#include "pcdp.h" 20#include "pcdp.h"
20 21
21static int __init 22static int __init
@@ -40,10 +41,27 @@ setup_serial_console(struct pcdp_uart *uart)
40} 41}
41 42
42static int __init 43static int __init
43setup_vga_console(struct pcdp_vga *vga) 44setup_vga_console(struct pcdp_device *dev)
44{ 45{
45#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 46#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
46 if (efi_mem_type(0xA0000) == EFI_CONVENTIONAL_MEMORY) { 47 u8 *if_ptr;
48
49 if_ptr = ((u8 *)dev + sizeof(struct pcdp_device));
50 if (if_ptr[0] == PCDP_IF_PCI) {
51 struct pcdp_if_pci if_pci;
52
53 /* struct copy since ifptr might not be correctly aligned */
54
55 memcpy(&if_pci, if_ptr, sizeof(if_pci));
56
57 if (if_pci.trans & PCDP_PCI_TRANS_IOPORT)
58 vga_console_iobase = if_pci.ioport_tra;
59
60 if (if_pci.trans & PCDP_PCI_TRANS_MMIO)
61 vga_console_membase = if_pci.mmio_tra;
62 }
63
64 if (efi_mem_type(vga_console_membase + 0xA0000) == EFI_CONVENTIONAL_MEMORY) {
47 printk(KERN_ERR "PCDP: VGA selected, but frame buffer is not MMIO!\n"); 65 printk(KERN_ERR "PCDP: VGA selected, but frame buffer is not MMIO!\n");
48 return -ENODEV; 66 return -ENODEV;
49 } 67 }
@@ -95,7 +113,7 @@ efi_setup_pcdp_console(char *cmdline)
95 dev = (struct pcdp_device *) ((u8 *) dev + dev->length)) { 113 dev = (struct pcdp_device *) ((u8 *) dev + dev->length)) {
96 if (dev->flags & PCDP_PRIMARY_CONSOLE) { 114 if (dev->flags & PCDP_PRIMARY_CONSOLE) {
97 if (dev->type == PCDP_CONSOLE_VGA) { 115 if (dev->type == PCDP_CONSOLE_VGA) {
98 return setup_vga_console((struct pcdp_vga *) dev); 116 return setup_vga_console(dev);
99 } 117 }
100 } 118 }
101 } 119 }
diff --git a/drivers/firmware/pcdp.h b/drivers/firmware/pcdp.h
index 1dc7c88b7b4d..e72cc47de33b 100644
--- a/drivers/firmware/pcdp.h
+++ b/drivers/firmware/pcdp.h
@@ -52,11 +52,34 @@ struct pcdp_uart {
52 u32 clock_rate; 52 u32 clock_rate;
53 u8 pci_prog_intfc; 53 u8 pci_prog_intfc;
54 u8 flags; 54 u8 flags;
55}; 55} __attribute__((packed));
56
57#define PCDP_IF_PCI 1
58
59/* pcdp_if_pci.trans */
60#define PCDP_PCI_TRANS_IOPORT 0x02
61#define PCDP_PCI_TRANS_MMIO 0x01
62
63struct pcdp_if_pci {
64 u8 interconnect;
65 u8 reserved;
66 u16 length;
67 u8 segment;
68 u8 bus;
69 u8 dev;
70 u8 fun;
71 u16 dev_id;
72 u16 vendor_id;
73 u32 acpi_interrupt;
74 u64 mmio_tra;
75 u64 ioport_tra;
76 u8 flags;
77 u8 trans;
78} __attribute__((packed));
56 79
57struct pcdp_vga { 80struct pcdp_vga {
58 u8 count; /* address space descriptors */ 81 u8 count; /* address space descriptors */
59}; 82} __attribute__((packed));
60 83
61/* pcdp_device.flags */ 84/* pcdp_device.flags */
62#define PCDP_PRIMARY_CONSOLE 1 85#define PCDP_PRIMARY_CONSOLE 1
@@ -66,7 +89,9 @@ struct pcdp_device {
66 u8 flags; 89 u8 flags;
67 u16 length; 90 u16 length;
68 u16 efi_index; 91 u16 efi_index;
69}; 92 /* next data is pcdp_if_pci or pcdp_if_acpi (not yet supported) */
93 /* next data is device specific type (currently only pcdp_vga) */
94} __attribute__((packed));
70 95
71struct pcdp { 96struct pcdp {
72 u8 signature[4]; 97 u8 signature[4];
@@ -81,4 +106,4 @@ struct pcdp {
81 u32 num_uarts; 106 u32 num_uarts;
82 struct pcdp_uart uart[0]; /* actual size is num_uarts */ 107 struct pcdp_uart uart[0]; /* actual size is num_uarts */
83 /* remainder of table is pcdp_device structures */ 108 /* remainder of table is pcdp_device structures */
84}; 109} __attribute__((packed));
diff --git a/drivers/i2c/chips/atxp1.c b/drivers/i2c/chips/atxp1.c
index 5c6597aa2c7f..0bcf82b4c07b 100644
--- a/drivers/i2c/chips/atxp1.c
+++ b/drivers/i2c/chips/atxp1.c
@@ -144,7 +144,7 @@ static ssize_t atxp1_storevcore(struct device *dev, struct device_attribute *att
144 if (vid == cvid) 144 if (vid == cvid)
145 return count; 145 return count;
146 146
147 dev_info(dev, "Setting VCore to %d mV (0x%02x)\n", vcore, vid); 147 dev_dbg(dev, "Setting VCore to %d mV (0x%02x)\n", vcore, vid);
148 148
149 /* Write every 25 mV step to increase stability */ 149 /* Write every 25 mV step to increase stability */
150 if (cvid > vid) { 150 if (cvid > vid) {
diff --git a/drivers/net/arm/etherh.c b/drivers/net/arm/etherh.c
index 2e28c201dcc0..942a2819576c 100644
--- a/drivers/net/arm/etherh.c
+++ b/drivers/net/arm/etherh.c
@@ -68,7 +68,6 @@ struct etherh_priv {
68 void __iomem *dma_base; 68 void __iomem *dma_base;
69 unsigned int id; 69 unsigned int id;
70 void __iomem *ctrl_port; 70 void __iomem *ctrl_port;
71 void __iomem *base;
72 unsigned char ctrl; 71 unsigned char ctrl;
73 u32 supported; 72 u32 supported;
74}; 73};
@@ -178,7 +177,7 @@ etherh_setif(struct net_device *dev)
178 switch (etherh_priv(dev)->id) { 177 switch (etherh_priv(dev)->id) {
179 case PROD_I3_ETHERLAN600: 178 case PROD_I3_ETHERLAN600:
180 case PROD_I3_ETHERLAN600A: 179 case PROD_I3_ETHERLAN600A:
181 addr = etherh_priv(dev)->base + EN0_RCNTHI; 180 addr = (void *)dev->base_addr + EN0_RCNTHI;
182 181
183 switch (dev->if_port) { 182 switch (dev->if_port) {
184 case IF_PORT_10BASE2: 183 case IF_PORT_10BASE2:
@@ -219,7 +218,7 @@ etherh_getifstat(struct net_device *dev)
219 switch (etherh_priv(dev)->id) { 218 switch (etherh_priv(dev)->id) {
220 case PROD_I3_ETHERLAN600: 219 case PROD_I3_ETHERLAN600:
221 case PROD_I3_ETHERLAN600A: 220 case PROD_I3_ETHERLAN600A:
222 addr = etherh_priv(dev)->base + EN0_RCNTHI; 221 addr = (void *)dev->base_addr + EN0_RCNTHI;
223 switch (dev->if_port) { 222 switch (dev->if_port) {
224 case IF_PORT_10BASE2: 223 case IF_PORT_10BASE2:
225 stat = 1; 224 stat = 1;
@@ -282,7 +281,7 @@ static void
282etherh_reset(struct net_device *dev) 281etherh_reset(struct net_device *dev)
283{ 282{
284 struct ei_device *ei_local = netdev_priv(dev); 283 struct ei_device *ei_local = netdev_priv(dev);
285 void __iomem *addr = etherh_priv(dev)->base; 284 void __iomem *addr = (void *)dev->base_addr;
286 285
287 writeb(E8390_NODMA+E8390_PAGE0+E8390_STOP, addr); 286 writeb(E8390_NODMA+E8390_PAGE0+E8390_STOP, addr);
288 287
@@ -328,7 +327,7 @@ etherh_block_output (struct net_device *dev, int count, const unsigned char *buf
328 327
329 ei_local->dmaing = 1; 328 ei_local->dmaing = 1;
330 329
331 addr = etherh_priv(dev)->base; 330 addr = (void *)dev->base_addr;
332 dma_base = etherh_priv(dev)->dma_base; 331 dma_base = etherh_priv(dev)->dma_base;
333 332
334 count = (count + 1) & ~1; 333 count = (count + 1) & ~1;
@@ -388,7 +387,7 @@ etherh_block_input (struct net_device *dev, int count, struct sk_buff *skb, int
388 387
389 ei_local->dmaing = 1; 388 ei_local->dmaing = 1;
390 389
391 addr = etherh_priv(dev)->base; 390 addr = (void *)dev->base_addr;
392 dma_base = etherh_priv(dev)->dma_base; 391 dma_base = etherh_priv(dev)->dma_base;
393 392
394 buf = skb->data; 393 buf = skb->data;
@@ -428,7 +427,7 @@ etherh_get_header (struct net_device *dev, struct e8390_pkt_hdr *hdr, int ring_p
428 427
429 ei_local->dmaing = 1; 428 ei_local->dmaing = 1;
430 429
431 addr = etherh_priv(dev)->base; 430 addr = (void *)dev->base_addr;
432 dma_base = etherh_priv(dev)->dma_base; 431 dma_base = etherh_priv(dev)->dma_base;
433 432
434 writeb (E8390_NODMA | E8390_PAGE0 | E8390_START, addr + E8390_CMD); 433 writeb (E8390_NODMA | E8390_PAGE0 | E8390_START, addr + E8390_CMD);
@@ -697,8 +696,7 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id)
697 eh->ctrl_port = eh->ioc_fast; 696 eh->ctrl_port = eh->ioc_fast;
698 } 697 }
699 698
700 eh->base = eh->memc + data->ns8390_offset; 699 dev->base_addr = (unsigned long)eh->memc + data->ns8390_offset;
701 dev->base_addr = (unsigned long)eh->base;
702 eh->dma_base = eh->memc + data->dataport_offset; 700 eh->dma_base = eh->memc + data->dataport_offset;
703 eh->ctrl_port += data->ctrlport_offset; 701 eh->ctrl_port += data->ctrlport_offset;
704 702
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index 34e75bc8f4cc..9224fc3184ea 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -105,7 +105,7 @@ static struct old_serial_port old_serial_port[] = {
105 SERIAL_PORT_DFNS /* defined in asm/serial.h */ 105 SERIAL_PORT_DFNS /* defined in asm/serial.h */
106}; 106};
107 107
108#define UART_NR (ARRAY_SIZE(old_serial_port) + CONFIG_SERIAL_8250_NR_UARTS) 108#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
109 109
110#ifdef CONFIG_SERIAL_8250_RSA 110#ifdef CONFIG_SERIAL_8250_RSA
111 111
@@ -993,21 +993,24 @@ static void autoconfig_irq(struct uart_8250_port *up)
993 up->port.irq = (irq > 0) ? irq : 0; 993 up->port.irq = (irq > 0) ? irq : 0;
994} 994}
995 995
996static inline void __stop_tx(struct uart_8250_port *p)
997{
998 if (p->ier & UART_IER_THRI) {
999 p->ier &= ~UART_IER_THRI;
1000 serial_out(p, UART_IER, p->ier);
1001 }
1002}
1003
996static void serial8250_stop_tx(struct uart_port *port, unsigned int tty_stop) 1004static void serial8250_stop_tx(struct uart_port *port, unsigned int tty_stop)
997{ 1005{
998 struct uart_8250_port *up = (struct uart_8250_port *)port; 1006 struct uart_8250_port *up = (struct uart_8250_port *)port;
999 1007
1000 if (up->ier & UART_IER_THRI) { 1008 __stop_tx(up);
1001 up->ier &= ~UART_IER_THRI;
1002 serial_out(up, UART_IER, up->ier);
1003 }
1004 1009
1005 /* 1010 /*
1006 * We only do this from uart_stop - if we run out of 1011 * We really want to stop the transmitter from sending.
1007 * characters to send, we don't want to prevent the
1008 * FIFO from emptying.
1009 */ 1012 */
1010 if (up->port.type == PORT_16C950 && tty_stop) { 1013 if (up->port.type == PORT_16C950) {
1011 up->acr |= UART_ACR_TXDIS; 1014 up->acr |= UART_ACR_TXDIS;
1012 serial_icr_write(up, UART_ACR, up->acr); 1015 serial_icr_write(up, UART_ACR, up->acr);
1013 } 1016 }
@@ -1031,10 +1034,11 @@ static void serial8250_start_tx(struct uart_port *port, unsigned int tty_start)
1031 transmit_chars(up); 1034 transmit_chars(up);
1032 } 1035 }
1033 } 1036 }
1037
1034 /* 1038 /*
1035 * We only do this from uart_start 1039 * Re-enable the transmitter if we disabled it.
1036 */ 1040 */
1037 if (tty_start && up->port.type == PORT_16C950) { 1041 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1038 up->acr &= ~UART_ACR_TXDIS; 1042 up->acr &= ~UART_ACR_TXDIS;
1039 serial_icr_write(up, UART_ACR, up->acr); 1043 serial_icr_write(up, UART_ACR, up->acr);
1040 } 1044 }
@@ -1155,7 +1159,7 @@ static _INLINE_ void transmit_chars(struct uart_8250_port *up)
1155 return; 1159 return;
1156 } 1160 }
1157 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 1161 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
1158 serial8250_stop_tx(&up->port, 0); 1162 __stop_tx(up);
1159 return; 1163 return;
1160 } 1164 }
1161 1165
@@ -1174,7 +1178,7 @@ static _INLINE_ void transmit_chars(struct uart_8250_port *up)
1174 DEBUG_INTR("THRE..."); 1178 DEBUG_INTR("THRE...");
1175 1179
1176 if (uart_circ_empty(xmit)) 1180 if (uart_circ_empty(xmit))
1177 serial8250_stop_tx(&up->port, 0); 1181 __stop_tx(up);
1178} 1182}
1179 1183
1180static _INLINE_ void check_modem_status(struct uart_8250_port *up) 1184static _INLINE_ void check_modem_status(struct uart_8250_port *up)
@@ -1376,13 +1380,10 @@ static unsigned int serial8250_tx_empty(struct uart_port *port)
1376static unsigned int serial8250_get_mctrl(struct uart_port *port) 1380static unsigned int serial8250_get_mctrl(struct uart_port *port)
1377{ 1381{
1378 struct uart_8250_port *up = (struct uart_8250_port *)port; 1382 struct uart_8250_port *up = (struct uart_8250_port *)port;
1379 unsigned long flags;
1380 unsigned char status; 1383 unsigned char status;
1381 unsigned int ret; 1384 unsigned int ret;
1382 1385
1383 spin_lock_irqsave(&up->port.lock, flags);
1384 status = serial_in(up, UART_MSR); 1386 status = serial_in(up, UART_MSR);
1385 spin_unlock_irqrestore(&up->port.lock, flags);
1386 1387
1387 ret = 0; 1388 ret = 0;
1388 if (status & UART_MSR_DCD) 1389 if (status & UART_MSR_DCD)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index e879bce160df..e0d0a470ddfc 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -86,7 +86,7 @@ config SERIAL_8250_ACPI
86 namespace, say Y here. If unsure, say N. 86 namespace, say Y here. If unsure, say N.
87 87
88config SERIAL_8250_NR_UARTS 88config SERIAL_8250_NR_UARTS
89 int "Maximum number of non-legacy 8250/16550 serial ports" 89 int "Maximum number of 8250/16550 serial ports"
90 depends on SERIAL_8250 90 depends on SERIAL_8250
91 default "4" 91 default "4"
92 help 92 help
diff --git a/drivers/serial/au1x00_uart.c b/drivers/serial/au1x00_uart.c
index 5400dc2c087e..6104aeef1243 100644
--- a/drivers/serial/au1x00_uart.c
+++ b/drivers/serial/au1x00_uart.c
@@ -556,13 +556,10 @@ static unsigned int serial8250_tx_empty(struct uart_port *port)
556static unsigned int serial8250_get_mctrl(struct uart_port *port) 556static unsigned int serial8250_get_mctrl(struct uart_port *port)
557{ 557{
558 struct uart_8250_port *up = (struct uart_8250_port *)port; 558 struct uart_8250_port *up = (struct uart_8250_port *)port;
559 unsigned long flags;
560 unsigned char status; 559 unsigned char status;
561 unsigned int ret; 560 unsigned int ret;
562 561
563 spin_lock_irqsave(&up->port.lock, flags);
564 status = serial_in(up, UART_MSR); 562 status = serial_in(up, UART_MSR);
565 spin_unlock_irqrestore(&up->port.lock, flags);
566 563
567 ret = 0; 564 ret = 0;
568 if (status & UART_MSR_DCD) 565 if (status & UART_MSR_DCD)
diff --git a/drivers/serial/ip22zilog.c b/drivers/serial/ip22zilog.c
index 3ea46c069f6f..ea5bf4d4daa3 100644
--- a/drivers/serial/ip22zilog.c
+++ b/drivers/serial/ip22zilog.c
@@ -518,27 +518,28 @@ static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id, struct pt_regs *re
518static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port) 518static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port)
519{ 519{
520 struct zilog_channel *channel; 520 struct zilog_channel *channel;
521 unsigned long flags;
522 unsigned char status; 521 unsigned char status;
523 522
524 spin_lock_irqsave(&port->lock, flags);
525
526 channel = ZILOG_CHANNEL_FROM_PORT(port); 523 channel = ZILOG_CHANNEL_FROM_PORT(port);
527 status = readb(&channel->control); 524 status = readb(&channel->control);
528 ZSDELAY(); 525 ZSDELAY();
529 526
530 spin_unlock_irqrestore(&port->lock, flags);
531
532 return status; 527 return status;
533} 528}
534 529
535/* The port lock is not held. */ 530/* The port lock is not held. */
536static unsigned int ip22zilog_tx_empty(struct uart_port *port) 531static unsigned int ip22zilog_tx_empty(struct uart_port *port)
537{ 532{
533 unsigned long flags;
538 unsigned char status; 534 unsigned char status;
539 unsigned int ret; 535 unsigned int ret;
540 536
537 spin_lock_irqsave(&port->lock, flags);
538
541 status = ip22zilog_read_channel_status(port); 539 status = ip22zilog_read_channel_status(port);
540
541 spin_unlock_irqrestore(&port->lock, flags);
542
542 if (status & Tx_BUF_EMP) 543 if (status & Tx_BUF_EMP)
543 ret = TIOCSER_TEMT; 544 ret = TIOCSER_TEMT;
544 else 545 else
@@ -547,7 +548,7 @@ static unsigned int ip22zilog_tx_empty(struct uart_port *port)
547 return ret; 548 return ret;
548} 549}
549 550
550/* The port lock is not held. */ 551/* The port lock is held and interrupts are disabled. */
551static unsigned int ip22zilog_get_mctrl(struct uart_port *port) 552static unsigned int ip22zilog_get_mctrl(struct uart_port *port)
552{ 553{
553 unsigned char status; 554 unsigned char status;
diff --git a/drivers/serial/mpsc.c b/drivers/serial/mpsc.c
index a2a643318002..e43276c6a954 100644
--- a/drivers/serial/mpsc.c
+++ b/drivers/serial/mpsc.c
@@ -1058,12 +1058,9 @@ mpsc_get_mctrl(struct uart_port *port)
1058{ 1058{
1059 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1059 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1060 u32 mflags, status; 1060 u32 mflags, status;
1061 ulong iflags;
1062 1061
1063 spin_lock_irqsave(&pi->port.lock, iflags);
1064 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m : 1062 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m :
1065 readl(pi->mpsc_base + MPSC_CHR_10); 1063 readl(pi->mpsc_base + MPSC_CHR_10);
1066 spin_unlock_irqrestore(&pi->port.lock, iflags);
1067 1064
1068 mflags = 0; 1065 mflags = 0;
1069 if (status & 0x1) 1066 if (status & 0x1)
diff --git a/drivers/serial/pmac_zilog.c b/drivers/serial/pmac_zilog.c
index 85abd8a045e0..1c9f71617123 100644
--- a/drivers/serial/pmac_zilog.c
+++ b/drivers/serial/pmac_zilog.c
@@ -604,7 +604,7 @@ static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
604/* 604/*
605 * Get Modem Control bits (only the input ones, the core will 605 * Get Modem Control bits (only the input ones, the core will
606 * or that with a cached value of the control ones) 606 * or that with a cached value of the control ones)
607 * The port lock is not held. 607 * The port lock is held and interrupts are disabled.
608 */ 608 */
609static unsigned int pmz_get_mctrl(struct uart_port *port) 609static unsigned int pmz_get_mctrl(struct uart_port *port)
610{ 610{
@@ -615,7 +615,7 @@ static unsigned int pmz_get_mctrl(struct uart_port *port)
615 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 615 if (ZS_IS_ASLEEP(uap) || uap->node == NULL)
616 return 0; 616 return 0;
617 617
618 status = pmz_peek_status(to_pmz(port)); 618 status = read_zsreg(uap, R0);
619 619
620 ret = 0; 620 ret = 0;
621 if (status & DCD) 621 if (status & DCD)
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c
index 08b08d6ae904..461c81c93207 100644
--- a/drivers/serial/pxa.c
+++ b/drivers/serial/pxa.c
@@ -274,14 +274,11 @@ static unsigned int serial_pxa_tx_empty(struct uart_port *port)
274static unsigned int serial_pxa_get_mctrl(struct uart_port *port) 274static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
275{ 275{
276 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 276 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
277 unsigned long flags;
278 unsigned char status; 277 unsigned char status;
279 unsigned int ret; 278 unsigned int ret;
280 279
281return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 280return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
282 spin_lock_irqsave(&up->port.lock, flags);
283 status = serial_in(up, UART_MSR); 281 status = serial_in(up, UART_MSR);
284 spin_unlock_irqrestore(&up->port.lock, flags);
285 282
286 ret = 0; 283 ret = 0;
287 if (status & UART_MSR_DCD) 284 if (status & UART_MSR_DCD)
diff --git a/drivers/serial/serial_core.c b/drivers/serial/serial_core.c
index 36b1ae083fb7..139863a787f3 100644
--- a/drivers/serial/serial_core.c
+++ b/drivers/serial/serial_core.c
@@ -182,6 +182,13 @@ static int uart_startup(struct uart_state *state, int init_hw)
182 uart_set_mctrl(port, TIOCM_RTS | TIOCM_DTR); 182 uart_set_mctrl(port, TIOCM_RTS | TIOCM_DTR);
183 } 183 }
184 184
185 if (info->flags & UIF_CTS_FLOW) {
186 spin_lock_irq(&port->lock);
187 if (!(port->ops->get_mctrl(port) & TIOCM_CTS))
188 info->tty->hw_stopped = 1;
189 spin_unlock_irq(&port->lock);
190 }
191
185 info->flags |= UIF_INITIALIZED; 192 info->flags |= UIF_INITIALIZED;
186 193
187 clear_bit(TTY_IO_ERROR, &info->tty->flags); 194 clear_bit(TTY_IO_ERROR, &info->tty->flags);
@@ -828,7 +835,10 @@ static int uart_tiocmget(struct tty_struct *tty, struct file *file)
828 if ((!file || !tty_hung_up_p(file)) && 835 if ((!file || !tty_hung_up_p(file)) &&
829 !(tty->flags & (1 << TTY_IO_ERROR))) { 836 !(tty->flags & (1 << TTY_IO_ERROR))) {
830 result = port->mctrl; 837 result = port->mctrl;
838
839 spin_lock_irq(&port->lock);
831 result |= port->ops->get_mctrl(port); 840 result |= port->ops->get_mctrl(port);
841 spin_unlock_irq(&port->lock);
832 } 842 }
833 up(&state->sem); 843 up(&state->sem);
834 844
@@ -1131,6 +1141,16 @@ static void uart_set_termios(struct tty_struct *tty, struct termios *old_termios
1131 spin_unlock_irqrestore(&state->port->lock, flags); 1141 spin_unlock_irqrestore(&state->port->lock, flags);
1132 } 1142 }
1133 1143
1144 /* Handle turning on CRTSCTS */
1145 if (!(old_termios->c_cflag & CRTSCTS) && (cflag & CRTSCTS)) {
1146 spin_lock_irqsave(&state->port->lock, flags);
1147 if (!(state->port->ops->get_mctrl(state->port) & TIOCM_CTS)) {
1148 tty->hw_stopped = 1;
1149 state->port->ops->stop_tx(state->port, 0);
1150 }
1151 spin_unlock_irqrestore(&state->port->lock, flags);
1152 }
1153
1134#if 0 1154#if 0
1135 /* 1155 /*
1136 * No need to wake up processes in open wait, since they 1156 * No need to wake up processes in open wait, since they
@@ -1369,6 +1389,7 @@ uart_block_til_ready(struct file *filp, struct uart_state *state)
1369 DECLARE_WAITQUEUE(wait, current); 1389 DECLARE_WAITQUEUE(wait, current);
1370 struct uart_info *info = state->info; 1390 struct uart_info *info = state->info;
1371 struct uart_port *port = state->port; 1391 struct uart_port *port = state->port;
1392 unsigned int mctrl;
1372 1393
1373 info->blocked_open++; 1394 info->blocked_open++;
1374 state->count--; 1395 state->count--;
@@ -1416,7 +1437,10 @@ uart_block_til_ready(struct file *filp, struct uart_state *state)
1416 * and wait for the carrier to indicate that the 1437 * and wait for the carrier to indicate that the
1417 * modem is ready for us. 1438 * modem is ready for us.
1418 */ 1439 */
1419 if (port->ops->get_mctrl(port) & TIOCM_CAR) 1440 spin_lock_irq(&port->lock);
1441 mctrl = port->ops->get_mctrl(port);
1442 spin_unlock_irq(&port->lock);
1443 if (mctrl & TIOCM_CAR)
1420 break; 1444 break;
1421 1445
1422 up(&state->sem); 1446 up(&state->sem);
@@ -1618,7 +1642,9 @@ static int uart_line_info(char *buf, struct uart_driver *drv, int i)
1618 1642
1619 if(capable(CAP_SYS_ADMIN)) 1643 if(capable(CAP_SYS_ADMIN))
1620 { 1644 {
1645 spin_lock_irq(&port->lock);
1621 status = port->ops->get_mctrl(port); 1646 status = port->ops->get_mctrl(port);
1647 spin_unlock_irq(&port->lock);
1622 1648
1623 ret += sprintf(buf + ret, " tx:%d rx:%d", 1649 ret += sprintf(buf + ret, " tx:%d rx:%d",
1624 port->icount.tx, port->icount.rx); 1650 port->icount.tx, port->icount.rx);
diff --git a/drivers/serial/serial_txx9.c b/drivers/serial/serial_txx9.c
index 3f1051a4a13f..d085030df70b 100644
--- a/drivers/serial/serial_txx9.c
+++ b/drivers/serial/serial_txx9.c
@@ -442,13 +442,10 @@ static unsigned int serial_txx9_tx_empty(struct uart_port *port)
442static unsigned int serial_txx9_get_mctrl(struct uart_port *port) 442static unsigned int serial_txx9_get_mctrl(struct uart_port *port)
443{ 443{
444 struct uart_txx9_port *up = (struct uart_txx9_port *)port; 444 struct uart_txx9_port *up = (struct uart_txx9_port *)port;
445 unsigned long flags;
446 unsigned int ret; 445 unsigned int ret;
447 446
448 spin_lock_irqsave(&up->port.lock, flags);
449 ret = ((sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS) 447 ret = ((sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS)
450 | ((sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS); 448 | ((sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS);
451 spin_unlock_irqrestore(&up->port.lock, flags);
452 449
453 return ret; 450 return ret;
454} 451}
diff --git a/drivers/serial/sunsab.c b/drivers/serial/sunsab.c
index 10e2990a40d4..8d198880756a 100644
--- a/drivers/serial/sunsab.c
+++ b/drivers/serial/sunsab.c
@@ -426,18 +426,15 @@ static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
426 sunsab_tx_idle(up); 426 sunsab_tx_idle(up);
427} 427}
428 428
429/* port->lock is not held. */ 429/* port->lock is held by caller and interrupts are disabled. */
430static unsigned int sunsab_get_mctrl(struct uart_port *port) 430static unsigned int sunsab_get_mctrl(struct uart_port *port)
431{ 431{
432 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 432 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
433 unsigned long flags;
434 unsigned char val; 433 unsigned char val;
435 unsigned int result; 434 unsigned int result;
436 435
437 result = 0; 436 result = 0;
438 437
439 spin_lock_irqsave(&up->port.lock, flags);
440
441 val = readb(&up->regs->r.pvr); 438 val = readb(&up->regs->r.pvr);
442 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR; 439 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
443 440
@@ -447,8 +444,6 @@ static unsigned int sunsab_get_mctrl(struct uart_port *port)
447 val = readb(&up->regs->r.star); 444 val = readb(&up->regs->r.star);
448 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0; 445 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
449 446
450 spin_unlock_irqrestore(&up->port.lock, flags);
451
452 return result; 447 return result;
453} 448}
454 449
diff --git a/drivers/serial/sunsu.c b/drivers/serial/sunsu.c
index ddc97c905e14..d57a3553aea3 100644
--- a/drivers/serial/sunsu.c
+++ b/drivers/serial/sunsu.c
@@ -572,13 +572,10 @@ static unsigned int sunsu_tx_empty(struct uart_port *port)
572static unsigned int sunsu_get_mctrl(struct uart_port *port) 572static unsigned int sunsu_get_mctrl(struct uart_port *port)
573{ 573{
574 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port; 574 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
575 unsigned long flags;
576 unsigned char status; 575 unsigned char status;
577 unsigned int ret; 576 unsigned int ret;
578 577
579 spin_lock_irqsave(&up->port.lock, flags);
580 status = serial_in(up, UART_MSR); 578 status = serial_in(up, UART_MSR);
581 spin_unlock_irqrestore(&up->port.lock, flags);
582 579
583 ret = 0; 580 ret = 0;
584 if (status & UART_MSR_DCD) 581 if (status & UART_MSR_DCD)
diff --git a/drivers/serial/sunzilog.c b/drivers/serial/sunzilog.c
index 8e65206d3d76..bff42a7b89d0 100644
--- a/drivers/serial/sunzilog.c
+++ b/drivers/serial/sunzilog.c
@@ -610,27 +610,28 @@ static irqreturn_t sunzilog_interrupt(int irq, void *dev_id, struct pt_regs *reg
610static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port) 610static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
611{ 611{
612 struct zilog_channel __iomem *channel; 612 struct zilog_channel __iomem *channel;
613 unsigned long flags;
614 unsigned char status; 613 unsigned char status;
615 614
616 spin_lock_irqsave(&port->lock, flags);
617
618 channel = ZILOG_CHANNEL_FROM_PORT(port); 615 channel = ZILOG_CHANNEL_FROM_PORT(port);
619 status = sbus_readb(&channel->control); 616 status = sbus_readb(&channel->control);
620 ZSDELAY(); 617 ZSDELAY();
621 618
622 spin_unlock_irqrestore(&port->lock, flags);
623
624 return status; 619 return status;
625} 620}
626 621
627/* The port lock is not held. */ 622/* The port lock is not held. */
628static unsigned int sunzilog_tx_empty(struct uart_port *port) 623static unsigned int sunzilog_tx_empty(struct uart_port *port)
629{ 624{
625 unsigned long flags;
630 unsigned char status; 626 unsigned char status;
631 unsigned int ret; 627 unsigned int ret;
632 628
629 spin_lock_irqsave(&port->lock, flags);
630
633 status = sunzilog_read_channel_status(port); 631 status = sunzilog_read_channel_status(port);
632
633 spin_unlock_irqrestore(&port->lock, flags);
634
634 if (status & Tx_BUF_EMP) 635 if (status & Tx_BUF_EMP)
635 ret = TIOCSER_TEMT; 636 ret = TIOCSER_TEMT;
636 else 637 else
@@ -639,7 +640,7 @@ static unsigned int sunzilog_tx_empty(struct uart_port *port)
639 return ret; 640 return ret;
640} 641}
641 642
642/* The port lock is not held. */ 643/* The port lock is held and interrupts are disabled. */
643static unsigned int sunzilog_get_mctrl(struct uart_port *port) 644static unsigned int sunzilog_get_mctrl(struct uart_port *port)
644{ 645{
645 unsigned char status; 646 unsigned char status;
diff --git a/fs/reiserfs/ioctl.c b/fs/reiserfs/ioctl.c
index 94dc42475a04..76caedf737f2 100644
--- a/fs/reiserfs/ioctl.c
+++ b/fs/reiserfs/ioctl.c
@@ -36,10 +36,16 @@ int reiserfs_ioctl (struct inode * inode, struct file * filp, unsigned int cmd,
36 /* following two cases are taken from fs/ext2/ioctl.c by Remy 36 /* following two cases are taken from fs/ext2/ioctl.c by Remy
37 Card (card@masi.ibp.fr) */ 37 Card (card@masi.ibp.fr) */
38 case REISERFS_IOC_GETFLAGS: 38 case REISERFS_IOC_GETFLAGS:
39 if (!reiserfs_attrs (inode->i_sb))
40 return -ENOTTY;
41
39 flags = REISERFS_I(inode) -> i_attrs; 42 flags = REISERFS_I(inode) -> i_attrs;
40 i_attrs_to_sd_attrs( inode, ( __u16 * ) &flags ); 43 i_attrs_to_sd_attrs( inode, ( __u16 * ) &flags );
41 return put_user(flags, (int __user *) arg); 44 return put_user(flags, (int __user *) arg);
42 case REISERFS_IOC_SETFLAGS: { 45 case REISERFS_IOC_SETFLAGS: {
46 if (!reiserfs_attrs (inode->i_sb))
47 return -ENOTTY;
48
43 if (IS_RDONLY(inode)) 49 if (IS_RDONLY(inode))
44 return -EROFS; 50 return -EROFS;
45 51
diff --git a/fs/reiserfs/super.c b/fs/reiserfs/super.c
index 660aefca1fd2..d50a5cd860ce 100644
--- a/fs/reiserfs/super.c
+++ b/fs/reiserfs/super.c
@@ -1066,6 +1066,8 @@ static void handle_attrs( struct super_block *s )
1066 reiserfs_warning(s, "reiserfs: cannot support attributes until flag is set in super-block" ); 1066 reiserfs_warning(s, "reiserfs: cannot support attributes until flag is set in super-block" );
1067 REISERFS_SB(s) -> s_mount_opt &= ~ ( 1 << REISERFS_ATTRS ); 1067 REISERFS_SB(s) -> s_mount_opt &= ~ ( 1 << REISERFS_ATTRS );
1068 } 1068 }
1069 } else if (le32_to_cpu( rs -> s_flags ) & reiserfs_attrs_cleared) {
1070 REISERFS_SB(s)->s_mount_opt |= REISERFS_ATTRS;
1069 } 1071 }
1070} 1072}
1071 1073
diff --git a/include/asm-alpha/serial.h b/include/asm-alpha/serial.h
index 7b2d9ee95a44..7e4b2987d453 100644
--- a/include/asm-alpha/serial.h
+++ b/include/asm-alpha/serial.h
@@ -22,54 +22,9 @@
22#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 22#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
23#endif 23#endif
24 24
25#ifdef CONFIG_SERIAL_MANY_PORTS 25#define SERIAL_PORT_DFNS \
26#define FOURPORT_FLAGS ASYNC_FOURPORT
27#define ACCENT_FLAGS 0
28#define BOCA_FLAGS 0
29#endif
30
31#define STD_SERIAL_PORT_DEFNS \
32 /* UART CLK PORT IRQ FLAGS */ \ 26 /* UART CLK PORT IRQ FLAGS */ \
33 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 27 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
34 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 28 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
35 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 29 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
36 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 30 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
37
38
39#ifdef CONFIG_SERIAL_MANY_PORTS
40#define EXTRA_SERIAL_PORT_DEFNS \
41 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
42 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
43 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
44 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
45 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
46 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
47 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
48 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
49 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
50 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
51 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
52 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
53 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
54 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
55 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
56 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
57 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
58 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
59 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
60 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
61 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
62 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
63 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
64 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
65 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
66 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
67 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
68 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
69#else
70#define EXTRA_SERIAL_PORT_DEFNS
71#endif
72
73#define SERIAL_PORT_DFNS \
74 STD_SERIAL_PORT_DEFNS \
75 EXTRA_SERIAL_PORT_DEFNS
diff --git a/include/asm-arm/arch-pxa/debug-macro.S b/include/asm-arm/arch-pxa/debug-macro.S
index f288e74b67c2..b6ec68879176 100644
--- a/include/asm-arm/arch-pxa/debug-macro.S
+++ b/include/asm-arm/arch-pxa/debug-macro.S
@@ -11,6 +11,8 @@
11 * 11 *
12*/ 12*/
13 13
14#include "hardware.h"
15
14 .macro addruart,rx 16 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0 17 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled? 18 tst \rx, #1 @ MMU enabled?
diff --git a/include/asm-arm/hardware/arm_timer.h b/include/asm-arm/hardware/arm_timer.h
new file mode 100644
index 000000000000..04be3bdf46b8
--- /dev/null
+++ b/include/asm-arm/hardware/arm_timer.h
@@ -0,0 +1,21 @@
1#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H
2#define __ASM_ARM_HARDWARE_ARM_TIMER_H
3
4#define TIMER_LOAD 0x00
5#define TIMER_VALUE 0x04
6#define TIMER_CTRL 0x08
7#define TIMER_CTRL_ONESHOT (1 << 0)
8#define TIMER_CTRL_32BIT (1 << 1)
9#define TIMER_CTRL_DIV1 (0 << 2)
10#define TIMER_CTRL_DIV16 (1 << 2)
11#define TIMER_CTRL_DIV256 (2 << 2)
12#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */
13#define TIMER_CTRL_PERIODIC (1 << 6)
14#define TIMER_CTRL_ENABLE (1 << 7)
15
16#define TIMER_INTCLR 0x0c
17#define TIMER_RIS 0x10
18#define TIMER_MIS 0x14
19#define TIMER_BGLOAD 0x18
20
21#endif
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 3d0d2860b6db..cdf49f442fd2 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -290,7 +290,6 @@ do { \
290}) 290})
291 291
292#ifdef CONFIG_SMP 292#ifdef CONFIG_SMP
293#error SMP not supported
294 293
295#define smp_mb() mb() 294#define smp_mb() mb()
296#define smp_rmb() rmb() 295#define smp_rmb() rmb()
@@ -304,6 +303,8 @@ do { \
304#define smp_wmb() barrier() 303#define smp_wmb() barrier()
305#define smp_read_barrier_depends() do { } while(0) 304#define smp_read_barrier_depends() do { } while(0)
306 305
306#endif /* CONFIG_SMP */
307
307#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) 308#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
308/* 309/*
309 * On the StrongARM, "swp" is terminally broken since it bypasses the 310 * On the StrongARM, "swp" is terminally broken since it bypasses the
@@ -316,9 +317,16 @@ do { \
316 * 317 *
317 * We choose (1) since its the "easiest" to achieve here and is not 318 * We choose (1) since its the "easiest" to achieve here and is not
318 * dependent on the processor type. 319 * dependent on the processor type.
320 *
321 * NOTE that this solution won't work on an SMP system, so explcitly
322 * forbid it here.
319 */ 323 */
324#ifdef CONFIG_SMP
325#error SMP is not supported on SA1100/SA110
326#else
320#define swp_is_buggy 327#define swp_is_buggy
321#endif 328#endif
329#endif
322 330
323static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) 331static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
324{ 332{
@@ -361,8 +369,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
361 return ret; 369 return ret;
362} 370}
363 371
364#endif /* CONFIG_SMP */
365
366#endif /* __ASSEMBLY__ */ 372#endif /* __ASSEMBLY__ */
367 373
368#define arch_align_stack(x) (x) 374#define arch_align_stack(x) (x)
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 8a864b118569..9387a5e1ffe0 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -235,7 +235,7 @@ extern struct cpu_tlb_fns cpu_tlb;
235 235
236#define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f))) 236#define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
237 237
238static inline void flush_tlb_all(void) 238static inline void local_flush_tlb_all(void)
239{ 239{
240 const int zero = 0; 240 const int zero = 0;
241 const unsigned int __tlb_flag = __cpu_tlb_flags; 241 const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -253,7 +253,7 @@ static inline void flush_tlb_all(void)
253 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero)); 253 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
254} 254}
255 255
256static inline void flush_tlb_mm(struct mm_struct *mm) 256static inline void local_flush_tlb_mm(struct mm_struct *mm)
257{ 257{
258 const int zero = 0; 258 const int zero = 0;
259 const int asid = ASID(mm); 259 const int asid = ASID(mm);
@@ -282,7 +282,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
282} 282}
283 283
284static inline void 284static inline void
285flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) 285local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
286{ 286{
287 const int zero = 0; 287 const int zero = 0;
288 const unsigned int __tlb_flag = __cpu_tlb_flags; 288 const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -313,7 +313,7 @@ flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
313 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr)); 313 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
314} 314}
315 315
316static inline void flush_tlb_kernel_page(unsigned long kaddr) 316static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
317{ 317{
318 const int zero = 0; 318 const int zero = 0;
319 const unsigned int __tlb_flag = __cpu_tlb_flags; 319 const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -384,8 +384,24 @@ static inline void clean_pmd_entry(pmd_t *pmd)
384/* 384/*
385 * Convert calls to our calling convention. 385 * Convert calls to our calling convention.
386 */ 386 */
387#define flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma) 387#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
388#define flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e) 388#define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
389
390#ifndef CONFIG_SMP
391#define flush_tlb_all local_flush_tlb_all
392#define flush_tlb_mm local_flush_tlb_mm
393#define flush_tlb_page local_flush_tlb_page
394#define flush_tlb_kernel_page local_flush_tlb_kernel_page
395#define flush_tlb_range local_flush_tlb_range
396#define flush_tlb_kernel_range local_flush_tlb_kernel_range
397#else
398extern void flush_tlb_all(void);
399extern void flush_tlb_mm(struct mm_struct *mm);
400extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
401extern void flush_tlb_kernel_page(unsigned long kaddr);
402extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
403extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
404#endif
389 405
390/* 406/*
391 * if PG_dcache_dirty is set for the page, we need to ensure that any 407 * if PG_dcache_dirty is set for the page, we need to ensure that any
diff --git a/include/asm-arm26/serial.h b/include/asm-arm26/serial.h
index 21e1df31f086..5fc747d1b501 100644
--- a/include/asm-arm26/serial.h
+++ b/include/asm-arm26/serial.h
@@ -30,34 +30,16 @@
30#if defined(CONFIG_ARCH_A5K) 30#if defined(CONFIG_ARCH_A5K)
31 /* UART CLK PORT IRQ FLAGS */ 31 /* UART CLK PORT IRQ FLAGS */
32 32
33#define STD_SERIAL_PORT_DEFNS \ 33#define SERIAL_PORT_DFNS \
34 { 0, BASE_BAUD, 0x3F8, 10, STD_COM_FLAGS }, /* ttyS0 */ \ 34 { 0, BASE_BAUD, 0x3F8, 10, STD_COM_FLAGS }, /* ttyS0 */ \
35 { 0, BASE_BAUD, 0x2F8, 10, STD_COM_FLAGS }, /* ttyS1 */ 35 { 0, BASE_BAUD, 0x2F8, 10, STD_COM_FLAGS }, /* ttyS1 */
36 36
37#else 37#else
38 38
39#define STD_SERIAL_PORT_DEFNS \ 39#define SERIAL_PORT_DFNS \
40 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS0 */ \ 40 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS0 */ \
41 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS1 */ 41 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS1 */
42 42
43#endif 43#endif
44 44
45#define EXTRA_SERIAL_PORT_DEFNS \
46 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS2 */ \
47 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS3 */ \
48 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS4 */ \
49 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS5 */ \
50 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS6 */ \
51 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS7 */ \
52 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS8 */ \
53 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS9 */ \
54 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS10 */ \
55 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS11 */ \
56 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS12 */ \
57 { 0, BASE_BAUD, 0 , 0, STD_COM_FLAGS }, /* ttyS13 */
58
59#define SERIAL_PORT_DFNS \
60 STD_SERIAL_PORT_DEFNS \
61 EXTRA_SERIAL_PORT_DEFNS
62
63#endif 45#endif
diff --git a/include/asm-i386/serial.h b/include/asm-i386/serial.h
index 21ddecc77c77..e1ecfccb743b 100644
--- a/include/asm-i386/serial.h
+++ b/include/asm-i386/serial.h
@@ -22,109 +22,9 @@
22#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 22#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
23#endif 23#endif
24 24
25#ifdef CONFIG_SERIAL_MANY_PORTS 25#define SERIAL_PORT_DFNS \
26#define FOURPORT_FLAGS ASYNC_FOURPORT
27#define ACCENT_FLAGS 0
28#define BOCA_FLAGS 0
29#define HUB6_FLAGS 0
30#endif
31
32#define MCA_COM_FLAGS (STD_COM_FLAGS|ASYNC_BOOT_ONLYMCA)
33
34/*
35 * The following define the access methods for the HUB6 card. All
36 * access is through two ports for all 24 possible chips. The card is
37 * selected through the high 2 bits, the port on that card with the
38 * "middle" 3 bits, and the register on that port with the bottom
39 * 3 bits.
40 *
41 * While the access port and interrupt is configurable, the default
42 * port locations are 0x302 for the port control register, and 0x303
43 * for the data read/write register. Normally, the interrupt is at irq3
44 * but can be anything from 3 to 7 inclusive. Note that using 3 will
45 * require disabling com2.
46 */
47
48#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
49
50#define STD_SERIAL_PORT_DEFNS \
51 /* UART CLK PORT IRQ FLAGS */ \ 26 /* UART CLK PORT IRQ FLAGS */ \
52 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 27 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
53 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 28 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
54 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 29 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
55 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 30 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
56
57
58#ifdef CONFIG_SERIAL_MANY_PORTS
59#define EXTRA_SERIAL_PORT_DEFNS \
60 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
61 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
62 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
63 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
64 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
65 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
66 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
67 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
68 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
69 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
70 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
71 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
72 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
73 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
74 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
75 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
76 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
77 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
78 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
79 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
80 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
81 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
82 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
83 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
84 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
85 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
86 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
87 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
88#else
89#define EXTRA_SERIAL_PORT_DEFNS
90#endif
91
92/* You can have up to four HUB6's in the system, but I've only
93 * included two cards here for a total of twelve ports.
94 */
95#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
96#define HUB6_SERIAL_PORT_DFNS \
97 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
98 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
99 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
100 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
101 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
102 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
103 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
104 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
105 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
106 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
107 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
108 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
109#else
110#define HUB6_SERIAL_PORT_DFNS
111#endif
112
113#ifdef CONFIG_MCA
114#define MCA_SERIAL_PORT_DFNS \
115 { 0, BASE_BAUD, 0x3220, 3, MCA_COM_FLAGS }, \
116 { 0, BASE_BAUD, 0x3228, 3, MCA_COM_FLAGS }, \
117 { 0, BASE_BAUD, 0x4220, 3, MCA_COM_FLAGS }, \
118 { 0, BASE_BAUD, 0x4228, 3, MCA_COM_FLAGS }, \
119 { 0, BASE_BAUD, 0x5220, 3, MCA_COM_FLAGS }, \
120 { 0, BASE_BAUD, 0x5228, 3, MCA_COM_FLAGS },
121#else
122#define MCA_SERIAL_PORT_DFNS
123#endif
124
125#define SERIAL_PORT_DFNS \
126 STD_SERIAL_PORT_DEFNS \
127 EXTRA_SERIAL_PORT_DEFNS \
128 HUB6_SERIAL_PORT_DFNS \
129 MCA_SERIAL_PORT_DFNS
130
diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h
index 0096e7e05012..e3e5fededb04 100644
--- a/include/asm-ia64/mmu_context.h
+++ b/include/asm-ia64/mmu_context.h
@@ -132,6 +132,9 @@ reload_context (mm_context_t context)
132 ia64_srlz_i(); /* srlz.i implies srlz.d */ 132 ia64_srlz_i(); /* srlz.i implies srlz.d */
133} 133}
134 134
135/*
136 * Must be called with preemption off
137 */
135static inline void 138static inline void
136activate_context (struct mm_struct *mm) 139activate_context (struct mm_struct *mm)
137{ 140{
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
index 1bfdfb4d7b01..103d745dc5f2 100644
--- a/include/asm-ia64/sn/addrs.h
+++ b/include/asm-ia64/sn/addrs.h
@@ -216,6 +216,10 @@
216#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK) 216#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
217 217
218 218
219#define TIO_IOSPACE_ADDR(n,x) \
220 /* Move in the Chiplet ID for TIO Local Block MMR */ \
221 (REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2))
222
219/* 223/*
220 * The following macros produce the correct base virtual address for 224 * The following macros produce the correct base virtual address for
221 * the hub registers. The REMOTE_HUB_* macro produce 225 * the hub registers. The REMOTE_HUB_* macro produce
@@ -233,13 +237,16 @@
233#define REMOTE_HUB_ADDR(n,x) \ 237#define REMOTE_HUB_ADDR(n,x) \
234 ((n & 1) ? \ 238 ((n & 1) ? \
235 /* TIO: */ \ 239 /* TIO: */ \
236 ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \ 240 (is_shub2() ? \
237 : /* SHUB: */ \ 241 /* TIO on Shub2 */ \
238 (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))\ 242 (volatile u64 *)(TIO_IOSPACE_ADDR(n,x)) \
243 : /* TIO on shub1 */ \
244 (volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
245 \
246 : /* SHUB1 and SHUB2 MMRs: */ \
247 (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x))) \
239 : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x))))) 248 : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
240 249
241
242
243#define HUB_L(x) (*((volatile typeof(*x) *)x)) 250#define HUB_L(x) (*((volatile typeof(*x) *)x))
244#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d)) 251#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
245 252
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
index 08050d37b662..2e5f0aa38889 100644
--- a/include/asm-ia64/sn/l1.h
+++ b/include/asm-ia64/sn/l1.h
@@ -33,5 +33,6 @@
33#define L1_BRICKTYPE_PA 0x6a /* j */ 33#define L1_BRICKTYPE_PA 0x6a /* j */
34#define L1_BRICKTYPE_IA 0x6b /* k */ 34#define L1_BRICKTYPE_IA 0x6b /* k */
35#define L1_BRICKTYPE_ATHENA 0x2b /* + */ 35#define L1_BRICKTYPE_ATHENA 0x2b /* + */
36#define L1_BRICKTYPE_DAYTONA 0x7a /* z */
36 37
37#endif /* _ASM_IA64_SN_L1_H */ 38#endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h
index 323fa0cd8d83..7de1d1d4b71a 100644
--- a/include/asm-ia64/sn/shub_mmr.h
+++ b/include/asm-ia64/sn/shub_mmr.h
@@ -14,96 +14,98 @@
14/* Register "SH_IPI_INT" */ 14/* Register "SH_IPI_INT" */
15/* SHub Inter-Processor Interrupt Registers */ 15/* SHub Inter-Processor Interrupt Registers */
16/* ==================================================================== */ 16/* ==================================================================== */
17#define SH1_IPI_INT 0x0000000110000380 17#define SH1_IPI_INT __IA64_UL_CONST(0x0000000110000380)
18#define SH2_IPI_INT 0x0000000010000380 18#define SH2_IPI_INT __IA64_UL_CONST(0x0000000010000380)
19 19
20/* SH_IPI_INT_TYPE */ 20/* SH_IPI_INT_TYPE */
21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
22#define SH_IPI_INT_TYPE_SHFT 0 22#define SH_IPI_INT_TYPE_SHFT 0
23#define SH_IPI_INT_TYPE_MASK 0x0000000000000007 23#define SH_IPI_INT_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
24 24
25/* SH_IPI_INT_AGT */ 25/* SH_IPI_INT_AGT */
26/* Description: Agent, must be 0 for SHub */ 26/* Description: Agent, must be 0 for SHub */
27#define SH_IPI_INT_AGT_SHFT 3 27#define SH_IPI_INT_AGT_SHFT 3
28#define SH_IPI_INT_AGT_MASK 0x0000000000000008 28#define SH_IPI_INT_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
29 29
30/* SH_IPI_INT_PID */ 30/* SH_IPI_INT_PID */
31/* Description: Processor ID, same setting as on targeted McKinley */ 31/* Description: Processor ID, same setting as on targeted McKinley */
32#define SH_IPI_INT_PID_SHFT 4 32#define SH_IPI_INT_PID_SHFT 4
33#define SH_IPI_INT_PID_MASK 0x00000000000ffff0 33#define SH_IPI_INT_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
34 34
35/* SH_IPI_INT_BASE */ 35/* SH_IPI_INT_BASE */
36/* Description: Optional interrupt vector area, 2MB aligned */ 36/* Description: Optional interrupt vector area, 2MB aligned */
37#define SH_IPI_INT_BASE_SHFT 21 37#define SH_IPI_INT_BASE_SHFT 21
38#define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000 38#define SH_IPI_INT_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
39 39
40/* SH_IPI_INT_IDX */ 40/* SH_IPI_INT_IDX */
41/* Description: Targeted McKinley interrupt vector */ 41/* Description: Targeted McKinley interrupt vector */
42#define SH_IPI_INT_IDX_SHFT 52 42#define SH_IPI_INT_IDX_SHFT 52
43#define SH_IPI_INT_IDX_MASK 0x0ff0000000000000 43#define SH_IPI_INT_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
44 44
45/* SH_IPI_INT_SEND */ 45/* SH_IPI_INT_SEND */
46/* Description: Send Interrupt Message to PI, This generates a puls */ 46/* Description: Send Interrupt Message to PI, This generates a puls */
47#define SH_IPI_INT_SEND_SHFT 63 47#define SH_IPI_INT_SEND_SHFT 63
48#define SH_IPI_INT_SEND_MASK 0x8000000000000000 48#define SH_IPI_INT_SEND_MASK __IA64_UL_CONST(0x8000000000000000)
49 49
50/* ==================================================================== */ 50/* ==================================================================== */
51/* Register "SH_EVENT_OCCURRED" */ 51/* Register "SH_EVENT_OCCURRED" */
52/* SHub Interrupt Event Occurred */ 52/* SHub Interrupt Event Occurred */
53/* ==================================================================== */ 53/* ==================================================================== */
54#define SH1_EVENT_OCCURRED 0x0000000110010000 54#define SH1_EVENT_OCCURRED __IA64_UL_CONST(0x0000000110010000)
55#define SH1_EVENT_OCCURRED_ALIAS 0x0000000110010008 55#define SH1_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000110010008)
56#define SH2_EVENT_OCCURRED 0x0000000010010000 56#define SH2_EVENT_OCCURRED __IA64_UL_CONST(0x0000000010010000)
57#define SH2_EVENT_OCCURRED_ALIAS 0x0000000010010008 57#define SH2_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000010010008)
58 58
59/* ==================================================================== */ 59/* ==================================================================== */
60/* Register "SH_PI_CAM_CONTROL" */ 60/* Register "SH_PI_CAM_CONTROL" */
61/* CRB CAM MMR Access Control */ 61/* CRB CAM MMR Access Control */
62/* ==================================================================== */ 62/* ==================================================================== */
63#define SH1_PI_CAM_CONTROL 0x0000000120050300 63#define SH1_PI_CAM_CONTROL __IA64_UL_CONST(0x0000000120050300)
64 64
65/* ==================================================================== */ 65/* ==================================================================== */
66/* Register "SH_SHUB_ID" */ 66/* Register "SH_SHUB_ID" */
67/* SHub ID Number */ 67/* SHub ID Number */
68/* ==================================================================== */ 68/* ==================================================================== */
69#define SH1_SHUB_ID 0x0000000110060580 69#define SH1_SHUB_ID __IA64_UL_CONST(0x0000000110060580)
70#define SH1_SHUB_ID_REVISION_SHFT 28 70#define SH1_SHUB_ID_REVISION_SHFT 28
71#define SH1_SHUB_ID_REVISION_MASK 0x00000000f0000000 71#define SH1_SHUB_ID_REVISION_MASK __IA64_UL_CONST(0x00000000f0000000)
72 72
73/* ==================================================================== */ 73/* ==================================================================== */
74/* Register "SH_RTC" */ 74/* Register "SH_RTC" */
75/* Real-time Clock */ 75/* Real-time Clock */
76/* ==================================================================== */ 76/* ==================================================================== */
77#define SH1_RTC 0x00000001101c0000 77#define SH1_RTC __IA64_UL_CONST(0x00000001101c0000)
78#define SH2_RTC 0x00000002101c0000 78#define SH2_RTC __IA64_UL_CONST(0x00000002101c0000)
79#define SH_RTC_MASK 0x007fffffffffffff 79#define SH_RTC_MASK __IA64_UL_CONST(0x007fffffffffffff)
80 80
81/* ==================================================================== */ 81/* ==================================================================== */
82/* Register "SH_PIO_WRITE_STATUS_0|1" */ 82/* Register "SH_PIO_WRITE_STATUS_0|1" */
83/* PIO Write Status for CPU 0 & 1 */ 83/* PIO Write Status for CPU 0 & 1 */
84/* ==================================================================== */ 84/* ==================================================================== */
85#define SH1_PIO_WRITE_STATUS_0 0x0000000120070200 85#define SH1_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000120070200)
86#define SH1_PIO_WRITE_STATUS_1 0x0000000120070280 86#define SH1_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000120070280)
87#define SH2_PIO_WRITE_STATUS_0 0x0000000020070200 87#define SH2_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000020070200)
88#define SH2_PIO_WRITE_STATUS_1 0x0000000020070280 88#define SH2_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000020070280)
89#define SH2_PIO_WRITE_STATUS_2 0x0000000020070300 89#define SH2_PIO_WRITE_STATUS_2 __IA64_UL_CONST(0x0000000020070300)
90#define SH2_PIO_WRITE_STATUS_3 0x0000000020070380 90#define SH2_PIO_WRITE_STATUS_3 __IA64_UL_CONST(0x0000000020070380)
91 91
92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ 92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */
93/* Description: Deadlock response detected */ 93/* Description: Deadlock response detected */
94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1 94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK 0x0000000000000002 95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
96 __IA64_UL_CONST(0x0000000000000002)
96 97
97/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ 98/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */
98/* Description: Count of currently pending PIO writes */ 99/* Description: Count of currently pending PIO writes */
99#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56 100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 101#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
102 __IA64_UL_CONST(0x3f00000000000000)
101 103
102/* ==================================================================== */ 104/* ==================================================================== */
103/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ 105/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */
104/* ==================================================================== */ 106/* ==================================================================== */
105#define SH1_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 107#define SH1_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000120070208)
106#define SH2_PIO_WRITE_STATUS_0_ALIAS 0x0000000020070208 108#define SH2_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000020070208)
107 109
108/* ==================================================================== */ 110/* ==================================================================== */
109/* Register "SH_EVENT_OCCURRED" */ 111/* Register "SH_EVENT_OCCURRED" */
@@ -111,33 +113,33 @@
111/* ==================================================================== */ 113/* ==================================================================== */
112/* SH_EVENT_OCCURRED_UART_INT */ 114/* SH_EVENT_OCCURRED_UART_INT */
113/* Description: Pending Junk Bus UART Interrupt */ 115/* Description: Pending Junk Bus UART Interrupt */
114#define SH_EVENT_OCCURRED_UART_INT_SHFT 20 116#define SH_EVENT_OCCURRED_UART_INT_SHFT 20
115#define SH_EVENT_OCCURRED_UART_INT_MASK 0x0000000000100000 117#define SH_EVENT_OCCURRED_UART_INT_MASK __IA64_UL_CONST(0x0000000000100000)
116 118
117/* SH_EVENT_OCCURRED_IPI_INT */ 119/* SH_EVENT_OCCURRED_IPI_INT */
118/* Description: Pending IPI Interrupt */ 120/* Description: Pending IPI Interrupt */
119#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28 121#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28
120#define SH_EVENT_OCCURRED_IPI_INT_MASK 0x0000000010000000 122#define SH_EVENT_OCCURRED_IPI_INT_MASK __IA64_UL_CONST(0x0000000010000000)
121 123
122/* SH_EVENT_OCCURRED_II_INT0 */ 124/* SH_EVENT_OCCURRED_II_INT0 */
123/* Description: Pending II 0 Interrupt */ 125/* Description: Pending II 0 Interrupt */
124#define SH_EVENT_OCCURRED_II_INT0_SHFT 29 126#define SH_EVENT_OCCURRED_II_INT0_SHFT 29
125#define SH_EVENT_OCCURRED_II_INT0_MASK 0x0000000020000000 127#define SH_EVENT_OCCURRED_II_INT0_MASK __IA64_UL_CONST(0x0000000020000000)
126 128
127/* SH_EVENT_OCCURRED_II_INT1 */ 129/* SH_EVENT_OCCURRED_II_INT1 */
128/* Description: Pending II 1 Interrupt */ 130/* Description: Pending II 1 Interrupt */
129#define SH_EVENT_OCCURRED_II_INT1_SHFT 30 131#define SH_EVENT_OCCURRED_II_INT1_SHFT 30
130#define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 132#define SH_EVENT_OCCURRED_II_INT1_MASK __IA64_UL_CONST(0x0000000040000000)
131 133
132/* SH2_EVENT_OCCURRED_EXTIO_INT2 */ 134/* SH2_EVENT_OCCURRED_EXTIO_INT2 */
133/* Description: Pending SHUB 2 EXT IO INT2 */ 135/* Description: Pending SHUB 2 EXT IO INT2 */
134#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33 136#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33
135#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK 0x0000000200000000 137#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
136 138
137/* SH2_EVENT_OCCURRED_EXTIO_INT3 */ 139/* SH2_EVENT_OCCURRED_EXTIO_INT3 */
138/* Description: Pending SHUB 2 EXT IO INT3 */ 140/* Description: Pending SHUB 2 EXT IO INT3 */
139#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34 141#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34
140#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK 0x0000000400000000 142#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
141 143
142#define SH_ALL_INT_MASK \ 144#define SH_ALL_INT_MASK \
143 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \ 145 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
@@ -149,310 +151,310 @@
149/* ==================================================================== */ 151/* ==================================================================== */
150/* LEDS */ 152/* LEDS */
151/* ==================================================================== */ 153/* ==================================================================== */
152#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL 154#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL
153#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL 155#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL
154#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL 156#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL
155#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL 157#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL
156 158
157#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL 159#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL
158#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL 160#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL
159#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL 161#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL
160#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL 162#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL
161 163
162/* ==================================================================== */ 164/* ==================================================================== */
163/* Register "SH1_PTC_0" */ 165/* Register "SH1_PTC_0" */
164/* Puge Translation Cache Message Configuration Information */ 166/* Puge Translation Cache Message Configuration Information */
165/* ==================================================================== */ 167/* ==================================================================== */
166#define SH1_PTC_0 0x00000001101a0000 168#define SH1_PTC_0 __IA64_UL_CONST(0x00000001101a0000)
167 169
168/* SH1_PTC_0_A */ 170/* SH1_PTC_0_A */
169/* Description: Type */ 171/* Description: Type */
170#define SH1_PTC_0_A_SHFT 0 172#define SH1_PTC_0_A_SHFT 0
171 173
172/* SH1_PTC_0_PS */ 174/* SH1_PTC_0_PS */
173/* Description: Page Size */ 175/* Description: Page Size */
174#define SH1_PTC_0_PS_SHFT 2 176#define SH1_PTC_0_PS_SHFT 2
175 177
176/* SH1_PTC_0_RID */ 178/* SH1_PTC_0_RID */
177/* Description: Region ID */ 179/* Description: Region ID */
178#define SH1_PTC_0_RID_SHFT 8 180#define SH1_PTC_0_RID_SHFT 8
179 181
180/* SH1_PTC_0_START */ 182/* SH1_PTC_0_START */
181/* Description: Start */ 183/* Description: Start */
182#define SH1_PTC_0_START_SHFT 63 184#define SH1_PTC_0_START_SHFT 63
183 185
184/* ==================================================================== */ 186/* ==================================================================== */
185/* Register "SH1_PTC_1" */ 187/* Register "SH1_PTC_1" */
186/* Puge Translation Cache Message Configuration Information */ 188/* Puge Translation Cache Message Configuration Information */
187/* ==================================================================== */ 189/* ==================================================================== */
188#define SH1_PTC_1 0x00000001101a0080 190#define SH1_PTC_1 __IA64_UL_CONST(0x00000001101a0080)
189 191
190/* SH1_PTC_1_START */ 192/* SH1_PTC_1_START */
191/* Description: PTC_1 Start */ 193/* Description: PTC_1 Start */
192#define SH1_PTC_1_START_SHFT 63 194#define SH1_PTC_1_START_SHFT 63
193
194 195
195/* ==================================================================== */ 196/* ==================================================================== */
196/* Register "SH2_PTC" */ 197/* Register "SH2_PTC" */
197/* Puge Translation Cache Message Configuration Information */ 198/* Puge Translation Cache Message Configuration Information */
198/* ==================================================================== */ 199/* ==================================================================== */
199#define SH2_PTC 0x0000000170000000 200#define SH2_PTC __IA64_UL_CONST(0x0000000170000000)
200 201
201/* SH2_PTC_A */ 202/* SH2_PTC_A */
202/* Description: Type */ 203/* Description: Type */
203#define SH2_PTC_A_SHFT 0 204#define SH2_PTC_A_SHFT 0
204 205
205/* SH2_PTC_PS */ 206/* SH2_PTC_PS */
206/* Description: Page Size */ 207/* Description: Page Size */
207#define SH2_PTC_PS_SHFT 2 208#define SH2_PTC_PS_SHFT 2
208 209
209/* SH2_PTC_RID */ 210/* SH2_PTC_RID */
210/* Description: Region ID */ 211/* Description: Region ID */
211#define SH2_PTC_RID_SHFT 4 212#define SH2_PTC_RID_SHFT 4
212 213
213/* SH2_PTC_START */ 214/* SH2_PTC_START */
214/* Description: Start */ 215/* Description: Start */
215#define SH2_PTC_START_SHFT 63 216#define SH2_PTC_START_SHFT 63
216 217
217/* SH2_PTC_ADDR_RID */ 218/* SH2_PTC_ADDR_RID */
218/* Description: Region ID */ 219/* Description: Region ID */
219#define SH2_PTC_ADDR_SHFT 4 220#define SH2_PTC_ADDR_SHFT 4
220#define SH2_PTC_ADDR_MASK 0x1ffffffffffff000 221#define SH2_PTC_ADDR_MASK __IA64_UL_CONST(0x1ffffffffffff000)
221 222
222/* ==================================================================== */ 223/* ==================================================================== */
223/* Register "SH_RTC1_INT_CONFIG" */ 224/* Register "SH_RTC1_INT_CONFIG" */
224/* SHub RTC 1 Interrupt Config Registers */ 225/* SHub RTC 1 Interrupt Config Registers */
225/* ==================================================================== */ 226/* ==================================================================== */
226 227
227#define SH1_RTC1_INT_CONFIG 0x0000000110001480 228#define SH1_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000110001480)
228#define SH2_RTC1_INT_CONFIG 0x0000000010001480 229#define SH2_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000010001480)
229#define SH_RTC1_INT_CONFIG_MASK 0x0ff3ffffffefffff 230#define SH_RTC1_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
230#define SH_RTC1_INT_CONFIG_INIT 0x0000000000000000 231#define SH_RTC1_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
231 232
232/* SH_RTC1_INT_CONFIG_TYPE */ 233/* SH_RTC1_INT_CONFIG_TYPE */
233/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 234/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
234#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0 235#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0
235#define SH_RTC1_INT_CONFIG_TYPE_MASK 0x0000000000000007 236#define SH_RTC1_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
236 237
237/* SH_RTC1_INT_CONFIG_AGT */ 238/* SH_RTC1_INT_CONFIG_AGT */
238/* Description: Agent, must be 0 for SHub */ 239/* Description: Agent, must be 0 for SHub */
239#define SH_RTC1_INT_CONFIG_AGT_SHFT 3 240#define SH_RTC1_INT_CONFIG_AGT_SHFT 3
240#define SH_RTC1_INT_CONFIG_AGT_MASK 0x0000000000000008 241#define SH_RTC1_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
241 242
242/* SH_RTC1_INT_CONFIG_PID */ 243/* SH_RTC1_INT_CONFIG_PID */
243/* Description: Processor ID, same setting as on targeted McKinley */ 244/* Description: Processor ID, same setting as on targeted McKinley */
244#define SH_RTC1_INT_CONFIG_PID_SHFT 4 245#define SH_RTC1_INT_CONFIG_PID_SHFT 4
245#define SH_RTC1_INT_CONFIG_PID_MASK 0x00000000000ffff0 246#define SH_RTC1_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
246 247
247/* SH_RTC1_INT_CONFIG_BASE */ 248/* SH_RTC1_INT_CONFIG_BASE */
248/* Description: Optional interrupt vector area, 2MB aligned */ 249/* Description: Optional interrupt vector area, 2MB aligned */
249#define SH_RTC1_INT_CONFIG_BASE_SHFT 21 250#define SH_RTC1_INT_CONFIG_BASE_SHFT 21
250#define SH_RTC1_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 251#define SH_RTC1_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
251 252
252/* SH_RTC1_INT_CONFIG_IDX */ 253/* SH_RTC1_INT_CONFIG_IDX */
253/* Description: Targeted McKinley interrupt vector */ 254/* Description: Targeted McKinley interrupt vector */
254#define SH_RTC1_INT_CONFIG_IDX_SHFT 52 255#define SH_RTC1_INT_CONFIG_IDX_SHFT 52
255#define SH_RTC1_INT_CONFIG_IDX_MASK 0x0ff0000000000000 256#define SH_RTC1_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
256 257
257/* ==================================================================== */ 258/* ==================================================================== */
258/* Register "SH_RTC1_INT_ENABLE" */ 259/* Register "SH_RTC1_INT_ENABLE" */
259/* SHub RTC 1 Interrupt Enable Registers */ 260/* SHub RTC 1 Interrupt Enable Registers */
260/* ==================================================================== */ 261/* ==================================================================== */
261 262
262#define SH1_RTC1_INT_ENABLE 0x0000000110001500 263#define SH1_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000110001500)
263#define SH2_RTC1_INT_ENABLE 0x0000000010001500 264#define SH2_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000010001500)
264#define SH_RTC1_INT_ENABLE_MASK 0x0000000000000001 265#define SH_RTC1_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
265#define SH_RTC1_INT_ENABLE_INIT 0x0000000000000000 266#define SH_RTC1_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
266 267
267/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */ 268/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */
268/* Description: Enable RTC 1 Interrupt */ 269/* Description: Enable RTC 1 Interrupt */
269#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0 270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0
270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK 0x0000000000000001 271#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
272 __IA64_UL_CONST(0x0000000000000001)
271 273
272/* ==================================================================== */ 274/* ==================================================================== */
273/* Register "SH_RTC2_INT_CONFIG" */ 275/* Register "SH_RTC2_INT_CONFIG" */
274/* SHub RTC 2 Interrupt Config Registers */ 276/* SHub RTC 2 Interrupt Config Registers */
275/* ==================================================================== */ 277/* ==================================================================== */
276 278
277#define SH1_RTC2_INT_CONFIG 0x0000000110001580 279#define SH1_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000110001580)
278#define SH2_RTC2_INT_CONFIG 0x0000000010001580 280#define SH2_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000010001580)
279#define SH_RTC2_INT_CONFIG_MASK 0x0ff3ffffffefffff 281#define SH_RTC2_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
280#define SH_RTC2_INT_CONFIG_INIT 0x0000000000000000 282#define SH_RTC2_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
281 283
282/* SH_RTC2_INT_CONFIG_TYPE */ 284/* SH_RTC2_INT_CONFIG_TYPE */
283/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 285/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
284#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0 286#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0
285#define SH_RTC2_INT_CONFIG_TYPE_MASK 0x0000000000000007 287#define SH_RTC2_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
286 288
287/* SH_RTC2_INT_CONFIG_AGT */ 289/* SH_RTC2_INT_CONFIG_AGT */
288/* Description: Agent, must be 0 for SHub */ 290/* Description: Agent, must be 0 for SHub */
289#define SH_RTC2_INT_CONFIG_AGT_SHFT 3 291#define SH_RTC2_INT_CONFIG_AGT_SHFT 3
290#define SH_RTC2_INT_CONFIG_AGT_MASK 0x0000000000000008 292#define SH_RTC2_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
291 293
292/* SH_RTC2_INT_CONFIG_PID */ 294/* SH_RTC2_INT_CONFIG_PID */
293/* Description: Processor ID, same setting as on targeted McKinley */ 295/* Description: Processor ID, same setting as on targeted McKinley */
294#define SH_RTC2_INT_CONFIG_PID_SHFT 4 296#define SH_RTC2_INT_CONFIG_PID_SHFT 4
295#define SH_RTC2_INT_CONFIG_PID_MASK 0x00000000000ffff0 297#define SH_RTC2_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
296 298
297/* SH_RTC2_INT_CONFIG_BASE */ 299/* SH_RTC2_INT_CONFIG_BASE */
298/* Description: Optional interrupt vector area, 2MB aligned */ 300/* Description: Optional interrupt vector area, 2MB aligned */
299#define SH_RTC2_INT_CONFIG_BASE_SHFT 21 301#define SH_RTC2_INT_CONFIG_BASE_SHFT 21
300#define SH_RTC2_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 302#define SH_RTC2_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
301 303
302/* SH_RTC2_INT_CONFIG_IDX */ 304/* SH_RTC2_INT_CONFIG_IDX */
303/* Description: Targeted McKinley interrupt vector */ 305/* Description: Targeted McKinley interrupt vector */
304#define SH_RTC2_INT_CONFIG_IDX_SHFT 52 306#define SH_RTC2_INT_CONFIG_IDX_SHFT 52
305#define SH_RTC2_INT_CONFIG_IDX_MASK 0x0ff0000000000000 307#define SH_RTC2_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
306 308
307/* ==================================================================== */ 309/* ==================================================================== */
308/* Register "SH_RTC2_INT_ENABLE" */ 310/* Register "SH_RTC2_INT_ENABLE" */
309/* SHub RTC 2 Interrupt Enable Registers */ 311/* SHub RTC 2 Interrupt Enable Registers */
310/* ==================================================================== */ 312/* ==================================================================== */
311 313
312#define SH1_RTC2_INT_ENABLE 0x0000000110001600 314#define SH1_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000110001600)
313#define SH2_RTC2_INT_ENABLE 0x0000000010001600 315#define SH2_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000010001600)
314#define SH_RTC2_INT_ENABLE_MASK 0x0000000000000001 316#define SH_RTC2_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
315#define SH_RTC2_INT_ENABLE_INIT 0x0000000000000000 317#define SH_RTC2_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
316 318
317/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */ 319/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */
318/* Description: Enable RTC 2 Interrupt */ 320/* Description: Enable RTC 2 Interrupt */
319#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0 321#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0
320#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK 0x0000000000000001 322#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
323 __IA64_UL_CONST(0x0000000000000001)
321 324
322/* ==================================================================== */ 325/* ==================================================================== */
323/* Register "SH_RTC3_INT_CONFIG" */ 326/* Register "SH_RTC3_INT_CONFIG" */
324/* SHub RTC 3 Interrupt Config Registers */ 327/* SHub RTC 3 Interrupt Config Registers */
325/* ==================================================================== */ 328/* ==================================================================== */
326 329
327#define SH1_RTC3_INT_CONFIG 0x0000000110001680 330#define SH1_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000110001680)
328#define SH2_RTC3_INT_CONFIG 0x0000000010001680 331#define SH2_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000010001680)
329#define SH_RTC3_INT_CONFIG_MASK 0x0ff3ffffffefffff 332#define SH_RTC3_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
330#define SH_RTC3_INT_CONFIG_INIT 0x0000000000000000 333#define SH_RTC3_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
331 334
332/* SH_RTC3_INT_CONFIG_TYPE */ 335/* SH_RTC3_INT_CONFIG_TYPE */
333/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ 336/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
334#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0 337#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0
335#define SH_RTC3_INT_CONFIG_TYPE_MASK 0x0000000000000007 338#define SH_RTC3_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
336 339
337/* SH_RTC3_INT_CONFIG_AGT */ 340/* SH_RTC3_INT_CONFIG_AGT */
338/* Description: Agent, must be 0 for SHub */ 341/* Description: Agent, must be 0 for SHub */
339#define SH_RTC3_INT_CONFIG_AGT_SHFT 3 342#define SH_RTC3_INT_CONFIG_AGT_SHFT 3
340#define SH_RTC3_INT_CONFIG_AGT_MASK 0x0000000000000008 343#define SH_RTC3_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
341 344
342/* SH_RTC3_INT_CONFIG_PID */ 345/* SH_RTC3_INT_CONFIG_PID */
343/* Description: Processor ID, same setting as on targeted McKinley */ 346/* Description: Processor ID, same setting as on targeted McKinley */
344#define SH_RTC3_INT_CONFIG_PID_SHFT 4 347#define SH_RTC3_INT_CONFIG_PID_SHFT 4
345#define SH_RTC3_INT_CONFIG_PID_MASK 0x00000000000ffff0 348#define SH_RTC3_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
346 349
347/* SH_RTC3_INT_CONFIG_BASE */ 350/* SH_RTC3_INT_CONFIG_BASE */
348/* Description: Optional interrupt vector area, 2MB aligned */ 351/* Description: Optional interrupt vector area, 2MB aligned */
349#define SH_RTC3_INT_CONFIG_BASE_SHFT 21 352#define SH_RTC3_INT_CONFIG_BASE_SHFT 21
350#define SH_RTC3_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 353#define SH_RTC3_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
351 354
352/* SH_RTC3_INT_CONFIG_IDX */ 355/* SH_RTC3_INT_CONFIG_IDX */
353/* Description: Targeted McKinley interrupt vector */ 356/* Description: Targeted McKinley interrupt vector */
354#define SH_RTC3_INT_CONFIG_IDX_SHFT 52 357#define SH_RTC3_INT_CONFIG_IDX_SHFT 52
355#define SH_RTC3_INT_CONFIG_IDX_MASK 0x0ff0000000000000 358#define SH_RTC3_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
356 359
357/* ==================================================================== */ 360/* ==================================================================== */
358/* Register "SH_RTC3_INT_ENABLE" */ 361/* Register "SH_RTC3_INT_ENABLE" */
359/* SHub RTC 3 Interrupt Enable Registers */ 362/* SHub RTC 3 Interrupt Enable Registers */
360/* ==================================================================== */ 363/* ==================================================================== */
361 364
362#define SH1_RTC3_INT_ENABLE 0x0000000110001700 365#define SH1_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000110001700)
363#define SH2_RTC3_INT_ENABLE 0x0000000010001700 366#define SH2_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000010001700)
364#define SH_RTC3_INT_ENABLE_MASK 0x0000000000000001 367#define SH_RTC3_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
365#define SH_RTC3_INT_ENABLE_INIT 0x0000000000000000 368#define SH_RTC3_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
366 369
367/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */ 370/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */
368/* Description: Enable RTC 3 Interrupt */ 371/* Description: Enable RTC 3 Interrupt */
369#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0 372#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0
370#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK 0x0000000000000001 373#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
374 __IA64_UL_CONST(0x0000000000000001)
371 375
372/* SH_EVENT_OCCURRED_RTC1_INT */ 376/* SH_EVENT_OCCURRED_RTC1_INT */
373/* Description: Pending RTC 1 Interrupt */ 377/* Description: Pending RTC 1 Interrupt */
374#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24 378#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24
375#define SH_EVENT_OCCURRED_RTC1_INT_MASK 0x0000000001000000 379#define SH_EVENT_OCCURRED_RTC1_INT_MASK __IA64_UL_CONST(0x0000000001000000)
376 380
377/* SH_EVENT_OCCURRED_RTC2_INT */ 381/* SH_EVENT_OCCURRED_RTC2_INT */
378/* Description: Pending RTC 2 Interrupt */ 382/* Description: Pending RTC 2 Interrupt */
379#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25 383#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25
380#define SH_EVENT_OCCURRED_RTC2_INT_MASK 0x0000000002000000 384#define SH_EVENT_OCCURRED_RTC2_INT_MASK __IA64_UL_CONST(0x0000000002000000)
381 385
382/* SH_EVENT_OCCURRED_RTC3_INT */ 386/* SH_EVENT_OCCURRED_RTC3_INT */
383/* Description: Pending RTC 3 Interrupt */ 387/* Description: Pending RTC 3 Interrupt */
384#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26 388#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26
385#define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 389#define SH_EVENT_OCCURRED_RTC3_INT_MASK __IA64_UL_CONST(0x0000000004000000)
386 390
387/* ==================================================================== */ 391/* ==================================================================== */
388/* Register "SH_IPI_ACCESS" */ 392/* Register "SH_IPI_ACCESS" */
389/* CPU interrupt Access Permission Bits */ 393/* CPU interrupt Access Permission Bits */
390/* ==================================================================== */ 394/* ==================================================================== */
391 395
392#define SH1_IPI_ACCESS 0x0000000110060480 396#define SH1_IPI_ACCESS __IA64_UL_CONST(0x0000000110060480)
393#define SH2_IPI_ACCESS0 0x0000000010060c00 397#define SH2_IPI_ACCESS0 __IA64_UL_CONST(0x0000000010060c00)
394#define SH2_IPI_ACCESS1 0x0000000010060c80 398#define SH2_IPI_ACCESS1 __IA64_UL_CONST(0x0000000010060c80)
395#define SH2_IPI_ACCESS2 0x0000000010060d00 399#define SH2_IPI_ACCESS2 __IA64_UL_CONST(0x0000000010060d00)
396#define SH2_IPI_ACCESS3 0x0000000010060d80 400#define SH2_IPI_ACCESS3 __IA64_UL_CONST(0x0000000010060d80)
397 401
398/* ==================================================================== */ 402/* ==================================================================== */
399/* Register "SH_INT_CMPB" */ 403/* Register "SH_INT_CMPB" */
400/* RTC Compare Value for Processor B */ 404/* RTC Compare Value for Processor B */
401/* ==================================================================== */ 405/* ==================================================================== */
402 406
403#define SH1_INT_CMPB 0x00000001101b0080 407#define SH1_INT_CMPB __IA64_UL_CONST(0x00000001101b0080)
404#define SH2_INT_CMPB 0x00000000101b0080 408#define SH2_INT_CMPB __IA64_UL_CONST(0x00000000101b0080)
405#define SH_INT_CMPB_MASK 0x007fffffffffffff 409#define SH_INT_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
406#define SH_INT_CMPB_INIT 0x0000000000000000 410#define SH_INT_CMPB_INIT __IA64_UL_CONST(0x0000000000000000)
407 411
408/* SH_INT_CMPB_REAL_TIME_CMPB */ 412/* SH_INT_CMPB_REAL_TIME_CMPB */
409/* Description: Real Time Clock Compare */ 413/* Description: Real Time Clock Compare */
410#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 414#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
411#define SH_INT_CMPB_REAL_TIME_CMPB_MASK 0x007fffffffffffff 415#define SH_INT_CMPB_REAL_TIME_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
412 416
413/* ==================================================================== */ 417/* ==================================================================== */
414/* Register "SH_INT_CMPC" */ 418/* Register "SH_INT_CMPC" */
415/* RTC Compare Value for Processor C */ 419/* RTC Compare Value for Processor C */
416/* ==================================================================== */ 420/* ==================================================================== */
417 421
418#define SH1_INT_CMPC 0x00000001101b0100 422#define SH1_INT_CMPC __IA64_UL_CONST(0x00000001101b0100)
419#define SH2_INT_CMPC 0x00000000101b0100 423#define SH2_INT_CMPC __IA64_UL_CONST(0x00000000101b0100)
420#define SH_INT_CMPC_MASK 0x007fffffffffffff 424#define SH_INT_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
421#define SH_INT_CMPC_INIT 0x0000000000000000 425#define SH_INT_CMPC_INIT __IA64_UL_CONST(0x0000000000000000)
422 426
423/* SH_INT_CMPC_REAL_TIME_CMPC */ 427/* SH_INT_CMPC_REAL_TIME_CMPC */
424/* Description: Real Time Clock Compare */ 428/* Description: Real Time Clock Compare */
425#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 429#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
426#define SH_INT_CMPC_REAL_TIME_CMPC_MASK 0x007fffffffffffff 430#define SH_INT_CMPC_REAL_TIME_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
427 431
428/* ==================================================================== */ 432/* ==================================================================== */
429/* Register "SH_INT_CMPD" */ 433/* Register "SH_INT_CMPD" */
430/* RTC Compare Value for Processor D */ 434/* RTC Compare Value for Processor D */
431/* ==================================================================== */ 435/* ==================================================================== */
432 436
433#define SH1_INT_CMPD 0x00000001101b0180 437#define SH1_INT_CMPD __IA64_UL_CONST(0x00000001101b0180)
434#define SH2_INT_CMPD 0x00000000101b0180 438#define SH2_INT_CMPD __IA64_UL_CONST(0x00000000101b0180)
435#define SH_INT_CMPD_MASK 0x007fffffffffffff 439#define SH_INT_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
436#define SH_INT_CMPD_INIT 0x0000000000000000 440#define SH_INT_CMPD_INIT __IA64_UL_CONST(0x0000000000000000)
437 441
438/* SH_INT_CMPD_REAL_TIME_CMPD */ 442/* SH_INT_CMPD_REAL_TIME_CMPD */
439/* Description: Real Time Clock Compare */ 443/* Description: Real Time Clock Compare */
440#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 444#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
441#define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff 445#define SH_INT_CMPD_REAL_TIME_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
442 446
443/* ==================================================================== */ 447/* ==================================================================== */
444/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ 448/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
445/* privilege vector for acc=0 */ 449/* privilege vector for acc=0 */
446/* ==================================================================== */ 450/* ==================================================================== */
447 451#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100030300)
448#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300
449 452
450/* ==================================================================== */ 453/* ==================================================================== */
451/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ 454/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
452/* privilege vector for acc=0 */ 455/* privilege vector for acc=0 */
453/* ==================================================================== */ 456/* ==================================================================== */
454 457#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100050300)
455#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300
456 458
457/* ==================================================================== */ 459/* ==================================================================== */
458/* Some MMRs are functionally identical (or close enough) on both SHUB1 */ 460/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
@@ -484,17 +486,17 @@
484/* Engine 0 Control and Status Register */ 486/* Engine 0 Control and Status Register */
485/* ========================================================================== */ 487/* ========================================================================== */
486 488
487#define SH2_BT_ENG_CSR_0 0x0000000030040000 489#define SH2_BT_ENG_CSR_0 __IA64_UL_CONST(0x0000000030040000)
488#define SH2_BT_ENG_SRC_ADDR_0 0x0000000030040080 490#define SH2_BT_ENG_SRC_ADDR_0 __IA64_UL_CONST(0x0000000030040080)
489#define SH2_BT_ENG_DEST_ADDR_0 0x0000000030040100 491#define SH2_BT_ENG_DEST_ADDR_0 __IA64_UL_CONST(0x0000000030040100)
490#define SH2_BT_ENG_NOTIF_ADDR_0 0x0000000030040180 492#define SH2_BT_ENG_NOTIF_ADDR_0 __IA64_UL_CONST(0x0000000030040180)
491 493
492/* ========================================================================== */ 494/* ========================================================================== */
493/* BTE interfaces 1-3 */ 495/* BTE interfaces 1-3 */
494/* ========================================================================== */ 496/* ========================================================================== */
495 497
496#define SH2_BT_ENG_CSR_1 0x0000000030050000 498#define SH2_BT_ENG_CSR_1 __IA64_UL_CONST(0x0000000030050000)
497#define SH2_BT_ENG_CSR_2 0x0000000030060000 499#define SH2_BT_ENG_CSR_2 __IA64_UL_CONST(0x0000000030060000)
498#define SH2_BT_ENG_CSR_3 0x0000000030070000 500#define SH2_BT_ENG_CSR_3 __IA64_UL_CONST(0x0000000030070000)
499 501
500#endif /* _ASM_IA64_SN_SHUB_MMR_H */ 502#endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h
index 78eb4f869c8b..cf770e246af5 100644
--- a/include/asm-ia64/sn/simulator.h
+++ b/include/asm-ia64/sn/simulator.h
@@ -10,16 +10,17 @@
10 10
11#include <linux/config.h> 11#include <linux/config.h>
12 12
13#ifdef CONFIG_IA64_SGI_SN_SIM
14
15#define SNMAGIC 0xaeeeeeee8badbeefL 13#define SNMAGIC 0xaeeeeeee8badbeefL
16#define IS_RUNNING_ON_SIMULATOR() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;}) 14#define IS_MEDUSA() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
17
18#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
19 15
16#ifdef CONFIG_IA64_SGI_SN_SIM
17#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
18#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type)
19#define IS_RUNNING_ON_FAKE_PROM() (sn_prom_type == 2)
20extern int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
20#else 21#else
21
22#define IS_RUNNING_ON_SIMULATOR() (0) 22#define IS_RUNNING_ON_SIMULATOR() (0)
23#define IS_RUNNING_ON_FAKE_PROM() (0)
23#define SIMULATOR_SLEEP() 24#define SIMULATOR_SLEEP()
24 25
25#endif 26#endif
diff --git a/include/asm-ia64/sn/sn2/sn_hwperf.h b/include/asm-ia64/sn/sn2/sn_hwperf.h
index b0c4d6dd77ba..df75f4c4aec3 100644
--- a/include/asm-ia64/sn/sn2/sn_hwperf.h
+++ b/include/asm-ia64/sn/sn2/sn_hwperf.h
@@ -223,4 +223,6 @@ struct sn_hwperf_ioctl_args {
223#define SN_HWPERF_OP_RECONFIGURE 253 223#define SN_HWPERF_OP_RECONFIGURE 253
224#define SN_HWPERF_OP_INVAL 254 224#define SN_HWPERF_OP_INVAL 254
225 225
226int sn_topology_open(struct inode *inode, struct file *file);
227int sn_topology_release(struct inode *inode, struct file *file);
226#endif /* SN_HWPERF_H */ 228#endif /* SN_HWPERF_H */
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index eb0395ad0d6a..1455375d2ce4 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -132,6 +132,8 @@
132#define SALRET_INVALID_ARG (-2) 132#define SALRET_INVALID_ARG (-2)
133#define SALRET_ERROR (-3) 133#define SALRET_ERROR (-3)
134 134
135#define SN_SAL_FAKE_PROM 0x02009999
136
135 137
136/** 138/**
137 * sn_sal_rev_major - get the major SGI SAL revision number 139 * sn_sal_rev_major - get the major SGI SAL revision number
@@ -1105,4 +1107,12 @@ ia64_sn_bte_recovery(nasid_t nasid)
1105 return (int) rv.status; 1107 return (int) rv.status;
1106} 1108}
1107 1109
1110static inline int
1111ia64_sn_is_fake_prom(void)
1112{
1113 struct ia64_sal_retval rv;
1114 SAL_CALL_NOLOCK(rv, SN_SAL_FAKE_PROM, 0, 0, 0, 0, 0, 0, 0);
1115 return (rv.status == 0);
1116}
1117
1108#endif /* _ASM_IA64_SN_SN_SAL_H */ 1118#endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
index b6acc22ab239..5ccec608d325 100644
--- a/include/asm-ia64/sn/tioca_provider.h
+++ b/include/asm-ia64/sn/tioca_provider.h
@@ -201,6 +201,7 @@ tioca_tlbflush(struct tioca_kernel *tioca_kernel)
201} 201}
202 202
203extern uint32_t tioca_gart_found; 203extern uint32_t tioca_gart_found;
204extern struct list_head tioca_list;
204extern int tioca_init_provider(void); 205extern int tioca_init_provider(void);
205extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern); 206extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
206#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */ 207#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
diff --git a/include/asm-ia64/vga.h b/include/asm-ia64/vga.h
index 1f446d6841f6..bc3349ffc505 100644
--- a/include/asm-ia64/vga.h
+++ b/include/asm-ia64/vga.h
@@ -14,7 +14,10 @@
14 * videoram directly without any black magic. 14 * videoram directly without any black magic.
15 */ 15 */
16 16
17#define VGA_MAP_MEM(x) ((unsigned long) ioremap((x), 0)) 17extern unsigned long vga_console_iobase;
18extern unsigned long vga_console_membase;
19
20#define VGA_MAP_MEM(x) ((unsigned long) ioremap(vga_console_membase + (x), 0))
18 21
19#define vga_readb(x) (*(x)) 22#define vga_readb(x) (*(x))
20#define vga_writeb(x,y) (*(y) = (x)) 23#define vga_writeb(x,y) (*(y) = (x))
diff --git a/include/asm-m68k/serial.h b/include/asm-m68k/serial.h
index 9f5bcdc105fc..3fe29f8b0194 100644
--- a/include/asm-m68k/serial.h
+++ b/include/asm-m68k/serial.h
@@ -26,54 +26,9 @@
26#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 26#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
27#endif 27#endif
28 28
29#ifdef CONFIG_SERIAL_MANY_PORTS 29#define SERIAL_PORT_DFNS \
30#define FOURPORT_FLAGS ASYNC_FOURPORT
31#define ACCENT_FLAGS 0
32#define BOCA_FLAGS 0
33#endif
34
35#define STD_SERIAL_PORT_DEFNS \
36 /* UART CLK PORT IRQ FLAGS */ \ 30 /* UART CLK PORT IRQ FLAGS */ \
37 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 31 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
38 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 32 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
39 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 33 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
40 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 34 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
41
42
43#ifdef CONFIG_SERIAL_MANY_PORTS
44#define EXTRA_SERIAL_PORT_DEFNS \
45 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
46 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
47 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
48 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
49 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
50 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
51 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
52 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
53 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
54 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
55 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
56 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
57 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
58 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
59 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
60 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
61 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
62 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
63 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
64 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
65 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
66 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
67 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
68 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
69 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
70 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
71 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
72 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
73#else
74#define EXTRA_SERIAL_PORT_DEFNS
75#endif
76
77#define SERIAL_PORT_DFNS \
78 STD_SERIAL_PORT_DEFNS \
79 EXTRA_SERIAL_PORT_DEFNS
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 8a70ff58f760..4eed8e2acdc3 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -29,32 +29,6 @@
29#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 29#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
30#endif 30#endif
31 31
32#ifdef CONFIG_SERIAL_MANY_PORTS
33#define FOURPORT_FLAGS ASYNC_FOURPORT
34#define ACCENT_FLAGS 0
35#define BOCA_FLAGS 0
36#define HUB6_FLAGS 0
37#define RS_TABLE_SIZE 64
38#else
39#define RS_TABLE_SIZE
40#endif
41
42/*
43 * The following define the access methods for the HUB6 card. All
44 * access is through two ports for all 24 possible chips. The card is
45 * selected through the high 2 bits, the port on that card with the
46 * "middle" 3 bits, and the register on that port with the bottom
47 * 3 bits.
48 *
49 * While the access port and interrupt is configurable, the default
50 * port locations are 0x302 for the port control register, and 0x303
51 * for the data read/write register. Normally, the interrupt is at irq3
52 * but can be anything from 3 to 7 inclusive. Note that using 3 will
53 * require disabling com2.
54 */
55
56#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
57
58#ifdef CONFIG_MACH_JAZZ 32#ifdef CONFIG_MACH_JAZZ
59#include <asm/jazz.h> 33#include <asm/jazz.h>
60 34
@@ -240,66 +214,10 @@
240 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 214 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
241 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 215 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
242 216
243#ifdef CONFIG_SERIAL_MANY_PORTS
244#define EXTRA_SERIAL_PORT_DEFNS \
245 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
246 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
247 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
248 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
249 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
250 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
251 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
252 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
253 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
254 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
255 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
256 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
257 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
258 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
259 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
260 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
261 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
262 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
263 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
264 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
265 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
266 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
267 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
268 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
269 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
270 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
271 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
272 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
273#else /* CONFIG_SERIAL_MANY_PORTS */
274#define EXTRA_SERIAL_PORT_DEFNS
275#endif /* CONFIG_SERIAL_MANY_PORTS */
276
277#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ 217#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
278#define STD_SERIAL_PORT_DEFNS 218#define STD_SERIAL_PORT_DEFNS
279#define EXTRA_SERIAL_PORT_DEFNS
280#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */ 219#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
281 220
282/* You can have up to four HUB6's in the system, but I've only
283 * included two cards here for a total of twelve ports.
284 */
285#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
286#define HUB6_SERIAL_PORT_DFNS \
287 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
288 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
289 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
290 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
291 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
292 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
293 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
294 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
295 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
296 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
297 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
298 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
299#else
300#define HUB6_SERIAL_PORT_DFNS
301#endif
302
303#ifdef CONFIG_MOMENCO_JAGUAR_ATX 221#ifdef CONFIG_MOMENCO_JAGUAR_ATX
304/* Ordinary NS16552 duart with a 20MHz crystal. */ 222/* Ordinary NS16552 duart with a 20MHz crystal. */
305#define JAGUAR_ATX_UART_CLK 20000000 223#define JAGUAR_ATX_UART_CLK 20000000
@@ -427,8 +345,6 @@
427 COBALT_SERIAL_PORT_DEFNS \ 345 COBALT_SERIAL_PORT_DEFNS \
428 DDB5477_SERIAL_PORT_DEFNS \ 346 DDB5477_SERIAL_PORT_DEFNS \
429 EV96100_SERIAL_PORT_DEFNS \ 347 EV96100_SERIAL_PORT_DEFNS \
430 EXTRA_SERIAL_PORT_DEFNS \
431 HUB6_SERIAL_PORT_DFNS \
432 IP32_SERIAL_PORT_DEFNS \ 348 IP32_SERIAL_PORT_DEFNS \
433 ITE_SERIAL_PORT_DEFNS \ 349 ITE_SERIAL_PORT_DEFNS \
434 IVR_SERIAL_PORT_DEFNS \ 350 IVR_SERIAL_PORT_DEFNS \
diff --git a/include/asm-parisc/serial.h b/include/asm-parisc/serial.h
index 239c5dcab7e6..82fd820d684f 100644
--- a/include/asm-parisc/serial.h
+++ b/include/asm-parisc/serial.h
@@ -19,18 +19,4 @@
19 * A500 w/ PCI serial cards: 5 + 4 * card ~= 17 19 * A500 w/ PCI serial cards: 5 + 4 * card ~= 17
20 */ 20 */
21 21
22#define STD_SERIAL_PORT_DEFNS \ 22#define SERIAL_PORT_DFNS
23 { 0, }, /* ttyS0 */ \
24 { 0, }, /* ttyS1 */ \
25 { 0, }, /* ttyS2 */ \
26 { 0, }, /* ttyS3 */ \
27 { 0, }, /* ttyS4 */ \
28 { 0, }, /* ttyS5 */ \
29 { 0, }, /* ttyS6 */ \
30 { 0, }, /* ttyS7 */ \
31 { 0, }, /* ttyS8 */
32
33
34#define SERIAL_PORT_DFNS \
35 STD_SERIAL_PORT_DEFNS
36
diff --git a/include/asm-ppc/pc_serial.h b/include/asm-ppc/pc_serial.h
index fa9cbb67ce3e..8f994f9f8857 100644
--- a/include/asm-ppc/pc_serial.h
+++ b/include/asm-ppc/pc_serial.h
@@ -35,93 +35,9 @@
35#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 35#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
36#endif 36#endif
37 37
38#ifdef CONFIG_SERIAL_MANY_PORTS 38#define SERIAL_PORT_DFNS \
39#define FOURPORT_FLAGS ASYNC_FOURPORT
40#define ACCENT_FLAGS 0
41#define BOCA_FLAGS 0
42#define HUB6_FLAGS 0
43#endif
44
45/*
46 * The following define the access methods for the HUB6 card. All
47 * access is through two ports for all 24 possible chips. The card is
48 * selected through the high 2 bits, the port on that card with the
49 * "middle" 3 bits, and the register on that port with the bottom
50 * 3 bits.
51 *
52 * While the access port and interrupt is configurable, the default
53 * port locations are 0x302 for the port control register, and 0x303
54 * for the data read/write register. Normally, the interrupt is at irq3
55 * but can be anything from 3 to 7 inclusive. Note that using 3 will
56 * require disabling com2.
57 */
58
59#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
60
61#define STD_SERIAL_PORT_DEFNS \
62 /* UART CLK PORT IRQ FLAGS */ \ 39 /* UART CLK PORT IRQ FLAGS */ \
63 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 40 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
64 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 41 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
65 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 42 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
66 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 43 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
67
68
69#ifdef CONFIG_SERIAL_MANY_PORTS
70#define EXTRA_SERIAL_PORT_DEFNS \
71 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
72 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
73 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
74 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
75 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
76 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
77 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
78 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
79 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
80 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
81 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
82 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
83 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
84 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
85 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
86 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
87 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
88 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
89 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
90 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
91 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
92 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
93 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
94 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
95 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
96 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
97 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
98 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
99#else
100#define EXTRA_SERIAL_PORT_DEFNS
101#endif
102
103/* You can have up to four HUB6's in the system, but I've only
104 * included two cards here for a total of twelve ports.
105 */
106#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
107#define HUB6_SERIAL_PORT_DFNS \
108 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
109 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
110 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
111 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
112 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
113 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
114 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
115 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
116 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
117 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
118 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
119 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
120#else
121#define HUB6_SERIAL_PORT_DFNS
122#endif
123
124#define SERIAL_PORT_DFNS \
125 STD_SERIAL_PORT_DEFNS \
126 EXTRA_SERIAL_PORT_DEFNS \
127 HUB6_SERIAL_PORT_DFNS
diff --git a/include/asm-sh/bigsur/serial.h b/include/asm-sh/bigsur/serial.h
index 540f12205923..7233af42f755 100644
--- a/include/asm-sh/bigsur/serial.h
+++ b/include/asm-sh/bigsur/serial.h
@@ -14,13 +14,10 @@
14#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) 14#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
15 15
16 16
17#define STD_SERIAL_PORT_DEFNS \ 17#define SERIAL_PORT_DFNS \
18 /* UART CLK PORT IRQ FLAGS */ \ 18 /* UART CLK PORT IRQ FLAGS */ \
19 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */ 19 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */
20 20
21
22#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
23
24/* XXX: This should be moved ino irq.h */ 21/* XXX: This should be moved ino irq.h */
25#define irq_cannonicalize(x) (x) 22#define irq_cannonicalize(x) (x)
26 23
diff --git a/include/asm-sh/ec3104/serial.h b/include/asm-sh/ec3104/serial.h
index f8eb16312ed9..cfe4d78ec1ee 100644
--- a/include/asm-sh/ec3104/serial.h
+++ b/include/asm-sh/ec3104/serial.h
@@ -10,13 +10,11 @@
10 * it's got the keyboard controller behind it so we can't really use it 10 * it's got the keyboard controller behind it so we can't really use it
11 * (without moving the keyboard driver to userspace, which doesn't sound 11 * (without moving the keyboard driver to userspace, which doesn't sound
12 * like a very good idea) */ 12 * like a very good idea) */
13#define STD_SERIAL_PORT_DEFNS \ 13#define SERIAL_PORT_DFNS \
14 /* UART CLK PORT IRQ FLAGS */ \ 14 /* UART CLK PORT IRQ FLAGS */ \
15 { 0, BASE_BAUD, 0x11C00, EC3104_IRQBASE+7, STD_COM_FLAGS }, /* ttyS0 */ \ 15 { 0, BASE_BAUD, 0x11C00, EC3104_IRQBASE+7, STD_COM_FLAGS }, /* ttyS0 */ \
16 { 0, BASE_BAUD, 0x12000, EC3104_IRQBASE+8, STD_COM_FLAGS }, /* ttyS1 */ \ 16 { 0, BASE_BAUD, 0x12000, EC3104_IRQBASE+8, STD_COM_FLAGS }, /* ttyS1 */ \
17 { 0, BASE_BAUD, 0x12400, EC3104_IRQBASE+9, STD_COM_FLAGS }, /* ttyS2 */ 17 { 0, BASE_BAUD, 0x12400, EC3104_IRQBASE+9, STD_COM_FLAGS }, /* ttyS2 */
18 18
19#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
20
21/* XXX: This should be moved ino irq.h */ 19/* XXX: This should be moved ino irq.h */
22#define irq_cannonicalize(x) (x) 20#define irq_cannonicalize(x) (x)
diff --git a/include/asm-sh/serial.h b/include/asm-sh/serial.h
index 5474dbdbaa86..f51e232d5cd9 100644
--- a/include/asm-sh/serial.h
+++ b/include/asm-sh/serial.h
@@ -29,20 +29,18 @@
29#ifdef CONFIG_HD64465 29#ifdef CONFIG_HD64465
30#include <asm/hd64465.h> 30#include <asm/hd64465.h>
31 31
32#define STD_SERIAL_PORT_DEFNS \ 32#define SERIAL_PORT_DFNS \
33 /* UART CLK PORT IRQ FLAGS */ \ 33 /* UART CLK PORT IRQ FLAGS */ \
34 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */ 34 { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */
35 35
36#else 36#else
37 37
38#define STD_SERIAL_PORT_DEFNS \ 38#define SERIAL_PORT_DFNS \
39 /* UART CLK PORT IRQ FLAGS */ \ 39 /* UART CLK PORT IRQ FLAGS */ \
40 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 40 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
41 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS } /* ttyS1 */ 41 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS } /* ttyS1 */
42 42
43#endif 43#endif
44 44
45#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
46
47#endif 45#endif
48#endif /* _ASM_SERIAL_H */ 46#endif /* _ASM_SERIAL_H */
diff --git a/include/asm-sh64/serial.h b/include/asm-sh64/serial.h
index 8e39b4e90c76..29c9be15112b 100644
--- a/include/asm-sh64/serial.h
+++ b/include/asm-sh64/serial.h
@@ -20,13 +20,11 @@
20 20
21#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) 21#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
22 22
23#define STD_SERIAL_PORT_DEFNS \ 23#define SERIAL_PORT_DFNS \
24 /* UART CLK PORT IRQ FLAGS */ \ 24 /* UART CLK PORT IRQ FLAGS */ \
25 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 25 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
26 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS } /* ttyS1 */ 26 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS } /* ttyS1 */
27 27
28#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS
29
30/* XXX: This should be moved ino irq.h */ 28/* XXX: This should be moved ino irq.h */
31#define irq_cannonicalize(x) (x) 29#define irq_cannonicalize(x) (x)
32 30
diff --git a/include/asm-x86_64/serial.h b/include/asm-x86_64/serial.h
index dbab232044cd..dc752eafa681 100644
--- a/include/asm-x86_64/serial.h
+++ b/include/asm-x86_64/serial.h
@@ -22,109 +22,9 @@
22#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF 22#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
23#endif 23#endif
24 24
25#ifdef CONFIG_SERIAL_MANY_PORTS 25#define SERIAL_PORT_DFNS \
26#define FOURPORT_FLAGS ASYNC_FOURPORT
27#define ACCENT_FLAGS 0
28#define BOCA_FLAGS 0
29#define HUB6_FLAGS 0
30#endif
31
32#define MCA_COM_FLAGS (STD_COM_FLAGS|ASYNC_BOOT_ONLYMCA)
33
34/*
35 * The following define the access methods for the HUB6 card. All
36 * access is through two ports for all 24 possible chips. The card is
37 * selected through the high 2 bits, the port on that card with the
38 * "middle" 3 bits, and the register on that port with the bottom
39 * 3 bits.
40 *
41 * While the access port and interrupt is configurable, the default
42 * port locations are 0x302 for the port control register, and 0x303
43 * for the data read/write register. Normally, the interrupt is at irq3
44 * but can be anything from 3 to 7 inclusive. Note that using 3 will
45 * require disabling com2.
46 */
47
48#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
49
50#define STD_SERIAL_PORT_DEFNS \
51 /* UART CLK PORT IRQ FLAGS */ \ 26 /* UART CLK PORT IRQ FLAGS */ \
52 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ 27 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
53 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ 28 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
54 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ 29 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
55 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ 30 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
56
57
58#ifdef CONFIG_SERIAL_MANY_PORTS
59#define EXTRA_SERIAL_PORT_DEFNS \
60 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
61 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
62 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
63 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
64 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
65 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
66 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
67 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
68 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
69 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
70 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
71 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
72 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
73 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
74 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
75 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
76 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
77 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
78 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
79 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
80 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
81 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
82 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
83 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
84 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
85 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
86 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
87 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
88#else
89#define EXTRA_SERIAL_PORT_DEFNS
90#endif
91
92/* You can have up to four HUB6's in the system, but I've only
93 * included two cards here for a total of twelve ports.
94 */
95#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
96#define HUB6_SERIAL_PORT_DFNS \
97 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
98 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
99 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
100 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
101 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
102 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
103 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
104 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
105 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
106 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
107 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
108 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
109#else
110#define HUB6_SERIAL_PORT_DFNS
111#endif
112
113#ifdef CONFIG_MCA
114#define MCA_SERIAL_PORT_DFNS \
115 { 0, BASE_BAUD, 0x3220, 3, MCA_COM_FLAGS }, \
116 { 0, BASE_BAUD, 0x3228, 3, MCA_COM_FLAGS }, \
117 { 0, BASE_BAUD, 0x4220, 3, MCA_COM_FLAGS }, \
118 { 0, BASE_BAUD, 0x4228, 3, MCA_COM_FLAGS }, \
119 { 0, BASE_BAUD, 0x5220, 3, MCA_COM_FLAGS }, \
120 { 0, BASE_BAUD, 0x5228, 3, MCA_COM_FLAGS },
121#else
122#define MCA_SERIAL_PORT_DFNS
123#endif
124
125#define SERIAL_PORT_DFNS \
126 STD_SERIAL_PORT_DEFNS \
127 EXTRA_SERIAL_PORT_DEFNS \
128 HUB6_SERIAL_PORT_DFNS \
129 MCA_SERIAL_PORT_DFNS
130
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-28 02:29:56 -0400