2 files changed, 10 insertions, 9 deletions

diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index c5c5eec2fa74..9bf901762411 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -101,14 +101,15 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
         for (i = 0; i < NUM_COUNTERS; ++i) {
                 if (unlikely(!msrs->counters[i].addr))
                         continue;
-                wrmsr(msrs->counters[i].addr, -1, -1);
+                wrmsrl(msrs->counters[i].addr, -1LL);
         }
 
         /* enable active counters */
         for (i = 0; i < NUM_COUNTERS; ++i) {
                 if (counter_config[i].enabled && msrs->counters[i].addr) {
                         reset_value[i] = counter_config[i].count;
-                        wrmsr(msrs->counters[i].addr, -(unsigned int)counter_config[i].count, -1);
+                        wrmsrl(msrs->counters[i].addr,
+                               -(s64)counter_config[i].count);
                         rdmsrl(msrs->controls[i].addr, val);
                         val &= model->reserved;
                         val |= op_x86_get_ctrl(model, &counter_config[i]);
@@ -251,7 +252,7 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
                 if (val & OP_CTR_OVERFLOW)
                         continue;
                 oprofile_add_sample(regs, i);
-                wrmsr(msrs->counters[i].addr, -(unsigned int)reset_value[i], -1);
+                wrmsrl(msrs->counters[i].addr, -(s64)reset_value[i]);
         }
 
         op_amd_handle_ibs(regs, msrs);
diff --git a/arch/x86/oprofile/op_model_p4.c b/arch/x86/oprofile/op_model_p4.c
index 9db0ca9af764..f01e53b118fa 100644
--- a/arch/x86/oprofile/op_model_p4.c
+++ b/arch/x86/oprofile/op_model_p4.c
@@ -579,8 +579,8 @@ static void p4_setup_ctrs(struct op_x86_model_spec const *model,
                 if (counter_config[i].enabled && msrs->controls[i].addr) {
                         reset_value[i] = counter_config[i].count;
                         pmc_setup_one_p4_counter(i);
-                        wrmsr(p4_counters[VIRT_CTR(stag, i)].counter_address,
-                              -(u32)counter_config[i].count, -1);
+                        wrmsrl(p4_counters[VIRT_CTR(stag, i)].counter_address,
+                               -(s64)counter_config[i].count);
                 } else {
                         reset_value[i] = 0;
                 }
@@ -624,12 +624,12 @@ static int p4_check_ctrs(struct pt_regs * const regs,
                 rdmsr(p4_counters[real].counter_address, ctr, high);
                 if (CCCR_OVF_P(low) || !(ctr & OP_CTR_OVERFLOW)) {
                         oprofile_add_sample(regs, i);
-                        wrmsr(p4_counters[real].counter_address,
-                              -(u32)reset_value[i], -1);
+                        wrmsrl(p4_counters[real].counter_address,
+                               -(s64)reset_value[i]);
                         CCCR_CLEAR_OVF(low);
                         wrmsr(p4_counters[real].cccr_address, low, high);
-                        wrmsr(p4_counters[real].counter_address,
-                              -(u32)reset_value[i], -1);
+                        wrmsrl(p4_counters[real].counter_address,
+                               -(s64)reset_value[i]);
                 }
         }