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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-ep93xx/Makefile2
-rw-r--r--arch/arm/mach-ep93xx/core.c109
-rw-r--r--arch/arm/mach-ep93xx/gpio.c158
-rw-r--r--include/asm-arm/arch-ep93xx/gpio.h21
5 files changed, 176 insertions, 115 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4039a133006e..a583c0bf8203 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -255,6 +255,7 @@ config ARCH_EP93XX
255 select ARM_AMBA 255 select ARM_AMBA
256 select ARM_VIC 256 select ARM_VIC
257 select GENERIC_GPIO 257 select GENERIC_GPIO
258 select HAVE_GPIO_LIB
258 help 259 help
259 This enables support for the Cirrus EP93xx series of CPUs. 260 This enables support for the Cirrus EP93xx series of CPUs.
260 261
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index 0ecf99761feb..c1252ca9648e 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -1,7 +1,7 @@
1# 1#
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4obj-y := core.o clock.o 4obj-y := core.o clock.o gpio.o
5obj-m := 5obj-m :=
6obj-n := 6obj-n :=
7obj- := 7obj- :=
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 91f6a07a51d5..8bc187240542 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -159,7 +159,7 @@ static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
159static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; 159static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
160static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c }; 160static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c };
161 161
162static void update_gpio_int_params(unsigned port) 162void ep93xx_gpio_update_int_params(unsigned port)
163{ 163{
164 BUG_ON(port > 2); 164 BUG_ON(port > 2);
165 165
@@ -175,98 +175,10 @@ static void update_gpio_int_params(unsigned port)
175 EP93XX_GPIO_REG(int_en_register_offset[port])); 175 EP93XX_GPIO_REG(int_en_register_offset[port]));
176} 176}
177 177
178/* Port ordering is: A B F D E C G H */ 178void ep93xx_gpio_int_mask(unsigned line)
179static const u8 data_register_offset[8] = {
180 0x00, 0x04, 0x30, 0x0c, 0x20, 0x08, 0x38, 0x40,
181};
182
183static const u8 data_direction_register_offset[8] = {
184 0x10, 0x14, 0x34, 0x1c, 0x24, 0x18, 0x3c, 0x44,
185};
186
187#define GPIO_IN 0
188#define GPIO_OUT 1
189
190static void ep93xx_gpio_set_direction(unsigned line, int direction)
191{
192 unsigned int data_direction_register;
193 unsigned long flags;
194 unsigned char v;
195
196 data_direction_register =
197 EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
198
199 local_irq_save(flags);
200 if (direction == GPIO_OUT) {
201 if (line >= 0 && line <= EP93XX_GPIO_LINE_MAX_IRQ) {
202 /* Port A/B/F */
203 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
204 update_gpio_int_params(line >> 3);
205 }
206
207 v = __raw_readb(data_direction_register);
208 v |= 1 << (line & 7);
209 __raw_writeb(v, data_direction_register);
210 } else if (direction == GPIO_IN) {
211 v = __raw_readb(data_direction_register);
212 v &= ~(1 << (line & 7));
213 __raw_writeb(v, data_direction_register);
214 }
215 local_irq_restore(flags);
216}
217
218int gpio_direction_input(unsigned gpio)
219{
220 if (gpio > EP93XX_GPIO_LINE_MAX)
221 return -EINVAL;
222
223 ep93xx_gpio_set_direction(gpio, GPIO_IN);
224
225 return 0;
226}
227EXPORT_SYMBOL(gpio_direction_input);
228
229int gpio_direction_output(unsigned gpio, int value)
230{
231 if (gpio > EP93XX_GPIO_LINE_MAX)
232 return -EINVAL;
233
234 gpio_set_value(gpio, value);
235 ep93xx_gpio_set_direction(gpio, GPIO_OUT);
236
237 return 0;
238}
239EXPORT_SYMBOL(gpio_direction_output);
240
241int gpio_get_value(unsigned gpio)
242{
243 unsigned int data_register;
244
245 data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
246
247 return !!(__raw_readb(data_register) & (1 << (gpio & 7)));
248}
249EXPORT_SYMBOL(gpio_get_value);
250
251void gpio_set_value(unsigned gpio, int value)
252{ 179{
253 unsigned int data_register; 180 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
254 unsigned long flags;
255 unsigned char v;
256
257 data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
258
259 local_irq_save(flags);
260 v = __raw_readb(data_register);
261 if (value)
262 v |= 1 << (gpio & 7);
263 else
264 v &= ~(1 << (gpio & 7));
265 __raw_writeb(v, data_register);
266 local_irq_restore(flags);
267} 181}
268EXPORT_SYMBOL(gpio_set_value);
269
270 182
271/************************************************************************* 183/*************************************************************************
272 * EP93xx IRQ handling 184 * EP93xx IRQ handling
@@ -316,7 +228,7 @@ static void ep93xx_gpio_irq_ack(unsigned int irq)
316 228
317 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { 229 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
318 gpio_int_type2[port] ^= port_mask; /* switch edge direction */ 230 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
319 update_gpio_int_params(port); 231 ep93xx_gpio_update_int_params(port);
320 } 232 }
321 233
322 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); 234 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
@@ -332,7 +244,7 @@ static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
332 gpio_int_type2[port] ^= port_mask; /* switch edge direction */ 244 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
333 245
334 gpio_int_unmasked[port] &= ~port_mask; 246 gpio_int_unmasked[port] &= ~port_mask;
335 update_gpio_int_params(port); 247 ep93xx_gpio_update_int_params(port);
336 248
337 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); 249 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
338} 250}
@@ -343,7 +255,7 @@ static void ep93xx_gpio_irq_mask(unsigned int irq)
343 int port = line >> 3; 255 int port = line >> 3;
344 256
345 gpio_int_unmasked[port] &= ~(1 << (line & 7)); 257 gpio_int_unmasked[port] &= ~(1 << (line & 7));
346 update_gpio_int_params(port); 258 ep93xx_gpio_update_int_params(port);
347} 259}
348 260
349static void ep93xx_gpio_irq_unmask(unsigned int irq) 261static void ep93xx_gpio_irq_unmask(unsigned int irq)
@@ -352,7 +264,7 @@ static void ep93xx_gpio_irq_unmask(unsigned int irq)
352 int port = line >> 3; 264 int port = line >> 3;
353 265
354 gpio_int_unmasked[port] |= 1 << (line & 7); 266 gpio_int_unmasked[port] |= 1 << (line & 7);
355 update_gpio_int_params(port); 267 ep93xx_gpio_update_int_params(port);
356} 268}
357 269
358 270
@@ -368,7 +280,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
368 const int port = gpio >> 3; 280 const int port = gpio >> 3;
369 const int port_mask = 1 << (gpio & 7); 281 const int port_mask = 1 << (gpio & 7);
370 282
371 ep93xx_gpio_set_direction(gpio, GPIO_IN); 283 gpio_direction_output(gpio, gpio_get_value(gpio));
372 284
373 switch (type) { 285 switch (type) {
374 case IRQT_RISING: 286 case IRQT_RISING:
@@ -411,7 +323,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
411 desc->status &= ~IRQ_TYPE_SENSE_MASK; 323 desc->status &= ~IRQ_TYPE_SENSE_MASK;
412 desc->status |= type & IRQ_TYPE_SENSE_MASK; 324 desc->status |= type & IRQ_TYPE_SENSE_MASK;
413 325
414 update_gpio_int_params(port); 326 ep93xx_gpio_update_int_params(port);
415 327
416 return 0; 328 return 0;
417} 329}
@@ -549,6 +461,7 @@ static struct platform_device ep93xx_ohci_device = {
549 .resource = ep93xx_ohci_resources, 461 .resource = ep93xx_ohci_resources,
550}; 462};
551 463
464extern void ep93xx_gpio_init(void);
552 465
553void __init ep93xx_init_devices(void) 466void __init ep93xx_init_devices(void)
554{ 467{
@@ -562,6 +475,8 @@ void __init ep93xx_init_devices(void)
562 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 475 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
563 __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG); 476 __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
564 477
478 ep93xx_gpio_init();
479
565 amba_device_register(&uart1_device, &iomem_resource); 480 amba_device_register(&uart1_device, &iomem_resource);
566 amba_device_register(&uart2_device, &iomem_resource); 481 amba_device_register(&uart2_device, &iomem_resource);
567 amba_device_register(&uart3_device, &iomem_resource); 482 amba_device_register(&uart3_device, &iomem_resource);
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
new file mode 100644
index 000000000000..dc2e4c00d989
--- /dev/null
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -0,0 +1,158 @@
1/*
2 * linux/arch/arm/mach-ep93xx/gpio.c
3 *
4 * Generic EP93xx GPIO handling
5 *
6 * Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
7 *
8 * Based on code originally from:
9 * linux/arch/arm/mach-ep93xx/core.c
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/seq_file.h>
19
20#include <asm/arch/ep93xx-regs.h>
21#include <asm/io.h>
22#include <asm/gpio.h>
23
24struct ep93xx_gpio_chip {
25 struct gpio_chip chip;
26
27 unsigned int data_reg;
28 unsigned int data_dir_reg;
29};
30
31#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
32
33/* From core.c */
34extern void ep93xx_gpio_int_mask(unsigned line);
35extern void ep93xx_gpio_update_int_params(unsigned port);
36
37static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
38{
39 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
40 unsigned long flags;
41 u8 v;
42
43 local_irq_save(flags);
44 v = __raw_readb(ep93xx_chip->data_dir_reg);
45 v &= ~(1 << offset);
46 __raw_writeb(v, ep93xx_chip->data_dir_reg);
47 local_irq_restore(flags);
48
49 return 0;
50}
51
52static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
53 unsigned offset, int val)
54{
55 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
56 unsigned long flags;
57 int line;
58 u8 v;
59
60 local_irq_save(flags);
61
62 /* Set the value */
63 v = __raw_readb(ep93xx_chip->data_reg);
64 if (val)
65 v |= (1 << offset);
66 else
67 v &= ~(1 << offset);
68 __raw_writeb(v, ep93xx_chip->data_reg);
69
70 /* Drive as an output */
71 line = chip->base + offset;
72 if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
73 /* Ports A/B/F */
74 ep93xx_gpio_int_mask(line);
75 ep93xx_gpio_update_int_params(line >> 3);
76 }
77
78 v = __raw_readb(ep93xx_chip->data_dir_reg);
79 v |= (1 << offset);
80 __raw_writeb(v, ep93xx_chip->data_dir_reg);
81
82 local_irq_restore(flags);
83
84 return 0;
85}
86
87static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
88{
89 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
90
91 return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
92}
93
94static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
95{
96 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
97 unsigned long flags;
98 u8 v;
99
100 local_irq_save(flags);
101 v = __raw_readb(ep93xx_chip->data_reg);
102 if (val)
103 v |= (1 << offset);
104 else
105 v &= ~(1 << offset);
106 __raw_writeb(v, ep93xx_chip->data_reg);
107 local_irq_restore(flags);
108}
109
110static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
111{
112 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
113 u8 data_reg, data_dir_reg;
114 int i;
115
116 data_reg = __raw_readb(ep93xx_chip->data_reg);
117 data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
118
119 for (i = 0; i < chip->ngpio; i++)
120 seq_printf(s, "GPIO %s%d: %s %s\n", chip->label, i,
121 (data_reg & (1 << i)) ? "set" : "clear",
122 (data_dir_reg & (1 << i)) ? "out" : "in");
123}
124
125#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \
126 { \
127 .chip = { \
128 .label = name, \
129 .direction_input = ep93xx_gpio_direction_input, \
130 .direction_output = ep93xx_gpio_direction_output, \
131 .get = ep93xx_gpio_get, \
132 .set = ep93xx_gpio_set, \
133 .dbg_show = ep93xx_gpio_dbg_show, \
134 .base = base_gpio, \
135 .ngpio = 8, \
136 }, \
137 .data_reg = EP93XX_GPIO_REG(dr), \
138 .data_dir_reg = EP93XX_GPIO_REG(ddr), \
139 }
140
141static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
142 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
143 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
144 EP93XX_GPIO_BANK("C", 0x30, 0x34, 40),
145 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
146 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
147 EP93XX_GPIO_BANK("F", 0x08, 0x18, 16),
148 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
149 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
150};
151
152void __init ep93xx_gpio_init(void)
153{
154 int i;
155
156 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++)
157 gpiochip_add(&ep93xx_gpio_banks[i].chip);
158}
diff --git a/include/asm-arm/arch-ep93xx/gpio.h b/include/asm-arm/arch-ep93xx/gpio.h
index 9b1864bbd9a8..186e7c715f8a 100644
--- a/include/asm-arm/arch-ep93xx/gpio.h
+++ b/include/asm-arm/arch-ep93xx/gpio.h
@@ -101,30 +101,17 @@
101 101
102/* new generic GPIO API - see Documentation/gpio.txt */ 102/* new generic GPIO API - see Documentation/gpio.txt */
103 103
104static inline int gpio_request(unsigned gpio, const char *label) 104#include <asm-generic/gpio.h>
105{
106 if (gpio > EP93XX_GPIO_LINE_MAX)
107 return -EINVAL;
108 return 0;
109}
110 105
111static inline void gpio_free(unsigned gpio) 106#define gpio_get_value __gpio_get_value
112{ 107#define gpio_set_value __gpio_set_value
113} 108#define gpio_cansleep __gpio_cansleep
114
115int gpio_direction_input(unsigned gpio);
116int gpio_direction_output(unsigned gpio, int value);
117int gpio_get_value(unsigned gpio);
118void gpio_set_value(unsigned gpio, int value);
119
120#include <asm-generic/gpio.h> /* cansleep wrappers */
121 109
122/* 110/*
123 * Map GPIO A0..A7 (0..7) to irq 64..71, 111 * Map GPIO A0..A7 (0..7) to irq 64..71,
124 * B0..B7 (7..15) to irq 72..79, and 112 * B0..B7 (7..15) to irq 72..79, and
125 * F0..F7 (16..24) to irq 80..87. 113 * F0..F7 (16..24) to irq 80..87.
126 */ 114 */
127
128static inline int gpio_to_irq(unsigned gpio) 115static inline int gpio_to_irq(unsigned gpio)
129{ 116{
130 if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ) 117 if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ)
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-04 09:48:31 -0500