19 files changed, 273 insertions, 225 deletions

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 51dbf5489b6b..d74990717559 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -24,6 +24,7 @@
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/smp.h>
+#include <linux/cpumask.h>
 
 #include <asm/irq.h>
 #include <asm/io.h>
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index 1b7fcd50c3e2..8880482dcbff 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -433,10 +433,12 @@ void timer_dyn_reprogram(void)
 {
         struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick;
 
-        write_seqlock(&xtime_lock);
-        if (dyn_tick->state & DYN_TICK_ENABLED)
-                dyn_tick->reprogram(next_timer_interrupt() - jiffies);
-        write_sequnlock(&xtime_lock);
+        if (dyn_tick) {
+                write_seqlock(&xtime_lock);
+                if (dyn_tick->state & DYN_TICK_ENABLED)
+                        dyn_tick->reprogram(next_timer_interrupt() - jiffies);
+                write_sequnlock(&xtime_lock);
+        }
 }
 
 static ssize_t timer_show_dyn_tick(struct sys_device *dev, char *buf)
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 04490a9f8f6e..0422e906cc9a 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -38,90 +38,6 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 
-enum ixp4xx_irq_type {
-        IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
-};
-static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type);
-
-/*************************************************************************
- * GPIO acces functions
- *************************************************************************/
-
-/*
- * Configure GPIO line for input, interrupt, or output operation
- *
- * TODO: Enable/disable the irq_desc based on interrupt or output mode.
- * TODO: Should these be named ixp4xx_gpio_?
- */
-void gpio_line_config(u8 line, u32 style)
-{
-        static const int gpio2irq[] = {
-                6, 7, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29
-        };
-        u32 enable;
-        volatile u32 *int_reg;
-        u32 int_style;
-        enum ixp4xx_irq_type irq_type;
-
-        enable = *IXP4XX_GPIO_GPOER;
-
-        if (style & IXP4XX_GPIO_OUT) {
-                enable &= ~((1) << line);
-        } else if (style & IXP4XX_GPIO_IN) {
-                enable |= ((1) << line);
-
-                switch (style & IXP4XX_GPIO_INTSTYLE_MASK)
-                {
-                case (IXP4XX_GPIO_ACTIVE_HIGH):
-                        int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
-                        irq_type = IXP4XX_IRQ_LEVEL;
-                        break;
-                case (IXP4XX_GPIO_ACTIVE_LOW):
-                        int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
-                        irq_type = IXP4XX_IRQ_LEVEL;
-                        break;
-                case (IXP4XX_GPIO_RISING_EDGE):
-                        int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
-                        irq_type = IXP4XX_IRQ_EDGE;
-                        break;
-                case (IXP4XX_GPIO_FALLING_EDGE):
-                        int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
-                        irq_type = IXP4XX_IRQ_EDGE;
-                        break;
-                case (IXP4XX_GPIO_TRANSITIONAL):
-                        int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
-                        irq_type = IXP4XX_IRQ_EDGE;
-                        break;
-                default:
-                        int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
-                        irq_type = IXP4XX_IRQ_LEVEL;
-                        break;
-                }
-
-                if (style & IXP4XX_GPIO_INTSTYLE_MASK)
-                        ixp4xx_config_irq(gpio2irq[line], irq_type);
-
-                if (line >= 8) {        /* pins 8-15 */ 
-                        line -= 8;
-                        int_reg = IXP4XX_GPIO_GPIT2R;
-                }
-                else {                  /* pins 0-7 */
-                        int_reg = IXP4XX_GPIO_GPIT1R;
-                }
-
-                /* Clear the style for the appropriate pin */
-                *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << 
-                                (line * IXP4XX_GPIO_STYLE_SIZE));
-
-                /* Set the new style */
-                *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
-        }
-
-        *IXP4XX_GPIO_GPOER = enable;
-}
-
-EXPORT_SYMBOL(gpio_line_config);
-
 /*************************************************************************
  * IXP4xx chipset I/O mapping
  *************************************************************************/
@@ -165,6 +81,69 @@ void __init ixp4xx_map_io(void)
  *       (be it PCI or something else) configures that GPIO line
  *       as an IRQ.
  **************************************************************************/
+enum ixp4xx_irq_type {
+        IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
+};
+
+static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type);
+
+/*
+ * IRQ -> GPIO mapping table
+ */
+static int irq2gpio[32] = {
+        -1, -1, -1, -1, -1, -1,  0,  1,
+        -1, -1, -1, -1, -1, -1, -1, -1,
+        -1, -1, -1,  2,  3,  4,  5,  6,
+         7,  8,  9, 10, 11, 12, -1, -1,
+};
+
+static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
+{
+        int line = irq2gpio[irq];
+        u32 int_style;
+        enum ixp4xx_irq_type irq_type;
+        volatile u32 *int_reg;
+
+        /*
+         * Only for GPIO IRQs
+         */
+        if (line < 0)
+                return -EINVAL;
+
+        if (type & IRQT_BOTHEDGE) {
+                int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
+                irq_type = IXP4XX_IRQ_EDGE;
+        } else  if (type & IRQT_RISING) {
+                int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
+                irq_type = IXP4XX_IRQ_EDGE;
+        } else if (type & IRQT_FALLING) {
+                int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
+                irq_type = IXP4XX_IRQ_EDGE;
+        } else if (type & IRQT_HIGH) {
+                int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
+                irq_type = IXP4XX_IRQ_LEVEL;
+        } else if (type & IRQT_LOW) {
+                int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
+                irq_type = IXP4XX_IRQ_LEVEL;
+        }
+
+        ixp4xx_config_irq(irq, irq_type);
+
+        if (line >= 8) {        /* pins 8-15 */
+                line -= 8;
+                int_reg = IXP4XX_GPIO_GPIT2R;
+        } else {                /* pins 0-7 */
+                int_reg = IXP4XX_GPIO_GPIT1R;
+        }
+
+        /* Clear the style for the appropriate pin */
+        *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
+                        (line * IXP4XX_GPIO_STYLE_SIZE));
+
+        /* Set the new style */
+        *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
+}
+
 static void ixp4xx_irq_mask(unsigned int irq)
 {
         if (cpu_is_ixp46x() && irq >= 32)
@@ -183,12 +162,6 @@ static void ixp4xx_irq_unmask(unsigned int irq)
 
 static void ixp4xx_irq_ack(unsigned int irq)
 {
-        static int irq2gpio[32] = {
-                -1, -1, -1, -1, -1, -1,  0,  1,
-                -1, -1, -1, -1, -1, -1, -1, -1,
-                -1, -1, -1,  2,  3,  4,  5,  6,
-                 7,  8,  9, 10, 11, 12, -1, -1,
-        };
         int line = (irq < 32) ? irq2gpio[irq] : -1;
 
         if (line >= 0)
@@ -209,12 +182,14 @@ static struct irqchip ixp4xx_irq_level_chip = {
         .ack    = ixp4xx_irq_mask,
         .mask   = ixp4xx_irq_mask,
         .unmask = ixp4xx_irq_level_unmask,
+        .type   = ixp4xx_set_irq_type
 };
 
 static struct irqchip ixp4xx_irq_edge_chip = {
         .ack    = ixp4xx_irq_ack,
         .mask   = ixp4xx_irq_mask,
         .unmask = ixp4xx_irq_unmask,
+        .type   = ixp4xx_set_irq_type
 };
 
 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type)
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c
index afafb42ae129..60de8a94cff5 100644
--- a/arch/arm/mach-ixp4xx/coyote-pci.c
+++ b/arch/arm/mach-ixp4xx/coyote-pci.c
@@ -30,11 +30,8 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
 
 void __init coyote_pci_preinit(void)
 {
-        gpio_line_config(COYOTE_PCI_SLOT0_PIN,
-                        IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
-
-        gpio_line_config(COYOTE_PCI_SLOT1_PIN,
-                        IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+        set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQT_LOW);
+        set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQT_LOW);
 
         gpio_line_isr_clear(COYOTE_PCI_SLOT0_PIN);
         gpio_line_isr_clear(COYOTE_PCI_SLOT1_PIN);
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 411ea9996190..8b2f25322452 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -24,11 +24,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
-void __init coyote_map_io(void)
-{
-        ixp4xx_map_io();
-}
-
 static struct flash_platform_data coyote_flash_data = {
         .map_name       = "cfi_probe",
         .width          = 2,
@@ -107,7 +102,7 @@ MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
         .phys_ram       = PHYS_OFFSET,
         .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
         .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-        .map_io         = coyote_map_io,
+        .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
         .boot_params    = 0x0100,
@@ -125,7 +120,7 @@ MACHINE_START(IXDPG425, "Intel IXDPG425")
         .phys_ram       = PHYS_OFFSET,
         .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
         .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-        .map_io         = coyote_map_io,
+        .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
         .boot_params    = 0x0100,
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
index b18035824e3e..a66484b63d36 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
@@ -35,26 +35,20 @@ extern void ixp4xx_pci_preinit(void);
 extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
 extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
 
-        /*
-        * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h
-        * Slot 0 isn't actually populated with a card connector but
-        * we initialize it anyway in case a future version has the
-        * slot populated or someone with good soldering skills has
-        * some free time.
-        */
-
-
-static void gtwx5715_init_gpio(u8 pin, u32 style)
-{
-        gpio_line_config(pin, style | IXP4XX_GPIO_ACTIVE_LOW);
-
-        if (style & IXP4XX_GPIO_IN) gpio_line_isr_clear(pin);
-}
 
+/*
+ * The exact GPIO pins and IRQs are defined in arch-ixp4xx/gtwx5715.h
+ * Slot 0 isn't actually populated with a card connector but
+ * we initialize it anyway in case a future version has the
+ * slot populated or someone with good soldering skills has
+ * some free time.
+ */
 void __init gtwx5715_pci_preinit(void)
 {
-        gtwx5715_init_gpio(GTWX5715_PCI_SLOT0_INTA_GPIO,        IXP4XX_GPIO_IN);
-        gtwx5715_init_gpio(GTWX5715_PCI_SLOT1_INTA_GPIO,        IXP4XX_GPIO_IN);
+        set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQT_LOW);
+        set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQT_LOW);
+        set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQT_LOW);
+        set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQT_LOW);
 
         ixp4xx_pci_preinit();
 }
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 333459d6aa46..3fd92c5cbaa8 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -101,12 +101,6 @@ static struct platform_device gtwx5715_uart_device = {
         .resource       = gtwx5715_uart_resources,
 };
 
-
-void __init gtwx5715_map_io(void)
-{
-        ixp4xx_map_io();
-}
-
 static struct flash_platform_data gtwx5715_flash_data = {
         .map_name       = "cfi_probe",
         .width          = 2,
@@ -144,7 +138,7 @@ MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
         .phys_ram       = PHYS_OFFSET,
         .phys_io        = IXP4XX_UART2_BASE_PHYS,
         .io_pg_offst    = ((IXP4XX_UART2_BASE_VIRT) >> 18) & 0xfffc,
-        .map_io         = gtwx5715_map_io,
+        .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
         .boot_params    = 0x0100,
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c
index c2ab9ebb5980..f9a1d3e7d692 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -27,14 +27,10 @@
 
 void __init ixdp425_pci_preinit(void)
 {
-        gpio_line_config(IXDP425_PCI_INTA_PIN,
-                                IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
-        gpio_line_config(IXDP425_PCI_INTB_PIN, 
-                                IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
-        gpio_line_config(IXDP425_PCI_INTC_PIN, 
-                                IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
-        gpio_line_config(IXDP425_PCI_INTD_PIN, 
-                                IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+        set_irq_type(IRQ_IXDP425_PCI_INTA, IRQT_LOW);
+        set_irq_type(IRQ_IXDP425_PCI_INTB, IRQT_LOW);
+        set_irq_type(IRQ_IXDP425_PCI_INTC, IRQT_LOW);
+        set_irq_type(IRQ_IXDP425_PCI_INTD, IRQT_LOW);
 
         gpio_line_isr_clear(IXDP425_PCI_INTA_PIN);
         gpio_line_isr_clear(IXDP425_PCI_INTB_PIN);
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index fa0646c8693b..6c14ff3c23a0 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -24,11 +24,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
-void __init ixdp425_map_io(void) 
-{
-        ixp4xx_map_io();
-}
-
 static struct flash_platform_data ixdp425_flash_data = {
         .map_name       = "cfi_probe",
         .width          = 2,
@@ -133,7 +128,7 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
         .phys_ram       = PHYS_OFFSET,
         .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
         .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-        .map_io         = ixdp425_map_io,
+        .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
         .boot_params    = 0x0100,
@@ -145,7 +140,7 @@ MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
         .phys_ram       = PHYS_OFFSET,
         .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
         .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-        .map_io         = ixdp425_map_io,
+        .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
         .boot_params    = 0x0100,
@@ -157,7 +152,7 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
         .phys_ram       = PHYS_OFFSET,
         .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
         .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-        .map_io         = ixdp425_map_io,
+        .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
         .boot_params    = 0x0100,
@@ -176,7 +171,7 @@ MACHINE_START(AVILA, "Gateworks Avila Network Platform")
         .phys_ram       = PHYS_OFFSET,
         .phys_io        = IXP4XX_PERIPHERAL_BASE_PHYS,
         .io_pg_offst    = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
-        .map_io         = ixdp425_map_io,
+        .map_io         = ixp4xx_map_io,
         .init_irq       = ixp4xx_init_irq,
         .timer          = &ixp4xx_timer,
         .boot_params    = 0x0100,
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
index ce4563f00676..fe5e7660de1d 100644
--- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
@@ -29,8 +29,8 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
 
 void __init ixdpg425_pci_preinit(void)
 {
-        gpio_line_config(6, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
-        gpio_line_config(7, IXP4XX_GPIO_IN | IXP4XX_GPIO_ACTIVE_LOW);
+        set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW);
+        set_irq_type(IRQ_IXP4XX_GPIO7, IRQT_LOW);
 
         gpio_line_isr_clear(6);
         gpio_line_isr_clear(7);
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index 9a66050e887d..f59608268751 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -388,6 +388,7 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
                                 unsigned long hclk,
                                 unsigned long pclk)
 {
+        unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
         struct clk *clkp = init_clocks;
         int ptr;
         int ret;
@@ -446,5 +447,13 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
                 }
         }
 
+        /* show the clock-slow value */
+
+        printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
+               print_mhz(xtal / ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
+               (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
+               (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
+               (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
+
         return 0;
 }
diff --git a/arch/arm/mach-s3c2410/s3c2440-clock.c b/arch/arm/mach-s3c2410/s3c2440-clock.c
index b018a1f680ce..c67e0979aec3 100644
--- a/arch/arm/mach-s3c2410/s3c2440-clock.c
+++ b/arch/arm/mach-s3c2410/s3c2440-clock.c
@@ -68,6 +68,7 @@ static struct clk s3c2440_clk_ac97 = {
 static int s3c2440_clk_add(struct sys_device *sysdev)
 {
         unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
+        unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
         struct clk *clk_h;
         struct clk *clk_p;
         struct clk *clk_xtal;
@@ -80,8 +81,9 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
 
         s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate);
 
-        printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz\n",
-               print_mhz(s3c2440_clk_upll.rate));
+        printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz, DVS %s\n",
+               print_mhz(s3c2440_clk_upll.rate),
+               (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
 
         clk_p = clk_get(NULL, "pclk");
         clk_h = clk_get(NULL, "hclk");
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 81f4a8a2d34b..4b39d867ac14 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -45,7 +45,7 @@
 
 #define LDST_P_EQ_U(i)  ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
 
-#define LDSTH_I_BIT(i)  (i & (1 << 22))         /* half-word immed      */
+#define LDSTHD_I_BIT(i) (i & (1 << 22))         /* double/half-word immed */
 #define LDM_S_BIT(i)    (i & (1 << 22))         /* write CPSR from SPSR */
 
 #define RN_BITS(i)      ((i >> 16) & 15)        /* Rn                   */
@@ -68,6 +68,7 @@ static unsigned long ai_sys;
 static unsigned long ai_skipped;
 static unsigned long ai_half;
 static unsigned long ai_word;
+static unsigned long ai_dword;
 static unsigned long ai_multi;
 static int ai_usermode;
 
@@ -93,6 +94,8 @@ proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
         p += sprintf(p, "Skipped:\t%lu\n", ai_skipped);
         p += sprintf(p, "Half:\t\t%lu\n", ai_half);
         p += sprintf(p, "Word:\t\t%lu\n", ai_word);
+        if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
+                p += sprintf(p, "DWord:\t\t%lu\n", ai_dword);
         p += sprintf(p, "Multi:\t\t%lu\n", ai_multi);
         p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode,
                         usermode_action[ai_usermode]);
@@ -283,12 +286,6 @@ do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *r
 {
         unsigned int rd = RD_BITS(instr);
 
-        if ((instr & 0x01f00ff0) == 0x01000090)
-                goto swp;
-
-        if ((instr & 0x90) != 0x90 || (instr & 0x60) == 0)
-                goto bad;
-
         ai_half += 1;
 
         if (user_mode(regs))
@@ -323,10 +320,47 @@ do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *r
 
         return TYPE_LDST;
 
- swp:
-        printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
- bad:
-        return TYPE_ERROR;
+ fault:
+        return TYPE_FAULT;
+}
+
+static int
+do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
+                      struct pt_regs *regs)
+{
+        unsigned int rd = RD_BITS(instr);
+
+        ai_dword += 1;
+
+        if (user_mode(regs))
+                goto user;
+
+        if ((instr & 0xf0) == 0xd0) {
+                unsigned long val;
+                get32_unaligned_check(val, addr);
+                regs->uregs[rd] = val;
+                get32_unaligned_check(val, addr+4);
+                regs->uregs[rd+1] = val;
+        } else {
+                put32_unaligned_check(regs->uregs[rd], addr);
+                put32_unaligned_check(regs->uregs[rd+1], addr+4);
+        }
+
+        return TYPE_LDST;
+
+ user:
+        if ((instr & 0xf0) == 0xd0) {
+                unsigned long val;
+                get32t_unaligned_check(val, addr);
+                regs->uregs[rd] = val;
+                get32t_unaligned_check(val, addr+4);
+                regs->uregs[rd+1] = val;
+        } else {
+                put32t_unaligned_check(regs->uregs[rd], addr);
+                put32t_unaligned_check(regs->uregs[rd+1], addr+4);
+        }
+
+        return TYPE_LDST;
 
  fault:
         return TYPE_FAULT;
@@ -617,12 +651,20 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
         regs->ARM_pc += thumb_mode(regs) ? 2 : 4;
 
         switch (CODING_BITS(instr)) {
-        case 0x00000000:        /* ldrh or strh */
-                if (LDSTH_I_BIT(instr))
+        case 0x00000000:        /* 3.13.4 load/store instruction extensions */
+                if (LDSTHD_I_BIT(instr))
                         offset.un = (instr & 0xf00) >> 4 | (instr & 15);
                 else
                         offset.un = regs->uregs[RM_BITS(instr)];
-                handler = do_alignment_ldrhstrh;
+
+                if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
+                    (instr & 0x001000f0) == 0x001000f0)   /* LDRSH */
+                        handler = do_alignment_ldrhstrh;
+                else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
+                         (instr & 0x001000f0) == 0x000000f0)   /* STRD */
+                        handler = do_alignment_ldrdstrd;
+                else
+                        goto bad;
                 break;
 
         case 0x04000000:        /* ldr or str immediate */
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index 3c655c54e231..4dae00bf7a56 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -275,11 +275,9 @@ alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
         int i;
 
         for (i = 0; i < 16; i += 1) {
-                alloc_init_section(virt, phys & SUPERSECTION_MASK,
-                                   prot | PMD_SECT_SUPER);
+                alloc_init_section(virt, phys, prot | PMD_SECT_SUPER);
 
                 virt += (PGDIR_SIZE / 2);
-                phys += (PGDIR_SIZE / 2);
         }
 }
 
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index 7495026e2c18..e350dcb544e8 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -383,39 +383,45 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
                 *vaddr++ = inl(io_addr);
 }
 
-#define __is_io_address(p)      (((unsigned long)p >= 0x0) && \
-                                        ((unsigned long)p <= 0x0000ffff))
+#define PIO_OFFSET      0x10000UL
+#define PIO_MASK        0x0ffffUL
+
+#define __is_io_address(p)      (((unsigned long)p >= PIO_OFFSET) && \
+                                        ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
 static inline unsigned int
-__ixp4xx_ioread8(void __iomem *port)
+__ixp4xx_ioread8(void __iomem *addr)
 {
+        unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                return  (unsigned int)__ixp4xx_inb((unsigned int)port);
+                return  (unsigned int)__ixp4xx_inb(port & PIO_MASK);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                return (unsigned int)__raw_readb((u32)port);
+                return (unsigned int)__raw_readb(port);
 #else
-                return (unsigned int)__ixp4xx_readb((u32)port);
+                return (unsigned int)__ixp4xx_readb(port);
 #endif
 }
 
 static inline void
-__ixp4xx_ioread8_rep(u32 port, u8 *vaddr, u32 count)
+__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
 {
+        unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_insb(port, vaddr, count);
+                __ixp4xx_insb(port & PIO_MASK, vaddr, count);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_readsb((void __iomem *)port, vaddr, count);
+                __raw_readsb(addr, vaddr, count);
 #else
                 __ixp4xx_readsb(port, vaddr, count);
 #endif
 }
 
 static inline unsigned int
-__ixp4xx_ioread16(void __iomem *port)
+__ixp4xx_ioread16(void __iomem *addr)
 {
+        unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                return  (unsigned int)__ixp4xx_inw((unsigned int)port);
+                return  (unsigned int)__ixp4xx_inw(port & PIO_MASK);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 return le16_to_cpu(__raw_readw((u32)port));
@@ -425,23 +431,25 @@ __ixp4xx_ioread16(void __iomem *port)
 }
 
 static inline void
-__ixp4xx_ioread16_rep(u32 port, u16 *vaddr, u32 count)
+__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
 {
+        unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_insw(port, vaddr, count);
+                __ixp4xx_insw(port & PIO_MASK, vaddr, count);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_readsw((void __iomem *)port, vaddr, count);
+                __raw_readsw(addr, vaddr, count);
 #else
                 __ixp4xx_readsw(port, vaddr, count);
 #endif
 }
 
 static inline unsigned int
-__ixp4xx_ioread32(void __iomem *port)
+__ixp4xx_ioread32(void __iomem *addr)
 {
+        unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                return  (unsigned int)__ixp4xx_inl((unsigned int)port);
+                return  (unsigned int)__ixp4xx_inl(port & PIO_MASK);
         else {
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
                 return le32_to_cpu(__raw_readl((u32)port));
@@ -452,90 +460,100 @@ __ixp4xx_ioread32(void __iomem *port)
 }
 
 static inline void
-__ixp4xx_ioread32_rep(u32 port, u32 *vaddr, u32 count)
+__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
 {
+        unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_insl(port, vaddr, count);
+                __ixp4xx_insl(port & PIO_MASK, vaddr, count);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_readsl((void __iomem *)port, vaddr, count);
+                __raw_readsl(addr, vaddr, count);
 #else
                 __ixp4xx_readsl(port, vaddr, count);
 #endif
 }
 
 static inline void
-__ixp4xx_iowrite8(u8 value, void __iomem *port)
+__ixp4xx_iowrite8(u8 value, void __iomem *addr)
 {
+        unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_outb(value, (unsigned int)port);
+                __ixp4xx_outb(value, port & PIO_MASK);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_writeb(value, (u32)port);
+                __raw_writeb(value, port);
 #else
-                __ixp4xx_writeb(value, (u32)port);
+                __ixp4xx_writeb(value, port);
 #endif
 }
 
 static inline void
-__ixp4xx_iowrite8_rep(u32 port, u8 *vaddr, u32 count)
+__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
 {
+        unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_outsb(port, vaddr, count);
+                __ixp4xx_outsb(port & PIO_MASK, vaddr, count);
+        else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_writesb((void __iomem *)port, vaddr, count);
+                __raw_writesb(addr, vaddr, count);
 #else
                 __ixp4xx_writesb(port, vaddr, count);
 #endif
 }
 
 static inline void
-__ixp4xx_iowrite16(u16 value, void __iomem *port)
+__ixp4xx_iowrite16(u16 value, void __iomem *addr)
 {
+        unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_outw(value, (unsigned int)port);
+                __ixp4xx_outw(value, port & PIO_MASK);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_writew(cpu_to_le16(value), (u32)port);
+                __raw_writew(cpu_to_le16(value), addr);
 #else
-                __ixp4xx_writew(value, (u32)port);
+                __ixp4xx_writew(value, port);
 #endif
 }
 
 static inline void
-__ixp4xx_iowrite16_rep(u32 port, u16 *vaddr, u32 count)
+__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
 {
+        unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_outsw(port, vaddr, count);
+                __ixp4xx_outsw(port & PIO_MASK, vaddr, count);
+        else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_readsw((void __iomem *)port, vaddr, count);
+                __raw_writesw(addr, vaddr, count);
 #else
                 __ixp4xx_writesw(port, vaddr, count);
 #endif
 }
 
 static inline void
-__ixp4xx_iowrite32(u32 value, void __iomem *port)
+__ixp4xx_iowrite32(u32 value, void __iomem *addr)
 {
+        unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_outl(value, (unsigned int)port);
+                __ixp4xx_outl(value, port & PIO_MASK);
         else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_writel(cpu_to_le32(value), (u32)port);
+                __raw_writel(cpu_to_le32(value), port);
 #else
-                __ixp4xx_writel(value, (u32)port);
+                __ixp4xx_writel(value, port);
 #endif
 }
 
 static inline void
-__ixp4xx_iowrite32_rep(u32 port, u32 *vaddr, u32 count)
+__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
 {
+        unsigned long port = (unsigned long __force)addr;
         if (__is_io_address(port))
-                __ixp4xx_outsl(port, vaddr, count);
+                __ixp4xx_outsl(port & PIO_MASK, vaddr, count);
+        else
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
-                __raw_readsl((void __iomem *)port, vaddr, count);
+                __raw_writesl(addr, vaddr, count);
 #else
-                __ixp4xx_outsl(port, vaddr, count);
+                __ixp4xx_writesl(port, vaddr, count);
 #endif
 }
 
@@ -555,7 +573,7 @@ __ixp4xx_iowrite32_rep(u32 port, u32 *vaddr, u32 count)
 #define iowrite16_rep(p, v, c)          __ixp4xx_iowrite16_rep(p, v, c)
 #define iowrite32_rep(p, v, c)          __ixp4xx_iowrite32_rep(p, v, c)
 
-#define ioport_map(port, nr)            ((void __iomem*)port)
+#define ioport_map(port, nr)            ((void __iomem*)(port + PIO_OFFSET))
 #define ioport_unmap(addr)
 
 #endif  //  __ASM_ARM_ARCH_IO_H
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index 3a626c03ea26..d13ee7f78c70 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -83,17 +83,6 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
 #define IXP4XX_GPIO_OUT                 0x1
 #define IXP4XX_GPIO_IN                  0x2
 
-#define IXP4XX_GPIO_INTSTYLE_MASK       0x7C  /* Bits [6:2] define interrupt style */
-
-/* 
- * GPIO interrupt types.
- */
-#define IXP4XX_GPIO_ACTIVE_HIGH         0x4 /* Default */
-#define IXP4XX_GPIO_ACTIVE_LOW          0x8
-#define IXP4XX_GPIO_RISING_EDGE         0x10
-#define IXP4XX_GPIO_FALLING_EDGE        0x20
-#define IXP4XX_GPIO_TRANSITIONAL        0x40
-
 /* GPIO signal types */
 #define IXP4XX_GPIO_LOW                 0
 #define IXP4XX_GPIO_HIGH                1
@@ -102,7 +91,13 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
 #define IXP4XX_GPIO_CLK_0               14
 #define IXP4XX_GPIO_CLK_1               15
 
-extern void gpio_line_config(u8 line, u32 style);
+static inline void gpio_line_config(u8 line, u32 direction)
+{
+        if (direction == IXP4XX_GPIO_OUT)
+                *IXP4XX_GPIO_GPOER |= (1 << line);
+        else
+                *IXP4XX_GPIO_GPOER &= ~(1 << line);
+}
 
 static inline void gpio_line_get(u8 line, int *value)
 {
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 51f0fe0ac165..939d9e5020a0 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -818,6 +818,23 @@
 #define UDCOTGICR_IEIDF (1 << 0)        /* OTG ID Change Falling Edge
                                            Interrupt Enable */
 
+#define UP2OCR            __REG(0x40600020)  /* USB Port 2 Output Control register */
+
+#define UP2OCR_CPVEN    (1 << 0)        /* Charge Pump Vbus Enable */
+#define UP2OCR_CPVPE    (1 << 1)        /* Charge Pump Vbus Pulse Enable */
+#define UP2OCR_DPPDE    (1 << 2)        /* Host Port 2 Transceiver D+ Pull Down Enable */
+#define UP2OCR_DMPDE    (1 << 3)        /* Host Port 2 Transceiver D- Pull Down Enable */
+#define UP2OCR_DPPUE    (1 << 4)        /* Host Port 2 Transceiver D+ Pull Up Enable */
+#define UP2OCR_DMPUE    (1 << 5)        /* Host Port 2 Transceiver D- Pull Up Enable */
+#define UP2OCR_DPPUBE   (1 << 6)        /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
+#define UP2OCR_DMPUBE   (1 << 7)        /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
+#define UP2OCR_EXSP             (1 << 8)        /* External Transceiver Speed Control */
+#define UP2OCR_EXSUS    (1 << 9)        /* External Transceiver Speed Enable */
+#define UP2OCR_IDON             (1 << 10)       /* OTG ID Read Enable */
+#define UP2OCR_HXS              (1 << 16)       /* Host Port 2 Transceiver Output Select */
+#define UP2OCR_HXOE             (1 << 17)       /* Host Port 2 Transceiver Output Enable */
+#define UP2OCR_SEOS             (1 << 24)       /* Single-Ended Output Select */
+
 #define UDCCSN(x)       __REG2(0x40600100, (x) << 2)
 #define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
 #define UDCCSR0_SA      (1 << 7)        /* Setup Active */
@@ -1423,6 +1440,7 @@
 #define GPIO84_NSSP_RX          (84 | GPIO_ALT_FN_2_IN)
 #define GPIO85_nPCE_1_MD        (85 | GPIO_ALT_FN_1_OUT)
 #define GPIO92_MMCDAT0_MD       (92 | GPIO_ALT_FN_1_OUT)
+#define GPIO104_pSKTSEL_MD      (104 | GPIO_ALT_FN_1_OUT)
 #define GPIO109_MMCDAT1_MD      (109 | GPIO_ALT_FN_1_OUT)
 #define GPIO110_MMCDAT2_MD      (110 | GPIO_ALT_FN_1_OUT)
 #define GPIO110_MMCCS0_MD       (110 | GPIO_ALT_FN_1_OUT)
@@ -1510,6 +1528,8 @@
 #define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
 #define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
 
+#define PSLR_SL_ROD     (1 << 20)       /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
+
 #define PCFR_RO         (1 << 15)       /* RDH Override */
 #define PCFR_PO         (1 << 14)       /* PH Override */
 #define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
@@ -1517,6 +1537,7 @@
 #define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
 #define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
 #define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
+#define PCFR_GPR_EN     (1 << 4)        /* nRESET_GPIO Pin Enable */
 #define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
 #define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
 #define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
@@ -1810,6 +1831,11 @@
 #define LCCR0_PDD_S     12
 #define LCCR0_BM        (1 << 20)       /* Branch mask */
 #define LCCR0_OUM       (1 << 21)       /* Output FIFO underrun mask */
+#define LCCR0_LCDT      (1 << 22)       /* LCD panel type */
+#define LCCR0_RDSTM     (1 << 23)       /* Read status interrupt mask */
+#define LCCR0_CMDIM     (1 << 24)       /* Command interrupt mask */
+#define LCCR0_OUC       (1 << 25)       /* Overlay Underlay control bit */
+#define LCCR0_LDDALT    (1 << 26)       /* LDD alternate mapping control */
 
 #define LCCR1_PPL       Fld (10, 0)      /* Pixels Per Line - 1 */
 #define LCCR1_DisWdth(Pixel)            /* Display Width [1..800 pix.]  */ \
@@ -2062,7 +2088,10 @@
 #define UHCFMN          __REG(0x4C00003C) /* UHC Frame Number */
 #define UHCPERS         __REG(0x4C000040) /* UHC Periodic Start */
 #define UHCLS           __REG(0x4C000044) /* UHC Low Speed Threshold */
+
 #define UHCRHDA         __REG(0x4C000048) /* UHC Root Hub Descriptor A */
+#define UHCRHDA_NOCP    (1 << 12)       /* No over current protection */
+
 #define UHCRHDB         __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
 #define UHCRHS          __REG(0x4C000050) /* UHC Root Hub Status */
 #define UHCRHPS1        __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index e5e938b79acc..16f4c3cc1388 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -1,7 +1,7 @@
 /* linux/include/asm/arch-s3c2410/regs-clock.h
  *
- * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
+ * Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://armlinux.simtec.co.uk/
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -17,6 +17,7 @@
  *    29-Sep-2004 Ben Dooks         Fixed usage for assembly inclusion
  *    10-Feb-2005 Ben Dooks         Fixed CAMDIVN address (Guillaume Gourat)
  *    10-Mar-2005 Lucas Villa Real  Changed S3C2410_VA to S3C24XX_VA
+ *    27-Aug-2005 Ben Dooks         Add clock-slow info
  */
 
 #ifndef __ASM_ARM_REGS_CLOCK
@@ -74,6 +75,12 @@
 #define S3C2410_CLKDIVN_PDIVN        (1<<0)
 #define S3C2410_CLKDIVN_HDIVN        (1<<1)
 
+#define S3C2410_CLKSLOW_UCLK_OFF        (1<<7)
+#define S3C2410_CLKSLOW_MPLL_OFF        (1<<5)
+#define S3C2410_CLKSLOW_SLOW            (1<<4)
+#define S3C2410_CLKSLOW_SLOWVAL(x)      (x)
+#define S3C2410_CLKSLOW_GET_SLOWVAL(x)  ((x) & 7)
+
 #ifndef __ASSEMBLY__
 
 static inline unsigned int
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index abb36e54c966..94619ccee789 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -515,7 +515,6 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
 #define __ARCH_WANT_SYS_TIME
 #define __ARCH_WANT_SYS_UTIME
 #define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
 #define __ARCH_WANT_SYS_GETPGRP
 #define __ARCH_WANT_SYS_LLSEEK
 #define __ARCH_WANT_SYS_NICE