2 files changed, 15 insertions, 1 deletions

diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index b84ec6a2fc94..c2b9dc4fce5d 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -653,7 +653,14 @@ finish_tlb_load:
         rlwimi  r10, r11, 0, 26, 26             /* UX = HWEXEC & USER */
 
         rlwimi  r12, r10, 0, 26, 31             /* Insert static perms */
-        rlwinm  r12, r12, 0, 20, 15             /* Clear U0-U3 */
+
+        /*
+         * Clear U0-U3 and WL1 IL1I IL1D IL2I IL2D bits which are added
+         * on newer 440 cores like the 440x6 used on AMCC 460EX/460GT (see
+         * include/asm-powerpc/pgtable-ppc32.h for details).
+         */
+        rlwinm  r12, r12, 0, 20, 10
+
         tlbwe   r12, r13, PPC44x_TLB_ATTRIB     /* Write ATTRIB */
 
         /* Done...restore registers and get out of here.
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index 7c97b5a08d08..c08e714d0c42 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -209,6 +209,13 @@ extern int icache_44x_need_flush;
  *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
  *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
  *
+ * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional
+ * TLB2 storage attibute fields. Those are:
+ *
+ *   TLB2:
+ *   0...10    11   12   13   14   15   16...31
+ *   no change WL1  IL1I IL1D IL2I IL2D no change
+ *
  * There are some constrains and options, to decide mapping software bits
  * into TLB entry.
  *