181 files changed, 5383 insertions, 2485 deletions

diff --git a/Documentation/cgroups/cgroups.txt b/Documentation/cgroups/cgroups.txt
index 455d4e6d346d..0b33bfe7dde9 100644
--- a/Documentation/cgroups/cgroups.txt
+++ b/Documentation/cgroups/cgroups.txt
@@ -227,7 +227,14 @@ as the path relative to the root of the cgroup file system.
 Each cgroup is represented by a directory in the cgroup file system
 containing the following files describing that cgroup:
 
- - tasks: list of tasks (by pid) attached to that cgroup
+ - tasks: list of tasks (by pid) attached to that cgroup.  This list
+   is not guaranteed to be sorted.  Writing a thread id into this file
+   moves the thread into this cgroup.
+ - cgroup.procs: list of tgids in the cgroup.  This list is not
+   guaranteed to be sorted or free of duplicate tgids, and userspace
+   should sort/uniquify the list if this property is required.
+   Writing a tgid into this file moves all threads with that tgid into
+   this cgroup.
  - notify_on_release flag: run the release agent on exit?
  - release_agent: the path to use for release notifications (this file
    exists in the top cgroup only)
@@ -374,7 +381,7 @@ Now you want to do something with this cgroup.
 
 In this directory you can find several files:
 # ls
-notify_on_release tasks
+cgroup.procs notify_on_release tasks
 (plus whatever files added by the attached subsystems)
 
 Now attach your shell to this cgroup:
diff --git a/Documentation/isdn/INTERFACE.CAPI b/Documentation/isdn/INTERFACE.CAPI
index 686e107923ec..5fe8de5cc727 100644
--- a/Documentation/isdn/INTERFACE.CAPI
+++ b/Documentation/isdn/INTERFACE.CAPI
@@ -60,10 +60,9 @@ open() operation on regular files or character devices.
 
 After a successful return from register_appl(), CAPI messages from the
 application may be passed to the driver for the device via calls to the
-send_message() callback function. The CAPI message to send is stored in the
-data portion of an skb. Conversely, the driver may call Kernel CAPI's
-capi_ctr_handle_message() function to pass a received CAPI message to Kernel
-CAPI for forwarding to an application, specifying its ApplID.
+send_message() callback function. Conversely, the driver may call Kernel
+CAPI's capi_ctr_handle_message() function to pass a received CAPI message to
+Kernel CAPI for forwarding to an application, specifying its ApplID.
 
 Deregistration requests (CAPI operation CAPI_RELEASE) from applications are
 forwarded as calls to the release_appl() callback function, passing the same
@@ -142,6 +141,7 @@ u16  (*send_message)(struct capi_ctr *ctrlr, struct sk_buff *skb)
         to accepting or queueing the message. Errors occurring during the
         actual processing of the message should be signaled with an
         appropriate reply message.
+        May be called in process or interrupt context.
         Calls to this function are not serialized by Kernel CAPI, ie. it must
         be prepared to be re-entered.
 
@@ -154,7 +154,8 @@ read_proc_t *ctr_read_proc
         system entry, /proc/capi/controllers/<n>; will be called with a
         pointer to the device's capi_ctr structure as the last (data) argument
 
-Note: Callback functions are never called in interrupt context.
+Note: Callback functions except send_message() are never called in interrupt
+context.
 
 - to be filled in before calling capi_ctr_ready():
 
@@ -171,14 +172,40 @@ u8 serial[CAPI_SERIAL_LEN]
         value to return for CAPI_GET_SERIAL
 
 
-4.3 The _cmsg Structure
+4.3 SKBs
+
+CAPI messages are passed between Kernel CAPI and the driver via send_message()
+and capi_ctr_handle_message(), stored in the data portion of a socket buffer
+(skb).  Each skb contains a single CAPI message coded according to the CAPI 2.0
+standard.
+
+For the data transfer messages, DATA_B3_REQ and DATA_B3_IND, the actual
+payload data immediately follows the CAPI message itself within the same skb.
+The Data and Data64 parameters are not used for processing. The Data64
+parameter may be omitted by setting the length field of the CAPI message to 22
+instead of 30.
+
+
+4.4 The _cmsg Structure
 
 (declared in <linux/isdn/capiutil.h>)
 
 The _cmsg structure stores the contents of a CAPI 2.0 message in an easily
-accessible form. It contains members for all possible CAPI 2.0 parameters, of
-which only those appearing in the message type currently being processed are
-actually used. Unused members should be set to zero.
+accessible form. It contains members for all possible CAPI 2.0 parameters,
+including subparameters of the Additional Info and B Protocol structured
+parameters, with the following exceptions:
+
+* second Calling party number (CONNECT_IND)
+
+* Data64 (DATA_B3_REQ and DATA_B3_IND)
+
+* Sending complete (subparameter of Additional Info, CONNECT_REQ and INFO_REQ)
+
+* Global Configuration (subparameter of B Protocol, CONNECT_REQ, CONNECT_RESP
+  and SELECT_B_PROTOCOL_REQ)
+
+Only those parameters appearing in the message type currently being processed
+are actually used. Unused members should be set to zero.
 
 Members are named after the CAPI 2.0 standard names of the parameters they
 represent. See <linux/isdn/capiutil.h> for the exact spelling. Member data
@@ -190,18 +217,19 @@ u16         for CAPI parameters of type 'word'
 
 u32         for CAPI parameters of type 'dword'
 
-_cstruct    for CAPI parameters of type 'struct' not containing any
-            variably-sized (struct) subparameters (eg. 'Called Party Number')
+_cstruct    for CAPI parameters of type 'struct'
             The member is a pointer to a buffer containing the parameter in
             CAPI encoding (length + content). It may also be NULL, which will
             be taken to represent an empty (zero length) parameter.
+            Subparameters are stored in encoded form within the content part.
 
-_cmstruct   for CAPI parameters of type 'struct' containing 'struct'
-            subparameters ('Additional Info' and 'B Protocol')
+_cmstruct   alternative representation for CAPI parameters of type 'struct'
+            (used only for the 'Additional Info' and 'B Protocol' parameters)
             The representation is a single byte containing one of the values:
-            CAPI_DEFAULT: the parameter is empty
-            CAPI_COMPOSE: the values of the subparameters are stored
-            individually in the corresponding _cmsg structure members
+            CAPI_DEFAULT: The parameter is empty/absent.
+            CAPI_COMPOSE: The parameter is present.
+            Subparameter values are stored individually in the corresponding
+            _cmsg structure members.
 
 Functions capi_cmsg2message() and capi_message2cmsg() are provided to convert
 messages between their transport encoding described in the CAPI 2.0 standard
@@ -297,3 +325,26 @@ char *capi_cmd2str(u8 Command, u8 Subcommand)
         be NULL if the command/subcommand is not one of those defined in the
         CAPI 2.0 standard.
 
+
+7. Debugging
+
+The module kernelcapi has a module parameter showcapimsgs controlling some
+debugging output produced by the module. It can only be set when the module is
+loaded, via a parameter "showcapimsgs=<n>" to the modprobe command, either on
+the command line or in the configuration file.
+
+If the lowest bit of showcapimsgs is set, kernelcapi logs controller and
+application up and down events.
+
+In addition, every registered CAPI controller has an associated traceflag
+parameter controlling how CAPI messages sent from and to tha controller are
+logged. The traceflag parameter is initialized with the value of the
+showcapimsgs parameter when the controller is registered, but can later be
+changed via the MANUFACTURER_REQ command KCAPI_CMD_TRACE.
+
+If the value of traceflag is non-zero, CAPI messages are logged.
+DATA_B3 messages are only logged if the value of traceflag is > 2.
+
+If the lowest bit of traceflag is set, only the command/subcommand and message
+length are logged. Otherwise, kernelcapi logs a readable representation of
+the entire message.
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 6fa7292947e5..9107b387e91f 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -671,6 +671,7 @@ and is between 256 and 4096 characters. It is defined in the file
         earlyprintk=    [X86,SH,BLACKFIN]
                         earlyprintk=vga
                         earlyprintk=serial[,ttySn[,baudrate]]
+                        earlyprintk=ttySn[,baudrate]
                         earlyprintk=dbgp[debugController#]
 
                         Append ",keep" to not disable it when the real console
diff --git a/Documentation/networking/pktgen.txt b/Documentation/networking/pktgen.txt
index c6cf4a3c16e0..61bb645d50e0 100644
--- a/Documentation/networking/pktgen.txt
+++ b/Documentation/networking/pktgen.txt
@@ -90,6 +90,11 @@ Examples:
  pgset "dstmac 00:00:00:00:00:00"    sets MAC destination address
  pgset "srcmac 00:00:00:00:00:00"    sets MAC source address
 
+ pgset "queue_map_min 0" Sets the min value of tx queue interval
+ pgset "queue_map_max 7" Sets the max value of tx queue interval, for multiqueue devices
+                         To select queue 1 of a given device,
+                         use queue_map_min=1 and queue_map_max=1
+
  pgset "src_mac_count 1" Sets the number of MACs we'll range through.  
                          The 'minimum' MAC is what you set with srcmac.
 
@@ -101,6 +106,9 @@ Examples:
                               IPDST_RND, UDPSRC_RND,
                               UDPDST_RND, MACSRC_RND, MACDST_RND 
                               MPLS_RND, VID_RND, SVID_RND
+                              QUEUE_MAP_RND # queue map random
+                              QUEUE_MAP_CPU # queue map mirrors smp_processor_id()
+
 
  pgset "udp_src_min 9"   set UDP source port min, If < udp_src_max, then
                          cycle through the port range.
diff --git a/Documentation/vm/ksm.txt b/Documentation/vm/ksm.txt
index 72a22f65960e..262d8e6793a3 100644
--- a/Documentation/vm/ksm.txt
+++ b/Documentation/vm/ksm.txt
@@ -52,15 +52,15 @@ The KSM daemon is controlled by sysfs files in /sys/kernel/mm/ksm/,
 readable by all but writable only by root:
 
 max_kernel_pages - set to maximum number of kernel pages that KSM may use
-                   e.g. "echo 2000 > /sys/kernel/mm/ksm/max_kernel_pages"
+                   e.g. "echo 100000 > /sys/kernel/mm/ksm/max_kernel_pages"
                    Value 0 imposes no limit on the kernel pages KSM may use;
                    but note that any process using MADV_MERGEABLE can cause
                    KSM to allocate these pages, unswappable until it exits.
-                   Default: 2000 (chosen for demonstration purposes)
+                   Default: quarter of memory (chosen to not pin too much)
 
 pages_to_scan    - how many present pages to scan before ksmd goes to sleep
-                   e.g. "echo 200 > /sys/kernel/mm/ksm/pages_to_scan"
-                   Default: 200 (chosen for demonstration purposes)
+                   e.g. "echo 100 > /sys/kernel/mm/ksm/pages_to_scan"
+                   Default: 100 (chosen for demonstration purposes)
 
 sleep_millisecs  - how many milliseconds ksmd should sleep before next scan
                    e.g. "echo 20 > /sys/kernel/mm/ksm/sleep_millisecs"
@@ -70,7 +70,8 @@ run              - set 0 to stop ksmd from running but keep merged pages,
                    set 1 to run ksmd e.g. "echo 1 > /sys/kernel/mm/ksm/run",
                    set 2 to stop ksmd and unmerge all pages currently merged,
                          but leave mergeable areas registered for next run
-                   Default: 1 (for immediate use by apps which register)
+                   Default: 0 (must be changed to 1 to activate KSM,
+                               except if CONFIG_SYSFS is disabled)
 
 The effectiveness of KSM and MADV_MERGEABLE is shown in /sys/kernel/mm/ksm/:
 
@@ -86,4 +87,4 @@ pages_volatile embraces several different kinds of activity, but a high
 proportion there would also indicate poor use of madvise MADV_MERGEABLE.
 
 Izik Eidus,
-Hugh Dickins, 30 July 2009
+Hugh Dickins, 24 Sept 2009
diff --git a/Documentation/vm/page-types.c b/Documentation/vm/page-types.c
index fa1a30d9e9d5..3ec4f2a22585 100644
--- a/Documentation/vm/page-types.c
+++ b/Documentation/vm/page-types.c
@@ -2,7 +2,10 @@
  * page-types: Tool for querying page flags
  *
  * Copyright (C) 2009 Intel corporation
- * Copyright (C) 2009 Wu Fengguang <fengguang.wu@intel.com>
+ *
+ * Authors: Wu Fengguang <fengguang.wu@intel.com>
+ *
+ * Released under the General Public License (GPL).
  */
 
 #define _LARGEFILE64_SOURCE
@@ -69,7 +72,9 @@
 #define KPF_COMPOUND_TAIL       16
 #define KPF_HUGE                17
 #define KPF_UNEVICTABLE         18
+#define KPF_HWPOISON            19
 #define KPF_NOPAGE              20
+#define KPF_KSM                 21
 
 /* [32-] kernel hacking assistances */
 #define KPF_RESERVED            32
@@ -116,7 +121,9 @@ static char *page_flag_names[] = {
         [KPF_COMPOUND_TAIL]     = "T:compound_tail",
         [KPF_HUGE]              = "G:huge",
         [KPF_UNEVICTABLE]       = "u:unevictable",
+        [KPF_HWPOISON]          = "X:hwpoison",
         [KPF_NOPAGE]            = "n:nopage",
+        [KPF_KSM]               = "x:ksm",
 
         [KPF_RESERVED]          = "r:reserved",
         [KPF_MLOCKED]           = "m:mlocked",
@@ -152,9 +159,6 @@ static unsigned long	opt_size[MAX_ADDR_RANGES];
 static int              nr_vmas;
 static unsigned long    pg_start[MAX_VMAS];
 static unsigned long    pg_end[MAX_VMAS];
-static unsigned long    voffset;
-
-static int              pagemap_fd;
 
 #define MAX_BIT_FILTERS 64
 static int              nr_bit_filters;
@@ -163,9 +167,16 @@ static uint64_t		opt_bits[MAX_BIT_FILTERS];
 
 static int              page_size;
 
-#define PAGES_BATCH     (64 << 10)      /* 64k pages */
+static int              pagemap_fd;
 static int              kpageflags_fd;
 
+static int              opt_hwpoison;
+static int              opt_unpoison;
+
+static char             *hwpoison_debug_fs = "/debug/hwpoison";
+static int              hwpoison_inject_fd;
+static int              hwpoison_forget_fd;
+
 #define HASH_SHIFT      13
 #define HASH_SIZE       (1 << HASH_SHIFT)
 #define HASH_MASK       (HASH_SIZE - 1)
@@ -207,6 +218,74 @@ static void fatal(const char *x, ...)
         exit(EXIT_FAILURE);
 }
 
+int checked_open(const char *pathname, int flags)
+{
+        int fd = open(pathname, flags);
+
+        if (fd < 0) {
+                perror(pathname);
+                exit(EXIT_FAILURE);
+        }
+
+        return fd;
+}
+
+/*
+ * pagemap/kpageflags routines
+ */
+
+static unsigned long do_u64_read(int fd, char *name,
+                                 uint64_t *buf,
+                                 unsigned long index,
+                                 unsigned long count)
+{
+        long bytes;
+
+        if (index > ULONG_MAX / 8)
+                fatal("index overflow: %lu\n", index);
+
+        if (lseek(fd, index * 8, SEEK_SET) < 0) {
+                perror(name);
+                exit(EXIT_FAILURE);
+        }
+
+        bytes = read(fd, buf, count * 8);
+        if (bytes < 0) {
+                perror(name);
+                exit(EXIT_FAILURE);
+        }
+        if (bytes % 8)
+                fatal("partial read: %lu bytes\n", bytes);
+
+        return bytes / 8;
+}
+
+static unsigned long kpageflags_read(uint64_t *buf,
+                                     unsigned long index,
+                                     unsigned long pages)
+{
+        return do_u64_read(kpageflags_fd, PROC_KPAGEFLAGS, buf, index, pages);
+}
+
+static unsigned long pagemap_read(uint64_t *buf,
+                                  unsigned long index,
+                                  unsigned long pages)
+{
+        return do_u64_read(pagemap_fd, "/proc/pid/pagemap", buf, index, pages);
+}
+
+static unsigned long pagemap_pfn(uint64_t val)
+{
+        unsigned long pfn;
+
+        if (val & PM_PRESENT)
+                pfn = PM_PFRAME(val);
+        else
+                pfn = 0;
+
+        return pfn;
+}
+
 
 /*
  * page flag names
@@ -255,7 +334,8 @@ static char *page_flag_longname(uint64_t flags)
  * page list and summary
  */
 
-static void show_page_range(unsigned long offset, uint64_t flags)
+static void show_page_range(unsigned long voffset,
+                            unsigned long offset, uint64_t flags)
 {
         static uint64_t      flags0;
         static unsigned long voff;
@@ -281,7 +361,8 @@ static void show_page_range(unsigned long offset, uint64_t flags)
         count  = 1;
 }
 
-static void show_page(unsigned long offset, uint64_t flags)
+static void show_page(unsigned long voffset,
+                      unsigned long offset, uint64_t flags)
 {
         if (opt_pid)
                 printf("%lx\t", voffset);
@@ -362,6 +443,62 @@ static uint64_t well_known_flags(uint64_t flags)
         return flags;
 }
 
+static uint64_t kpageflags_flags(uint64_t flags)
+{
+        flags = expand_overloaded_flags(flags);
+
+        if (!opt_raw)
+                flags = well_known_flags(flags);
+
+        return flags;
+}
+
+/*
+ * page actions
+ */
+
+static void prepare_hwpoison_fd(void)
+{
+        char buf[100];
+
+        if (opt_hwpoison && !hwpoison_inject_fd) {
+                sprintf(buf, "%s/corrupt-pfn", hwpoison_debug_fs);
+                hwpoison_inject_fd = checked_open(buf, O_WRONLY);
+        }
+
+        if (opt_unpoison && !hwpoison_forget_fd) {
+                sprintf(buf, "%s/renew-pfn", hwpoison_debug_fs);
+                hwpoison_forget_fd = checked_open(buf, O_WRONLY);
+        }
+}
+
+static int hwpoison_page(unsigned long offset)
+{
+        char buf[100];
+        int len;
+
+        len = sprintf(buf, "0x%lx\n", offset);
+        len = write(hwpoison_inject_fd, buf, len);
+        if (len < 0) {
+                perror("hwpoison inject");
+                return len;
+        }
+        return 0;
+}
+
+static int unpoison_page(unsigned long offset)
+{
+        char buf[100];
+        int len;
+
+        len = sprintf(buf, "0x%lx\n", offset);
+        len = write(hwpoison_forget_fd, buf, len);
+        if (len < 0) {
+                perror("hwpoison forget");
+                return len;
+        }
+        return 0;
+}
 
 /*
  * page frame walker
@@ -394,104 +531,83 @@ static int hash_slot(uint64_t flags)
         exit(EXIT_FAILURE);
 }
 
-static void add_page(unsigned long offset, uint64_t flags)
+static void add_page(unsigned long voffset,
+                     unsigned long offset, uint64_t flags)
 {
-        flags = expand_overloaded_flags(flags);
-
-        if (!opt_raw)
-                flags = well_known_flags(flags);
+        flags = kpageflags_flags(flags);
 
         if (!bit_mask_ok(flags))
                 return;
 
+        if (opt_hwpoison)
+                hwpoison_page(offset);
+        if (opt_unpoison)
+                unpoison_page(offset);
+
         if (opt_list == 1)
-                show_page_range(offset, flags);
+                show_page_range(voffset, offset, flags);
         else if (opt_list == 2)
-                show_page(offset, flags);
+                show_page(voffset, offset, flags);
 
         nr_pages[hash_slot(flags)]++;
         total_pages++;
 }
 
-static void walk_pfn(unsigned long index, unsigned long count)
+#define KPAGEFLAGS_BATCH        (64 << 10)      /* 64k pages */
+static void walk_pfn(unsigned long voffset,
+                     unsigned long index,
+                     unsigned long count)
 {
+        uint64_t buf[KPAGEFLAGS_BATCH];
         unsigned long batch;
-        unsigned long n;
+        unsigned long pages;
         unsigned long i;
 
-        if (index > ULONG_MAX / KPF_BYTES)
-                fatal("index overflow: %lu\n", index);
-
-        lseek(kpageflags_fd, index * KPF_BYTES, SEEK_SET);
-
         while (count) {
-                uint64_t kpageflags_buf[KPF_BYTES * PAGES_BATCH];
-
-                batch = min_t(unsigned long, count, PAGES_BATCH);
-                n = read(kpageflags_fd, kpageflags_buf, batch * KPF_BYTES);
-                if (n == 0)
+                batch = min_t(unsigned long, count, KPAGEFLAGS_BATCH);
+                pages = kpageflags_read(buf, index, batch);
+                if (pages == 0)
                         break;
-                if (n < 0) {
-                        perror(PROC_KPAGEFLAGS);
-                        exit(EXIT_FAILURE);
-                }
 
-                if (n % KPF_BYTES != 0)
-                        fatal("partial read: %lu bytes\n", n);
-                n = n / KPF_BYTES;
+                for (i = 0; i < pages; i++)
+                        add_page(voffset + i, index + i, buf[i]);
 
-                for (i = 0; i < n; i++)
-                        add_page(index + i, kpageflags_buf[i]);
-
-                index += batch;
-                count -= batch;
+                index += pages;
+                count -= pages;
         }
 }
 
-
-#define PAGEMAP_BATCH   4096
-static unsigned long task_pfn(unsigned long pgoff)
+#define PAGEMAP_BATCH   (64 << 10)
+static void walk_vma(unsigned long index, unsigned long count)
 {
-        static uint64_t buf[PAGEMAP_BATCH];
-        static unsigned long start;
-        static long count;
-        uint64_t pfn;
+        uint64_t buf[PAGEMAP_BATCH];
+        unsigned long batch;
+        unsigned long pages;
+        unsigned long pfn;
+        unsigned long i;
 
-        if (pgoff < start || pgoff >= start + count) {
-                if (lseek64(pagemap_fd,
-                            (uint64_t)pgoff * PM_ENTRY_BYTES,
-                            SEEK_SET) < 0) {
-                        perror("pagemap seek");
-                        exit(EXIT_FAILURE);
-                }
-                count = read(pagemap_fd, buf, sizeof(buf));
-                if (count == 0)
-                        return 0;
-                if (count < 0) {
-                        perror("pagemap read");
-                        exit(EXIT_FAILURE);
-                }
-                if (count % PM_ENTRY_BYTES) {
-                        fatal("pagemap read not aligned.\n");
-                        exit(EXIT_FAILURE);
-                }
-                count /= PM_ENTRY_BYTES;
-                start = pgoff;
-        }
+        while (count) {
+                batch = min_t(unsigned long, count, PAGEMAP_BATCH);
+                pages = pagemap_read(buf, index, batch);
+                if (pages == 0)
+                        break;
 
-        pfn = buf[pgoff - start];
-        if (pfn & PM_PRESENT)
-                pfn = PM_PFRAME(pfn);
-        else
-                pfn = 0;
+                for (i = 0; i < pages; i++) {
+                        pfn = pagemap_pfn(buf[i]);
+                        if (pfn)
+                                walk_pfn(index + i, pfn, 1);
+                }
 
-        return pfn;
+                index += pages;
+                count -= pages;
+        }
 }
 
 static void walk_task(unsigned long index, unsigned long count)
 {
-        int i = 0;
         const unsigned long end = index + count;
+        unsigned long start;
+        int i = 0;
 
         while (index < end) {
 
@@ -501,15 +617,11 @@ static void walk_task(unsigned long index, unsigned long count)
                 if (pg_start[i] >= end)
                         return;
 
-                voffset = max_t(unsigned long, pg_start[i], index);
-                index   = min_t(unsigned long, pg_end[i], end);
+                start = max_t(unsigned long, pg_start[i], index);
+                index = min_t(unsigned long, pg_end[i], end);
 
-                assert(voffset < index);
-                for (; voffset < index; voffset++) {
-                        unsigned long pfn = task_pfn(voffset);
-                        if (pfn)
-                                walk_pfn(pfn, 1);
-                }
+                assert(start < index);
+                walk_vma(start, index - start);
         }
 }
 
@@ -527,18 +639,14 @@ static void walk_addr_ranges(void)
 {
         int i;
 
-        kpageflags_fd = open(PROC_KPAGEFLAGS, O_RDONLY);
-        if (kpageflags_fd < 0) {
-                perror(PROC_KPAGEFLAGS);
-                exit(EXIT_FAILURE);
-        }
+        kpageflags_fd = checked_open(PROC_KPAGEFLAGS, O_RDONLY);
 
         if (!nr_addr_ranges)
                 add_addr_range(0, ULONG_MAX);
 
         for (i = 0; i < nr_addr_ranges; i++)
                 if (!opt_pid)
-                        walk_pfn(opt_offset[i], opt_size[i]);
+                        walk_pfn(0, opt_offset[i], opt_size[i]);
                 else
                         walk_task(opt_offset[i], opt_size[i]);
 
@@ -575,6 +683,8 @@ static void usage(void)
 "            -l|--list                 Show page details in ranges\n"
 "            -L|--list-each            Show page details one by one\n"
 "            -N|--no-summary           Don't show summay info\n"
+"            -X|--hwpoison             hwpoison pages\n"
+"            -x|--unpoison             unpoison pages\n"
 "            -h|--help                 Show this usage message\n"
 "addr-spec:\n"
 "            N                         one page at offset N (unit: pages)\n"
@@ -624,11 +734,7 @@ static void parse_pid(const char *str)
         opt_pid = parse_number(str);
 
         sprintf(buf, "/proc/%d/pagemap", opt_pid);
-        pagemap_fd = open(buf, O_RDONLY);
-        if (pagemap_fd < 0) {
-                perror(buf);
-                exit(EXIT_FAILURE);
-        }
+        pagemap_fd = checked_open(buf, O_RDONLY);
 
         sprintf(buf, "/proc/%d/maps", opt_pid);
         file = fopen(buf, "r");
@@ -788,6 +894,8 @@ static struct option opts[] = {
         { "list"      , 0, NULL, 'l' },
         { "list-each" , 0, NULL, 'L' },
         { "no-summary", 0, NULL, 'N' },
+        { "hwpoison"  , 0, NULL, 'X' },
+        { "unpoison"  , 0, NULL, 'x' },
         { "help"      , 0, NULL, 'h' },
         { NULL        , 0, NULL, 0 }
 };
@@ -799,7 +907,7 @@ int main(int argc, char *argv[])
         page_size = getpagesize();
 
         while ((c = getopt_long(argc, argv,
-                                "rp:f:a:b:lLNh", opts, NULL)) != -1) {
+                                "rp:f:a:b:lLNXxh", opts, NULL)) != -1) {
                 switch (c) {
                 case 'r':
                         opt_raw = 1;
@@ -825,6 +933,14 @@ int main(int argc, char *argv[])
                 case 'N':
                         opt_no_summary = 1;
                         break;
+                case 'X':
+                        opt_hwpoison = 1;
+                        prepare_hwpoison_fd();
+                        break;
+                case 'x':
+                        opt_unpoison = 1;
+                        prepare_hwpoison_fd();
+                        break;
                 case 'h':
                         usage();
                         exit(0);
@@ -844,7 +960,7 @@ int main(int argc, char *argv[])
         walk_addr_ranges();
 
         if (opt_list == 1)
-                show_page_range(0, 0);  /* drain the buffer */
+                show_page_range(0, 0, 0);  /* drain the buffer */
 
         if (opt_no_summary)
                 return 0;
diff --git a/Documentation/vm/pagemap.txt b/Documentation/vm/pagemap.txt
index 600a304a828c..df09b9650a81 100644
--- a/Documentation/vm/pagemap.txt
+++ b/Documentation/vm/pagemap.txt
@@ -57,7 +57,9 @@ There are three components to pagemap:
     16. COMPOUND_TAIL
     16. HUGE
     18. UNEVICTABLE
+    19. HWPOISON
     20. NOPAGE
+    21. KSM
 
 Short descriptions to the page flags:
 
@@ -86,9 +88,15 @@ Short descriptions to the page flags:
 17. HUGE
     this is an integral part of a HugeTLB page
 
+19. HWPOISON
+    hardware detected memory corruption on this page: don't touch the data!
+
 20. NOPAGE
     no page frame exists at the requested address
 
+21. KSM
+    identical memory pages dynamically shared between one or more processes
+
     [IO related page flags]
  1. ERROR     IO error occurred
  3. UPTODATE  page has up-to-date data
diff --git a/MAINTAINERS b/MAINTAINERS
index 09a2028bab7f..e1da925b38c8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3643,6 +3643,13 @@ F:	Documentation/blockdev/nbd.txt
 F:      drivers/block/nbd.c
 F:      include/linux/nbd.h
 
+NETWORK DROP MONITOR
+M:      Neil Horman <nhorman@tuxdriver.com>
+L:      netdev@vger.kernel.org
+S:      Maintained
+W:      https://fedorahosted.org/dropwatch/
+F:      net/core/drop_monitor.c
+
 NETWORKING [GENERAL]
 M:      "David S. Miller" <davem@davemloft.net>
 L:      netdev@vger.kernel.org
@@ -3973,6 +3980,7 @@ F:	drivers/block/paride/
 PARISC ARCHITECTURE
 M:      Kyle McMartin <kyle@mcmartin.ca>
 M:      Helge Deller <deller@gmx.de>
+M:      "James E.J. Bottomley" <jejb@parisc-linux.org>
 L:      linux-parisc@vger.kernel.org
 W:      http://www.parisc-linux.org/
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/kyle/parisc-2.6.git
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index fafcd32e6907..489556eecbd1 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -338,6 +338,13 @@ static struct omap_clk omap34xx_clks[] = {
  */
 #define SDRC_MPURATE_LOOPS              96
 
+/*
+ * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
+ * that are sourced by DPLL5, and both of these require this clock
+ * to be at 120 MHz for proper operation.
+ */
+#define DPLL5_FREQ_FOR_USBHOST          120000000
+
 /**
  * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
  * @clk: struct clk * being enabled
@@ -1056,6 +1063,28 @@ void omap2_clk_prepare_for_reboot(void)
 #endif
 }
 
+static void omap3_clk_lock_dpll5(void)
+{
+        struct clk *dpll5_clk;
+        struct clk *dpll5_m2_clk;
+
+        dpll5_clk = clk_get(NULL, "dpll5_ck");
+        clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
+        clk_enable(dpll5_clk);
+
+        /* Enable autoidle to allow it to enter low power bypass */
+        omap3_dpll_allow_idle(dpll5_clk);
+
+        /* Program dpll5_m2_clk divider for no division */
+        dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
+        clk_enable(dpll5_m2_clk);
+        clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
+
+        clk_disable(dpll5_m2_clk);
+        clk_disable(dpll5_clk);
+        return;
+}
+
 /* REVISIT: Move this init stuff out into clock.c */
 
 /*
@@ -1148,6 +1177,12 @@ int __init omap2_clk_init(void)
          */
         clk_enable_init_clocks();
 
+        /*
+         * Lock DPLL5 and put it in autoidle.
+         */
+        if (omap_rev() >= OMAP3430_REV_ES2_0)
+                omap3_clk_lock_dpll5();
+
         /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
         /* REVISIT: not yet ready for 343x */
 #if 0
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 1b4c1600f8d8..2fc4d6abbd0a 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -541,7 +541,7 @@ static int __init pm_dbg_init(void)
                 printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
                 return -ENODEV;
         }
-                
+
         d = debugfs_create_dir("pm_debug", NULL);
         if (IS_ERR(d))
                 return PTR_ERR(d);
@@ -551,7 +551,7 @@ static int __init pm_dbg_init(void)
         (void) debugfs_create_file("time", S_IRUGO,
                 d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
 
-        pwrdm_for_each(pwrdms_setup, (void *)d);
+        pwrdm_for_each_nolock(pwrdms_setup, (void *)d);
 
         pm_dbg_dir = debugfs_create_dir("registers", d);
         if (IS_ERR(pm_dbg_dir))
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 0ff5a6c53aa0..378c2f618358 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -51,97 +51,112 @@ static void (*_omap_sram_idle)(u32 *addr, int save_state);
 
 static struct powerdomain *mpu_pwrdm;
 
-/* PRCM Interrupt Handler for wakeups */
-static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
+/*
+ * PRCM Interrupt Handler Helper Function
+ *
+ * The purpose of this function is to clear any wake-up events latched
+ * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
+ * may occur whilst attempting to clear a PM_WKST_x register and thus
+ * set another bit in this register. A while loop is used to ensure
+ * that any peripheral wake-up events occurring while attempting to
+ * clear the PM_WKST_x are detected and cleared.
+ */
+static int prcm_clear_mod_irqs(s16 module, u8 regs)
 {
-        u32 wkst, irqstatus_mpu;
-        u32 fclk, iclk;
-
-        /* WKUP */
-        wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
+        u32 wkst, fclk, iclk, clken;
+        u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
+        u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
+        u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
+        u16 grpsel_off = (regs == 3) ?
+                OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
+        int c = 0;
+
+        wkst = prm_read_mod_reg(module, wkst_off);
+        wkst &= prm_read_mod_reg(module, grpsel_off);
         if (wkst) {
-                iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
-                fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
-                cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
-                cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
-                prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
-                while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
-                        cpu_relax();
-                cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
-                cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
+                iclk = cm_read_mod_reg(module, iclk_off);
+                fclk = cm_read_mod_reg(module, fclk_off);
+                while (wkst) {
+                        clken = wkst;
+                        cm_set_mod_reg_bits(clken, module, iclk_off);
+                        /*
+                         * For USBHOST, we don't know whether HOST1 or
+                         * HOST2 woke us up, so enable both f-clocks
+                         */
+                        if (module == OMAP3430ES2_USBHOST_MOD)
+                                clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
+                        cm_set_mod_reg_bits(clken, module, fclk_off);
+                        prm_write_mod_reg(wkst, module, wkst_off);
+                        wkst = prm_read_mod_reg(module, wkst_off);
+                        c++;
+                }
+                cm_write_mod_reg(iclk, module, iclk_off);
+                cm_write_mod_reg(fclk, module, fclk_off);
         }
 
-        /* CORE */
-        wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
-        if (wkst) {
-                iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
-                fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-                cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
-                cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
-                prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
-                while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
-                        cpu_relax();
-                cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
-                cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
-        }
-        wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
-        if (wkst) {
-                iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
-                fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
-                cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
-                cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
-                prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
-                while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
-                        cpu_relax();
-                cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
-                cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
-        }
+        return c;
+}
 
-        /* PER */
-        wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
-        if (wkst) {
-                iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
-                fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
-                cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
-                cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
-                prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
-                while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
-                        cpu_relax();
-                cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
-                cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
-        }
+static int _prcm_int_handle_wakeup(void)
+{
+        int c;
 
+        c = prcm_clear_mod_irqs(WKUP_MOD, 1);
+        c += prcm_clear_mod_irqs(CORE_MOD, 1);
+        c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
         if (omap_rev() > OMAP3430_REV_ES1_0) {
-                /* USBHOST */
-                wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
-                if (wkst) {
-                        iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
-                                               CM_ICLKEN);
-                        fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
-                                               CM_FCLKEN);
-                        cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
-                                            CM_ICLKEN);
-                        cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
-                                            CM_FCLKEN);
-                        prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
-                                          PM_WKST);
-                        while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
-                                                PM_WKST))
-                                cpu_relax();
-                        cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
-                                         CM_ICLKEN);
-                        cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
-                                         CM_FCLKEN);
-                }
+                c += prcm_clear_mod_irqs(CORE_MOD, 3);
+                c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
         }
 
-        irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
-                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-        prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
-                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        return c;
+}
+
+/*
+ * PRCM Interrupt Handler
+ *
+ * The PRM_IRQSTATUS_MPU register indicates if there are any pending
+ * interrupts from the PRCM for the MPU. These bits must be cleared in
+ * order to clear the PRCM interrupt. The PRCM interrupt handler is
+ * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
+ * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
+ * register indicates that a wake-up event is pending for the MPU and
+ * this bit can only be cleared if the all the wake-up events latched
+ * in the various PM_WKST_x registers have been cleared. The interrupt
+ * handler is implemented using a do-while loop so that if a wake-up
+ * event occurred during the processing of the prcm interrupt handler
+ * (setting a bit in the corresponding PM_WKST_x register and thus
+ * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
+ * this would be handled.
+ */
+static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
+{
+        u32 irqstatus_mpu;
+        int c = 0;
+
+        do {
+                irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
+                                        OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+
+                if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
+                        c = _prcm_int_handle_wakeup();
+
+                        /*
+                         * Is the MPU PRCM interrupt handler racing with the
+                         * IVA2 PRCM interrupt handler ?
+                         */
+                        WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
+                             "but no wakeup sources are marked\n");
+                } else {
+                        /* XXX we need to expand our PRCM interrupt handler */
+                        WARN(1, "prcm: WARNING: PRCM interrupt received, but "
+                             "no code to handle it (%08x)\n", irqstatus_mpu);
+                }
+
+                prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
+                                        OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
-        while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))
-                cpu_relax();
+        } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
 
         return IRQ_HANDLED;
 }
@@ -624,6 +639,16 @@ static void __init prcm_setup_regs(void)
         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 
+        /* Enable GPIO wakeups in PER */
+        prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
+                          OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
+                          OMAP3430_EN_GPIO6, OMAP3430_PER_MOD, PM_WKEN);
+        /* and allow them to wake up MPU */
+        prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
+                          OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
+                          OMAP3430_GRPSEL_GPIO6,
+                          OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
+
         /* Don't attach IVA interrupts */
         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 2594cbff3947..f00289abd30f 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -273,35 +273,50 @@ struct powerdomain *pwrdm_lookup(const char *name)
 }
 
 /**
- * pwrdm_for_each - call function on each registered clockdomain
+ * pwrdm_for_each_nolock - call function on each registered clockdomain
  * @fn: callback function *
  *
  * Call the supplied function for each registered powerdomain.  The
  * callback function can return anything but 0 to bail out early from
- * the iterator.  The callback function is called with the pwrdm_rwlock
- * held for reading, so no powerdomain structure manipulation
- * functions should be called from the callback, although hardware
- * powerdomain control functions are fine.  Returns the last return
- * value of the callback function, which should be 0 for success or
- * anything else to indicate failure; or -EINVAL if the function
- * pointer is null.
+ * the iterator.  Returns the last return value of the callback function, which
+ * should be 0 for success or anything else to indicate failure; or -EINVAL if
+ * the function pointer is null.
  */
-int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
-                        void *user)
+int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
+                                void *user)
 {
         struct powerdomain *temp_pwrdm;
-        unsigned long flags;
         int ret = 0;
 
         if (!fn)
                 return -EINVAL;
 
-        read_lock_irqsave(&pwrdm_rwlock, flags);
         list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
                 ret = (*fn)(temp_pwrdm, user);
                 if (ret)
                         break;
         }
+
+        return ret;
+}
+
+/**
+ * pwrdm_for_each - call function on each registered clockdomain
+ * @fn: callback function *
+ *
+ * This function is the same as 'pwrdm_for_each_nolock()', but keeps the
+ * &pwrdm_rwlock locked for reading, so no powerdomain structure manipulation
+ * functions should be called from the callback, although hardware powerdomain
+ * control functions are fine.
+ */
+int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
+                        void *user)
+{
+        unsigned long flags;
+        int ret;
+
+        read_lock_irqsave(&pwrdm_rwlock, flags);
+        ret = pwrdm_for_each_nolock(fn, user);
         read_unlock_irqrestore(&pwrdm_rwlock, flags);
 
         return ret;
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index 11e73d9e8928..f129efb3075e 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -303,32 +303,21 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define cpu_is_omap2430()               0
 #define cpu_is_omap3430()               0
 
-#if defined(MULTI_OMAP1)
-# if defined(CONFIG_ARCH_OMAP730)
-#  undef  cpu_is_omap730
-#  define cpu_is_omap730()              is_omap730()
-# endif
-# if defined(CONFIG_ARCH_OMAP850)
-#  undef  cpu_is_omap850
-#  define cpu_is_omap850()              is_omap850()
-# endif
-#else
-# if defined(CONFIG_ARCH_OMAP730)
-#  undef  cpu_is_omap730
-#  define cpu_is_omap730()              1
-# endif
-#endif
-#else
-# if defined(CONFIG_ARCH_OMAP850)
-#  undef  cpu_is_omap850
-#  define cpu_is_omap850()              1
-# endif
-#endif
-
 /*
  * Whether we have MULTI_OMAP1 or not, we still need to distinguish
- * between 330 vs. 1510 and 1611B/5912 vs. 1710.
+ * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
  */
+
+#if defined(CONFIG_ARCH_OMAP730)
+# undef  cpu_is_omap730
+# define cpu_is_omap730()               is_omap730()
+#endif
+
+#if defined(CONFIG_ARCH_OMAP850)
+# undef  cpu_is_omap850
+# define cpu_is_omap850()               is_omap850()
+#endif
+
 #if defined(CONFIG_ARCH_OMAP15XX)
 # undef  cpu_is_omap310
 # undef  cpu_is_omap1510
@@ -433,3 +422,5 @@ IS_OMAP_TYPE(3430, 0x3430)
 
 int omap_chip_is(struct omap_chip_id oci);
 void omap2_check_revision(void);
+
+#endif
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h
index 6271d8556a40..fa6461423bd0 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -135,6 +135,8 @@ struct powerdomain *pwrdm_lookup(const char *name);
 
 int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
                         void *user);
+int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
+                        void *user);
 
 int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
 int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index 57f7122a0919..dc3fac3dd0ea 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -47,7 +47,7 @@
  *      'va':   mpu virtual address
  *
  *      'c':    contiguous memory area
- *      'd':    dicontiguous memory area
+ *      'd':    discontiguous memory area
  *      'a':    anonymous memory allocation
  *      '()':   optional feature
  *
@@ -363,8 +363,9 @@ void *da_to_va(struct iommu *obj, u32 da)
                 goto out;
         }
         va = area->va;
-        mutex_unlock(&obj->mmap_lock);
 out:
+        mutex_unlock(&obj->mmap_lock);
+
         return va;
 }
 EXPORT_SYMBOL_GPL(da_to_va);
@@ -398,7 +399,7 @@ static inline void sgtable_drain_vmalloc(struct sg_table *sgt)
 {
         /*
          * Actually this is not necessary at all, just exists for
-         * consistency of the code readibility.
+         * consistency of the code readability.
          */
         BUG_ON(!sgt);
 }
@@ -434,7 +435,7 @@ static inline void sgtable_drain_kmalloc(struct sg_table *sgt)
 {
         /*
          * Actually this is not necessary at all, just exists for
-         * consistency of the code readibility
+         * consistency of the code readability
          */
         BUG_ON(!sgt);
 }
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 925f64711c37..75d1f26e5b17 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -270,7 +270,8 @@ void * omap_sram_push(void * start, unsigned long size)
         omap_sram_ceil -= size;
         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
         memcpy((void *)omap_sram_ceil, start, size);
-        flush_icache_range((unsigned long)start, (unsigned long)(start + size));
+        flush_icache_range((unsigned long)omap_sram_ceil,
+                (unsigned long)(omap_sram_ceil + size));
 
         return (void *)omap_sram_ceil;
 }
diff --git a/arch/m68knommu/kernel/asm-offsets.c b/arch/m68knommu/kernel/asm-offsets.c
index 594ee0e657fe..9a8876f715d8 100644
--- a/arch/m68knommu/kernel/asm-offsets.c
+++ b/arch/m68knommu/kernel/asm-offsets.c
@@ -45,25 +45,25 @@ int main(void)
         DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fpstate));
 
         /* offsets into the pt_regs */
-        DEFINE(PT_D0, offsetof(struct pt_regs, d0));
-        DEFINE(PT_ORIG_D0, offsetof(struct pt_regs, orig_d0));
-        DEFINE(PT_D1, offsetof(struct pt_regs, d1));
-        DEFINE(PT_D2, offsetof(struct pt_regs, d2));
-        DEFINE(PT_D3, offsetof(struct pt_regs, d3));
-        DEFINE(PT_D4, offsetof(struct pt_regs, d4));
-        DEFINE(PT_D5, offsetof(struct pt_regs, d5));
-        DEFINE(PT_A0, offsetof(struct pt_regs, a0));
-        DEFINE(PT_A1, offsetof(struct pt_regs, a1));
-        DEFINE(PT_A2, offsetof(struct pt_regs, a2));
-        DEFINE(PT_PC, offsetof(struct pt_regs, pc));
-        DEFINE(PT_SR, offsetof(struct pt_regs, sr));
+        DEFINE(PT_OFF_D0, offsetof(struct pt_regs, d0));
+        DEFINE(PT_OFF_ORIG_D0, offsetof(struct pt_regs, orig_d0));
+        DEFINE(PT_OFF_D1, offsetof(struct pt_regs, d1));
+        DEFINE(PT_OFF_D2, offsetof(struct pt_regs, d2));
+        DEFINE(PT_OFF_D3, offsetof(struct pt_regs, d3));
+        DEFINE(PT_OFF_D4, offsetof(struct pt_regs, d4));
+        DEFINE(PT_OFF_D5, offsetof(struct pt_regs, d5));
+        DEFINE(PT_OFF_A0, offsetof(struct pt_regs, a0));
+        DEFINE(PT_OFF_A1, offsetof(struct pt_regs, a1));
+        DEFINE(PT_OFF_A2, offsetof(struct pt_regs, a2));
+        DEFINE(PT_OFF_PC, offsetof(struct pt_regs, pc));
+        DEFINE(PT_OFF_SR, offsetof(struct pt_regs, sr));
 
 #ifdef CONFIG_COLDFIRE
         /* bitfields are a bit difficult */
-        DEFINE(PT_FORMATVEC, offsetof(struct pt_regs, sr) - 2);
+        DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, sr) - 2);
 #else
         /* bitfields are a bit difficult */
-        DEFINE(PT_VECTOR, offsetof(struct pt_regs, pc) + 4);
+        DEFINE(PT_OFF_VECTOR, offsetof(struct pt_regs, pc) + 4);
 #endif
 
         /* signal defines */
diff --git a/arch/m68knommu/kernel/entry.S b/arch/m68knommu/kernel/entry.S
index f56faa5c9cd9..56043ade3941 100644
--- a/arch/m68knommu/kernel/entry.S
+++ b/arch/m68knommu/kernel/entry.S
@@ -46,7 +46,7 @@
 ENTRY(buserr)
         SAVE_ALL
         moveq   #-1,%d0
-        movel   %d0,%sp@(PT_ORIG_D0)
+        movel   %d0,%sp@(PT_OFF_ORIG_D0)
         movel   %sp,%sp@-               /* stack frame pointer argument */
         jsr     buserr_c
         addql   #4,%sp
@@ -55,7 +55,7 @@ ENTRY(buserr)
 ENTRY(trap)
         SAVE_ALL
         moveq   #-1,%d0
-        movel   %d0,%sp@(PT_ORIG_D0)
+        movel   %d0,%sp@(PT_OFF_ORIG_D0)
         movel   %sp,%sp@-               /* stack frame pointer argument */
         jsr     trap_c
         addql   #4,%sp
@@ -67,7 +67,7 @@ ENTRY(trap)
 ENTRY(dbginterrupt)
         SAVE_ALL
         moveq   #-1,%d0
-        movel   %d0,%sp@(PT_ORIG_D0)
+        movel   %d0,%sp@(PT_OFF_ORIG_D0)
         movel   %sp,%sp@-               /* stack frame pointer argument */
         jsr     dbginterrupt_c
         addql   #4,%sp
diff --git a/arch/m68knommu/mm/init.c b/arch/m68knommu/mm/init.c
index b1703c67a4f1..f3236d0b522d 100644
--- a/arch/m68knommu/mm/init.c
+++ b/arch/m68knommu/mm/init.c
@@ -162,7 +162,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
                 totalram_pages++;
                 pages++;
         }
-        printk (KERN_NOTICE "Freeing initrd memory: %dk freed\n", pages);
+        printk (KERN_NOTICE "Freeing initrd memory: %dk freed\n", pages * (PAGE_SIZE / 1024));
 }
 #endif
 
diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c
index 0f41ba82a3b5..942397984c66 100644
--- a/arch/m68knommu/platform/5206e/config.c
+++ b/arch/m68knommu/platform/5206e/config.c
@@ -17,7 +17,6 @@
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
 #include <asm/mcfdma.h>
-#include <asm/mcfuart.h>
 
 /***************************************************************************/
 
diff --git a/arch/m68knommu/platform/68328/entry.S b/arch/m68knommu/platform/68328/entry.S
index b1aef72f3baf..9d80d2c42866 100644
--- a/arch/m68knommu/platform/68328/entry.S
+++ b/arch/m68knommu/platform/68328/entry.S
@@ -39,17 +39,17 @@
 .globl inthandler7
 
 badsys:
-        movel   #-ENOSYS,%sp@(PT_D0)
+        movel   #-ENOSYS,%sp@(PT_OFF_D0)
         jra     ret_from_exception
 
 do_trace:
-        movel   #-ENOSYS,%sp@(PT_D0)    /* needed for strace*/
+        movel   #-ENOSYS,%sp@(PT_OFF_D0)        /* needed for strace*/
         subql   #4,%sp
         SAVE_SWITCH_STACK
         jbsr    syscall_trace
         RESTORE_SWITCH_STACK
         addql   #4,%sp
-        movel   %sp@(PT_ORIG_D0),%d1
+        movel   %sp@(PT_OFF_ORIG_D0),%d1
         movel   #-ENOSYS,%d0
         cmpl    #NR_syscalls,%d1
         jcc     1f
@@ -57,7 +57,7 @@ do_trace:
         lea     sys_call_table, %a0
         jbsr    %a0@(%d1)
 
-1:      movel   %d0,%sp@(PT_D0)         /* save the return value */
+1:      movel   %d0,%sp@(PT_OFF_D0)             /* save the return value */
         subql   #4,%sp                  /* dummy return address */
         SAVE_SWITCH_STACK
         jbsr    syscall_trace
@@ -75,7 +75,7 @@ ENTRY(system_call)
         jbsr    set_esp0
         addql   #4,%sp
 
-        movel   %sp@(PT_ORIG_D0),%d0
+        movel   %sp@(PT_OFF_ORIG_D0),%d0
 
         movel   %sp,%d1                 /* get thread_info pointer */
         andl    #-THREAD_SIZE,%d1
@@ -88,10 +88,10 @@ ENTRY(system_call)
         lea     sys_call_table,%a0
         movel   %a0@(%d0), %a0
         jbsr    %a0@
-        movel   %d0,%sp@(PT_D0)         /* save the return value*/
+        movel   %d0,%sp@(PT_OFF_D0)             /* save the return value*/
 
 ret_from_exception:
-        btst    #5,%sp@(PT_SR)          /* check if returning to kernel*/
+        btst    #5,%sp@(PT_OFF_SR)              /* check if returning to kernel*/
         jeq     Luser_return            /* if so, skip resched, signals*/
 
 Lkernel_return:
@@ -133,7 +133,7 @@ Lreturn:
  */
 inthandler1:
         SAVE_ALL
-        movew   %sp@(PT_VECTOR), %d0
+        movew   %sp@(PT_OFF_VECTOR), %d0
         and     #0x3ff, %d0
 
         movel   %sp,%sp@-
@@ -144,7 +144,7 @@ inthandler1:
 
 inthandler2:
         SAVE_ALL
-        movew   %sp@(PT_VECTOR), %d0
+        movew   %sp@(PT_OFF_VECTOR), %d0
         and     #0x3ff, %d0
 
         movel   %sp,%sp@-
@@ -155,7 +155,7 @@ inthandler2:
 
 inthandler3:
         SAVE_ALL
-        movew   %sp@(PT_VECTOR), %d0
+        movew   %sp@(PT_OFF_VECTOR), %d0
         and     #0x3ff, %d0
 
         movel   %sp,%sp@-
@@ -166,7 +166,7 @@ inthandler3:
 
 inthandler4:
         SAVE_ALL
-        movew   %sp@(PT_VECTOR), %d0
+        movew   %sp@(PT_OFF_VECTOR), %d0
         and     #0x3ff, %d0
 
         movel   %sp,%sp@-
@@ -177,7 +177,7 @@ inthandler4:
 
 inthandler5:
         SAVE_ALL
-        movew   %sp@(PT_VECTOR), %d0
+        movew   %sp@(PT_OFF_VECTOR), %d0
         and     #0x3ff, %d0
 
         movel   %sp,%sp@-
@@ -188,7 +188,7 @@ inthandler5:
 
 inthandler6:
         SAVE_ALL
-        movew   %sp@(PT_VECTOR), %d0
+        movew   %sp@(PT_OFF_VECTOR), %d0
         and     #0x3ff, %d0
 
         movel   %sp,%sp@-
@@ -199,7 +199,7 @@ inthandler6:
 
 inthandler7:
         SAVE_ALL
-        movew   %sp@(PT_VECTOR), %d0
+        movew   %sp@(PT_OFF_VECTOR), %d0
         and     #0x3ff, %d0
 
         movel   %sp,%sp@-
@@ -210,7 +210,7 @@ inthandler7:
 
 inthandler:
         SAVE_ALL
-        movew   %sp@(PT_VECTOR), %d0
+        movew   %sp@(PT_OFF_VECTOR), %d0
         and     #0x3ff, %d0
 
         movel   %sp,%sp@-
@@ -224,7 +224,7 @@ ret_from_interrupt:
 2:
         RESTORE_ALL
 1:
-        moveb   %sp@(PT_SR), %d0
+        moveb   %sp@(PT_OFF_SR), %d0
         and     #7, %d0
         jhi     2b
 
diff --git a/arch/m68knommu/platform/68360/entry.S b/arch/m68knommu/platform/68360/entry.S
index 55dfefe38642..6d3460a39cac 100644
--- a/arch/m68knommu/platform/68360/entry.S
+++ b/arch/m68knommu/platform/68360/entry.S
@@ -35,17 +35,17 @@
 .globl inthandler
 
 badsys:
-        movel   #-ENOSYS,%sp@(PT_D0)
+        movel   #-ENOSYS,%sp@(PT_OFF_D0)
         jra     ret_from_exception
 
 do_trace:
-        movel   #-ENOSYS,%sp@(PT_D0)    /* needed for strace*/
+        movel   #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/
         subql   #4,%sp
         SAVE_SWITCH_STACK
         jbsr    syscall_trace
         RESTORE_SWITCH_STACK
         addql   #4,%sp
-        movel   %sp@(PT_ORIG_D0),%d1
+        movel   %sp@(PT_OFF_ORIG_D0),%d1
         movel   #-ENOSYS,%d0
         cmpl    #NR_syscalls,%d1
         jcc     1f
@@ -53,7 +53,7 @@ do_trace:
         lea     sys_call_table, %a0
         jbsr    %a0@(%d1)
 
-1:      movel   %d0,%sp@(PT_D0)         /* save the return value */
+1:      movel   %d0,%sp@(PT_OFF_D0)     /* save the return value */
         subql   #4,%sp                  /* dummy return address */
         SAVE_SWITCH_STACK
         jbsr    syscall_trace
@@ -79,10 +79,10 @@ ENTRY(system_call)
         lea     sys_call_table,%a0
         movel   %a0@(%d0), %a0
         jbsr    %a0@
-        movel   %d0,%sp@(PT_D0)         /* save the return value*/
+        movel   %d0,%sp@(PT_OFF_D0)     /* save the return value*/
 
 ret_from_exception:
-        btst    #5,%sp@(PT_SR)          /* check if returning to kernel*/
+        btst    #5,%sp@(PT_OFF_SR)      /* check if returning to kernel*/
         jeq     Luser_return            /* if so, skip resched, signals*/
 
 Lkernel_return:
@@ -124,7 +124,7 @@ Lreturn:
  */
 inthandler:
         SAVE_ALL
-        movew   %sp@(PT_VECTOR), %d0
+        movew   %sp@(PT_OFF_VECTOR), %d0
         and.l   #0x3ff, %d0
         lsr.l   #0x02,  %d0
 
@@ -139,7 +139,7 @@ ret_from_interrupt:
 2:
         RESTORE_ALL
 1:
-        moveb   %sp@(PT_SR), %d0
+        moveb   %sp@(PT_OFF_SR), %d0
         and     #7, %d0
         jhi     2b
         /* check if we need to do software interrupts */
diff --git a/arch/m68knommu/platform/coldfire/entry.S b/arch/m68knommu/platform/coldfire/entry.S
index 3b471c0da24a..dd7d591f70ea 100644
--- a/arch/m68knommu/platform/coldfire/entry.S
+++ b/arch/m68knommu/platform/coldfire/entry.S
@@ -81,11 +81,11 @@ ENTRY(system_call)
 
         movel   %d3,%a0
         jbsr    %a0@
-        movel   %d0,%sp@(PT_D0)         /* save the return value */
+        movel   %d0,%sp@(PT_OFF_D0)     /* save the return value */
         jra     ret_from_exception
 1:
-        movel   #-ENOSYS,%d2            /* strace needs -ENOSYS in PT_D0 */
-        movel   %d2,PT_D0(%sp)          /* on syscall entry */
+        movel   #-ENOSYS,%d2            /* strace needs -ENOSYS in PT_OFF_D0 */
+        movel   %d2,PT_OFF_D0(%sp)      /* on syscall entry */
         subql   #4,%sp
         SAVE_SWITCH_STACK
         jbsr    syscall_trace
@@ -93,7 +93,7 @@ ENTRY(system_call)
         addql   #4,%sp
         movel   %d3,%a0
         jbsr    %a0@
-        movel   %d0,%sp@(PT_D0)         /* save the return value */
+        movel   %d0,%sp@(PT_OFF_D0)             /* save the return value */
         subql   #4,%sp                  /* dummy return address */
         SAVE_SWITCH_STACK
         jbsr    syscall_trace
@@ -104,7 +104,7 @@ ret_from_signal:
 
 ret_from_exception:
         move    #0x2700,%sr             /* disable intrs */
-        btst    #5,%sp@(PT_SR)          /* check if returning to kernel */
+        btst    #5,%sp@(PT_OFF_SR)      /* check if returning to kernel */
         jeq     Luser_return            /* if so, skip resched, signals */
 
 #ifdef CONFIG_PREEMPT
@@ -142,8 +142,8 @@ Luser_return:
 Lreturn:
         move    #0x2700,%sr             /* disable intrs */
         movel   sw_usp,%a0              /* get usp */
-        movel   %sp@(PT_PC),%a0@-       /* copy exception program counter */
-        movel   %sp@(PT_FORMATVEC),%a0@-/* copy exception format/vector/sr */
+        movel   %sp@(PT_OFF_PC),%a0@-   /* copy exception program counter */
+        movel   %sp@(PT_OFF_FORMATVEC),%a0@- /* copy exception format/vector/sr */
         moveml  %sp@,%d1-%d5/%a0-%a2
         lea     %sp@(32),%sp            /* space for 8 regs */
         movel   %sp@+,%d0
@@ -181,9 +181,9 @@ Lsignal_return:
 ENTRY(inthandler)
         SAVE_ALL
         moveq   #-1,%d0
-        movel   %d0,%sp@(PT_ORIG_D0)
+        movel   %d0,%sp@(PT_OFF_ORIG_D0)
 
-        movew   %sp@(PT_FORMATVEC),%d0  /* put exception # in d0 */
+        movew   %sp@(PT_OFF_FORMATVEC),%d0 /* put exception # in d0 */
         andl    #0x03fc,%d0             /* mask out vector only */
 
         movel   %sp,%sp@-               /* push regs arg */
@@ -203,7 +203,7 @@ ENTRY(inthandler)
 ENTRY(fasthandler)
         SAVE_LOCAL
 
-        movew   %sp@(PT_FORMATVEC),%d0
+        movew   %sp@(PT_OFF_FORMATVEC),%d0
         andl    #0x03fc,%d0             /* mask out vector only */
 
         movel   %sp,%sp@-               /* push regs arg */
diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S
index acc1f05d1e2c..e3ecb36dd554 100644
--- a/arch/microblaze/kernel/entry.S
+++ b/arch/microblaze/kernel/entry.S
@@ -592,6 +592,8 @@ C_ENTRY(full_exception_trap):
         nop
         mfs     r7, rfsr;               /* save FSR */
         nop
+        mts     rfsr, r0;       /* Clear sticky fsr */
+        nop
         la      r12, r0, full_exception
         set_vms;
         rtbd    r12, 0;
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index 6b0288ebccd6..2b86c03aa841 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -384,7 +384,7 @@ handle_other_ex: /* Handle Other exceptions here */
         addk    r8, r17, r0; /* Load exception address */
         bralid  r15, full_exception; /* Branch to the handler */
         nop;
-        mts     r0, rfsr;       /* Clear sticky fsr */
+        mts     rfsr, r0;       /* Clear sticky fsr */
         nop
 
         /*
diff --git a/arch/microblaze/kernel/process.c b/arch/microblaze/kernel/process.c
index 4201c743cc9f..c592d475b3d8 100644
--- a/arch/microblaze/kernel/process.c
+++ b/arch/microblaze/kernel/process.c
@@ -235,7 +235,9 @@ void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long usp)
         regs->pc = pc;
         regs->r1 = usp;
         regs->pt_mode = 0;
+#ifdef CONFIG_MMU
         regs->msr |= MSR_UMS;
+#endif
 }
 
 #ifdef CONFIG_MMU
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index f388dc68f605..524d9352f17e 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -18,6 +18,7 @@ config PARISC
         select BUG
         select HAVE_PERF_EVENTS
         select GENERIC_ATOMIC64 if !64BIT
+        select HAVE_ARCH_TRACEHOOK
         help
           The PA-RISC microprocessor is designed by Hewlett-Packard and used
           in many of their workstations & servers (HP9000 700 and 800 series,
diff --git a/arch/parisc/include/asm/fixmap.h b/arch/parisc/include/asm/fixmap.h
index de3fe3a18229..6fec4d4a1a18 100644
--- a/arch/parisc/include/asm/fixmap.h
+++ b/arch/parisc/include/asm/fixmap.h
@@ -21,9 +21,9 @@
 #define KERNEL_MAP_END          (TMPALIAS_MAP_START)
 
 #ifndef __ASSEMBLY__
-extern void *vmalloc_start;
+extern void *parisc_vmalloc_start;
 #define PCXL_DMA_MAP_SIZE       (8*1024*1024)
-#define VMALLOC_START           ((unsigned long)vmalloc_start)
+#define VMALLOC_START           ((unsigned long)parisc_vmalloc_start)
 #define VMALLOC_END             (KERNEL_MAP_END)
 #endif /*__ASSEMBLY__*/
 
diff --git a/arch/parisc/include/asm/hardirq.h b/arch/parisc/include/asm/hardirq.h
index ce93133d5112..0d68184a76cb 100644
--- a/arch/parisc/include/asm/hardirq.h
+++ b/arch/parisc/include/asm/hardirq.h
@@ -1,29 +1,11 @@
 /* hardirq.h: PA-RISC hard IRQ support.
  *
  * Copyright (C) 2001 Matthew Wilcox <matthew@wil.cx>
- *
- * The locking is really quite interesting.  There's a cpu-local
- * count of how many interrupts are being handled, and a global
- * lock.  An interrupt can only be serviced if the global lock
- * is free.  You can't be sure no more interrupts are being
- * serviced until you've acquired the lock and then checked
- * all the per-cpu interrupt counts are all zero.  It's a specialised
- * br_lock, and that's exactly how Sparc does it.  We don't because
- * it's more locking for us.  This way is lock-free in the interrupt path.
  */
 
 #ifndef _PARISC_HARDIRQ_H
 #define _PARISC_HARDIRQ_H
 
-#include <linux/threads.h>
-#include <linux/irq.h>
-
-typedef struct {
-        unsigned long __softirq_pending; /* set_bit is used on this */
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
-
-void ack_bad_irq(unsigned int irq);
+#include <asm-generic/hardirq.h>
 
 #endif /* _PARISC_HARDIRQ_H */
diff --git a/arch/parisc/include/asm/ptrace.h b/arch/parisc/include/asm/ptrace.h
index 302f68dc889c..aead40b16dd8 100644
--- a/arch/parisc/include/asm/ptrace.h
+++ b/arch/parisc/include/asm/ptrace.h
@@ -59,8 +59,11 @@ void user_enable_block_step(struct task_struct *task);
 #define user_mode(regs)                 (((regs)->iaoq[0] & 3) ? 1 : 0)
 #define user_space(regs)                (((regs)->iasq[1] != 0) ? 1 : 0)
 #define instruction_pointer(regs)       ((regs)->iaoq[0] & ~3)
+#define user_stack_pointer(regs)        ((regs)->gr[30])
 unsigned long profile_pc(struct pt_regs *);
 extern void show_regs(struct pt_regs *);
-#endif
+
+
+#endif /* __KERNEL__ */
 
 #endif
diff --git a/arch/parisc/include/asm/syscall.h b/arch/parisc/include/asm/syscall.h
new file mode 100644
index 000000000000..8bdfd2c8c39f
--- /dev/null
+++ b/arch/parisc/include/asm/syscall.h
@@ -0,0 +1,40 @@
+/* syscall.h */
+
+#ifndef _ASM_PARISC_SYSCALL_H_
+#define _ASM_PARISC_SYSCALL_H_
+
+#include <linux/err.h>
+#include <asm/ptrace.h>
+
+static inline long syscall_get_nr(struct task_struct *tsk,
+                                  struct pt_regs *regs)
+{
+        return regs->gr[20];
+}
+
+static inline void syscall_get_arguments(struct task_struct *tsk,
+                                         struct pt_regs *regs, unsigned int i,
+                                         unsigned int n, unsigned long *args)
+{
+        BUG_ON(i);
+
+        switch (n) {
+        case 6:
+                args[5] = regs->gr[21];
+        case 5:
+                args[4] = regs->gr[22];
+        case 4:
+                args[3] = regs->gr[23];
+        case 3:
+                args[2] = regs->gr[24];
+        case 2:
+                args[1] = regs->gr[25];
+        case 1:
+                args[0] = regs->gr[26];
+                break;
+        default:
+                BUG();
+        }
+}
+
+#endif /*_ASM_PARISC_SYSCALL_H_*/
diff --git a/arch/parisc/include/asm/thread_info.h b/arch/parisc/include/asm/thread_info.h
index ac775a76bff7..7ecc1039cfed 100644
--- a/arch/parisc/include/asm/thread_info.h
+++ b/arch/parisc/include/asm/thread_info.h
@@ -32,6 +32,11 @@ struct thread_info {
 #define init_thread_info        (init_thread_union.thread_info)
 #define init_stack              (init_thread_union.stack)
 
+/* how to get the thread information struct from C */
+#define current_thread_info()   ((struct thread_info *)mfctl(30))
+
+#endif /* !__ASSEMBLY */
+
 /* thread information allocation */
 
 #define THREAD_SIZE_ORDER            2
@@ -40,11 +45,6 @@ struct thread_info {
 #define THREAD_SIZE             (PAGE_SIZE << THREAD_SIZE_ORDER)
 #define THREAD_SHIFT            (PAGE_SHIFT + THREAD_SIZE_ORDER)
 
-/* how to get the thread information struct from C */
-#define current_thread_info()   ((struct thread_info *)mfctl(30))
-
-#endif /* !__ASSEMBLY */
-
 #define PREEMPT_ACTIVE_BIT      28
 #define PREEMPT_ACTIVE          (1 << PREEMPT_ACTIVE_BIT)
 
@@ -60,6 +60,8 @@ struct thread_info {
 #define TIF_RESTORE_SIGMASK     6       /* restore saved signal mask */
 #define TIF_FREEZE              7       /* is freezing for suspend */
 #define TIF_NOTIFY_RESUME       8       /* callback before returning to user */
+#define TIF_SINGLESTEP          9       /* single stepping? */
+#define TIF_BLOCKSTEP           10      /* branch stepping? */
 
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
@@ -69,6 +71,8 @@ struct thread_info {
 #define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
 #define _TIF_FREEZE             (1 << TIF_FREEZE)
 #define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
+#define _TIF_SINGLESTEP         (1 << TIF_SINGLESTEP)
+#define _TIF_BLOCKSTEP          (1 << TIF_BLOCKSTEP)
 
 #define _TIF_USER_WORK_MASK     (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | \
                                  _TIF_NEED_RESCHED | _TIF_RESTORE_SIGMASK)
diff --git a/arch/parisc/kernel/asm-offsets.c b/arch/parisc/kernel/asm-offsets.c
index 699cf8ef2118..fcd3c707bf12 100644
--- a/arch/parisc/kernel/asm-offsets.c
+++ b/arch/parisc/kernel/asm-offsets.c
@@ -270,8 +270,8 @@ int main(void)
         DEFINE(DTLB_OFF_COUNT, offsetof(struct pdc_cache_info, dt_off_count));
         DEFINE(DTLB_LOOP, offsetof(struct pdc_cache_info, dt_loop));
         BLANK();
-        DEFINE(PA_BLOCKSTEP_BIT, 31-PT_BLOCKSTEP_BIT);
-        DEFINE(PA_SINGLESTEP_BIT, 31-PT_SINGLESTEP_BIT);
+        DEFINE(TIF_BLOCKSTEP_PA_BIT, 31-TIF_BLOCKSTEP);
+        DEFINE(TIF_SINGLESTEP_PA_BIT, 31-TIF_SINGLESTEP);
         BLANK();
         DEFINE(ASM_PMD_SHIFT, PMD_SHIFT);
         DEFINE(ASM_PGDIR_SHIFT, PGDIR_SHIFT);
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index 8c4712b74dc1..3a44f7f704fa 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -2047,12 +2047,13 @@ syscall_do_signal:
         b,n     syscall_check_sig
 
 syscall_restore:
-        /* Are we being ptraced? */
         LDREG   TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
 
-        ldw     TASK_PTRACE(%r1), %r19
-        bb,<    %r19,31,syscall_restore_rfi
-        nop
+        /* Are we being ptraced? */
+        ldw     TASK_FLAGS(%r1),%r19
+        ldi     (_TIF_SINGLESTEP|_TIF_BLOCKSTEP),%r2
+        and,COND(=)     %r19,%r2,%r0
+        b,n     syscall_restore_rfi
 
         ldo     TASK_PT_FR31(%r1),%r19             /* reload fpregs */
         rest_fp %r19
@@ -2113,16 +2114,16 @@ syscall_restore_rfi:
         ldi     0x0b,%r20                          /* Create new PSW */
         depi    -1,13,1,%r20                       /* C, Q, D, and I bits */
 
-        /* The values of PA_SINGLESTEP_BIT and PA_BLOCKSTEP_BIT are
-         * set in include/linux/ptrace.h and converted to PA bitmap
+        /* The values of SINGLESTEP_BIT and BLOCKSTEP_BIT are
+         * set in thread_info.h and converted to PA bitmap
          * numbers in asm-offsets.c */
 
-        /* if ((%r19.PA_SINGLESTEP_BIT)) { %r20.27=1} */
-        extru,= %r19,PA_SINGLESTEP_BIT,1,%r0
+        /* if ((%r19.SINGLESTEP_BIT)) { %r20.27=1} */
+        extru,= %r19,TIF_SINGLESTEP_PA_BIT,1,%r0
         depi    -1,27,1,%r20                       /* R bit */
 
-        /* if ((%r19.PA_BLOCKSTEP_BIT)) { %r20.7=1} */
-        extru,= %r19,PA_BLOCKSTEP_BIT,1,%r0
+        /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7=1} */
+        extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
         depi    -1,7,1,%r20                        /* T bit */
 
         STREG   %r20,TASK_PT_PSW(%r1)
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c
index 330f536a9324..2e7610cb33d5 100644
--- a/arch/parisc/kernel/irq.c
+++ b/arch/parisc/kernel/irq.c
@@ -423,8 +423,3 @@ void __init init_IRQ(void)
         set_eiem(cpu_eiem);     /* EIEM : enable all external intr */
 
 }
-
-void ack_bad_irq(unsigned int irq)
-{
-        printk(KERN_WARNING "unexpected IRQ %d\n", irq);
-}
diff --git a/arch/parisc/kernel/module.c b/arch/parisc/kernel/module.c
index 61ee0eec4e69..212074653df7 100644
--- a/arch/parisc/kernel/module.c
+++ b/arch/parisc/kernel/module.c
@@ -893,7 +893,7 @@ int module_finalize(const Elf_Ehdr *hdr,
          * ourselves */
         for (i = 1; i < hdr->e_shnum; i++) {
                 if(sechdrs[i].sh_type == SHT_SYMTAB
-                   && (sechdrs[i].sh_type & SHF_ALLOC)) {
+                   && (sechdrs[i].sh_flags & SHF_ALLOC)) {
                         int strindex = sechdrs[i].sh_link;
                         /* FIXME: AWFUL HACK
                          * The cast is to drop the const from
diff --git a/arch/parisc/kernel/ptrace.c b/arch/parisc/kernel/ptrace.c
index 927db3668b6f..c4f49e45129d 100644
--- a/arch/parisc/kernel/ptrace.c
+++ b/arch/parisc/kernel/ptrace.c
@@ -13,6 +13,7 @@
 #include <linux/smp.h>
 #include <linux/errno.h>
 #include <linux/ptrace.h>
+#include <linux/tracehook.h>
 #include <linux/user.h>
 #include <linux/personality.h>
 #include <linux/security.h>
@@ -35,7 +36,8 @@
  */
 void ptrace_disable(struct task_struct *task)
 {
-        task->ptrace &= ~(PT_SINGLESTEP|PT_BLOCKSTEP);
+        clear_tsk_thread_flag(task, TIF_SINGLESTEP);
+        clear_tsk_thread_flag(task, TIF_BLOCKSTEP);
 
         /* make sure the trap bits are not set */
         pa_psw(task)->r = 0;
@@ -55,8 +57,8 @@ void user_disable_single_step(struct task_struct *task)
 
 void user_enable_single_step(struct task_struct *task)
 {
-        task->ptrace &= ~PT_BLOCKSTEP;
-        task->ptrace |= PT_SINGLESTEP;
+        clear_tsk_thread_flag(task, TIF_BLOCKSTEP);
+        set_tsk_thread_flag(task, TIF_SINGLESTEP);
 
         if (pa_psw(task)->n) {
                 struct siginfo si;
@@ -98,8 +100,8 @@ void user_enable_single_step(struct task_struct *task)
 
 void user_enable_block_step(struct task_struct *task)
 {
-        task->ptrace &= ~PT_SINGLESTEP;
-        task->ptrace |= PT_BLOCKSTEP;
+        clear_tsk_thread_flag(task, TIF_SINGLESTEP);
+        set_tsk_thread_flag(task, TIF_BLOCKSTEP);
 
         /* Enable taken branch trap. */
         pa_psw(task)->r = 0;
@@ -263,22 +265,20 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
 }
 #endif
 
+long do_syscall_trace_enter(struct pt_regs *regs)
+{
+        if (test_thread_flag(TIF_SYSCALL_TRACE) &&
+            tracehook_report_syscall_entry(regs))
+                return -1L;
+
+        return regs->gr[20];
+}
 
-void syscall_trace(void)
+void do_syscall_trace_exit(struct pt_regs *regs)
 {
-        if (!test_thread_flag(TIF_SYSCALL_TRACE))
-                return;
-        if (!(current->ptrace & PT_PTRACED))
-                return;
-        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
-                                 ? 0x80 : 0));
-        /*
-         * this isn't the same as continuing with a signal, but it will do
-         * for normal use.  strace only continues with a signal if the
-         * stopping signal is not SIGTRAP.  -brl
-         */
-        if (current->exit_code) {
-                send_sig(current->exit_code, current, 1);
-                current->exit_code = 0;
-        }
+        int stepping = test_thread_flag(TIF_SINGLESTEP) ||
+                test_thread_flag(TIF_BLOCKSTEP);
+
+        if (stepping || test_thread_flag(TIF_SYSCALL_TRACE))
+                tracehook_report_syscall_exit(regs, stepping);
 }
diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c
index 8eb3c63c407a..e8467e4aa8d1 100644
--- a/arch/parisc/kernel/signal.c
+++ b/arch/parisc/kernel/signal.c
@@ -21,6 +21,7 @@
 #include <linux/errno.h>
 #include <linux/wait.h>
 #include <linux/ptrace.h>
+#include <linux/tracehook.h>
 #include <linux/unistd.h>
 #include <linux/stddef.h>
 #include <linux/compat.h>
@@ -34,7 +35,6 @@
 #include <asm/asm-offsets.h>
 
 #ifdef CONFIG_COMPAT
-#include <linux/compat.h>
 #include "signal32.h"
 #endif
 
@@ -468,6 +468,9 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
                 sigaddset(&current->blocked,sig);
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
+
+        tracehook_signal_handler(sig, info, ka, regs, 0);
+
         return 1;
 }
 
diff --git a/arch/parisc/kernel/syscall.S b/arch/parisc/kernel/syscall.S
index 59fc1a43ec3e..f5f96021caa0 100644
--- a/arch/parisc/kernel/syscall.S
+++ b/arch/parisc/kernel/syscall.S
@@ -288,18 +288,23 @@ tracesys:
         STREG   %r18,PT_GR18(%r2)
         /* Finished saving things for the debugger */
 
-        ldil    L%syscall_trace,%r1
+        copy    %r2,%r26
+        ldil    L%do_syscall_trace_enter,%r1
         ldil    L%tracesys_next,%r2
-        be      R%syscall_trace(%sr7,%r1)
+        be      R%do_syscall_trace_enter(%sr7,%r1)
         ldo     R%tracesys_next(%r2),%r2
         
-tracesys_next:  
+tracesys_next:
+        /* do_syscall_trace_enter either returned the syscallno, or -1L,
+         *  so we skip restoring the PT_GR20 below, since we pulled it from
+         *  task->thread.regs.gr[20] above.
+         */
+        copy    %ret0,%r20
         ldil    L%sys_call_table,%r1
         ldo     R%sys_call_table(%r1), %r19
 
         ldo     -THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1      /* get task ptr */
         LDREG   TI_TASK(%r1), %r1
-        LDREG   TASK_PT_GR20(%r1), %r20
         LDREG   TASK_PT_GR26(%r1), %r26         /* Restore the users args */
         LDREG   TASK_PT_GR25(%r1), %r25
         LDREG   TASK_PT_GR24(%r1), %r24
@@ -336,7 +341,8 @@ tracesys_exit:
 #ifdef CONFIG_64BIT
         ldo     -16(%r30),%r29                  /* Reference param save area */
 #endif
-        bl      syscall_trace, %r2
+        ldo     TASK_REGS(%r1),%r26
+        bl      do_syscall_trace_exit,%r2
         STREG   %r28,TASK_PT_GR28(%r1)          /* save return value now */
         ldo     -THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1      /* get task ptr */
         LDREG   TI_TASK(%r1), %r1
@@ -353,12 +359,12 @@ tracesys_exit:
 
 tracesys_sigexit:
         ldo     -THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1      /* get task ptr */
-        LDREG   0(%r1), %r1
+        LDREG   TI_TASK(%r1), %r1
 #ifdef CONFIG_64BIT
         ldo     -16(%r30),%r29                  /* Reference param save area */
 #endif
-        bl      syscall_trace, %r2
-        nop
+        bl      do_syscall_trace_exit,%r2
+        ldo     TASK_REGS(%r1),%r26
 
         ldil    L%syscall_exit_rfi,%r1
         be,n    R%syscall_exit_rfi(%sr7,%r1)
diff --git a/arch/parisc/kernel/vmlinux.lds.S b/arch/parisc/kernel/vmlinux.lds.S
index 775be2791bc2..fda4baa059b5 100644
--- a/arch/parisc/kernel/vmlinux.lds.S
+++ b/arch/parisc/kernel/vmlinux.lds.S
@@ -28,6 +28,7 @@
 #include <asm/cache.h>
 #include <asm/page.h>
 #include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
         
 /* ld script to make hppa Linux kernel */
 #ifndef CONFIG_64BIT
@@ -134,6 +135,15 @@ SECTIONS
         __init_begin = .;
         INIT_TEXT_SECTION(16384)
         INIT_DATA_SECTION(16)
+        /* we have to discard exit text and such at runtime, not link time */
+        .exit.text :
+        {
+                EXIT_TEXT
+        }
+        .exit.data :
+        {
+                EXIT_DATA
+        }
 
         PERCPU(PAGE_SIZE)
         . = ALIGN(PAGE_SIZE);
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index d5aca31fddbb..13b6e3e59b99 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -434,8 +434,8 @@ void mark_rodata_ro(void)
 #define SET_MAP_OFFSET(x) ((void *)(((unsigned long)(x) + VM_MAP_OFFSET) \
                                      & ~(VM_MAP_OFFSET-1)))
 
-void *vmalloc_start __read_mostly;
-EXPORT_SYMBOL(vmalloc_start);
+void *parisc_vmalloc_start __read_mostly;
+EXPORT_SYMBOL(parisc_vmalloc_start);
 
 #ifdef CONFIG_PA11
 unsigned long pcxl_dma_start __read_mostly;
@@ -496,13 +496,14 @@ void __init mem_init(void)
 #ifdef CONFIG_PA11
         if (hppa_dma_ops == &pcxl_dma_ops) {
                 pcxl_dma_start = (unsigned long)SET_MAP_OFFSET(MAP_START);
-                vmalloc_start = SET_MAP_OFFSET(pcxl_dma_start + PCXL_DMA_MAP_SIZE);
+                parisc_vmalloc_start = SET_MAP_OFFSET(pcxl_dma_start
+                                                + PCXL_DMA_MAP_SIZE);
         } else {
                 pcxl_dma_start = 0;
-                vmalloc_start = SET_MAP_OFFSET(MAP_START);
+                parisc_vmalloc_start = SET_MAP_OFFSET(MAP_START);
         }
 #else
-        vmalloc_start = SET_MAP_OFFSET(MAP_START);
+        parisc_vmalloc_start = SET_MAP_OFFSET(MAP_START);
 #endif
 
         printk(KERN_INFO "Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
index ec5eee7c25d8..06cce8285ba0 100644
--- a/arch/s390/kvm/kvm-s390.h
+++ b/arch/s390/kvm/kvm-s390.h
@@ -58,7 +58,7 @@ int kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
 int kvm_s390_inject_program_int(struct kvm_vcpu *vcpu, u16 code);
 int kvm_s390_inject_sigp_stop(struct kvm_vcpu *vcpu, int action);
 
-static inline int kvm_s390_vcpu_get_memsize(struct kvm_vcpu *vcpu)
+static inline long kvm_s390_vcpu_get_memsize(struct kvm_vcpu *vcpu)
 {
         return vcpu->arch.sie_block->gmslm
                 - vcpu->arch.sie_block->gmsor
diff --git a/arch/sparc/include/asm/hardirq_32.h b/arch/sparc/include/asm/hardirq_32.h
index 4f63ed8df551..162007643cdc 100644
--- a/arch/sparc/include/asm/hardirq_32.h
+++ b/arch/sparc/include/asm/hardirq_32.h
@@ -7,17 +7,7 @@
 #ifndef __SPARC_HARDIRQ_H
 #define __SPARC_HARDIRQ_H
 
-#include <linux/threads.h>
-#include <linux/spinlock.h>
-#include <linux/cache.h>
-
-/* entry.S is sensitive to the offsets of these fields */ /* XXX P3 Is it? */
-typedef struct {
-        unsigned int __softirq_pending;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
-
 #define HARDIRQ_BITS    8
+#include <asm-generic/hardirq.h>
 
 #endif /* __SPARC_HARDIRQ_H */
diff --git a/arch/sparc/include/asm/irq_32.h b/arch/sparc/include/asm/irq_32.h
index ea43057d4763..cbf4801deaaf 100644
--- a/arch/sparc/include/asm/irq_32.h
+++ b/arch/sparc/include/asm/irq_32.h
@@ -6,10 +6,10 @@
 #ifndef _SPARC_IRQ_H
 #define _SPARC_IRQ_H
 
-#include <linux/interrupt.h>
-
 #define NR_IRQS    16
 
+#include <linux/interrupt.h>
+
 #define irq_canonicalize(irq)   (irq)
 
 extern void __init init_IRQ(void);
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
index 0ff92fa22064..f3cb790fa2ae 100644
--- a/arch/sparc/include/asm/pgtable_64.h
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -41,8 +41,8 @@
 #define LOW_OBP_ADDRESS         _AC(0x00000000f0000000,UL)
 #define HI_OBP_ADDRESS          _AC(0x0000000100000000,UL)
 #define VMALLOC_START           _AC(0x0000000100000000,UL)
-#define VMALLOC_END             _AC(0x0000000200000000,UL)
-#define VMEMMAP_BASE            _AC(0x0000000200000000,UL)
+#define VMALLOC_END             _AC(0x0000010000000000,UL)
+#define VMEMMAP_BASE            _AC(0x0000010000000000,UL)
 
 #define vmemmap                 ((struct page *)VMEMMAP_BASE)
 
diff --git a/arch/sparc/kernel/ktlb.S b/arch/sparc/kernel/ktlb.S
index 3ea6e8cde8c5..1d361477d7d6 100644
--- a/arch/sparc/kernel/ktlb.S
+++ b/arch/sparc/kernel/ktlb.S
@@ -280,8 +280,8 @@ kvmap_dtlb_nonlinear:
 
 #ifdef CONFIG_SPARSEMEM_VMEMMAP
         /* Do not use the TSB for vmemmap.  */
-        mov             (VMEMMAP_BASE >> 24), %g5
-        sllx            %g5, 24, %g5
+        mov             (VMEMMAP_BASE >> 40), %g5
+        sllx            %g5, 40, %g5
         cmp             %g4,%g5
         bgeu,pn         %xcc, kvmap_vmemmap
          nop
@@ -293,8 +293,8 @@ kvmap_dtlb_tsbmiss:
         sethi           %hi(MODULES_VADDR), %g5
         cmp             %g4, %g5
         blu,pn          %xcc, kvmap_dtlb_longpath
-         mov            (VMALLOC_END >> 24), %g5
-        sllx            %g5, 24, %g5
+         mov            (VMALLOC_END >> 40), %g5
+        sllx            %g5, 40, %g5
         cmp             %g4, %g5
         bgeu,pn         %xcc, kvmap_dtlb_longpath
          nop
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 2d6a1b10c81d..04db92743896 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -56,7 +56,8 @@ struct cpu_hw_events {
         struct perf_event       *events[MAX_HWEVENTS];
         unsigned long           used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
         unsigned long           active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
-        int enabled;
+        u64                     pcr;
+        int                     enabled;
 };
 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
 
@@ -68,8 +69,30 @@ struct perf_event_map {
 #define PIC_LOWER       0x02
 };
 
+static unsigned long perf_event_encode(const struct perf_event_map *pmap)
+{
+        return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
+}
+
+static void perf_event_decode(unsigned long val, u16 *enc, u8 *msk)
+{
+        *msk = val & 0xff;
+        *enc = val >> 16;
+}
+
+#define C(x) PERF_COUNT_HW_CACHE_##x
+
+#define CACHE_OP_UNSUPPORTED    0xfffe
+#define CACHE_OP_NONSENSE       0xffff
+
+typedef struct perf_event_map cache_map_t
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX];
+
 struct sparc_pmu {
         const struct perf_event_map     *(*event_map)(int);
+        const cache_map_t               *cache_map;
         int                             max_events;
         int                             upper_shift;
         int                             lower_shift;
@@ -80,21 +103,109 @@ struct sparc_pmu {
         int                             lower_nop;
 };
 
-static const struct perf_event_map ultra3i_perfmon_event_map[] = {
+static const struct perf_event_map ultra3_perfmon_event_map[] = {
         [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
         [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
 };
 
-static const struct perf_event_map *ultra3i_event_map(int event_id)
+static const struct perf_event_map *ultra3_event_map(int event_id)
 {
-        return &ultra3i_perfmon_event_map[event_id];
+        return &ultra3_perfmon_event_map[event_id];
 }
 
-static const struct sparc_pmu ultra3i_pmu = {
-        .event_map      = ultra3i_event_map,
-        .max_events     = ARRAY_SIZE(ultra3i_perfmon_event_map),
+static const cache_map_t ultra3_cache_map = {
+[C(L1D)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
+                [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
+                [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(L1I)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
+                [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(LL)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
+                [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
+                [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(DTLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(ITLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(BPU)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+};
+
+static const struct sparc_pmu ultra3_pmu = {
+        .event_map      = ultra3_event_map,
+        .cache_map      = &ultra3_cache_map,
+        .max_events     = ARRAY_SIZE(ultra3_perfmon_event_map),
         .upper_shift    = 11,
         .lower_shift    = 4,
         .event_mask     = 0x3f,
@@ -102,6 +213,121 @@ static const struct sparc_pmu ultra3i_pmu = {
         .lower_nop      = 0x14,
 };
 
+/* Niagara1 is very limited.  The upper PIC is hard-locked to count
+ * only instructions, so it is free running which creates all kinds of
+ * problems.  Some hardware designs make one wonder if the creator
+ * even looked at how this stuff gets used by software.
+ */
+static const struct perf_event_map niagara1_perfmon_event_map[] = {
+        [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
+        [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
+        [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
+        [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
+};
+
+static const struct perf_event_map *niagara1_event_map(int event_id)
+{
+        return &niagara1_perfmon_event_map[event_id];
+}
+
+static const cache_map_t niagara1_cache_map = {
+[C(L1D)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(L1I)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
+                [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(LL)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(DTLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(ITLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(BPU)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+};
+
+static const struct sparc_pmu niagara1_pmu = {
+        .event_map      = niagara1_event_map,
+        .cache_map      = &niagara1_cache_map,
+        .max_events     = ARRAY_SIZE(niagara1_perfmon_event_map),
+        .upper_shift    = 0,
+        .lower_shift    = 4,
+        .event_mask     = 0x7,
+        .upper_nop      = 0x0,
+        .lower_nop      = 0x0,
+};
+
 static const struct perf_event_map niagara2_perfmon_event_map[] = {
         [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
@@ -116,8 +342,96 @@ static const struct perf_event_map *niagara2_event_map(int event_id)
         return &niagara2_perfmon_event_map[event_id];
 }
 
+static const cache_map_t niagara2_cache_map = {
+[C(L1D)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
+                [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
+                [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(L1I)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
+                [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(LL)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
+                [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
+                [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(DTLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(ITLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+[C(BPU)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
+                [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
+                [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
+        },
+},
+};
+
 static const struct sparc_pmu niagara2_pmu = {
         .event_map      = niagara2_event_map,
+        .cache_map      = &niagara2_cache_map,
         .max_events     = ARRAY_SIZE(niagara2_perfmon_event_map),
         .upper_shift    = 19,
         .lower_shift    = 6,
@@ -151,23 +465,30 @@ static u64 nop_for_index(int idx)
                               sparc_pmu->lower_nop, idx);
 }
 
-static inline void sparc_pmu_enable_event(struct hw_perf_event *hwc,
-                                            int idx)
+static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
 {
         u64 val, mask = mask_for_index(idx);
 
-        val = pcr_ops->read();
-        pcr_ops->write((val & ~mask) | hwc->config);
+        val = cpuc->pcr;
+        val &= ~mask;
+        val |= hwc->config;
+        cpuc->pcr = val;
+
+        pcr_ops->write(cpuc->pcr);
 }
 
-static inline void sparc_pmu_disable_event(struct hw_perf_event *hwc,
-                                             int idx)
+static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
 {
         u64 mask = mask_for_index(idx);
         u64 nop = nop_for_index(idx);
-        u64 val = pcr_ops->read();
+        u64 val;
 
-        pcr_ops->write((val & ~mask) | nop);
+        val = cpuc->pcr;
+        val &= ~mask;
+        val |= nop;
+        cpuc->pcr = val;
+
+        pcr_ops->write(cpuc->pcr);
 }
 
 void hw_perf_enable(void)
@@ -182,7 +503,7 @@ void hw_perf_enable(void)
         cpuc->enabled = 1;
         barrier();
 
-        val = pcr_ops->read();
+        val = cpuc->pcr;
 
         for (i = 0; i < MAX_HWEVENTS; i++) {
                 struct perf_event *cp = cpuc->events[i];
@@ -194,7 +515,9 @@ void hw_perf_enable(void)
                 val |= hwc->config_base;
         }
 
-        pcr_ops->write(val);
+        cpuc->pcr = val;
+
+        pcr_ops->write(cpuc->pcr);
 }
 
 void hw_perf_disable(void)
@@ -207,10 +530,12 @@ void hw_perf_disable(void)
 
         cpuc->enabled = 0;
 
-        val = pcr_ops->read();
+        val = cpuc->pcr;
         val &= ~(PCR_UTRACE | PCR_STRACE |
                  sparc_pmu->hv_bit | sparc_pmu->irq_bit);
-        pcr_ops->write(val);
+        cpuc->pcr = val;
+
+        pcr_ops->write(cpuc->pcr);
 }
 
 static u32 read_pmc(int idx)
@@ -242,7 +567,7 @@ static void write_pmc(int idx, u64 val)
 }
 
 static int sparc_perf_event_set_period(struct perf_event *event,
-                                         struct hw_perf_event *hwc, int idx)
+                                       struct hw_perf_event *hwc, int idx)
 {
         s64 left = atomic64_read(&hwc->period_left);
         s64 period = hwc->sample_period;
@@ -282,19 +607,19 @@ static int sparc_pmu_enable(struct perf_event *event)
         if (test_and_set_bit(idx, cpuc->used_mask))
                 return -EAGAIN;
 
-        sparc_pmu_disable_event(hwc, idx);
+        sparc_pmu_disable_event(cpuc, hwc, idx);
 
         cpuc->events[idx] = event;
         set_bit(idx, cpuc->active_mask);
 
         sparc_perf_event_set_period(event, hwc, idx);
-        sparc_pmu_enable_event(hwc, idx);
+        sparc_pmu_enable_event(cpuc, hwc, idx);
         perf_event_update_userpage(event);
         return 0;
 }
 
 static u64 sparc_perf_event_update(struct perf_event *event,
-                                     struct hw_perf_event *hwc, int idx)
+                                   struct hw_perf_event *hwc, int idx)
 {
         int shift = 64 - 32;
         u64 prev_raw_count, new_raw_count;
@@ -324,7 +649,7 @@ static void sparc_pmu_disable(struct perf_event *event)
         int idx = hwc->idx;
 
         clear_bit(idx, cpuc->active_mask);
-        sparc_pmu_disable_event(hwc, idx);
+        sparc_pmu_disable_event(cpuc, hwc, idx);
 
         barrier();
 
@@ -338,18 +663,29 @@ static void sparc_pmu_disable(struct perf_event *event)
 static void sparc_pmu_read(struct perf_event *event)
 {
         struct hw_perf_event *hwc = &event->hw;
+
         sparc_perf_event_update(event, hwc, hwc->idx);
 }
 
 static void sparc_pmu_unthrottle(struct perf_event *event)
 {
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct hw_perf_event *hwc = &event->hw;
-        sparc_pmu_enable_event(hwc, hwc->idx);
+
+        sparc_pmu_enable_event(cpuc, hwc, hwc->idx);
 }
 
 static atomic_t active_events = ATOMIC_INIT(0);
 static DEFINE_MUTEX(pmc_grab_mutex);
 
+static void perf_stop_nmi_watchdog(void *unused)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+
+        stop_nmi_watchdog(NULL);
+        cpuc->pcr = pcr_ops->read();
+}
+
 void perf_event_grab_pmc(void)
 {
         if (atomic_inc_not_zero(&active_events))
@@ -358,7 +694,7 @@ void perf_event_grab_pmc(void)
         mutex_lock(&pmc_grab_mutex);
         if (atomic_read(&active_events) == 0) {
                 if (atomic_read(&nmi_active) > 0) {
-                        on_each_cpu(stop_nmi_watchdog, NULL, 1);
+                        on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
                         BUG_ON(atomic_read(&nmi_active) != 0);
                 }
                 atomic_inc(&active_events);
@@ -375,30 +711,160 @@ void perf_event_release_pmc(void)
         }
 }
 
+static const struct perf_event_map *sparc_map_cache_event(u64 config)
+{
+        unsigned int cache_type, cache_op, cache_result;
+        const struct perf_event_map *pmap;
+
+        if (!sparc_pmu->cache_map)
+                return ERR_PTR(-ENOENT);
+
+        cache_type = (config >>  0) & 0xff;
+        if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
+                return ERR_PTR(-EINVAL);
+
+        cache_op = (config >>  8) & 0xff;
+        if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
+                return ERR_PTR(-EINVAL);
+
+        cache_result = (config >> 16) & 0xff;
+        if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+                return ERR_PTR(-EINVAL);
+
+        pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);
+
+        if (pmap->encoding == CACHE_OP_UNSUPPORTED)
+                return ERR_PTR(-ENOENT);
+
+        if (pmap->encoding == CACHE_OP_NONSENSE)
+                return ERR_PTR(-EINVAL);
+
+        return pmap;
+}
+
 static void hw_perf_event_destroy(struct perf_event *event)
 {
         perf_event_release_pmc();
 }
 
+/* Make sure all events can be scheduled into the hardware at
+ * the same time.  This is simplified by the fact that we only
+ * need to support 2 simultaneous HW events.
+ */
+static int sparc_check_constraints(unsigned long *events, int n_ev)
+{
+        if (n_ev <= perf_max_events) {
+                u8 msk1, msk2;
+                u16 dummy;
+
+                if (n_ev == 1)
+                        return 0;
+                BUG_ON(n_ev != 2);
+                perf_event_decode(events[0], &dummy, &msk1);
+                perf_event_decode(events[1], &dummy, &msk2);
+
+                /* If both events can go on any counter, OK.  */
+                if (msk1 == (PIC_UPPER | PIC_LOWER) &&
+                    msk2 == (PIC_UPPER | PIC_LOWER))
+                        return 0;
+
+                /* If one event is limited to a specific counter,
+                 * and the other can go on both, OK.
+                 */
+                if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
+                    msk2 == (PIC_UPPER | PIC_LOWER))
+                        return 0;
+                if ((msk2 == PIC_UPPER || msk2 == PIC_LOWER) &&
+                    msk1 == (PIC_UPPER | PIC_LOWER))
+                        return 0;
+
+                /* If the events are fixed to different counters, OK.  */
+                if ((msk1 == PIC_UPPER && msk2 == PIC_LOWER) ||
+                    (msk1 == PIC_LOWER && msk2 == PIC_UPPER))
+                        return 0;
+
+                /* Otherwise, there is a conflict.  */
+        }
+
+        return -1;
+}
+
+static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
+{
+        int eu = 0, ek = 0, eh = 0;
+        struct perf_event *event;
+        int i, n, first;
+
+        n = n_prev + n_new;
+        if (n <= 1)
+                return 0;
+
+        first = 1;
+        for (i = 0; i < n; i++) {
+                event = evts[i];
+                if (first) {
+                        eu = event->attr.exclude_user;
+                        ek = event->attr.exclude_kernel;
+                        eh = event->attr.exclude_hv;
+                        first = 0;
+                } else if (event->attr.exclude_user != eu ||
+                           event->attr.exclude_kernel != ek ||
+                           event->attr.exclude_hv != eh) {
+                        return -EAGAIN;
+                }
+        }
+
+        return 0;
+}
+
+static int collect_events(struct perf_event *group, int max_count,
+                          struct perf_event *evts[], unsigned long *events)
+{
+        struct perf_event *event;
+        int n = 0;
+
+        if (!is_software_event(group)) {
+                if (n >= max_count)
+                        return -1;
+                evts[n] = group;
+                events[n++] = group->hw.event_base;
+        }
+        list_for_each_entry(event, &group->sibling_list, group_entry) {
+                if (!is_software_event(event) &&
+                    event->state != PERF_EVENT_STATE_OFF) {
+                        if (n >= max_count)
+                                return -1;
+                        evts[n] = event;
+                        events[n++] = event->hw.event_base;
+                }
+        }
+        return n;
+}
+
 static int __hw_perf_event_init(struct perf_event *event)
 {
         struct perf_event_attr *attr = &event->attr;
+        struct perf_event *evts[MAX_HWEVENTS];
         struct hw_perf_event *hwc = &event->hw;
+        unsigned long events[MAX_HWEVENTS];
         const struct perf_event_map *pmap;
         u64 enc;
+        int n;
 
         if (atomic_read(&nmi_active) < 0)
                 return -ENODEV;
 
-        if (attr->type != PERF_TYPE_HARDWARE)
+        if (attr->type == PERF_TYPE_HARDWARE) {
+                if (attr->config >= sparc_pmu->max_events)
+                        return -EINVAL;
+                pmap = sparc_pmu->event_map(attr->config);
+        } else if (attr->type == PERF_TYPE_HW_CACHE) {
+                pmap = sparc_map_cache_event(attr->config);
+                if (IS_ERR(pmap))
+                        return PTR_ERR(pmap);
+        } else
                 return -EOPNOTSUPP;
 
-        if (attr->config >= sparc_pmu->max_events)
-                return -EINVAL;
-
-        perf_event_grab_pmc();
-        event->destroy = hw_perf_event_destroy;
-
         /* We save the enable bits in the config_base.  So to
          * turn off sampling just write 'config', and to enable
          * things write 'config | config_base'.
@@ -411,15 +877,39 @@ static int __hw_perf_event_init(struct perf_event *event)
         if (!attr->exclude_hv)
                 hwc->config_base |= sparc_pmu->hv_bit;
 
+        hwc->event_base = perf_event_encode(pmap);
+
+        enc = pmap->encoding;
+
+        n = 0;
+        if (event->group_leader != event) {
+                n = collect_events(event->group_leader,
+                                   perf_max_events - 1,
+                                   evts, events);
+                if (n < 0)
+                        return -EINVAL;
+        }
+        events[n] = hwc->event_base;
+        evts[n] = event;
+
+        if (check_excludes(evts, n, 1))
+                return -EINVAL;
+
+        if (sparc_check_constraints(events, n + 1))
+                return -EINVAL;
+
+        /* Try to do all error checking before this point, as unwinding
+         * state after grabbing the PMC is difficult.
+         */
+        perf_event_grab_pmc();
+        event->destroy = hw_perf_event_destroy;
+
         if (!hwc->sample_period) {
                 hwc->sample_period = MAX_PERIOD;
                 hwc->last_period = hwc->sample_period;
                 atomic64_set(&hwc->period_left, hwc->sample_period);
         }
 
-        pmap = sparc_pmu->event_map(attr->config);
-
-        enc = pmap->encoding;
         if (pmap->pic_mask & PIC_UPPER) {
                 hwc->idx = PIC_UPPER_INDEX;
                 enc <<= sparc_pmu->upper_shift;
@@ -472,7 +962,7 @@ void perf_event_print_debug(void)
 }
 
 static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
-                                              unsigned long cmd, void *__args)
+                                            unsigned long cmd, void *__args)
 {
         struct die_args *args = __args;
         struct perf_sample_data data;
@@ -513,7 +1003,7 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
                         continue;
 
                 if (perf_event_overflow(event, 1, &data, regs))
-                        sparc_pmu_disable_event(hwc, idx);
+                        sparc_pmu_disable_event(cpuc, hwc, idx);
         }
 
         return NOTIFY_STOP;
@@ -525,8 +1015,15 @@ static __read_mostly struct notifier_block perf_event_nmi_notifier = {
 
 static bool __init supported_pmu(void)
 {
-        if (!strcmp(sparc_pmu_type, "ultra3i")) {
-                sparc_pmu = &ultra3i_pmu;
+        if (!strcmp(sparc_pmu_type, "ultra3") ||
+            !strcmp(sparc_pmu_type, "ultra3+") ||
+            !strcmp(sparc_pmu_type, "ultra3i") ||
+            !strcmp(sparc_pmu_type, "ultra4+")) {
+                sparc_pmu = &ultra3_pmu;
+                return true;
+        }
+        if (!strcmp(sparc_pmu_type, "niagara")) {
+                sparc_pmu = &niagara1_pmu;
                 return true;
         }
         if (!strcmp(sparc_pmu_type, "niagara2")) {
diff --git a/arch/sparc/oprofile/init.c b/arch/sparc/oprofile/init.c
index f97cb8b6ee5f..f9024bccff16 100644
--- a/arch/sparc/oprofile/init.c
+++ b/arch/sparc/oprofile/init.c
@@ -11,6 +11,7 @@
 #include <linux/oprofile.h>
 #include <linux/errno.h>
 #include <linux/init.h>
+#include <linux/param.h>        /* for HZ */
  
 #ifdef CONFIG_SPARC64
 #include <linux/notifier.h>
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 8da93745c087..c876bace8fdc 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -86,10 +86,6 @@ config STACKTRACE_SUPPORT
 config HAVE_LATENCYTOP_SUPPORT
         def_bool y
 
-config FAST_CMPXCHG_LOCAL
-        bool
-        default y
-
 config MMU
         def_bool y
 
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 527519b8a9f9..f2824fb8c79c 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -400,7 +400,7 @@ config X86_TSC
 
 config X86_CMPXCHG64
         def_bool y
-        depends on X86_PAE || X86_64
+        depends on X86_PAE || X86_64 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MATOM
 
 # this should be set for all -march=.. options where the compiler
 # generates cmov.
@@ -412,6 +412,7 @@ config X86_MINIMUM_CPU_FAMILY
         int
         default "64" if X86_64
         default "6" if X86_32 && X86_P6_NOP
+        default "5" if X86_32 && X86_CMPXCHG64
         default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK)
         default "3"
 
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index 74619c4f9fda..1733f9f65e82 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -21,8 +21,8 @@
 #define __AUDIT_ARCH_LE    0x40000000
 
 #ifndef CONFIG_AUDITSYSCALL
-#define sysexit_audit int_ret_from_sys_call
-#define sysretl_audit int_ret_from_sys_call
+#define sysexit_audit ia32_ret_from_sys_call
+#define sysretl_audit ia32_ret_from_sys_call
 #endif
 
 #define IA32_NR_syscalls ((ia32_syscall_end - ia32_sys_call_table)/8)
@@ -39,12 +39,12 @@
         .endm 
 
         /* clobbers %eax */     
-        .macro  CLEAR_RREGS _r9=rax
+        .macro  CLEAR_RREGS offset=0, _r9=rax
         xorl    %eax,%eax
-        movq    %rax,R11(%rsp)
-        movq    %rax,R10(%rsp)
-        movq    %\_r9,R9(%rsp)
-        movq    %rax,R8(%rsp)
+        movq    %rax,\offset+R11(%rsp)
+        movq    %rax,\offset+R10(%rsp)
+        movq    %\_r9,\offset+R9(%rsp)
+        movq    %rax,\offset+R8(%rsp)
         .endm
 
         /*
@@ -172,6 +172,10 @@ sysexit_from_sys_call:
         movl    RIP-R11(%rsp),%edx              /* User %eip */
         CFI_REGISTER rip,rdx
         RESTORE_ARGS 1,24,1,1,1,1
+        xorq    %r8,%r8
+        xorq    %r9,%r9
+        xorq    %r10,%r10
+        xorq    %r11,%r11
         popfq
         CFI_ADJUST_CFA_OFFSET -8
         /*CFI_RESTORE rflags*/
@@ -202,7 +206,7 @@ sysexit_from_sys_call:
 
         .macro auditsys_exit exit,ebpsave=RBP
         testl $(_TIF_ALLWORK_MASK & ~_TIF_SYSCALL_AUDIT),TI_flags(%r10)
-        jnz int_ret_from_sys_call
+        jnz ia32_ret_from_sys_call
         TRACE_IRQS_ON
         sti
         movl %eax,%esi          /* second arg, syscall return value */
@@ -218,8 +222,9 @@ sysexit_from_sys_call:
         cli
         TRACE_IRQS_OFF
         testl %edi,TI_flags(%r10)
-        jnz int_with_check
-        jmp \exit
+        jz \exit
+        CLEAR_RREGS -ARGOFFSET
+        jmp int_with_check
         .endm
 
 sysenter_auditsys:
@@ -329,6 +334,9 @@ sysretl_from_sys_call:
         CFI_REGISTER rip,rcx
         movl EFLAGS-ARGOFFSET(%rsp),%r11d       
         /*CFI_REGISTER rflags,r11*/
+        xorq    %r10,%r10
+        xorq    %r9,%r9
+        xorq    %r8,%r8
         TRACE_IRQS_ON
         movl RSP-ARGOFFSET(%rsp),%esp
         CFI_RESTORE rsp
@@ -353,7 +361,7 @@ cstar_tracesys:
 #endif
         xchgl %r9d,%ebp
         SAVE_REST
-        CLEAR_RREGS r9
+        CLEAR_RREGS 0, r9
         movq $-ENOSYS,RAX(%rsp) /* ptrace can change this for a bad syscall */
         movq %rsp,%rdi        /* &pt_regs -> arg1 */
         call syscall_trace_enter
@@ -425,6 +433,8 @@ ia32_do_call:
         call *ia32_sys_call_table(,%rax,8) # xxx: rip relative
 ia32_sysret:
         movq %rax,RAX-ARGOFFSET(%rsp)
+ia32_ret_from_sys_call:
+        CLEAR_RREGS -ARGOFFSET
         jmp int_ret_from_sys_call 
 
 ia32_tracesys:                   
@@ -442,8 +452,8 @@ END(ia32_syscall)
 
 ia32_badsys:
         movq $0,ORIG_RAX-ARGOFFSET(%rsp)
-        movq $-ENOSYS,RAX-ARGOFFSET(%rsp)
-        jmp int_ret_from_sys_call
+        movq $-ENOSYS,%rax
+        jmp ia32_sysret
 
 quiet_ni_syscall:
         movq $-ENOSYS,%rax
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 3be000435fad..d83892226f73 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -796,6 +796,7 @@ asmlinkage void kvm_handle_fault_on_reboot(void);
 #define KVM_ARCH_WANT_MMU_NOTIFIER
 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
 int kvm_age_hva(struct kvm *kvm, unsigned long hva);
+void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu);
 int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c
index 41fd965c80c6..b9c830c12b4a 100644
--- a/arch/x86/kernel/early_printk.c
+++ b/arch/x86/kernel/early_printk.c
@@ -206,8 +206,11 @@ static int __init setup_early_printk(char *buf)
 
         while (*buf != '\0') {
                 if (!strncmp(buf, "serial", 6)) {
-                        early_serial_init(buf + 6);
+                        buf += 6;
+                        early_serial_init(buf);
                         early_console_register(&early_serial_console, keep);
+                        if (!strncmp(buf, ",ttyS", 5))
+                                buf += 5;
                 }
                 if (!strncmp(buf, "ttyS", 4)) {
                         early_serial_init(buf + 4);
diff --git a/arch/x86/kernel/i386_ksyms_32.c b/arch/x86/kernel/i386_ksyms_32.c
index 1736c5a725aa..9c3bd4a2050e 100644
--- a/arch/x86/kernel/i386_ksyms_32.c
+++ b/arch/x86/kernel/i386_ksyms_32.c
@@ -15,8 +15,10 @@ EXPORT_SYMBOL(mcount);
  * the export, but dont use it from C code, it is used
  * by assembly code and is not using C calling convention!
  */
+#ifndef CONFIG_X86_CMPXCHG64
 extern void cmpxchg8b_emu(void);
 EXPORT_SYMBOL(cmpxchg8b_emu);
+#endif
 
 /* Networking helper routines. */
 EXPORT_SYMBOL(csum_partial_copy_generic);
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 1ae5ceba7eb2..7024224f0fc8 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -664,7 +664,7 @@ static void start_apic_timer(struct kvm_lapic *apic)
 {
         ktime_t now = apic->lapic_timer.timer.base->get_time();
 
-        apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
+        apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
                     APIC_BUS_CYCLE_NS * apic->divide_count;
         atomic_set(&apic->lapic_timer.pending, 0);
 
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index eca41ae9f453..685a4ffac8e6 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -156,6 +156,8 @@ module_param(oos_shadow, bool, 0644);
 #define CREATE_TRACE_POINTS
 #include "mmutrace.h"
 
+#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
+
 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
 
 struct kvm_rmap_desc {
@@ -634,9 +636,7 @@ static void rmap_remove(struct kvm *kvm, u64 *spte)
         if (*spte & shadow_accessed_mask)
                 kvm_set_pfn_accessed(pfn);
         if (is_writeble_pte(*spte))
-                kvm_release_pfn_dirty(pfn);
-        else
-                kvm_release_pfn_clean(pfn);
+                kvm_set_pfn_dirty(pfn);
         rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
         if (!*rmapp) {
                 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
@@ -748,7 +748,7 @@ static int rmap_write_protect(struct kvm *kvm, u64 gfn)
         return write_protected;
 }
 
-static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp)
+static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp, u64 data)
 {
         u64 *spte;
         int need_tlb_flush = 0;
@@ -763,8 +763,45 @@ static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp)
         return need_tlb_flush;
 }
 
-static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
-                          int (*handler)(struct kvm *kvm, unsigned long *rmapp))
+static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp, u64 data)
+{
+        int need_flush = 0;
+        u64 *spte, new_spte;
+        pte_t *ptep = (pte_t *)data;
+        pfn_t new_pfn;
+
+        WARN_ON(pte_huge(*ptep));
+        new_pfn = pte_pfn(*ptep);
+        spte = rmap_next(kvm, rmapp, NULL);
+        while (spte) {
+                BUG_ON(!is_shadow_present_pte(*spte));
+                rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
+                need_flush = 1;
+                if (pte_write(*ptep)) {
+                        rmap_remove(kvm, spte);
+                        __set_spte(spte, shadow_trap_nonpresent_pte);
+                        spte = rmap_next(kvm, rmapp, NULL);
+                } else {
+                        new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
+                        new_spte |= (u64)new_pfn << PAGE_SHIFT;
+
+                        new_spte &= ~PT_WRITABLE_MASK;
+                        new_spte &= ~SPTE_HOST_WRITEABLE;
+                        if (is_writeble_pte(*spte))
+                                kvm_set_pfn_dirty(spte_to_pfn(*spte));
+                        __set_spte(spte, new_spte);
+                        spte = rmap_next(kvm, rmapp, spte);
+                }
+        }
+        if (need_flush)
+                kvm_flush_remote_tlbs(kvm);
+
+        return 0;
+}
+
+static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, u64 data,
+                          int (*handler)(struct kvm *kvm, unsigned long *rmapp,
+                                         u64 data))
 {
         int i, j;
         int retval = 0;
@@ -786,13 +823,15 @@ static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
                 if (hva >= start && hva < end) {
                         gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
 
-                        retval |= handler(kvm, &memslot->rmap[gfn_offset]);
+                        retval |= handler(kvm, &memslot->rmap[gfn_offset],
+                                          data);
 
                         for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
                                 int idx = gfn_offset;
                                 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
                                 retval |= handler(kvm,
-                                        &memslot->lpage_info[j][idx].rmap_pde);
+                                        &memslot->lpage_info[j][idx].rmap_pde,
+                                        data);
                         }
                 }
         }
@@ -802,10 +841,15 @@ static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
 
 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
 {
-        return kvm_handle_hva(kvm, hva, kvm_unmap_rmapp);
+        return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
 }
 
-static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp)
+void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
+{
+        kvm_handle_hva(kvm, hva, (u64)&pte, kvm_set_pte_rmapp);
+}
+
+static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp, u64 data)
 {
         u64 *spte;
         int young = 0;
@@ -841,13 +885,13 @@ static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
         gfn = unalias_gfn(vcpu->kvm, gfn);
         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
 
-        kvm_unmap_rmapp(vcpu->kvm, rmapp);
+        kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
         kvm_flush_remote_tlbs(vcpu->kvm);
 }
 
 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
 {
-        return kvm_handle_hva(kvm, hva, kvm_age_rmapp);
+        return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
 }
 
 #ifdef MMU_DEBUG
@@ -1756,7 +1800,7 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                     unsigned pte_access, int user_fault,
                     int write_fault, int dirty, int level,
                     gfn_t gfn, pfn_t pfn, bool speculative,
-                    bool can_unsync)
+                    bool can_unsync, bool reset_host_protection)
 {
         u64 spte;
         int ret = 0;
@@ -1783,6 +1827,9 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
                         kvm_is_mmio_pfn(pfn));
 
+        if (reset_host_protection)
+                spte |= SPTE_HOST_WRITEABLE;
+
         spte |= (u64)pfn << PAGE_SHIFT;
 
         if ((pte_access & ACC_WRITE_MASK)
@@ -1828,7 +1875,8 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                          unsigned pt_access, unsigned pte_access,
                          int user_fault, int write_fault, int dirty,
                          int *ptwrite, int level, gfn_t gfn,
-                         pfn_t pfn, bool speculative)
+                         pfn_t pfn, bool speculative,
+                         bool reset_host_protection)
 {
         int was_rmapped = 0;
         int was_writeble = is_writeble_pte(*sptep);
@@ -1860,7 +1908,8 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
         }
 
         if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
-                      dirty, level, gfn, pfn, speculative, true)) {
+                      dirty, level, gfn, pfn, speculative, true,
+                      reset_host_protection)) {
                 if (write_fault)
                         *ptwrite = 1;
                 kvm_x86_ops->tlb_flush(vcpu);
@@ -1877,8 +1926,7 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
         page_header_update_slot(vcpu->kvm, sptep, gfn);
         if (!was_rmapped) {
                 rmap_count = rmap_add(vcpu, sptep, gfn);
-                if (!is_rmap_spte(*sptep))
-                        kvm_release_pfn_clean(pfn);
+                kvm_release_pfn_clean(pfn);
                 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
                         rmap_recycle(vcpu, sptep, gfn);
         } else {
@@ -1909,7 +1957,7 @@ static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
                 if (iterator.level == level) {
                         mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
                                      0, write, 1, &pt_write,
-                                     level, gfn, pfn, false);
+                                     level, gfn, pfn, false, true);
                         ++vcpu->stat.pf_fixed;
                         break;
                 }
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index d2fec9c12d22..72558f8ff3f5 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -273,9 +273,13 @@ static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
         if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
                 return;
         kvm_get_pfn(pfn);
+        /*
+         * we call mmu_set_spte() with reset_host_protection = true beacuse that
+         * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
+         */
         mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
                      gpte & PT_DIRTY_MASK, NULL, PT_PAGE_TABLE_LEVEL,
-                     gpte_to_gfn(gpte), pfn, true);
+                     gpte_to_gfn(gpte), pfn, true, true);
 }
 
 /*
@@ -308,7 +312,7 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
                                      user_fault, write_fault,
                                      gw->ptes[gw->level-1] & PT_DIRTY_MASK,
                                      ptwrite, level,
-                                     gw->gfn, pfn, false);
+                                     gw->gfn, pfn, false, true);
                         break;
                 }
 
@@ -558,6 +562,7 @@ static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 {
         int i, offset, nr_present;
+        bool reset_host_protection;
 
         offset = nr_present = 0;
 
@@ -595,9 +600,16 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 
                 nr_present++;
                 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
+                if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
+                        pte_access &= ~ACC_WRITE_MASK;
+                        reset_host_protection = 0;
+                } else {
+                        reset_host_protection = 1;
+                }
                 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
                          is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
-                         spte_to_pfn(sp->spt[i]), true, false);
+                         spte_to_pfn(sp->spt[i]), true, false,
+                         reset_host_protection);
         }
 
         return !nr_present;
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 944cc9c04b3c..c17404add91f 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -767,6 +767,8 @@ static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
                 rdtscll(tsc_this);
                 delta = vcpu->arch.host_tsc - tsc_this;
                 svm->vmcb->control.tsc_offset += delta;
+                if (is_nested(svm))
+                        svm->nested.hsave->control.tsc_offset += delta;
                 vcpu->cpu = cpu;
                 kvm_migrate_timers(vcpu);
                 svm->asid_generation = 0;
@@ -2057,10 +2059,14 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
 
         switch (ecx) {
         case MSR_IA32_TSC: {
-                u64 tsc;
+                u64 tsc_offset;
+
+                if (is_nested(svm))
+                        tsc_offset = svm->nested.hsave->control.tsc_offset;
+                else
+                        tsc_offset = svm->vmcb->control.tsc_offset;
 
-                rdtscll(tsc);
-                *data = svm->vmcb->control.tsc_offset + tsc;
+                *data = tsc_offset + native_read_tsc();
                 break;
         }
         case MSR_K6_STAR:
@@ -2146,10 +2152,17 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
 
         switch (ecx) {
         case MSR_IA32_TSC: {
-                u64 tsc;
+                u64 tsc_offset = data - native_read_tsc();
+                u64 g_tsc_offset = 0;
+
+                if (is_nested(svm)) {
+                        g_tsc_offset = svm->vmcb->control.tsc_offset -
+                                       svm->nested.hsave->control.tsc_offset;
+                        svm->nested.hsave->control.tsc_offset = tsc_offset;
+                }
+
+                svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
 
-                rdtscll(tsc);
-                svm->vmcb->control.tsc_offset = data - tsc;
                 break;
         }
         case MSR_K6_STAR:
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index f3812014bd0b..ed53b42caba1 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -709,7 +709,7 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
         if (vcpu->cpu != cpu) {
                 vcpu_clear(vmx);
                 kvm_migrate_timers(vcpu);
-                vpid_sync_vcpu_all(vmx);
+                set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
                 local_irq_disable();
                 list_add(&vmx->local_vcpus_link,
                          &per_cpu(vcpus_on_cpu, cpu));
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index be451ee44249..9b9695322f56 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1591,6 +1591,8 @@ static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
 
         if (cpuid->nent < 1)
                 goto out;
+        if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
+                cpuid->nent = KVM_MAX_CPUID_ENTRIES;
         r = -ENOMEM;
         cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
         if (!cpuid_entries)
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 3e549b8ec8c9..85f5db95c60f 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -15,8 +15,10 @@ ifeq ($(CONFIG_X86_32),y)
         obj-y += atomic64_32.o
         lib-y += checksum_32.o
         lib-y += strstr_32.o
-        lib-y += semaphore_32.o string_32.o cmpxchg8b_emu.o
-
+        lib-y += semaphore_32.o string_32.o
+ifneq ($(CONFIG_X86_CMPXCHG64),y)
+        lib-y += cmpxchg8b_emu.o
+endif
         lib-$(CONFIG_X86_USE_3DNOW) += mmx_32.o
 else
         obj-y += io_64.o iomap_copy_64.o
diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c
index 60ab75104da9..1c129211302d 100644
--- a/drivers/char/agp/parisc-agp.c
+++ b/drivers/char/agp/parisc-agp.c
@@ -217,7 +217,7 @@ static const struct agp_bridge_driver parisc_agp_driver = {
         .configure              = parisc_agp_configure,
         .fetch_size             = parisc_agp_fetch_size,
         .tlb_flush              = parisc_agp_tlbflush,
-        .mask_memory            = parisc_agp_page_mask_memory,
+        .mask_memory            = parisc_agp_mask_memory,
         .masks                  = parisc_agp_masks,
         .agp_enable             = parisc_agp_enable,
         .cache_flush            = global_cache_flush,
diff --git a/drivers/connector/cn_proc.c b/drivers/connector/cn_proc.c
index abf4a2529f80..60697909ebdb 100644
--- a/drivers/connector/cn_proc.c
+++ b/drivers/connector/cn_proc.c
@@ -227,7 +227,8 @@ static void cn_proc_ack(int err, int rcvd_seq, int rcvd_ack)
  * cn_proc_mcast_ctl
  * @data: message sent from userspace via the connector
  */
-static void cn_proc_mcast_ctl(struct cn_msg *msg)
+static void cn_proc_mcast_ctl(struct cn_msg *msg,
+                              struct netlink_skb_parms *nsp)
 {
         enum proc_cn_mcast_op *mc_op = NULL;
         int err = 0;
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 4e551e63b6dc..4f4ac82382f7 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -15,8 +15,8 @@ module_param(ecc_enable_override, int, 0644);
 
 /* Lookup table for all possible MC control instances */
 struct amd64_pvt;
-static struct mem_ctl_info *mci_lookup[MAX_NUMNODES];
-static struct amd64_pvt *pvt_lookup[MAX_NUMNODES];
+static struct mem_ctl_info *mci_lookup[EDAC_MAX_NUMNODES];
+static struct amd64_pvt *pvt_lookup[EDAC_MAX_NUMNODES];
 
 /*
  * See F2x80 for K8 and F2x[1,0]80 for Fam10 and later. The table below is only
@@ -189,7 +189,10 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
 /* Map from a CSROW entry to the mask entry that operates on it */
 static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow)
 {
-        return csrow >> (pvt->num_dcsm >> 3);
+        if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_F)
+                return csrow;
+        else
+                return csrow >> 1;
 }
 
 /* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */
@@ -279,29 +282,26 @@ static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
         intlv_en = pvt->dram_IntlvEn[0];
 
         if (intlv_en == 0) {
-                for (node_id = 0; ; ) {
+                for (node_id = 0; node_id < DRAM_REG_COUNT; node_id++) {
                         if (amd64_base_limit_match(pvt, sys_addr, node_id))
-                                break;
-
-                        if (++node_id >= DRAM_REG_COUNT)
-                                goto err_no_match;
+                                goto found;
                 }
-                goto found;
+                goto err_no_match;
         }
 
-        if (unlikely((intlv_en != (0x01 << 8)) &&
-                     (intlv_en != (0x03 << 8)) &&
-                     (intlv_en != (0x07 << 8)))) {
+        if (unlikely((intlv_en != 0x01) &&
+                     (intlv_en != 0x03) &&
+                     (intlv_en != 0x07))) {
                 amd64_printk(KERN_WARNING, "junk value of 0x%x extracted from "
                              "IntlvEn field of DRAM Base Register for node 0: "
-                             "This probably indicates a BIOS bug.\n", intlv_en);
+                             "this probably indicates a BIOS bug.\n", intlv_en);
                 return NULL;
         }
 
         bits = (((u32) sys_addr) >> 12) & intlv_en;
 
         for (node_id = 0; ; ) {
-                if ((pvt->dram_limit[node_id] & intlv_en) == bits)
+                if ((pvt->dram_IntlvSel[node_id] & intlv_en) == bits)
                         break;  /* intlv_sel field matches */
 
                 if (++node_id >= DRAM_REG_COUNT)
@@ -311,10 +311,10 @@ static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci,
         /* sanity test for sys_addr */
         if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) {
                 amd64_printk(KERN_WARNING,
-                          "%s(): sys_addr 0x%lx falls outside base/limit "
-                          "address range for node %d with node interleaving "
-                          "enabled.\n", __func__, (unsigned long)sys_addr,
-                          node_id);
+                             "%s(): sys_addr 0x%llx falls outside base/limit "
+                             "address range for node %d with node interleaving "
+                             "enabled.\n",
+                             __func__, sys_addr, node_id);
                 return NULL;
         }
 
@@ -377,7 +377,7 @@ static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
          * base/mask register pair, test the condition shown near the start of
          * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E).
          */
-        for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) {
+        for (csrow = 0; csrow < pvt->cs_count; csrow++) {
 
                 /* This DRAM chip select is disabled on this node */
                 if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0)
@@ -734,7 +734,7 @@ static void find_csrow_limits(struct mem_ctl_info *mci, int csrow,
         u64 base, mask;
 
         pvt = mci->pvt_info;
-        BUG_ON((csrow < 0) || (csrow >= CHIPSELECT_COUNT));
+        BUG_ON((csrow < 0) || (csrow >= pvt->cs_count));
 
         base = base_from_dct_base(pvt, csrow);
         mask = mask_from_dct_mask(pvt, csrow);
@@ -962,35 +962,27 @@ err_reg:
  */
 static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt)
 {
-        if (pvt->ext_model >= OPTERON_CPU_REV_F) {
+
+        if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_F) {
+                pvt->dcsb_base          = REV_E_DCSB_BASE_BITS;
+                pvt->dcsm_mask          = REV_E_DCSM_MASK_BITS;
+                pvt->dcs_mask_notused   = REV_E_DCS_NOTUSED_BITS;
+                pvt->dcs_shift          = REV_E_DCS_SHIFT;
+                pvt->cs_count           = 8;
+                pvt->num_dcsm           = 8;
+        } else {
                 pvt->dcsb_base          = REV_F_F1Xh_DCSB_BASE_BITS;
                 pvt->dcsm_mask          = REV_F_F1Xh_DCSM_MASK_BITS;
                 pvt->dcs_mask_notused   = REV_F_F1Xh_DCS_NOTUSED_BITS;
                 pvt->dcs_shift          = REV_F_F1Xh_DCS_SHIFT;
 
-                switch (boot_cpu_data.x86) {
-                case 0xf:
-                        pvt->num_dcsm = REV_F_DCSM_COUNT;
-                        break;
-
-                case 0x10:
-                        pvt->num_dcsm = F10_DCSM_COUNT;
-                        break;
-
-                case 0x11:
-                        pvt->num_dcsm = F11_DCSM_COUNT;
-                        break;
-
-                default:
-                        amd64_printk(KERN_ERR, "Unsupported family!\n");
-                        break;
+                if (boot_cpu_data.x86 == 0x11) {
+                        pvt->cs_count = 4;
+                        pvt->num_dcsm = 2;
+                } else {
+                        pvt->cs_count = 8;
+                        pvt->num_dcsm = 4;
                 }
-        } else {
-                pvt->dcsb_base          = REV_E_DCSB_BASE_BITS;
-                pvt->dcsm_mask          = REV_E_DCSM_MASK_BITS;
-                pvt->dcs_mask_notused   = REV_E_DCS_NOTUSED_BITS;
-                pvt->dcs_shift          = REV_E_DCS_SHIFT;
-                pvt->num_dcsm           = REV_E_DCSM_COUNT;
         }
 }
 
@@ -1003,7 +995,7 @@ static void amd64_read_dct_base_mask(struct amd64_pvt *pvt)
 
         amd64_set_dct_base_and_mask(pvt);
 
-        for (cs = 0; cs < CHIPSELECT_COUNT; cs++) {
+        for (cs = 0; cs < pvt->cs_count; cs++) {
                 reg = K8_DCSB0 + (cs * 4);
                 err = pci_read_config_dword(pvt->dram_f2_ctl, reg,
                                                 &pvt->dcsb0[cs]);
@@ -1130,7 +1122,7 @@ static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
                 debugf0("Reading K8_DRAM_BASE_LOW failed\n");
 
         /* Extract parts into separate data entries */
-        pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8;
+        pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 24;
         pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7;
         pvt->dram_rw_en[dram] = (low & 0x3);
 
@@ -1143,7 +1135,7 @@ static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
          * Extract parts into separate data entries. Limit is the HIGHEST memory
          * location of the region, so lower 24 bits need to be all ones
          */
-        pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF;
+        pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 24) | 0x00FFFFFF;
         pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7;
         pvt->dram_DstNode[dram] = (low & 0x7);
 }
@@ -1193,7 +1185,7 @@ static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
          * different from the node that detected the error.
          */
         src_mci = find_mc_by_sys_addr(mci, SystemAddress);
-        if (src_mci) {
+        if (!src_mci) {
                 amd64_mc_printk(mci, KERN_ERR,
                              "failed to map error address 0x%lx to a node\n",
                              (unsigned long)SystemAddress);
@@ -1376,8 +1368,8 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
 
         pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7;
 
-        pvt->dram_base[dram] = (((((u64) high_base & 0x000000FF) << 32) |
-                                ((u64) low_base & 0xFFFF0000))) << 8;
+        pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) |
+                               (((u64)low_base  & 0xFFFF0000) << 24);
 
         low_offset = K8_DRAM_LIMIT_LOW + (dram << 3);
         high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3);
@@ -1398,9 +1390,9 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram)
          * Extract address values and form a LIMIT address. Limit is the HIGHEST
          * memory location of the region, so low 24 bits need to be all ones.
          */
-        low_limit |= 0x0000FFFF;
-        pvt->dram_limit[dram] =
-                ((((u64) high_limit << 32) + (u64) low_limit) << 8) | (0xFF);
+        pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) |
+                                (((u64) low_limit & 0xFFFF0000) << 24) |
+                                0x00FFFFFF;
 }
 
 static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
@@ -1566,7 +1558,7 @@ static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs)
 
         debugf1("InputAddr=0x%x  channelselect=%d\n", in_addr, cs);
 
-        for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) {
+        for (csrow = 0; csrow < pvt->cs_count; csrow++) {
 
                 cs_base = amd64_get_dct_base(pvt, cs, csrow);
                 if (!(cs_base & K8_DCSB_CS_ENABLE))
@@ -2497,7 +2489,7 @@ err_reg:
  * NOTE: CPU Revision Dependent code
  *
  * Input:
- *      @csrow_nr ChipSelect Row Number (0..CHIPSELECT_COUNT-1)
+ *      @csrow_nr ChipSelect Row Number (0..pvt->cs_count-1)
  *      k8 private pointer to -->
  *                      DRAM Bank Address mapping register
  *                      node_id
@@ -2577,7 +2569,7 @@ static int amd64_init_csrows(struct mem_ctl_info *mci)
                 (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"
                 );
 
-        for (i = 0; i < CHIPSELECT_COUNT; i++) {
+        for (i = 0; i < pvt->cs_count; i++) {
                 csrow = &mci->csrows[i];
 
                 if ((pvt->dcsb0[i] & K8_DCSB_CS_ENABLE) == 0) {
@@ -2988,7 +2980,7 @@ static int amd64_init_2nd_stage(struct amd64_pvt *pvt)
                 goto err_exit;
 
         ret = -ENOMEM;
-        mci = edac_mc_alloc(0, CHIPSELECT_COUNT, pvt->channel_count, node_id);
+        mci = edac_mc_alloc(0, pvt->cs_count, pvt->channel_count, node_id);
         if (!mci)
                 goto err_exit;
 
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 8ea07e2715dc..c6f359a85207 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -132,6 +132,8 @@
 #define EDAC_AMD64_VERSION              " Ver: 3.2.0 " __DATE__
 #define EDAC_MOD_STR                    "amd64_edac"
 
+#define EDAC_MAX_NUMNODES               8
+
 /* Extended Model from CPUID, for CPU Revision numbers */
 #define OPTERON_CPU_LE_REV_C            0
 #define OPTERON_CPU_REV_D               1
@@ -142,7 +144,7 @@
 #define OPTERON_CPU_REV_FA              5
 
 /* Hardware limit on ChipSelect rows per MC and processors per system */
-#define CHIPSELECT_COUNT                8
+#define MAX_CS_COUNT                    8
 #define DRAM_REG_COUNT                  8
 
 
@@ -193,7 +195,6 @@
  */
 #define REV_E_DCSB_BASE_BITS            (0xFFE0FE00ULL)
 #define REV_E_DCS_SHIFT                 4
-#define REV_E_DCSM_COUNT                8
 
 #define REV_F_F1Xh_DCSB_BASE_BITS       (0x1FF83FE0ULL)
 #define REV_F_F1Xh_DCS_SHIFT            8
@@ -204,9 +205,6 @@
  */
 #define REV_F_DCSB_BASE_BITS            (0x1FF83FE0ULL)
 #define REV_F_DCS_SHIFT                 8
-#define REV_F_DCSM_COUNT                4
-#define F10_DCSM_COUNT                  4
-#define F11_DCSM_COUNT                  2
 
 /* DRAM CS Mask Registers */
 #define K8_DCSM0                        0x60
@@ -374,13 +372,11 @@ enum {
 
 #define SET_NB_DRAM_INJECTION_WRITE(word, bits)  \
                                         (BIT(((word) & 0xF) + 20) | \
-                                        BIT(17) |  \
-                                        ((bits) & 0xF))
+                                        BIT(17) | bits)
 
 #define SET_NB_DRAM_INJECTION_READ(word, bits)  \
                                         (BIT(((word) & 0xF) + 20) | \
-                                        BIT(16) |  \
-                                        ((bits) & 0xF))
+                                        BIT(16) |  bits)
 
 #define K8_NBCAP                        0xE8
 #define K8_NBCAP_CORES                  (BIT(12)|BIT(13))
@@ -445,12 +441,12 @@ struct amd64_pvt {
         u32 dbam1;              /* DRAM Base Address Mapping reg for DCT1 */
 
         /* DRAM CS Base Address Registers F2x[1,0][5C:40] */
-        u32 dcsb0[CHIPSELECT_COUNT];
-        u32 dcsb1[CHIPSELECT_COUNT];
+        u32 dcsb0[MAX_CS_COUNT];
+        u32 dcsb1[MAX_CS_COUNT];
 
         /* DRAM CS Mask Registers F2x[1,0][6C:60] */
-        u32 dcsm0[CHIPSELECT_COUNT];
-        u32 dcsm1[CHIPSELECT_COUNT];
+        u32 dcsm0[MAX_CS_COUNT];
+        u32 dcsm1[MAX_CS_COUNT];
 
         /*
          * Decoded parts of DRAM BASE and LIMIT Registers
@@ -470,6 +466,7 @@ struct amd64_pvt {
          */
         u32 dcsb_base;          /* DCSB base bits */
         u32 dcsm_mask;          /* DCSM mask bits */
+        u32 cs_count;           /* num chip selects (== num DCSB registers) */
         u32 num_dcsm;           /* Number of DCSM registers */
         u32 dcs_mask_notused;   /* DCSM notused mask bits */
         u32 dcs_shift;          /* DCSB and DCSM shift value */
diff --git a/drivers/edac/amd64_edac_inj.c b/drivers/edac/amd64_edac_inj.c
index d3675b76b3a7..29f1f7a612d9 100644
--- a/drivers/edac/amd64_edac_inj.c
+++ b/drivers/edac/amd64_edac_inj.c
@@ -1,5 +1,11 @@
 #include "amd64_edac.h"
 
+static ssize_t amd64_inject_section_show(struct mem_ctl_info *mci, char *buf)
+{
+        struct amd64_pvt *pvt = mci->pvt_info;
+        return sprintf(buf, "0x%x\n", pvt->injection.section);
+}
+
 /*
  * store error injection section value which refers to one of 4 16-byte sections
  * within a 64-byte cacheline
@@ -15,12 +21,26 @@ static ssize_t amd64_inject_section_store(struct mem_ctl_info *mci,
 
         ret = strict_strtoul(data, 10, &value);
         if (ret != -EINVAL) {
+
+                if (value > 3) {
+                        amd64_printk(KERN_WARNING,
+                                     "%s: invalid section 0x%lx\n",
+                                     __func__, value);
+                        return -EINVAL;
+                }
+
                 pvt->injection.section = (u32) value;
                 return count;
         }
         return ret;
 }
 
+static ssize_t amd64_inject_word_show(struct mem_ctl_info *mci, char *buf)
+{
+        struct amd64_pvt *pvt = mci->pvt_info;
+        return sprintf(buf, "0x%x\n", pvt->injection.word);
+}
+
 /*
  * store error injection word value which refers to one of 9 16-bit word of the
  * 16-byte (128-bit + ECC bits) section
@@ -37,14 +57,25 @@ static ssize_t amd64_inject_word_store(struct mem_ctl_info *mci,
         ret = strict_strtoul(data, 10, &value);
         if (ret != -EINVAL) {
 
-                value = (value <= 8) ? value : 0;
-                pvt->injection.word = (u32) value;
+                if (value > 8) {
+                        amd64_printk(KERN_WARNING,
+                                     "%s: invalid word 0x%lx\n",
+                                     __func__, value);
+                        return -EINVAL;
+                }
 
+                pvt->injection.word = (u32) value;
                 return count;
         }
         return ret;
 }
 
+static ssize_t amd64_inject_ecc_vector_show(struct mem_ctl_info *mci, char *buf)
+{
+        struct amd64_pvt *pvt = mci->pvt_info;
+        return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
+}
+
 /*
  * store 16 bit error injection vector which enables injecting errors to the
  * corresponding bit within the error injection word above. When used during a
@@ -60,8 +91,14 @@ static ssize_t amd64_inject_ecc_vector_store(struct mem_ctl_info *mci,
         ret = strict_strtoul(data, 16, &value);
         if (ret != -EINVAL) {
 
-                pvt->injection.bit_map = (u32) value & 0xFFFF;
+                if (value & 0xFFFF0000) {
+                        amd64_printk(KERN_WARNING,
+                                     "%s: invalid EccVector: 0x%lx\n",
+                                     __func__, value);
+                        return -EINVAL;
+                }
 
+                pvt->injection.bit_map = (u32) value;
                 return count;
         }
         return ret;
@@ -147,7 +184,7 @@ struct mcidev_sysfs_attribute amd64_inj_attrs[] = {
                         .name = "inject_section",
                         .mode = (S_IRUGO | S_IWUSR)
                 },
-                .show = NULL,
+                .show = amd64_inject_section_show,
                 .store = amd64_inject_section_store,
         },
         {
@@ -155,7 +192,7 @@ struct mcidev_sysfs_attribute amd64_inj_attrs[] = {
                         .name = "inject_word",
                         .mode = (S_IRUGO | S_IWUSR)
                 },
-                .show = NULL,
+                .show = amd64_inject_word_show,
                 .store = amd64_inject_word_store,
         },
         {
@@ -163,7 +200,7 @@ struct mcidev_sysfs_attribute amd64_inj_attrs[] = {
                         .name = "inject_ecc_vector",
                         .mode = (S_IRUGO | S_IWUSR)
                 },
-                .show = NULL,
+                .show = amd64_inject_ecc_vector_show,
                 .store = amd64_inject_ecc_vector_store,
         },
         {
diff --git a/drivers/firmware/iscsi_ibft.c b/drivers/firmware/iscsi_ibft.c
index 420a96e7f2db..051d1ebbd287 100644
--- a/drivers/firmware/iscsi_ibft.c
+++ b/drivers/firmware/iscsi_ibft.c
@@ -939,7 +939,7 @@ static int __init ibft_init(void)
 
         if (ibft_addr) {
                 printk(KERN_INFO "iBFT detected at 0x%llx.\n",
-                       (u64)virt_to_phys((void *)ibft_addr));
+                       (u64)isa_virt_to_bus(ibft_addr));
 
                 rc = ibft_check_device();
                 if (rc)
diff --git a/drivers/firmware/iscsi_ibft_find.c b/drivers/firmware/iscsi_ibft_find.c
index d53fbbfefa3e..dfb15c06c88f 100644
--- a/drivers/firmware/iscsi_ibft_find.c
+++ b/drivers/firmware/iscsi_ibft_find.c
@@ -65,10 +65,10 @@ void __init reserve_ibft_region(void)
                  * so skip that area */
                 if (pos == VGA_MEM)
                         pos += VGA_SIZE;
-                virt = phys_to_virt(pos);
+                virt = isa_bus_to_virt(pos);
                 if (memcmp(virt, IBFT_SIGN, IBFT_SIGN_LEN) == 0) {
                         unsigned long *addr =
-                            (unsigned long *)phys_to_virt(pos + 4);
+                            (unsigned long *)isa_bus_to_virt(pos + 4);
                         len = *addr;
                         /* if the length of the table extends past 1M,
                          * the table cannot be valid. */
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 8e7b0ebece0c..5cae0b3eee9b 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -1556,8 +1556,6 @@ int drm_mode_cursor_ioctl(struct drm_device *dev,
         struct drm_crtc *crtc;
         int ret = 0;
 
-        DRM_DEBUG_KMS("\n");
-
         if (!req->flags) {
                 DRM_ERROR("no operation set\n");
                 return -EINVAL;
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 819ddcbfcce5..23dc9c115fd9 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -454,6 +454,96 @@ out_free:
 }
 EXPORT_SYMBOL(drm_fb_helper_init_crtc_count);
 
+static void setcolreg(struct drm_crtc *crtc, u16 red, u16 green,
+                     u16 blue, u16 regno, struct fb_info *info)
+{
+        struct drm_fb_helper *fb_helper = info->par;
+        struct drm_framebuffer *fb = fb_helper->fb;
+        int pindex;
+
+        pindex = regno;
+
+        if (fb->bits_per_pixel == 16) {
+                pindex = regno << 3;
+
+                if (fb->depth == 16 && regno > 63)
+                        return;
+                if (fb->depth == 15 && regno > 31)
+                        return;
+
+                if (fb->depth == 16) {
+                        u16 r, g, b;
+                        int i;
+                        if (regno < 32) {
+                                for (i = 0; i < 8; i++)
+                                        fb_helper->funcs->gamma_set(crtc, red,
+                                                green, blue, pindex + i);
+                        }
+
+                        fb_helper->funcs->gamma_get(crtc, &r,
+                                                    &g, &b,
+                                                    pindex >> 1);
+
+                        for (i = 0; i < 4; i++)
+                                fb_helper->funcs->gamma_set(crtc, r,
+                                                            green, b,
+                                                            (pindex >> 1) + i);
+                }
+        }
+
+        if (fb->depth != 16)
+                fb_helper->funcs->gamma_set(crtc, red, green, blue, pindex);
+
+        if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
+                ((u32 *) fb->pseudo_palette)[regno] =
+                        (regno << info->var.red.offset) |
+                        (regno << info->var.green.offset) |
+                        (regno << info->var.blue.offset);
+        }
+}
+
+int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct fb_info *info)
+{
+        struct drm_fb_helper *fb_helper = info->par;
+        struct drm_device *dev = fb_helper->dev;
+        u16 *red, *green, *blue, *transp;
+        struct drm_crtc *crtc;
+        int i, rc = 0;
+        int start;
+
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+                for (i = 0; i < fb_helper->crtc_count; i++) {
+                        if (crtc->base.id == fb_helper->crtc_info[i].crtc_id)
+                                break;
+                }
+                if (i == fb_helper->crtc_count)
+                        continue;
+
+                red = cmap->red;
+                green = cmap->green;
+                blue = cmap->blue;
+                transp = cmap->transp;
+                start = cmap->start;
+
+                for (i = 0; i < cmap->len; i++) {
+                        u16 hred, hgreen, hblue, htransp = 0xffff;
+
+                        hred = *red++;
+                        hgreen = *green++;
+                        hblue = *blue++;
+
+                        if (transp)
+                                htransp = *transp++;
+
+                        setcolreg(crtc, hred, hgreen, hblue, start++, info);
+                }
+                crtc_funcs->load_lut(crtc);
+        }
+        return rc;
+}
+EXPORT_SYMBOL(drm_fb_helper_setcmap);
+
 int drm_fb_helper_setcolreg(unsigned regno,
                             unsigned red,
                             unsigned green,
@@ -466,9 +556,11 @@ int drm_fb_helper_setcolreg(unsigned regno,
         struct drm_crtc *crtc;
         int i;
 
-        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
-                struct drm_framebuffer *fb = fb_helper->fb;
+        if (regno > 255)
+                return 1;
 
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
                 for (i = 0; i < fb_helper->crtc_count; i++) {
                         if (crtc->base.id == fb_helper->crtc_info[i].crtc_id)
                                 break;
@@ -476,35 +568,9 @@ int drm_fb_helper_setcolreg(unsigned regno,
                 if (i == fb_helper->crtc_count)
                         continue;
 
-                if (regno > 255)
-                        return 1;
-
-                if (fb->depth == 8) {
-                        fb_helper->funcs->gamma_set(crtc, red, green, blue, regno);
-                        return 0;
-                }
 
-                if (regno < 16) {
-                        switch (fb->depth) {
-                        case 15:
-                                fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
-                                        ((green & 0xf800) >>  6) |
-                                        ((blue & 0xf800) >> 11);
-                                break;
-                        case 16:
-                                fb->pseudo_palette[regno] = (red & 0xf800) |
-                                        ((green & 0xfc00) >>  5) |
-                                        ((blue  & 0xf800) >> 11);
-                                break;
-                        case 24:
-                        case 32:
-                                fb->pseudo_palette[regno] =
-                                        (((red >> 8) & 0xff) << info->var.red.offset) |
-                                        (((green >> 8) & 0xff) << info->var.green.offset) |
-                                        (((blue >> 8) & 0xff) << info->var.blue.offset);
-                                break;
-                        }
-                }
+                setcolreg(crtc, red, green, blue, regno, info);
+                crtc_funcs->load_lut(crtc);
         }
         return 0;
 }
@@ -674,6 +740,7 @@ int drm_fb_helper_pan_display(struct fb_var_screeninfo *var,
 EXPORT_SYMBOL(drm_fb_helper_pan_display);
 
 int drm_fb_helper_single_fb_probe(struct drm_device *dev,
+                                  int preferred_bpp,
                                   int (*fb_create)(struct drm_device *dev,
                                                    uint32_t fb_width,
                                                    uint32_t fb_height,
@@ -696,6 +763,11 @@ int drm_fb_helper_single_fb_probe(struct drm_device *dev,
         struct drm_fb_helper *fb_helper;
         uint32_t surface_depth = 24, surface_bpp = 32;
 
+        /* if driver picks 8 or 16 by default use that
+           for both depth/bpp */
+        if (preferred_bpp != surface_bpp) {
+                surface_depth = surface_bpp = preferred_bpp;
+        }
         /* first up get a count of crtcs now in use and new min/maxes width/heights */
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                 struct drm_fb_helper_connector *fb_help_conn = connector->fb_helper_private;
@@ -851,10 +923,12 @@ void drm_fb_helper_free(struct drm_fb_helper *helper)
 }
 EXPORT_SYMBOL(drm_fb_helper_free);
 
-void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch)
+void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch,
+                            uint32_t depth)
 {
         info->fix.type = FB_TYPE_PACKED_PIXELS;
-        info->fix.visual = FB_VISUAL_TRUECOLOR;
+        info->fix.visual = depth == 8 ? FB_VISUAL_PSEUDOCOLOR :
+                FB_VISUAL_DIRECTCOLOR;
         info->fix.type_aux = 0;
         info->fix.xpanstep = 1; /* doing it in hw */
         info->fix.ypanstep = 1; /* doing it in hw */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 93ff6c03733e..ffa39671751f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3244,6 +3244,16 @@ void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
         intel_crtc->lut_b[regno] = blue >> 8;
 }
 
+void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
+                             u16 *blue, int regno)
+{
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+        *red = intel_crtc->lut_r[regno] << 8;
+        *green = intel_crtc->lut_g[regno] << 8;
+        *blue = intel_crtc->lut_b[regno] << 8;
+}
+
 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
                                  u16 *blue, uint32_t size)
 {
@@ -3835,6 +3845,7 @@ static const struct drm_crtc_helper_funcs intel_helper_funcs = {
         .mode_set_base = intel_pipe_set_base,
         .prepare = intel_crtc_prepare,
         .commit = intel_crtc_commit,
+        .load_lut = intel_crtc_load_lut,
 };
 
 static const struct drm_crtc_funcs intel_crtc_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8aa4b7f30daa..ef61fe9507e2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -175,6 +175,8 @@ extern int intelfb_resize(struct drm_device *dev, struct drm_crtc *crtc);
 extern void intelfb_restore(void);
 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
                                     u16 blue, int regno);
+extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
+                                    u16 *blue, int regno);
 
 extern int intel_framebuffer_create(struct drm_device *dev,
                                     struct drm_mode_fb_cmd *mode_cmd,
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index e85d7e9eed7d..2b0fe54cd92c 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -60,10 +60,12 @@ static struct fb_ops intelfb_ops = {
         .fb_imageblit = cfb_imageblit,
         .fb_pan_display = drm_fb_helper_pan_display,
         .fb_blank = drm_fb_helper_blank,
+        .fb_setcmap = drm_fb_helper_setcmap,
 };
 
 static struct drm_fb_helper_funcs intel_fb_helper_funcs = {
         .gamma_set = intel_crtc_fb_gamma_set,
+        .gamma_get = intel_crtc_fb_gamma_get,
 };
 
 
@@ -123,6 +125,10 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
         struct device *device = &dev->pdev->dev;
         int size, ret, mmio_bar = IS_I9XX(dev) ? 0 : 1;
 
+        /* we don't do packed 24bpp */
+        if (surface_bpp == 24)
+                surface_bpp = 32;
+
         mode_cmd.width = surface_width;
         mode_cmd.height = surface_height;
 
@@ -206,7 +212,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
 
 //      memset(info->screen_base, 0, size);
 
-        drm_fb_helper_fill_fix(info, fb->pitch);
+        drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
         drm_fb_helper_fill_var(info, fb, fb_width, fb_height);
 
         /* FIXME: we really shouldn't expose mmio space at all */
@@ -244,7 +250,7 @@ int intelfb_probe(struct drm_device *dev)
         int ret;
 
         DRM_DEBUG("\n");
-        ret = drm_fb_helper_single_fb_probe(dev, intelfb_create);
+        ret = drm_fb_helper_single_fb_probe(dev, 32, intelfb_create);
         return ret;
 }
 EXPORT_SYMBOL(intelfb_probe);
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 6a015929deee..14fa9701aeb3 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -733,6 +733,7 @@ static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
         .mode_set_base = atombios_crtc_set_base,
         .prepare = atombios_crtc_prepare,
         .commit = atombios_crtc_commit,
+        .load_lut = radeon_crtc_load_lut,
 };
 
 void radeon_atombios_init_crtc(struct drm_device *dev,
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index e6cce24de802..161094c07d94 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -32,6 +32,9 @@
 #include "radeon_reg.h"
 #include "radeon.h"
 #include "r100d.h"
+#include "rs100d.h"
+#include "rv200d.h"
+#include "rv250d.h"
 
 #include <linux/firmware.h>
 #include <linux/platform_device.h>
@@ -60,18 +63,7 @@ MODULE_FIRMWARE(FIRMWARE_R520);
 
 /* This files gather functions specifics to:
  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
- *
- * Some of these functions might be used by newer ASICs.
  */
-int r200_init(struct radeon_device *rdev);
-void r100_hdp_reset(struct radeon_device *rdev);
-void r100_gpu_init(struct radeon_device *rdev);
-int r100_gui_wait_for_idle(struct radeon_device *rdev);
-int r100_mc_wait_for_idle(struct radeon_device *rdev);
-void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
-void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
-int r100_debugfs_mc_info_init(struct radeon_device *rdev);
-
 
 /*
  * PCI GART
@@ -152,136 +144,6 @@ void r100_pci_gart_fini(struct radeon_device *rdev)
         radeon_gart_fini(rdev);
 }
 
-
-/*
- * MC
- */
-void r100_mc_disable_clients(struct radeon_device *rdev)
-{
-        uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
-
-        /* FIXME: is this function correct for rs100,rs200,rs300 ? */
-        if (r100_gui_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "Failed to wait GUI idle while "
-                       "programming pipes. Bad things might happen.\n");
-        }
-
-        /* stop display and memory access */
-        ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
-        WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
-        crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
-        WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
-        crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
-
-        r100_gpu_wait_for_vsync(rdev);
-
-        WREG32(RADEON_CRTC_GEN_CNTL,
-               (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
-               RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
-
-        if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
-                crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
-
-                r100_gpu_wait_for_vsync2(rdev);
-                WREG32(RADEON_CRTC2_GEN_CNTL,
-                       (crtc2_gen_cntl &
-                        ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
-                       RADEON_CRTC2_DISP_REQ_EN_B);
-        }
-
-        udelay(500);
-}
-
-void r100_mc_setup(struct radeon_device *rdev)
-{
-        uint32_t tmp;
-        int r;
-
-        r = r100_debugfs_mc_info_init(rdev);
-        if (r) {
-                DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
-        }
-        /* Write VRAM size in case we are limiting it */
-        WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
-        /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM,
-         * if the aperture is 64MB but we have 32MB VRAM
-         * we report only 32MB VRAM but we have to set MC_FB_LOCATION
-         * to 64MB, otherwise the gpu accidentially dies */
-        tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
-        tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
-        tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
-        WREG32(RADEON_MC_FB_LOCATION, tmp);
-
-        /* Enable bus mastering */
-        tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
-        WREG32(RADEON_BUS_CNTL, tmp);
-
-        if (rdev->flags & RADEON_IS_AGP) {
-                tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
-                tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
-                tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
-                WREG32(RADEON_MC_AGP_LOCATION, tmp);
-                WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
-        } else {
-                WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
-                WREG32(RADEON_AGP_BASE, 0);
-        }
-
-        tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
-        tmp |= (7 << 28);
-        WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
-        (void)RREG32(RADEON_HOST_PATH_CNTL);
-        WREG32(RADEON_HOST_PATH_CNTL, tmp);
-        (void)RREG32(RADEON_HOST_PATH_CNTL);
-}
-
-int r100_mc_init(struct radeon_device *rdev)
-{
-        int r;
-
-        if (r100_debugfs_rbbm_init(rdev)) {
-                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
-        }
-
-        r100_gpu_init(rdev);
-        /* Disable gart which also disable out of gart access */
-        r100_pci_gart_disable(rdev);
-
-        /* Setup GPU memory space */
-        rdev->mc.gtt_location = 0xFFFFFFFFUL;
-        if (rdev->flags & RADEON_IS_AGP) {
-                r = radeon_agp_init(rdev);
-                if (r) {
-                        printk(KERN_WARNING "[drm] Disabling AGP\n");
-                        rdev->flags &= ~RADEON_IS_AGP;
-                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
-                } else {
-                        rdev->mc.gtt_location = rdev->mc.agp_base;
-                }
-        }
-        r = radeon_mc_setup(rdev);
-        if (r) {
-                return r;
-        }
-
-        r100_mc_disable_clients(rdev);
-        if (r100_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "Failed to wait MC idle while "
-                       "programming pipes. Bad things might happen.\n");
-        }
-
-        r100_mc_setup(rdev);
-        return 0;
-}
-
-void r100_mc_fini(struct radeon_device *rdev)
-{
-}
-
-
-/*
- * Interrupts
- */
 int r100_irq_set(struct radeon_device *rdev)
 {
         uint32_t tmp = 0;
@@ -358,10 +220,6 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 }
 
-
-/*
- * Fence emission
- */
 void r100_fence_ring_emit(struct radeon_device *rdev,
                           struct radeon_fence *fence)
 {
@@ -377,10 +235,6 @@ void r100_fence_ring_emit(struct radeon_device *rdev,
         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 }
 
-
-/*
- * Writeback
- */
 int r100_wb_init(struct radeon_device *rdev)
 {
         int r;
@@ -504,10 +358,6 @@ int r100_copy_blit(struct radeon_device *rdev,
         return r;
 }
 
-
-/*
- * CP
- */
 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 {
         unsigned i;
@@ -612,6 +462,7 @@ static int r100_cp_init_microcode(struct radeon_device *rdev)
         }
         return err;
 }
+
 static void r100_cp_load_microcode(struct radeon_device *rdev)
 {
         const __be32 *fw_data;
@@ -978,7 +829,7 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
 
         header = radeon_get_ib_value(p, h_idx);
         crtc_id = radeon_get_ib_value(p, h_idx + 5);
-        reg = header >> 2;
+        reg = CP_PACKET0_GET_REG(header);
         mutex_lock(&p->rdev->ddev->mode_config.mutex);
         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
         if (!obj) {
@@ -1990,7 +1841,7 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
         r100_pll_errata_after_data(rdev);
 }
 
-int r100_init(struct radeon_device *rdev)
+void r100_set_safe_registers(struct radeon_device *rdev)
 {
         if (ASIC_IS_RN50(rdev)) {
                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
@@ -1999,9 +1850,8 @@ int r100_init(struct radeon_device *rdev)
                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
         } else {
-                return r200_init(rdev);
+                r200_set_safe_registers(rdev);
         }
-        return 0;
 }
 
 /*
@@ -2299,9 +2149,11 @@ void r100_bandwidth_update(struct radeon_device *rdev)
                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
         }
-        if (rdev->mode_info.crtcs[1]->base.enabled) {
-                mode2 = &rdev->mode_info.crtcs[1]->base.mode;
-                pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
+        if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+                if (rdev->mode_info.crtcs[1]->base.enabled) {
+                        mode2 = &rdev->mode_info.crtcs[1]->base.mode;
+                        pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
+                }
         }
 
         min_mem_eff.full = rfixed_const_8(0);
@@ -3114,7 +2966,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
         WREG32(R_000740_CP_CSQ_CNTL, 0);
 
         /* Save few CRTC registers */
-        save->GENMO_WT = RREG32(R_0003C0_GENMO_WT);
+        save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
@@ -3124,7 +2976,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
         }
 
         /* Disable VGA aperture access */
-        WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT);
+        WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
         /* Disable cursor, overlay, crtc */
         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
@@ -3156,10 +3008,264 @@ void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
                                 rdev->mc.vram_location);
         }
         /* Restore CRTC registers */
-        WREG32(R_0003C0_GENMO_WT, save->GENMO_WT);
+        WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
         }
 }
+
+void r100_vga_render_disable(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        tmp = RREG8(R_0003C2_GENMO_WT);
+        WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
+}
+
+static void r100_debugfs(struct radeon_device *rdev)
+{
+        int r;
+
+        r = r100_debugfs_mc_info_init(rdev);
+        if (r)
+                dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
+}
+
+static void r100_mc_program(struct radeon_device *rdev)
+{
+        struct r100_mc_save save;
+
+        /* Stops all mc clients */
+        r100_mc_stop(rdev, &save);
+        if (rdev->flags & RADEON_IS_AGP) {
+                WREG32(R_00014C_MC_AGP_LOCATION,
+                        S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
+                        S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
+                WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
+                if (rdev->family > CHIP_RV200)
+                        WREG32(R_00015C_AGP_BASE_2,
+                                upper_32_bits(rdev->mc.agp_base) & 0xff);
+        } else {
+                WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
+                WREG32(R_000170_AGP_BASE, 0);
+                if (rdev->family > CHIP_RV200)
+                        WREG32(R_00015C_AGP_BASE_2, 0);
+        }
+        /* Wait for mc idle */
+        if (r100_mc_wait_for_idle(rdev))
+                dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
+        /* Program MC, should be a 32bits limited address space */
+        WREG32(R_000148_MC_FB_LOCATION,
+                S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
+                S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
+        r100_mc_resume(rdev, &save);
+}
+
+void r100_clock_startup(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        if (radeon_dynclks != -1 && radeon_dynclks)
+                radeon_legacy_set_clock_gating(rdev, 1);
+        /* We need to force on some of the block */
+        tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
+        tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
+        if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
+                tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
+        WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
+}
+
+static int r100_startup(struct radeon_device *rdev)
+{
+        int r;
+
+        r100_mc_program(rdev);
+        /* Resume clock */
+        r100_clock_startup(rdev);
+        /* Initialize GPU configuration (# pipes, ...) */
+        r100_gpu_init(rdev);
+        /* Initialize GART (initialize after TTM so we can allocate
+         * memory through TTM but finalize after TTM) */
+        if (rdev->flags & RADEON_IS_PCI) {
+                r = r100_pci_gart_enable(rdev);
+                if (r)
+                        return r;
+        }
+        /* Enable IRQ */
+        rdev->irq.sw_int = true;
+        r100_irq_set(rdev);
+        /* 1M ring buffer */
+        r = r100_cp_init(rdev, 1024 * 1024);
+        if (r) {
+                dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
+                return r;
+        }
+        r = r100_wb_init(rdev);
+        if (r)
+                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
+        r = r100_ib_init(rdev);
+        if (r) {
+                dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
+                return r;
+        }
+        return 0;
+}
+
+int r100_resume(struct radeon_device *rdev)
+{
+        /* Make sur GART are not working */
+        if (rdev->flags & RADEON_IS_PCI)
+                r100_pci_gart_disable(rdev);
+        /* Resume clock before doing reset */
+        r100_clock_startup(rdev);
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* post */
+        radeon_combios_asic_init(rdev->ddev);
+        /* Resume clock after posting */
+        r100_clock_startup(rdev);
+        return r100_startup(rdev);
+}
+
+int r100_suspend(struct radeon_device *rdev)
+{
+        r100_cp_disable(rdev);
+        r100_wb_disable(rdev);
+        r100_irq_disable(rdev);
+        if (rdev->flags & RADEON_IS_PCI)
+                r100_pci_gart_disable(rdev);
+        return 0;
+}
+
+void r100_fini(struct radeon_device *rdev)
+{
+        r100_suspend(rdev);
+        r100_cp_fini(rdev);
+        r100_wb_fini(rdev);
+        r100_ib_fini(rdev);
+        radeon_gem_fini(rdev);
+        if (rdev->flags & RADEON_IS_PCI)
+                r100_pci_gart_fini(rdev);
+        radeon_irq_kms_fini(rdev);
+        radeon_fence_driver_fini(rdev);
+        radeon_object_fini(rdev);
+        radeon_atombios_fini(rdev);
+        kfree(rdev->bios);
+        rdev->bios = NULL;
+}
+
+int r100_mc_init(struct radeon_device *rdev)
+{
+        int r;
+        u32 tmp;
+
+        /* Setup GPU memory space */
+        rdev->mc.vram_location = 0xFFFFFFFFUL;
+        rdev->mc.gtt_location = 0xFFFFFFFFUL;
+        if (rdev->flags & RADEON_IS_IGP) {
+                tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
+                rdev->mc.vram_location = tmp << 16;
+        }
+        if (rdev->flags & RADEON_IS_AGP) {
+                r = radeon_agp_init(rdev);
+                if (r) {
+                        printk(KERN_WARNING "[drm] Disabling AGP\n");
+                        rdev->flags &= ~RADEON_IS_AGP;
+                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+                } else {
+                        rdev->mc.gtt_location = rdev->mc.agp_base;
+                }
+        }
+        r = radeon_mc_setup(rdev);
+        if (r)
+                return r;
+        return 0;
+}
+
+int r100_init(struct radeon_device *rdev)
+{
+        int r;
+
+        /* Register debugfs file specific to this group of asics */
+        r100_debugfs(rdev);
+        /* Disable VGA */
+        r100_vga_render_disable(rdev);
+        /* Initialize scratch registers */
+        radeon_scratch_init(rdev);
+        /* Initialize surface registers */
+        radeon_surface_init(rdev);
+        /* TODO: disable VGA need to use VGA request */
+        /* BIOS*/
+        if (!radeon_get_bios(rdev)) {
+                if (ASIC_IS_AVIVO(rdev))
+                        return -EINVAL;
+        }
+        if (rdev->is_atom_bios) {
+                dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
+                return -EINVAL;
+        } else {
+                r = radeon_combios_init(rdev);
+                if (r)
+                        return r;
+        }
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev,
+                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* check if cards are posted or not */
+        if (!radeon_card_posted(rdev) && rdev->bios) {
+                DRM_INFO("GPU not posted. posting now...\n");
+                radeon_combios_asic_init(rdev->ddev);
+        }
+        /* Set asic errata */
+        r100_errata(rdev);
+        /* Initialize clocks */
+        radeon_get_clock_info(rdev->ddev);
+        /* Get vram informations */
+        r100_vram_info(rdev);
+        /* Initialize memory controller (also test AGP) */
+        r = r100_mc_init(rdev);
+        if (r)
+                return r;
+        /* Fence driver */
+        r = radeon_fence_driver_init(rdev);
+        if (r)
+                return r;
+        r = radeon_irq_kms_init(rdev);
+        if (r)
+                return r;
+        /* Memory manager */
+        r = radeon_object_init(rdev);
+        if (r)
+                return r;
+        if (rdev->flags & RADEON_IS_PCI) {
+                r = r100_pci_gart_init(rdev);
+                if (r)
+                        return r;
+        }
+        r100_set_safe_registers(rdev);
+        rdev->accel_working = true;
+        r = r100_startup(rdev);
+        if (r) {
+                /* Somethings want wront with the accel init stop accel */
+                dev_err(rdev->dev, "Disabling GPU acceleration\n");
+                r100_suspend(rdev);
+                r100_cp_fini(rdev);
+                r100_wb_fini(rdev);
+                r100_ib_fini(rdev);
+                if (rdev->flags & RADEON_IS_PCI)
+                        r100_pci_gart_fini(rdev);
+                radeon_irq_kms_fini(rdev);
+                rdev->accel_working = false;
+        }
+        return 0;
+}
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h
index c4b257ec920e..df29a630c466 100644
--- a/drivers/gpu/drm/radeon/r100d.h
+++ b/drivers/gpu/drm/radeon/r100d.h
@@ -381,6 +381,24 @@
 #define   S_000054_VCRTC_IDX_MASTER(x)                 (((x) & 0x7F) << 24)
 #define   G_000054_VCRTC_IDX_MASTER(x)                 (((x) >> 24) & 0x7F)
 #define   C_000054_VCRTC_IDX_MASTER                    0x80FFFFFF
+#define R_000148_MC_FB_LOCATION                      0x000148
+#define   S_000148_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
+#define   G_000148_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
+#define   C_000148_MC_FB_START                         0xFFFF0000
+#define   S_000148_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
+#define   G_000148_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
+#define   C_000148_MC_FB_TOP                           0x0000FFFF
+#define R_00014C_MC_AGP_LOCATION                     0x00014C
+#define   S_00014C_MC_AGP_START(x)                     (((x) & 0xFFFF) << 0)
+#define   G_00014C_MC_AGP_START(x)                     (((x) >> 0) & 0xFFFF)
+#define   C_00014C_MC_AGP_START                        0xFFFF0000
+#define   S_00014C_MC_AGP_TOP(x)                       (((x) & 0xFFFF) << 16)
+#define   G_00014C_MC_AGP_TOP(x)                       (((x) >> 16) & 0xFFFF)
+#define   C_00014C_MC_AGP_TOP                          0x0000FFFF
+#define R_000170_AGP_BASE                            0x000170
+#define   S_000170_AGP_BASE_ADDR(x)                    (((x) & 0xFFFFFFFF) << 0)
+#define   G_000170_AGP_BASE_ADDR(x)                    (((x) >> 0) & 0xFFFFFFFF)
+#define   C_000170_AGP_BASE_ADDR                       0x00000000
 #define R_00023C_DISPLAY_BASE_ADDR                   0x00023C
 #define   S_00023C_DISPLAY_BASE_ADDR(x)                (((x) & 0xFFFFFFFF) << 0)
 #define   G_00023C_DISPLAY_BASE_ADDR(x)                (((x) >> 0) & 0xFFFFFFFF)
@@ -403,25 +421,25 @@
 #define   S_000360_CUR2_LOCK(x)                        (((x) & 0x1) << 31)
 #define   G_000360_CUR2_LOCK(x)                        (((x) >> 31) & 0x1)
 #define   C_000360_CUR2_LOCK                           0x7FFFFFFF
-#define R_0003C0_GENMO_WT                            0x0003C0
-#define   S_0003C0_GENMO_MONO_ADDRESS_B(x)             (((x) & 0x1) << 0)
-#define   G_0003C0_GENMO_MONO_ADDRESS_B(x)             (((x) >> 0) & 0x1)
-#define   C_0003C0_GENMO_MONO_ADDRESS_B                0xFFFFFFFE
-#define   S_0003C0_VGA_RAM_EN(x)                       (((x) & 0x1) << 1)
-#define   G_0003C0_VGA_RAM_EN(x)                       (((x) >> 1) & 0x1)
-#define   C_0003C0_VGA_RAM_EN                          0xFFFFFFFD
-#define   S_0003C0_VGA_CKSEL(x)                        (((x) & 0x3) << 2)
-#define   G_0003C0_VGA_CKSEL(x)                        (((x) >> 2) & 0x3)
-#define   C_0003C0_VGA_CKSEL                           0xFFFFFFF3
-#define   S_0003C0_ODD_EVEN_MD_PGSEL(x)                (((x) & 0x1) << 5)
-#define   G_0003C0_ODD_EVEN_MD_PGSEL(x)                (((x) >> 5) & 0x1)
-#define   C_0003C0_ODD_EVEN_MD_PGSEL                   0xFFFFFFDF
-#define   S_0003C0_VGA_HSYNC_POL(x)                    (((x) & 0x1) << 6)
-#define   G_0003C0_VGA_HSYNC_POL(x)                    (((x) >> 6) & 0x1)
-#define   C_0003C0_VGA_HSYNC_POL                       0xFFFFFFBF
-#define   S_0003C0_VGA_VSYNC_POL(x)                    (((x) & 0x1) << 7)
-#define   G_0003C0_VGA_VSYNC_POL(x)                    (((x) >> 7) & 0x1)
-#define   C_0003C0_VGA_VSYNC_POL                       0xFFFFFF7F
+#define R_0003C2_GENMO_WT                            0x0003C0
+#define   S_0003C2_GENMO_MONO_ADDRESS_B(x)             (((x) & 0x1) << 0)
+#define   G_0003C2_GENMO_MONO_ADDRESS_B(x)             (((x) >> 0) & 0x1)
+#define   C_0003C2_GENMO_MONO_ADDRESS_B                0xFE
+#define   S_0003C2_VGA_RAM_EN(x)                       (((x) & 0x1) << 1)
+#define   G_0003C2_VGA_RAM_EN(x)                       (((x) >> 1) & 0x1)
+#define   C_0003C2_VGA_RAM_EN                          0xFD
+#define   S_0003C2_VGA_CKSEL(x)                        (((x) & 0x3) << 2)
+#define   G_0003C2_VGA_CKSEL(x)                        (((x) >> 2) & 0x3)
+#define   C_0003C2_VGA_CKSEL                           0xF3
+#define   S_0003C2_ODD_EVEN_MD_PGSEL(x)                (((x) & 0x1) << 5)
+#define   G_0003C2_ODD_EVEN_MD_PGSEL(x)                (((x) >> 5) & 0x1)
+#define   C_0003C2_ODD_EVEN_MD_PGSEL                   0xDF
+#define   S_0003C2_VGA_HSYNC_POL(x)                    (((x) & 0x1) << 6)
+#define   G_0003C2_VGA_HSYNC_POL(x)                    (((x) >> 6) & 0x1)
+#define   C_0003C2_VGA_HSYNC_POL                       0xBF
+#define   S_0003C2_VGA_VSYNC_POL(x)                    (((x) & 0x1) << 7)
+#define   G_0003C2_VGA_VSYNC_POL(x)                    (((x) >> 7) & 0x1)
+#define   C_0003C2_VGA_VSYNC_POL                       0x7F
 #define R_0003F8_CRTC2_GEN_CNTL                      0x0003F8
 #define   S_0003F8_CRTC2_DBL_SCAN_EN(x)                (((x) & 0x1) << 0)
 #define   G_0003F8_CRTC2_DBL_SCAN_EN(x)                (((x) >> 0) & 0x1)
@@ -545,6 +563,46 @@
 #define   S_000774_SCRATCH_ADDR(x)                     (((x) & 0x7FFFFFF) << 5)
 #define   G_000774_SCRATCH_ADDR(x)                     (((x) >> 5) & 0x7FFFFFF)
 #define   C_000774_SCRATCH_ADDR                        0x0000001F
+#define R_0007C0_CP_STAT                             0x0007C0
+#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
+#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
+#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
+#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
+#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
+#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
+#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
+#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
+#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
+#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
+#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
+#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
+#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
+#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
+#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
+#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
+#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
+#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
+#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
+#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
+#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
+#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
+#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
+#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
+#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
+#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
+#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
+#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
+#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
+#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
+#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
+#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
+#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
+#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
+#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
+#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
+#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
+#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
+#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
 #define R_000E40_RBBM_STATUS                         0x000E40
 #define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
 #define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
@@ -604,4 +662,53 @@
 #define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
 #define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
 
+
+#define R_00000D_SCLK_CNTL                           0x00000D
+#define   S_00000D_SCLK_SRC_SEL(x)                     (((x) & 0x7) << 0)
+#define   G_00000D_SCLK_SRC_SEL(x)                     (((x) >> 0) & 0x7)
+#define   C_00000D_SCLK_SRC_SEL                        0xFFFFFFF8
+#define   S_00000D_TCLK_SRC_SEL(x)                     (((x) & 0x7) << 8)
+#define   G_00000D_TCLK_SRC_SEL(x)                     (((x) >> 8) & 0x7)
+#define   C_00000D_TCLK_SRC_SEL                        0xFFFFF8FF
+#define   S_00000D_FORCE_CP(x)                         (((x) & 0x1) << 16)
+#define   G_00000D_FORCE_CP(x)                         (((x) >> 16) & 0x1)
+#define   C_00000D_FORCE_CP                            0xFFFEFFFF
+#define   S_00000D_FORCE_HDP(x)                        (((x) & 0x1) << 17)
+#define   G_00000D_FORCE_HDP(x)                        (((x) >> 17) & 0x1)
+#define   C_00000D_FORCE_HDP                           0xFFFDFFFF
+#define   S_00000D_FORCE_DISP(x)                       (((x) & 0x1) << 18)
+#define   G_00000D_FORCE_DISP(x)                       (((x) >> 18) & 0x1)
+#define   C_00000D_FORCE_DISP                          0xFFFBFFFF
+#define   S_00000D_FORCE_TOP(x)                        (((x) & 0x1) << 19)
+#define   G_00000D_FORCE_TOP(x)                        (((x) >> 19) & 0x1)
+#define   C_00000D_FORCE_TOP                           0xFFF7FFFF
+#define   S_00000D_FORCE_E2(x)                         (((x) & 0x1) << 20)
+#define   G_00000D_FORCE_E2(x)                         (((x) >> 20) & 0x1)
+#define   C_00000D_FORCE_E2                            0xFFEFFFFF
+#define   S_00000D_FORCE_SE(x)                         (((x) & 0x1) << 21)
+#define   G_00000D_FORCE_SE(x)                         (((x) >> 21) & 0x1)
+#define   C_00000D_FORCE_SE                            0xFFDFFFFF
+#define   S_00000D_FORCE_IDCT(x)                       (((x) & 0x1) << 22)
+#define   G_00000D_FORCE_IDCT(x)                       (((x) >> 22) & 0x1)
+#define   C_00000D_FORCE_IDCT                          0xFFBFFFFF
+#define   S_00000D_FORCE_VIP(x)                        (((x) & 0x1) << 23)
+#define   G_00000D_FORCE_VIP(x)                        (((x) >> 23) & 0x1)
+#define   C_00000D_FORCE_VIP                           0xFF7FFFFF
+#define   S_00000D_FORCE_RE(x)                         (((x) & 0x1) << 24)
+#define   G_00000D_FORCE_RE(x)                         (((x) >> 24) & 0x1)
+#define   C_00000D_FORCE_RE                            0xFEFFFFFF
+#define   S_00000D_FORCE_PB(x)                         (((x) & 0x1) << 25)
+#define   G_00000D_FORCE_PB(x)                         (((x) >> 25) & 0x1)
+#define   C_00000D_FORCE_PB                            0xFDFFFFFF
+#define   S_00000D_FORCE_TAM(x)                        (((x) & 0x1) << 26)
+#define   G_00000D_FORCE_TAM(x)                        (((x) >> 26) & 0x1)
+#define   C_00000D_FORCE_TAM                           0xFBFFFFFF
+#define   S_00000D_FORCE_TDM(x)                        (((x) & 0x1) << 27)
+#define   G_00000D_FORCE_TDM(x)                        (((x) >> 27) & 0x1)
+#define   C_00000D_FORCE_TDM                           0xF7FFFFFF
+#define   S_00000D_FORCE_RB(x)                         (((x) & 0x1) << 28)
+#define   G_00000D_FORCE_RB(x)                         (((x) >> 28) & 0x1)
+#define   C_00000D_FORCE_RB                            0xEFFFFFFF
+
+
 #endif
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index cf7fea5ff2e5..eb740fc3549f 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -447,9 +447,8 @@ int r200_packet0_check(struct radeon_cs_parser *p,
         return 0;
 }
 
-int r200_init(struct radeon_device *rdev)
+void r200_set_safe_registers(struct radeon_device *rdev)
 {
         rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
         rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);
-        return 0;
 }
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 1ebea8cc8c93..e08c4a8974ca 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -33,43 +33,16 @@
 #include "radeon_drm.h"
 #include "r100_track.h"
 #include "r300d.h"
-
+#include "rv350d.h"
 #include "r300_reg_safe.h"
 
-/* r300,r350,rv350,rv370,rv380 depends on : */
-void r100_hdp_reset(struct radeon_device *rdev);
-int r100_cp_reset(struct radeon_device *rdev);
-int r100_rb2d_reset(struct radeon_device *rdev);
-int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
-int r100_pci_gart_enable(struct radeon_device *rdev);
-void r100_mc_setup(struct radeon_device *rdev);
-void r100_mc_disable_clients(struct radeon_device *rdev);
-int r100_gui_wait_for_idle(struct radeon_device *rdev);
-int r100_cs_packet_parse(struct radeon_cs_parser *p,
-                         struct radeon_cs_packet *pkt,
-                         unsigned idx);
-int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
-int r100_cs_parse_packet0(struct radeon_cs_parser *p,
-                          struct radeon_cs_packet *pkt,
-                          const unsigned *auth, unsigned n,
-                          radeon_packet0_check_t check);
-int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
-                                         struct radeon_cs_packet *pkt,
-                                         struct radeon_object *robj);
-
-/* This files gather functions specifics to:
- * r300,r350,rv350,rv370,rv380
- *
- * Some of these functions might be used by newer ASICs.
- */
-void r300_gpu_init(struct radeon_device *rdev);
-int r300_mc_wait_for_idle(struct radeon_device *rdev);
-int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
-
+/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
 
 /*
  * rv370,rv380 PCIE GART
  */
+static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
+
 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
 {
         uint32_t tmp;
@@ -182,59 +155,6 @@ void rv370_pcie_gart_fini(struct radeon_device *rdev)
         radeon_gart_fini(rdev);
 }
 
-/*
- * MC
- */
-int r300_mc_init(struct radeon_device *rdev)
-{
-        int r;
-
-        if (r100_debugfs_rbbm_init(rdev)) {
-                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
-        }
-
-        r300_gpu_init(rdev);
-        r100_pci_gart_disable(rdev);
-        if (rdev->flags & RADEON_IS_PCIE) {
-                rv370_pcie_gart_disable(rdev);
-        }
-
-        /* Setup GPU memory space */
-        rdev->mc.vram_location = 0xFFFFFFFFUL;
-        rdev->mc.gtt_location = 0xFFFFFFFFUL;
-        if (rdev->flags & RADEON_IS_AGP) {
-                r = radeon_agp_init(rdev);
-                if (r) {
-                        printk(KERN_WARNING "[drm] Disabling AGP\n");
-                        rdev->flags &= ~RADEON_IS_AGP;
-                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
-                } else {
-                        rdev->mc.gtt_location = rdev->mc.agp_base;
-                }
-        }
-        r = radeon_mc_setup(rdev);
-        if (r) {
-                return r;
-        }
-
-        /* Program GPU memory space */
-        r100_mc_disable_clients(rdev);
-        if (r300_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "Failed to wait MC idle while "
-                       "programming pipes. Bad things might happen.\n");
-        }
-        r100_mc_setup(rdev);
-        return 0;
-}
-
-void r300_mc_fini(struct radeon_device *rdev)
-{
-}
-
-
-/*
- * Fence emission
- */
 void r300_fence_ring_emit(struct radeon_device *rdev,
                           struct radeon_fence *fence)
 {
@@ -260,10 +180,6 @@ void r300_fence_ring_emit(struct radeon_device *rdev,
         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 }
 
-
-/*
- * Global GPU functions
- */
 int r300_copy_dma(struct radeon_device *rdev,
                   uint64_t src_offset,
                   uint64_t dst_offset,
@@ -582,11 +498,6 @@ void r300_vram_info(struct radeon_device *rdev)
         r100_vram_init_sizes(rdev);
 }
 
-
-/*
- * PCIE Lanes
- */
-
 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
 {
         uint32_t link_width_cntl, mask;
@@ -646,10 +557,6 @@ void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
 
 }
 
-
-/*
- * Debugfs info
- */
 #if defined(CONFIG_DEBUG_FS)
 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
 {
@@ -680,7 +587,7 @@ static struct drm_info_list rv370_pcie_gart_info_list[] = {
 };
 #endif
 
-int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
+static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 {
 #if defined(CONFIG_DEBUG_FS)
         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
@@ -689,10 +596,6 @@ int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 #endif
 }
 
-
-/*
- * CS functions
- */
 static int r300_packet0_check(struct radeon_cs_parser *p,
                 struct radeon_cs_packet *pkt,
                 unsigned idx, unsigned reg)
@@ -1226,12 +1129,6 @@ void r300_set_reg_safe(struct radeon_device *rdev)
         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
 }
 
-int r300_init(struct radeon_device *rdev)
-{
-        r300_set_reg_safe(rdev);
-        return 0;
-}
-
 void r300_mc_program(struct radeon_device *rdev)
 {
         struct r100_mc_save save;
@@ -1265,3 +1162,198 @@ void r300_mc_program(struct radeon_device *rdev)
                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
         r100_mc_resume(rdev, &save);
 }
+
+void r300_clock_startup(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        if (radeon_dynclks != -1 && radeon_dynclks)
+                radeon_legacy_set_clock_gating(rdev, 1);
+        /* We need to force on some of the block */
+        tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
+        tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
+        if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
+                tmp |= S_00000D_FORCE_VAP(1);
+        WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
+}
+
+static int r300_startup(struct radeon_device *rdev)
+{
+        int r;
+
+        r300_mc_program(rdev);
+        /* Resume clock */
+        r300_clock_startup(rdev);
+        /* Initialize GPU configuration (# pipes, ...) */
+        r300_gpu_init(rdev);
+        /* Initialize GART (initialize after TTM so we can allocate
+         * memory through TTM but finalize after TTM) */
+        if (rdev->flags & RADEON_IS_PCIE) {
+                r = rv370_pcie_gart_enable(rdev);
+                if (r)
+                        return r;
+        }
+        if (rdev->flags & RADEON_IS_PCI) {
+                r = r100_pci_gart_enable(rdev);
+                if (r)
+                        return r;
+        }
+        /* Enable IRQ */
+        rdev->irq.sw_int = true;
+        r100_irq_set(rdev);
+        /* 1M ring buffer */
+        r = r100_cp_init(rdev, 1024 * 1024);
+        if (r) {
+                dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
+                return r;
+        }
+        r = r100_wb_init(rdev);
+        if (r)
+                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
+        r = r100_ib_init(rdev);
+        if (r) {
+                dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
+                return r;
+        }
+        return 0;
+}
+
+int r300_resume(struct radeon_device *rdev)
+{
+        /* Make sur GART are not working */
+        if (rdev->flags & RADEON_IS_PCIE)
+                rv370_pcie_gart_disable(rdev);
+        if (rdev->flags & RADEON_IS_PCI)
+                r100_pci_gart_disable(rdev);
+        /* Resume clock before doing reset */
+        r300_clock_startup(rdev);
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* post */
+        radeon_combios_asic_init(rdev->ddev);
+        /* Resume clock after posting */
+        r300_clock_startup(rdev);
+        return r300_startup(rdev);
+}
+
+int r300_suspend(struct radeon_device *rdev)
+{
+        r100_cp_disable(rdev);
+        r100_wb_disable(rdev);
+        r100_irq_disable(rdev);
+        if (rdev->flags & RADEON_IS_PCIE)
+                rv370_pcie_gart_disable(rdev);
+        if (rdev->flags & RADEON_IS_PCI)
+                r100_pci_gart_disable(rdev);
+        return 0;
+}
+
+void r300_fini(struct radeon_device *rdev)
+{
+        r300_suspend(rdev);
+        r100_cp_fini(rdev);
+        r100_wb_fini(rdev);
+        r100_ib_fini(rdev);
+        radeon_gem_fini(rdev);
+        if (rdev->flags & RADEON_IS_PCIE)
+                rv370_pcie_gart_fini(rdev);
+        if (rdev->flags & RADEON_IS_PCI)
+                r100_pci_gart_fini(rdev);
+        radeon_irq_kms_fini(rdev);
+        radeon_fence_driver_fini(rdev);
+        radeon_object_fini(rdev);
+        radeon_atombios_fini(rdev);
+        kfree(rdev->bios);
+        rdev->bios = NULL;
+}
+
+int r300_init(struct radeon_device *rdev)
+{
+        int r;
+
+        /* Disable VGA */
+        r100_vga_render_disable(rdev);
+        /* Initialize scratch registers */
+        radeon_scratch_init(rdev);
+        /* Initialize surface registers */
+        radeon_surface_init(rdev);
+        /* TODO: disable VGA need to use VGA request */
+        /* BIOS*/
+        if (!radeon_get_bios(rdev)) {
+                if (ASIC_IS_AVIVO(rdev))
+                        return -EINVAL;
+        }
+        if (rdev->is_atom_bios) {
+                dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
+                return -EINVAL;
+        } else {
+                r = radeon_combios_init(rdev);
+                if (r)
+                        return r;
+        }
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev,
+                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* check if cards are posted or not */
+        if (!radeon_card_posted(rdev) && rdev->bios) {
+                DRM_INFO("GPU not posted. posting now...\n");
+                radeon_combios_asic_init(rdev->ddev);
+        }
+        /* Set asic errata */
+        r300_errata(rdev);
+        /* Initialize clocks */
+        radeon_get_clock_info(rdev->ddev);
+        /* Get vram informations */
+        r300_vram_info(rdev);
+        /* Initialize memory controller (also test AGP) */
+        r = r420_mc_init(rdev);
+        if (r)
+                return r;
+        /* Fence driver */
+        r = radeon_fence_driver_init(rdev);
+        if (r)
+                return r;
+        r = radeon_irq_kms_init(rdev);
+        if (r)
+                return r;
+        /* Memory manager */
+        r = radeon_object_init(rdev);
+        if (r)
+                return r;
+        if (rdev->flags & RADEON_IS_PCIE) {
+                r = rv370_pcie_gart_init(rdev);
+                if (r)
+                        return r;
+        }
+        if (rdev->flags & RADEON_IS_PCI) {
+                r = r100_pci_gart_init(rdev);
+                if (r)
+                        return r;
+        }
+        r300_set_reg_safe(rdev);
+        rdev->accel_working = true;
+        r = r300_startup(rdev);
+        if (r) {
+                /* Somethings want wront with the accel init stop accel */
+                dev_err(rdev->dev, "Disabling GPU acceleration\n");
+                r300_suspend(rdev);
+                r100_cp_fini(rdev);
+                r100_wb_fini(rdev);
+                r100_ib_fini(rdev);
+                if (rdev->flags & RADEON_IS_PCIE)
+                        rv370_pcie_gart_fini(rdev);
+                if (rdev->flags & RADEON_IS_PCI)
+                        r100_pci_gart_fini(rdev);
+                radeon_irq_kms_fini(rdev);
+                rdev->accel_working = false;
+        }
+        return 0;
+}
diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h
index d4fa3eb1074f..4c73114f0de9 100644
--- a/drivers/gpu/drm/radeon/r300d.h
+++ b/drivers/gpu/drm/radeon/r300d.h
@@ -96,6 +96,211 @@
 #define   S_000170_AGP_BASE_ADDR(x)                    (((x) & 0xFFFFFFFF) << 0)
 #define   G_000170_AGP_BASE_ADDR(x)                    (((x) >> 0) & 0xFFFFFFFF)
 #define   C_000170_AGP_BASE_ADDR                       0x00000000
+#define R_0007C0_CP_STAT                             0x0007C0
+#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
+#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
+#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
+#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
+#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
+#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
+#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
+#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
+#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
+#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
+#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
+#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
+#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
+#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
+#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
+#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
+#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
+#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
+#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
+#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
+#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
+#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
+#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
+#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
+#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
+#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
+#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
+#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
+#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
+#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
+#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
+#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
+#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
+#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
+#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
+#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
+#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
+#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
+#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
+#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
+#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
+#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
+#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
+#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
+#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
+#define R_000E40_RBBM_STATUS                         0x000E40
+#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
+#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
+#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
+#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
+#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
+#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
+#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
+#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
+#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
+#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
+#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
+#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
+#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
+#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
+#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
+#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
+#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
+#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
+#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
+#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
+#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
+#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
+#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
+#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
+#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
+#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
+#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
+#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
+#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
+#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
+#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
+#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
+#define   C_000E40_E2_BUSY                             0xFFFDFFFF
+#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
+#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
+#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
+#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
+#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
+#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
+#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
+#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
+#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
+#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
+#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
+#define   C_000E40_RE_BUSY                             0xFFDFFFFF
+#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
+#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
+#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
+#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
+#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
+#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
+#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
+#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
+#define   C_000E40_PB_BUSY                             0xFEFFFFFF
+#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
+#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
+#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
+#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
+#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
+#define   C_000E40_GA_BUSY                             0xFBFFFFFF
+#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
+#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
+#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
+#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
+#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
+#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
 
 
+#define R_00000D_SCLK_CNTL                           0x00000D
+#define   S_00000D_SCLK_SRC_SEL(x)                     (((x) & 0x7) << 0)
+#define   G_00000D_SCLK_SRC_SEL(x)                     (((x) >> 0) & 0x7)
+#define   C_00000D_SCLK_SRC_SEL                        0xFFFFFFF8
+#define   S_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 3)
+#define   G_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) >> 3) & 0x1)
+#define   C_00000D_CP_MAX_DYN_STOP_LAT                 0xFFFFFFF7
+#define   S_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 4)
+#define   G_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) >> 4) & 0x1)
+#define   C_00000D_HDP_MAX_DYN_STOP_LAT                0xFFFFFFEF
+#define   S_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 5)
+#define   G_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) >> 5) & 0x1)
+#define   C_00000D_TV_MAX_DYN_STOP_LAT                 0xFFFFFFDF
+#define   S_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 6)
+#define   G_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) >> 6) & 0x1)
+#define   C_00000D_E2_MAX_DYN_STOP_LAT                 0xFFFFFFBF
+#define   S_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 7)
+#define   G_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) >> 7) & 0x1)
+#define   C_00000D_SE_MAX_DYN_STOP_LAT                 0xFFFFFF7F
+#define   S_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) & 0x1) << 8)
+#define   G_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) >> 8) & 0x1)
+#define   C_00000D_IDCT_MAX_DYN_STOP_LAT               0xFFFFFEFF
+#define   S_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 9)
+#define   G_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) >> 9) & 0x1)
+#define   C_00000D_VIP_MAX_DYN_STOP_LAT                0xFFFFFDFF
+#define   S_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 10)
+#define   G_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) >> 10) & 0x1)
+#define   C_00000D_RE_MAX_DYN_STOP_LAT                 0xFFFFFBFF
+#define   S_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 11)
+#define   G_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) >> 11) & 0x1)
+#define   C_00000D_PB_MAX_DYN_STOP_LAT                 0xFFFFF7FF
+#define   S_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 12)
+#define   G_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) >> 12) & 0x1)
+#define   C_00000D_TAM_MAX_DYN_STOP_LAT                0xFFFFEFFF
+#define   S_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 13)
+#define   G_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) >> 13) & 0x1)
+#define   C_00000D_TDM_MAX_DYN_STOP_LAT                0xFFFFDFFF
+#define   S_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 14)
+#define   G_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) >> 14) & 0x1)
+#define   C_00000D_RB_MAX_DYN_STOP_LAT                 0xFFFFBFFF
+#define   S_00000D_FORCE_DISP2(x)                      (((x) & 0x1) << 15)
+#define   G_00000D_FORCE_DISP2(x)                      (((x) >> 15) & 0x1)
+#define   C_00000D_FORCE_DISP2                         0xFFFF7FFF
+#define   S_00000D_FORCE_CP(x)                         (((x) & 0x1) << 16)
+#define   G_00000D_FORCE_CP(x)                         (((x) >> 16) & 0x1)
+#define   C_00000D_FORCE_CP                            0xFFFEFFFF
+#define   S_00000D_FORCE_HDP(x)                        (((x) & 0x1) << 17)
+#define   G_00000D_FORCE_HDP(x)                        (((x) >> 17) & 0x1)
+#define   C_00000D_FORCE_HDP                           0xFFFDFFFF
+#define   S_00000D_FORCE_DISP1(x)                      (((x) & 0x1) << 18)
+#define   G_00000D_FORCE_DISP1(x)                      (((x) >> 18) & 0x1)
+#define   C_00000D_FORCE_DISP1                         0xFFFBFFFF
+#define   S_00000D_FORCE_TOP(x)                        (((x) & 0x1) << 19)
+#define   G_00000D_FORCE_TOP(x)                        (((x) >> 19) & 0x1)
+#define   C_00000D_FORCE_TOP                           0xFFF7FFFF
+#define   S_00000D_FORCE_E2(x)                         (((x) & 0x1) << 20)
+#define   G_00000D_FORCE_E2(x)                         (((x) >> 20) & 0x1)
+#define   C_00000D_FORCE_E2                            0xFFEFFFFF
+#define   S_00000D_FORCE_SE(x)                         (((x) & 0x1) << 21)
+#define   G_00000D_FORCE_SE(x)                         (((x) >> 21) & 0x1)
+#define   C_00000D_FORCE_SE                            0xFFDFFFFF
+#define   S_00000D_FORCE_IDCT(x)                       (((x) & 0x1) << 22)
+#define   G_00000D_FORCE_IDCT(x)                       (((x) >> 22) & 0x1)
+#define   C_00000D_FORCE_IDCT                          0xFFBFFFFF
+#define   S_00000D_FORCE_VIP(x)                        (((x) & 0x1) << 23)
+#define   G_00000D_FORCE_VIP(x)                        (((x) >> 23) & 0x1)
+#define   C_00000D_FORCE_VIP                           0xFF7FFFFF
+#define   S_00000D_FORCE_RE(x)                         (((x) & 0x1) << 24)
+#define   G_00000D_FORCE_RE(x)                         (((x) >> 24) & 0x1)
+#define   C_00000D_FORCE_RE                            0xFEFFFFFF
+#define   S_00000D_FORCE_PB(x)                         (((x) & 0x1) << 25)
+#define   G_00000D_FORCE_PB(x)                         (((x) >> 25) & 0x1)
+#define   C_00000D_FORCE_PB                            0xFDFFFFFF
+#define   S_00000D_FORCE_TAM(x)                        (((x) & 0x1) << 26)
+#define   G_00000D_FORCE_TAM(x)                        (((x) >> 26) & 0x1)
+#define   C_00000D_FORCE_TAM                           0xFBFFFFFF
+#define   S_00000D_FORCE_TDM(x)                        (((x) & 0x1) << 27)
+#define   G_00000D_FORCE_TDM(x)                        (((x) >> 27) & 0x1)
+#define   C_00000D_FORCE_TDM                           0xF7FFFFFF
+#define   S_00000D_FORCE_RB(x)                         (((x) & 0x1) << 28)
+#define   G_00000D_FORCE_RB(x)                         (((x) >> 28) & 0x1)
+#define   C_00000D_FORCE_RB                            0xEFFFFFFF
+#define   S_00000D_FORCE_TV_SCLK(x)                    (((x) & 0x1) << 29)
+#define   G_00000D_FORCE_TV_SCLK(x)                    (((x) >> 29) & 0x1)
+#define   C_00000D_FORCE_TV_SCLK                       0xDFFFFFFF
+#define   S_00000D_FORCE_SUBPIC(x)                     (((x) & 0x1) << 30)
+#define   G_00000D_FORCE_SUBPIC(x)                     (((x) >> 30) & 0x1)
+#define   C_00000D_FORCE_SUBPIC                        0xBFFFFFFF
+#define   S_00000D_FORCE_OV0(x)                        (((x) & 0x1) << 31)
+#define   G_00000D_FORCE_OV0(x)                        (((x) >> 31) & 0x1)
+#define   C_00000D_FORCE_OV0                           0x7FFFFFFF
+
 #endif
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 49a2fdc57d27..5c7fe52de30e 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -155,6 +155,9 @@ static void r420_debugfs(struct radeon_device *rdev)
 static void r420_clock_resume(struct radeon_device *rdev)
 {
         u32 sclk_cntl;
+
+        if (radeon_dynclks != -1 && radeon_dynclks)
+                radeon_atom_set_clock_gating(rdev, 1);
         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
         if (rdev->family == CHIP_R420)
@@ -167,6 +170,8 @@ static int r420_startup(struct radeon_device *rdev)
         int r;
 
         r300_mc_program(rdev);
+        /* Resume clock */
+        r420_clock_resume(rdev);
         /* Initialize GART (initialize after TTM so we can allocate
          * memory through TTM but finalize after TTM) */
         if (rdev->flags & RADEON_IS_PCIE) {
@@ -267,7 +272,6 @@ int r420_init(struct radeon_device *rdev)
 {
         int r;
 
-        rdev->new_init_path = true;
         /* Initialize scratch registers */
         radeon_scratch_init(rdev);
         /* Initialize surface registers */
diff --git a/drivers/gpu/drm/radeon/r420d.h b/drivers/gpu/drm/radeon/r420d.h
index a48a7db1e2aa..fc78d31a0b4a 100644
--- a/drivers/gpu/drm/radeon/r420d.h
+++ b/drivers/gpu/drm/radeon/r420d.h
@@ -212,9 +212,9 @@
 #define   S_00000D_FORCE_E2(x)                         (((x) & 0x1) << 20)
 #define   G_00000D_FORCE_E2(x)                         (((x) >> 20) & 0x1)
 #define   C_00000D_FORCE_E2                            0xFFEFFFFF
-#define   S_00000D_FORCE_SE(x)                         (((x) & 0x1) << 21)
-#define   G_00000D_FORCE_SE(x)                         (((x) >> 21) & 0x1)
-#define   C_00000D_FORCE_SE                            0xFFDFFFFF
+#define   S_00000D_FORCE_VAP(x)                        (((x) & 0x1) << 21)
+#define   G_00000D_FORCE_VAP(x)                        (((x) >> 21) & 0x1)
+#define   C_00000D_FORCE_VAP                           0xFFDFFFFF
 #define   S_00000D_FORCE_IDCT(x)                       (((x) & 0x1) << 22)
 #define   G_00000D_FORCE_IDCT(x)                       (((x) >> 22) & 0x1)
 #define   C_00000D_FORCE_IDCT                          0xFFBFFFFF
@@ -224,24 +224,24 @@
 #define   S_00000D_FORCE_RE(x)                         (((x) & 0x1) << 24)
 #define   G_00000D_FORCE_RE(x)                         (((x) >> 24) & 0x1)
 #define   C_00000D_FORCE_RE                            0xFEFFFFFF
-#define   S_00000D_FORCE_PB(x)                         (((x) & 0x1) << 25)
-#define   G_00000D_FORCE_PB(x)                         (((x) >> 25) & 0x1)
-#define   C_00000D_FORCE_PB                            0xFDFFFFFF
+#define   S_00000D_FORCE_SR(x)                         (((x) & 0x1) << 25)
+#define   G_00000D_FORCE_SR(x)                         (((x) >> 25) & 0x1)
+#define   C_00000D_FORCE_SR                            0xFDFFFFFF
 #define   S_00000D_FORCE_PX(x)                         (((x) & 0x1) << 26)
 #define   G_00000D_FORCE_PX(x)                         (((x) >> 26) & 0x1)
 #define   C_00000D_FORCE_PX                            0xFBFFFFFF
 #define   S_00000D_FORCE_TX(x)                         (((x) & 0x1) << 27)
 #define   G_00000D_FORCE_TX(x)                         (((x) >> 27) & 0x1)
 #define   C_00000D_FORCE_TX                            0xF7FFFFFF
-#define   S_00000D_FORCE_RB(x)                         (((x) & 0x1) << 28)
-#define   G_00000D_FORCE_RB(x)                         (((x) >> 28) & 0x1)
-#define   C_00000D_FORCE_RB                            0xEFFFFFFF
+#define   S_00000D_FORCE_US(x)                         (((x) & 0x1) << 28)
+#define   G_00000D_FORCE_US(x)                         (((x) >> 28) & 0x1)
+#define   C_00000D_FORCE_US                            0xEFFFFFFF
 #define   S_00000D_FORCE_TV_SCLK(x)                    (((x) & 0x1) << 29)
 #define   G_00000D_FORCE_TV_SCLK(x)                    (((x) >> 29) & 0x1)
 #define   C_00000D_FORCE_TV_SCLK                       0xDFFFFFFF
-#define   S_00000D_FORCE_SUBPIC(x)                     (((x) & 0x1) << 30)
-#define   G_00000D_FORCE_SUBPIC(x)                     (((x) >> 30) & 0x1)
-#define   C_00000D_FORCE_SUBPIC                        0xBFFFFFFF
+#define   S_00000D_FORCE_SU(x)                         (((x) & 0x1) << 30)
+#define   G_00000D_FORCE_SU(x)                         (((x) >> 30) & 0x1)
+#define   C_00000D_FORCE_SU                            0xBFFFFFFF
 #define   S_00000D_FORCE_OV0(x)                        (((x) & 0x1) << 31)
 #define   G_00000D_FORCE_OV0(x)                        (((x) >> 31) & 0x1)
 #define   C_00000D_FORCE_OV0                           0x7FFFFFFF
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 0bf13fccdaf2..a555b7b19b48 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -186,7 +186,7 @@ static int r520_startup(struct radeon_device *rdev)
         }
         /* Enable IRQ */
         rdev->irq.sw_int = true;
-        r100_irq_set(rdev);
+        rs600_irq_set(rdev);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -228,7 +228,6 @@ int r520_init(struct radeon_device *rdev)
 {
         int r;
 
-        rdev->new_init_path = true;
         /* Initialize scratch registers */
         radeon_scratch_init(rdev);
         /* Initialize surface registers */
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 2e4e60edbff4..609719490ec2 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -65,16 +65,11 @@ MODULE_FIRMWARE("radeon/RV710_me.bin");
 
 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
 
-/* This files gather functions specifics to:
- * r600,rv610,rv630,rv620,rv635,rv670
- *
- * Some of these functions might be used by newer ASICs.
- */
+/* r600,rv610,rv630,rv620,rv635,rv670 */
 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 void r600_gpu_init(struct radeon_device *rdev);
 void r600_fini(struct radeon_device *rdev);
 
-
 /*
  * R600 PCIE GART
  */
@@ -168,7 +163,7 @@ int r600_pcie_gart_enable(struct radeon_device *rdev)
         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
-        WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
+        WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
@@ -225,6 +220,40 @@ void r600_pcie_gart_fini(struct radeon_device *rdev)
         radeon_gart_fini(rdev);
 }
 
+void r600_agp_enable(struct radeon_device *rdev)
+{
+        u32 tmp;
+        int i;
+
+        /* Setup L2 cache */
+        WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
+                                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
+                                EFFECTIVE_L2_QUEUE_SIZE(7));
+        WREG32(VM_L2_CNTL2, 0);
+        WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
+        /* Setup TLB control */
+        tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
+                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
+                EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
+                ENABLE_WAIT_L2_QUERY;
+        WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
+        WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
+        WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
+        WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
+        WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
+        WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
+        WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
+        WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
+        WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
+        WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
+        WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
+        WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
+        WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
+        WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
+        for (i = 0; i < 7; i++)
+                WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
+}
+
 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 {
         unsigned i;
@@ -240,14 +269,9 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev)
         return -1;
 }
 
-static void r600_mc_resume(struct radeon_device *rdev)
+static void r600_mc_program(struct radeon_device *rdev)
 {
-        u32 d1vga_control, d2vga_control;
-        u32 vga_render_control, vga_hdp_control;
-        u32 d1crtc_control, d2crtc_control;
-        u32 new_d1grph_primary, new_d1grph_secondary;
-        u32 new_d2grph_primary, new_d2grph_secondary;
-        u64 old_vram_start;
+        struct rv515_mc_save save;
         u32 tmp;
         int i, j;
 
@@ -261,85 +285,51 @@ static void r600_mc_resume(struct radeon_device *rdev)
         }
         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 
-        d1vga_control = RREG32(D1VGA_CONTROL);
-        d2vga_control = RREG32(D2VGA_CONTROL);
-        vga_render_control = RREG32(VGA_RENDER_CONTROL);
-        vga_hdp_control = RREG32(VGA_HDP_CONTROL);
-        d1crtc_control = RREG32(D1CRTC_CONTROL);
-        d2crtc_control = RREG32(D2CRTC_CONTROL);
-        old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
-        new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
-        new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
-        new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
-        new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
-        new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
-        new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
-        new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
-        new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
-
-        /* Stop all video */
-        WREG32(D1VGA_CONTROL, 0);
-        WREG32(D2VGA_CONTROL, 0);
-        WREG32(VGA_RENDER_CONTROL, 0);
-        WREG32(D1CRTC_UPDATE_LOCK, 1);
-        WREG32(D2CRTC_UPDATE_LOCK, 1);
-        WREG32(D1CRTC_CONTROL, 0);
-        WREG32(D2CRTC_CONTROL, 0);
-        WREG32(D1CRTC_UPDATE_LOCK, 0);
-        WREG32(D2CRTC_UPDATE_LOCK, 0);
-
-        mdelay(1);
+        rv515_mc_stop(rdev, &save);
         if (r600_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "[drm] MC not idle !\n");
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
         }
-
-        /* Lockout access through VGA aperture*/
+        /* Lockout access through VGA aperture (doesn't exist before R600) */
         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
-
         /* Update configuration */
-        WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
-        WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
+        if (rdev->flags & RADEON_IS_AGP) {
+                if (rdev->mc.vram_start < rdev->mc.gtt_start) {
+                        /* VRAM before AGP */
+                        WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+                                rdev->mc.vram_start >> 12);
+                        WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+                                rdev->mc.gtt_end >> 12);
+                } else {
+                        /* VRAM after AGP */
+                        WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+                                rdev->mc.gtt_start >> 12);
+                        WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+                                rdev->mc.vram_end >> 12);
+                }
+        } else {
+                WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
+                WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
+        }
         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
-        tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
+        tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
         WREG32(MC_VM_FB_LOCATION, tmp);
         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
-        WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
+        WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
         if (rdev->flags & RADEON_IS_AGP) {
-                WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
-                WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
+                WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
+                WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
         } else {
                 WREG32(MC_VM_AGP_BASE, 0);
                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
         }
-        WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
-        WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
-        WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
-        WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
-        WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
-
-        /* Unlock host access */
-        WREG32(VGA_HDP_CONTROL, vga_hdp_control);
-
-        mdelay(1);
         if (r600_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "[drm] MC not idle !\n");
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
         }
-
-        /* Restore video state */
-        WREG32(D1CRTC_UPDATE_LOCK, 1);
-        WREG32(D2CRTC_UPDATE_LOCK, 1);
-        WREG32(D1CRTC_CONTROL, d1crtc_control);
-        WREG32(D2CRTC_CONTROL, d2crtc_control);
-        WREG32(D1CRTC_UPDATE_LOCK, 0);
-        WREG32(D2CRTC_UPDATE_LOCK, 0);
-        WREG32(D1VGA_CONTROL, d1vga_control);
-        WREG32(D2VGA_CONTROL, d2vga_control);
-        WREG32(VGA_RENDER_CONTROL, vga_render_control);
-
+        rv515_mc_resume(rdev, &save);
         /* we need to own VRAM, so turn off the VGA renderer here
          * to stop it overwriting our objects */
         rv515_vga_render_disable(rdev);
@@ -445,9 +435,9 @@ int r600_mc_init(struct radeon_device *rdev)
                 }
         }
         rdev->mc.vram_start = rdev->mc.vram_location;
-        rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
+        rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
         rdev->mc.gtt_start = rdev->mc.gtt_location;
-        rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
+        rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
         /* FIXME: we should enforce default clock in case GPU is not in
          * default setup
          */
@@ -463,6 +453,7 @@ int r600_mc_init(struct radeon_device *rdev)
  */
 int r600_gpu_soft_reset(struct radeon_device *rdev)
 {
+        struct rv515_mc_save save;
         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
@@ -480,13 +471,25 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
         u32 srbm_reset = 0;
+        u32 tmp;
 
+        dev_info(rdev->dev, "GPU softreset \n");
+        dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
+                RREG32(R_008010_GRBM_STATUS));
+        dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
+                RREG32(R_008014_GRBM_STATUS2));
+        dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
+                RREG32(R_000E50_SRBM_STATUS));
+        rv515_mc_stop(rdev, &save);
+        if (r600_mc_wait_for_idle(rdev)) {
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+        }
         /* Disable CP parsing/prefetching */
         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
         /* Check if any of the rendering block is busy and reset it */
         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
-                WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) |
+                tmp = S_008020_SOFT_RESET_CR(1) |
                         S_008020_SOFT_RESET_DB(1) |
                         S_008020_SOFT_RESET_CB(1) |
                         S_008020_SOFT_RESET_PA(1) |
@@ -498,14 +501,18 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
                         S_008020_SOFT_RESET_TC(1) |
                         S_008020_SOFT_RESET_TA(1) |
                         S_008020_SOFT_RESET_VC(1) |
-                        S_008020_SOFT_RESET_VGT(1));
+                        S_008020_SOFT_RESET_VGT(1);
+                dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
+                WREG32(R_008020_GRBM_SOFT_RESET, tmp);
                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
                 udelay(50);
                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
         }
         /* Reset CP (we always reset CP) */
-        WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1));
+        tmp = S_008020_SOFT_RESET_CP(1);
+        dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
+        WREG32(R_008020_GRBM_SOFT_RESET, tmp);
         (void)RREG32(R_008020_GRBM_SOFT_RESET);
         udelay(50);
         WREG32(R_008020_GRBM_SOFT_RESET, 0);
@@ -533,6 +540,14 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
+        if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
+                srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
+        dev_info(rdev->dev, "  R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
+        WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
+        (void)RREG32(R_000E60_SRBM_SOFT_RESET);
+        udelay(50);
+        WREG32(R_000E60_SRBM_SOFT_RESET, 0);
+        (void)RREG32(R_000E60_SRBM_SOFT_RESET);
         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
         udelay(50);
@@ -540,6 +555,17 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
         /* Wait a little for things to settle down */
         udelay(50);
+        dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
+                RREG32(R_008010_GRBM_STATUS));
+        dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
+                RREG32(R_008014_GRBM_STATUS2));
+        dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
+                RREG32(R_000E50_SRBM_STATUS));
+        /* After reset we need to reinit the asic as GPU often endup in an
+         * incoherent state.
+         */
+        atom_asic_init(rdev->mode_info.atom_context);
+        rv515_mc_resume(rdev, &save);
         return 0;
 }
 
@@ -1350,32 +1376,47 @@ int r600_ring_test(struct radeon_device *rdev)
         return r;
 }
 
-/*
- * Writeback
- */
-int r600_wb_init(struct radeon_device *rdev)
+void r600_wb_disable(struct radeon_device *rdev)
+{
+        WREG32(SCRATCH_UMSK, 0);
+        if (rdev->wb.wb_obj) {
+                radeon_object_kunmap(rdev->wb.wb_obj);
+                radeon_object_unpin(rdev->wb.wb_obj);
+        }
+}
+
+void r600_wb_fini(struct radeon_device *rdev)
+{
+        r600_wb_disable(rdev);
+        if (rdev->wb.wb_obj) {
+                radeon_object_unref(&rdev->wb.wb_obj);
+                rdev->wb.wb = NULL;
+                rdev->wb.wb_obj = NULL;
+        }
+}
+
+int r600_wb_enable(struct radeon_device *rdev)
 {
         int r;
 
         if (rdev->wb.wb_obj == NULL) {
-                r = radeon_object_create(rdev, NULL, 4096,
-                                         true,
-                                         RADEON_GEM_DOMAIN_GTT,
-                                         false, &rdev->wb.wb_obj);
+                r = radeon_object_create(rdev, NULL, 4096, true,
+                                RADEON_GEM_DOMAIN_GTT, false, &rdev->wb.wb_obj);
                 if (r) {
-                        DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
+                        dev_warn(rdev->dev, "failed to create WB buffer (%d).\n", r);
                         return r;
                 }
-                r = radeon_object_pin(rdev->wb.wb_obj,
-                                      RADEON_GEM_DOMAIN_GTT,
-                                      &rdev->wb.gpu_addr);
+                r = radeon_object_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
+                                &rdev->wb.gpu_addr);
                 if (r) {
-                        DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
+                        dev_warn(rdev->dev, "failed to pin WB buffer (%d).\n", r);
+                        r600_wb_fini(rdev);
                         return r;
                 }
                 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
                 if (r) {
-                        DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
+                        dev_warn(rdev->dev, "failed to map WB buffer (%d).\n", r);
+                        r600_wb_fini(rdev);
                         return r;
                 }
         }
@@ -1386,21 +1427,6 @@ int r600_wb_init(struct radeon_device *rdev)
         return 0;
 }
 
-void r600_wb_fini(struct radeon_device *rdev)
-{
-        if (rdev->wb.wb_obj) {
-                radeon_object_kunmap(rdev->wb.wb_obj);
-                radeon_object_unpin(rdev->wb.wb_obj);
-                radeon_object_unref(&rdev->wb.wb_obj);
-                rdev->wb.wb = NULL;
-                rdev->wb.wb_obj = NULL;
-        }
-}
-
-
-/*
- * CS
- */
 void r600_fence_ring_emit(struct radeon_device *rdev,
                           struct radeon_fence *fence)
 {
@@ -1477,11 +1503,14 @@ int r600_startup(struct radeon_device *rdev)
 {
         int r;
 
-        r600_gpu_reset(rdev);
-        r600_mc_resume(rdev);
-        r = r600_pcie_gart_enable(rdev);
-        if (r)
-                return r;
+        r600_mc_program(rdev);
+        if (rdev->flags & RADEON_IS_AGP) {
+                r600_agp_enable(rdev);
+        } else {
+                r = r600_pcie_gart_enable(rdev);
+                if (r)
+                        return r;
+        }
         r600_gpu_init(rdev);
 
         r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
@@ -1500,9 +1529,8 @@ int r600_startup(struct radeon_device *rdev)
         r = r600_cp_resume(rdev);
         if (r)
                 return r;
-        r = r600_wb_init(rdev);
-        if (r)
-                return r;
+        /* write back buffer are not vital so don't worry about failure */
+        r600_wb_enable(rdev);
         return 0;
 }
 
@@ -1524,15 +1552,12 @@ int r600_resume(struct radeon_device *rdev)
 {
         int r;
 
-        if (radeon_gpu_reset(rdev)) {
-                /* FIXME: what do we want to do here ? */
-        }
+        /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
+         * posting will perform necessary task to bring back GPU into good
+         * shape.
+         */
         /* post card */
-        if (rdev->is_atom_bios) {
-                atom_asic_init(rdev->mode_info.atom_context);
-        } else {
-                radeon_combios_asic_init(rdev->ddev);
-        }
+        atom_asic_init(rdev->mode_info.atom_context);
         /* Initialize clocks */
         r = radeon_clocks_init(rdev);
         if (r) {
@@ -1545,7 +1570,7 @@ int r600_resume(struct radeon_device *rdev)
                 return r;
         }
 
-        r = radeon_ib_test(rdev);
+        r = r600_ib_test(rdev);
         if (r) {
                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
                 return r;
@@ -1553,13 +1578,12 @@ int r600_resume(struct radeon_device *rdev)
         return r;
 }
 
-
 int r600_suspend(struct radeon_device *rdev)
 {
         /* FIXME: we should wait for ring to be empty */
         r600_cp_stop(rdev);
         rdev->cp.ready = false;
-
+        r600_wb_disable(rdev);
         r600_pcie_gart_disable(rdev);
         /* unpin shaders bo */
         radeon_object_unpin(rdev->r600_blit.shader_obj);
@@ -1576,7 +1600,6 @@ int r600_init(struct radeon_device *rdev)
 {
         int r;
 
-        rdev->new_init_path = true;
         r = radeon_dummy_page_init(rdev);
         if (r)
                 return r;
@@ -1593,8 +1616,10 @@ int r600_init(struct radeon_device *rdev)
                         return -EINVAL;
         }
         /* Must be an ATOMBIOS */
-        if (!rdev->is_atom_bios)
+        if (!rdev->is_atom_bios) {
+                dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
                 return -EINVAL;
+        }
         r = radeon_atombios_init(rdev);
         if (r)
                 return r;
@@ -1616,15 +1641,8 @@ int r600_init(struct radeon_device *rdev)
         if (r)
                 return r;
         r = r600_mc_init(rdev);
-        if (r) {
-                if (rdev->flags & RADEON_IS_AGP) {
-                        /* Retry with disabling AGP */
-                        r600_fini(rdev);
-                        rdev->flags &= ~RADEON_IS_AGP;
-                        return r600_init(rdev);
-                }
+        if (r)
                 return r;
-        }
         /* Memory manager */
         r = radeon_object_init(rdev);
         if (r)
@@ -1653,12 +1671,10 @@ int r600_init(struct radeon_device *rdev)
 
         r = r600_startup(rdev);
         if (r) {
-                if (rdev->flags & RADEON_IS_AGP) {
-                        /* Retry with disabling AGP */
-                        r600_fini(rdev);
-                        rdev->flags &= ~RADEON_IS_AGP;
-                        return r600_init(rdev);
-                }
+                r600_suspend(rdev);
+                r600_wb_fini(rdev);
+                radeon_ring_fini(rdev);
+                r600_pcie_gart_fini(rdev);
                 rdev->accel_working = false;
         }
         if (rdev->accel_working) {
@@ -1667,7 +1683,7 @@ int r600_init(struct radeon_device *rdev)
                         DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
                         rdev->accel_working = false;
                 }
-                r = radeon_ib_test(rdev);
+                r = r600_ib_test(rdev);
                 if (r) {
                         DRM_ERROR("radeon: failled testing IB (%d).\n", r);
                         rdev->accel_working = false;
@@ -1683,19 +1699,15 @@ void r600_fini(struct radeon_device *rdev)
 
         r600_blit_fini(rdev);
         radeon_ring_fini(rdev);
+        r600_wb_fini(rdev);
         r600_pcie_gart_fini(rdev);
         radeon_gem_fini(rdev);
         radeon_fence_driver_fini(rdev);
         radeon_clocks_fini(rdev);
-#if __OS_HAS_AGP
         if (rdev->flags & RADEON_IS_AGP)
                 radeon_agp_fini(rdev);
-#endif
         radeon_object_fini(rdev);
-        if (rdev->is_atom_bios)
-                radeon_atombios_fini(rdev);
-        else
-                radeon_combios_fini(rdev);
+        radeon_atombios_fini(rdev);
         kfree(rdev->bios);
         rdev->bios = NULL;
         radeon_dummy_page_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
index d988eece0187..dec501081608 100644
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -582,8 +582,6 @@ r600_blit_copy(struct drm_device *dev,
         u64 vb_addr;
         u32 *vb;
 
-        vb = r600_nomm_get_vb_ptr(dev);
-
         if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
                 max_bytes = 8192;
 
@@ -619,8 +617,8 @@ r600_blit_copy(struct drm_device *dev,
                                 if (!dev_priv->blit_vb)
                                         return;
                                 set_shaders(dev);
-                                vb = r600_nomm_get_vb_ptr(dev);
                         }
+                        vb = r600_nomm_get_vb_ptr(dev);
 
                         vb[0] = i2f(dst_x);
                         vb[1] = 0;
@@ -708,8 +706,8 @@ r600_blit_copy(struct drm_device *dev,
                                         return;
 
                                 set_shaders(dev);
-                                vb = r600_nomm_get_vb_ptr(dev);
                         }
+                        vb = r600_nomm_get_vb_ptr(dev);
 
                         vb[0] = i2f(dst_x / 4);
                         vb[1] = 0;
@@ -777,8 +775,6 @@ r600_blit_swap(struct drm_device *dev,
         u64 vb_addr;
         u32 *vb;
 
-        vb = r600_nomm_get_vb_ptr(dev);
-
         if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
 
                 r600_nomm_put_vb(dev);
@@ -787,8 +783,8 @@ r600_blit_swap(struct drm_device *dev,
                         return;
 
                 set_shaders(dev);
-                vb = r600_nomm_get_vb_ptr(dev);
         }
+        vb = r600_nomm_get_vb_ptr(dev);
 
         if (cpp == 4) {
                 cb_format = COLOR_8_8_8_8;
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index acae33e2ad51..93108bb31d1d 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -610,7 +610,6 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
 
         DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
                   size_bytes, rdev->r600_blit.vb_used);
-        vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
         if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
                 max_bytes = 8192;
 
@@ -653,6 +652,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
                                 vb = r600_nomm_get_vb_ptr(dev);
 #endif
                         }
+                        vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
 
                         vb[0] = i2f(dst_x);
                         vb[1] = 0;
@@ -747,6 +747,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
                                 vb = r600_nomm_get_vb_ptr(dev);
                         }
 #endif
+                        vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
 
                         vb[0] = i2f(dst_x / 4);
                         vb[1] = 0;
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index d28970db6a2d..17e42195c632 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -252,7 +252,7 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
 
         header = radeon_get_ib_value(p, h_idx);
         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
-        reg = header >> 2;
+        reg = CP_PACKET0_GET_REG(header);
         mutex_lock(&p->rdev->ddev->mode_config.mutex);
         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
         if (!obj) {
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 4a9028a85c9b..9b64d47f1f82 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -643,6 +643,7 @@
 #define         G_000E50_MCDW_BUSY(x)                   (((x) >> 13) & 1)
 #define         G_000E50_SEM_BUSY(x)                    (((x) >> 14) & 1)
 #define         G_000E50_RLC_BUSY(x)                    (((x) >> 15) & 1)
+#define         G_000E50_BIF_BUSY(x)                    (((x) >> 29) & 1)
 #define R_000E60_SRBM_SOFT_RESET                        0x0E60
 #define         S_000E60_SOFT_RESET_BIF(x)              (((x) & 1) << 1)
 #define         S_000E60_SOFT_RESET_CG(x)               (((x) & 1) << 2)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 950b346e343f..5ab35b81c86b 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -590,18 +590,8 @@ struct radeon_asic {
         void (*fini)(struct radeon_device *rdev);
         int (*resume)(struct radeon_device *rdev);
         int (*suspend)(struct radeon_device *rdev);
-        void (*errata)(struct radeon_device *rdev);
-        void (*vram_info)(struct radeon_device *rdev);
         void (*vga_set_state)(struct radeon_device *rdev, bool state);
         int (*gpu_reset)(struct radeon_device *rdev);
-        int (*mc_init)(struct radeon_device *rdev);
-        void (*mc_fini)(struct radeon_device *rdev);
-        int (*wb_init)(struct radeon_device *rdev);
-        void (*wb_fini)(struct radeon_device *rdev);
-        int (*gart_init)(struct radeon_device *rdev);
-        void (*gart_fini)(struct radeon_device *rdev);
-        int (*gart_enable)(struct radeon_device *rdev);
-        void (*gart_disable)(struct radeon_device *rdev);
         void (*gart_tlb_flush)(struct radeon_device *rdev);
         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
@@ -611,7 +601,6 @@ struct radeon_asic {
         void (*ring_start)(struct radeon_device *rdev);
         int (*ring_test)(struct radeon_device *rdev);
         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
-        int (*ib_test)(struct radeon_device *rdev);
         int (*irq_set)(struct radeon_device *rdev);
         int (*irq_process)(struct radeon_device *rdev);
         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
@@ -789,7 +778,6 @@ struct radeon_device {
         bool                            shutdown;
         bool                            suspend;
         bool                            need_dma32;
-        bool                            new_init_path;
         bool                            accel_working;
         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
         const struct firmware *me_fw;   /* all family ME firmware */
@@ -949,28 +937,14 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
-#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
-#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
 #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
-#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
-#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
-#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
-#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
-#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
-#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
-#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
-#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
-#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
-#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
-#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
-#define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
@@ -996,6 +970,7 @@ extern void radeon_clocks_fini(struct radeon_device *rdev);
 extern void radeon_scratch_init(struct radeon_device *rdev);
 extern void radeon_surface_init(struct radeon_device *rdev);
 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
+extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
 
 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
@@ -1031,11 +1006,27 @@ extern int r100_wb_init(struct radeon_device *rdev);
 extern void r100_hdp_reset(struct radeon_device *rdev);
 extern int r100_rb2d_reset(struct radeon_device *rdev);
 extern int r100_cp_reset(struct radeon_device *rdev);
+extern void r100_vga_render_disable(struct radeon_device *rdev);
+extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
+                                                struct radeon_cs_packet *pkt,
+                                                struct radeon_object *robj);
+extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
+                                struct radeon_cs_packet *pkt,
+                                const unsigned *auth, unsigned n,
+                                radeon_packet0_check_t check);
+extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
+                                struct radeon_cs_packet *pkt,
+                                unsigned idx);
+
+/* rv200,rv250,rv280 */
+extern void r200_set_safe_registers(struct radeon_device *rdev);
 
 /* r300,r350,rv350,rv370,rv380 */
 extern void r300_set_reg_safe(struct radeon_device *rdev);
 extern void r300_mc_program(struct radeon_device *rdev);
 extern void r300_vram_info(struct radeon_device *rdev);
+extern void r300_clock_startup(struct radeon_device *rdev);
+extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
@@ -1066,6 +1057,18 @@ extern void rv515_clock_startup(struct radeon_device *rdev);
 extern void rv515_debugfs(struct radeon_device *rdev);
 extern int rv515_suspend(struct radeon_device *rdev);
 
+/* rs400 */
+extern int rs400_gart_init(struct radeon_device *rdev);
+extern int rs400_gart_enable(struct radeon_device *rdev);
+extern void rs400_gart_adjust_size(struct radeon_device *rdev);
+extern void rs400_gart_disable(struct radeon_device *rdev);
+extern void rs400_gart_fini(struct radeon_device *rdev);
+
+/* rs600 */
+extern void rs600_set_safe_registers(struct radeon_device *rdev);
+extern int rs600_irq_set(struct radeon_device *rdev);
+extern void rs600_irq_disable(struct radeon_device *rdev);
+
 /* rs690, rs740 */
 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
                                         struct drm_display_mode *mode1,
@@ -1083,8 +1086,9 @@ extern int r600_pcie_gart_init(struct radeon_device *rdev);
 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 extern int r600_ib_test(struct radeon_device *rdev);
 extern int r600_ring_test(struct radeon_device *rdev);
-extern int r600_wb_init(struct radeon_device *rdev);
 extern void r600_wb_fini(struct radeon_device *rdev);
+extern int r600_wb_enable(struct radeon_device *rdev);
+extern void r600_wb_disable(struct radeon_device *rdev);
 extern void r600_scratch_init(struct radeon_device *rdev);
 extern int r600_blit_init(struct radeon_device *rdev);
 extern void r600_blit_fini(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index c8a4e7b5663d..c3532c7a6f3f 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -41,28 +41,17 @@ void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
 /*
  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  */
-int r100_init(struct radeon_device *rdev);
-int r200_init(struct radeon_device *rdev);
+extern int r100_init(struct radeon_device *rdev);
+extern void r100_fini(struct radeon_device *rdev);
+extern int r100_suspend(struct radeon_device *rdev);
+extern int r100_resume(struct radeon_device *rdev);
 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-void r100_errata(struct radeon_device *rdev);
-void r100_vram_info(struct radeon_device *rdev);
 void r100_vga_set_state(struct radeon_device *rdev, bool state);
 int r100_gpu_reset(struct radeon_device *rdev);
-int r100_mc_init(struct radeon_device *rdev);
-void r100_mc_fini(struct radeon_device *rdev);
 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
-int r100_wb_init(struct radeon_device *rdev);
-void r100_wb_fini(struct radeon_device *rdev);
-int r100_pci_gart_init(struct radeon_device *rdev);
-void r100_pci_gart_fini(struct radeon_device *rdev);
-int r100_pci_gart_enable(struct radeon_device *rdev);
-void r100_pci_gart_disable(struct radeon_device *rdev);
 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
-int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
-void r100_cp_fini(struct radeon_device *rdev);
-void r100_cp_disable(struct radeon_device *rdev);
 void r100_cp_commit(struct radeon_device *rdev);
 void r100_ring_start(struct radeon_device *rdev);
 int r100_irq_set(struct radeon_device *rdev);
@@ -83,33 +72,21 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
 int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
 void r100_bandwidth_update(struct radeon_device *rdev);
 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-int r100_ib_test(struct radeon_device *rdev);
 int r100_ring_test(struct radeon_device *rdev);
 
 static struct radeon_asic r100_asic = {
         .init = &r100_init,
-        .errata = &r100_errata,
-        .vram_info = &r100_vram_info,
+        .fini = &r100_fini,
+        .suspend = &r100_suspend,
+        .resume = &r100_resume,
         .vga_set_state = &r100_vga_set_state,
         .gpu_reset = &r100_gpu_reset,
-        .mc_init = &r100_mc_init,
-        .mc_fini = &r100_mc_fini,
-        .wb_init = &r100_wb_init,
-        .wb_fini = &r100_wb_fini,
-        .gart_init = &r100_pci_gart_init,
-        .gart_fini = &r100_pci_gart_fini,
-        .gart_enable = &r100_pci_gart_enable,
-        .gart_disable = &r100_pci_gart_disable,
         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
         .gart_set_page = &r100_pci_gart_set_page,
-        .cp_init = &r100_cp_init,
-        .cp_fini = &r100_cp_fini,
-        .cp_disable = &r100_cp_disable,
         .cp_commit = &r100_cp_commit,
         .ring_start = &r100_ring_start,
         .ring_test = &r100_ring_test,
         .ring_ib_execute = &r100_ring_ib_execute,
-        .ib_test = &r100_ib_test,
         .irq_set = &r100_irq_set,
         .irq_process = &r100_irq_process,
         .get_vblank_counter = &r100_get_vblank_counter,
@@ -131,55 +108,38 @@ static struct radeon_asic r100_asic = {
 /*
  * r300,r350,rv350,rv380
  */
-int r300_init(struct radeon_device *rdev);
-void r300_errata(struct radeon_device *rdev);
-void r300_vram_info(struct radeon_device *rdev);
-int r300_gpu_reset(struct radeon_device *rdev);
-int r300_mc_init(struct radeon_device *rdev);
-void r300_mc_fini(struct radeon_device *rdev);
-void r300_ring_start(struct radeon_device *rdev);
-void r300_fence_ring_emit(struct radeon_device *rdev,
-                          struct radeon_fence *fence);
-int r300_cs_parse(struct radeon_cs_parser *p);
-int rv370_pcie_gart_init(struct radeon_device *rdev);
-void rv370_pcie_gart_fini(struct radeon_device *rdev);
-int rv370_pcie_gart_enable(struct radeon_device *rdev);
-void rv370_pcie_gart_disable(struct radeon_device *rdev);
-void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
-int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
-uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
-void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
-void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
-int r300_copy_dma(struct radeon_device *rdev,
-                  uint64_t src_offset,
-                  uint64_t dst_offset,
-                  unsigned num_pages,
-                  struct radeon_fence *fence);
-
+extern int r300_init(struct radeon_device *rdev);
+extern void r300_fini(struct radeon_device *rdev);
+extern int r300_suspend(struct radeon_device *rdev);
+extern int r300_resume(struct radeon_device *rdev);
+extern int r300_gpu_reset(struct radeon_device *rdev);
+extern void r300_ring_start(struct radeon_device *rdev);
+extern void r300_fence_ring_emit(struct radeon_device *rdev,
+                                struct radeon_fence *fence);
+extern int r300_cs_parse(struct radeon_cs_parser *p);
+extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
+extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
+extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
+extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
+extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
+extern int r300_copy_dma(struct radeon_device *rdev,
+                        uint64_t src_offset,
+                        uint64_t dst_offset,
+                        unsigned num_pages,
+                        struct radeon_fence *fence);
 static struct radeon_asic r300_asic = {
         .init = &r300_init,
-        .errata = &r300_errata,
-        .vram_info = &r300_vram_info,
+        .fini = &r300_fini,
+        .suspend = &r300_suspend,
+        .resume = &r300_resume,
         .vga_set_state = &r100_vga_set_state,
         .gpu_reset = &r300_gpu_reset,
-        .mc_init = &r300_mc_init,
-        .mc_fini = &r300_mc_fini,
-        .wb_init = &r100_wb_init,
-        .wb_fini = &r100_wb_fini,
-        .gart_init = &r100_pci_gart_init,
-        .gart_fini = &r100_pci_gart_fini,
-        .gart_enable = &r100_pci_gart_enable,
-        .gart_disable = &r100_pci_gart_disable,
         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
         .gart_set_page = &r100_pci_gart_set_page,
-        .cp_init = &r100_cp_init,
-        .cp_fini = &r100_cp_fini,
-        .cp_disable = &r100_cp_disable,
         .cp_commit = &r100_cp_commit,
         .ring_start = &r300_ring_start,
         .ring_test = &r100_ring_test,
         .ring_ib_execute = &r100_ring_ib_execute,
-        .ib_test = &r100_ib_test,
         .irq_set = &r100_irq_set,
         .irq_process = &r100_irq_process,
         .get_vblank_counter = &r100_get_vblank_counter,
@@ -209,26 +169,14 @@ static struct radeon_asic r420_asic = {
         .fini = &r420_fini,
         .suspend = &r420_suspend,
         .resume = &r420_resume,
-        .errata = NULL,
-        .vram_info = NULL,
         .vga_set_state = &r100_vga_set_state,
         .gpu_reset = &r300_gpu_reset,
-        .mc_init = NULL,
-        .mc_fini = NULL,
-        .wb_init = NULL,
-        .wb_fini = NULL,
-        .gart_enable = NULL,
-        .gart_disable = NULL,
         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
         .gart_set_page = &rv370_pcie_gart_set_page,
-        .cp_init = NULL,
-        .cp_fini = NULL,
-        .cp_disable = NULL,
         .cp_commit = &r100_cp_commit,
         .ring_start = &r300_ring_start,
         .ring_test = &r100_ring_test,
         .ring_ib_execute = &r100_ring_ib_execute,
-        .ib_test = NULL,
         .irq_set = &r100_irq_set,
         .irq_process = &r100_irq_process,
         .get_vblank_counter = &r100_get_vblank_counter,
@@ -250,42 +198,27 @@ static struct radeon_asic r420_asic = {
 /*
  * rs400,rs480
  */
-void rs400_errata(struct radeon_device *rdev);
-void rs400_vram_info(struct radeon_device *rdev);
-int rs400_mc_init(struct radeon_device *rdev);
-void rs400_mc_fini(struct radeon_device *rdev);
-int rs400_gart_init(struct radeon_device *rdev);
-void rs400_gart_fini(struct radeon_device *rdev);
-int rs400_gart_enable(struct radeon_device *rdev);
-void rs400_gart_disable(struct radeon_device *rdev);
+extern int rs400_init(struct radeon_device *rdev);
+extern void rs400_fini(struct radeon_device *rdev);
+extern int rs400_suspend(struct radeon_device *rdev);
+extern int rs400_resume(struct radeon_device *rdev);
 void rs400_gart_tlb_flush(struct radeon_device *rdev);
 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 static struct radeon_asic rs400_asic = {
-        .init = &r300_init,
-        .errata = &rs400_errata,
-        .vram_info = &rs400_vram_info,
+        .init = &rs400_init,
+        .fini = &rs400_fini,
+        .suspend = &rs400_suspend,
+        .resume = &rs400_resume,
         .vga_set_state = &r100_vga_set_state,
         .gpu_reset = &r300_gpu_reset,
-        .mc_init = &rs400_mc_init,
-        .mc_fini = &rs400_mc_fini,
-        .wb_init = &r100_wb_init,
-        .wb_fini = &r100_wb_fini,
-        .gart_init = &rs400_gart_init,
-        .gart_fini = &rs400_gart_fini,
-        .gart_enable = &rs400_gart_enable,
-        .gart_disable = &rs400_gart_disable,
         .gart_tlb_flush = &rs400_gart_tlb_flush,
         .gart_set_page = &rs400_gart_set_page,
-        .cp_init = &r100_cp_init,
-        .cp_fini = &r100_cp_fini,
-        .cp_disable = &r100_cp_disable,
         .cp_commit = &r100_cp_commit,
         .ring_start = &r300_ring_start,
         .ring_test = &r100_ring_test,
         .ring_ib_execute = &r100_ring_ib_execute,
-        .ib_test = &r100_ib_test,
         .irq_set = &r100_irq_set,
         .irq_process = &r100_irq_process,
         .get_vblank_counter = &r100_get_vblank_counter,
@@ -307,18 +240,13 @@ static struct radeon_asic rs400_asic = {
 /*
  * rs600.
  */
-int rs600_init(struct radeon_device *rdev);
-void rs600_errata(struct radeon_device *rdev);
-void rs600_vram_info(struct radeon_device *rdev);
-int rs600_mc_init(struct radeon_device *rdev);
-void rs600_mc_fini(struct radeon_device *rdev);
+extern int rs600_init(struct radeon_device *rdev);
+extern void rs600_fini(struct radeon_device *rdev);
+extern int rs600_suspend(struct radeon_device *rdev);
+extern int rs600_resume(struct radeon_device *rdev);
 int rs600_irq_set(struct radeon_device *rdev);
 int rs600_irq_process(struct radeon_device *rdev);
 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
-int rs600_gart_init(struct radeon_device *rdev);
-void rs600_gart_fini(struct radeon_device *rdev);
-int rs600_gart_enable(struct radeon_device *rdev);
-void rs600_gart_disable(struct radeon_device *rdev);
 void rs600_gart_tlb_flush(struct radeon_device *rdev);
 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
@@ -326,28 +254,17 @@ void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void rs600_bandwidth_update(struct radeon_device *rdev);
 static struct radeon_asic rs600_asic = {
         .init = &rs600_init,
-        .errata = &rs600_errata,
-        .vram_info = &rs600_vram_info,
+        .fini = &rs600_fini,
+        .suspend = &rs600_suspend,
+        .resume = &rs600_resume,
         .vga_set_state = &r100_vga_set_state,
         .gpu_reset = &r300_gpu_reset,
-        .mc_init = &rs600_mc_init,
-        .mc_fini = &rs600_mc_fini,
-        .wb_init = &r100_wb_init,
-        .wb_fini = &r100_wb_fini,
-        .gart_init = &rs600_gart_init,
-        .gart_fini = &rs600_gart_fini,
-        .gart_enable = &rs600_gart_enable,
-        .gart_disable = &rs600_gart_disable,
         .gart_tlb_flush = &rs600_gart_tlb_flush,
         .gart_set_page = &rs600_gart_set_page,
-        .cp_init = &r100_cp_init,
-        .cp_fini = &r100_cp_fini,
-        .cp_disable = &r100_cp_disable,
         .cp_commit = &r100_cp_commit,
         .ring_start = &r300_ring_start,
         .ring_test = &r100_ring_test,
         .ring_ib_execute = &r100_ring_ib_execute,
-        .ib_test = &r100_ib_test,
         .irq_set = &rs600_irq_set,
         .irq_process = &rs600_irq_process,
         .get_vblank_counter = &rs600_get_vblank_counter,
@@ -367,37 +284,26 @@ static struct radeon_asic rs600_asic = {
 /*
  * rs690,rs740
  */
-void rs690_errata(struct radeon_device *rdev);
-void rs690_vram_info(struct radeon_device *rdev);
-int rs690_mc_init(struct radeon_device *rdev);
-void rs690_mc_fini(struct radeon_device *rdev);
+int rs690_init(struct radeon_device *rdev);
+void rs690_fini(struct radeon_device *rdev);
+int rs690_resume(struct radeon_device *rdev);
+int rs690_suspend(struct radeon_device *rdev);
 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 void rs690_bandwidth_update(struct radeon_device *rdev);
 static struct radeon_asic rs690_asic = {
-        .init = &rs600_init,
-        .errata = &rs690_errata,
-        .vram_info = &rs690_vram_info,
+        .init = &rs690_init,
+        .fini = &rs690_fini,
+        .suspend = &rs690_suspend,
+        .resume = &rs690_resume,
         .vga_set_state = &r100_vga_set_state,
         .gpu_reset = &r300_gpu_reset,
-        .mc_init = &rs690_mc_init,
-        .mc_fini = &rs690_mc_fini,
-        .wb_init = &r100_wb_init,
-        .wb_fini = &r100_wb_fini,
-        .gart_init = &rs400_gart_init,
-        .gart_fini = &rs400_gart_fini,
-        .gart_enable = &rs400_gart_enable,
-        .gart_disable = &rs400_gart_disable,
         .gart_tlb_flush = &rs400_gart_tlb_flush,
         .gart_set_page = &rs400_gart_set_page,
-        .cp_init = &r100_cp_init,
-        .cp_fini = &r100_cp_fini,
-        .cp_disable = &r100_cp_disable,
         .cp_commit = &r100_cp_commit,
         .ring_start = &r300_ring_start,
         .ring_test = &r100_ring_test,
         .ring_ib_execute = &r100_ring_ib_execute,
-        .ib_test = &r100_ib_test,
         .irq_set = &rs600_irq_set,
         .irq_process = &rs600_irq_process,
         .get_vblank_counter = &rs600_get_vblank_counter,
@@ -435,28 +341,14 @@ static struct radeon_asic rv515_asic = {
         .fini = &rv515_fini,
         .suspend = &rv515_suspend,
         .resume = &rv515_resume,
-        .errata = NULL,
-        .vram_info = NULL,
         .vga_set_state = &r100_vga_set_state,
         .gpu_reset = &rv515_gpu_reset,
-        .mc_init = NULL,
-        .mc_fini = NULL,
-        .wb_init = NULL,
-        .wb_fini = NULL,
-        .gart_init = &rv370_pcie_gart_init,
-        .gart_fini = &rv370_pcie_gart_fini,
-        .gart_enable = NULL,
-        .gart_disable = NULL,
         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
         .gart_set_page = &rv370_pcie_gart_set_page,
-        .cp_init = NULL,
-        .cp_fini = NULL,
-        .cp_disable = NULL,
         .cp_commit = &r100_cp_commit,
         .ring_start = &rv515_ring_start,
         .ring_test = &r100_ring_test,
         .ring_ib_execute = &r100_ring_ib_execute,
-        .ib_test = NULL,
         .irq_set = &rs600_irq_set,
         .irq_process = &rs600_irq_process,
         .get_vblank_counter = &rs600_get_vblank_counter,
@@ -485,28 +377,14 @@ static struct radeon_asic r520_asic = {
         .fini = &rv515_fini,
         .suspend = &rv515_suspend,
         .resume = &r520_resume,
-        .errata = NULL,
-        .vram_info = NULL,
         .vga_set_state = &r100_vga_set_state,
         .gpu_reset = &rv515_gpu_reset,
-        .mc_init = NULL,
-        .mc_fini = NULL,
-        .wb_init = NULL,
-        .wb_fini = NULL,
-        .gart_init = NULL,
-        .gart_fini = NULL,
-        .gart_enable = NULL,
-        .gart_disable = NULL,
         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
         .gart_set_page = &rv370_pcie_gart_set_page,
-        .cp_init = NULL,
-        .cp_fini = NULL,
-        .cp_disable = NULL,
         .cp_commit = &r100_cp_commit,
         .ring_start = &rv515_ring_start,
         .ring_test = &r100_ring_test,
         .ring_ib_execute = &r100_ring_ib_execute,
-        .ib_test = NULL,
         .irq_set = &rs600_irq_set,
         .irq_process = &rs600_irq_process,
         .get_vblank_counter = &rs600_get_vblank_counter,
@@ -554,37 +432,23 @@ int r600_set_surface_reg(struct radeon_device *rdev, int reg,
                          uint32_t offset, uint32_t obj_size);
 int r600_clear_surface_reg(struct radeon_device *rdev, int reg);
 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
-int r600_ib_test(struct radeon_device *rdev);
 int r600_ring_test(struct radeon_device *rdev);
 int r600_copy_blit(struct radeon_device *rdev,
                    uint64_t src_offset, uint64_t dst_offset,
                    unsigned num_pages, struct radeon_fence *fence);
 
 static struct radeon_asic r600_asic = {
-        .errata = NULL,
         .init = &r600_init,
         .fini = &r600_fini,
         .suspend = &r600_suspend,
         .resume = &r600_resume,
         .cp_commit = &r600_cp_commit,
-        .vram_info = NULL,
         .vga_set_state = &r600_vga_set_state,
         .gpu_reset = &r600_gpu_reset,
-        .mc_init = NULL,
-        .mc_fini = NULL,
-        .wb_init = &r600_wb_init,
-        .wb_fini = &r600_wb_fini,
-        .gart_enable = NULL,
-        .gart_disable = NULL,
         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
         .gart_set_page = &rs600_gart_set_page,
-        .cp_init = NULL,
-        .cp_fini = NULL,
-        .cp_disable = NULL,
-        .ring_start = NULL,
         .ring_test = &r600_ring_test,
         .ring_ib_execute = &r600_ring_ib_execute,
-        .ib_test = &r600_ib_test,
         .irq_set = &r600_irq_set,
         .irq_process = &r600_irq_process,
         .fence_ring_emit = &r600_fence_ring_emit,
@@ -611,30 +475,17 @@ int rv770_resume(struct radeon_device *rdev);
 int rv770_gpu_reset(struct radeon_device *rdev);
 
 static struct radeon_asic rv770_asic = {
-        .errata = NULL,
         .init = &rv770_init,
         .fini = &rv770_fini,
         .suspend = &rv770_suspend,
         .resume = &rv770_resume,
         .cp_commit = &r600_cp_commit,
-        .vram_info = NULL,
         .gpu_reset = &rv770_gpu_reset,
         .vga_set_state = &r600_vga_set_state,
-        .mc_init = NULL,
-        .mc_fini = NULL,
-        .wb_init = &r600_wb_init,
-        .wb_fini = &r600_wb_fini,
-        .gart_enable = NULL,
-        .gart_disable = NULL,
         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
         .gart_set_page = &rs600_gart_set_page,
-        .cp_init = NULL,
-        .cp_fini = NULL,
-        .cp_disable = NULL,
-        .ring_start = NULL,
         .ring_test = &r600_ring_test,
         .ring_ib_execute = &r600_ring_ib_execute,
-        .ib_test = &r600_ib_test,
         .irq_set = &r600_irq_set,
         .irq_process = &r600_irq_process,
         .fence_ring_emit = &r600_fence_ring_emit,
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 96e37a6e7ce4..34a9b9119518 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -33,12 +33,50 @@
 /*
  * BIOS.
  */
+
+/* If you boot an IGP board with a discrete card as the primary,
+ * the IGP rom is not accessible via the rom bar as the IGP rom is
+ * part of the system bios.  On boot, the system bios puts a
+ * copy of the igp rom at the start of vram if a discrete card is
+ * present.
+ */
+static bool igp_read_bios_from_vram(struct radeon_device *rdev)
+{
+        uint8_t __iomem *bios;
+        resource_size_t vram_base;
+        resource_size_t size = 256 * 1024; /* ??? */
+
+        rdev->bios = NULL;
+        vram_base = drm_get_resource_start(rdev->ddev, 0);
+        bios = ioremap(vram_base, size);
+        if (!bios) {
+                DRM_ERROR("Unable to mmap vram\n");
+                return false;
+        }
+
+        if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
+                iounmap(bios);
+                DRM_ERROR("bad rom signature\n");
+                return false;
+        }
+        rdev->bios = kmalloc(size, GFP_KERNEL);
+        if (rdev->bios == NULL) {
+                iounmap(bios);
+                DRM_ERROR("kmalloc failed\n");
+                return false;
+        }
+        memcpy(rdev->bios, bios, size);
+        iounmap(bios);
+        return true;
+}
+
 static bool radeon_read_bios(struct radeon_device *rdev)
 {
         uint8_t __iomem *bios;
         size_t size;
 
         rdev->bios = NULL;
+        /* XXX: some cards may return 0 for rom size? ddx has a workaround */
         bios = pci_map_rom(rdev->pdev, &size);
         if (!bios) {
                 return false;
@@ -341,7 +379,9 @@ static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 
 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 {
-        if (rdev->family >= CHIP_RV770)
+        if (rdev->flags & RADEON_IS_IGP)
+                return igp_read_bios_from_vram(rdev);
+        else if (rdev->family >= CHIP_RV770)
                 return r700_read_disabled_bios(rdev);
         else if (rdev->family >= CHIP_R600)
                 return r600_read_disabled_bios(rdev);
@@ -356,7 +396,12 @@ bool radeon_get_bios(struct radeon_device *rdev)
         bool r;
         uint16_t tmp;
 
-        r = radeon_read_bios(rdev);
+        if (rdev->flags & RADEON_IS_IGP) {
+                r = igp_read_bios_from_vram(rdev);
+                if (r == false)
+                        r = radeon_read_bios(rdev);
+        } else
+                r = radeon_read_bios(rdev);
         if (r == false) {
                 r = radeon_read_disabled_bios(rdev);
         }
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index 152eef13197a..f5c32a766b10 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -411,7 +411,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                                         R300_PIXCLK_TRANS_ALWAYS_ONb |
                                         R300_PIXCLK_TVO_ALWAYS_ONb |
                                         R300_P2G2CLK_ALWAYS_ONb |
-                                        R300_P2G2CLK_ALWAYS_ONb);
+                                        R300_P2G2CLK_DAC_ALWAYS_ONb);
                                 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
                         } else if (rdev->family >= CHIP_RV350) {
                                 tmp = RREG32_PLL(R300_SCLK_CNTL2);
@@ -464,7 +464,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                                         R300_PIXCLK_TRANS_ALWAYS_ONb |
                                         R300_PIXCLK_TVO_ALWAYS_ONb |
                                         R300_P2G2CLK_ALWAYS_ONb |
-                                        R300_P2G2CLK_ALWAYS_ONb);
+                                        R300_P2G2CLK_DAC_ALWAYS_ONb);
                                 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
 
                                 tmp = RREG32_PLL(RADEON_MCLK_MISC);
@@ -654,7 +654,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                                  R300_PIXCLK_TRANS_ALWAYS_ONb |
                                  R300_PIXCLK_TVO_ALWAYS_ONb |
                                  R300_P2G2CLK_ALWAYS_ONb |
-                                 R300_P2G2CLK_ALWAYS_ONb |
+                                 R300_P2G2CLK_DAC_ALWAYS_ONb |
                                  R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
                         WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
                 } else if (rdev->family >= CHIP_RV350) {
@@ -705,7 +705,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                                  R300_PIXCLK_TRANS_ALWAYS_ONb |
                                  R300_PIXCLK_TVO_ALWAYS_ONb |
                                  R300_P2G2CLK_ALWAYS_ONb |
-                                 R300_P2G2CLK_ALWAYS_ONb |
+                                 R300_P2G2CLK_DAC_ALWAYS_ONb |
                                  R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
                         WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
                 } else {
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index ec835d56d30a..3d667031de6e 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -322,10 +322,6 @@ int radeon_asic_init(struct radeon_device *rdev)
         case CHIP_RV380:
                 rdev->asic = &r300_asic;
                 if (rdev->flags & RADEON_IS_PCIE) {
-                        rdev->asic->gart_init = &rv370_pcie_gart_init;
-                        rdev->asic->gart_fini = &rv370_pcie_gart_fini;
-                        rdev->asic->gart_enable = &rv370_pcie_gart_enable;
-                        rdev->asic->gart_disable = &rv370_pcie_gart_disable;
                         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
                         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
                 }
@@ -485,7 +481,6 @@ void radeon_combios_fini(struct radeon_device *rdev)
 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
 {
         struct radeon_device *rdev = cookie;
-
         radeon_vga_set_state(rdev, state);
         if (state)
                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
@@ -493,6 +488,29 @@ static unsigned int radeon_vga_set_decode(void *cookie, bool state)
         else
                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 }
+
+void radeon_agp_disable(struct radeon_device *rdev)
+{
+        rdev->flags &= ~RADEON_IS_AGP;
+        if (rdev->family >= CHIP_R600) {
+                DRM_INFO("Forcing AGP to PCIE mode\n");
+                rdev->flags |= RADEON_IS_PCIE;
+        } else if (rdev->family >= CHIP_RV515 ||
+                        rdev->family == CHIP_RV380 ||
+                        rdev->family == CHIP_RV410 ||
+                        rdev->family == CHIP_R423) {
+                DRM_INFO("Forcing AGP to PCIE mode\n");
+                rdev->flags |= RADEON_IS_PCIE;
+                rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
+                rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
+        } else {
+                DRM_INFO("Forcing AGP to PCI mode\n");
+                rdev->flags |= RADEON_IS_PCI;
+                rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
+                rdev->asic->gart_set_page = &r100_pci_gart_set_page;
+        }
+}
+
 /*
  * Radeon device.
  */
@@ -531,32 +549,7 @@ int radeon_device_init(struct radeon_device *rdev,
         }
 
         if (radeon_agpmode == -1) {
-                rdev->flags &= ~RADEON_IS_AGP;
-                if (rdev->family >= CHIP_R600) {
-                        DRM_INFO("Forcing AGP to PCIE mode\n");
-                        rdev->flags |= RADEON_IS_PCIE;
-                } else if (rdev->family >= CHIP_RV515 ||
-                           rdev->family == CHIP_RV380 ||
-                           rdev->family == CHIP_RV410 ||
-                           rdev->family == CHIP_R423) {
-                        DRM_INFO("Forcing AGP to PCIE mode\n");
-                        rdev->flags |= RADEON_IS_PCIE;
-                        rdev->asic->gart_init = &rv370_pcie_gart_init;
-                        rdev->asic->gart_fini = &rv370_pcie_gart_fini;
-                        rdev->asic->gart_enable = &rv370_pcie_gart_enable;
-                        rdev->asic->gart_disable = &rv370_pcie_gart_disable;
-                        rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
-                        rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
-                } else {
-                        DRM_INFO("Forcing AGP to PCI mode\n");
-                        rdev->flags |= RADEON_IS_PCI;
-                        rdev->asic->gart_init = &r100_pci_gart_init;
-                        rdev->asic->gart_fini = &r100_pci_gart_fini;
-                        rdev->asic->gart_enable = &r100_pci_gart_enable;
-                        rdev->asic->gart_disable = &r100_pci_gart_disable;
-                        rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
-                        rdev->asic->gart_set_page = &r100_pci_gart_set_page;
-                }
+                radeon_agp_disable(rdev);
         }
 
         /* set DMA mask + need_dma32 flags.
@@ -588,111 +581,27 @@ int radeon_device_init(struct radeon_device *rdev,
         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 
-        rdev->new_init_path = false;
-        r = radeon_init(rdev);
-        if (r) {
-                return r;
-        }
-
         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
         r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
         if (r) {
                 return -EINVAL;
         }
 
-        if (!rdev->new_init_path) {
-                /* Setup errata flags */
-                radeon_errata(rdev);
-                /* Initialize scratch registers */
-                radeon_scratch_init(rdev);
-                /* Initialize surface registers */
-                radeon_surface_init(rdev);
-
-                /* BIOS*/
-                if (!radeon_get_bios(rdev)) {
-                        if (ASIC_IS_AVIVO(rdev))
-                                return -EINVAL;
-                }
-                if (rdev->is_atom_bios) {
-                        r = radeon_atombios_init(rdev);
-                        if (r) {
-                                return r;
-                        }
-                } else {
-                        r = radeon_combios_init(rdev);
-                        if (r) {
-                                return r;
-                        }
-                }
-                /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-                if (radeon_gpu_reset(rdev)) {
-                        /* FIXME: what do we want to do here ? */
-                }
-                /* check if cards are posted or not */
-                if (!radeon_card_posted(rdev) && rdev->bios) {
-                        DRM_INFO("GPU not posted. posting now...\n");
-                        if (rdev->is_atom_bios) {
-                                atom_asic_init(rdev->mode_info.atom_context);
-                        } else {
-                                radeon_combios_asic_init(rdev->ddev);
-                        }
-                }
-                /* Get clock & vram information */
-                radeon_get_clock_info(rdev->ddev);
-                radeon_vram_info(rdev);
-                /* Initialize clocks */
-                r = radeon_clocks_init(rdev);
-                if (r) {
-                        return r;
-                }
+        r = radeon_init(rdev);
+        if (r)
+                return r;
 
-                /* Initialize memory controller (also test AGP) */
-                r = radeon_mc_init(rdev);
-                if (r) {
-                        return r;
-                }
-                /* Fence driver */
-                r = radeon_fence_driver_init(rdev);
-                if (r) {
-                        return r;
-                }
-                r = radeon_irq_kms_init(rdev);
-                if (r) {
-                        return r;
-                }
-                /* Memory manager */
-                r = radeon_object_init(rdev);
-                if (r) {
-                        return r;
-                }
-                r = radeon_gpu_gart_init(rdev);
+        if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
+                /* Acceleration not working on AGP card try again
+                 * with fallback to PCI or PCIE GART
+                 */
+                radeon_gpu_reset(rdev);
+                radeon_fini(rdev);
+                radeon_agp_disable(rdev);
+                r = radeon_init(rdev);
                 if (r)
                         return r;
-                /* Initialize GART (initialize after TTM so we can allocate
-                 * memory through TTM but finalize after TTM) */
-                r = radeon_gart_enable(rdev);
-                if (r)
-                        return 0;
-                        r = radeon_gem_init(rdev);
-                if (r)
-                        return 0;
-
-                /* 1M ring buffer */
-                r = radeon_cp_init(rdev, 1024 * 1024);
-                if (r)
-                        return 0;
-                r = radeon_wb_init(rdev);
-                if (r)
-                        DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
-                r = radeon_ib_pool_init(rdev);
-                if (r)
-                        return 0;
-                r = radeon_ib_test(rdev);
-                if (r)
-                        return 0;
-                rdev->accel_working = true;
         }
-        DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
         if (radeon_testing) {
                 radeon_test_moves(rdev);
         }
@@ -706,32 +615,8 @@ void radeon_device_fini(struct radeon_device *rdev)
 {
         DRM_INFO("radeon: finishing device.\n");
         rdev->shutdown = true;
-        /* Order matter so becarefull if you rearrange anythings */
-        if (!rdev->new_init_path) {
-                radeon_ib_pool_fini(rdev);
-                radeon_cp_fini(rdev);
-                radeon_wb_fini(rdev);
-                radeon_gpu_gart_fini(rdev);
-                radeon_gem_fini(rdev);
-                radeon_mc_fini(rdev);
-#if __OS_HAS_AGP
-                radeon_agp_fini(rdev);
-#endif
-                radeon_irq_kms_fini(rdev);
-                vga_client_register(rdev->pdev, NULL, NULL, NULL);
-                radeon_fence_driver_fini(rdev);
-                radeon_clocks_fini(rdev);
-                radeon_object_fini(rdev);
-                if (rdev->is_atom_bios) {
-                        radeon_atombios_fini(rdev);
-                } else {
-                        radeon_combios_fini(rdev);
-                }
-                kfree(rdev->bios);
-                rdev->bios = NULL;
-        } else {
-                radeon_fini(rdev);
-        }
+        radeon_fini(rdev);
+        vga_client_register(rdev->pdev, NULL, NULL, NULL);
         iounmap(rdev->rmmio);
         rdev->rmmio = NULL;
 }
@@ -771,14 +656,7 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 
         radeon_save_bios_scratch_regs(rdev);
 
-        if (!rdev->new_init_path) {
-                radeon_cp_disable(rdev);
-                radeon_gart_disable(rdev);
-                rdev->irq.sw_int = false;
-                radeon_irq_set(rdev);
-        } else {
-                radeon_suspend(rdev);
-        }
+        radeon_suspend(rdev);
         /* evict remaining vram memory */
         radeon_object_evict_vram(rdev);
 
@@ -797,7 +675,6 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 int radeon_resume_kms(struct drm_device *dev)
 {
         struct radeon_device *rdev = dev->dev_private;
-        int r;
 
         acquire_console_sem();
         pci_set_power_state(dev->pdev, PCI_D0);
@@ -807,43 +684,7 @@ int radeon_resume_kms(struct drm_device *dev)
                 return -1;
         }
         pci_set_master(dev->pdev);
-        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
-        if (!rdev->new_init_path) {
-                if (radeon_gpu_reset(rdev)) {
-                        /* FIXME: what do we want to do here ? */
-                }
-                /* post card */
-                if (rdev->is_atom_bios) {
-                        atom_asic_init(rdev->mode_info.atom_context);
-                } else {
-                        radeon_combios_asic_init(rdev->ddev);
-                }
-                /* Initialize clocks */
-                r = radeon_clocks_init(rdev);
-                if (r) {
-                        release_console_sem();
-                        return r;
-                }
-                /* Enable IRQ */
-                rdev->irq.sw_int = true;
-                radeon_irq_set(rdev);
-                /* Initialize GPU Memory Controller */
-                r = radeon_mc_init(rdev);
-                if (r) {
-                        goto out;
-                }
-                r = radeon_gart_enable(rdev);
-                if (r) {
-                        goto out;
-                }
-                r = radeon_cp_init(rdev, rdev->cp.ring_size);
-                if (r) {
-                        goto out;
-                }
-        } else {
-                radeon_resume(rdev);
-        }
-out:
+        radeon_resume(rdev);
         radeon_restore_bios_scratch_regs(rdev);
         fb_set_suspend(rdev->fbdev_info, 0);
         release_console_sem();
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 5d8141b13765..3655d91993a6 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -106,24 +106,33 @@ void radeon_crtc_load_lut(struct drm_crtc *crtc)
                 legacy_crtc_load_lut(crtc);
 }
 
-/** Sets the color ramps on behalf of RandR */
+/** Sets the color ramps on behalf of fbcon */
 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
                               u16 blue, int regno)
 {
         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
-        if (regno == 0)
-                DRM_DEBUG("gamma set %d\n", radeon_crtc->crtc_id);
         radeon_crtc->lut_r[regno] = red >> 6;
         radeon_crtc->lut_g[regno] = green >> 6;
         radeon_crtc->lut_b[regno] = blue >> 6;
 }
 
+/** Gets the color ramps on behalf of fbcon */
+void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
+                              u16 *blue, int regno)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+
+        *red = radeon_crtc->lut_r[regno] << 6;
+        *green = radeon_crtc->lut_g[regno] << 6;
+        *blue = radeon_crtc->lut_b[regno] << 6;
+}
+
 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
                                   u16 *blue, uint32_t size)
 {
         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
-        int i, j;
+        int i;
 
         if (size != 256) {
                 return;
@@ -132,23 +141,11 @@ static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
                 return;
         }
 
-        if (crtc->fb->depth == 16) {
-                for (i = 0; i < 64; i++) {
-                        if (i <= 31) {
-                                for (j = 0; j < 8; j++) {
-                                        radeon_crtc->lut_r[i * 8 + j] = red[i] >> 6;
-                                        radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 6;
-                                }
-                        }
-                        for (j = 0; j < 4; j++)
-                                radeon_crtc->lut_g[i * 4 + j] = green[i] >> 6;
-                }
-        } else {
-                for (i = 0; i < 256; i++) {
-                        radeon_crtc->lut_r[i] = red[i] >> 6;
-                        radeon_crtc->lut_g[i] = green[i] >> 6;
-                        radeon_crtc->lut_b[i] = blue[i] >> 6;
-                }
+        /* userspace palettes are always correct as is */
+        for (i = 0; i < 256; i++) {
+                radeon_crtc->lut_r[i] = red[i] >> 6;
+                radeon_crtc->lut_g[i] = green[i] >> 6;
+                radeon_crtc->lut_b[i] = blue[i] >> 6;
         }
 
         radeon_crtc_load_lut(crtc);
@@ -724,7 +721,11 @@ int radeon_modeset_init(struct radeon_device *rdev)
         if (ret) {
                 return ret;
         }
-        /* allocate crtcs - TODO single crtc */
+
+        if (rdev->flags & RADEON_SINGLE_CRTC)
+                num_crtc = 1;
+
+        /* allocate crtcs */
         for (i = 0; i < num_crtc; i++) {
                 radeon_crtc_init(rdev->ddev, i);
         }
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 621646752cd2..a65ab1a0dad2 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1345,6 +1345,7 @@ radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
 void
 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
 {
+        struct radeon_device *rdev = dev->dev_private;
         struct drm_encoder *encoder;
         struct radeon_encoder *radeon_encoder;
 
@@ -1364,7 +1365,10 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t su
                 return;
 
         encoder = &radeon_encoder->base;
-        encoder->possible_crtcs = 0x3;
+        if (rdev->flags & RADEON_SINGLE_CRTC)
+                encoder->possible_crtcs = 0x1;
+        else
+                encoder->possible_crtcs = 0x3;
         encoder->possible_clones = 0;
 
         radeon_encoder->enc_priv = NULL;
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 1ba704eedefb..b38c4c8e2c61 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -55,6 +55,7 @@ static struct fb_ops radeonfb_ops = {
         .fb_imageblit = cfb_imageblit,
         .fb_pan_display = drm_fb_helper_pan_display,
         .fb_blank = drm_fb_helper_blank,
+        .fb_setcmap = drm_fb_helper_setcmap,
 };
 
 /**
@@ -123,6 +124,7 @@ static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bo
 
 static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
         .gamma_set = radeon_crtc_fb_gamma_set,
+        .gamma_get = radeon_crtc_fb_gamma_get,
 };
 
 int radeonfb_create(struct drm_device *dev,
@@ -146,9 +148,15 @@ int radeonfb_create(struct drm_device *dev,
         unsigned long tmp;
         bool fb_tiled = false; /* useful for testing */
         u32 tiling_flags = 0;
+        int crtc_count;
 
         mode_cmd.width = surface_width;
         mode_cmd.height = surface_height;
+
+        /* avivo can't scanout real 24bpp */
+        if ((surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
+                surface_bpp = 32;
+
         mode_cmd.bpp = surface_bpp;
         /* need to align pitch with crtc limits */
         mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8);
@@ -217,7 +225,11 @@ int radeonfb_create(struct drm_device *dev,
         rfbdev = info->par;
         rfbdev->helper.funcs = &radeon_fb_helper_funcs;
         rfbdev->helper.dev = dev;
-        ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, 2,
+        if (rdev->flags & RADEON_SINGLE_CRTC)
+                crtc_count = 1;
+        else
+                crtc_count = 2;
+        ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, crtc_count,
                                             RADEONFB_CONN_LIMIT);
         if (ret)
                 goto out_unref;
@@ -234,7 +246,7 @@ int radeonfb_create(struct drm_device *dev,
 
         strcpy(info->fix.id, "radeondrmfb");
 
-        drm_fb_helper_fill_fix(info, fb->pitch);
+        drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
 
         info->flags = FBINFO_DEFAULT;
         info->fbops = &radeonfb_ops;
@@ -309,7 +321,7 @@ int radeon_parse_options(char *options)
 
 int radeonfb_probe(struct drm_device *dev)
 {
-        return drm_fb_helper_single_fb_probe(dev, &radeonfb_create);
+        return drm_fb_helper_single_fb_probe(dev, 32, &radeonfb_create);
 }
 
 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 1841145a7c4f..8e0a8759e428 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -83,8 +83,12 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
 int radeon_irq_kms_init(struct radeon_device *rdev)
 {
         int r = 0;
+        int num_crtc = 2;
 
-        r = drm_vblank_init(rdev->ddev, 2);
+        if (rdev->flags & RADEON_SINGLE_CRTC)
+                num_crtc = 1;
+
+        r = drm_vblank_init(rdev->ddev, num_crtc);
         if (r) {
                 return r;
         }
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 2b997a15fb1f..36410f85d705 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -1053,6 +1053,7 @@ static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
         .mode_set_base = radeon_crtc_set_base,
         .prepare = radeon_crtc_prepare,
         .commit = radeon_crtc_commit,
+        .load_lut = radeon_crtc_load_lut,
 };
 
 
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index b1547f700d73..6ceb958fd194 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -881,7 +881,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
                                         R420_TV_DAC_DACADJ_MASK |
                                         R420_TV_DAC_RDACPD |
                                         R420_TV_DAC_GDACPD |
-                                        R420_TV_DAC_GDACPD |
+                                        R420_TV_DAC_BDACPD |
                                         R420_TV_DAC_TVENABLE);
                 } else {
                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
@@ -889,7 +889,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
                                         RADEON_TV_DAC_DACADJ_MASK |
                                         RADEON_TV_DAC_RDACPD |
                                         RADEON_TV_DAC_GDACPD |
-                                        RADEON_TV_DAC_GDACPD);
+                                        RADEON_TV_DAC_BDACPD);
                 }
 
                 /*  FIXME TV */
@@ -1318,7 +1318,10 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t
                 return;
 
         encoder = &radeon_encoder->base;
-        encoder->possible_crtcs = 0x3;
+        if (rdev->flags & RADEON_SINGLE_CRTC)
+                encoder->possible_crtcs = 0x1;
+        else
+                encoder->possible_crtcs = 0x3;
         encoder->possible_clones = 0;
 
         radeon_encoder->enc_priv = NULL;
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 570a58729daf..e61226817ccf 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -407,6 +407,8 @@ extern void
 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
                                      u16 blue, int regno);
+extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
+                                     u16 *blue, int regno);
 struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
                                                   struct drm_mode_fb_cmd *mode_cmd,
                                                   struct drm_gem_object *obj);
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 73af463b7a59..1f056dadc5c2 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -400,11 +400,9 @@ void radeon_object_list_add_object(struct radeon_object_list *lobj,
 int radeon_object_list_reserve(struct list_head *head)
 {
         struct radeon_object_list *lobj;
-        struct list_head *i;
         int r;
 
-        list_for_each(i, head) {
-                lobj = list_entry(i, struct radeon_object_list, list);
+        list_for_each_entry(lobj, head, list){
                 if (!lobj->robj->pin_count) {
                         r = radeon_object_reserve(lobj->robj, true);
                         if (unlikely(r != 0)) {
@@ -420,13 +418,10 @@ int radeon_object_list_reserve(struct list_head *head)
 void radeon_object_list_unreserve(struct list_head *head)
 {
         struct radeon_object_list *lobj;
-        struct list_head *i;
 
-        list_for_each(i, head) {
-                lobj = list_entry(i, struct radeon_object_list, list);
+        list_for_each_entry(lobj, head, list) {
                 if (!lobj->robj->pin_count) {
                         radeon_object_unreserve(lobj->robj);
-                } else {
                 }
         }
 }
@@ -436,7 +431,6 @@ int radeon_object_list_validate(struct list_head *head, void *fence)
         struct radeon_object_list *lobj;
         struct radeon_object *robj;
         struct radeon_fence *old_fence = NULL;
-        struct list_head *i;
         int r;
 
         r = radeon_object_list_reserve(head);
@@ -444,8 +438,7 @@ int radeon_object_list_validate(struct list_head *head, void *fence)
                 radeon_object_list_unreserve(head);
                 return r;
         }
-        list_for_each(i, head) {
-                lobj = list_entry(i, struct radeon_object_list, list);
+        list_for_each_entry(lobj, head, list) {
                 robj = lobj->robj;
                 if (!robj->pin_count) {
                         if (lobj->wdomain) {
@@ -482,10 +475,8 @@ void radeon_object_list_unvalidate(struct list_head *head)
 {
         struct radeon_object_list *lobj;
         struct radeon_fence *old_fence = NULL;
-        struct list_head *i;
 
-        list_for_each(i, head) {
-                lobj = list_entry(i, struct radeon_object_list, list);
+        list_for_each_entry(lobj, head, list) {
                 old_fence = (struct radeon_fence *)lobj->robj->tobj.sync_obj;
                 lobj->robj->tobj.sync_obj = NULL;
                 if (old_fence) {
diff --git a/drivers/gpu/drm/radeon/rs100d.h b/drivers/gpu/drm/radeon/rs100d.h
new file mode 100644
index 000000000000..48a913a06cfd
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rs100d.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __RS100D_H__
+#define __RS100D_H__
+
+/* Registers */
+#define R_00015C_NB_TOM                              0x00015C
+#define   S_00015C_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
+#define   G_00015C_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
+#define   C_00015C_MC_FB_START                         0xFFFF0000
+#define   S_00015C_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
+#define   G_00015C_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
+#define   C_00015C_MC_FB_TOP                           0x0000FFFF
+
+#endif
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index a3fbdad938c7..a769c296f6a6 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -27,27 +27,12 @@
  */
 #include <linux/seq_file.h>
 #include <drm/drmP.h>
-#include "radeon_reg.h"
 #include "radeon.h"
+#include "rs400d.h"
 
-/* rs400,rs480 depends on : */
-void r100_hdp_reset(struct radeon_device *rdev);
-void r100_mc_disable_clients(struct radeon_device *rdev);
-int r300_mc_wait_for_idle(struct radeon_device *rdev);
-void r420_pipes_init(struct radeon_device *rdev);
+/* This files gather functions specifics to : rs400,rs480 */
+static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
 
-/* This files gather functions specifics to :
- * rs400,rs480
- *
- * Some of these functions might be used by newer ASICs.
- */
-void rs400_gpu_init(struct radeon_device *rdev);
-int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
-
-
-/*
- * GART functions.
- */
 void rs400_gart_adjust_size(struct radeon_device *rdev)
 {
         /* Check gart size */
@@ -238,61 +223,6 @@ int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
         return 0;
 }
 
-
-/*
- * MC functions.
- */
-int rs400_mc_init(struct radeon_device *rdev)
-{
-        uint32_t tmp;
-        int r;
-
-        if (r100_debugfs_rbbm_init(rdev)) {
-                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
-        }
-
-        rs400_gpu_init(rdev);
-        rs400_gart_disable(rdev);
-        rdev->mc.gtt_location = rdev->mc.mc_vram_size;
-        rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
-        rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
-        r = radeon_mc_setup(rdev);
-        if (r) {
-                return r;
-        }
-
-        r100_mc_disable_clients(rdev);
-        if (r300_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "Failed to wait MC idle while "
-                       "programming pipes. Bad things might happen.\n");
-        }
-
-        tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
-        tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
-        tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
-        WREG32(RADEON_MC_FB_LOCATION, tmp);
-        tmp = RREG32(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS;
-        WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
-        (void)RREG32(RADEON_HOST_PATH_CNTL);
-        WREG32(RADEON_HOST_PATH_CNTL, tmp);
-        (void)RREG32(RADEON_HOST_PATH_CNTL);
-
-        return 0;
-}
-
-void rs400_mc_fini(struct radeon_device *rdev)
-{
-}
-
-
-/*
- * Global GPU functions
- */
-void rs400_errata(struct radeon_device *rdev)
-{
-        rdev->pll_errata = 0;
-}
-
 void rs400_gpu_init(struct radeon_device *rdev)
 {
         /* FIXME: HDP same place on rs400 ? */
@@ -305,10 +235,6 @@ void rs400_gpu_init(struct radeon_device *rdev)
         }
 }
 
-
-/*
- * VRAM info.
- */
 void rs400_vram_info(struct radeon_device *rdev)
 {
         rs400_gart_adjust_size(rdev);
@@ -319,10 +245,6 @@ void rs400_vram_info(struct radeon_device *rdev)
         r100_vram_init_sizes(rdev);
 }
 
-
-/*
- * Indirect registers accessor
- */
 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 {
         uint32_t r;
@@ -340,10 +262,6 @@ void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
         WREG32(RS480_NB_MC_INDEX, 0xff);
 }
 
-
-/*
- * Debugfs info
- */
 #if defined(CONFIG_DEBUG_FS)
 static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
 {
@@ -419,7 +337,7 @@ static struct drm_info_list rs400_gart_info_list[] = {
 };
 #endif
 
-int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
+static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 {
 #if defined(CONFIG_DEBUG_FS)
         return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
@@ -427,3 +345,188 @@ int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
         return 0;
 #endif
 }
+
+static int rs400_mc_init(struct radeon_device *rdev)
+{
+        int r;
+        u32 tmp;
+
+        /* Setup GPU memory space */
+        tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
+        rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16;
+        rdev->mc.gtt_location = 0xFFFFFFFFUL;
+        r = radeon_mc_setup(rdev);
+        if (r)
+                return r;
+        return 0;
+}
+
+void rs400_mc_program(struct radeon_device *rdev)
+{
+        struct r100_mc_save save;
+
+        /* Stops all mc clients */
+        r100_mc_stop(rdev, &save);
+
+        /* Wait for mc idle */
+        if (r300_mc_wait_for_idle(rdev))
+                dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
+        WREG32(R_000148_MC_FB_LOCATION,
+                S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
+                S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
+
+        r100_mc_resume(rdev, &save);
+}
+
+static int rs400_startup(struct radeon_device *rdev)
+{
+        int r;
+
+        rs400_mc_program(rdev);
+        /* Resume clock */
+        r300_clock_startup(rdev);
+        /* Initialize GPU configuration (# pipes, ...) */
+        rs400_gpu_init(rdev);
+        /* Initialize GART (initialize after TTM so we can allocate
+         * memory through TTM but finalize after TTM) */
+        r = rs400_gart_enable(rdev);
+        if (r)
+                return r;
+        /* Enable IRQ */
+        rdev->irq.sw_int = true;
+        r100_irq_set(rdev);
+        /* 1M ring buffer */
+        r = r100_cp_init(rdev, 1024 * 1024);
+        if (r) {
+                dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
+                return r;
+        }
+        r = r100_wb_init(rdev);
+        if (r)
+                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
+        r = r100_ib_init(rdev);
+        if (r) {
+                dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
+                return r;
+        }
+        return 0;
+}
+
+int rs400_resume(struct radeon_device *rdev)
+{
+        /* Make sur GART are not working */
+        rs400_gart_disable(rdev);
+        /* Resume clock before doing reset */
+        r300_clock_startup(rdev);
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* post */
+        radeon_combios_asic_init(rdev->ddev);
+        /* Resume clock after posting */
+        r300_clock_startup(rdev);
+        return rs400_startup(rdev);
+}
+
+int rs400_suspend(struct radeon_device *rdev)
+{
+        r100_cp_disable(rdev);
+        r100_wb_disable(rdev);
+        r100_irq_disable(rdev);
+        rs400_gart_disable(rdev);
+        return 0;
+}
+
+void rs400_fini(struct radeon_device *rdev)
+{
+        rs400_suspend(rdev);
+        r100_cp_fini(rdev);
+        r100_wb_fini(rdev);
+        r100_ib_fini(rdev);
+        radeon_gem_fini(rdev);
+        rs400_gart_fini(rdev);
+        radeon_irq_kms_fini(rdev);
+        radeon_fence_driver_fini(rdev);
+        radeon_object_fini(rdev);
+        radeon_atombios_fini(rdev);
+        kfree(rdev->bios);
+        rdev->bios = NULL;
+}
+
+int rs400_init(struct radeon_device *rdev)
+{
+        int r;
+
+        /* Disable VGA */
+        r100_vga_render_disable(rdev);
+        /* Initialize scratch registers */
+        radeon_scratch_init(rdev);
+        /* Initialize surface registers */
+        radeon_surface_init(rdev);
+        /* TODO: disable VGA need to use VGA request */
+        /* BIOS*/
+        if (!radeon_get_bios(rdev)) {
+                if (ASIC_IS_AVIVO(rdev))
+                        return -EINVAL;
+        }
+        if (rdev->is_atom_bios) {
+                dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
+                return -EINVAL;
+        } else {
+                r = radeon_combios_init(rdev);
+                if (r)
+                        return r;
+        }
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev,
+                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* check if cards are posted or not */
+        if (!radeon_card_posted(rdev) && rdev->bios) {
+                DRM_INFO("GPU not posted. posting now...\n");
+                radeon_combios_asic_init(rdev->ddev);
+        }
+        /* Initialize clocks */
+        radeon_get_clock_info(rdev->ddev);
+        /* Get vram informations */
+        rs400_vram_info(rdev);
+        /* Initialize memory controller (also test AGP) */
+        r = rs400_mc_init(rdev);
+        if (r)
+                return r;
+        /* Fence driver */
+        r = radeon_fence_driver_init(rdev);
+        if (r)
+                return r;
+        r = radeon_irq_kms_init(rdev);
+        if (r)
+                return r;
+        /* Memory manager */
+        r = radeon_object_init(rdev);
+        if (r)
+                return r;
+        r = rs400_gart_init(rdev);
+        if (r)
+                return r;
+        r300_set_reg_safe(rdev);
+        rdev->accel_working = true;
+        r = rs400_startup(rdev);
+        if (r) {
+                /* Somethings want wront with the accel init stop accel */
+                dev_err(rdev->dev, "Disabling GPU acceleration\n");
+                rs400_suspend(rdev);
+                r100_cp_fini(rdev);
+                r100_wb_fini(rdev);
+                r100_ib_fini(rdev);
+                rs400_gart_fini(rdev);
+                radeon_irq_kms_fini(rdev);
+                rdev->accel_working = false;
+        }
+        return 0;
+}
diff --git a/drivers/gpu/drm/radeon/rs400d.h b/drivers/gpu/drm/radeon/rs400d.h
new file mode 100644
index 000000000000..6d8bac58ced9
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rs400d.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __RS400D_H__
+#define __RS400D_H__
+
+/* Registers */
+#define R_000148_MC_FB_LOCATION                      0x000148
+#define   S_000148_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
+#define   G_000148_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
+#define   C_000148_MC_FB_START                         0xFFFF0000
+#define   S_000148_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
+#define   G_000148_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
+#define   C_000148_MC_FB_TOP                           0x0000FFFF
+#define R_00015C_NB_TOM                              0x00015C
+#define   S_00015C_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
+#define   G_00015C_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
+#define   C_00015C_MC_FB_START                         0xFFFF0000
+#define   S_00015C_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
+#define   G_00015C_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
+#define   C_00015C_MC_FB_TOP                           0x0000FFFF
+#define R_0007C0_CP_STAT                             0x0007C0
+#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
+#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
+#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
+#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
+#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
+#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
+#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
+#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
+#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
+#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
+#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
+#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
+#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
+#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
+#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
+#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
+#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
+#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
+#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
+#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
+#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
+#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
+#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
+#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
+#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
+#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
+#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
+#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
+#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
+#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
+#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
+#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
+#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
+#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
+#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
+#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
+#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
+#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
+#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
+#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
+#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
+#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
+#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
+#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
+#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
+#define R_000E40_RBBM_STATUS                         0x000E40
+#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
+#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
+#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
+#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
+#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
+#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
+#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
+#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
+#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
+#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
+#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
+#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
+#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
+#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
+#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
+#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
+#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
+#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
+#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
+#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
+#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
+#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
+#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
+#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
+#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
+#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
+#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
+#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
+#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
+#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
+#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
+#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
+#define   C_000E40_E2_BUSY                             0xFFFDFFFF
+#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
+#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
+#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
+#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
+#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
+#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
+#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
+#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
+#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
+#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
+#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
+#define   C_000E40_RE_BUSY                             0xFFDFFFFF
+#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
+#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
+#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
+#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
+#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
+#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
+#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
+#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
+#define   C_000E40_PB_BUSY                             0xFEFFFFFF
+#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
+#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
+#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
+#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
+#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
+#define   C_000E40_GA_BUSY                             0xFBFFFFFF
+#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
+#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
+#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
+#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
+#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
+#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
+
+#endif
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 4a4fe1cb131c..10dfa78762da 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -25,27 +25,26 @@
  *          Alex Deucher
  *          Jerome Glisse
  */
+/* RS600 / Radeon X1250/X1270 integrated GPU
+ *
+ * This file gather function specific to RS600 which is the IGP of
+ * the X1250/X1270 family supporting intel CPU (while RS690/RS740
+ * is the X1250/X1270 supporting AMD CPU). The display engine are
+ * the avivo one, bios is an atombios, 3D block are the one of the
+ * R4XX family. The GART is different from the RS400 one and is very
+ * close to the one of the R600 family (R600 likely being an evolution
+ * of the RS600 GART block).
+ */
 #include "drmP.h"
-#include "radeon_reg.h"
 #include "radeon.h"
+#include "atom.h"
+#include "rs600d.h"
 
 #include "rs600_reg_safe.h"
 
-/* rs600 depends on : */
-void r100_hdp_reset(struct radeon_device *rdev);
-int r100_gui_wait_for_idle(struct radeon_device *rdev);
-int r300_mc_wait_for_idle(struct radeon_device *rdev);
-void r420_pipes_init(struct radeon_device *rdev);
-
-/* This files gather functions specifics to :
- * rs600
- *
- * Some of these functions might be used by newer ASICs.
- */
 void rs600_gpu_init(struct radeon_device *rdev);
 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
 
-
 /*
  * GART.
  */
@@ -53,18 +52,18 @@ void rs600_gart_tlb_flush(struct radeon_device *rdev)
 {
         uint32_t tmp;
 
-        tmp = RREG32_MC(RS600_MC_PT0_CNTL);
-        tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
-        WREG32_MC(RS600_MC_PT0_CNTL, tmp);
+        tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
+        tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
+        WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 
-        tmp = RREG32_MC(RS600_MC_PT0_CNTL);
-        tmp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
-        WREG32_MC(RS600_MC_PT0_CNTL, tmp);
+        tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
+        tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
+        WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
 
-        tmp = RREG32_MC(RS600_MC_PT0_CNTL);
-        tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
-        WREG32_MC(RS600_MC_PT0_CNTL, tmp);
-        tmp = RREG32_MC(RS600_MC_PT0_CNTL);
+        tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
+        tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
+        WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
+        tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
 }
 
 int rs600_gart_init(struct radeon_device *rdev)
@@ -86,7 +85,7 @@ int rs600_gart_init(struct radeon_device *rdev)
 
 int rs600_gart_enable(struct radeon_device *rdev)
 {
-        uint32_t tmp;
+        u32 tmp;
         int r, i;
 
         if (rdev->gart.table.vram.robj == NULL) {
@@ -96,46 +95,50 @@ int rs600_gart_enable(struct radeon_device *rdev)
         r = radeon_gart_table_vram_pin(rdev);
         if (r)
                 return r;
+        /* Enable bus master */
+        tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
+        WREG32(R_00004C_BUS_CNTL, tmp);
         /* FIXME: setup default page */
-        WREG32_MC(RS600_MC_PT0_CNTL,
-                 (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
-                  RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
+        WREG32_MC(R_000100_MC_PT0_CNTL,
+                 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
+                  S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
         for (i = 0; i < 19; i++) {
-                WREG32_MC(RS600_MC_PT0_CLIENT0_CNTL + i,
-                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
-                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
-                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE |
-                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
-                          RS600_ENABLE_FRAGMENT_PROCESSING |
-                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
+                WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
+                        S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
+                        S_00016C_SYSTEM_ACCESS_MODE_MASK(
+                                V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) |
+                        S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
+                                V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) |
+                        S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) |
+                        S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
+                        S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1));
         }
 
         /* System context map to GART space */
-        WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_location);
-        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
-        WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, tmp);
+        WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start);
+        WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end);
 
         /* enable first context */
-        WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_location);
-        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
-        WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, tmp);
-        WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL,
-                 (RS600_ENABLE_PAGE_TABLE | RS600_PAGE_TABLE_TYPE_FLAT));
+        WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
+        WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
+        WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
+                        S_000102_ENABLE_PAGE_TABLE(1) |
+                        S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
         /* disable all other contexts */
         for (i = 1; i < 8; i++) {
-                WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
+                WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
         }
 
         /* setup the page table */
-        WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
-                 rdev->gart.table_addr);
-        WREG32_MC(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
+        WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
+                        rdev->gart.table_addr);
+        WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 
         /* enable page tables */
-        tmp = RREG32_MC(RS600_MC_PT0_CNTL);
-        WREG32_MC(RS600_MC_PT0_CNTL, (tmp | RS600_ENABLE_PT));
-        tmp = RREG32_MC(RS600_MC_CNTL1);
-        WREG32_MC(RS600_MC_CNTL1, (tmp | RS600_ENABLE_PAGE_TABLES));
+        tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
+        WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
+        tmp = RREG32_MC(R_000009_MC_CNTL1);
+        WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
         rs600_gart_tlb_flush(rdev);
         rdev->gart.ready = true;
         return 0;
@@ -146,10 +149,9 @@ void rs600_gart_disable(struct radeon_device *rdev)
         uint32_t tmp;
 
         /* FIXME: disable out of gart access */
-        WREG32_MC(RS600_MC_PT0_CNTL, 0);
-        tmp = RREG32_MC(RS600_MC_CNTL1);
-        tmp &= ~RS600_ENABLE_PAGE_TABLES;
-        WREG32_MC(RS600_MC_CNTL1, tmp);
+        WREG32_MC(R_000100_MC_PT0_CNTL, 0);
+        tmp = RREG32_MC(R_000009_MC_CNTL1);
+        WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
         if (rdev->gart.table.vram.robj) {
                 radeon_object_kunmap(rdev->gart.table.vram.robj);
                 radeon_object_unpin(rdev->gart.table.vram.robj);
@@ -183,129 +185,61 @@ int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
         return 0;
 }
 
-
-/*
- * MC.
- */
-void rs600_mc_disable_clients(struct radeon_device *rdev)
-{
-        unsigned tmp;
-
-        if (r100_gui_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "Failed to wait GUI idle while "
-                       "programming pipes. Bad things might happen.\n");
-        }
-
-        rv515_vga_render_disable(rdev);
-
-        tmp = RREG32(AVIVO_D1VGA_CONTROL);
-        WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
-        tmp = RREG32(AVIVO_D2VGA_CONTROL);
-        WREG32(AVIVO_D2VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
-
-        tmp = RREG32(AVIVO_D1CRTC_CONTROL);
-        WREG32(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
-        tmp = RREG32(AVIVO_D2CRTC_CONTROL);
-        WREG32(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
-
-        /* make sure all previous write got through */
-        tmp = RREG32(AVIVO_D2CRTC_CONTROL);
-
-        mdelay(1);
-}
-
-int rs600_mc_init(struct radeon_device *rdev)
-{
-        uint32_t tmp;
-        int r;
-
-        if (r100_debugfs_rbbm_init(rdev)) {
-                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
-        }
-
-        rs600_gpu_init(rdev);
-        rs600_gart_disable(rdev);
-
-        /* Setup GPU memory space */
-        rdev->mc.vram_location = 0xFFFFFFFFUL;
-        rdev->mc.gtt_location = 0xFFFFFFFFUL;
-        r = radeon_mc_setup(rdev);
-        if (r) {
-                return r;
-        }
-
-        /* Program GPU memory space */
-        /* Enable bus master */
-        tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
-        WREG32(RADEON_BUS_CNTL, tmp);
-        /* FIXME: What does AGP means for such chipset ? */
-        WREG32_MC(RS600_MC_AGP_LOCATION, 0x0FFFFFFF);
-        /* FIXME: are this AGP reg in indirect MC range ? */
-        WREG32_MC(RS600_MC_AGP_BASE, 0);
-        WREG32_MC(RS600_MC_AGP_BASE_2, 0);
-        rs600_mc_disable_clients(rdev);
-        if (rs600_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "Failed to wait MC idle while "
-                       "programming pipes. Bad things might happen.\n");
-        }
-        tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
-        tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16);
-        tmp |= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16);
-        WREG32_MC(RS600_MC_FB_LOCATION, tmp);
-        WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
-        return 0;
-}
-
-void rs600_mc_fini(struct radeon_device *rdev)
-{
-}
-
-
-/*
- * Interrupts
- */
 int rs600_irq_set(struct radeon_device *rdev)
 {
         uint32_t tmp = 0;
         uint32_t mode_int = 0;
 
         if (rdev->irq.sw_int) {
-                tmp |= RADEON_SW_INT_ENABLE;
+                tmp |= S_000040_SW_INT_EN(1);
         }
         if (rdev->irq.crtc_vblank_int[0]) {
-                mode_int |= AVIVO_D1MODE_INT_MASK;
+                mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
         }
         if (rdev->irq.crtc_vblank_int[1]) {
-                mode_int |= AVIVO_D2MODE_INT_MASK;
+                mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
         }
-        WREG32(RADEON_GEN_INT_CNTL, tmp);
-        WREG32(AVIVO_DxMODE_INT_MASK, mode_int);
+        WREG32(R_000040_GEN_INT_CNTL, tmp);
+        WREG32(R_006540_DxMODE_INT_MASK, mode_int);
         return 0;
 }
 
 static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
 {
-        uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
-        uint32_t irq_mask = RADEON_SW_INT_TEST;
-
-        if (irqs & AVIVO_DISPLAY_INT_STATUS) {
-                *r500_disp_int = RREG32(AVIVO_DISP_INTERRUPT_STATUS);
-                if (*r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
-                        WREG32(AVIVO_D1MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
+        uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
+        uint32_t irq_mask = ~C_000044_SW_INT;
+
+        if (G_000044_DISPLAY_INT_STAT(irqs)) {
+                *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
+                if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
+                        WREG32(R_006534_D1MODE_VBLANK_STATUS,
+                                S_006534_D1MODE_VBLANK_ACK(1));
                 }
-                if (*r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
-                        WREG32(AVIVO_D2MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
+                if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
+                        WREG32(R_006D34_D2MODE_VBLANK_STATUS,
+                                S_006D34_D2MODE_VBLANK_ACK(1));
                 }
         } else {
                 *r500_disp_int = 0;
         }
 
         if (irqs) {
-                WREG32(RADEON_GEN_INT_STATUS, irqs);
+                WREG32(R_000044_GEN_INT_STATUS, irqs);
         }
         return irqs & irq_mask;
 }
 
+void rs600_irq_disable(struct radeon_device *rdev)
+{
+        u32 tmp;
+
+        WREG32(R_000040_GEN_INT_CNTL, 0);
+        WREG32(R_006540_DxMODE_INT_MASK, 0);
+        /* Wait and acknowledge irq */
+        mdelay(1);
+        rs600_irq_ack(rdev, &tmp);
+}
+
 int rs600_irq_process(struct radeon_device *rdev)
 {
         uint32_t status;
@@ -317,16 +251,13 @@ int rs600_irq_process(struct radeon_device *rdev)
         }
         while (status || r500_disp_int) {
                 /* SW interrupt */
-                if (status & RADEON_SW_INT_TEST) {
+                if (G_000040_SW_INT_EN(status))
                         radeon_fence_process(rdev);
-                }
                 /* Vertical blank interrupts */
-                if (r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
+                if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int))
                         drm_handle_vblank(rdev->ddev, 0);
-                }
-                if (r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
+                if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int))
                         drm_handle_vblank(rdev->ddev, 1);
-                }
                 status = rs600_irq_ack(rdev, &r500_disp_int);
         }
         return IRQ_HANDLED;
@@ -335,53 +266,34 @@ int rs600_irq_process(struct radeon_device *rdev)
 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
 {
         if (crtc == 0)
-                return RREG32(AVIVO_D1CRTC_FRAME_COUNT);
+                return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
         else
-                return RREG32(AVIVO_D2CRTC_FRAME_COUNT);
+                return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
 }
 
-
-/*
- * Global GPU functions
- */
 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
 {
         unsigned i;
-        uint32_t tmp;
 
         for (i = 0; i < rdev->usec_timeout; i++) {
-                /* read MC_STATUS */
-                tmp = RREG32_MC(RS600_MC_STATUS);
-                if (tmp & RS600_MC_STATUS_IDLE) {
+                if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
                         return 0;
-                }
-                DRM_UDELAY(1);
+                udelay(1);
         }
         return -1;
 }
 
-void rs600_errata(struct radeon_device *rdev)
-{
-        rdev->pll_errata = 0;
-}
-
 void rs600_gpu_init(struct radeon_device *rdev)
 {
         /* FIXME: HDP same place on rs600 ? */
         r100_hdp_reset(rdev);
-        rv515_vga_render_disable(rdev);
         /* FIXME: is this correct ? */
         r420_pipes_init(rdev);
-        if (rs600_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "Failed to wait MC idle while "
-                       "programming pipes. Bad things might happen.\n");
-        }
+        /* Wait for mc idle */
+        if (rs600_mc_wait_for_idle(rdev))
+                dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 }
 
-
-/*
- * VRAM info.
- */
 void rs600_vram_info(struct radeon_device *rdev)
 {
         /* FIXME: to do or is these values sane ? */
@@ -394,31 +306,206 @@ void rs600_bandwidth_update(struct radeon_device *rdev)
         /* FIXME: implement, should this be like rs690 ? */
 }
 
-
-/*
- * Indirect registers accessor
- */
 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 {
-        uint32_t r;
-
-        WREG32(RS600_MC_INDEX,
-               ((reg & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0));
-        r = RREG32(RS600_MC_DATA);
-        return r;
+        WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
+                S_000070_MC_IND_CITF_ARB0(1));
+        return RREG32(R_000074_MC_IND_DATA);
 }
 
 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 {
-        WREG32(RS600_MC_INDEX,
-                RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 |
-                ((reg) & RS600_MC_ADDR_MASK));
-        WREG32(RS600_MC_DATA, v);
+        WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
+                S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
+        WREG32(R_000074_MC_IND_DATA, v);
 }
 
-int rs600_init(struct radeon_device *rdev)
+void rs600_debugfs(struct radeon_device *rdev)
+{
+        if (r100_debugfs_rbbm_init(rdev))
+                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
+}
+
+void rs600_set_safe_registers(struct radeon_device *rdev)
 {
         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
+}
+
+static void rs600_mc_program(struct radeon_device *rdev)
+{
+        struct rv515_mc_save save;
+
+        /* Stops all mc clients */
+        rv515_mc_stop(rdev, &save);
+
+        /* Wait for mc idle */
+        if (rs600_mc_wait_for_idle(rdev))
+                dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
+
+        /* FIXME: What does AGP means for such chipset ? */
+        WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
+        WREG32_MC(R_000006_AGP_BASE, 0);
+        WREG32_MC(R_000007_AGP_BASE_2, 0);
+        /* Program MC */
+        WREG32_MC(R_000004_MC_FB_LOCATION,
+                        S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
+                        S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
+        WREG32(R_000134_HDP_FB_LOCATION,
+                S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
+
+        rv515_mc_resume(rdev, &save);
+}
+
+static int rs600_startup(struct radeon_device *rdev)
+{
+        int r;
+
+        rs600_mc_program(rdev);
+        /* Resume clock */
+        rv515_clock_startup(rdev);
+        /* Initialize GPU configuration (# pipes, ...) */
+        rs600_gpu_init(rdev);
+        /* Initialize GART (initialize after TTM so we can allocate
+         * memory through TTM but finalize after TTM) */
+        r = rs600_gart_enable(rdev);
+        if (r)
+                return r;
+        /* Enable IRQ */
+        rdev->irq.sw_int = true;
+        rs600_irq_set(rdev);
+        /* 1M ring buffer */
+        r = r100_cp_init(rdev, 1024 * 1024);
+        if (r) {
+                dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
+                return r;
+        }
+        r = r100_wb_init(rdev);
+        if (r)
+                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
+        r = r100_ib_init(rdev);
+        if (r) {
+                dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
+                return r;
+        }
+        return 0;
+}
+
+int rs600_resume(struct radeon_device *rdev)
+{
+        /* Make sur GART are not working */
+        rs600_gart_disable(rdev);
+        /* Resume clock before doing reset */
+        rv515_clock_startup(rdev);
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* post */
+        atom_asic_init(rdev->mode_info.atom_context);
+        /* Resume clock after posting */
+        rv515_clock_startup(rdev);
+        return rs600_startup(rdev);
+}
+
+int rs600_suspend(struct radeon_device *rdev)
+{
+        r100_cp_disable(rdev);
+        r100_wb_disable(rdev);
+        rs600_irq_disable(rdev);
+        rs600_gart_disable(rdev);
+        return 0;
+}
+
+void rs600_fini(struct radeon_device *rdev)
+{
+        rs600_suspend(rdev);
+        r100_cp_fini(rdev);
+        r100_wb_fini(rdev);
+        r100_ib_fini(rdev);
+        radeon_gem_fini(rdev);
+        rs600_gart_fini(rdev);
+        radeon_irq_kms_fini(rdev);
+        radeon_fence_driver_fini(rdev);
+        radeon_object_fini(rdev);
+        radeon_atombios_fini(rdev);
+        kfree(rdev->bios);
+        rdev->bios = NULL;
+}
+
+int rs600_init(struct radeon_device *rdev)
+{
+        int r;
+
+        /* Disable VGA */
+        rv515_vga_render_disable(rdev);
+        /* Initialize scratch registers */
+        radeon_scratch_init(rdev);
+        /* Initialize surface registers */
+        radeon_surface_init(rdev);
+        /* BIOS */
+        if (!radeon_get_bios(rdev)) {
+                if (ASIC_IS_AVIVO(rdev))
+                        return -EINVAL;
+        }
+        if (rdev->is_atom_bios) {
+                r = radeon_atombios_init(rdev);
+                if (r)
+                        return r;
+        } else {
+                dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
+                return -EINVAL;
+        }
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev,
+                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* check if cards are posted or not */
+        if (!radeon_card_posted(rdev) && rdev->bios) {
+                DRM_INFO("GPU not posted. posting now...\n");
+                atom_asic_init(rdev->mode_info.atom_context);
+        }
+        /* Initialize clocks */
+        radeon_get_clock_info(rdev->ddev);
+        /* Get vram informations */
+        rs600_vram_info(rdev);
+        /* Initialize memory controller (also test AGP) */
+        r = r420_mc_init(rdev);
+        if (r)
+                return r;
+        rs600_debugfs(rdev);
+        /* Fence driver */
+        r = radeon_fence_driver_init(rdev);
+        if (r)
+                return r;
+        r = radeon_irq_kms_init(rdev);
+        if (r)
+                return r;
+        /* Memory manager */
+        r = radeon_object_init(rdev);
+        if (r)
+                return r;
+        r = rs600_gart_init(rdev);
+        if (r)
+                return r;
+        rs600_set_safe_registers(rdev);
+        rdev->accel_working = true;
+        r = rs600_startup(rdev);
+        if (r) {
+                /* Somethings want wront with the accel init stop accel */
+                dev_err(rdev->dev, "Disabling GPU acceleration\n");
+                rs600_suspend(rdev);
+                r100_cp_fini(rdev);
+                r100_wb_fini(rdev);
+                r100_ib_fini(rdev);
+                rs600_gart_fini(rdev);
+                radeon_irq_kms_fini(rdev);
+                rdev->accel_working = false;
+        }
         return 0;
 }
diff --git a/drivers/gpu/drm/radeon/rs600d.h b/drivers/gpu/drm/radeon/rs600d.h
new file mode 100644
index 000000000000..81308924859a
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rs600d.h
@@ -0,0 +1,470 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __RS600D_H__
+#define __RS600D_H__
+
+/* Registers */
+#define R_000040_GEN_INT_CNTL                        0x000040
+#define   S_000040_DISPLAY_INT_STATUS(x)               (((x) & 0x1) << 0)
+#define   G_000040_DISPLAY_INT_STATUS(x)               (((x) >> 0) & 0x1)
+#define   C_000040_DISPLAY_INT_STATUS                  0xFFFFFFFE
+#define   S_000040_DMA_VIPH0_INT_EN(x)                 (((x) & 0x1) << 12)
+#define   G_000040_DMA_VIPH0_INT_EN(x)                 (((x) >> 12) & 0x1)
+#define   C_000040_DMA_VIPH0_INT_EN                    0xFFFFEFFF
+#define   S_000040_CRTC2_VSYNC(x)                      (((x) & 0x1) << 6)
+#define   G_000040_CRTC2_VSYNC(x)                      (((x) >> 6) & 0x1)
+#define   C_000040_CRTC2_VSYNC                         0xFFFFFFBF
+#define   S_000040_SNAPSHOT2(x)                        (((x) & 0x1) << 7)
+#define   G_000040_SNAPSHOT2(x)                        (((x) >> 7) & 0x1)
+#define   C_000040_SNAPSHOT2                           0xFFFFFF7F
+#define   S_000040_CRTC2_VBLANK(x)                     (((x) & 0x1) << 9)
+#define   G_000040_CRTC2_VBLANK(x)                     (((x) >> 9) & 0x1)
+#define   C_000040_CRTC2_VBLANK                        0xFFFFFDFF
+#define   S_000040_FP2_DETECT(x)                       (((x) & 0x1) << 10)
+#define   G_000040_FP2_DETECT(x)                       (((x) >> 10) & 0x1)
+#define   C_000040_FP2_DETECT                          0xFFFFFBFF
+#define   S_000040_VSYNC_DIFF_OVER_LIMIT(x)            (((x) & 0x1) << 11)
+#define   G_000040_VSYNC_DIFF_OVER_LIMIT(x)            (((x) >> 11) & 0x1)
+#define   C_000040_VSYNC_DIFF_OVER_LIMIT               0xFFFFF7FF
+#define   S_000040_DMA_VIPH1_INT_EN(x)                 (((x) & 0x1) << 13)
+#define   G_000040_DMA_VIPH1_INT_EN(x)                 (((x) >> 13) & 0x1)
+#define   C_000040_DMA_VIPH1_INT_EN                    0xFFFFDFFF
+#define   S_000040_DMA_VIPH2_INT_EN(x)                 (((x) & 0x1) << 14)
+#define   G_000040_DMA_VIPH2_INT_EN(x)                 (((x) >> 14) & 0x1)
+#define   C_000040_DMA_VIPH2_INT_EN                    0xFFFFBFFF
+#define   S_000040_DMA_VIPH3_INT_EN(x)                 (((x) & 0x1) << 15)
+#define   G_000040_DMA_VIPH3_INT_EN(x)                 (((x) >> 15) & 0x1)
+#define   C_000040_DMA_VIPH3_INT_EN                    0xFFFF7FFF
+#define   S_000040_I2C_INT_EN(x)                       (((x) & 0x1) << 17)
+#define   G_000040_I2C_INT_EN(x)                       (((x) >> 17) & 0x1)
+#define   C_000040_I2C_INT_EN                          0xFFFDFFFF
+#define   S_000040_GUI_IDLE(x)                         (((x) & 0x1) << 19)
+#define   G_000040_GUI_IDLE(x)                         (((x) >> 19) & 0x1)
+#define   C_000040_GUI_IDLE                            0xFFF7FFFF
+#define   S_000040_VIPH_INT_EN(x)                      (((x) & 0x1) << 24)
+#define   G_000040_VIPH_INT_EN(x)                      (((x) >> 24) & 0x1)
+#define   C_000040_VIPH_INT_EN                         0xFEFFFFFF
+#define   S_000040_SW_INT_EN(x)                        (((x) & 0x1) << 25)
+#define   G_000040_SW_INT_EN(x)                        (((x) >> 25) & 0x1)
+#define   C_000040_SW_INT_EN                           0xFDFFFFFF
+#define   S_000040_GEYSERVILLE(x)                      (((x) & 0x1) << 27)
+#define   G_000040_GEYSERVILLE(x)                      (((x) >> 27) & 0x1)
+#define   C_000040_GEYSERVILLE                         0xF7FFFFFF
+#define   S_000040_HDCP_AUTHORIZED_INT(x)              (((x) & 0x1) << 28)
+#define   G_000040_HDCP_AUTHORIZED_INT(x)              (((x) >> 28) & 0x1)
+#define   C_000040_HDCP_AUTHORIZED_INT                 0xEFFFFFFF
+#define   S_000040_DVI_I2C_INT(x)                      (((x) & 0x1) << 29)
+#define   G_000040_DVI_I2C_INT(x)                      (((x) >> 29) & 0x1)
+#define   C_000040_DVI_I2C_INT                         0xDFFFFFFF
+#define   S_000040_GUIDMA(x)                           (((x) & 0x1) << 30)
+#define   G_000040_GUIDMA(x)                           (((x) >> 30) & 0x1)
+#define   C_000040_GUIDMA                              0xBFFFFFFF
+#define   S_000040_VIDDMA(x)                           (((x) & 0x1) << 31)
+#define   G_000040_VIDDMA(x)                           (((x) >> 31) & 0x1)
+#define   C_000040_VIDDMA                              0x7FFFFFFF
+#define R_000044_GEN_INT_STATUS                      0x000044
+#define   S_000044_DISPLAY_INT_STAT(x)                 (((x) & 0x1) << 0)
+#define   G_000044_DISPLAY_INT_STAT(x)                 (((x) >> 0) & 0x1)
+#define   C_000044_DISPLAY_INT_STAT                    0xFFFFFFFE
+#define   S_000044_VGA_INT_STAT(x)                     (((x) & 0x1) << 1)
+#define   G_000044_VGA_INT_STAT(x)                     (((x) >> 1) & 0x1)
+#define   C_000044_VGA_INT_STAT                        0xFFFFFFFD
+#define   S_000044_CAP0_INT_ACTIVE(x)                  (((x) & 0x1) << 8)
+#define   G_000044_CAP0_INT_ACTIVE(x)                  (((x) >> 8) & 0x1)
+#define   C_000044_CAP0_INT_ACTIVE                     0xFFFFFEFF
+#define   S_000044_DMA_VIPH0_INT(x)                    (((x) & 0x1) << 12)
+#define   G_000044_DMA_VIPH0_INT(x)                    (((x) >> 12) & 0x1)
+#define   C_000044_DMA_VIPH0_INT                       0xFFFFEFFF
+#define   S_000044_DMA_VIPH1_INT(x)                    (((x) & 0x1) << 13)
+#define   G_000044_DMA_VIPH1_INT(x)                    (((x) >> 13) & 0x1)
+#define   C_000044_DMA_VIPH1_INT                       0xFFFFDFFF
+#define   S_000044_DMA_VIPH2_INT(x)                    (((x) & 0x1) << 14)
+#define   G_000044_DMA_VIPH2_INT(x)                    (((x) >> 14) & 0x1)
+#define   C_000044_DMA_VIPH2_INT                       0xFFFFBFFF
+#define   S_000044_DMA_VIPH3_INT(x)                    (((x) & 0x1) << 15)
+#define   G_000044_DMA_VIPH3_INT(x)                    (((x) >> 15) & 0x1)
+#define   C_000044_DMA_VIPH3_INT                       0xFFFF7FFF
+#define   S_000044_MC_PROBE_FAULT_STAT(x)              (((x) & 0x1) << 16)
+#define   G_000044_MC_PROBE_FAULT_STAT(x)              (((x) >> 16) & 0x1)
+#define   C_000044_MC_PROBE_FAULT_STAT                 0xFFFEFFFF
+#define   S_000044_I2C_INT(x)                          (((x) & 0x1) << 17)
+#define   G_000044_I2C_INT(x)                          (((x) >> 17) & 0x1)
+#define   C_000044_I2C_INT                             0xFFFDFFFF
+#define   S_000044_SCRATCH_INT_STAT(x)                 (((x) & 0x1) << 18)
+#define   G_000044_SCRATCH_INT_STAT(x)                 (((x) >> 18) & 0x1)
+#define   C_000044_SCRATCH_INT_STAT                    0xFFFBFFFF
+#define   S_000044_GUI_IDLE_STAT(x)                    (((x) & 0x1) << 19)
+#define   G_000044_GUI_IDLE_STAT(x)                    (((x) >> 19) & 0x1)
+#define   C_000044_GUI_IDLE_STAT                       0xFFF7FFFF
+#define   S_000044_ATI_OVERDRIVE_INT_STAT(x)           (((x) & 0x1) << 20)
+#define   G_000044_ATI_OVERDRIVE_INT_STAT(x)           (((x) >> 20) & 0x1)
+#define   C_000044_ATI_OVERDRIVE_INT_STAT              0xFFEFFFFF
+#define   S_000044_MC_PROTECTION_FAULT_STAT(x)         (((x) & 0x1) << 21)
+#define   G_000044_MC_PROTECTION_FAULT_STAT(x)         (((x) >> 21) & 0x1)
+#define   C_000044_MC_PROTECTION_FAULT_STAT            0xFFDFFFFF
+#define   S_000044_RBBM_READ_INT_STAT(x)               (((x) & 0x1) << 22)
+#define   G_000044_RBBM_READ_INT_STAT(x)               (((x) >> 22) & 0x1)
+#define   C_000044_RBBM_READ_INT_STAT                  0xFFBFFFFF
+#define   S_000044_CB_CONTEXT_SWITCH_STAT(x)           (((x) & 0x1) << 23)
+#define   G_000044_CB_CONTEXT_SWITCH_STAT(x)           (((x) >> 23) & 0x1)
+#define   C_000044_CB_CONTEXT_SWITCH_STAT              0xFF7FFFFF
+#define   S_000044_VIPH_INT(x)                         (((x) & 0x1) << 24)
+#define   G_000044_VIPH_INT(x)                         (((x) >> 24) & 0x1)
+#define   C_000044_VIPH_INT                            0xFEFFFFFF
+#define   S_000044_SW_INT(x)                           (((x) & 0x1) << 25)
+#define   G_000044_SW_INT(x)                           (((x) >> 25) & 0x1)
+#define   C_000044_SW_INT                              0xFDFFFFFF
+#define   S_000044_SW_INT_SET(x)                       (((x) & 0x1) << 26)
+#define   G_000044_SW_INT_SET(x)                       (((x) >> 26) & 0x1)
+#define   C_000044_SW_INT_SET                          0xFBFFFFFF
+#define   S_000044_IDCT_INT_STAT(x)                    (((x) & 0x1) << 27)
+#define   G_000044_IDCT_INT_STAT(x)                    (((x) >> 27) & 0x1)
+#define   C_000044_IDCT_INT_STAT                       0xF7FFFFFF
+#define   S_000044_GUIDMA_STAT(x)                      (((x) & 0x1) << 30)
+#define   G_000044_GUIDMA_STAT(x)                      (((x) >> 30) & 0x1)
+#define   C_000044_GUIDMA_STAT                         0xBFFFFFFF
+#define   S_000044_VIDDMA_STAT(x)                      (((x) & 0x1) << 31)
+#define   G_000044_VIDDMA_STAT(x)                      (((x) >> 31) & 0x1)
+#define   C_000044_VIDDMA_STAT                         0x7FFFFFFF
+#define R_00004C_BUS_CNTL                            0x00004C
+#define   S_00004C_BUS_MASTER_DIS(x)                   (((x) & 0x1) << 14)
+#define   G_00004C_BUS_MASTER_DIS(x)                   (((x) >> 14) & 0x1)
+#define   C_00004C_BUS_MASTER_DIS                      0xFFFFBFFF
+#define   S_00004C_BUS_MSI_REARM(x)                    (((x) & 0x1) << 20)
+#define   G_00004C_BUS_MSI_REARM(x)                    (((x) >> 20) & 0x1)
+#define   C_00004C_BUS_MSI_REARM                       0xFFEFFFFF
+#define R_000070_MC_IND_INDEX                        0x000070
+#define   S_000070_MC_IND_ADDR(x)                      (((x) & 0xFFFF) << 0)
+#define   G_000070_MC_IND_ADDR(x)                      (((x) >> 0) & 0xFFFF)
+#define   C_000070_MC_IND_ADDR                         0xFFFF0000
+#define   S_000070_MC_IND_SEQ_RBS_0(x)                 (((x) & 0x1) << 16)
+#define   G_000070_MC_IND_SEQ_RBS_0(x)                 (((x) >> 16) & 0x1)
+#define   C_000070_MC_IND_SEQ_RBS_0                    0xFFFEFFFF
+#define   S_000070_MC_IND_SEQ_RBS_1(x)                 (((x) & 0x1) << 17)
+#define   G_000070_MC_IND_SEQ_RBS_1(x)                 (((x) >> 17) & 0x1)
+#define   C_000070_MC_IND_SEQ_RBS_1                    0xFFFDFFFF
+#define   S_000070_MC_IND_SEQ_RBS_2(x)                 (((x) & 0x1) << 18)
+#define   G_000070_MC_IND_SEQ_RBS_2(x)                 (((x) >> 18) & 0x1)
+#define   C_000070_MC_IND_SEQ_RBS_2                    0xFFFBFFFF
+#define   S_000070_MC_IND_SEQ_RBS_3(x)                 (((x) & 0x1) << 19)
+#define   G_000070_MC_IND_SEQ_RBS_3(x)                 (((x) >> 19) & 0x1)
+#define   C_000070_MC_IND_SEQ_RBS_3                    0xFFF7FFFF
+#define   S_000070_MC_IND_AIC_RBS(x)                   (((x) & 0x1) << 20)
+#define   G_000070_MC_IND_AIC_RBS(x)                   (((x) >> 20) & 0x1)
+#define   C_000070_MC_IND_AIC_RBS                      0xFFEFFFFF
+#define   S_000070_MC_IND_CITF_ARB0(x)                 (((x) & 0x1) << 21)
+#define   G_000070_MC_IND_CITF_ARB0(x)                 (((x) >> 21) & 0x1)
+#define   C_000070_MC_IND_CITF_ARB0                    0xFFDFFFFF
+#define   S_000070_MC_IND_CITF_ARB1(x)                 (((x) & 0x1) << 22)
+#define   G_000070_MC_IND_CITF_ARB1(x)                 (((x) >> 22) & 0x1)
+#define   C_000070_MC_IND_CITF_ARB1                    0xFFBFFFFF
+#define   S_000070_MC_IND_WR_EN(x)                     (((x) & 0x1) << 23)
+#define   G_000070_MC_IND_WR_EN(x)                     (((x) >> 23) & 0x1)
+#define   C_000070_MC_IND_WR_EN                        0xFF7FFFFF
+#define   S_000070_MC_IND_RD_INV(x)                    (((x) & 0x1) << 24)
+#define   G_000070_MC_IND_RD_INV(x)                    (((x) >> 24) & 0x1)
+#define   C_000070_MC_IND_RD_INV                       0xFEFFFFFF
+#define R_000074_MC_IND_DATA                         0x000074
+#define   S_000074_MC_IND_DATA(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_000074_MC_IND_DATA(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_000074_MC_IND_DATA                         0x00000000
+#define R_000134_HDP_FB_LOCATION                     0x000134
+#define   S_000134_HDP_FB_START(x)                     (((x) & 0xFFFF) << 0)
+#define   G_000134_HDP_FB_START(x)                     (((x) >> 0) & 0xFFFF)
+#define   C_000134_HDP_FB_START                        0xFFFF0000
+#define R_0007C0_CP_STAT                             0x0007C0
+#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
+#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
+#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
+#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
+#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
+#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
+#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
+#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
+#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
+#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
+#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
+#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
+#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
+#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
+#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
+#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
+#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
+#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
+#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
+#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
+#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
+#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
+#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
+#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
+#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
+#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
+#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
+#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
+#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
+#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
+#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
+#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
+#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
+#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
+#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
+#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
+#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
+#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
+#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
+#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
+#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
+#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
+#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
+#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
+#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
+#define R_000E40_RBBM_STATUS                         0x000E40
+#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
+#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
+#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
+#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
+#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
+#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
+#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
+#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
+#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
+#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
+#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
+#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
+#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
+#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
+#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
+#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
+#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
+#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
+#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
+#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
+#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
+#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
+#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
+#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
+#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
+#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
+#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
+#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
+#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
+#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
+#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
+#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
+#define   C_000E40_E2_BUSY                             0xFFFDFFFF
+#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
+#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
+#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
+#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
+#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
+#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
+#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
+#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
+#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
+#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
+#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
+#define   C_000E40_RE_BUSY                             0xFFDFFFFF
+#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
+#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
+#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
+#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
+#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
+#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
+#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
+#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
+#define   C_000E40_PB_BUSY                             0xFEFFFFFF
+#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
+#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
+#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
+#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
+#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
+#define   C_000E40_GA_BUSY                             0xFBFFFFFF
+#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
+#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
+#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
+#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
+#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
+#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
+#define R_0060A4_D1CRTC_STATUS_FRAME_COUNT           0x0060A4
+#define   S_0060A4_D1CRTC_FRAME_COUNT(x)               (((x) & 0xFFFFFF) << 0)
+#define   G_0060A4_D1CRTC_FRAME_COUNT(x)               (((x) >> 0) & 0xFFFFFF)
+#define   C_0060A4_D1CRTC_FRAME_COUNT                  0xFF000000
+#define R_006534_D1MODE_VBLANK_STATUS                0x006534
+#define   S_006534_D1MODE_VBLANK_OCCURRED(x)           (((x) & 0x1) << 0)
+#define   G_006534_D1MODE_VBLANK_OCCURRED(x)           (((x) >> 0) & 0x1)
+#define   C_006534_D1MODE_VBLANK_OCCURRED              0xFFFFFFFE
+#define   S_006534_D1MODE_VBLANK_ACK(x)                (((x) & 0x1) << 4)
+#define   G_006534_D1MODE_VBLANK_ACK(x)                (((x) >> 4) & 0x1)
+#define   C_006534_D1MODE_VBLANK_ACK                   0xFFFFFFEF
+#define   S_006534_D1MODE_VBLANK_STAT(x)               (((x) & 0x1) << 12)
+#define   G_006534_D1MODE_VBLANK_STAT(x)               (((x) >> 12) & 0x1)
+#define   C_006534_D1MODE_VBLANK_STAT                  0xFFFFEFFF
+#define   S_006534_D1MODE_VBLANK_INTERRUPT(x)          (((x) & 0x1) << 16)
+#define   G_006534_D1MODE_VBLANK_INTERRUPT(x)          (((x) >> 16) & 0x1)
+#define   C_006534_D1MODE_VBLANK_INTERRUPT             0xFFFEFFFF
+#define R_006540_DxMODE_INT_MASK                     0x006540
+#define   S_006540_D1MODE_VBLANK_INT_MASK(x)           (((x) & 0x1) << 0)
+#define   G_006540_D1MODE_VBLANK_INT_MASK(x)           (((x) >> 0) & 0x1)
+#define   C_006540_D1MODE_VBLANK_INT_MASK              0xFFFFFFFE
+#define   S_006540_D1MODE_VLINE_INT_MASK(x)            (((x) & 0x1) << 4)
+#define   G_006540_D1MODE_VLINE_INT_MASK(x)            (((x) >> 4) & 0x1)
+#define   C_006540_D1MODE_VLINE_INT_MASK               0xFFFFFFEF
+#define   S_006540_D2MODE_VBLANK_INT_MASK(x)           (((x) & 0x1) << 8)
+#define   G_006540_D2MODE_VBLANK_INT_MASK(x)           (((x) >> 8) & 0x1)
+#define   C_006540_D2MODE_VBLANK_INT_MASK              0xFFFFFEFF
+#define   S_006540_D2MODE_VLINE_INT_MASK(x)            (((x) & 0x1) << 12)
+#define   G_006540_D2MODE_VLINE_INT_MASK(x)            (((x) >> 12) & 0x1)
+#define   C_006540_D2MODE_VLINE_INT_MASK               0xFFFFEFFF
+#define   S_006540_D1MODE_VBLANK_CP_SEL(x)             (((x) & 0x1) << 30)
+#define   G_006540_D1MODE_VBLANK_CP_SEL(x)             (((x) >> 30) & 0x1)
+#define   C_006540_D1MODE_VBLANK_CP_SEL                0xBFFFFFFF
+#define   S_006540_D2MODE_VBLANK_CP_SEL(x)             (((x) & 0x1) << 31)
+#define   G_006540_D2MODE_VBLANK_CP_SEL(x)             (((x) >> 31) & 0x1)
+#define   C_006540_D2MODE_VBLANK_CP_SEL                0x7FFFFFFF
+#define R_0068A4_D2CRTC_STATUS_FRAME_COUNT           0x0068A4
+#define   S_0068A4_D2CRTC_FRAME_COUNT(x)               (((x) & 0xFFFFFF) << 0)
+#define   G_0068A4_D2CRTC_FRAME_COUNT(x)               (((x) >> 0) & 0xFFFFFF)
+#define   C_0068A4_D2CRTC_FRAME_COUNT                  0xFF000000
+#define R_006D34_D2MODE_VBLANK_STATUS                0x006D34
+#define   S_006D34_D2MODE_VBLANK_OCCURRED(x)           (((x) & 0x1) << 0)
+#define   G_006D34_D2MODE_VBLANK_OCCURRED(x)           (((x) >> 0) & 0x1)
+#define   C_006D34_D2MODE_VBLANK_OCCURRED              0xFFFFFFFE
+#define   S_006D34_D2MODE_VBLANK_ACK(x)                (((x) & 0x1) << 4)
+#define   G_006D34_D2MODE_VBLANK_ACK(x)                (((x) >> 4) & 0x1)
+#define   C_006D34_D2MODE_VBLANK_ACK                   0xFFFFFFEF
+#define   S_006D34_D2MODE_VBLANK_STAT(x)               (((x) & 0x1) << 12)
+#define   G_006D34_D2MODE_VBLANK_STAT(x)               (((x) >> 12) & 0x1)
+#define   C_006D34_D2MODE_VBLANK_STAT                  0xFFFFEFFF
+#define   S_006D34_D2MODE_VBLANK_INTERRUPT(x)          (((x) & 0x1) << 16)
+#define   G_006D34_D2MODE_VBLANK_INTERRUPT(x)          (((x) >> 16) & 0x1)
+#define   C_006D34_D2MODE_VBLANK_INTERRUPT             0xFFFEFFFF
+#define R_007EDC_DISP_INTERRUPT_STATUS               0x007EDC
+#define   S_007EDC_LB_D1_VBLANK_INTERRUPT(x)           (((x) & 0x1) << 4)
+#define   G_007EDC_LB_D1_VBLANK_INTERRUPT(x)           (((x) >> 4) & 0x1)
+#define   C_007EDC_LB_D1_VBLANK_INTERRUPT              0xFFFFFFEF
+#define   S_007EDC_LB_D2_VBLANK_INTERRUPT(x)           (((x) & 0x1) << 5)
+#define   G_007EDC_LB_D2_VBLANK_INTERRUPT(x)           (((x) >> 5) & 0x1)
+#define   C_007EDC_LB_D2_VBLANK_INTERRUPT              0xFFFFFFDF
+
+
+/* MC registers */
+#define R_000000_MC_STATUS                           0x000000
+#define   S_000000_MC_IDLE(x)                          (((x) & 0x1) << 0)
+#define   G_000000_MC_IDLE(x)                          (((x) >> 0) & 0x1)
+#define   C_000000_MC_IDLE                             0xFFFFFFFE
+#define R_000004_MC_FB_LOCATION                      0x000004
+#define   S_000004_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
+#define   G_000004_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
+#define   C_000004_MC_FB_START                         0xFFFF0000
+#define   S_000004_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
+#define   G_000004_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
+#define   C_000004_MC_FB_TOP                           0x0000FFFF
+#define R_000005_MC_AGP_LOCATION                     0x000005
+#define   S_000005_MC_AGP_START(x)                     (((x) & 0xFFFF) << 0)
+#define   G_000005_MC_AGP_START(x)                     (((x) >> 0) & 0xFFFF)
+#define   C_000005_MC_AGP_START                        0xFFFF0000
+#define   S_000005_MC_AGP_TOP(x)                       (((x) & 0xFFFF) << 16)
+#define   G_000005_MC_AGP_TOP(x)                       (((x) >> 16) & 0xFFFF)
+#define   C_000005_MC_AGP_TOP                          0x0000FFFF
+#define R_000006_AGP_BASE                            0x000006
+#define   S_000006_AGP_BASE_ADDR(x)                    (((x) & 0xFFFFFFFF) << 0)
+#define   G_000006_AGP_BASE_ADDR(x)                    (((x) >> 0) & 0xFFFFFFFF)
+#define   C_000006_AGP_BASE_ADDR                       0x00000000
+#define R_000007_AGP_BASE_2                          0x000007
+#define   S_000007_AGP_BASE_ADDR_2(x)                  (((x) & 0xF) << 0)
+#define   G_000007_AGP_BASE_ADDR_2(x)                  (((x) >> 0) & 0xF)
+#define   C_000007_AGP_BASE_ADDR_2                     0xFFFFFFF0
+#define R_000009_MC_CNTL1                            0x000009
+#define   S_000009_ENABLE_PAGE_TABLES(x)               (((x) & 0x1) << 26)
+#define   G_000009_ENABLE_PAGE_TABLES(x)               (((x) >> 26) & 0x1)
+#define   C_000009_ENABLE_PAGE_TABLES                  0xFBFFFFFF
+/* FIXME don't know the various field size need feedback from AMD */
+#define R_000100_MC_PT0_CNTL                         0x000100
+#define   S_000100_ENABLE_PT(x)                        (((x) & 0x1) << 0)
+#define   G_000100_ENABLE_PT(x)                        (((x) >> 0) & 0x1)
+#define   C_000100_ENABLE_PT                           0xFFFFFFFE
+#define   S_000100_EFFECTIVE_L2_CACHE_SIZE(x)          (((x) & 0x7) << 15)
+#define   G_000100_EFFECTIVE_L2_CACHE_SIZE(x)          (((x) >> 15) & 0x7)
+#define   C_000100_EFFECTIVE_L2_CACHE_SIZE             0xFFFC7FFF
+#define   S_000100_EFFECTIVE_L2_QUEUE_SIZE(x)          (((x) & 0x7) << 21)
+#define   G_000100_EFFECTIVE_L2_QUEUE_SIZE(x)          (((x) >> 21) & 0x7)
+#define   C_000100_EFFECTIVE_L2_QUEUE_SIZE             0xFF1FFFFF
+#define   S_000100_INVALIDATE_ALL_L1_TLBS(x)           (((x) & 0x1) << 28)
+#define   G_000100_INVALIDATE_ALL_L1_TLBS(x)           (((x) >> 28) & 0x1)
+#define   C_000100_INVALIDATE_ALL_L1_TLBS              0xEFFFFFFF
+#define   S_000100_INVALIDATE_L2_CACHE(x)              (((x) & 0x1) << 29)
+#define   G_000100_INVALIDATE_L2_CACHE(x)              (((x) >> 29) & 0x1)
+#define   C_000100_INVALIDATE_L2_CACHE                 0xDFFFFFFF
+#define R_000102_MC_PT0_CONTEXT0_CNTL                0x000102
+#define   S_000102_ENABLE_PAGE_TABLE(x)                (((x) & 0x1) << 0)
+#define   G_000102_ENABLE_PAGE_TABLE(x)                (((x) >> 0) & 0x1)
+#define   C_000102_ENABLE_PAGE_TABLE                   0xFFFFFFFE
+#define   S_000102_PAGE_TABLE_DEPTH(x)                 (((x) & 0x3) << 1)
+#define   G_000102_PAGE_TABLE_DEPTH(x)                 (((x) >> 1) & 0x3)
+#define   C_000102_PAGE_TABLE_DEPTH                    0xFFFFFFF9
+#define   V_000102_PAGE_TABLE_FLAT                     0
+/* R600 documentation suggest that this should be a number of pages */
+#define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR     0x000112
+#define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR    0x000114
+#define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR   0x00011C
+#define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR      0x00012C
+#define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR     0x00013C
+#define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR       0x00014C
+#define R_00016C_MC_PT0_CLIENT0_CNTL                 0x00016C
+#define   S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 0)
+#define   G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 0) & 0x1)
+#define   C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE    0xFFFFFFFE
+#define   S_00016C_TRANSLATION_MODE_OVERRIDE(x)        (((x) & 0x1) << 1)
+#define   G_00016C_TRANSLATION_MODE_OVERRIDE(x)        (((x) >> 1) & 0x1)
+#define   C_00016C_TRANSLATION_MODE_OVERRIDE           0xFFFFFFFD
+#define   S_00016C_SYSTEM_ACCESS_MODE_MASK(x)          (((x) & 0x3) << 8)
+#define   G_00016C_SYSTEM_ACCESS_MODE_MASK(x)          (((x) >> 8) & 0x3)
+#define   C_00016C_SYSTEM_ACCESS_MODE_MASK             0xFFFFFCFF
+#define   V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY          0
+#define   V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP      1
+#define   V_00016C_SYSTEM_ACCESS_MODE_IN_SYS           2
+#define   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS       3
+#define   S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x)  (((x) & 0x1) << 10)
+#define   G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x)  (((x) >> 10) & 0x1)
+#define   C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS     0xFFFFFBFF
+#define   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH  0
+#define   V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE 1
+#define   S_00016C_EFFECTIVE_L1_CACHE_SIZE(x)          (((x) & 0x7) << 11)
+#define   G_00016C_EFFECTIVE_L1_CACHE_SIZE(x)          (((x) >> 11) & 0x7)
+#define   C_00016C_EFFECTIVE_L1_CACHE_SIZE             0xFFFFC7FF
+#define   S_00016C_ENABLE_FRAGMENT_PROCESSING(x)       (((x) & 0x1) << 14)
+#define   G_00016C_ENABLE_FRAGMENT_PROCESSING(x)       (((x) >> 14) & 0x1)
+#define   C_00016C_ENABLE_FRAGMENT_PROCESSING          0xFFFFBFFF
+#define   S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x)          (((x) & 0x7) << 15)
+#define   G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x)          (((x) >> 15) & 0x7)
+#define   C_00016C_EFFECTIVE_L1_QUEUE_SIZE             0xFFFC7FFF
+#define   S_00016C_INVALIDATE_L1_TLB(x)                (((x) & 0x1) << 20)
+#define   G_00016C_INVALIDATE_L1_TLB(x)                (((x) >> 20) & 0x1)
+#define   C_00016C_INVALIDATE_L1_TLB                   0xFFEFFFFF
+
+#endif
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 7a0098ddf977..025e3225346c 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -26,105 +26,29 @@
  *          Jerome Glisse
  */
 #include "drmP.h"
-#include "radeon_reg.h"
 #include "radeon.h"
-#include "rs690r.h"
 #include "atom.h"
-#include "atom-bits.h"
-
-/* rs690,rs740 depends on : */
-void r100_hdp_reset(struct radeon_device *rdev);
-int r300_mc_wait_for_idle(struct radeon_device *rdev);
-void r420_pipes_init(struct radeon_device *rdev);
-void rs400_gart_disable(struct radeon_device *rdev);
-int rs400_gart_enable(struct radeon_device *rdev);
-void rs400_gart_adjust_size(struct radeon_device *rdev);
-void rs600_mc_disable_clients(struct radeon_device *rdev);
-
-/* This files gather functions specifics to :
- * rs690,rs740
- *
- * Some of these functions might be used by newer ASICs.
- */
-void rs690_gpu_init(struct radeon_device *rdev);
-int rs690_mc_wait_for_idle(struct radeon_device *rdev);
-
-
-/*
- * MC functions.
- */
-int rs690_mc_init(struct radeon_device *rdev)
-{
-        uint32_t tmp;
-        int r;
-
-        if (r100_debugfs_rbbm_init(rdev)) {
-                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
-        }
-
-        rs690_gpu_init(rdev);
-        rs400_gart_disable(rdev);
-
-        /* Setup GPU memory space */
-        rdev->mc.gtt_location = rdev->mc.mc_vram_size;
-        rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
-        rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
-        rdev->mc.vram_location = 0xFFFFFFFFUL;
-        r = radeon_mc_setup(rdev);
-        if (r) {
-                return r;
-        }
-
-        /* Program GPU memory space */
-        rs600_mc_disable_clients(rdev);
-        if (rs690_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "Failed to wait MC idle while "
-                       "programming pipes. Bad things might happen.\n");
-        }
-        tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
-        tmp = REG_SET(RS690_MC_FB_TOP, tmp >> 16);
-        tmp |= REG_SET(RS690_MC_FB_START, rdev->mc.vram_location >> 16);
-        WREG32_MC(RS690_MCCFG_FB_LOCATION, tmp);
-        /* FIXME: Does this reg exist on RS480,RS740 ? */
-        WREG32(0x310, rdev->mc.vram_location);
-        WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
-        return 0;
-}
-
-void rs690_mc_fini(struct radeon_device *rdev)
-{
-}
-
+#include "rs690d.h"
 
-/*
- * Global GPU functions
- */
-int rs690_mc_wait_for_idle(struct radeon_device *rdev)
+static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
 {
         unsigned i;
         uint32_t tmp;
 
         for (i = 0; i < rdev->usec_timeout; i++) {
                 /* read MC_STATUS */
-                tmp = RREG32_MC(RS690_MC_STATUS);
-                if (tmp & RS690_MC_STATUS_IDLE) {
+                tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
+                if (G_000090_MC_SYSTEM_IDLE(tmp))
                         return 0;
-                }
-                DRM_UDELAY(1);
+                udelay(1);
         }
         return -1;
 }
 
-void rs690_errata(struct radeon_device *rdev)
-{
-        rdev->pll_errata = 0;
-}
-
-void rs690_gpu_init(struct radeon_device *rdev)
+static void rs690_gpu_init(struct radeon_device *rdev)
 {
         /* FIXME: HDP same place on rs690 ? */
         r100_hdp_reset(rdev);
-        rv515_vga_render_disable(rdev);
         /* FIXME: is this correct ? */
         r420_pipes_init(rdev);
         if (rs690_mc_wait_for_idle(rdev)) {
@@ -133,10 +57,6 @@ void rs690_gpu_init(struct radeon_device *rdev)
         }
 }
 
-
-/*
- * VRAM info.
- */
 void rs690_pm_info(struct radeon_device *rdev)
 {
         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
@@ -250,39 +170,39 @@ void rs690_line_buffer_adjust(struct radeon_device *rdev,
         /*
          * Line Buffer Setup
          * There is a single line buffer shared by both display controllers.
-         * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
+         * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
          * the display controllers.  The paritioning can either be done
          * manually or via one of four preset allocations specified in bits 1:0:
          *  0 - line buffer is divided in half and shared between crtc
          *  1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
          *  2 - D1 gets the whole buffer
          *  3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
-         * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual
+         * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
          * allocation mode. In manual allocation mode, D1 always starts at 0,
          * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
          */
-        tmp = RREG32(DC_LB_MEMORY_SPLIT) & ~DC_LB_MEMORY_SPLIT_MASK;
-        tmp &= ~DC_LB_MEMORY_SPLIT_SHIFT_MODE;
+        tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
+        tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
         /* auto */
         if (mode1 && mode2) {
                 if (mode1->hdisplay > mode2->hdisplay) {
                         if (mode1->hdisplay > 2560)
-                                tmp |= DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
+                                tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
                         else
-                                tmp |= DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
+                                tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
                 } else if (mode2->hdisplay > mode1->hdisplay) {
                         if (mode2->hdisplay > 2560)
-                                tmp |= DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
+                                tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
                         else
-                                tmp |= DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
+                                tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
                 } else
-                        tmp |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
+                        tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
         } else if (mode1) {
-                tmp |= DC_LB_MEMORY_SPLIT_D1_ONLY;
+                tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
         } else if (mode2) {
-                tmp |= DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
+                tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
         }
-        WREG32(DC_LB_MEMORY_SPLIT, tmp);
+        WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
 }
 
 struct rs690_watermark {
@@ -487,28 +407,28 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
          * option.
          */
         if (rdev->disp_priority == 2) {
-                tmp = RREG32_MC(MC_INIT_MISC_LAT_TIMER);
-                tmp &= ~MC_DISP1R_INIT_LAT_MASK;
-                tmp &= ~MC_DISP0R_INIT_LAT_MASK;
-                if (mode1)
-                        tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
+                tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
+                tmp &= C_000104_MC_DISP0R_INIT_LAT;
+                tmp &= C_000104_MC_DISP1R_INIT_LAT;
                 if (mode0)
-                        tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
-                WREG32_MC(MC_INIT_MISC_LAT_TIMER, tmp);
+                        tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
+                if (mode1)
+                        tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
+                WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
         }
         rs690_line_buffer_adjust(rdev, mode0, mode1);
 
         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
-                WREG32(DCP_CONTROL, 0);
+                WREG32(R_006C9C_DCP_CONTROL, 0);
         if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
-                WREG32(DCP_CONTROL, 2);
+                WREG32(R_006C9C_DCP_CONTROL, 2);
 
         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
 
         tmp = (wm0.lb_request_fifo_depth - 1);
         tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
-        WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
+        WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
 
         if (mode0 && mode1) {
                 if (rfixed_trunc(wm0.dbpp) > 64)
@@ -561,10 +481,10 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
                         priority_mark12.full = 0;
                 if (wm1.priority_mark_max.full > priority_mark12.full)
                         priority_mark12.full = wm1.priority_mark_max.full;
-                WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
-                WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
-                WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
-                WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
+                WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
+                WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
+                WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
+                WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
         } else if (mode0) {
                 if (rfixed_trunc(wm0.dbpp) > 64)
                         a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
@@ -591,10 +511,12 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
                         priority_mark02.full = 0;
                 if (wm0.priority_mark_max.full > priority_mark02.full)
                         priority_mark02.full = wm0.priority_mark_max.full;
-                WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
-                WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
-                WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
-                WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
+                WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
+                WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
+                WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
+                        S_006D48_D2MODE_PRIORITY_A_OFF(1));
+                WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
+                        S_006D4C_D2MODE_PRIORITY_B_OFF(1));
         } else {
                 if (rfixed_trunc(wm1.dbpp) > 64)
                         a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
@@ -621,30 +543,203 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
                         priority_mark12.full = 0;
                 if (wm1.priority_mark_max.full > priority_mark12.full)
                         priority_mark12.full = wm1.priority_mark_max.full;
-                WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
-                WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
-                WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
-                WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
+                WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
+                        S_006548_D1MODE_PRIORITY_A_OFF(1));
+                WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
+                        S_00654C_D1MODE_PRIORITY_B_OFF(1));
+                WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
+                WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
         }
 }
 
-/*
- * Indirect registers accessor
- */
 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 {
         uint32_t r;
 
-        WREG32(RS690_MC_INDEX, (reg & RS690_MC_INDEX_MASK));
-        r = RREG32(RS690_MC_DATA);
-        WREG32(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
+        WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
+        r = RREG32(R_00007C_MC_DATA);
+        WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
         return r;
 }
 
 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 {
-        WREG32(RS690_MC_INDEX,
-               RS690_MC_INDEX_WR_EN | ((reg) & RS690_MC_INDEX_MASK));
-        WREG32(RS690_MC_DATA, v);
-        WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
+        WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
+                S_000078_MC_IND_WR_EN(1));
+        WREG32(R_00007C_MC_DATA, v);
+        WREG32(R_000078_MC_INDEX, 0x7F);
+}
+
+void rs690_mc_program(struct radeon_device *rdev)
+{
+        struct rv515_mc_save save;
+
+        /* Stops all mc clients */
+        rv515_mc_stop(rdev, &save);
+
+        /* Wait for mc idle */
+        if (rs690_mc_wait_for_idle(rdev))
+                dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
+        /* Program MC, should be a 32bits limited address space */
+        WREG32_MC(R_000100_MCCFG_FB_LOCATION,
+                        S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
+                        S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
+        WREG32(R_000134_HDP_FB_LOCATION,
+                S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
+
+        rv515_mc_resume(rdev, &save);
+}
+
+static int rs690_startup(struct radeon_device *rdev)
+{
+        int r;
+
+        rs690_mc_program(rdev);
+        /* Resume clock */
+        rv515_clock_startup(rdev);
+        /* Initialize GPU configuration (# pipes, ...) */
+        rs690_gpu_init(rdev);
+        /* Initialize GART (initialize after TTM so we can allocate
+         * memory through TTM but finalize after TTM) */
+        r = rs400_gart_enable(rdev);
+        if (r)
+                return r;
+        /* Enable IRQ */
+        rdev->irq.sw_int = true;
+        rs600_irq_set(rdev);
+        /* 1M ring buffer */
+        r = r100_cp_init(rdev, 1024 * 1024);
+        if (r) {
+                dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
+                return r;
+        }
+        r = r100_wb_init(rdev);
+        if (r)
+                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
+        r = r100_ib_init(rdev);
+        if (r) {
+                dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
+                return r;
+        }
+        return 0;
+}
+
+int rs690_resume(struct radeon_device *rdev)
+{
+        /* Make sur GART are not working */
+        rs400_gart_disable(rdev);
+        /* Resume clock before doing reset */
+        rv515_clock_startup(rdev);
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* post */
+        atom_asic_init(rdev->mode_info.atom_context);
+        /* Resume clock after posting */
+        rv515_clock_startup(rdev);
+        return rs690_startup(rdev);
+}
+
+int rs690_suspend(struct radeon_device *rdev)
+{
+        r100_cp_disable(rdev);
+        r100_wb_disable(rdev);
+        rs600_irq_disable(rdev);
+        rs400_gart_disable(rdev);
+        return 0;
+}
+
+void rs690_fini(struct radeon_device *rdev)
+{
+        rs690_suspend(rdev);
+        r100_cp_fini(rdev);
+        r100_wb_fini(rdev);
+        r100_ib_fini(rdev);
+        radeon_gem_fini(rdev);
+        rs400_gart_fini(rdev);
+        radeon_irq_kms_fini(rdev);
+        radeon_fence_driver_fini(rdev);
+        radeon_object_fini(rdev);
+        radeon_atombios_fini(rdev);
+        kfree(rdev->bios);
+        rdev->bios = NULL;
+}
+
+int rs690_init(struct radeon_device *rdev)
+{
+        int r;
+
+        /* Disable VGA */
+        rv515_vga_render_disable(rdev);
+        /* Initialize scratch registers */
+        radeon_scratch_init(rdev);
+        /* Initialize surface registers */
+        radeon_surface_init(rdev);
+        /* TODO: disable VGA need to use VGA request */
+        /* BIOS*/
+        if (!radeon_get_bios(rdev)) {
+                if (ASIC_IS_AVIVO(rdev))
+                        return -EINVAL;
+        }
+        if (rdev->is_atom_bios) {
+                r = radeon_atombios_init(rdev);
+                if (r)
+                        return r;
+        } else {
+                dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
+                return -EINVAL;
+        }
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                dev_warn(rdev->dev,
+                        "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
+                        RREG32(R_000E40_RBBM_STATUS),
+                        RREG32(R_0007C0_CP_STAT));
+        }
+        /* check if cards are posted or not */
+        if (!radeon_card_posted(rdev) && rdev->bios) {
+                DRM_INFO("GPU not posted. posting now...\n");
+                atom_asic_init(rdev->mode_info.atom_context);
+        }
+        /* Initialize clocks */
+        radeon_get_clock_info(rdev->ddev);
+        /* Get vram informations */
+        rs690_vram_info(rdev);
+        /* Initialize memory controller (also test AGP) */
+        r = r420_mc_init(rdev);
+        if (r)
+                return r;
+        rv515_debugfs(rdev);
+        /* Fence driver */
+        r = radeon_fence_driver_init(rdev);
+        if (r)
+                return r;
+        r = radeon_irq_kms_init(rdev);
+        if (r)
+                return r;
+        /* Memory manager */
+        r = radeon_object_init(rdev);
+        if (r)
+                return r;
+        r = rs400_gart_init(rdev);
+        if (r)
+                return r;
+        rs600_set_safe_registers(rdev);
+        rdev->accel_working = true;
+        r = rs690_startup(rdev);
+        if (r) {
+                /* Somethings want wront with the accel init stop accel */
+                dev_err(rdev->dev, "Disabling GPU acceleration\n");
+                rs690_suspend(rdev);
+                r100_cp_fini(rdev);
+                r100_wb_fini(rdev);
+                r100_ib_fini(rdev);
+                rs400_gart_fini(rdev);
+                radeon_irq_kms_fini(rdev);
+                rdev->accel_working = false;
+        }
+        return 0;
 }
diff --git a/drivers/gpu/drm/radeon/rs690d.h b/drivers/gpu/drm/radeon/rs690d.h
new file mode 100644
index 000000000000..62d31e7a897f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rs690d.h
@@ -0,0 +1,307 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __RS690D_H__
+#define __RS690D_H__
+
+/* Registers */
+#define R_000078_MC_INDEX                            0x000078
+#define   S_000078_MC_IND_ADDR(x)                      (((x) & 0x1FF) << 0)
+#define   G_000078_MC_IND_ADDR(x)                      (((x) >> 0) & 0x1FF)
+#define   C_000078_MC_IND_ADDR                         0xFFFFFE00
+#define   S_000078_MC_IND_WR_EN(x)                     (((x) & 0x1) << 9)
+#define   G_000078_MC_IND_WR_EN(x)                     (((x) >> 9) & 0x1)
+#define   C_000078_MC_IND_WR_EN                        0xFFFFFDFF
+#define R_00007C_MC_DATA                             0x00007C
+#define   S_00007C_MC_DATA(x)                          (((x) & 0xFFFFFFFF) << 0)
+#define   G_00007C_MC_DATA(x)                          (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00007C_MC_DATA                             0x00000000
+#define R_0000F8_CONFIG_MEMSIZE                      0x0000F8
+#define   S_0000F8_CONFIG_MEMSIZE(x)                   (((x) & 0xFFFFFFFF) << 0)
+#define   G_0000F8_CONFIG_MEMSIZE(x)                   (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0000F8_CONFIG_MEMSIZE                      0x00000000
+#define R_000134_HDP_FB_LOCATION                     0x000134
+#define   S_000134_HDP_FB_START(x)                     (((x) & 0xFFFF) << 0)
+#define   G_000134_HDP_FB_START(x)                     (((x) >> 0) & 0xFFFF)
+#define   C_000134_HDP_FB_START                        0xFFFF0000
+#define R_0007C0_CP_STAT                             0x0007C0
+#define   S_0007C0_MRU_BUSY(x)                         (((x) & 0x1) << 0)
+#define   G_0007C0_MRU_BUSY(x)                         (((x) >> 0) & 0x1)
+#define   C_0007C0_MRU_BUSY                            0xFFFFFFFE
+#define   S_0007C0_MWU_BUSY(x)                         (((x) & 0x1) << 1)
+#define   G_0007C0_MWU_BUSY(x)                         (((x) >> 1) & 0x1)
+#define   C_0007C0_MWU_BUSY                            0xFFFFFFFD
+#define   S_0007C0_RSIU_BUSY(x)                        (((x) & 0x1) << 2)
+#define   G_0007C0_RSIU_BUSY(x)                        (((x) >> 2) & 0x1)
+#define   C_0007C0_RSIU_BUSY                           0xFFFFFFFB
+#define   S_0007C0_RCIU_BUSY(x)                        (((x) & 0x1) << 3)
+#define   G_0007C0_RCIU_BUSY(x)                        (((x) >> 3) & 0x1)
+#define   C_0007C0_RCIU_BUSY                           0xFFFFFFF7
+#define   S_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) & 0x1) << 9)
+#define   G_0007C0_CSF_PRIMARY_BUSY(x)                 (((x) >> 9) & 0x1)
+#define   C_0007C0_CSF_PRIMARY_BUSY                    0xFFFFFDFF
+#define   S_0007C0_CSF_INDIRECT_BUSY(x)                (((x) & 0x1) << 10)
+#define   G_0007C0_CSF_INDIRECT_BUSY(x)                (((x) >> 10) & 0x1)
+#define   C_0007C0_CSF_INDIRECT_BUSY                   0xFFFFFBFF
+#define   S_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) & 0x1) << 11)
+#define   G_0007C0_CSQ_PRIMARY_BUSY(x)                 (((x) >> 11) & 0x1)
+#define   C_0007C0_CSQ_PRIMARY_BUSY                    0xFFFFF7FF
+#define   S_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) & 0x1) << 12)
+#define   G_0007C0_CSQ_INDIRECT_BUSY(x)                (((x) >> 12) & 0x1)
+#define   C_0007C0_CSQ_INDIRECT_BUSY                   0xFFFFEFFF
+#define   S_0007C0_CSI_BUSY(x)                         (((x) & 0x1) << 13)
+#define   G_0007C0_CSI_BUSY(x)                         (((x) >> 13) & 0x1)
+#define   C_0007C0_CSI_BUSY                            0xFFFFDFFF
+#define   S_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) & 0x1) << 14)
+#define   G_0007C0_CSF_INDIRECT2_BUSY(x)               (((x) >> 14) & 0x1)
+#define   C_0007C0_CSF_INDIRECT2_BUSY                  0xFFFFBFFF
+#define   S_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) & 0x1) << 15)
+#define   G_0007C0_CSQ_INDIRECT2_BUSY(x)               (((x) >> 15) & 0x1)
+#define   C_0007C0_CSQ_INDIRECT2_BUSY                  0xFFFF7FFF
+#define   S_0007C0_GUIDMA_BUSY(x)                      (((x) & 0x1) << 28)
+#define   G_0007C0_GUIDMA_BUSY(x)                      (((x) >> 28) & 0x1)
+#define   C_0007C0_GUIDMA_BUSY                         0xEFFFFFFF
+#define   S_0007C0_VIDDMA_BUSY(x)                      (((x) & 0x1) << 29)
+#define   G_0007C0_VIDDMA_BUSY(x)                      (((x) >> 29) & 0x1)
+#define   C_0007C0_VIDDMA_BUSY                         0xDFFFFFFF
+#define   S_0007C0_CMDSTRM_BUSY(x)                     (((x) & 0x1) << 30)
+#define   G_0007C0_CMDSTRM_BUSY(x)                     (((x) >> 30) & 0x1)
+#define   C_0007C0_CMDSTRM_BUSY                        0xBFFFFFFF
+#define   S_0007C0_CP_BUSY(x)                          (((x) & 0x1) << 31)
+#define   G_0007C0_CP_BUSY(x)                          (((x) >> 31) & 0x1)
+#define   C_0007C0_CP_BUSY                             0x7FFFFFFF
+#define R_000E40_RBBM_STATUS                         0x000E40
+#define   S_000E40_CMDFIFO_AVAIL(x)                    (((x) & 0x7F) << 0)
+#define   G_000E40_CMDFIFO_AVAIL(x)                    (((x) >> 0) & 0x7F)
+#define   C_000E40_CMDFIFO_AVAIL                       0xFFFFFF80
+#define   S_000E40_HIRQ_ON_RBB(x)                      (((x) & 0x1) << 8)
+#define   G_000E40_HIRQ_ON_RBB(x)                      (((x) >> 8) & 0x1)
+#define   C_000E40_HIRQ_ON_RBB                         0xFFFFFEFF
+#define   S_000E40_CPRQ_ON_RBB(x)                      (((x) & 0x1) << 9)
+#define   G_000E40_CPRQ_ON_RBB(x)                      (((x) >> 9) & 0x1)
+#define   C_000E40_CPRQ_ON_RBB                         0xFFFFFDFF
+#define   S_000E40_CFRQ_ON_RBB(x)                      (((x) & 0x1) << 10)
+#define   G_000E40_CFRQ_ON_RBB(x)                      (((x) >> 10) & 0x1)
+#define   C_000E40_CFRQ_ON_RBB                         0xFFFFFBFF
+#define   S_000E40_HIRQ_IN_RTBUF(x)                    (((x) & 0x1) << 11)
+#define   G_000E40_HIRQ_IN_RTBUF(x)                    (((x) >> 11) & 0x1)
+#define   C_000E40_HIRQ_IN_RTBUF                       0xFFFFF7FF
+#define   S_000E40_CPRQ_IN_RTBUF(x)                    (((x) & 0x1) << 12)
+#define   G_000E40_CPRQ_IN_RTBUF(x)                    (((x) >> 12) & 0x1)
+#define   C_000E40_CPRQ_IN_RTBUF                       0xFFFFEFFF
+#define   S_000E40_CFRQ_IN_RTBUF(x)                    (((x) & 0x1) << 13)
+#define   G_000E40_CFRQ_IN_RTBUF(x)                    (((x) >> 13) & 0x1)
+#define   C_000E40_CFRQ_IN_RTBUF                       0xFFFFDFFF
+#define   S_000E40_CF_PIPE_BUSY(x)                     (((x) & 0x1) << 14)
+#define   G_000E40_CF_PIPE_BUSY(x)                     (((x) >> 14) & 0x1)
+#define   C_000E40_CF_PIPE_BUSY                        0xFFFFBFFF
+#define   S_000E40_ENG_EV_BUSY(x)                      (((x) & 0x1) << 15)
+#define   G_000E40_ENG_EV_BUSY(x)                      (((x) >> 15) & 0x1)
+#define   C_000E40_ENG_EV_BUSY                         0xFFFF7FFF
+#define   S_000E40_CP_CMDSTRM_BUSY(x)                  (((x) & 0x1) << 16)
+#define   G_000E40_CP_CMDSTRM_BUSY(x)                  (((x) >> 16) & 0x1)
+#define   C_000E40_CP_CMDSTRM_BUSY                     0xFFFEFFFF
+#define   S_000E40_E2_BUSY(x)                          (((x) & 0x1) << 17)
+#define   G_000E40_E2_BUSY(x)                          (((x) >> 17) & 0x1)
+#define   C_000E40_E2_BUSY                             0xFFFDFFFF
+#define   S_000E40_RB2D_BUSY(x)                        (((x) & 0x1) << 18)
+#define   G_000E40_RB2D_BUSY(x)                        (((x) >> 18) & 0x1)
+#define   C_000E40_RB2D_BUSY                           0xFFFBFFFF
+#define   S_000E40_RB3D_BUSY(x)                        (((x) & 0x1) << 19)
+#define   G_000E40_RB3D_BUSY(x)                        (((x) >> 19) & 0x1)
+#define   C_000E40_RB3D_BUSY                           0xFFF7FFFF
+#define   S_000E40_VAP_BUSY(x)                         (((x) & 0x1) << 20)
+#define   G_000E40_VAP_BUSY(x)                         (((x) >> 20) & 0x1)
+#define   C_000E40_VAP_BUSY                            0xFFEFFFFF
+#define   S_000E40_RE_BUSY(x)                          (((x) & 0x1) << 21)
+#define   G_000E40_RE_BUSY(x)                          (((x) >> 21) & 0x1)
+#define   C_000E40_RE_BUSY                             0xFFDFFFFF
+#define   S_000E40_TAM_BUSY(x)                         (((x) & 0x1) << 22)
+#define   G_000E40_TAM_BUSY(x)                         (((x) >> 22) & 0x1)
+#define   C_000E40_TAM_BUSY                            0xFFBFFFFF
+#define   S_000E40_TDM_BUSY(x)                         (((x) & 0x1) << 23)
+#define   G_000E40_TDM_BUSY(x)                         (((x) >> 23) & 0x1)
+#define   C_000E40_TDM_BUSY                            0xFF7FFFFF
+#define   S_000E40_PB_BUSY(x)                          (((x) & 0x1) << 24)
+#define   G_000E40_PB_BUSY(x)                          (((x) >> 24) & 0x1)
+#define   C_000E40_PB_BUSY                             0xFEFFFFFF
+#define   S_000E40_TIM_BUSY(x)                         (((x) & 0x1) << 25)
+#define   G_000E40_TIM_BUSY(x)                         (((x) >> 25) & 0x1)
+#define   C_000E40_TIM_BUSY                            0xFDFFFFFF
+#define   S_000E40_GA_BUSY(x)                          (((x) & 0x1) << 26)
+#define   G_000E40_GA_BUSY(x)                          (((x) >> 26) & 0x1)
+#define   C_000E40_GA_BUSY                             0xFBFFFFFF
+#define   S_000E40_CBA2D_BUSY(x)                       (((x) & 0x1) << 27)
+#define   G_000E40_CBA2D_BUSY(x)                       (((x) >> 27) & 0x1)
+#define   C_000E40_CBA2D_BUSY                          0xF7FFFFFF
+#define   S_000E40_GUI_ACTIVE(x)                       (((x) & 0x1) << 31)
+#define   G_000E40_GUI_ACTIVE(x)                       (((x) >> 31) & 0x1)
+#define   C_000E40_GUI_ACTIVE                          0x7FFFFFFF
+#define R_006520_DC_LB_MEMORY_SPLIT                  0x006520
+#define   S_006520_DC_LB_MEMORY_SPLIT(x)               (((x) & 0x3) << 0)
+#define   G_006520_DC_LB_MEMORY_SPLIT(x)               (((x) >> 0) & 0x3)
+#define   C_006520_DC_LB_MEMORY_SPLIT                  0xFFFFFFFC
+#define   S_006520_DC_LB_MEMORY_SPLIT_MODE(x)          (((x) & 0x1) << 2)
+#define   G_006520_DC_LB_MEMORY_SPLIT_MODE(x)          (((x) >> 2) & 0x1)
+#define   C_006520_DC_LB_MEMORY_SPLIT_MODE             0xFFFFFFFB
+#define   V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF    0
+#define   V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q      1
+#define   V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY          2
+#define   V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q      3
+#define   S_006520_DC_LB_DISP1_END_ADR(x)              (((x) & 0x7FF) << 4)
+#define   G_006520_DC_LB_DISP1_END_ADR(x)              (((x) >> 4) & 0x7FF)
+#define   C_006520_DC_LB_DISP1_END_ADR                 0xFFFF800F
+#define R_006548_D1MODE_PRIORITY_A_CNT               0x006548
+#define   S_006548_D1MODE_PRIORITY_MARK_A(x)           (((x) & 0x7FFF) << 0)
+#define   G_006548_D1MODE_PRIORITY_MARK_A(x)           (((x) >> 0) & 0x7FFF)
+#define   C_006548_D1MODE_PRIORITY_MARK_A              0xFFFF8000
+#define   S_006548_D1MODE_PRIORITY_A_OFF(x)            (((x) & 0x1) << 16)
+#define   G_006548_D1MODE_PRIORITY_A_OFF(x)            (((x) >> 16) & 0x1)
+#define   C_006548_D1MODE_PRIORITY_A_OFF               0xFFFEFFFF
+#define   S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)     (((x) & 0x1) << 24)
+#define   G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x)     (((x) >> 24) & 0x1)
+#define   C_006548_D1MODE_PRIORITY_A_FORCE_MASK        0xFEFFFFFF
+#define R_00654C_D1MODE_PRIORITY_B_CNT               0x00654C
+#define   S_00654C_D1MODE_PRIORITY_MARK_B(x)           (((x) & 0x7FFF) << 0)
+#define   G_00654C_D1MODE_PRIORITY_MARK_B(x)           (((x) >> 0) & 0x7FFF)
+#define   C_00654C_D1MODE_PRIORITY_MARK_B              0xFFFF8000
+#define   S_00654C_D1MODE_PRIORITY_B_OFF(x)            (((x) & 0x1) << 16)
+#define   G_00654C_D1MODE_PRIORITY_B_OFF(x)            (((x) >> 16) & 0x1)
+#define   C_00654C_D1MODE_PRIORITY_B_OFF               0xFFFEFFFF
+#define   S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) & 0x1) << 20)
+#define   G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
+#define   C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON         0xFFEFFFFF
+#define   S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x)     (((x) & 0x1) << 24)
+#define   G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x)     (((x) >> 24) & 0x1)
+#define   C_00654C_D1MODE_PRIORITY_B_FORCE_MASK        0xFEFFFFFF
+#define R_006C9C_DCP_CONTROL                         0x006C9C
+#define R_006D48_D2MODE_PRIORITY_A_CNT               0x006D48
+#define   S_006D48_D2MODE_PRIORITY_MARK_A(x)           (((x) & 0x7FFF) << 0)
+#define   G_006D48_D2MODE_PRIORITY_MARK_A(x)           (((x) >> 0) & 0x7FFF)
+#define   C_006D48_D2MODE_PRIORITY_MARK_A              0xFFFF8000
+#define   S_006D48_D2MODE_PRIORITY_A_OFF(x)            (((x) & 0x1) << 16)
+#define   G_006D48_D2MODE_PRIORITY_A_OFF(x)            (((x) >> 16) & 0x1)
+#define   C_006D48_D2MODE_PRIORITY_A_OFF               0xFFFEFFFF
+#define   S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) & 0x1) << 20)
+#define   G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
+#define   C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON         0xFFEFFFFF
+#define   S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x)     (((x) & 0x1) << 24)
+#define   G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x)     (((x) >> 24) & 0x1)
+#define   C_006D48_D2MODE_PRIORITY_A_FORCE_MASK        0xFEFFFFFF
+#define R_006D4C_D2MODE_PRIORITY_B_CNT               0x006D4C
+#define   S_006D4C_D2MODE_PRIORITY_MARK_B(x)           (((x) & 0x7FFF) << 0)
+#define   G_006D4C_D2MODE_PRIORITY_MARK_B(x)           (((x) >> 0) & 0x7FFF)
+#define   C_006D4C_D2MODE_PRIORITY_MARK_B              0xFFFF8000
+#define   S_006D4C_D2MODE_PRIORITY_B_OFF(x)            (((x) & 0x1) << 16)
+#define   G_006D4C_D2MODE_PRIORITY_B_OFF(x)            (((x) >> 16) & 0x1)
+#define   C_006D4C_D2MODE_PRIORITY_B_OFF               0xFFFEFFFF
+#define   S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) & 0x1) << 20)
+#define   G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x)      (((x) >> 20) & 0x1)
+#define   C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON         0xFFEFFFFF
+#define   S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x)     (((x) & 0x1) << 24)
+#define   G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x)     (((x) >> 24) & 0x1)
+#define   C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK        0xFEFFFFFF
+#define R_006D58_LB_MAX_REQ_OUTSTANDING              0x006D58
+#define   S_006D58_LB_D1_MAX_REQ_OUTSTANDING(x)        (((x) & 0xF) << 0)
+#define   G_006D58_LB_D1_MAX_REQ_OUTSTANDING(x)        (((x) >> 0) & 0xF)
+#define   C_006D58_LB_D1_MAX_REQ_OUTSTANDING           0xFFFFFFF0
+#define   S_006D58_LB_D2_MAX_REQ_OUTSTANDING(x)        (((x) & 0xF) << 16)
+#define   G_006D58_LB_D2_MAX_REQ_OUTSTANDING(x)        (((x) >> 16) & 0xF)
+#define   C_006D58_LB_D2_MAX_REQ_OUTSTANDING           0xFFF0FFFF
+
+
+#define R_000090_MC_SYSTEM_STATUS                    0x000090
+#define   S_000090_MC_SYSTEM_IDLE(x)                   (((x) & 0x1) << 0)
+#define   G_000090_MC_SYSTEM_IDLE(x)                   (((x) >> 0) & 0x1)
+#define   C_000090_MC_SYSTEM_IDLE                      0xFFFFFFFE
+#define   S_000090_MC_SEQUENCER_IDLE(x)                (((x) & 0x1) << 1)
+#define   G_000090_MC_SEQUENCER_IDLE(x)                (((x) >> 1) & 0x1)
+#define   C_000090_MC_SEQUENCER_IDLE                   0xFFFFFFFD
+#define   S_000090_MC_ARBITER_IDLE(x)                  (((x) & 0x1) << 2)
+#define   G_000090_MC_ARBITER_IDLE(x)                  (((x) >> 2) & 0x1)
+#define   C_000090_MC_ARBITER_IDLE                     0xFFFFFFFB
+#define   S_000090_MC_SELECT_PM(x)                     (((x) & 0x1) << 3)
+#define   G_000090_MC_SELECT_PM(x)                     (((x) >> 3) & 0x1)
+#define   C_000090_MC_SELECT_PM                        0xFFFFFFF7
+#define   S_000090_RESERVED4(x)                        (((x) & 0xF) << 4)
+#define   G_000090_RESERVED4(x)                        (((x) >> 4) & 0xF)
+#define   C_000090_RESERVED4                           0xFFFFFF0F
+#define   S_000090_RESERVED8(x)                        (((x) & 0xF) << 8)
+#define   G_000090_RESERVED8(x)                        (((x) >> 8) & 0xF)
+#define   C_000090_RESERVED8                           0xFFFFF0FF
+#define   S_000090_RESERVED12(x)                       (((x) & 0xF) << 12)
+#define   G_000090_RESERVED12(x)                       (((x) >> 12) & 0xF)
+#define   C_000090_RESERVED12                          0xFFFF0FFF
+#define   S_000090_MCA_INIT_EXECUTED(x)                (((x) & 0x1) << 16)
+#define   G_000090_MCA_INIT_EXECUTED(x)                (((x) >> 16) & 0x1)
+#define   C_000090_MCA_INIT_EXECUTED                   0xFFFEFFFF
+#define   S_000090_MCA_IDLE(x)                         (((x) & 0x1) << 17)
+#define   G_000090_MCA_IDLE(x)                         (((x) >> 17) & 0x1)
+#define   C_000090_MCA_IDLE                            0xFFFDFFFF
+#define   S_000090_MCA_SEQ_IDLE(x)                     (((x) & 0x1) << 18)
+#define   G_000090_MCA_SEQ_IDLE(x)                     (((x) >> 18) & 0x1)
+#define   C_000090_MCA_SEQ_IDLE                        0xFFFBFFFF
+#define   S_000090_MCA_ARB_IDLE(x)                     (((x) & 0x1) << 19)
+#define   G_000090_MCA_ARB_IDLE(x)                     (((x) >> 19) & 0x1)
+#define   C_000090_MCA_ARB_IDLE                        0xFFF7FFFF
+#define   S_000090_RESERVED20(x)                       (((x) & 0xFFF) << 20)
+#define   G_000090_RESERVED20(x)                       (((x) >> 20) & 0xFFF)
+#define   C_000090_RESERVED20                          0x000FFFFF
+#define R_000100_MCCFG_FB_LOCATION                   0x000100
+#define   S_000100_MC_FB_START(x)                      (((x) & 0xFFFF) << 0)
+#define   G_000100_MC_FB_START(x)                      (((x) >> 0) & 0xFFFF)
+#define   C_000100_MC_FB_START                         0xFFFF0000
+#define   S_000100_MC_FB_TOP(x)                        (((x) & 0xFFFF) << 16)
+#define   G_000100_MC_FB_TOP(x)                        (((x) >> 16) & 0xFFFF)
+#define   C_000100_MC_FB_TOP                           0x0000FFFF
+#define R_000104_MC_INIT_MISC_LAT_TIMER              0x000104
+#define   S_000104_MC_CPR_INIT_LAT(x)                  (((x) & 0xF) << 0)
+#define   G_000104_MC_CPR_INIT_LAT(x)                  (((x) >> 0) & 0xF)
+#define   C_000104_MC_CPR_INIT_LAT                     0xFFFFFFF0
+#define   S_000104_MC_VF_INIT_LAT(x)                   (((x) & 0xF) << 4)
+#define   G_000104_MC_VF_INIT_LAT(x)                   (((x) >> 4) & 0xF)
+#define   C_000104_MC_VF_INIT_LAT                      0xFFFFFF0F
+#define   S_000104_MC_DISP0R_INIT_LAT(x)               (((x) & 0xF) << 8)
+#define   G_000104_MC_DISP0R_INIT_LAT(x)               (((x) >> 8) & 0xF)
+#define   C_000104_MC_DISP0R_INIT_LAT                  0xFFFFF0FF
+#define   S_000104_MC_DISP1R_INIT_LAT(x)               (((x) & 0xF) << 12)
+#define   G_000104_MC_DISP1R_INIT_LAT(x)               (((x) >> 12) & 0xF)
+#define   C_000104_MC_DISP1R_INIT_LAT                  0xFFFF0FFF
+#define   S_000104_MC_FIXED_INIT_LAT(x)                (((x) & 0xF) << 16)
+#define   G_000104_MC_FIXED_INIT_LAT(x)                (((x) >> 16) & 0xF)
+#define   C_000104_MC_FIXED_INIT_LAT                   0xFFF0FFFF
+#define   S_000104_MC_E2R_INIT_LAT(x)                  (((x) & 0xF) << 20)
+#define   G_000104_MC_E2R_INIT_LAT(x)                  (((x) >> 20) & 0xF)
+#define   C_000104_MC_E2R_INIT_LAT                     0xFF0FFFFF
+#define   S_000104_SAME_PAGE_PRIO(x)                   (((x) & 0xF) << 24)
+#define   G_000104_SAME_PAGE_PRIO(x)                   (((x) >> 24) & 0xF)
+#define   C_000104_SAME_PAGE_PRIO                      0xF0FFFFFF
+#define   S_000104_MC_GLOBW_INIT_LAT(x)                (((x) & 0xF) << 28)
+#define   G_000104_MC_GLOBW_INIT_LAT(x)                (((x) >> 28) & 0xF)
+#define   C_000104_MC_GLOBW_INIT_LAT                   0x0FFFFFFF
+
+#endif
diff --git a/drivers/gpu/drm/radeon/rs690r.h b/drivers/gpu/drm/radeon/rs690r.h
deleted file mode 100644
index c0d9faa2175b..000000000000
--- a/drivers/gpu/drm/radeon/rs690r.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright 2008 Advanced Micro Devices, Inc.
- * Copyright 2008 Red Hat Inc.
- * Copyright 2009 Jerome Glisse.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Dave Airlie
- *          Alex Deucher
- *          Jerome Glisse
- */
-#ifndef RS690R_H
-#define RS690R_H
-
-/* RS690/RS740 registers */
-#define MC_INDEX                        0x0078
-#       define MC_INDEX_MASK                    0x1FF
-#       define MC_INDEX_WR_EN                   (1 << 9)
-#       define MC_INDEX_WR_ACK                  0x7F
-#define MC_DATA                         0x007C
-#define HDP_FB_LOCATION                 0x0134
-#define DC_LB_MEMORY_SPLIT              0x6520
-#define         DC_LB_MEMORY_SPLIT_MASK                 0x00000003
-#define         DC_LB_MEMORY_SPLIT_SHIFT                0
-#define         DC_LB_MEMORY_SPLIT_D1HALF_D2HALF        0
-#define         DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q          1
-#define         DC_LB_MEMORY_SPLIT_D1_ONLY              2
-#define         DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q          3
-#define         DC_LB_MEMORY_SPLIT_SHIFT_MODE           (1 << 2)
-#define         DC_LB_DISP1_END_ADR_SHIFT               4
-#define         DC_LB_DISP1_END_ADR_MASK                0x00007FF0
-#define D1MODE_PRIORITY_A_CNT           0x6548
-#define         MODE_PRIORITY_MARK_MASK                 0x00007FFF
-#define         MODE_PRIORITY_OFF                       (1 << 16)
-#define         MODE_PRIORITY_ALWAYS_ON                 (1 << 20)
-#define         MODE_PRIORITY_FORCE_MASK                (1 << 24)
-#define D1MODE_PRIORITY_B_CNT           0x654C
-#define LB_MAX_REQ_OUTSTANDING          0x6D58
-#define         LB_D1_MAX_REQ_OUTSTANDING_MASK          0x0000000F
-#define         LB_D1_MAX_REQ_OUTSTANDING_SHIFT         0
-#define         LB_D2_MAX_REQ_OUTSTANDING_MASK          0x000F0000
-#define         LB_D2_MAX_REQ_OUTSTANDING_SHIFT         16
-#define DCP_CONTROL                     0x6C9C
-#define D2MODE_PRIORITY_A_CNT           0x6D48
-#define D2MODE_PRIORITY_B_CNT           0x6D4C
-
-/* MC indirect registers */
-#define MC_STATUS_IDLE                          (1 << 0)
-#define MC_MISC_CNTL                    0x18
-#define         DISABLE_GTW                     (1 << 1)
-#define         GART_INDEX_REG_EN               (1 << 12)
-#define         BLOCK_GFX_D3_EN                 (1 << 14)
-#define GART_FEATURE_ID                 0x2B
-#define         HANG_EN                         (1 << 11)
-#define         TLB_ENABLE                      (1 << 18)
-#define         P2P_ENABLE                      (1 << 19)
-#define         GTW_LAC_EN                      (1 << 25)
-#define         LEVEL2_GART                     (0 << 30)
-#define         LEVEL1_GART                     (1 << 30)
-#define         PDC_EN                          (1 << 31)
-#define GART_BASE                       0x2C
-#define GART_CACHE_CNTRL                0x2E
-#       define GART_CACHE_INVALIDATE            (1 << 0)
-#define MC_STATUS                       0x90
-#define MCCFG_FB_LOCATION               0x100
-#define         MC_FB_START_MASK                0x0000FFFF
-#define         MC_FB_START_SHIFT               0
-#define         MC_FB_TOP_MASK                  0xFFFF0000
-#define         MC_FB_TOP_SHIFT                 16
-#define MCCFG_AGP_LOCATION              0x101
-#define         MC_AGP_START_MASK               0x0000FFFF
-#define         MC_AGP_START_SHIFT              0
-#define         MC_AGP_TOP_MASK                 0xFFFF0000
-#define         MC_AGP_TOP_SHIFT                16
-#define MCCFG_AGP_BASE                  0x102
-#define MCCFG_AGP_BASE_2                0x103
-#define MC_INIT_MISC_LAT_TIMER          0x104
-#define         MC_DISP0R_INIT_LAT_SHIFT        8
-#define         MC_DISP0R_INIT_LAT_MASK         0x00000F00
-#define         MC_DISP1R_INIT_LAT_SHIFT        12
-#define         MC_DISP1R_INIT_LAT_MASK         0x0000F000
-
-#endif
diff --git a/drivers/gpu/drm/radeon/rv200d.h b/drivers/gpu/drm/radeon/rv200d.h
new file mode 100644
index 000000000000..c5b398330c26
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv200d.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __RV200D_H__
+#define __RV200D_H__
+
+#define R_00015C_AGP_BASE_2                          0x00015C
+#define   S_00015C_AGP_BASE_ADDR_2(x)                  (((x) & 0xF) << 0)
+#define   G_00015C_AGP_BASE_ADDR_2(x)                  (((x) >> 0) & 0xF)
+#define   C_00015C_AGP_BASE_ADDR_2                     0xFFFFFFF0
+
+#endif
diff --git a/drivers/gpu/drm/radeon/rv250d.h b/drivers/gpu/drm/radeon/rv250d.h
new file mode 100644
index 000000000000..e5a70b06fe1f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv250d.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __RV250D_H__
+#define __RV250D_H__
+
+#define R_00000D_SCLK_CNTL_M6                        0x00000D
+#define   S_00000D_SCLK_SRC_SEL(x)                     (((x) & 0x7) << 0)
+#define   G_00000D_SCLK_SRC_SEL(x)                     (((x) >> 0) & 0x7)
+#define   C_00000D_SCLK_SRC_SEL                        0xFFFFFFF8
+#define   S_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 3)
+#define   G_00000D_CP_MAX_DYN_STOP_LAT(x)              (((x) >> 3) & 0x1)
+#define   C_00000D_CP_MAX_DYN_STOP_LAT                 0xFFFFFFF7
+#define   S_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 4)
+#define   G_00000D_HDP_MAX_DYN_STOP_LAT(x)             (((x) >> 4) & 0x1)
+#define   C_00000D_HDP_MAX_DYN_STOP_LAT                0xFFFFFFEF
+#define   S_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 5)
+#define   G_00000D_TV_MAX_DYN_STOP_LAT(x)              (((x) >> 5) & 0x1)
+#define   C_00000D_TV_MAX_DYN_STOP_LAT                 0xFFFFFFDF
+#define   S_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 6)
+#define   G_00000D_E2_MAX_DYN_STOP_LAT(x)              (((x) >> 6) & 0x1)
+#define   C_00000D_E2_MAX_DYN_STOP_LAT                 0xFFFFFFBF
+#define   S_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 7)
+#define   G_00000D_SE_MAX_DYN_STOP_LAT(x)              (((x) >> 7) & 0x1)
+#define   C_00000D_SE_MAX_DYN_STOP_LAT                 0xFFFFFF7F
+#define   S_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) & 0x1) << 8)
+#define   G_00000D_IDCT_MAX_DYN_STOP_LAT(x)            (((x) >> 8) & 0x1)
+#define   C_00000D_IDCT_MAX_DYN_STOP_LAT               0xFFFFFEFF
+#define   S_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 9)
+#define   G_00000D_VIP_MAX_DYN_STOP_LAT(x)             (((x) >> 9) & 0x1)
+#define   C_00000D_VIP_MAX_DYN_STOP_LAT                0xFFFFFDFF
+#define   S_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 10)
+#define   G_00000D_RE_MAX_DYN_STOP_LAT(x)              (((x) >> 10) & 0x1)
+#define   C_00000D_RE_MAX_DYN_STOP_LAT                 0xFFFFFBFF
+#define   S_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 11)
+#define   G_00000D_PB_MAX_DYN_STOP_LAT(x)              (((x) >> 11) & 0x1)
+#define   C_00000D_PB_MAX_DYN_STOP_LAT                 0xFFFFF7FF
+#define   S_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 12)
+#define   G_00000D_TAM_MAX_DYN_STOP_LAT(x)             (((x) >> 12) & 0x1)
+#define   C_00000D_TAM_MAX_DYN_STOP_LAT                0xFFFFEFFF
+#define   S_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) & 0x1) << 13)
+#define   G_00000D_TDM_MAX_DYN_STOP_LAT(x)             (((x) >> 13) & 0x1)
+#define   C_00000D_TDM_MAX_DYN_STOP_LAT                0xFFFFDFFF
+#define   S_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) & 0x1) << 14)
+#define   G_00000D_RB_MAX_DYN_STOP_LAT(x)              (((x) >> 14) & 0x1)
+#define   C_00000D_RB_MAX_DYN_STOP_LAT                 0xFFFFBFFF
+#define   S_00000D_FORCE_DISP2(x)                      (((x) & 0x1) << 15)
+#define   G_00000D_FORCE_DISP2(x)                      (((x) >> 15) & 0x1)
+#define   C_00000D_FORCE_DISP2                         0xFFFF7FFF
+#define   S_00000D_FORCE_CP(x)                         (((x) & 0x1) << 16)
+#define   G_00000D_FORCE_CP(x)                         (((x) >> 16) & 0x1)
+#define   C_00000D_FORCE_CP                            0xFFFEFFFF
+#define   S_00000D_FORCE_HDP(x)                        (((x) & 0x1) << 17)
+#define   G_00000D_FORCE_HDP(x)                        (((x) >> 17) & 0x1)
+#define   C_00000D_FORCE_HDP                           0xFFFDFFFF
+#define   S_00000D_FORCE_DISP1(x)                      (((x) & 0x1) << 18)
+#define   G_00000D_FORCE_DISP1(x)                      (((x) >> 18) & 0x1)
+#define   C_00000D_FORCE_DISP1                         0xFFFBFFFF
+#define   S_00000D_FORCE_TOP(x)                        (((x) & 0x1) << 19)
+#define   G_00000D_FORCE_TOP(x)                        (((x) >> 19) & 0x1)
+#define   C_00000D_FORCE_TOP                           0xFFF7FFFF
+#define   S_00000D_FORCE_E2(x)                         (((x) & 0x1) << 20)
+#define   G_00000D_FORCE_E2(x)                         (((x) >> 20) & 0x1)
+#define   C_00000D_FORCE_E2                            0xFFEFFFFF
+#define   S_00000D_FORCE_SE(x)                         (((x) & 0x1) << 21)
+#define   G_00000D_FORCE_SE(x)                         (((x) >> 21) & 0x1)
+#define   C_00000D_FORCE_SE                            0xFFDFFFFF
+#define   S_00000D_FORCE_IDCT(x)                       (((x) & 0x1) << 22)
+#define   G_00000D_FORCE_IDCT(x)                       (((x) >> 22) & 0x1)
+#define   C_00000D_FORCE_IDCT                          0xFFBFFFFF
+#define   S_00000D_FORCE_VIP(x)                        (((x) & 0x1) << 23)
+#define   G_00000D_FORCE_VIP(x)                        (((x) >> 23) & 0x1)
+#define   C_00000D_FORCE_VIP                           0xFF7FFFFF
+#define   S_00000D_FORCE_RE(x)                         (((x) & 0x1) << 24)
+#define   G_00000D_FORCE_RE(x)                         (((x) >> 24) & 0x1)
+#define   C_00000D_FORCE_RE                            0xFEFFFFFF
+#define   S_00000D_FORCE_PB(x)                         (((x) & 0x1) << 25)
+#define   G_00000D_FORCE_PB(x)                         (((x) >> 25) & 0x1)
+#define   C_00000D_FORCE_PB                            0xFDFFFFFF
+#define   S_00000D_FORCE_TAM(x)                        (((x) & 0x1) << 26)
+#define   G_00000D_FORCE_TAM(x)                        (((x) >> 26) & 0x1)
+#define   C_00000D_FORCE_TAM                           0xFBFFFFFF
+#define   S_00000D_FORCE_TDM(x)                        (((x) & 0x1) << 27)
+#define   G_00000D_FORCE_TDM(x)                        (((x) >> 27) & 0x1)
+#define   C_00000D_FORCE_TDM                           0xF7FFFFFF
+#define   S_00000D_FORCE_RB(x)                         (((x) & 0x1) << 28)
+#define   G_00000D_FORCE_RB(x)                         (((x) >> 28) & 0x1)
+#define   C_00000D_FORCE_RB                            0xEFFFFFFF
+#define   S_00000D_FORCE_TV_SCLK(x)                    (((x) & 0x1) << 29)
+#define   G_00000D_FORCE_TV_SCLK(x)                    (((x) >> 29) & 0x1)
+#define   C_00000D_FORCE_TV_SCLK                       0xDFFFFFFF
+#define   S_00000D_FORCE_SUBPIC(x)                     (((x) & 0x1) << 30)
+#define   G_00000D_FORCE_SUBPIC(x)                     (((x) >> 30) & 0x1)
+#define   C_00000D_FORCE_SUBPIC                        0xBFFFFFFF
+#define   S_00000D_FORCE_OV0(x)                        (((x) & 0x1) << 31)
+#define   G_00000D_FORCE_OV0(x)                        (((x) >> 31) & 0x1)
+#define   C_00000D_FORCE_OV0                           0x7FFFFFFF
+
+#endif
diff --git a/drivers/gpu/drm/radeon/rv350d.h b/drivers/gpu/drm/radeon/rv350d.h
new file mode 100644
index 000000000000..c75c5ed9e654
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv350d.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __RV350D_H__
+#define __RV350D_H__
+
+/* RV350, RV380 registers */
+/* #define R_00000D_SCLK_CNTL                           0x00000D */
+#define   S_00000D_FORCE_VAP(x)                        (((x) & 0x1) << 21)
+#define   G_00000D_FORCE_VAP(x)                        (((x) >> 21) & 0x1)
+#define   C_00000D_FORCE_VAP                           0xFFDFFFFF
+#define   S_00000D_FORCE_SR(x)                         (((x) & 0x1) << 25)
+#define   G_00000D_FORCE_SR(x)                         (((x) >> 25) & 0x1)
+#define   C_00000D_FORCE_SR                            0xFDFFFFFF
+#define   S_00000D_FORCE_PX(x)                         (((x) & 0x1) << 26)
+#define   G_00000D_FORCE_PX(x)                         (((x) >> 26) & 0x1)
+#define   C_00000D_FORCE_PX                            0xFBFFFFFF
+#define   S_00000D_FORCE_TX(x)                         (((x) & 0x1) << 27)
+#define   G_00000D_FORCE_TX(x)                         (((x) >> 27) & 0x1)
+#define   C_00000D_FORCE_TX                            0xF7FFFFFF
+#define   S_00000D_FORCE_US(x)                         (((x) & 0x1) << 28)
+#define   G_00000D_FORCE_US(x)                         (((x) >> 28) & 0x1)
+#define   C_00000D_FORCE_US                            0xEFFFFFFF
+#define   S_00000D_FORCE_SU(x)                         (((x) & 0x1) << 30)
+#define   G_00000D_FORCE_SU(x)                         (((x) >> 30) & 0x1)
+#define   C_00000D_FORCE_SU                            0xBFFFFFFF
+
+#endif
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index e53b5ca7a253..41a34c23e6d8 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -478,7 +478,7 @@ static int rv515_startup(struct radeon_device *rdev)
         }
         /* Enable IRQ */
         rdev->irq.sw_int = true;
-        r100_irq_set(rdev);
+        rs600_irq_set(rdev);
         /* 1M ring buffer */
         r = r100_cp_init(rdev, 1024 * 1024);
         if (r) {
@@ -520,7 +520,7 @@ int rv515_suspend(struct radeon_device *rdev)
 {
         r100_cp_disable(rdev);
         r100_wb_disable(rdev);
-        r100_irq_disable(rdev);
+        rs600_irq_disable(rdev);
         if (rdev->flags & RADEON_IS_PCIE)
                 rv370_pcie_gart_disable(rdev);
         return 0;
@@ -553,7 +553,6 @@ int rv515_init(struct radeon_device *rdev)
 {
         int r;
 
-        rdev->new_init_path = true;
         /* Initialize scratch registers */
         radeon_scratch_init(rdev);
         /* Initialize surface registers */
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index e0b97d161397..595ac638039d 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -75,7 +75,7 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
-        WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
+        WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
@@ -126,17 +126,36 @@ void rv770_pcie_gart_fini(struct radeon_device *rdev)
 }
 
 
-/*
- * MC
- */
-static void rv770_mc_resume(struct radeon_device *rdev)
+void rv770_agp_enable(struct radeon_device *rdev)
 {
-        u32 d1vga_control, d2vga_control;
-        u32 vga_render_control, vga_hdp_control;
-        u32 d1crtc_control, d2crtc_control;
-        u32 new_d1grph_primary, new_d1grph_secondary;
-        u32 new_d2grph_primary, new_d2grph_secondary;
-        u64 old_vram_start;
+        u32 tmp;
+        int i;
+
+        /* Setup L2 cache */
+        WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
+                                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
+                                EFFECTIVE_L2_QUEUE_SIZE(7));
+        WREG32(VM_L2_CNTL2, 0);
+        WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
+        /* Setup TLB control */
+        tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
+                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
+                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
+                EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
+        WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
+        WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
+        WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
+        WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
+        WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
+        WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
+        WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
+        for (i = 0; i < 7; i++)
+                WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
+}
+
+static void rv770_mc_program(struct radeon_device *rdev)
+{
+        struct rv515_mc_save save;
         u32 tmp;
         int i, j;
 
@@ -150,53 +169,42 @@ static void rv770_mc_resume(struct radeon_device *rdev)
         }
         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 
-        d1vga_control = RREG32(D1VGA_CONTROL);
-        d2vga_control = RREG32(D2VGA_CONTROL);
-        vga_render_control = RREG32(VGA_RENDER_CONTROL);
-        vga_hdp_control = RREG32(VGA_HDP_CONTROL);
-        d1crtc_control = RREG32(D1CRTC_CONTROL);
-        d2crtc_control = RREG32(D2CRTC_CONTROL);
-        old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
-        new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
-        new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
-        new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
-        new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
-        new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
-        new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
-        new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
-        new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
-
-        /* Stop all video */
-        WREG32(D1VGA_CONTROL, 0);
-        WREG32(D2VGA_CONTROL, 0);
-        WREG32(VGA_RENDER_CONTROL, 0);
-        WREG32(D1CRTC_UPDATE_LOCK, 1);
-        WREG32(D2CRTC_UPDATE_LOCK, 1);
-        WREG32(D1CRTC_CONTROL, 0);
-        WREG32(D2CRTC_CONTROL, 0);
-        WREG32(D1CRTC_UPDATE_LOCK, 0);
-        WREG32(D2CRTC_UPDATE_LOCK, 0);
-
-        mdelay(1);
+        rv515_mc_stop(rdev, &save);
         if (r600_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "[drm] MC not idle !\n");
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
         }
-
         /* Lockout access through VGA aperture*/
         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
-
         /* Update configuration */
-        WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
-        WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
+        if (rdev->flags & RADEON_IS_AGP) {
+                if (rdev->mc.vram_start < rdev->mc.gtt_start) {
+                        /* VRAM before AGP */
+                        WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+                                rdev->mc.vram_start >> 12);
+                        WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+                                rdev->mc.gtt_end >> 12);
+                } else {
+                        /* VRAM after AGP */
+                        WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+                                rdev->mc.gtt_start >> 12);
+                        WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+                                rdev->mc.vram_end >> 12);
+                }
+        } else {
+                WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+                        rdev->mc.vram_start >> 12);
+                WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+                        rdev->mc.vram_end >> 12);
+        }
         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
-        tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
+        tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
         WREG32(MC_VM_FB_LOCATION, tmp);
         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
         WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
         if (rdev->flags & RADEON_IS_AGP) {
-                WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
+                WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
         } else {
@@ -204,31 +212,10 @@ static void rv770_mc_resume(struct radeon_device *rdev)
                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
         }
-        WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
-        WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
-        WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
-        WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
-        WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
-
-        /* Unlock host access */
-        WREG32(VGA_HDP_CONTROL, vga_hdp_control);
-
-        mdelay(1);
         if (r600_mc_wait_for_idle(rdev)) {
-                printk(KERN_WARNING "[drm] MC not idle !\n");
+                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
         }
-
-        /* Restore video state */
-        WREG32(D1CRTC_UPDATE_LOCK, 1);
-        WREG32(D2CRTC_UPDATE_LOCK, 1);
-        WREG32(D1CRTC_CONTROL, d1crtc_control);
-        WREG32(D2CRTC_CONTROL, d2crtc_control);
-        WREG32(D1CRTC_UPDATE_LOCK, 0);
-        WREG32(D2CRTC_UPDATE_LOCK, 0);
-        WREG32(D1VGA_CONTROL, d1vga_control);
-        WREG32(D2VGA_CONTROL, d2vga_control);
-        WREG32(VGA_RENDER_CONTROL, vga_render_control);
-
+        rv515_mc_resume(rdev, &save);
         /* we need to own VRAM, so turn off the VGA renderer here
          * to stop it overwriting our objects */
         rv515_vga_render_disable(rdev);
@@ -840,9 +827,9 @@ int rv770_mc_init(struct radeon_device *rdev)
                 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
         }
         rdev->mc.vram_start = rdev->mc.vram_location;
-        rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
+        rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
         rdev->mc.gtt_start = rdev->mc.gtt_location;
-        rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
+        rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
         /* FIXME: we should enforce default clock in case GPU is not in
          * default setup
          */
@@ -861,11 +848,14 @@ static int rv770_startup(struct radeon_device *rdev)
 {
         int r;
 
-        radeon_gpu_reset(rdev);
-        rv770_mc_resume(rdev);
-        r = rv770_pcie_gart_enable(rdev);
-        if (r)
-                return r;
+        rv770_mc_program(rdev);
+        if (rdev->flags & RADEON_IS_AGP) {
+                rv770_agp_enable(rdev);
+        } else {
+                r = rv770_pcie_gart_enable(rdev);
+                if (r)
+                        return r;
+        }
         rv770_gpu_init(rdev);
 
         r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
@@ -884,9 +874,8 @@ static int rv770_startup(struct radeon_device *rdev)
         r = r600_cp_resume(rdev);
         if (r)
                 return r;
-        r = r600_wb_init(rdev);
-        if (r)
-                return r;
+        /* write back buffer are not vital so don't worry about failure */
+        r600_wb_enable(rdev);
         return 0;
 }
 
@@ -894,15 +883,12 @@ int rv770_resume(struct radeon_device *rdev)
 {
         int r;
 
-        if (radeon_gpu_reset(rdev)) {
-                /* FIXME: what do we want to do here ? */
-        }
+        /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
+         * posting will perform necessary task to bring back GPU into good
+         * shape.
+         */
         /* post card */
-        if (rdev->is_atom_bios) {
-                atom_asic_init(rdev->mode_info.atom_context);
-        } else {
-                radeon_combios_asic_init(rdev->ddev);
-        }
+        atom_asic_init(rdev->mode_info.atom_context);
         /* Initialize clocks */
         r = radeon_clocks_init(rdev);
         if (r) {
@@ -915,7 +901,7 @@ int rv770_resume(struct radeon_device *rdev)
                 return r;
         }
 
-        r = radeon_ib_test(rdev);
+        r = r600_ib_test(rdev);
         if (r) {
                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
                 return r;
@@ -929,8 +915,8 @@ int rv770_suspend(struct radeon_device *rdev)
         /* FIXME: we should wait for ring to be empty */
         r700_cp_stop(rdev);
         rdev->cp.ready = false;
+        r600_wb_disable(rdev);
         rv770_pcie_gart_disable(rdev);
-
         /* unpin shaders bo */
         radeon_object_unpin(rdev->r600_blit.shader_obj);
         return 0;
@@ -946,7 +932,6 @@ int rv770_init(struct radeon_device *rdev)
 {
         int r;
 
-        rdev->new_init_path = true;
         r = radeon_dummy_page_init(rdev);
         if (r)
                 return r;
@@ -960,8 +945,10 @@ int rv770_init(struct radeon_device *rdev)
                         return -EINVAL;
         }
         /* Must be an ATOMBIOS */
-        if (!rdev->is_atom_bios)
+        if (!rdev->is_atom_bios) {
+                dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
                 return -EINVAL;
+        }
         r = radeon_atombios_init(rdev);
         if (r)
                 return r;
@@ -983,15 +970,8 @@ int rv770_init(struct radeon_device *rdev)
         if (r)
                 return r;
         r = rv770_mc_init(rdev);
-        if (r) {
-                if (rdev->flags & RADEON_IS_AGP) {
-                        /* Retry with disabling AGP */
-                        rv770_fini(rdev);
-                        rdev->flags &= ~RADEON_IS_AGP;
-                        return rv770_init(rdev);
-                }
+        if (r)
                 return r;
-        }
         /* Memory manager */
         r = radeon_object_init(rdev);
         if (r)
@@ -1020,12 +1000,10 @@ int rv770_init(struct radeon_device *rdev)
 
         r = rv770_startup(rdev);
         if (r) {
-                if (rdev->flags & RADEON_IS_AGP) {
-                        /* Retry with disabling AGP */
-                        rv770_fini(rdev);
-                        rdev->flags &= ~RADEON_IS_AGP;
-                        return rv770_init(rdev);
-                }
+                rv770_suspend(rdev);
+                r600_wb_fini(rdev);
+                radeon_ring_fini(rdev);
+                rv770_pcie_gart_fini(rdev);
                 rdev->accel_working = false;
         }
         if (rdev->accel_working) {
@@ -1034,7 +1012,7 @@ int rv770_init(struct radeon_device *rdev)
                         DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
                         rdev->accel_working = false;
                 }
-                r = radeon_ib_test(rdev);
+                r = r600_ib_test(rdev);
                 if (r) {
                         DRM_ERROR("radeon: failled testing IB (%d).\n", r);
                         rdev->accel_working = false;
@@ -1049,20 +1027,15 @@ void rv770_fini(struct radeon_device *rdev)
 
         r600_blit_fini(rdev);
         radeon_ring_fini(rdev);
+        r600_wb_fini(rdev);
         rv770_pcie_gart_fini(rdev);
         radeon_gem_fini(rdev);
         radeon_fence_driver_fini(rdev);
         radeon_clocks_fini(rdev);
-#if __OS_HAS_AGP
         if (rdev->flags & RADEON_IS_AGP)
                 radeon_agp_fini(rdev);
-#endif
         radeon_object_fini(rdev);
-        if (rdev->is_atom_bios) {
-                radeon_atombios_fini(rdev);
-        } else {
-                radeon_combios_fini(rdev);
-        }
+        radeon_atombios_fini(rdev);
         kfree(rdev->bios);
         rdev->bios = NULL;
         radeon_dummy_page_fini(rdev);
diff --git a/drivers/gpu/drm/ttm/ttm_global.c b/drivers/gpu/drm/ttm/ttm_global.c
index 541744d00d3e..b17007178a36 100644
--- a/drivers/gpu/drm/ttm/ttm_global.c
+++ b/drivers/gpu/drm/ttm/ttm_global.c
@@ -82,8 +82,8 @@ int ttm_global_item_ref(struct ttm_global_reference *ref)
                 if (unlikely(ret != 0))
                         goto out_err;
 
-                ++item->refcount;
         }
+        ++item->refcount;
         ref->object = item->object;
         object = item->object;
         mutex_unlock(&item->mutex);
diff --git a/drivers/hwmon/lis3lv02d_spi.c b/drivers/hwmon/lis3lv02d_spi.c
index ecd739534f6a..82b16808a274 100644
--- a/drivers/hwmon/lis3lv02d_spi.c
+++ b/drivers/hwmon/lis3lv02d_spi.c
@@ -83,7 +83,8 @@ static int __devexit lis302dl_spi_remove(struct spi_device *spi)
         struct lis3lv02d *lis3 = spi_get_drvdata(spi);
         lis3lv02d_joystick_disable();
         lis3lv02d_poweroff(lis3);
-        return 0;
+
+        return lis3lv02d_remove_fs(&lis3_dev);
 }
 
 #ifdef CONFIG_PM
diff --git a/drivers/ide/ide-proc.c b/drivers/ide/ide-proc.c
index 28d09a5d8450..017c09540c2f 100644
--- a/drivers/ide/ide-proc.c
+++ b/drivers/ide/ide-proc.c
@@ -273,14 +273,8 @@ static const struct ide_proc_devset ide_generic_settings[] = {
 
 static void proc_ide_settings_warn(void)
 {
-        static int warned;
-
-        if (warned)
-                return;
-
-        printk(KERN_WARNING "Warning: /proc/ide/hd?/settings interface is "
+        printk_once(KERN_WARNING "Warning: /proc/ide/hd?/settings interface is "
                             "obsolete, and will be removed soon!\n");
-        warned = 1;
 }
 
 static int ide_settings_proc_show(struct seq_file *m, void *v)
diff --git a/drivers/ide/sis5513.c b/drivers/ide/sis5513.c
index afca22beaadf..3b88eba04c9c 100644
--- a/drivers/ide/sis5513.c
+++ b/drivers/ide/sis5513.c
@@ -2,7 +2,7 @@
  * Copyright (C) 1999-2000      Andre Hedrick <andre@linux-ide.org>
  * Copyright (C) 2002           Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
  * Copyright (C) 2003           Vojtech Pavlik <vojtech@suse.cz>
- * Copyright (C) 2007           Bartlomiej Zolnierkiewicz
+ * Copyright (C) 2007-2009      Bartlomiej Zolnierkiewicz
  *
  * May be copied or modified under the terms of the GNU General Public License
  *
@@ -281,11 +281,13 @@ static void config_drive_art_rwp(ide_drive_t *drive)
 
         pci_read_config_byte(dev, 0x4b, &reg4bh);
 
+        rw_prefetch = reg4bh & ~(0x11 << drive->dn);
+
         if (drive->media == ide_disk)
-                rw_prefetch = 0x11 << drive->dn;
+                rw_prefetch |= 0x11 << drive->dn;
 
-        if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch)
-                pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
+        if (reg4bh != rw_prefetch)
+                pci_write_config_byte(dev, 0x4b, rw_prefetch);
 }
 
 static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
diff --git a/drivers/isdn/capi/capi.c b/drivers/isdn/capi/capi.c
index 2d8352419c0d..65bf91e16a42 100644
--- a/drivers/isdn/capi/capi.c
+++ b/drivers/isdn/capi/capi.c
@@ -603,7 +603,7 @@ static void capi_recv_message(struct capi20_appl *ap, struct sk_buff *skb)
 
         if (CAPIMSG_CMD(skb->data) == CAPI_CONNECT_B3_CONF) {
                 u16 info = CAPIMSG_U16(skb->data, 12); // Info field
-                if (info == 0) {
+                if ((info & 0xff00) == 0) {
                         mutex_lock(&cdev->ncci_list_mtx);
                         capincci_alloc(cdev, CAPIMSG_NCCI(skb->data));
                         mutex_unlock(&cdev->ncci_list_mtx);
diff --git a/drivers/isdn/capi/capidrv.c b/drivers/isdn/capi/capidrv.c
index 650120261abf..3e6d17f42a98 100644
--- a/drivers/isdn/capi/capidrv.c
+++ b/drivers/isdn/capi/capidrv.c
@@ -40,7 +40,7 @@ static int debugmode = 0;
 MODULE_DESCRIPTION("CAPI4Linux: Interface to ISDN4Linux");
 MODULE_AUTHOR("Carsten Paeth");
 MODULE_LICENSE("GPL");
-module_param(debugmode, uint, 0);
+module_param(debugmode, uint, S_IRUGO|S_IWUSR);
 
 /* -------- type definitions ----------------------------------------- */
 
@@ -671,8 +671,8 @@ static void n0(capidrv_contr * card, capidrv_ncci * ncci)
                                  NULL,  /* Useruserdata */   /* $$$$ */
                                  NULL   /* Facilitydataarray */
         );
-        send_message(card, &cmsg);
         plci_change_state(card, ncci->plcip, EV_PLCI_DISCONNECT_REQ);
+        send_message(card, &cmsg);
 
         cmd.command = ISDN_STAT_BHUP;
         cmd.driver = card->myid;
@@ -924,8 +924,8 @@ static void handle_incoming_call(capidrv_contr * card, _cmsg * cmsg)
                  */
                 capi_cmsg_answer(cmsg);
                 cmsg->Reject = 1;       /* ignore */
-                send_message(card, cmsg);
                 plci_change_state(card, plcip, EV_PLCI_CONNECT_REJECT);
+                send_message(card, cmsg);
                 printk(KERN_INFO "capidrv-%d: incoming call %s,%d,%d,%s ignored\n",
                         card->contrnr,
                         cmd.parm.setup.phone,
@@ -974,8 +974,8 @@ static void handle_incoming_call(capidrv_contr * card, _cmsg * cmsg)
         case 2:         /* Call will be rejected. */
                 capi_cmsg_answer(cmsg);
                 cmsg->Reject = 2;       /* reject call, normal call clearing */
-                send_message(card, cmsg);
                 plci_change_state(card, plcip, EV_PLCI_CONNECT_REJECT);
+                send_message(card, cmsg);
                 break;
 
         default:
@@ -983,8 +983,8 @@ static void handle_incoming_call(capidrv_contr * card, _cmsg * cmsg)
                 capi_cmsg_answer(cmsg);
                 cmsg->Reject = 8;       /* reject call,
                                            destination out of order */
-                send_message(card, cmsg);
                 plci_change_state(card, plcip, EV_PLCI_CONNECT_REJECT);
+                send_message(card, cmsg);
                 break;
         }
         return;
@@ -1020,8 +1020,8 @@ static void handle_plci(_cmsg * cmsg)
                 card->bchans[plcip->chan].disconnecting = 1;
                 plci_change_state(card, plcip, EV_PLCI_DISCONNECT_IND);
                 capi_cmsg_answer(cmsg);
-                send_message(card, cmsg);
                 plci_change_state(card, plcip, EV_PLCI_DISCONNECT_RESP);
+                send_message(card, cmsg);
                 break;
 
         case CAPI_DISCONNECT_CONF:      /* plci */
@@ -1078,8 +1078,8 @@ static void handle_plci(_cmsg * cmsg)
 
                 if (card->bchans[plcip->chan].incoming) {
                         capi_cmsg_answer(cmsg);
-                        send_message(card, cmsg);
                         plci_change_state(card, plcip, EV_PLCI_CONNECT_ACTIVE_IND);
+                        send_message(card, cmsg);
                 } else {
                         capidrv_ncci *nccip;
                         capi_cmsg_answer(cmsg);
@@ -1098,13 +1098,14 @@ static void handle_plci(_cmsg * cmsg)
                                                  NULL   /* NCPI */
                         );
                         nccip->msgid = cmsg->Messagenumber;
+                        plci_change_state(card, plcip,
+                                          EV_PLCI_CONNECT_ACTIVE_IND);
+                        ncci_change_state(card, nccip, EV_NCCI_CONNECT_B3_REQ);
                         send_message(card, cmsg);
                         cmd.command = ISDN_STAT_DCONN;
                         cmd.driver = card->myid;
                         cmd.arg = plcip->chan;
                         card->interface.statcallb(&cmd);
-                        plci_change_state(card, plcip, EV_PLCI_CONNECT_ACTIVE_IND);
-                        ncci_change_state(card, nccip, EV_NCCI_CONNECT_B3_REQ);
                 }
                 break;
 
@@ -1193,8 +1194,8 @@ static void handle_ncci(_cmsg * cmsg)
                         goto notfound;
 
                 capi_cmsg_answer(cmsg);
-                send_message(card, cmsg);
                 ncci_change_state(card, nccip, EV_NCCI_CONNECT_B3_ACTIVE_IND);
+                send_message(card, cmsg);
 
                 cmd.command = ISDN_STAT_BCONN;
                 cmd.driver = card->myid;
@@ -1222,8 +1223,8 @@ static void handle_ncci(_cmsg * cmsg)
                                                           0,    /* Reject */
                                                           NULL  /* NCPI */
                                 );
-                                send_message(card, cmsg);
                                 ncci_change_state(card, nccip, EV_NCCI_CONNECT_B3_RESP);
+                                send_message(card, cmsg);
                                 break;
                         }
                         printk(KERN_ERR "capidrv-%d: no mem for ncci, sorry\n",                                                 card->contrnr);
@@ -1299,8 +1300,8 @@ static void handle_ncci(_cmsg * cmsg)
                 card->bchans[nccip->chan].disconnecting = 1;
                 ncci_change_state(card, nccip, EV_NCCI_DISCONNECT_B3_IND);
                 capi_cmsg_answer(cmsg);
-                send_message(card, cmsg);
                 ncci_change_state(card, nccip, EV_NCCI_DISCONNECT_B3_RESP);
+                send_message(card, cmsg);
                 break;
 
         case CAPI_DISCONNECT_B3_CONF:   /* ncci */
@@ -2014,8 +2015,8 @@ static void send_listen(capidrv_contr *card)
                              card->cipmask,
                              card->cipmask2,
                              NULL, NULL);
-        send_message(card, &cmdcmsg);
         listen_change_state(card, EV_LISTEN_REQ);
+        send_message(card, &cmdcmsg);
 }
 
 static void listentimerfunc(unsigned long x)
diff --git a/drivers/isdn/gigaset/asyncdata.c b/drivers/isdn/gigaset/asyncdata.c
index 234cc5d53312..44a58e6f8f65 100644
--- a/drivers/isdn/gigaset/asyncdata.c
+++ b/drivers/isdn/gigaset/asyncdata.c
@@ -334,7 +334,14 @@ static inline int iraw_loop(unsigned char c, unsigned char *src, int numbytes,
         return startbytes - numbytes;
 }
 
-/* process a block of data received from the device
+/**
+ * gigaset_m10x_input() - process a block of data received from the device
+ * @inbuf:      received data and device descriptor structure.
+ *
+ * Called by hardware module {ser,usb}_gigaset with a block of received
+ * bytes. Separates the bytes received over the serial data channel into
+ * user data and command replies (locked/unlocked) according to the
+ * current state of the interface.
  */
 void gigaset_m10x_input(struct inbuf_t *inbuf)
 {
@@ -543,16 +550,17 @@ static struct sk_buff *iraw_encode(struct sk_buff *skb, int head, int tail)
         return iraw_skb;
 }
 
-/* gigaset_send_skb
- * called by common.c to queue an skb for sending
- * and start transmission if necessary
- * parameters:
- *      B Channel control structure
- *      skb
+/**
+ * gigaset_m10x_send_skb() - queue an skb for sending
+ * @bcs:        B channel descriptor structure.
+ * @skb:        data to send.
+ *
+ * Called by i4l.c to encode and queue an skb for sending, and start
+ * transmission if necessary.
+ *
  * Return value:
- *      number of bytes accepted for sending
- *      (skb->len if ok, 0 if out of buffer space)
- *      or error code (< 0, eg. -EINVAL)
+ *      number of bytes accepted for sending (skb->len) if ok,
+ *      error code < 0 (eg. -ENOMEM) on error
  */
 int gigaset_m10x_send_skb(struct bc_state *bcs, struct sk_buff *skb)
 {
diff --git a/drivers/isdn/gigaset/bas-gigaset.c b/drivers/isdn/gigaset/bas-gigaset.c
index 781c4041f7b0..5ed1d99eb9f3 100644
--- a/drivers/isdn/gigaset/bas-gigaset.c
+++ b/drivers/isdn/gigaset/bas-gigaset.c
@@ -134,6 +134,7 @@ struct bas_cardstate {
 #define BS_ATRDPEND     0x040   /* urb_cmd_in in use */
 #define BS_ATWRPEND     0x080   /* urb_cmd_out in use */
 #define BS_SUSPEND      0x100   /* USB port suspended */
+#define BS_RESETTING    0x200   /* waiting for HD_RESET_INTERRUPT_PIPE_ACK */
 
 
 static struct gigaset_driver *driver = NULL;
@@ -319,6 +320,21 @@ static int gigaset_set_line_ctrl(struct cardstate *cs, unsigned cflag)
         return -EINVAL;
 }
 
+/* set/clear bits in base connection state, return previous state
+ */
+static inline int update_basstate(struct bas_cardstate *ucs,
+                                  int set, int clear)
+{
+        unsigned long flags;
+        int state;
+
+        spin_lock_irqsave(&ucs->lock, flags);
+        state = ucs->basstate;
+        ucs->basstate = (state & ~clear) | set;
+        spin_unlock_irqrestore(&ucs->lock, flags);
+        return state;
+}
+
 /* error_hangup
  * hang up any existing connection because of an unrecoverable error
  * This function may be called from any context and takes care of scheduling
@@ -350,12 +366,9 @@ static inline void error_hangup(struct bc_state *bcs)
  */
 static inline void error_reset(struct cardstate *cs)
 {
-        /* close AT command channel to recover (ignore errors) */
-        req_submit(cs->bcs, HD_CLOSE_ATCHANNEL, 0, BAS_TIMEOUT);
-
-        //FIXME try to recover without bothering the user
-        dev_err(cs->dev,
-            "unrecoverable error - please disconnect Gigaset base to reset\n");
+        /* reset interrupt pipe to recover (ignore errors) */
+        update_basstate(cs->hw.bas, BS_RESETTING, 0);
+        req_submit(cs->bcs, HD_RESET_INTERRUPT_PIPE, 0, BAS_TIMEOUT);
 }
 
 /* check_pending
@@ -398,8 +411,13 @@ static void check_pending(struct bas_cardstate *ucs)
         case HD_DEVICE_INIT_ACK:                /* no reply expected */
                 ucs->pending = 0;
                 break;
-        /* HD_READ_ATMESSAGE, HD_WRITE_ATMESSAGE, HD_RESET_INTERRUPTPIPE
-         * are handled separately and should never end up here
+        case HD_RESET_INTERRUPT_PIPE:
+                if (!(ucs->basstate & BS_RESETTING))
+                        ucs->pending = 0;
+                break;
+        /*
+         * HD_READ_ATMESSAGE and HD_WRITE_ATMESSAGE are handled separately
+         * and should never end up here
          */
         default:
                 dev_warn(&ucs->interface->dev,
@@ -449,21 +467,6 @@ static void cmd_in_timeout(unsigned long data)
         error_reset(cs);
 }
 
-/* set/clear bits in base connection state, return previous state
- */
-inline static int update_basstate(struct bas_cardstate *ucs,
-                                  int set, int clear)
-{
-        unsigned long flags;
-        int state;
-
-        spin_lock_irqsave(&ucs->lock, flags);
-        state = ucs->basstate;
-        ucs->basstate = (state & ~clear) | set;
-        spin_unlock_irqrestore(&ucs->lock, flags);
-        return state;
-}
-
 /* read_ctrl_callback
  * USB completion handler for control pipe input
  * called by the USB subsystem in interrupt context
@@ -762,7 +765,8 @@ static void read_int_callback(struct urb *urb)
                 break;
 
         case HD_RESET_INTERRUPT_PIPE_ACK:
-                gig_dbg(DEBUG_USBREQ, "HD_RESET_INTERRUPT_PIPE_ACK");
+                update_basstate(ucs, 0, BS_RESETTING);
+                dev_notice(cs->dev, "interrupt pipe reset\n");
                 break;
 
         case HD_SUSPEND_END:
@@ -1331,28 +1335,24 @@ static void read_iso_tasklet(unsigned long data)
                 rcvbuf = urb->transfer_buffer;
                 totleft = urb->actual_length;
                 for (frame = 0; totleft > 0 && frame < BAS_NUMFRAMES; frame++) {
-                        if (unlikely(urb->iso_frame_desc[frame].status)) {
+                        numbytes = urb->iso_frame_desc[frame].actual_length;
+                        if (unlikely(urb->iso_frame_desc[frame].status))
                                 dev_warn(cs->dev,
-                                         "isochronous read: frame %d: %s\n",
-                                         frame,
+                                         "isochronous read: frame %d[%d]: %s\n",
+                                         frame, numbytes,
                                          get_usb_statmsg(
                                             urb->iso_frame_desc[frame].status));
-                                break;
-                        }
-                        numbytes = urb->iso_frame_desc[frame].actual_length;
-                        if (unlikely(numbytes > BAS_MAXFRAME)) {
+                        if (unlikely(numbytes > BAS_MAXFRAME))
                                 dev_warn(cs->dev,
                                          "isochronous read: frame %d: "
                                          "numbytes (%d) > BAS_MAXFRAME\n",
                                          frame, numbytes);
-                                break;
-                        }
                         if (unlikely(numbytes > totleft)) {
                                 dev_warn(cs->dev,
                                          "isochronous read: frame %d: "
                                          "numbytes (%d) > totleft (%d)\n",
                                          frame, numbytes, totleft);
-                                break;
+                                numbytes = totleft;
                         }
                         offset = urb->iso_frame_desc[frame].offset;
                         if (unlikely(offset + numbytes > BAS_INBUFSIZE)) {
@@ -1361,7 +1361,7 @@ static void read_iso_tasklet(unsigned long data)
                                          "offset (%d) + numbytes (%d) "
                                          "> BAS_INBUFSIZE\n",
                                          frame, offset, numbytes);
-                                break;
+                                numbytes = BAS_INBUFSIZE - offset;
                         }
                         gigaset_isoc_receive(rcvbuf + offset, numbytes, bcs);
                         totleft -= numbytes;
@@ -1433,6 +1433,7 @@ static void req_timeout(unsigned long data)
 
         case HD_CLOSE_ATCHANNEL:
                 dev_err(bcs->cs->dev, "timeout closing AT channel\n");
+                error_reset(bcs->cs);
                 break;
 
         case HD_CLOSE_B2CHANNEL:
@@ -1442,6 +1443,13 @@ static void req_timeout(unsigned long data)
                 error_reset(bcs->cs);
                 break;
 
+        case HD_RESET_INTERRUPT_PIPE:
+                /* error recovery escalation */
+                dev_err(bcs->cs->dev,
+                        "reset interrupt pipe timeout, attempting USB reset\n");
+                usb_queue_reset_device(bcs->cs->hw.bas->interface);
+                break;
+
         default:
                 dev_warn(bcs->cs->dev, "request 0x%02x timed out, clearing\n",
                          pending);
@@ -1934,6 +1942,15 @@ static int gigaset_write_cmd(struct cardstate *cs,
                 goto notqueued;
         }
 
+        /* translate "+++" escape sequence sent as a single separate command
+         * into "close AT channel" command for error recovery
+         * The next command will reopen the AT channel automatically.
+         */
+        if (len == 3 && !memcmp(buf, "+++", 3)) {
+                rc = req_submit(cs->bcs, HD_CLOSE_ATCHANNEL, 0, BAS_TIMEOUT);
+                goto notqueued;
+        }
+
         if (len > IF_WRITEBUF)
                 len = IF_WRITEBUF;
         if (!(cb = kmalloc(sizeof(struct cmdbuf_t) + len, GFP_ATOMIC))) {
diff --git a/drivers/isdn/gigaset/common.c b/drivers/isdn/gigaset/common.c
index e4141bf8b2f3..33dcd8d72b7c 100644
--- a/drivers/isdn/gigaset/common.c
+++ b/drivers/isdn/gigaset/common.c
@@ -22,6 +22,12 @@
 #define DRIVER_AUTHOR "Hansjoerg Lipp <hjlipp@web.de>, Tilman Schmidt <tilman@imap.cc>, Stefan Eilers"
 #define DRIVER_DESC "Driver for Gigaset 307x"
 
+#ifdef CONFIG_GIGASET_DEBUG
+#define DRIVER_DESC_DEBUG " (debug build)"
+#else
+#define DRIVER_DESC_DEBUG ""
+#endif
+
 /* Module parameters */
 int gigaset_debuglevel = DEBUG_DEFAULT;
 EXPORT_SYMBOL_GPL(gigaset_debuglevel);
@@ -32,6 +38,17 @@ MODULE_PARM_DESC(debug, "debug level");
 #define VALID_MINOR     0x01
 #define VALID_ID        0x02
 
+/**
+ * gigaset_dbg_buffer() - dump data in ASCII and hex for debugging
+ * @level:      debugging level.
+ * @msg:        message prefix.
+ * @len:        number of bytes to dump.
+ * @buf:        data to dump.
+ *
+ * If the current debugging level includes one of the bits set in @level,
+ * @len bytes starting at @buf are logged to dmesg at KERN_DEBUG prio,
+ * prefixed by the text @msg.
+ */
 void gigaset_dbg_buffer(enum debuglevel level, const unsigned char *msg,
                         size_t len, const unsigned char *buf)
 {
@@ -274,6 +291,20 @@ static void clear_events(struct cardstate *cs)
         spin_unlock_irqrestore(&cs->ev_lock, flags);
 }
 
+/**
+ * gigaset_add_event() - add event to device event queue
+ * @cs:         device descriptor structure.
+ * @at_state:   connection state structure.
+ * @type:       event type.
+ * @ptr:        pointer parameter for event.
+ * @parameter:  integer parameter for event.
+ * @arg:        pointer parameter for event.
+ *
+ * Allocate an event queue entry from the device's event queue, and set it up
+ * with the parameters given.
+ *
+ * Return value: added event
+ */
 struct event_t *gigaset_add_event(struct cardstate *cs,
                                   struct at_state_t *at_state, int type,
                                   void *ptr, int parameter, void *arg)
@@ -398,6 +429,15 @@ static void make_invalid(struct cardstate *cs, unsigned mask)
         spin_unlock_irqrestore(&drv->lock, flags);
 }
 
+/**
+ * gigaset_freecs() - free all associated ressources of a device
+ * @cs:         device descriptor structure.
+ *
+ * Stops all tasklets and timers, unregisters the device from all
+ * subsystems it was registered to, deallocates the device structure
+ * @cs and all structures referenced from it.
+ * Operations on the device should be stopped before calling this.
+ */
 void gigaset_freecs(struct cardstate *cs)
 {
         int i;
@@ -506,7 +546,12 @@ static void gigaset_inbuf_init(struct inbuf_t *inbuf, struct bc_state *bcs,
         inbuf->inputstate = inputstate;
 }
 
-/* append received bytes to inbuf */
+/**
+ * gigaset_fill_inbuf() - append received data to input buffer
+ * @inbuf:      buffer structure.
+ * @src:        received data.
+ * @numbytes:   number of bytes received.
+ */
 int gigaset_fill_inbuf(struct inbuf_t *inbuf, const unsigned char *src,
                        unsigned numbytes)
 {
@@ -606,20 +651,22 @@ static struct bc_state *gigaset_initbcs(struct bc_state *bcs,
         return NULL;
 }
 
-/* gigaset_initcs
+/**
+ * gigaset_initcs() - initialize device structure
+ * @drv:        hardware driver the device belongs to
+ * @channels:   number of B channels supported by device
+ * @onechannel: !=0 if B channel data and AT commands share one
+ *                  communication channel (M10x),
+ *              ==0 if B channels have separate communication channels (base)
+ * @ignoreframes:       number of frames to ignore after setting up B channel
+ * @cidmode:    !=0: start in CallID mode
+ * @modulename: name of driver module for LL registration
+ *
  * Allocate and initialize cardstate structure for Gigaset driver
  * Calls hardware dependent gigaset_initcshw() function
  * Calls B channel initialization function gigaset_initbcs() for each B channel
- * parameters:
- *      drv             hardware driver the device belongs to
- *      channels        number of B channels supported by device
- *      onechannel      !=0: B channel data and AT commands share one
- *                           communication channel
- *                      ==0: B channels have separate communication channels
- *      ignoreframes    number of frames to ignore after setting up B channel
- *      cidmode         !=0: start in CallID mode
- *      modulename      name of driver module (used for I4L registration)
- * return value:
+ *
+ * Return value:
  *      pointer to cardstate structure
  */
 struct cardstate *gigaset_initcs(struct gigaset_driver *drv, int channels,
@@ -837,6 +884,17 @@ static void cleanup_cs(struct cardstate *cs)
 }
 
 
+/**
+ * gigaset_start() - start device operations
+ * @cs:         device descriptor structure.
+ *
+ * Prepares the device for use by setting up communication parameters,
+ * scheduling an EV_START event to initiate device initialization, and
+ * waiting for completion of the initialization.
+ *
+ * Return value:
+ *      1 - success, 0 - error
+ */
 int gigaset_start(struct cardstate *cs)
 {
         unsigned long flags;
@@ -879,9 +937,15 @@ error:
 }
 EXPORT_SYMBOL_GPL(gigaset_start);
 
-/* gigaset_shutdown
- * check if a device is associated to the cardstate structure and stop it
- * return value: 0 if ok, -1 if no device was associated
+/**
+ * gigaset_shutdown() - shut down device operations
+ * @cs:         device descriptor structure.
+ *
+ * Deactivates the device by scheduling an EV_SHUTDOWN event and
+ * waiting for completion of the shutdown.
+ *
+ * Return value:
+ *      0 - success, -1 - error (no device associated)
  */
 int gigaset_shutdown(struct cardstate *cs)
 {
@@ -912,6 +976,13 @@ exit:
 }
 EXPORT_SYMBOL_GPL(gigaset_shutdown);
 
+/**
+ * gigaset_stop() - stop device operations
+ * @cs:         device descriptor structure.
+ *
+ * Stops operations on the device by scheduling an EV_STOP event and
+ * waiting for completion of the shutdown.
+ */
 void gigaset_stop(struct cardstate *cs)
 {
         mutex_lock(&cs->mutex);
@@ -1020,6 +1091,14 @@ struct cardstate *gigaset_get_cs_by_tty(struct tty_struct *tty)
         return gigaset_get_cs_by_minor(tty->index + tty->driver->minor_start);
 }
 
+/**
+ * gigaset_freedriver() - free all associated ressources of a driver
+ * @drv:        driver descriptor structure.
+ *
+ * Unregisters the driver from the system and deallocates the driver
+ * structure @drv and all structures referenced from it.
+ * All devices should be shut down before calling this.
+ */
 void gigaset_freedriver(struct gigaset_driver *drv)
 {
         unsigned long flags;
@@ -1035,14 +1114,16 @@ void gigaset_freedriver(struct gigaset_driver *drv)
 }
 EXPORT_SYMBOL_GPL(gigaset_freedriver);
 
-/* gigaset_initdriver
+/**
+ * gigaset_initdriver() - initialize driver structure
+ * @minor:      First minor number
+ * @minors:     Number of minors this driver can handle
+ * @procname:   Name of the driver
+ * @devname:    Name of the device files (prefix without minor number)
+ *
  * Allocate and initialize gigaset_driver structure. Initialize interface.
- * parameters:
- *      minor           First minor number
- *      minors          Number of minors this driver can handle
- *      procname        Name of the driver
- *      devname         Name of the device files (prefix without minor number)
- * return value:
+ *
+ * Return value:
  *      Pointer to the gigaset_driver structure on success, NULL on failure.
  */
 struct gigaset_driver *gigaset_initdriver(unsigned minor, unsigned minors,
@@ -1095,6 +1176,13 @@ error:
 }
 EXPORT_SYMBOL_GPL(gigaset_initdriver);
 
+/**
+ * gigaset_blockdriver() - block driver
+ * @drv:        driver descriptor structure.
+ *
+ * Prevents the driver from attaching new devices, in preparation for
+ * deregistration.
+ */
 void gigaset_blockdriver(struct gigaset_driver *drv)
 {
         drv->blocked = 1;
@@ -1110,7 +1198,7 @@ static int __init gigaset_init_module(void)
         if (gigaset_debuglevel == 1)
                 gigaset_debuglevel = DEBUG_DEFAULT;
 
-        pr_info(DRIVER_DESC "\n");
+        pr_info(DRIVER_DESC DRIVER_DESC_DEBUG "\n");
         return 0;
 }
 
diff --git a/drivers/isdn/gigaset/ev-layer.c b/drivers/isdn/gigaset/ev-layer.c
index 2d91049571a4..cc768caa38f5 100644
--- a/drivers/isdn/gigaset/ev-layer.c
+++ b/drivers/isdn/gigaset/ev-layer.c
@@ -207,7 +207,6 @@ struct reply_t gigaset_tab_nocid[] =
         /* leave dle mode */
         {RSP_INIT,      0,  0,SEQ_DLE0,           201, 5, {0},             "^SDLE=0\r"},
         {RSP_OK,      201,201, -1,                202,-1},
-        //{RSP_ZDLE,    202,202,  0,                202, 0, {ACT_ERROR}},//DELETE
         {RSP_ZDLE,    202,202,  0,                  0, 0, {ACT_DLE0}},
         {RSP_NODEV,   200,249, -1,                  0, 0, {ACT_FAKEDLE0}},
         {RSP_ERROR,   200,249, -1,                  0, 0, {ACT_FAILDLE0}},
@@ -265,6 +264,7 @@ struct reply_t gigaset_tab_nocid[] =
         {EV_SHUTDOWN,  -1, -1, -1,                 -1,-1, {ACT_SHUTDOWN}}, //FIXME
 
         /* misc. */
+        {RSP_ERROR,    -1, -1, -1,                 -1, -1, {ACT_ERROR} },
         {RSP_EMPTY,    -1, -1, -1,                 -1,-1, {ACT_DEBUG}}, //FIXME
         {RSP_ZCFGT,    -1, -1, -1,                 -1,-1, {ACT_DEBUG}}, //FIXME
         {RSP_ZCFG,     -1, -1, -1,                 -1,-1, {ACT_DEBUG}}, //FIXME
@@ -328,10 +328,9 @@ struct reply_t gigaset_tab_cid[] =
         {RSP_INIT,     -1, -1,SEQ_HUP,            401, 5, {0},             "+VLS=0\r"}, /* hang up */ //-1,-1?
         {RSP_OK,      401,401, -1,                402, 5},
         {RSP_ZVLS,    402,402,  0,                403, 5},
-        {RSP_ZSAU,    403,403,ZSAU_DISCONNECT_REQ, -1,-1, {ACT_DEBUG}}, /* if not remote hup */
-        //{RSP_ZSAU,    403,403,ZSAU_NULL,          401, 0, {ACT_ERROR}}, //DELETE//FIXME -> DLE0 // should we do this _before_ hanging up for base driver?
-        {RSP_ZSAU,    403,403,ZSAU_NULL,            0, 0, {ACT_DISCONNECT}}, //FIXME -> DLE0 // should we do this _before_ hanging up for base driver?
-        {RSP_NODEV,   401,403, -1,                  0, 0, {ACT_FAKEHUP}}, //FIXME -> DLE0 // should we do this _before_ hanging up for base driver?
+        {RSP_ZSAU,    403, 403, ZSAU_DISCONNECT_REQ, -1, -1, {ACT_DEBUG} },
+        {RSP_ZSAU,    403, 403, ZSAU_NULL,            0,  0, {ACT_DISCONNECT} },
+        {RSP_NODEV,   401, 403, -1,                   0,  0, {ACT_FAKEHUP} },
         {RSP_ERROR,   401,401, -1,                  0, 0, {ACT_ABORTHUP}},
         {EV_TIMEOUT,  401,403, -1,                  0, 0, {ACT_ABORTHUP}},
 
@@ -474,8 +473,13 @@ static int cid_of_response(char *s)
         //FIXME is ;<digit>+ at end of non-CID response really impossible?
 }
 
-/* This function will be called via task queue from the callback handler.
- * We received a modem response and have to handle it..
+/**
+ * gigaset_handle_modem_response() - process received modem response
+ * @cs:         device descriptor structure.
+ *
+ * Called by asyncdata/isocdata if a block of data received from the
+ * device must be processed as a modem command response. The data is
+ * already in the cs structure.
  */
 void gigaset_handle_modem_response(struct cardstate *cs)
 {
@@ -707,6 +711,11 @@ static void disconnect(struct at_state_t **at_state_p)
         if (bcs) {
                 /* B channel assigned: invoke hardware specific handler */
                 cs->ops->close_bchannel(bcs);
+                /* notify LL */
+                if (bcs->chstate & (CHS_D_UP | CHS_NOTIFY_LL)) {
+                        bcs->chstate &= ~(CHS_D_UP | CHS_NOTIFY_LL);
+                        gigaset_i4l_channel_cmd(bcs, ISDN_STAT_DHUP);
+                }
         } else {
                 /* no B channel assigned: just deallocate */
                 spin_lock_irqsave(&cs->lock, flags);
@@ -1429,11 +1438,12 @@ static void do_action(int action, struct cardstate *cs,
                 cs->gotfwver = -1;
                 dev_err(cs->dev, "could not read firmware version.\n");
                 break;
-#ifdef CONFIG_GIGASET_DEBUG
         case ACT_ERROR:
-                *p_genresp = 1;
-                *p_resp_code = RSP_ERROR;
+                gig_dbg(DEBUG_ANY, "%s: ERROR response in ConState %d",
+                        __func__, at_state->ConState);
+                cs->cur_at_seq = SEQ_NONE;
                 break;
+#ifdef CONFIG_GIGASET_DEBUG
         case ACT_TEST:
                 {
                         static int count = 3; //2; //1;
diff --git a/drivers/isdn/gigaset/i4l.c b/drivers/isdn/gigaset/i4l.c
index 9b22f9cf2f33..654489d836cd 100644
--- a/drivers/isdn/gigaset/i4l.c
+++ b/drivers/isdn/gigaset/i4l.c
@@ -51,6 +51,12 @@ static int writebuf_from_LL(int driverID, int channel, int ack,
                 return -ENODEV;
         }
         bcs = &cs->bcs[channel];
+
+        /* can only handle linear sk_buffs */
+        if (skb_linearize(skb) < 0) {
+                dev_err(cs->dev, "%s: skb_linearize failed\n", __func__);
+                return -ENOMEM;
+        }
         len = skb->len;
 
         gig_dbg(DEBUG_LLDATA,
@@ -79,6 +85,14 @@ static int writebuf_from_LL(int driverID, int channel, int ack,
         return cs->ops->send_skb(bcs, skb);
 }
 
+/**
+ * gigaset_skb_sent() - acknowledge sending an skb
+ * @bcs:        B channel descriptor structure.
+ * @skb:        sent data.
+ *
+ * Called by hardware module {bas,ser,usb}_gigaset when the data in a
+ * skb has been successfully sent, for signalling completion to the LL.
+ */
 void gigaset_skb_sent(struct bc_state *bcs, struct sk_buff *skb)
 {
         unsigned len;
@@ -455,6 +469,15 @@ int gigaset_isdn_setup_accept(struct at_state_t *at_state)
         return 0;
 }
 
+/**
+ * gigaset_isdn_icall() - signal incoming call
+ * @at_state:   connection state structure.
+ *
+ * Called by main module to notify the LL that an incoming call has been
+ * received. @at_state contains the parameters of the call.
+ *
+ * Return value: call disposition (ICALL_*)
+ */
 int gigaset_isdn_icall(struct at_state_t *at_state)
 {
         struct cardstate *cs = at_state->cs;
diff --git a/drivers/isdn/gigaset/interface.c b/drivers/isdn/gigaset/interface.c
index f33ac27de643..6a8e1384e7bd 100644
--- a/drivers/isdn/gigaset/interface.c
+++ b/drivers/isdn/gigaset/interface.c
@@ -616,6 +616,15 @@ void gigaset_if_free(struct cardstate *cs)
         tty_unregister_device(drv->tty, cs->minor_index);
 }
 
+/**
+ * gigaset_if_receive() - pass a received block of data to the tty device
+ * @cs:         device descriptor structure.
+ * @buffer:     received data.
+ * @len:        number of bytes received.
+ *
+ * Called by asyncdata/isocdata if a block of data received from the
+ * device must be sent to userspace through the ttyG* device.
+ */
 void gigaset_if_receive(struct cardstate *cs,
                         unsigned char *buffer, size_t len)
 {
diff --git a/drivers/isdn/gigaset/isocdata.c b/drivers/isdn/gigaset/isocdata.c
index bed38fcc432b..9f3ef7b4248c 100644
--- a/drivers/isdn/gigaset/isocdata.c
+++ b/drivers/isdn/gigaset/isocdata.c
@@ -429,7 +429,7 @@ static inline int hdlc_buildframe(struct isowbuf_t *iwb,
                 return -EAGAIN;
         }
 
-        dump_bytes(DEBUG_STREAM, "snd data", in, count);
+        dump_bytes(DEBUG_STREAM_DUMP, "snd data", in, count);
 
         /* bitstuff and checksum input data */
         fcs = PPP_INITFCS;
@@ -448,7 +448,6 @@ static inline int hdlc_buildframe(struct isowbuf_t *iwb,
         /* put closing flag and repeat byte for flag idle */
         isowbuf_putflag(iwb);
         end = isowbuf_donewrite(iwb);
-        dump_bytes(DEBUG_STREAM_DUMP, "isowbuf", iwb->data, end + 1);
         return end;
 }
 
@@ -482,6 +481,8 @@ static inline int trans_buildframe(struct isowbuf_t *iwb,
         }
 
         gig_dbg(DEBUG_STREAM, "put %d bytes", count);
+        dump_bytes(DEBUG_STREAM_DUMP, "snd data", in, count);
+
         write = iwb->write;
         do {
                 c = bitrev8(*in++);
@@ -583,7 +584,7 @@ static inline void hdlc_done(struct bc_state *bcs)
                 procskb->tail -= 2;
                 gig_dbg(DEBUG_ISO, "%s: good frame (%d octets)",
                         __func__, procskb->len);
-                dump_bytes(DEBUG_STREAM,
+                dump_bytes(DEBUG_STREAM_DUMP,
                            "rcv data", procskb->data, procskb->len);
                 bcs->hw.bas->goodbytes += procskb->len;
                 gigaset_rcv_skb(procskb, bcs->cs, bcs);
@@ -878,6 +879,8 @@ static inline void trans_receive(unsigned char *src, unsigned count,
                         dobytes--;
                 }
                 if (dobytes == 0) {
+                        dump_bytes(DEBUG_STREAM_DUMP,
+                                   "rcv data", skb->data, skb->len);
                         gigaset_rcv_skb(skb, bcs->cs, bcs);
                         bcs->skb = skb = dev_alloc_skb(SBUFSIZE + HW_HDR_LEN);
                         if (!skb) {
@@ -973,16 +976,17 @@ void gigaset_isoc_input(struct inbuf_t *inbuf)
 
 /* == data output ========================================================== */
 
-/* gigaset_send_skb
- * called by common.c to queue an skb for sending
- * and start transmission if necessary
- * parameters:
- *      B Channel control structure
- *      skb
- * return value:
- *      number of bytes accepted for sending
- *      (skb->len if ok, 0 if out of buffer space)
- *      or error code (< 0, eg. -EINVAL)
+/**
+ * gigaset_isoc_send_skb() - queue an skb for sending
+ * @bcs:        B channel descriptor structure.
+ * @skb:        data to send.
+ *
+ * Called by i4l.c to queue an skb for sending, and start transmission if
+ * necessary.
+ *
+ * Return value:
+ *      number of bytes accepted for sending (skb->len) if ok,
+ *      error code < 0 (eg. -ENODEV) on error
  */
 int gigaset_isoc_send_skb(struct bc_state *bcs, struct sk_buff *skb)
 {
diff --git a/drivers/mmc/core/sdio_cis.c b/drivers/mmc/core/sdio_cis.c
index e1035c895808..f85dcd536508 100644
--- a/drivers/mmc/core/sdio_cis.c
+++ b/drivers/mmc/core/sdio_cis.c
@@ -29,6 +29,8 @@ static int cistpl_vers_1(struct mmc_card *card, struct sdio_func *func,
         unsigned i, nr_strings;
         char **buffer, *string;
 
+        /* Find all null-terminated (including zero length) strings in
+           the TPLLV1_INFO field. Trailing garbage is ignored. */
         buf += 2;
         size -= 2;
 
@@ -39,11 +41,8 @@ static int cistpl_vers_1(struct mmc_card *card, struct sdio_func *func,
                 if (buf[i] == 0)
                         nr_strings++;
         }
-
-        if (nr_strings < 4) {
-                printk(KERN_WARNING "SDIO: ignoring broken CISTPL_VERS_1\n");
+        if (nr_strings == 0)
                 return 0;
-        }
 
         size = i;
 
diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c
index fdf5937233fc..04f63c77071d 100644
--- a/drivers/net/au1000_eth.c
+++ b/drivers/net/au1000_eth.c
@@ -721,7 +721,7 @@ static inline void update_rx_stats(struct net_device *dev, u32 status)
                 ps->rx_errors++;
                 if (status & RX_MISSED_FRAME)
                         ps->rx_missed_errors++;
-                if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR))
+                if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
                         ps->rx_length_errors++;
                 if (status & RX_CRC_ERROR)
                         ps->rx_crc_errors++;
@@ -794,8 +794,6 @@ static int au1000_rx(struct net_device *dev)
                                         printk("rx len error\n");
                                 if (status & RX_U_CNTRL_FRAME)
                                         printk("rx u control frame\n");
-                                if (status & RX_MISSED_FRAME)
-                                        printk("rx miss\n");
                         }
                 }
                 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
diff --git a/drivers/net/benet/be_cmds.c b/drivers/net/benet/be_cmds.c
index 79d35d122c08..89876ade5e33 100644
--- a/drivers/net/benet/be_cmds.c
+++ b/drivers/net/benet/be_cmds.c
@@ -1129,7 +1129,6 @@ int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
         spin_lock_bh(&adapter->mcc_lock);
 
         wrb = wrb_from_mccq(adapter);
-        req = embedded_payload(wrb);
         sge = nonembedded_sgl(wrb);
 
         be_wrb_hdr_prepare(wrb, cmd->size, false, 1);
diff --git a/drivers/net/benet/be_cmds.h b/drivers/net/benet/be_cmds.h
index 8b4c2cb9ad62..a86f917f85f4 100644
--- a/drivers/net/benet/be_cmds.h
+++ b/drivers/net/benet/be_cmds.h
@@ -62,7 +62,7 @@ enum {
         MCC_STATUS_QUEUE_FLUSHING = 0x4,
 /* The command is completing with a DMA error */
         MCC_STATUS_DMA_FAILED = 0x5,
-        MCC_STATUS_NOT_SUPPORTED = 0x66
+        MCC_STATUS_NOT_SUPPORTED = 66
 };
 
 #define CQE_STATUS_COMPL_MASK           0xFFFF
diff --git a/drivers/net/benet/be_ethtool.c b/drivers/net/benet/be_ethtool.c
index 11445df3dbc0..cda5bf2fc50a 100644
--- a/drivers/net/benet/be_ethtool.c
+++ b/drivers/net/benet/be_ethtool.c
@@ -358,7 +358,7 @@ const struct ethtool_ops be_ethtool_ops = {
         .get_rx_csum = be_get_rx_csum,
         .set_rx_csum = be_set_rx_csum,
         .get_tx_csum = ethtool_op_get_tx_csum,
-        .set_tx_csum = ethtool_op_set_tx_csum,
+        .set_tx_csum = ethtool_op_set_tx_hw_csum,
         .get_sg = ethtool_op_get_sg,
         .set_sg = ethtool_op_set_sg,
         .get_tso = ethtool_op_get_tso,
diff --git a/drivers/net/benet/be_main.c b/drivers/net/benet/be_main.c
index 2f9b50156e0c..6d5e81f7046f 100644
--- a/drivers/net/benet/be_main.c
+++ b/drivers/net/benet/be_main.c
@@ -197,7 +197,7 @@ void netdev_stats_update(struct be_adapter *adapter)
         /* no space available in linux */
         dev_stats->tx_dropped = 0;
 
-        dev_stats->multicast = port_stats->tx_multicastframes;
+        dev_stats->multicast = port_stats->rx_multicast_frames;
         dev_stats->collisions = 0;
 
         /* detailed tx_errors */
@@ -1899,8 +1899,8 @@ static void be_netdev_init(struct net_device *netdev)
         struct be_adapter *adapter = netdev_priv(netdev);
 
         netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
-                NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_IP_CSUM |
-                NETIF_F_IPV6_CSUM | NETIF_F_GRO;
+                NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
+                NETIF_F_GRO;
 
         netdev->flags |= IFF_MULTICAST;
 
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c
index b53b40ba88a8..d1e0563a67df 100644
--- a/drivers/net/e1000e/82571.c
+++ b/drivers/net/e1000e/82571.c
@@ -1803,7 +1803,7 @@ struct e1000_info e1000_82574_info = {
                                   | FLAG_HAS_AMT
                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
         .pba                    = 20,
-        .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
+        .max_hw_frame_size      = DEFAULT_JUMBO,
         .get_variants           = e1000_get_variants_82571,
         .mac_ops                = &e82571_mac_ops,
         .phy_ops                = &e82_phy_ops_bm,
@@ -1820,7 +1820,7 @@ struct e1000_info e1000_82583_info = {
                                   | FLAG_HAS_AMT
                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
         .pba                    = 20,
-        .max_hw_frame_size      = DEFAULT_JUMBO,
+        .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
         .get_variants           = e1000_get_variants_82571,
         .mac_ops                = &e82571_mac_ops,
         .phy_ops                = &e82_phy_ops_bm,
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index b7311bc00258..34d0c69e67f7 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -19,6 +19,10 @@
 #include <linux/platform_device.h>
 #include <net/ethoc.h>
 
+static int buffer_size = 0x8000; /* 32 KBytes */
+module_param(buffer_size, int, 0);
+MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
+
 /* register offsets */
 #define MODER           0x00
 #define INT_SOURCE      0x04
@@ -167,6 +171,7 @@
  * struct ethoc - driver-private device structure
  * @iobase:     pointer to I/O memory region
  * @membase:    pointer to buffer memory region
+ * @dma_alloc:  dma allocated buffer size
  * @num_tx:     number of send buffers
  * @cur_tx:     last send buffer written
  * @dty_tx:     last buffer actually sent
@@ -185,6 +190,7 @@
 struct ethoc {
         void __iomem *iobase;
         void __iomem *membase;
+        int dma_alloc;
 
         unsigned int num_tx;
         unsigned int cur_tx;
@@ -284,7 +290,7 @@ static int ethoc_init_ring(struct ethoc *dev)
         dev->cur_rx = 0;
 
         /* setup transmission buffers */
-        bd.addr = 0;
+        bd.addr = virt_to_phys(dev->membase);
         bd.stat = TX_BD_IRQ | TX_BD_CRC;
 
         for (i = 0; i < dev->num_tx; i++) {
@@ -295,7 +301,6 @@ static int ethoc_init_ring(struct ethoc *dev)
                 bd.addr += ETHOC_BUFSIZ;
         }
 
-        bd.addr = dev->num_tx * ETHOC_BUFSIZ;
         bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
 
         for (i = 0; i < dev->num_rx; i++) {
@@ -400,8 +405,12 @@ static int ethoc_rx(struct net_device *dev, int limit)
                 if (ethoc_update_rx_stats(priv, &bd) == 0) {
                         int size = bd.stat >> 16;
                         struct sk_buff *skb = netdev_alloc_skb(dev, size);
+
+                        size -= 4; /* strip the CRC */
+                        skb_reserve(skb, 2); /* align TCP/IP header */
+
                         if (likely(skb)) {
-                                void *src = priv->membase + bd.addr;
+                                void *src = phys_to_virt(bd.addr);
                                 memcpy_fromio(skb_put(skb, size), src, size);
                                 skb->protocol = eth_type_trans(skb, dev);
                                 priv->stats.rx_packets++;
@@ -653,9 +662,9 @@ static int ethoc_open(struct net_device *dev)
         if (ret)
                 return ret;
 
-        /* calculate the number of TX/RX buffers */
-        num_bd = (dev->mem_end - dev->mem_start + 1) / ETHOC_BUFSIZ;
-        priv->num_tx = min(min_tx, num_bd / 4);
+        /* calculate the number of TX/RX buffers, maximum 128 supported */
+        num_bd = min(128, (dev->mem_end - dev->mem_start + 1) / ETHOC_BUFSIZ);
+        priv->num_tx = max(min_tx, num_bd / 4);
         priv->num_rx = num_bd - priv->num_tx;
         ethoc_write(priv, TX_BD_NUM, priv->num_tx);
 
@@ -823,7 +832,7 @@ static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
         else
                 bd.stat &= ~TX_BD_PAD;
 
-        dest = priv->membase + bd.addr;
+        dest = phys_to_virt(bd.addr);
         memcpy_toio(dest, skb->data, skb->len);
 
         bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
@@ -903,22 +912,19 @@ static int ethoc_probe(struct platform_device *pdev)
 
         /* obtain buffer memory space */
         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-        if (!res) {
-                dev_err(&pdev->dev, "cannot obtain memory space\n");
-                ret = -ENXIO;
-                goto free;
-        }
-
-        mem = devm_request_mem_region(&pdev->dev, res->start,
+        if (res) {
+                mem = devm_request_mem_region(&pdev->dev, res->start,
                         res->end - res->start + 1, res->name);
-        if (!mem) {
-                dev_err(&pdev->dev, "cannot request memory space\n");
-                ret = -ENXIO;
-                goto free;
+                if (!mem) {
+                        dev_err(&pdev->dev, "cannot request memory space\n");
+                        ret = -ENXIO;
+                        goto free;
+                }
+
+                netdev->mem_start = mem->start;
+                netdev->mem_end   = mem->end;
         }
 
-        netdev->mem_start = mem->start;
-        netdev->mem_end   = mem->end;
 
         /* obtain device IRQ number */
         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -933,6 +939,7 @@ static int ethoc_probe(struct platform_device *pdev)
         /* setup driver-private data */
         priv = netdev_priv(netdev);
         priv->netdev = netdev;
+        priv->dma_alloc = 0;
 
         priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
                         mmio->end - mmio->start + 1);
@@ -942,12 +949,27 @@ static int ethoc_probe(struct platform_device *pdev)
                 goto error;
         }
 
-        priv->membase = devm_ioremap_nocache(&pdev->dev, netdev->mem_start,
-                        mem->end - mem->start + 1);
-        if (!priv->membase) {
-                dev_err(&pdev->dev, "cannot remap memory space\n");
-                ret = -ENXIO;
-                goto error;
+        if (netdev->mem_end) {
+                priv->membase = devm_ioremap_nocache(&pdev->dev,
+                        netdev->mem_start, mem->end - mem->start + 1);
+                if (!priv->membase) {
+                        dev_err(&pdev->dev, "cannot remap memory space\n");
+                        ret = -ENXIO;
+                        goto error;
+                }
+        } else {
+                /* Allocate buffer memory */
+                priv->membase = dma_alloc_coherent(NULL,
+                        buffer_size, (void *)&netdev->mem_start,
+                        GFP_KERNEL);
+                if (!priv->membase) {
+                        dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
+                                buffer_size);
+                        ret = -ENOMEM;
+                        goto error;
+                }
+                netdev->mem_end = netdev->mem_start + buffer_size;
+                priv->dma_alloc = buffer_size;
         }
 
         /* Allow the platform setup code to pass in a MAC address. */
@@ -1034,6 +1056,9 @@ free_mdio:
         kfree(priv->mdio->irq);
         mdiobus_free(priv->mdio);
 free:
+        if (priv->dma_alloc)
+                dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
+                        netdev->mem_start);
         free_netdev(netdev);
 out:
         return ret;
@@ -1059,7 +1084,9 @@ static int ethoc_remove(struct platform_device *pdev)
                         kfree(priv->mdio->irq);
                         mdiobus_free(priv->mdio);
                 }
-
+                if (priv->dma_alloc)
+                        dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
+                                netdev->mem_start);
                 unregister_netdev(netdev);
                 free_netdev(netdev);
         }
diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
index 2ec58dcdb82b..34b04924c8a1 100644
--- a/drivers/net/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -330,6 +330,8 @@ static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
 
         switch (hw->device_id) {
         case IXGBE_DEV_ID_82599_KX4:
+        case IXGBE_DEV_ID_82599_KX4_MEZZ:
+        case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
         case IXGBE_DEV_ID_82599_XAUI_LOM:
                 /* Default device ID is mezzanine card KX/KX4 */
                 media_type = ixgbe_media_type_backplane;
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 28fbb9d281f9..cbb143ca1eb8 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -97,8 +97,12 @@ static struct pci_device_id ixgbe_pci_tbl[] = {
          board_82599 },
         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
          board_82599 },
+        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
+         board_82599 },
         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
          board_82599 },
+        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
+         board_82599 },
 
         /* required last entry */
         {0, }
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 7c93e923bf2e..ef4bdd58e016 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -49,9 +49,11 @@
 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM      0x10E1
 #define IXGBE_DEV_ID_82598EB_XF_LR       0x10F4
 #define IXGBE_DEV_ID_82599_KX4           0x10F7
+#define IXGBE_DEV_ID_82599_KX4_MEZZ      0x1514
 #define IXGBE_DEV_ID_82599_CX4           0x10F9
 #define IXGBE_DEV_ID_82599_SFP           0x10FB
 #define IXGBE_DEV_ID_82599_XAUI_LOM      0x10FC
+#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
 
 /* General Registers */
 #define IXGBE_CTRL      0x00000
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c
index b5aa974827e5..9b9eab107704 100644
--- a/drivers/net/netxen/netxen_nic_main.c
+++ b/drivers/net/netxen/netxen_nic_main.c
@@ -1714,7 +1714,7 @@ netxen_nic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
         /* 4 fragments per cmd des */
         no_of_desc = (frag_count + 3) >> 2;
 
-        if (unlikely(no_of_desc + 2) > netxen_tx_avail(tx_ring)) {
+        if (unlikely(no_of_desc + 2 > netxen_tx_avail(tx_ring))) {
                 netif_stop_queue(netdev);
                 return NETDEV_TX_BUSY;
         }
diff --git a/drivers/net/pasemi_mac_ethtool.c b/drivers/net/pasemi_mac_ethtool.c
index 064a4fe1dd90..28a86224879d 100644
--- a/drivers/net/pasemi_mac_ethtool.c
+++ b/drivers/net/pasemi_mac_ethtool.c
@@ -71,6 +71,9 @@ pasemi_mac_ethtool_get_settings(struct net_device *netdev,
         struct pasemi_mac *mac = netdev_priv(netdev);
         struct phy_device *phydev = mac->phydev;
 
+        if (!phydev)
+                return -EOPNOTSUPP;
+
         return phy_ethtool_gset(phydev, cmd);
 }
 
diff --git a/drivers/net/pcmcia/pcnet_cs.c b/drivers/net/pcmcia/pcnet_cs.c
index 474876c879cb..bd3447f04902 100644
--- a/drivers/net/pcmcia/pcnet_cs.c
+++ b/drivers/net/pcmcia/pcnet_cs.c
@@ -1754,14 +1754,14 @@ static struct pcmcia_device_id pcnet_ids[] = {
         PCMCIA_PFC_DEVICE_CIS_PROD_ID12(0, "Psion Dacom", "Gold Card V34 Ethernet", 0xf5f025c2, 0x338e8155, "cis/PCMLM28.cis"),
         PCMCIA_PFC_DEVICE_CIS_PROD_ID12(0, "Psion Dacom", "Gold Card V34 Ethernet GSM", 0xf5f025c2, 0x4ae85d35, "cis/PCMLM28.cis"),
         PCMCIA_PFC_DEVICE_CIS_PROD_ID12(0, "LINKSYS", "PCMLM28", 0xf7cb0b07, 0x66881874, "cis/PCMLM28.cis"),
-        PCMCIA_MFC_DEVICE_CIS_PROD_ID12(0, "DAYNA COMMUNICATIONS", "LAN AND MODEM MULTIFUNCTION", 0x8fdf8f89, 0xdd5ed9e8, "DP83903.cis"),
-        PCMCIA_MFC_DEVICE_CIS_PROD_ID4(0, "NSC MF LAN/Modem", 0x58fc6056, "DP83903.cis"),
-        PCMCIA_MFC_DEVICE_CIS_MANF_CARD(0, 0x0175, 0x0000, "DP83903.cis"),
+        PCMCIA_MFC_DEVICE_CIS_PROD_ID12(0, "DAYNA COMMUNICATIONS", "LAN AND MODEM MULTIFUNCTION", 0x8fdf8f89, 0xdd5ed9e8, "cis/DP83903.cis"),
+        PCMCIA_MFC_DEVICE_CIS_PROD_ID4(0, "NSC MF LAN/Modem", 0x58fc6056, "cis/DP83903.cis"),
+        PCMCIA_MFC_DEVICE_CIS_MANF_CARD(0, 0x0175, 0x0000, "cis/DP83903.cis"),
         PCMCIA_DEVICE_CIS_MANF_CARD(0xc00f, 0x0002, "cis/LA-PCM.cis"),
         PCMCIA_DEVICE_CIS_PROD_ID12("KTI", "PE520 PLUS", 0xad180345, 0x9d58d392, "PE520.cis"),
-        PCMCIA_DEVICE_CIS_PROD_ID12("NDC", "Ethernet", 0x01c43ae1, 0x00b2e941, "NE2K.cis"),
+        PCMCIA_DEVICE_CIS_PROD_ID12("NDC", "Ethernet", 0x01c43ae1, 0x00b2e941, "cis/NE2K.cis"),
         PCMCIA_DEVICE_CIS_PROD_ID12("PMX   ", "PE-200", 0x34f3f1c8, 0x10b59f8c, "PE-200.cis"),
-        PCMCIA_DEVICE_CIS_PROD_ID12("TAMARACK", "Ethernet", 0xcf434fba, 0x00b2e941, "tamarack.cis"),
+        PCMCIA_DEVICE_CIS_PROD_ID12("TAMARACK", "Ethernet", 0xcf434fba, 0x00b2e941, "cis/tamarack.cis"),
         PCMCIA_DEVICE_PROD_ID12("Ethernet", "CF Size PC Card", 0x00b2e941, 0x43ac239b),
         PCMCIA_DEVICE_PROD_ID123("Fast Ethernet", "CF Size PC Card", "1.0",
                 0xb4be14e3, 0x43ac239b, 0x0877b627),
diff --git a/drivers/net/qlge/qlge.h b/drivers/net/qlge/qlge.h
index 30d5585beeee..3ec6e85587a2 100644
--- a/drivers/net/qlge/qlge.h
+++ b/drivers/net/qlge/qlge.h
@@ -9,6 +9,7 @@
 
 #include <linux/pci.h>
 #include <linux/netdevice.h>
+#include <linux/rtnetlink.h>
 
 /*
  * General definitions...
@@ -135,9 +136,9 @@ enum {
         RST_FO_TFO = (1 << 0),
         RST_FO_RR_MASK = 0x00060000,
         RST_FO_RR_CQ_CAM = 0x00000000,
-        RST_FO_RR_DROP = 0x00000001,
-        RST_FO_RR_DQ = 0x00000002,
-        RST_FO_RR_RCV_FUNC_CQ = 0x00000003,
+        RST_FO_RR_DROP = 0x00000002,
+        RST_FO_RR_DQ = 0x00000004,
+        RST_FO_RR_RCV_FUNC_CQ = 0x00000006,
         RST_FO_FRB = (1 << 12),
         RST_FO_MOP = (1 << 13),
         RST_FO_REG = (1 << 14),
@@ -1477,7 +1478,6 @@ struct ql_adapter {
         u32 mailbox_in;
         u32 mailbox_out;
         struct mbox_params idc_mbc;
-        struct mutex    mpi_mutex;
 
         int tx_ring_size;
         int rx_ring_size;
diff --git a/drivers/net/qlge/qlge_ethtool.c b/drivers/net/qlge/qlge_ethtool.c
index 68f9bd280f86..52073946bce3 100644
--- a/drivers/net/qlge/qlge_ethtool.c
+++ b/drivers/net/qlge/qlge_ethtool.c
@@ -45,7 +45,6 @@ static int ql_update_ring_coalescing(struct ql_adapter *qdev)
         if (!netif_running(qdev->ndev))
                 return status;
 
-        spin_lock(&qdev->hw_lock);
         /* Skip the default queue, and update the outbound handler
          * queues if they changed.
          */
@@ -92,7 +91,6 @@ static int ql_update_ring_coalescing(struct ql_adapter *qdev)
                 }
         }
 exit:
-        spin_unlock(&qdev->hw_lock);
         return status;
 }
 
diff --git a/drivers/net/qlge/qlge_main.c b/drivers/net/qlge/qlge_main.c
index 3d0efea32111..61680715cde0 100644
--- a/drivers/net/qlge/qlge_main.c
+++ b/drivers/net/qlge/qlge_main.c
@@ -34,7 +34,6 @@
 #include <linux/etherdevice.h>
 #include <linux/ethtool.h>
 #include <linux/skbuff.h>
-#include <linux/rtnetlink.h>
 #include <linux/if_vlan.h>
 #include <linux/delay.h>
 #include <linux/mm.h>
@@ -1926,12 +1925,10 @@ static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
         if (status)
                 return;
-        spin_lock(&qdev->hw_lock);
         if (ql_set_mac_addr_reg
             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
         }
-        spin_unlock(&qdev->hw_lock);
         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 }
 
@@ -1945,12 +1942,10 @@ static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
         if (status)
                 return;
 
-        spin_lock(&qdev->hw_lock);
         if (ql_set_mac_addr_reg
             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
         }
-        spin_unlock(&qdev->hw_lock);
         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 
 }
@@ -2001,15 +1996,17 @@ static irqreturn_t qlge_isr(int irq, void *dev_id)
         /*
          * Check MPI processor activity.
          */
-        if (var & STS_PI) {
+        if ((var & STS_PI) &&
+                (ql_read32(qdev, INTR_MASK) & INTR_MASK_PI)) {
                 /*
                  * We've got an async event or mailbox completion.
                  * Handle it and clear the source of the interrupt.
                  */
                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
                 ql_disable_completion_interrupt(qdev, intr_context->intr);
-                queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
-                                      &qdev->mpi_work, 0);
+                ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
+                queue_delayed_work_on(smp_processor_id(),
+                                qdev->workqueue, &qdev->mpi_work, 0);
                 work_done++;
         }
 
@@ -3585,7 +3582,6 @@ static void qlge_set_multicast_list(struct net_device *ndev)
         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
         if (status)
                 return;
-        spin_lock(&qdev->hw_lock);
         /*
          * Set or clear promiscuous mode if a
          * transition is taking place.
@@ -3662,7 +3658,6 @@ static void qlge_set_multicast_list(struct net_device *ndev)
                 }
         }
 exit:
-        spin_unlock(&qdev->hw_lock);
         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 }
 
@@ -3682,10 +3677,8 @@ static int qlge_set_mac_address(struct net_device *ndev, void *p)
         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
         if (status)
                 return status;
-        spin_lock(&qdev->hw_lock);
         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
-        spin_unlock(&qdev->hw_lock);
         if (status)
                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
@@ -3928,7 +3921,6 @@ static int __devinit ql_init_device(struct pci_dev *pdev,
         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
         INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
         INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
-        mutex_init(&qdev->mpi_mutex);
         init_completion(&qdev->ide_completion);
 
         if (!cards_found) {
diff --git a/drivers/net/qlge/qlge_mpi.c b/drivers/net/qlge/qlge_mpi.c
index 6685bd97da91..c2e43073047e 100644
--- a/drivers/net/qlge/qlge_mpi.c
+++ b/drivers/net/qlge/qlge_mpi.c
@@ -472,7 +472,6 @@ static int ql_mailbox_command(struct ql_adapter *qdev, struct mbox_params *mbcp)
 {
         int status, count;
 
-        mutex_lock(&qdev->mpi_mutex);
 
         /* Begin polled mode for MPI */
         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
@@ -541,7 +540,6 @@ static int ql_mailbox_command(struct ql_adapter *qdev, struct mbox_params *mbcp)
                 status = -EIO;
         }
 end:
-        mutex_unlock(&qdev->mpi_mutex);
         /* End polled mode for MPI */
         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
         return status;
@@ -776,7 +774,9 @@ static int ql_idc_wait(struct ql_adapter *qdev)
 static int ql_set_port_cfg(struct ql_adapter *qdev)
 {
         int status;
+        rtnl_lock();
         status = ql_mb_set_port_cfg(qdev);
+        rtnl_unlock();
         if (status)
                 return status;
         status = ql_idc_wait(qdev);
@@ -797,7 +797,9 @@ void ql_mpi_port_cfg_work(struct work_struct *work)
             container_of(work, struct ql_adapter, mpi_port_cfg_work.work);
         int status;
 
+        rtnl_lock();
         status = ql_mb_get_port_cfg(qdev);
+        rtnl_unlock();
         if (status) {
                 QPRINTK(qdev, DRV, ERR,
                         "Bug: Failed to get port config data.\n");
@@ -855,7 +857,9 @@ void ql_mpi_idc_work(struct work_struct *work)
                  * needs to be set.
                  * */
                 set_bit(QL_CAM_RT_SET, &qdev->flags);
+                rtnl_lock();
                 status = ql_mb_idc_ack(qdev);
+                rtnl_unlock();
                 if (status) {
                         QPRINTK(qdev, DRV, ERR,
                         "Bug: No pending IDC!\n");
@@ -871,7 +875,7 @@ void ql_mpi_work(struct work_struct *work)
         struct mbox_params *mbcp = &mbc;
         int err = 0;
 
-        mutex_lock(&qdev->mpi_mutex);
+        rtnl_lock();
 
         while (ql_read32(qdev, STS) & STS_PI) {
                 memset(mbcp, 0, sizeof(struct mbox_params));
@@ -884,7 +888,7 @@ void ql_mpi_work(struct work_struct *work)
                         break;
         }
 
-        mutex_unlock(&qdev->mpi_mutex);
+        rtnl_unlock();
         ql_enable_completion_interrupt(qdev, 0);
 }
 
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index f09bc5dfe8b2..ba5d3fe753b6 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -902,11 +902,12 @@ static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
         struct tg3 *tp = bp->priv;
         u32 val;
 
-        if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
-                return -EAGAIN;
+        spin_lock_bh(&tp->lock);
 
         if (tg3_readphy(tp, reg, &val))
-                return -EIO;
+                val = -EIO;
+
+        spin_unlock_bh(&tp->lock);
 
         return val;
 }
@@ -914,14 +915,16 @@ static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 {
         struct tg3 *tp = bp->priv;
+        u32 ret = 0;
 
-        if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
-                return -EAGAIN;
+        spin_lock_bh(&tp->lock);
 
         if (tg3_writephy(tp, reg, val))
-                return -EIO;
+                ret = -EIO;
 
-        return 0;
+        spin_unlock_bh(&tp->lock);
+
+        return ret;
 }
 
 static int tg3_mdio_reset(struct mii_bus *bp)
@@ -1011,12 +1014,6 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
 
 static void tg3_mdio_start(struct tg3 *tp)
 {
-        if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
-                mutex_lock(&tp->mdio_bus->mdio_lock);
-                tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
-                mutex_unlock(&tp->mdio_bus->mdio_lock);
-        }
-
         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
         tw32_f(MAC_MI_MODE, tp->mi_mode);
         udelay(80);
@@ -1041,15 +1038,6 @@ static void tg3_mdio_start(struct tg3 *tp)
                 tg3_mdio_config_5785(tp);
 }
 
-static void tg3_mdio_stop(struct tg3 *tp)
-{
-        if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
-                mutex_lock(&tp->mdio_bus->mdio_lock);
-                tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
-                mutex_unlock(&tp->mdio_bus->mdio_lock);
-        }
-}
-
 static int tg3_mdio_init(struct tg3 *tp)
 {
         int i;
@@ -1141,7 +1129,6 @@ static void tg3_mdio_fini(struct tg3 *tp)
                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
                 mdiobus_unregister(tp->mdio_bus);
                 mdiobus_free(tp->mdio_bus);
-                tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
         }
 }
 
@@ -1363,7 +1350,7 @@ static void tg3_adjust_link(struct net_device *dev)
         struct tg3 *tp = netdev_priv(dev);
         struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
 
-        spin_lock(&tp->lock);
+        spin_lock_bh(&tp->lock);
 
         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
                                     MAC_MODE_HALF_DUPLEX);
@@ -1431,7 +1418,7 @@ static void tg3_adjust_link(struct net_device *dev)
         tp->link_config.active_speed = phydev->speed;
         tp->link_config.active_duplex = phydev->duplex;
 
-        spin_unlock(&tp->lock);
+        spin_unlock_bh(&tp->lock);
 
         if (linkmesg)
                 tg3_link_report(tp);
@@ -6392,8 +6379,6 @@ static int tg3_chip_reset(struct tg3 *tp)
 
         tg3_nvram_lock(tp);
 
-        tg3_mdio_stop(tp);
-
         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
 
         /* No matching tg3_nvram_unlock() after this because
@@ -8698,6 +8683,8 @@ static int tg3_close(struct net_device *dev)
 
         del_timer_sync(&tp->timer);
 
+        tg3_phy_stop(tp);
+
         tg3_full_lock(tp, 1);
 #if 0
         tg3_dump_state(tp);
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 524691cd9896..bab7940158e6 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2748,7 +2748,6 @@ struct tg3 {
 #define TG3_FLG3_5701_DMA_BUG           0x00000008
 #define TG3_FLG3_USE_PHYLIB             0x00000010
 #define TG3_FLG3_MDIOBUS_INITED         0x00000020
-#define TG3_FLG3_MDIOBUS_PAUSED         0x00000040
 #define TG3_FLG3_PHY_CONNECTED          0x00000080
 #define TG3_FLG3_RGMII_STD_IBND_DISABLE 0x00000100
 #define TG3_FLG3_RGMII_EXT_IBND_RX_EN   0x00000200
diff --git a/drivers/net/usb/rndis_host.c b/drivers/net/usb/rndis_host.c
index d032bba9bc4c..0caa8008c51c 100644
--- a/drivers/net/usb/rndis_host.c
+++ b/drivers/net/usb/rndis_host.c
@@ -418,6 +418,7 @@ generic_rndis_bind(struct usbnet *dev, struct usb_interface *intf, int flags)
                 goto halt_fail_and_release;
         }
         memcpy(net->dev_addr, bp, ETH_ALEN);
+        memcpy(net->perm_addr, bp, ETH_ALEN);
 
         /* set a nonzero filter to enable data transfers */
         memset(u.set, 0, sizeof *u.set);
diff --git a/drivers/serial/serial_cs.c b/drivers/serial/serial_cs.c
index a3bb49031a7f..ff4617e21426 100644
--- a/drivers/serial/serial_cs.c
+++ b/drivers/serial/serial_cs.c
@@ -873,10 +873,10 @@ static struct pcmcia_device_id serial_ids[] = {
         PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "Psion Dacom", "Gold Card V34 Ethernet", 0xf5f025c2, 0x338e8155, "cis/PCMLM28.cis"),
         PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "Psion Dacom", "Gold Card V34 Ethernet GSM", 0xf5f025c2, 0x4ae85d35, "cis/PCMLM28.cis"),
         PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "LINKSYS", "PCMLM28", 0xf7cb0b07, 0x66881874, "cis/PCMLM28.cis"),
-        PCMCIA_MFC_DEVICE_CIS_PROD_ID12(1, "DAYNA COMMUNICATIONS", "LAN AND MODEM MULTIFUNCTION", 0x8fdf8f89, 0xdd5ed9e8, "DP83903.cis"),
-        PCMCIA_MFC_DEVICE_CIS_PROD_ID4(1, "NSC MF LAN/Modem", 0x58fc6056, "DP83903.cis"),
+        PCMCIA_MFC_DEVICE_CIS_PROD_ID12(1, "DAYNA COMMUNICATIONS", "LAN AND MODEM MULTIFUNCTION", 0x8fdf8f89, 0xdd5ed9e8, "cis/DP83903.cis"),
+        PCMCIA_MFC_DEVICE_CIS_PROD_ID4(1, "NSC MF LAN/Modem", 0x58fc6056, "cis/DP83903.cis"),
         PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x0556, "cis/3CCFEM556.cis"),
-        PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0175, 0x0000, "DP83903.cis"),
+        PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0175, 0x0000, "cis/DP83903.cis"),
         PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x0035, "cis/3CXEM556.cis"),
         PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x003d, "cis/3CXEM556.cis"),
         PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC850", 0xd85f6206, 0x42a2c018, "SW_8xx_SER.cis"),  /* Sierra Wireless AC850 3G Network Adapter R1 */
@@ -884,9 +884,9 @@ static struct pcmcia_device_id serial_ids[] = {
         PCMCIA_DEVICE_CIS_MANF_CARD(0x0192, 0xa555, "SW_555_SER.cis"),  /* Sierra Aircard 555 CDMA 1xrtt Modem -- pre update */
         PCMCIA_DEVICE_CIS_MANF_CARD(0x013f, 0xa555, "SW_555_SER.cis"),  /* Sierra Aircard 555 CDMA 1xrtt Modem -- post update */
         PCMCIA_DEVICE_CIS_PROD_ID12("MultiTech", "PCMCIA 56K DataFax", 0x842047ee, 0xc2efcf03, "cis/MT5634ZLX.cis"),
-        PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-2", 0x96913a85, 0x27ab5437, "COMpad2.cis"),
-        PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-4", 0x96913a85, 0xcec8f102, "COMpad4.cis"),
-        PCMCIA_DEVICE_CIS_PROD_ID123("ADVANTECH", "COMpad-32/85", "1.0", 0x96913a85, 0x8fbe92ae, 0x0877b627, "COMpad2.cis"),
+        PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-2", 0x96913a85, 0x27ab5437, "cis/COMpad2.cis"),
+        PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-4", 0x96913a85, 0xcec8f102, "cis/COMpad4.cis"),
+        PCMCIA_DEVICE_CIS_PROD_ID123("ADVANTECH", "COMpad-32/85", "1.0", 0x96913a85, 0x8fbe92ae, 0x0877b627, "cis/COMpad2.cis"),
         PCMCIA_DEVICE_CIS_PROD_ID2("RS-COM 2P", 0xad20b156, "cis/RS-COM-2P.cis"),
         PCMCIA_DEVICE_CIS_MANF_CARD(0x0013, 0x0000, "GLOBETROTTER.cis"),
         PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL100  1.00.",0x19ca78af,0xf964f42b),
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index 42e1005e2916..d065894ce38f 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -26,7 +26,6 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/uaccess.h>
-#include <linux/device.h>
 #include <linux/interrupt.h>
 #include <linux/clk.h>
 #include <video/da8xx-fb.h>
diff --git a/drivers/video/msm/mddi.c b/drivers/video/msm/mddi.c
index f2de5a1acd6d..5c5a1ad1d397 100644
--- a/drivers/video/msm/mddi.c
+++ b/drivers/video/msm/mddi.c
@@ -27,8 +27,6 @@
 #include <mach/msm_iomap.h>
 #include <mach/irqs.h>
 #include <mach/board.h>
-#include <linux/delay.h>
-
 #include <mach/msm_fb.h>
 #include "mddi_hw.h"
 
diff --git a/drivers/video/omap/blizzard.c b/drivers/video/omap/blizzard.c
index d5e59556f9e2..70dadf9d2334 100644
--- a/drivers/video/omap/blizzard.c
+++ b/drivers/video/omap/blizzard.c
@@ -93,7 +93,7 @@ struct blizzard_reg_list {
 };
 
 /* These need to be saved / restored separately from the rest. */
-static struct blizzard_reg_list blizzard_pll_regs[] = {
+static const struct blizzard_reg_list blizzard_pll_regs[] = {
         {
                 .start  = 0x04,         /* Don't save PLL ctrl (0x0C) */
                 .end    = 0x0a,
@@ -104,7 +104,7 @@ static struct blizzard_reg_list blizzard_pll_regs[] = {
         },
 };
 
-static struct blizzard_reg_list blizzard_gen_regs[] = {
+static const struct blizzard_reg_list blizzard_gen_regs[] = {
         {
                 .start  = 0x18,         /* SDRAM control */
                 .end    = 0x20,
@@ -191,7 +191,7 @@ struct blizzard_struct {
 
         struct omapfb_device    *fbdev;
         struct lcd_ctrl_extif   *extif;
-        struct lcd_ctrl         *int_ctrl;
+        const struct lcd_ctrl   *int_ctrl;
 
         void                    (*power_up)(struct device *dev);
         void                    (*power_down)(struct device *dev);
@@ -1372,7 +1372,7 @@ static void blizzard_get_caps(int plane, struct omapfb_caps *caps)
                            (1 << OMAPFB_COLOR_YUV420);
 }
 
-static void _save_regs(struct blizzard_reg_list *list, int cnt)
+static void _save_regs(const struct blizzard_reg_list *list, int cnt)
 {
         int i;
 
@@ -1383,7 +1383,7 @@ static void _save_regs(struct blizzard_reg_list *list, int cnt)
         }
 }
 
-static void _restore_regs(struct blizzard_reg_list *list, int cnt)
+static void _restore_regs(const struct blizzard_reg_list *list, int cnt)
 {
         int i;
 
diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
index 125e605b8c68..0d0c8c8b9b56 100644
--- a/drivers/video/omap/omapfb_main.c
+++ b/drivers/video/omap/omapfb_main.c
@@ -393,7 +393,7 @@ static void omapfb_sync(struct fb_info *fbi)
  * Set fb_info.fix fields and also updates fbdev.
  * When calling this fb_info.var must be set up already.
  */
-static void set_fb_fix(struct fb_info *fbi)
+static void set_fb_fix(struct fb_info *fbi, int from_init)
 {
         struct fb_fix_screeninfo *fix = &fbi->fix;
         struct fb_var_screeninfo *var = &fbi->var;
@@ -403,10 +403,16 @@ static void set_fb_fix(struct fb_info *fbi)
 
         rg = &plane->fbdev->mem_desc.region[plane->idx];
         fbi->screen_base        = rg->vaddr;
-        mutex_lock(&fbi->mm_lock);
-        fix->smem_start         = rg->paddr;
-        fix->smem_len           = rg->size;
-        mutex_unlock(&fbi->mm_lock);
+
+        if (!from_init) {
+                mutex_lock(&fbi->mm_lock);
+                fix->smem_start         = rg->paddr;
+                fix->smem_len           = rg->size;
+                mutex_unlock(&fbi->mm_lock);
+        } else {
+                fix->smem_start         = rg->paddr;
+                fix->smem_len           = rg->size;
+        }
 
         fix->type = FB_TYPE_PACKED_PIXELS;
         bpp = var->bits_per_pixel;
@@ -704,7 +710,7 @@ static int omapfb_set_par(struct fb_info *fbi)
         int r = 0;
 
         omapfb_rqueue_lock(fbdev);
-        set_fb_fix(fbi);
+        set_fb_fix(fbi, 0);
         r = ctrl_change_mode(fbi);
         omapfb_rqueue_unlock(fbdev);
 
@@ -904,7 +910,7 @@ static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
                 if (old_size != size) {
                         if (size) {
                                 memcpy(&fbi->var, new_var, sizeof(fbi->var));
-                                set_fb_fix(fbi);
+                                set_fb_fix(fbi, 0);
                         } else {
                                 /*
                                  * Set these explicitly to indicate that the
@@ -1504,7 +1510,7 @@ static int fbinfo_init(struct omapfb_device *fbdev, struct fb_info *info)
         var->bits_per_pixel = fbdev->panel->bpp;
 
         set_fb_var(info, var);
-        set_fb_fix(info);
+        set_fb_fix(info, 1);
 
         r = fb_alloc_cmap(&info->cmap, 16, 0);
         if (r != 0)
diff --git a/firmware/Makefile b/firmware/Makefile
index 5ea80b19785b..a6c7c3e47e42 100644
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -67,10 +67,13 @@ fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin
 fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \
                              e100/d102e_ucode.bin
 fw-shipped-$(CONFIG_MYRI_SBUS) += myricom/lanai.bin
-fw-shipped-$(CONFIG_PCMCIA_PCNET) += cis/LA-PCM.cis cis/PCMLM28.cis
+fw-shipped-$(CONFIG_PCMCIA_PCNET) += cis/LA-PCM.cis cis/PCMLM28.cis \
+                                     cis/DP83903.cis cis/NE2K.cis \
+                                     cis/tamarack.cis
 fw-shipped-$(CONFIG_PCMCIA_3C589) += cis/3CXEM556.cis
 fw-shipped-$(CONFIG_PCMCIA_3C574) += cis/3CCFEM556.cis
-fw-shipped-$(CONFIG_SERIAL_8250_CS) += cis/MT5634ZLX.cis cis/RS-COM-2P.cis
+fw-shipped-$(CONFIG_SERIAL_8250_CS) += cis/MT5634ZLX.cis cis/RS-COM-2P.cis \
+                                       cis/COMpad2.cis cis/COMpad4.cis
 fw-shipped-$(CONFIG_PCMCIA_SMC91C92) += ositech/Xilinx7OD.bin
 fw-shipped-$(CONFIG_SCSI_ADVANSYS) += advansys/mcode.bin advansys/38C1600.bin \
                                       advansys/3550.bin advansys/38C0800.bin
diff --git a/firmware/WHENCE b/firmware/WHENCE
index 3f8c4f6bc43f..c437e14f0b11 100644
--- a/firmware/WHENCE
+++ b/firmware/WHENCE
@@ -597,6 +597,9 @@ Driver: PCMCIA_PCNET - NE2000 compatible PCMCIA adapter
 
 File: cis/LA-PCM.cis
       cis/PCMLM28.cis
+      cis/DP83903.cis
+      cis/NE2K.cis
+      cis/tamarack.cis
 
 Licence: GPL
 
@@ -628,6 +631,8 @@ Driver: SERIAL_8250_CS - Serial PCMCIA adapter
 
 File: cis/MT5634ZLX.cis
       cis/RS-COM-2P.cis
+      cis/COMpad2.cis
+      cis/COMpad4.cis
 
 Licence: GPL
 
diff --git a/firmware/cis/COMpad2.cis.ihex b/firmware/cis/COMpad2.cis.ihex
new file mode 100644
index 000000000000..1671c5e48caa
--- /dev/null
+++ b/firmware/cis/COMpad2.cis.ihex
@@ -0,0 +1,11 @@
+:1000000001030000FF151F0401414456414E5445B1
+:10001000434800434F4D7061642D33322F38350013
+:10002000312E300000FF210202011A0501050001F6
+:10003000031B0EC18118AA61E80207E8030730B864
+:100040009E1B08820108AA6030030F1B0883010869
+:10005000AA6040030F1B08840108AA6050030F1B0D
+:0D00600008850108AA6060030F1400FF006E
+:00000001FF
+#
+# Replacement CIS for Advantech COMpad-32/85
+#
diff --git a/firmware/cis/COMpad4.cis.ihex b/firmware/cis/COMpad4.cis.ihex
new file mode 100644
index 000000000000..27bbec1921b3
--- /dev/null
+++ b/firmware/cis/COMpad4.cis.ihex
@@ -0,0 +1,9 @@
+:1000000001030000FF151F0401414456414E5445B1
+:10001000434800434F4D7061642D33322F383542D1
+:100020002D34000000FF210202011A050102000127
+:10003000011B0BC18118AA6040021F30B89E1B082B
+:0C004000820108AA6040031F1400FF00AA
+:00000001FF
+#
+# Replacement CIS for Advantech COMpad-32/85B-4
+#
diff --git a/firmware/cis/DP83903.cis.ihex b/firmware/cis/DP83903.cis.ihex
new file mode 100644
index 000000000000..6d73ea3cf1b8
--- /dev/null
+++ b/firmware/cis/DP83903.cis.ihex
@@ -0,0 +1,14 @@
+:1000000001030000FF152904014D756C74696675C4
+:100010006E6374696F6E20436172640000004E531A
+:1000200043204D46204C414E2F4D6F64656D00FFBF
+:1000300020047501000021020000060B02004900A7
+:100040000000006A000000FF00130343495321022F
+:1000500006001A060517201077021B0C970179017C
+:10006000556530FFFF284000FF001303434953212B
+:100070000202001A060507401077021B09870119C2
+:0800800001552330FFFFFF00D2
+:00000001FF
+#
+# This CIS is for cards based on the National Semiconductor
+# DP83903 Multiple Function Interface Chip
+#
diff --git a/firmware/cis/NE2K.cis.ihex b/firmware/cis/NE2K.cis.ihex
new file mode 100644
index 000000000000..1bb40fc4759f
--- /dev/null
+++ b/firmware/cis/NE2K.cis.ihex
@@ -0,0 +1,8 @@
+:1000000001030000FF1515040150434D4349410011
+:1000100045746865726E6574000000FF2102060079
+:100020001A050120F803031B09E001190155653089
+:06003000FFFF1400FF00B9
+:00000001FF
+#
+# Replacement CIS for various busted NE2000-compatible cards
+#
diff --git a/firmware/cis/tamarack.cis.ihex b/firmware/cis/tamarack.cis.ihex
new file mode 100644
index 000000000000..1e86547fb361
--- /dev/null
+++ b/firmware/cis/tamarack.cis.ihex
@@ -0,0 +1,10 @@
+:100000000103D400FF17034100FF152404015441EC
+:100010004D415241434B0045746865726E657400F2
+:10002000410030303437343331313830303100FF33
+:10003000210206001A050120F803031B14E08119B0
+:100040003F554D5D06864626E551000F100F30FFE7
+:05005000FF1400FF0099
+:00000001FF
+#
+# Replacement CIS for Surecom, Tamarack NE2000 cards
+#
diff --git a/fs/proc/kcore.c b/fs/proc/kcore.c
index 56013371f9f3..a44a7897fd4d 100644
--- a/fs/proc/kcore.c
+++ b/fs/proc/kcore.c
@@ -23,7 +23,6 @@
 #include <asm/io.h>
 #include <linux/list.h>
 #include <linux/ioport.h>
-#include <linux/mm.h>
 #include <linux/memory.h>
 #include <asm/sections.h>
 
diff --git a/fs/proc/page.c b/fs/proc/page.c
index 2281c2cbfe2b..5033ce0d254b 100644
--- a/fs/proc/page.c
+++ b/fs/proc/page.c
@@ -94,6 +94,7 @@ static const struct file_operations proc_kpagecount_operations = {
 #define KPF_COMPOUND_TAIL       16
 #define KPF_HUGE                17
 #define KPF_UNEVICTABLE         18
+#define KPF_HWPOISON            19
 #define KPF_NOPAGE              20
 
 #define KPF_KSM                 21
@@ -180,6 +181,10 @@ static u64 get_uflags(struct page *page)
         u |= kpf_copy_bit(k, KPF_UNEVICTABLE,   PG_unevictable);
         u |= kpf_copy_bit(k, KPF_MLOCKED,       PG_mlocked);
 
+#ifdef CONFIG_MEMORY_FAILURE
+        u |= kpf_copy_bit(k, KPF_HWPOISON,      PG_hwpoison);
+#endif
+
 #ifdef CONFIG_IA64_UNCACHED_ALLOCATOR
         u |= kpf_copy_bit(k, KPF_UNCACHED,      PG_uncached);
 #endif
diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
index ef47dfd8e5e9..b29e20168b5f 100644
--- a/include/drm/drm_crtc_helper.h
+++ b/include/drm/drm_crtc_helper.h
@@ -61,6 +61,9 @@ struct drm_crtc_helper_funcs {
         /* Move the crtc on the current fb to the given position *optional* */
         int (*mode_set_base)(struct drm_crtc *crtc, int x, int y,
                              struct drm_framebuffer *old_fb);
+
+        /* reload the current crtc LUT */
+        void (*load_lut)(struct drm_crtc *crtc);
 };
 
 struct drm_encoder_helper_funcs {
diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
index 4aa5740ce59f..58c892a2cbfa 100644
--- a/include/drm/drm_fb_helper.h
+++ b/include/drm/drm_fb_helper.h
@@ -39,6 +39,8 @@ struct drm_fb_helper_crtc {
 struct drm_fb_helper_funcs {
         void (*gamma_set)(struct drm_crtc *crtc, u16 red, u16 green,
                           u16 blue, int regno);
+        void (*gamma_get)(struct drm_crtc *crtc, u16 *red, u16 *green,
+                          u16 *blue, int regno);
 };
 
 /* mode specified on the command line */
@@ -71,6 +73,7 @@ struct drm_fb_helper {
 };
 
 int drm_fb_helper_single_fb_probe(struct drm_device *dev,
+                                  int preferred_bpp,
                                   int (*fb_create)(struct drm_device *dev,
                                                    uint32_t fb_width,
                                                    uint32_t fb_height,
@@ -98,9 +101,11 @@ int drm_fb_helper_setcolreg(unsigned regno,
 void drm_fb_helper_restore(void);
 void drm_fb_helper_fill_var(struct fb_info *info, struct drm_framebuffer *fb,
                             uint32_t fb_width, uint32_t fb_height);
-void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch);
+void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch,
+                            uint32_t depth);
 
 int drm_fb_helper_add_connector(struct drm_connector *connector);
 int drm_fb_helper_parse_command_line(struct drm_device *dev);
+int drm_fb_helper_setcmap(struct fb_cmap *cmap, struct fb_info *info);
 
 #endif
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 3f6e545609be..e6f3b120f51a 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -80,7 +80,7 @@
         {0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
         {0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
         {0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
-        {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
+        {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_SINGLE_CRTC}, \
         {0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
         {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
         {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
@@ -113,7 +113,7 @@
         {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
         {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
         {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
-        {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
+        {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_SINGLE_CRTC}, \
         {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
         {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
         {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
diff --git a/include/linux/socket.h b/include/linux/socket.h
index 3b461dffe244..3273a0c5043b 100644
--- a/include/linux/socket.h
+++ b/include/linux/socket.h
@@ -16,7 +16,7 @@ struct __kernel_sockaddr_storage {
                                 /* _SS_MAXSIZE value minus size of ss_family */
 } __attribute__ ((aligned(_K_SS_ALIGNSIZE)));   /* force desired alignment */
 
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#ifdef __KERNEL__
 
 #include <asm/socket.h>                 /* arch-dependent defines       */
 #include <linux/sockios.h>              /* the SIOCxxx I/O controls     */
@@ -101,21 +101,6 @@ struct cmsghdr {
                               ((char *)(cmsg) - (char *)(mhdr)->msg_control)))
 
 /*
- *      This mess will go away with glibc
- */
- 
-#ifdef __KERNEL__
-#define __KINLINE static inline
-#elif  defined(__GNUC__) 
-#define __KINLINE static __inline__
-#elif defined(__cplusplus)
-#define __KINLINE static inline
-#else
-#define __KINLINE static
-#endif
-
-
-/*
  *      Get the next cmsg header
  *
  *      PLEASE, do not touch this function. If you think, that it is
@@ -128,7 +113,7 @@ struct cmsghdr {
  *      ancillary object DATA.                          --ANK (980731)
  */
  
-__KINLINE struct cmsghdr * __cmsg_nxthdr(void *__ctl, __kernel_size_t __size,
+static inline struct cmsghdr * __cmsg_nxthdr(void *__ctl, __kernel_size_t __size,
                                                struct cmsghdr *__cmsg)
 {
         struct cmsghdr * __ptr;
@@ -140,7 +125,7 @@ __KINLINE struct cmsghdr * __cmsg_nxthdr(void *__ctl, __kernel_size_t __size,
         return __ptr;
 }
 
-__KINLINE struct cmsghdr * cmsg_nxthdr (struct msghdr *__msg, struct cmsghdr *__cmsg)
+static inline struct cmsghdr * cmsg_nxthdr (struct msghdr *__msg, struct cmsghdr *__cmsg)
 {
         return __cmsg_nxthdr(__msg->msg_control, __msg->msg_controllen, __cmsg);
 }
diff --git a/kernel/hrtimer.c b/kernel/hrtimer.c
index 6d7020490f94..3e1c36e7998f 100644
--- a/kernel/hrtimer.c
+++ b/kernel/hrtimer.c
@@ -726,8 +726,6 @@ static int hrtimer_switch_to_hres(void)
         /* "Retrigger" the interrupt to get things going */
         retrigger_next_event(NULL);
         local_irq_restore(flags);
-        printk(KERN_DEBUG "Switched to high resolution mode on CPU %d\n",
-               smp_processor_id());
         return 1;
 }
 
diff --git a/kernel/perf_event.c b/kernel/perf_event.c
index 0f86feb6db0c..e491fb087939 100644
--- a/kernel/perf_event.c
+++ b/kernel/perf_event.c
@@ -1030,14 +1030,10 @@ void __perf_event_sched_out(struct perf_event_context *ctx,
         update_context_time(ctx);
 
         perf_disable();
-        if (ctx->nr_active) {
-                list_for_each_entry(event, &ctx->group_list, group_entry) {
-                        if (event != event->group_leader)
-                                event_sched_out(event, cpuctx, ctx);
-                        else
-                                group_sched_out(event, cpuctx, ctx);
-                }
-        }
+        if (ctx->nr_active)
+                list_for_each_entry(event, &ctx->group_list, group_entry)
+                        group_sched_out(event, cpuctx, ctx);
+
         perf_enable();
  out:
         spin_unlock(&ctx->lock);
@@ -1258,12 +1254,8 @@ __perf_event_sched_in(struct perf_event_context *ctx,
                 if (event->cpu != -1 && event->cpu != cpu)
                         continue;
 
-                if (event != event->group_leader)
-                        event_sched_in(event, cpuctx, ctx, cpu);
-                else {
-                        if (group_can_go_on(event, cpuctx, 1))
-                                group_sched_in(event, cpuctx, ctx, cpu);
-                }
+                if (group_can_go_on(event, cpuctx, 1))
+                        group_sched_in(event, cpuctx, ctx, cpu);
 
                 /*
                  * If this pinned group hasn't been scheduled,
@@ -1291,15 +1283,9 @@ __perf_event_sched_in(struct perf_event_context *ctx,
                 if (event->cpu != -1 && event->cpu != cpu)
                         continue;
 
-                if (event != event->group_leader) {
-                        if (event_sched_in(event, cpuctx, ctx, cpu))
+                if (group_can_go_on(event, cpuctx, can_add_hw))
+                        if (group_sched_in(event, cpuctx, ctx, cpu))
                                 can_add_hw = 0;
-                } else {
-                        if (group_can_go_on(event, cpuctx, can_add_hw)) {
-                                if (group_sched_in(event, cpuctx, ctx, cpu))
-                                        can_add_hw = 0;
-                        }
-                }
         }
         perf_enable();
  out:
@@ -4781,9 +4767,7 @@ int perf_event_init_task(struct task_struct *child)
          * We dont have to disable NMIs - we are only looking at
          * the list, not manipulating it:
          */
-        list_for_each_entry_rcu(event, &parent_ctx->event_list, event_entry) {
-                if (event != event->group_leader)
-                        continue;
+        list_for_each_entry(event, &parent_ctx->group_list, group_entry) {
 
                 if (!event->attr.inherit) {
                         inherited_all = 0;
diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c
index 46592feab5a6..3724756e41ca 100644
--- a/kernel/trace/ftrace.c
+++ b/kernel/trace/ftrace.c
@@ -225,7 +225,11 @@ static void ftrace_update_pid_func(void)
         if (ftrace_trace_function == ftrace_stub)
                 return;
 
+#ifdef CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST
         func = ftrace_trace_function;
+#else
+        func = __ftrace_trace_function;
+#endif
 
         if (ftrace_pid_trace) {
                 set_ftrace_pid_function(func);
diff --git a/kernel/trace/kmemtrace.c b/kernel/trace/kmemtrace.c
index 81b1645c8549..a91da69f153a 100644
--- a/kernel/trace/kmemtrace.c
+++ b/kernel/trace/kmemtrace.c
@@ -501,7 +501,7 @@ static int __init init_kmem_tracer(void)
                 return 1;
         }
 
-        if (!register_tracer(&kmem_tracer)) {
+        if (register_tracer(&kmem_tracer) != 0) {
                 pr_warning("Warning: could not register the kmem tracer\n");
                 return 1;
         }
diff --git a/mm/Kconfig b/mm/Kconfig
index edd300aca173..57963c6063d1 100644
--- a/mm/Kconfig
+++ b/mm/Kconfig
@@ -224,7 +224,9 @@ config KSM
           the many instances by a single resident page with that content, so
           saving memory until one or another app needs to modify the content.
           Recommended for use with KVM, or with other duplicative applications.
-          See Documentation/vm/ksm.txt for more information.
+          See Documentation/vm/ksm.txt for more information: KSM is inactive
+          until a program has madvised that an area is MADV_MERGEABLE, and
+          root has set /sys/kernel/mm/ksm/run to 1 (if CONFIG_SYSFS is set).
 
 config DEFAULT_MMAP_MIN_ADDR
         int "Low address space to protect from user allocation"
diff --git a/mm/ksm.c b/mm/ksm.c
index f7edac356f46..bef1af4f77e3 100644
--- a/mm/ksm.c
+++ b/mm/ksm.c
@@ -184,11 +184,6 @@ static DEFINE_SPINLOCK(ksm_mmlist_lock);
                 sizeof(struct __struct), __alignof__(struct __struct),\
                 (__flags), NULL)
 
-static void __init ksm_init_max_kernel_pages(void)
-{
-        ksm_max_kernel_pages = nr_free_buffer_pages() / 4;
-}
-
 static int __init ksm_slab_init(void)
 {
         rmap_item_cache = KSM_KMEM_CACHE(rmap_item, 0);
@@ -1673,7 +1668,7 @@ static int __init ksm_init(void)
         struct task_struct *ksm_thread;
         int err;
 
-        ksm_init_max_kernel_pages();
+        ksm_max_kernel_pages = totalram_pages / 4;
 
         err = ksm_slab_init();
         if (err)
@@ -1697,6 +1692,9 @@ static int __init ksm_init(void)
                 kthread_stop(ksm_thread);
                 goto out_free2;
         }
+#else
+        ksm_run = KSM_RUN_MERGE;        /* no way for user to start it */
+
 #endif /* CONFIG_SYSFS */
 
         return 0;
diff --git a/mm/vmalloc.c b/mm/vmalloc.c
index 69511e663234..2f7c9d75c552 100644
--- a/mm/vmalloc.c
+++ b/mm/vmalloc.c
@@ -25,7 +25,6 @@
 #include <linux/rcupdate.h>
 #include <linux/pfn.h>
 #include <linux/kmemleak.h>
-#include <linux/highmem.h>
 #include <asm/atomic.h>
 #include <asm/uaccess.h>
 #include <asm/tlbflush.h>
diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c
index 821d30918cfc..427ded841224 100644
--- a/net/core/net-sysfs.c
+++ b/net/core/net-sysfs.c
@@ -366,13 +366,13 @@ static ssize_t wireless_show(struct device *d, char *buf,
         const struct iw_statistics *iw;
         ssize_t ret = -EINVAL;
 
-        read_lock(&dev_base_lock);
+        rtnl_lock();
         if (dev_isalive(dev)) {
                 iw = get_wireless_stats(dev);
                 if (iw)
                         ret = (*format)(iw, buf);
         }
-        read_unlock(&dev_base_lock);
+        rtnl_unlock();
 
         return ret;
 }
diff --git a/net/core/pktgen.c b/net/core/pktgen.c
index b69455217ed6..86acdba0a97d 100644
--- a/net/core/pktgen.c
+++ b/net/core/pktgen.c
@@ -964,7 +964,7 @@ static ssize_t pktgen_if_write(struct file *file,
                 if (value == 0x7FFFFFFF)
                         pkt_dev->delay = ULLONG_MAX;
                 else
-                        pkt_dev->delay = (u64)value * NSEC_PER_USEC;
+                        pkt_dev->delay = (u64)value;
 
                 sprintf(pg_result, "OK: delay=%llu",
                         (unsigned long long) pkt_dev->delay);
@@ -2212,7 +2212,7 @@ static void set_cur_queue_map(struct pktgen_dev *pkt_dev)
         if (pkt_dev->flags & F_QUEUE_MAP_CPU)
                 pkt_dev->cur_queue_map = smp_processor_id();
 
-        else if (pkt_dev->queue_map_min < pkt_dev->queue_map_max) {
+        else if (pkt_dev->queue_map_min <= pkt_dev->queue_map_max) {
                 __u16 t;
                 if (pkt_dev->flags & F_QUEUE_MAP_RND) {
                         t = random32() %
diff --git a/net/ipv4/devinet.c b/net/ipv4/devinet.c
index e92f1fd28aa5..5df2f6a0b0f0 100644
--- a/net/ipv4/devinet.c
+++ b/net/ipv4/devinet.c
@@ -1077,12 +1077,16 @@ static int inetdev_event(struct notifier_block *this, unsigned long event,
                 ip_mc_up(in_dev);
                 /* fall through */
         case NETDEV_CHANGEADDR:
-                if (IN_DEV_ARP_NOTIFY(in_dev))
-                        arp_send(ARPOP_REQUEST, ETH_P_ARP,
-                                 in_dev->ifa_list->ifa_address,
-                                 dev,
-                                 in_dev->ifa_list->ifa_address,
-                                 NULL, dev->dev_addr, NULL);
+                /* Send gratuitous ARP to notify of link change */
+                if (IN_DEV_ARP_NOTIFY(in_dev)) {
+                        struct in_ifaddr *ifa = in_dev->ifa_list;
+
+                        if (ifa)
+                                arp_send(ARPOP_REQUEST, ETH_P_ARP,
+                                         ifa->ifa_address, dev,
+                                         ifa->ifa_address, NULL,
+                                         dev->dev_addr, NULL);
+                }
                 break;
         case NETDEV_DOWN:
                 ip_mc_down(in_dev);
diff --git a/tools/perf/Documentation/perf-timechart.txt b/tools/perf/Documentation/perf-timechart.txt
index 1c2ed3090cce..a7910099d6fd 100644
--- a/tools/perf/Documentation/perf-timechart.txt
+++ b/tools/perf/Documentation/perf-timechart.txt
@@ -31,6 +31,9 @@ OPTIONS
 -w::
 --width=::
         Select the width of the SVG file (default: 1000)
+-p::
+--power-only::
+        Only output the CPU power section of the diagram
 
 
 SEE ALSO
diff --git a/tools/perf/Makefile b/tools/perf/Makefile
index b5f1953b6144..5881943f0c34 100644
--- a/tools/perf/Makefile
+++ b/tools/perf/Makefile
@@ -728,7 +728,7 @@ $(BUILT_INS): perf$X
 common-cmds.h: util/generate-cmdlist.sh command-list.txt
 
 common-cmds.h: $(wildcard Documentation/perf-*.txt)
-        $(QUIET_GEN)util/generate-cmdlist.sh > $@+ && mv $@+ $@
+        $(QUIET_GEN). util/generate-cmdlist.sh > $@+ && mv $@+ $@
 
 $(patsubst %.sh,%,$(SCRIPT_SH)) : % : %.sh
         $(QUIET_GEN)$(RM) $@ $@+ && \
diff --git a/tools/perf/builtin-timechart.c b/tools/perf/builtin-timechart.c
index 4405681b3134..702d8fe58fbc 100644
--- a/tools/perf/builtin-timechart.c
+++ b/tools/perf/builtin-timechart.c
@@ -46,6 +46,8 @@ static u64		turbo_frequency;
 
 static u64              first_time, last_time;
 
+static int              power_only;
+
 
 static struct perf_header       *header;
 
@@ -547,7 +549,7 @@ static void end_sample_processing(void)
         u64 cpu;
         struct power_event *pwr;
 
-        for (cpu = 0; cpu < numcpus; cpu++) {
+        for (cpu = 0; cpu <= numcpus; cpu++) {
                 pwr = malloc(sizeof(struct power_event));
                 if (!pwr)
                         return;
@@ -871,7 +873,7 @@ static int determine_display_tasks(u64 threshold)
                 /* no exit marker, task kept running to the end */
                 if (p->end_time == 0)
                         p->end_time = last_time;
-                if (p->total_time >= threshold)
+                if (p->total_time >= threshold && !power_only)
                         p->display = 1;
 
                 c = p->all;
@@ -882,7 +884,7 @@ static int determine_display_tasks(u64 threshold)
                         if (c->start_time == 1)
                                 c->start_time = first_time;
 
-                        if (c->total_time >= threshold) {
+                        if (c->total_time >= threshold && !power_only) {
                                 c->display = 1;
                                 count++;
                         }
@@ -1134,6 +1136,8 @@ static const struct option options[] = {
                     "output file name"),
         OPT_INTEGER('w', "width", &svg_page_width,
                     "page width"),
+        OPT_BOOLEAN('p', "power-only", &power_only,
+                    "output power data only"),
         OPT_END()
 };
 
diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c
index 1ca88896eee4..37512e936235 100644
--- a/tools/perf/builtin-top.c
+++ b/tools/perf/builtin-top.c
@@ -782,6 +782,7 @@ static const char *skip_symbols[] = {
         "exit_idle",
         "mwait_idle",
         "mwait_idle_with_hints",
+        "poll_idle",
         "ppc64_runlatch_off",
         "pseries_dedicated_idle_sleep",
         NULL
diff --git a/tools/perf/util/svghelper.c b/tools/perf/util/svghelper.c
index a778fd0f4ae4..856655d8b0b8 100644
--- a/tools/perf/util/svghelper.c
+++ b/tools/perf/util/svghelper.c
@@ -28,7 +28,7 @@ static u64 turbo_frequency, max_freq;
 
 int svg_page_width = 1000;
 
-#define MIN_TEXT_SIZE 0.001
+#define MIN_TEXT_SIZE 0.01
 
 static u64 total_height;
 static FILE *svgfile;
@@ -217,6 +217,18 @@ static char *cpu_model(void)
                 }
                 fclose(file);
         }
+
+        /* CPU type */
+        file = fopen("/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", "r");
+        if (file) {
+                while (fgets(buf, 255, file)) {
+                        unsigned int freq;
+                        freq = strtoull(buf, NULL, 10);
+                        if (freq > max_freq)
+                                max_freq = freq;
+                }
+                fclose(file);
+        }
         return cpu_m;
 }
 
diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
index e79c54034bcd..b7c78a403dc2 100644
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
@@ -850,6 +850,19 @@ static void kvm_mmu_notifier_invalidate_page(struct mmu_notifier *mn,
 
 }
 
+static void kvm_mmu_notifier_change_pte(struct mmu_notifier *mn,
+                                        struct mm_struct *mm,
+                                        unsigned long address,
+                                        pte_t pte)
+{
+        struct kvm *kvm = mmu_notifier_to_kvm(mn);
+
+        spin_lock(&kvm->mmu_lock);
+        kvm->mmu_notifier_seq++;
+        kvm_set_spte_hva(kvm, address, pte);
+        spin_unlock(&kvm->mmu_lock);
+}
+
 static void kvm_mmu_notifier_invalidate_range_start(struct mmu_notifier *mn,
                                                     struct mm_struct *mm,
                                                     unsigned long start,
@@ -929,6 +942,7 @@ static const struct mmu_notifier_ops kvm_mmu_notifier_ops = {
         .invalidate_range_start = kvm_mmu_notifier_invalidate_range_start,
         .invalidate_range_end   = kvm_mmu_notifier_invalidate_range_end,
         .clear_flush_young      = kvm_mmu_notifier_clear_flush_young,
+        .change_pte             = kvm_mmu_notifier_change_pte,
         .release                = kvm_mmu_notifier_release,
 };
 #endif /* CONFIG_MMU_NOTIFIER && KVM_ARCH_WANT_MMU_NOTIFIER */