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-rw-r--r--arch/sh/Kconfig10
-rw-r--r--arch/sh/Kconfig.debug3
-rw-r--r--arch/sh/boards/renesas/hs7751rvoip/irq.c1
-rw-r--r--arch/sh/boards/renesas/hs7751rvoip/setup.c19
-rw-r--r--arch/sh/boards/renesas/sh7710voipgw/setup.c1
-rw-r--r--arch/sh/boards/se/7206/irq.c1
-rw-r--r--arch/sh/boards/se/770x/setup.c1
-rw-r--r--arch/sh/boards/se/7722/setup.c8
-rw-r--r--arch/sh/boards/se/7780/setup.c8
-rw-r--r--arch/sh/boards/snapgear/Makefile3
-rw-r--r--arch/sh/boards/snapgear/rtc.c309
-rw-r--r--arch/sh/boards/snapgear/setup.c16
-rw-r--r--arch/sh/boot/Makefile2
-rw-r--r--arch/sh/cchips/hd6446x/Makefile2
-rw-r--r--arch/sh/cchips/voyagergx/Makefile1
-rw-r--r--arch/sh/drivers/pci/Makefile1
-rw-r--r--arch/sh/drivers/pci/pci-st40.c488
-rw-r--r--arch/sh/drivers/pci/pci-st40.h136
-rw-r--r--arch/sh/kernel/Makefile3
-rw-r--r--arch/sh/kernel/cpu/sh3/ex.S2
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c8
-rw-r--r--arch/sh/kernel/irq.c1
-rw-r--r--arch/sh/kernel/kgdb_stub.c9
-rw-r--r--arch/sh/kernel/setup.c1
-rw-r--r--arch/sh/kernel/sh_ksyms.c2
-rw-r--r--arch/sh/lib/Makefile2
-rw-r--r--arch/sh/mm/Kconfig21
-rw-r--r--arch/sh/mm/Makefile2
-rw-r--r--arch/sh/mm/clear_page.S45
-rw-r--r--arch/sh/mm/copy_page.S61
-rw-r--r--arch/sh/mm/pg-sh4.c75
-rw-r--r--arch/sh/oprofile/Makefile1
-rw-r--r--arch/sh64/kernel/process.c10
-rw-r--r--arch/sh64/kernel/traps.c5
-rw-r--r--drivers/rtc/rtc-sh.c6
-rw-r--r--drivers/serial/sh-sci.h19
-rw-r--r--drivers/sh/superhyway/superhyway.c7
-rw-r--r--include/asm-sh/cacheflush.h18
-rw-r--r--include/asm-sh/cpu-sh3/timer.h6
-rw-r--r--include/asm-sh/page.h11
-rw-r--r--include/asm-sh/pgtable.h4
-rw-r--r--include/asm-sh/processor.h2
-rw-r--r--include/asm-sh/ptrace.h3
-rw-r--r--include/asm-sh/vga.h6
-rw-r--r--include/asm-sh64/ptrace.h2
45 files changed, 148 insertions, 1194 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 22a3eb38438b..496d635f89b2 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -211,10 +211,12 @@ config SH_SOLUTION_ENGINE
211 bool "SolutionEngine" 211 bool "SolutionEngine"
212 select SOLUTION_ENGINE 212 select SOLUTION_ENGINE
213 select CPU_HAS_IPR_IRQ 213 select CPU_HAS_IPR_IRQ
214 depends on CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7750 214 depends on CPU_SUBTYPE_SH7705 || CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7710 || \
215 CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \
216 CPU_SUBTYPE_SH7750R
215 help 217 help
216 Select SolutionEngine if configuring for a Hitachi SH7709 218 Select SolutionEngine if configuring for a Hitachi SH7705, SH7709,
217 or SH7750 evaluation board. 219 SH7710, SH7712, SH7750, SH7750S or SH7750R evaluation board.
218 220
219config SH_7206_SOLUTION_ENGINE 221config SH_7206_SOLUTION_ENGINE
220 bool "SolutionEngine7206" 222 bool "SolutionEngine7206"
@@ -603,7 +605,7 @@ config BOOT_LINK_OFFSET
603 605
604config UBC_WAKEUP 606config UBC_WAKEUP
605 bool "Wakeup UBC on startup" 607 bool "Wakeup UBC on startup"
606 depends on CPU_SH4 608 depends on CPU_SH4 && !CPU_SH4A
607 help 609 help
608 Selecting this option will wakeup the User Break Controller (UBC) on 610 Selecting this option will wakeup the User Break Controller (UBC) on
609 startup. Although the UBC is left in an awake state when the processor 611 startup. Although the UBC is left in an awake state when the processor
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index ab2f9f3c354c..722da6851f56 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -124,12 +124,13 @@ config KGDB_NMI
124 124
125config SH_KGDB_CONSOLE 125config SH_KGDB_CONSOLE
126 bool "Console messages through GDB" 126 bool "Console messages through GDB"
127 depends on !SERIAL_SH_SCI_CONSOLE 127 depends on !SERIAL_SH_SCI_CONSOLE && SERIAL_SH_SCI=y
128 select SERIAL_CORE_CONSOLE 128 select SERIAL_CORE_CONSOLE
129 default n 129 default n
130 130
131config KGDB_SYSRQ 131config KGDB_SYSRQ
132 bool "Allow SysRq 'G' to enter KGDB" 132 bool "Allow SysRq 'G' to enter KGDB"
133 depends on MAGIC_SYSRQ
133 default y 134 default y
134 135
135comment "Serial port setup" 136comment "Serial port setup"
diff --git a/arch/sh/boards/renesas/hs7751rvoip/irq.c b/arch/sh/boards/renesas/hs7751rvoip/irq.c
index 943f93aa6052..e55c6686b21f 100644
--- a/arch/sh/boards/renesas/hs7751rvoip/irq.c
+++ b/arch/sh/boards/renesas/hs7751rvoip/irq.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/irq.h> 14#include <linux/irq.h>
15#include <linux/interrupt.h>
15#include <asm/io.h> 16#include <asm/io.h>
16#include <asm/irq.h> 17#include <asm/irq.h>
17#include <asm/hs7751rvoip.h> 18#include <asm/hs7751rvoip.h>
diff --git a/arch/sh/boards/renesas/hs7751rvoip/setup.c b/arch/sh/boards/renesas/hs7751rvoip/setup.c
index fa5fa3920222..c05625975f2c 100644
--- a/arch/sh/boards/renesas/hs7751rvoip/setup.c
+++ b/arch/sh/boards/renesas/hs7751rvoip/setup.c
@@ -15,20 +15,6 @@
15#include <asm/io.h> 15#include <asm/io.h>
16#include <asm/machvec.h> 16#include <asm/machvec.h>
17 17
18static struct ipr_data hs77501rvoip_ipr_map[] = {
19#if defined(CONFIG_HS7751RVOIP_CODEC)
20 { DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
21 { DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
22#endif
23};
24
25static void __init hs7751rvoip_init_irq(void)
26{
27 make_ipr_irq(hs77501rvoip_ipr_map, ARRAY_SIZE(hs77501rvoip_ipr_map));
28
29 init_hs7751rvoip_IRQ();
30}
31
32static void hs7751rvoip_power_off(void) 18static void hs7751rvoip_power_off(void)
33{ 19{
34 ctrl_outw(ctrl_inw(PA_OUTPORTR) & 0xffdf, PA_OUTPORTR); 20 ctrl_outw(ctrl_inw(PA_OUTPORTR) & 0xffdf, PA_OUTPORTR);
@@ -75,14 +61,13 @@ static int __init hs7751rvoip_cf_init(void)
75 61
76 return 0; 62 return 0;
77} 63}
64device_initcall(hs7751rvoip_cf_init);
78 65
79/* 66/*
80 * Initialize the board 67 * Initialize the board
81 */ 68 */
82static void __init hs7751rvoip_setup(char **cmdline_p) 69static void __init hs7751rvoip_setup(char **cmdline_p)
83{ 70{
84 device_initcall(hs7751rvoip_cf_init);
85
86 ctrl_outb(0xf0, PA_OUTPORTR); 71 ctrl_outb(0xf0, PA_OUTPORTR);
87 pm_power_off = hs7751rvoip_power_off; 72 pm_power_off = hs7751rvoip_power_off;
88 73
@@ -115,6 +100,6 @@ static struct sh_machine_vector mv_hs7751rvoip __initmv = {
115 .mv_outsw = hs7751rvoip_outsw, 100 .mv_outsw = hs7751rvoip_outsw,
116 .mv_outsl = hs7751rvoip_outsl, 101 .mv_outsl = hs7751rvoip_outsl,
117 102
118 .mv_init_irq = hs7751rvoip_init_irq, 103 .mv_init_irq = init_hs7751rvoip_IRQ,
119 .mv_ioport_map = hs7751rvoip_ioport_map, 104 .mv_ioport_map = hs7751rvoip_ioport_map,
120}; 105};
diff --git a/arch/sh/boards/renesas/sh7710voipgw/setup.c b/arch/sh/boards/renesas/sh7710voipgw/setup.c
index 2dce8bd97f90..0d56fd83bcba 100644
--- a/arch/sh/boards/renesas/sh7710voipgw/setup.c
+++ b/arch/sh/boards/renesas/sh7710voipgw/setup.c
@@ -11,7 +11,6 @@
11#include <asm/machvec.h> 11#include <asm/machvec.h>
12#include <asm/irq.h> 12#include <asm/irq.h>
13#include <asm/io.h> 13#include <asm/io.h>
14#include <asm/irq.h>
15 14
16static struct ipr_data sh7710voipgw_ipr_map[] = { 15static struct ipr_data sh7710voipgw_ipr_map[] = {
17 { TIMER2_IRQ, TIMER2_IPR_ADDR, TIMER2_IPR_POS, TIMER2_PRIORITY }, 16 { TIMER2_IRQ, TIMER2_IPR_ADDR, TIMER2_IPR_POS, TIMER2_PRIORITY },
diff --git a/arch/sh/boards/se/7206/irq.c b/arch/sh/boards/se/7206/irq.c
index 27da88486f73..9d5bfc77d0de 100644
--- a/arch/sh/boards/se/7206/irq.c
+++ b/arch/sh/boards/se/7206/irq.c
@@ -9,7 +9,6 @@
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/irq.h> 10#include <linux/irq.h>
11#include <linux/io.h> 11#include <linux/io.h>
12#include <linux/irq.h>
13#include <linux/interrupt.h> 12#include <linux/interrupt.h>
14#include <asm/se7206.h> 13#include <asm/se7206.h>
15 14
diff --git a/arch/sh/boards/se/770x/setup.c b/arch/sh/boards/se/770x/setup.c
index d07a3368f546..318bc8a3969c 100644
--- a/arch/sh/boards/se/770x/setup.c
+++ b/arch/sh/boards/se/770x/setup.c
@@ -94,6 +94,7 @@ static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
94static struct heartbeat_data heartbeat_data = { 94static struct heartbeat_data heartbeat_data = {
95 .bit_pos = heartbeat_bit_pos, 95 .bit_pos = heartbeat_bit_pos,
96 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), 96 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
97 .regsize = 16,
97}; 98};
98 99
99static struct resource heartbeat_resources[] = { 100static struct resource heartbeat_resources[] = {
diff --git a/arch/sh/boards/se/7722/setup.c b/arch/sh/boards/se/7722/setup.c
index 20f064083cc2..eb97dca5b736 100644
--- a/arch/sh/boards/se/7722/setup.c
+++ b/arch/sh/boards/se/7722/setup.c
@@ -16,8 +16,13 @@
16#include <asm/machvec.h> 16#include <asm/machvec.h>
17#include <asm/se7722.h> 17#include <asm/se7722.h>
18#include <asm/io.h> 18#include <asm/io.h>
19#include <asm/heartbeat.h>
19 20
20/* Heartbeat */ 21/* Heartbeat */
22static struct heartbeat_data heartbeat_data = {
23 .regsize = 16,
24};
25
21static struct resource heartbeat_resources[] = { 26static struct resource heartbeat_resources[] = {
22 [0] = { 27 [0] = {
23 .start = PA_LED, 28 .start = PA_LED,
@@ -29,6 +34,9 @@ static struct resource heartbeat_resources[] = {
29static struct platform_device heartbeat_device = { 34static struct platform_device heartbeat_device = {
30 .name = "heartbeat", 35 .name = "heartbeat",
31 .id = -1, 36 .id = -1,
37 .dev = {
38 .platform_data = &heartbeat_data,
39 },
32 .num_resources = ARRAY_SIZE(heartbeat_resources), 40 .num_resources = ARRAY_SIZE(heartbeat_resources),
33 .resource = heartbeat_resources, 41 .resource = heartbeat_resources,
34}; 42};
diff --git a/arch/sh/boards/se/7780/setup.c b/arch/sh/boards/se/7780/setup.c
index 76e53b26a808..0f08ab3b2bec 100644
--- a/arch/sh/boards/se/7780/setup.c
+++ b/arch/sh/boards/se/7780/setup.c
@@ -14,8 +14,13 @@
14#include <asm/machvec.h> 14#include <asm/machvec.h>
15#include <asm/se7780.h> 15#include <asm/se7780.h>
16#include <asm/io.h> 16#include <asm/io.h>
17#include <asm/heartbeat.h>
17 18
18/* Heartbeat */ 19/* Heartbeat */
20static struct heartbeat_data heartbeat_data = {
21 .regsize = 16,
22};
23
19static struct resource heartbeat_resources[] = { 24static struct resource heartbeat_resources[] = {
20 [0] = { 25 [0] = {
21 .start = PA_LED, 26 .start = PA_LED,
@@ -27,6 +32,9 @@ static struct resource heartbeat_resources[] = {
27static struct platform_device heartbeat_device = { 32static struct platform_device heartbeat_device = {
28 .name = "heartbeat", 33 .name = "heartbeat",
29 .id = -1, 34 .id = -1,
35 .dev = {
36 .platform_data = &heartbeat_data,
37 },
30 .num_resources = ARRAY_SIZE(heartbeat_resources), 38 .num_resources = ARRAY_SIZE(heartbeat_resources),
31 .resource = heartbeat_resources, 39 .resource = heartbeat_resources,
32}; 40};
diff --git a/arch/sh/boards/snapgear/Makefile b/arch/sh/boards/snapgear/Makefile
index 59fc976bfc2f..d2d2f4b6a502 100644
--- a/arch/sh/boards/snapgear/Makefile
+++ b/arch/sh/boards/snapgear/Makefile
@@ -2,5 +2,4 @@
2# Makefile for the SnapGear specific parts of the kernel 2# Makefile for the SnapGear specific parts of the kernel
3# 3#
4 4
5obj-y := setup.o io.o rtc.o 5obj-y := setup.o io.o
6
diff --git a/arch/sh/boards/snapgear/rtc.c b/arch/sh/boards/snapgear/rtc.c
deleted file mode 100644
index edb3dd936cbb..000000000000
--- a/arch/sh/boards/snapgear/rtc.c
+++ /dev/null
@@ -1,309 +0,0 @@
1/****************************************************************************/
2/*
3 * linux/arch/sh/boards/snapgear/rtc.c -- Secureedge5410 RTC code
4 *
5 * Copyright (C) 2002 David McCullough <davidm@snapgear.com>
6 * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
7 *
8 * The SecureEdge5410 can have one of 2 real time clocks, the SH
9 * built in version or the preferred external DS1302. Here we work out
10 * each to see what we have and then run with it.
11 */
12/****************************************************************************/
13
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/time.h>
18#include <linux/rtc.h>
19#include <linux/mc146818rtc.h>
20#include <asm/io.h>
21
22static int use_ds1302;
23
24/****************************************************************************/
25/*
26 * we need to implement a DS1302 driver here that can operate in
27 * conjunction with the builtin rtc driver which is already quite friendly
28 */
29/*****************************************************************************/
30
31#define RTC_CMD_READ 0x81 /* Read command */
32#define RTC_CMD_WRITE 0x80 /* Write command */
33
34#define RTC_ADDR_YEAR 0x06 /* Address of year register */
35#define RTC_ADDR_DAY 0x05 /* Address of day of week register */
36#define RTC_ADDR_MON 0x04 /* Address of month register */
37#define RTC_ADDR_DATE 0x03 /* Address of day of month register */
38#define RTC_ADDR_HOUR 0x02 /* Address of hour register */
39#define RTC_ADDR_MIN 0x01 /* Address of minute register */
40#define RTC_ADDR_SEC 0x00 /* Address of second register */
41
42#define RTC_RESET 0x1000
43#define RTC_IODATA 0x0800
44#define RTC_SCLK 0x0400
45
46#define set_dirp(x)
47#define get_dirp(x) 0
48#define set_dp(x) SECUREEDGE_WRITE_IOPORT(x, 0x1c00)
49#define get_dp(x) SECUREEDGE_READ_IOPORT()
50
51static void ds1302_sendbits(unsigned int val)
52{
53 int i;
54
55 for (i = 8; (i); i--, val >>= 1) {
56 set_dp((get_dp() & ~RTC_IODATA) | ((val & 0x1) ? RTC_IODATA : 0));
57 set_dp(get_dp() | RTC_SCLK); // clock high
58 set_dp(get_dp() & ~RTC_SCLK); // clock low
59 }
60}
61
62static unsigned int ds1302_recvbits(void)
63{
64 unsigned int val;
65 int i;
66
67 for (i = 0, val = 0; (i < 8); i++) {
68 val |= (((get_dp() & RTC_IODATA) ? 1 : 0) << i);
69 set_dp(get_dp() | RTC_SCLK); // clock high
70 set_dp(get_dp() & ~RTC_SCLK); // clock low
71 }
72 return(val);
73}
74
75static unsigned int ds1302_readbyte(unsigned int addr)
76{
77 unsigned int val;
78 unsigned long flags;
79
80 local_irq_save(flags);
81 set_dirp(get_dirp() | RTC_RESET | RTC_IODATA | RTC_SCLK);
82 set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
83
84 set_dp(get_dp() | RTC_RESET);
85 ds1302_sendbits(((addr & 0x3f) << 1) | RTC_CMD_READ);
86 set_dirp(get_dirp() & ~RTC_IODATA);
87 val = ds1302_recvbits();
88 set_dp(get_dp() & ~RTC_RESET);
89 local_irq_restore(flags);
90
91 return(val);
92}
93
94static void ds1302_writebyte(unsigned int addr, unsigned int val)
95{
96 unsigned long flags;
97
98 local_irq_save(flags);
99 set_dirp(get_dirp() | RTC_RESET | RTC_IODATA | RTC_SCLK);
100 set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
101 set_dp(get_dp() | RTC_RESET);
102 ds1302_sendbits(((addr & 0x3f) << 1) | RTC_CMD_WRITE);
103 ds1302_sendbits(val);
104 set_dp(get_dp() & ~RTC_RESET);
105 local_irq_restore(flags);
106}
107
108static void ds1302_reset(void)
109{
110 unsigned long flags;
111 /* Hardware dependent reset/init */
112 local_irq_save(flags);
113 set_dirp(get_dirp() | RTC_RESET | RTC_IODATA | RTC_SCLK);
114 set_dp(get_dp() & ~(RTC_RESET | RTC_IODATA | RTC_SCLK));
115 local_irq_restore(flags);
116}
117
118/*****************************************************************************/
119
120static inline int bcd2int(int val)
121{
122 return((((val & 0xf0) >> 4) * 10) + (val & 0xf));
123}
124
125static inline int int2bcd(int val)
126{
127 return(((val / 10) << 4) + (val % 10));
128}
129
130/*****************************************************************************/
131/*
132 * Write and Read some RAM in the DS1302, if it works assume it's there
133 * Otherwise use the SH4 internal RTC
134 */
135
136void snapgear_rtc_gettimeofday(struct timespec *);
137int snapgear_rtc_settimeofday(const time_t);
138
139void __init secureedge5410_rtc_init(void)
140{
141 unsigned char *test = "snapgear";
142 int i;
143
144 ds1302_reset();
145
146 use_ds1302 = 1;
147
148 for (i = 0; test[i]; i++)
149 ds1302_writebyte(32 + i, test[i]);
150
151 for (i = 0; test[i]; i++)
152 if (ds1302_readbyte(32 + i) != test[i]) {
153 use_ds1302 = 0;
154 break;
155 }
156
157 if (use_ds1302) {
158 rtc_sh_get_time = snapgear_rtc_gettimeofday;
159 rtc_sh_set_time = snapgear_rtc_settimeofday;
160 }
161
162 printk("SnapGear RTC: using %s rtc.\n", use_ds1302 ? "ds1302" : "internal");
163}
164
165/****************************************************************************/
166/*
167 * our generic interface that chooses the correct code to use
168 */
169
170void snapgear_rtc_gettimeofday(struct timespec *ts)
171{
172 unsigned int sec, min, hr, day, mon, yr;
173
174 if (!use_ds1302)
175 return;
176
177 sec = bcd2int(ds1302_readbyte(RTC_ADDR_SEC));
178 min = bcd2int(ds1302_readbyte(RTC_ADDR_MIN));
179 hr = bcd2int(ds1302_readbyte(RTC_ADDR_HOUR));
180 day = bcd2int(ds1302_readbyte(RTC_ADDR_DATE));
181 mon = bcd2int(ds1302_readbyte(RTC_ADDR_MON));
182 yr = bcd2int(ds1302_readbyte(RTC_ADDR_YEAR));
183
184bad_time:
185 if (yr > 99 || mon < 1 || mon > 12 || day > 31 || day < 1 ||
186 hr > 23 || min > 59 || sec > 59) {
187 printk(KERN_ERR
188 "SnapGear RTC: invalid value, resetting to 1 Jan 2000\n");
189 ds1302_writebyte(RTC_ADDR_MIN, min = 0);
190 ds1302_writebyte(RTC_ADDR_HOUR, hr = 0);
191 ds1302_writebyte(RTC_ADDR_DAY, 7);
192 ds1302_writebyte(RTC_ADDR_DATE, day = 1);
193 ds1302_writebyte(RTC_ADDR_MON, mon = 1);
194 ds1302_writebyte(RTC_ADDR_YEAR, yr = 0);
195 ds1302_writebyte(RTC_ADDR_SEC, sec = 0);
196 }
197
198 ts->tv_sec = mktime(2000 + yr, mon, day, hr, min, sec);
199 if (ts->tv_sec < 0) {
200#if 0
201 printk("BAD TIME %d %d %d %d %d %d\n", yr, mon, day, hr, min, sec);
202#endif
203 yr = 100;
204 goto bad_time;
205 }
206 ts->tv_nsec = 0;
207}
208
209int snapgear_rtc_settimeofday(const time_t secs)
210{
211 int retval = 0;
212 int real_seconds, real_minutes, cmos_minutes;
213 unsigned long nowtime;
214
215 if (!use_ds1302)
216 return 0;
217
218/*
219 * This is called direct from the kernel timer handling code.
220 * It is supposed to synchronize the kernel clock to the RTC.
221 */
222
223 nowtime = secs;
224
225 /* STOP RTC */
226 ds1302_writebyte(RTC_ADDR_SEC, ds1302_readbyte(RTC_ADDR_SEC) | 0x80);
227
228 cmos_minutes = bcd2int(ds1302_readbyte(RTC_ADDR_MIN));
229
230 /*
231 * since we're only adjusting minutes and seconds,
232 * don't interfere with hour overflow. This avoids
233 * messing with unknown time zones but requires your
234 * RTC not to be off by more than 15 minutes
235 */
236 real_seconds = nowtime % 60;
237 real_minutes = nowtime / 60;
238 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
239 real_minutes += 30; /* correct for half hour time zone */
240 real_minutes %= 60;
241
242 if (abs(real_minutes - cmos_minutes) < 30) {
243 ds1302_writebyte(RTC_ADDR_MIN, int2bcd(real_minutes));
244 ds1302_writebyte(RTC_ADDR_SEC, int2bcd(real_seconds));
245 } else {
246 printk(KERN_WARNING
247 "SnapGear RTC: can't update from %d to %d\n",
248 cmos_minutes, real_minutes);
249 retval = -1;
250 }
251
252 /* START RTC */
253 ds1302_writebyte(RTC_ADDR_SEC, ds1302_readbyte(RTC_ADDR_SEC) & ~0x80);
254 return(0);
255}
256
257unsigned char secureedge5410_cmos_read(int addr)
258{
259 unsigned char val = 0;
260
261 if (!use_ds1302)
262 return(__CMOS_READ(addr, w));
263
264 switch(addr) {
265 case RTC_SECONDS: val = ds1302_readbyte(RTC_ADDR_SEC); break;
266 case RTC_SECONDS_ALARM: break;
267 case RTC_MINUTES: val = ds1302_readbyte(RTC_ADDR_MIN); break;
268 case RTC_MINUTES_ALARM: break;
269 case RTC_HOURS: val = ds1302_readbyte(RTC_ADDR_HOUR); break;
270 case RTC_HOURS_ALARM: break;
271 case RTC_DAY_OF_WEEK: val = ds1302_readbyte(RTC_ADDR_DAY); break;
272 case RTC_DAY_OF_MONTH: val = ds1302_readbyte(RTC_ADDR_DATE); break;
273 case RTC_MONTH: val = ds1302_readbyte(RTC_ADDR_MON); break;
274 case RTC_YEAR: val = ds1302_readbyte(RTC_ADDR_YEAR); break;
275 case RTC_REG_A: /* RTC_FREQ_SELECT */ break;
276 case RTC_REG_B: /* RTC_CONTROL */ break;
277 case RTC_REG_C: /* RTC_INTR_FLAGS */ break;
278 case RTC_REG_D: val = RTC_VRT /* RTC_VALID */; break;
279 default: break;
280 }
281
282 return(val);
283}
284
285void secureedge5410_cmos_write(unsigned char val, int addr)
286{
287 if (!use_ds1302) {
288 __CMOS_WRITE(val, addr, w);
289 return;
290 }
291
292 switch(addr) {
293 case RTC_SECONDS: ds1302_writebyte(RTC_ADDR_SEC, val); break;
294 case RTC_SECONDS_ALARM: break;
295 case RTC_MINUTES: ds1302_writebyte(RTC_ADDR_MIN, val); break;
296 case RTC_MINUTES_ALARM: break;
297 case RTC_HOURS: ds1302_writebyte(RTC_ADDR_HOUR, val); break;
298 case RTC_HOURS_ALARM: break;
299 case RTC_DAY_OF_WEEK: ds1302_writebyte(RTC_ADDR_DAY, val); break;
300 case RTC_DAY_OF_MONTH: ds1302_writebyte(RTC_ADDR_DATE, val); break;
301 case RTC_MONTH: ds1302_writebyte(RTC_ADDR_MON, val); break;
302 case RTC_YEAR: ds1302_writebyte(RTC_ADDR_YEAR, val); break;
303 case RTC_REG_A: /* RTC_FREQ_SELECT */ break;
304 case RTC_REG_B: /* RTC_CONTROL */ break;
305 case RTC_REG_C: /* RTC_INTR_FLAGS */ break;
306 case RTC_REG_D: /* RTC_VALID */ break;
307 default: break;
308 }
309}
diff --git a/arch/sh/boards/snapgear/setup.c b/arch/sh/boards/snapgear/setup.c
index 2b594f600002..7022483f98e8 100644
--- a/arch/sh/boards/snapgear/setup.c
+++ b/arch/sh/boards/snapgear/setup.c
@@ -22,20 +22,15 @@
22#include <asm/snapgear.h> 22#include <asm/snapgear.h>
23#include <asm/irq.h> 23#include <asm/irq.h>
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/rtc.h>
26#include <asm/cpu/timer.h> 25#include <asm/cpu/timer.h>
27 26
28extern void secureedge5410_rtc_init(void);
29extern void pcibios_init(void);
30
31/****************************************************************************/
32/* 27/*
33 * EraseConfig handling functions 28 * EraseConfig handling functions
34 */ 29 */
35 30
36static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id) 31static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
37{ 32{
38 volatile char dummy __attribute__((unused)) = * (volatile char *) 0xb8000000; 33 (void)ctrl_inb(0xb8000000); /* dummy read */
39 34
40 printk("SnapGear: erase switch interrupt!\n"); 35 printk("SnapGear: erase switch interrupt!\n");
41 36
@@ -76,19 +71,10 @@ static void __init init_snapgear_IRQ(void)
76} 71}
77 72
78/* 73/*
79 * Initialize the board
80 */
81static void __init snapgear_setup(char **cmdline_p)
82{
83 board_time_init = secureedge5410_rtc_init;
84}
85
86/*
87 * The Machine Vector 74 * The Machine Vector
88 */ 75 */
89static struct sh_machine_vector mv_snapgear __initmv = { 76static struct sh_machine_vector mv_snapgear __initmv = {
90 .mv_name = "SnapGear SecureEdge5410", 77 .mv_name = "SnapGear SecureEdge5410",
91 .mv_setup = snapgear_setup,
92 .mv_nr_irqs = 72, 78 .mv_nr_irqs = 72,
93 79
94 .mv_inb = snapgear_inb, 80 .mv_inb = snapgear_inb,
diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile
index 4c5ffdcd55b6..1b0f5be01d10 100644
--- a/arch/sh/boot/Makefile
+++ b/arch/sh/boot/Makefile
@@ -39,7 +39,7 @@ KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%8x" \
39 39
40quiet_cmd_uimage = UIMAGE $@ 40quiet_cmd_uimage = UIMAGE $@
41 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sh -O linux -T kernel \ 41 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A sh -O linux -T kernel \
42 -C gzip -a $(KERNEL_LOAD) -e $(KERNEL_LOAD) \ 42 -C none -a $(KERNEL_LOAD) -e $(KERNEL_LOAD) \
43 -n 'Linux-$(KERNELRELEASE)' -d $< $@ 43 -n 'Linux-$(KERNELRELEASE)' -d $< $@
44 44
45$(obj)/uImage: $(obj)/zImage FORCE 45$(obj)/uImage: $(obj)/zImage FORCE
diff --git a/arch/sh/cchips/hd6446x/Makefile b/arch/sh/cchips/hd6446x/Makefile
index a106dd9db986..f7de4076e242 100644
--- a/arch/sh/cchips/hd6446x/Makefile
+++ b/arch/sh/cchips/hd6446x/Makefile
@@ -1,2 +1,4 @@
1obj-$(CONFIG_HD64461) += hd64461.o 1obj-$(CONFIG_HD64461) += hd64461.o
2obj-$(CONFIG_HD64465) += hd64465/ 2obj-$(CONFIG_HD64465) += hd64465/
3
4EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/cchips/voyagergx/Makefile b/arch/sh/cchips/voyagergx/Makefile
index 085de72fd327..f73963cb3744 100644
--- a/arch/sh/cchips/voyagergx/Makefile
+++ b/arch/sh/cchips/voyagergx/Makefile
@@ -6,3 +6,4 @@ obj-y := irq.o setup.o
6 6
7obj-$(CONFIG_USB_OHCI_HCD) += consistent.o 7obj-$(CONFIG_USB_OHCI_HCD) += consistent.o
8 8
9EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index 2f65ac72f48a..fba6b5ba0b3a 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -5,7 +5,6 @@
5obj-y += pci.o 5obj-y += pci.o
6obj-$(CONFIG_PCI_AUTO) += pci-auto.o 6obj-$(CONFIG_PCI_AUTO) += pci-auto.o
7 7
8obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
diff --git a/arch/sh/drivers/pci/pci-st40.c b/arch/sh/drivers/pci/pci-st40.c
deleted file mode 100644
index 0814a5afe9b7..000000000000
--- a/arch/sh/drivers/pci/pci-st40.c
+++ /dev/null
@@ -1,488 +0,0 @@
1/*
2 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
3 *
4 * May be copied or modified under the terms of the GNU General Public
5 * License. See linux/COPYING for more information.
6 *
7 * Support functions for the ST40 PCI hardware.
8 */
9
10#include <linux/kernel.h>
11#include <linux/smp.h>
12#include <linux/init.h>
13#include <linux/errno.h>
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include <linux/types.h>
17#include <asm/pci.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h> /* irqreturn_t */
20
21#include "pci-st40.h"
22
23/* This is in P2 of course */
24#define ST40PCI_BASE_ADDRESS (0xb0000000)
25#define ST40PCI_MEM_ADDRESS (ST40PCI_BASE_ADDRESS+0x0)
26#define ST40PCI_IO_ADDRESS (ST40PCI_BASE_ADDRESS+0x06000000)
27#define ST40PCI_REG_ADDRESS (ST40PCI_BASE_ADDRESS+0x07000000)
28
29#define ST40PCI_REG(x) (ST40PCI_REG_ADDRESS+(ST40PCI_##x))
30#define ST40PCI_REG_INDEXED(reg, index) \
31 (ST40PCI_REG(reg##0) + \
32 ((ST40PCI_REG(reg##1) - ST40PCI_REG(reg##0))*index))
33
34#define ST40PCI_WRITE(reg,val) writel((val),ST40PCI_REG(reg))
35#define ST40PCI_WRITE_SHORT(reg,val) writew((val),ST40PCI_REG(reg))
36#define ST40PCI_WRITE_BYTE(reg,val) writeb((val),ST40PCI_REG(reg))
37#define ST40PCI_WRITE_INDEXED(reg, index, val) \
38 writel((val), ST40PCI_REG_INDEXED(reg, index));
39
40#define ST40PCI_READ(reg) readl(ST40PCI_REG(reg))
41#define ST40PCI_READ_SHORT(reg) readw(ST40PCI_REG(reg))
42#define ST40PCI_READ_BYTE(reg) readb(ST40PCI_REG(reg))
43
44#define ST40PCI_SERR_IRQ 64
45#define ST40PCI_ERR_IRQ 65
46
47
48/* Macros to extract PLL params */
49#define PLL_MDIV(reg) ( ((unsigned)reg) & 0xff )
50#define PLL_NDIV(reg) ( (((unsigned)reg)>>8) & 0xff )
51#define PLL_PDIV(reg) ( (((unsigned)reg)>>16) & 0x3 )
52#define PLL_SETUP(reg) ( (((unsigned)reg)>>19) & 0x1ff )
53
54/* Build up the appropriate settings */
55#define PLL_SET(mdiv,ndiv,pdiv,setup) \
56( ((mdiv)&0xff) | (((ndiv)&0xff)<<8) | (((pdiv)&3)<<16)| (((setup)&0x1ff)<<19))
57
58#define PLLPCICR (0xbb040000+0x10)
59
60#define PLLPCICR_POWERON (1<<28)
61#define PLLPCICR_OUT_EN (1<<29)
62#define PLLPCICR_LOCKSELECT (1<<30)
63#define PLLPCICR_LOCK (1<<31)
64
65
66#define PLL_25MHZ 0x793c8512
67#define PLL_33MHZ PLL_SET(18,88,3,295)
68
69static void pci_set_rbar_region(unsigned int region, unsigned long localAddr,
70 unsigned long pciOffset, unsigned long regionSize);
71
72static __init void SetPCIPLL(void)
73{
74 {
75 /* Lets play with the PLL values */
76 unsigned long pll1cr1;
77 unsigned long mdiv, ndiv, pdiv;
78 unsigned long muxcr;
79 unsigned int muxcr_ratios[4] = { 8, 16, 21, 1 };
80 unsigned int freq;
81
82#define CLKGENA 0xbb040000
83#define CLKGENA_PLL2_MUXCR CLKGENA + 0x48
84 pll1cr1 = ctrl_inl(PLLPCICR);
85 printk("PLL1CR1 %08lx\n", pll1cr1);
86 mdiv = PLL_MDIV(pll1cr1);
87 ndiv = PLL_NDIV(pll1cr1);
88 pdiv = PLL_PDIV(pll1cr1);
89 printk("mdiv %02lx ndiv %02lx pdiv %02lx\n", mdiv, ndiv, pdiv);
90 freq = ((2*27*ndiv)/mdiv) / (1 << pdiv);
91 printk("PLL freq %dMHz\n", freq);
92 muxcr = ctrl_inl(CLKGENA_PLL2_MUXCR);
93 printk("PCI freq %dMhz\n", freq / muxcr_ratios[muxcr & 3]);
94 }
95}
96
97
98struct pci_err {
99 unsigned mask;
100 const char *error_string;
101};
102
103static struct pci_err int_error[]={
104 { INT_MNLTDIM,"MNLTDIM: Master non-lock transfer"},
105 { INT_TTADI, "TTADI: Illegal byte enable in I/O transfer"},
106 { INT_TMTO, "TMTO: Target memory read/write timeout"},
107 { INT_MDEI, "MDEI: Master function disable error"},
108 { INT_APEDI, "APEDI: Address parity error"},
109 { INT_SDI, "SDI: SERR detected"},
110 { INT_DPEITW, "DPEITW: Data parity error target write"},
111 { INT_PEDITR, "PEDITR: PERR detected"},
112 { INT_TADIM, "TADIM: Target abort detected"},
113 { INT_MADIM, "MADIM: Master abort detected"},
114 { INT_MWPDI, "MWPDI: PERR from target at data write"},
115 { INT_MRDPEI, "MRDPEI: Master read data parity error"}
116};
117#define NUM_PCI_INT_ERRS ARRAY_SIZE(int_error)
118
119static struct pci_err aint_error[]={
120 { AINT_MBI, "MBI: Master broken"},
121 { AINT_TBTOI, "TBTOI: Target bus timeout"},
122 { AINT_MBTOI, "MBTOI: Master bus timeout"},
123 { AINT_TAI, "TAI: Target abort"},
124 { AINT_MAI, "MAI: Master abort"},
125 { AINT_RDPEI, "RDPEI: Read data parity"},
126 { AINT_WDPE, "WDPE: Write data parity"}
127};
128
129#define NUM_PCI_AINT_ERRS ARRAY_SIZE(aint_error)
130
131static void print_pci_errors(unsigned reg,struct pci_err *error,int num_errors)
132{
133 int i;
134
135 for(i=0;i<num_errors;i++) {
136 if(reg & error[i].mask) {
137 printk("%s\n",error[i].error_string);
138 }
139 }
140
141}
142
143
144static char * pci_commands[16]={
145 "Int Ack",
146 "Special Cycle",
147 "I/O Read",
148 "I/O Write",
149 "Reserved",
150 "Reserved",
151 "Memory Read",
152 "Memory Write",
153 "Reserved",
154 "Reserved",
155 "Configuration Read",
156 "Configuration Write",
157 "Memory Read Multiple",
158 "Dual Address Cycle",
159 "Memory Read Line",
160 "Memory Write-and-Invalidate"
161};
162
163static irqreturn_t st40_pci_irq(int irq, void *dev_instance)
164{
165 unsigned pci_int, pci_air, pci_cir, pci_aint;
166 static int count=0;
167
168
169 pci_int = ST40PCI_READ(INT);pci_aint = ST40PCI_READ(AINT);
170 pci_cir = ST40PCI_READ(CIR);pci_air = ST40PCI_READ(AIR);
171
172 /* Reset state to stop multiple interrupts */
173 ST40PCI_WRITE(INT, ~0); ST40PCI_WRITE(AINT, ~0);
174
175
176 if(++count>1) return IRQ_HANDLED;
177
178 printk("** PCI ERROR **\n");
179
180 if(pci_int) {
181 printk("** INT register status\n");
182 print_pci_errors(pci_int,int_error,NUM_PCI_INT_ERRS);
183 }
184
185 if(pci_aint) {
186 printk("** AINT register status\n");
187 print_pci_errors(pci_aint,aint_error,NUM_PCI_AINT_ERRS);
188 }
189
190 printk("** Address and command info\n");
191
192 printk("** Command %s : Address 0x%x\n",
193 pci_commands[pci_cir&0xf],pci_air);
194
195 if(pci_cir&CIR_PIOTEM) {
196 printk("CIR_PIOTEM:PIO transfer error for master\n");
197 }
198 if(pci_cir&CIR_RWTET) {
199 printk("CIR_RWTET:Read/Write transfer error for target\n");
200 }
201
202 return IRQ_HANDLED;
203}
204
205
206/* Rounds a number UP to the nearest power of two. Used for
207 * sizing the PCI window.
208 */
209static u32 r2p2(u32 num)
210{
211 int i = 31;
212 u32 tmp = num;
213
214 if (num == 0)
215 return 0;
216
217 do {
218 if (tmp & (1 << 31))
219 break;
220 i--;
221 tmp <<= 1;
222 } while (i >= 0);
223
224 tmp = 1 << i;
225 /* If the original number isn't a power of 2, round it up */
226 if (tmp != num)
227 tmp <<= 1;
228
229 return tmp;
230}
231
232static void __init pci_fixup_ide_bases(struct pci_dev *d)
233{
234 int i;
235
236 /*
237 * PCI IDE controllers use non-standard I/O port decoding, respect it.
238 */
239 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
240 return;
241 printk("PCI: IDE base address fixup for %s\n", pci_name(d));
242 for(i=0; i<4; i++) {
243 struct resource *r = &d->resource[i];
244 if ((r->start & ~0x80) == 0x374) {
245 r->start |= 2;
246 r->end = r->start;
247 }
248 }
249}
250DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
251
252int __init st40pci_init(unsigned memStart, unsigned memSize)
253{
254 u32 lsr0;
255
256 SetPCIPLL();
257
258 /* Initialises the ST40 pci subsystem, performing a reset, then programming
259 * up the address space decoders appropriately
260 */
261
262 /* Should reset core here as well methink */
263
264 ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_SOFT_RESET);
265
266 /* Loop while core resets */
267 while (ST40PCI_READ(CR) & CR_SOFT_RESET);
268
269 /* Switch off interrupts */
270 ST40PCI_WRITE(INTM, 0);
271 ST40PCI_WRITE(AINT, 0);
272
273 /* Now, lets reset all the cards on the bus with extreme prejudice */
274 ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_RSTCTL);
275 udelay(250);
276
277 /* Set bus active, take it out of reset */
278 ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_BMAM | CR_CFINT | CR_PFCS | CR_PFE);
279
280 /* The PCI spec says that no access must be made to the bus until 1 second
281 * after reset. This seem ludicrously long, but some delay is needed here
282 */
283 mdelay(1000);
284
285 /* Switch off interrupts */
286 ST40PCI_WRITE(INTM, 0);
287 ST40PCI_WRITE(AINT, 0);
288
289 /* Allow it to be a master */
290
291 ST40PCI_WRITE_SHORT(CSR_CMD,
292 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
293 PCI_COMMAND_IO);
294
295 /* Access to the 0xb0000000 -> 0xb6000000 area will go through to 0x10000000 -> 0x16000000
296 * on the PCI bus. This allows a nice 1-1 bus to phys mapping.
297 */
298
299
300 ST40PCI_WRITE(MBR, 0x10000000);
301 /* Always set the max size 128M (actually, it is only 96MB wide) */
302 ST40PCI_WRITE(MBMR, 0x07ff0000);
303
304 /* I/O addresses are mapped at 0xb6000000 -> 0xb7000000. These are changed to 0, to
305 * allow cards that have legacy io such as vga to function correctly. This gives a
306 * maximum of 64K of io/space as only the bottom 16 bits of the address are copied
307 * over to the bus when the transaction is made. 64K of io space is more than enough
308 */
309 ST40PCI_WRITE(IOBR, 0x0);
310 /* Set up the 64K window */
311 ST40PCI_WRITE(IOBMR, 0x0);
312
313 /* Now we set up the mbars so the PCI bus can see the local memory */
314 /* Expose a 256M window starting at PCI address 0... */
315 ST40PCI_WRITE(CSR_MBAR0, 0);
316 ST40PCI_WRITE(LSR0, 0x0fff0001);
317
318 /* ... and set up the initial incoming window to expose all of RAM */
319 pci_set_rbar_region(7, memStart, memStart, memSize);
320
321 /* Maximise timeout values */
322 ST40PCI_WRITE_BYTE(CSR_TRDY, 0xff);
323 ST40PCI_WRITE_BYTE(CSR_RETRY, 0xff);
324 ST40PCI_WRITE_BYTE(CSR_MIT, 0xff);
325
326 ST40PCI_WRITE_BYTE(PERF,PERF_MASTER_WRITE_POSTING);
327
328 return 1;
329}
330
331char * __devinit pcibios_setup(char *str)
332{
333 return str;
334}
335
336
337#define SET_CONFIG_BITS(bus,devfn,where)\
338 (((bus) << 16) | ((devfn) << 8) | ((where) & ~3) | (bus!=0))
339
340#define CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where)
341
342
343static int CheckForMasterAbort(void)
344{
345 if (ST40PCI_READ(INT) & INT_MADIM) {
346 /* Should we clear config space version as well ??? */
347 ST40PCI_WRITE(INT, INT_MADIM);
348 ST40PCI_WRITE_SHORT(CSR_STATUS, 0);
349 return 1;
350 }
351
352 return 0;
353}
354
355/* Write to config register */
356static int st40pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
357{
358 ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
359 switch (size) {
360 case 1:
361 *val = (u8)ST40PCI_READ_BYTE(PDR + (where & 3));
362 break;
363 case 2:
364 *val = (u16)ST40PCI_READ_SHORT(PDR + (where & 2));
365 break;
366 case 4:
367 *val = ST40PCI_READ(PDR);
368 break;
369 }
370
371 if (CheckForMasterAbort()){
372 switch (size) {
373 case 1:
374 *val = (u8)0xff;
375 break;
376 case 2:
377 *val = (u16)0xffff;
378 break;
379 case 4:
380 *val = 0xffffffff;
381 break;
382 }
383 }
384
385 return PCIBIOS_SUCCESSFUL;
386}
387
388static int st40pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
389{
390 ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
391
392 switch (size) {
393 case 1:
394 ST40PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
395 break;
396 case 2:
397 ST40PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
398 break;
399 case 4:
400 ST40PCI_WRITE(PDR, val);
401 break;
402 }
403
404 CheckForMasterAbort();
405
406 return PCIBIOS_SUCCESSFUL;
407}
408
409struct pci_ops st40pci_config_ops = {
410 .read = st40pci_read,
411 .write = st40pci_write,
412};
413
414
415/* Everything hangs off this */
416static struct pci_bus *pci_root_bus;
417
418static int __init pcibios_init(void)
419{
420 extern unsigned long memory_start, memory_end;
421
422 printk(KERN_ALERT "pci-st40.c: pcibios_init\n");
423
424 if (sh_mv.mv_init_pci != NULL) {
425 sh_mv.mv_init_pci();
426 }
427
428 /* The pci subsytem needs to know where memory is and how much
429 * of it there is. I've simply made these globals. A better mechanism
430 * is probably needed.
431 */
432 st40pci_init(PHYSADDR(memory_start),
433 PHYSADDR(memory_end) - PHYSADDR(memory_start));
434
435 if (request_irq(ST40PCI_ERR_IRQ, st40_pci_irq,
436 IRQF_DISABLED, "st40pci", NULL)) {
437 printk(KERN_ERR "st40pci: Cannot hook interrupt\n");
438 return -EIO;
439 }
440
441 /* Enable the PCI interrupts on the device */
442 ST40PCI_WRITE(INTM, ~0);
443 ST40PCI_WRITE(AINT, ~0);
444
445 /* Map the io address apprioately */
446#ifdef CONFIG_HD64465
447 hd64465_port_map(PCIBIOS_MIN_IO, (64 * 1024) - PCIBIOS_MIN_IO + 1,
448 ST40_IO_ADDR + PCIBIOS_MIN_IO, 0);
449#endif
450
451 /* ok, do the scan man */
452 pci_root_bus = pci_scan_bus(0, &st40pci_config_ops, NULL);
453 pci_assign_unassigned_resources();
454
455 return 0;
456}
457subsys_initcall(pcibios_init);
458
459/*
460 * Publish a region of local address space over the PCI bus
461 * to other devices.
462 */
463static void pci_set_rbar_region(unsigned int region, unsigned long localAddr,
464 unsigned long pciOffset, unsigned long regionSize)
465{
466 unsigned long mask;
467
468 if (region > 7)
469 return;
470
471 if (regionSize > (512 * 1024 * 1024))
472 return;
473
474 mask = r2p2(regionSize) - 0x10000;
475
476 /* Disable the region (in case currently in use, should never happen) */
477 ST40PCI_WRITE_INDEXED(RSR, region, 0);
478
479 /* Start of local address space to publish */
480 ST40PCI_WRITE_INDEXED(RLAR, region, PHYSADDR(localAddr) );
481
482 /* Start of region in PCI address space as an offset from MBAR0 */
483 ST40PCI_WRITE_INDEXED(RBAR, region, pciOffset);
484
485 /* Size of region */
486 ST40PCI_WRITE_INDEXED(RSR, region, mask | 1);
487}
488
diff --git a/arch/sh/drivers/pci/pci-st40.h b/arch/sh/drivers/pci/pci-st40.h
deleted file mode 100644
index cf0d35bd135c..000000000000
--- a/arch/sh/drivers/pci/pci-st40.h
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
3 *
4 * May be copied or modified under the terms of the GNU General Public
5 * License. See linux/COPYING for more information.
6 *
7 * Definitions for the ST40 PCI hardware.
8 */
9
10#ifndef __PCI_ST40_H__
11#define __PCI_ST40_H__
12
13#define ST40PCI_VCR_STATUS 0x00
14
15#define ST40PCI_VCR_VERSION 0x08
16
17#define ST40PCI_CR 0x10
18
19#define CR_SOFT_RESET (1<<12)
20#define CR_PFCS (1<<11)
21#define CR_PFE (1<<9)
22#define CR_BMAM (1<<6)
23#define CR_HOST (1<<5)
24#define CR_CLKEN (1<<4)
25#define CR_SOCS (1<<3)
26#define CR_IOCS (1<<2)
27#define CR_RSTCTL (1<<1)
28#define CR_CFINT (1<<0)
29#define CR_LOCK_MASK 0x5a000000
30
31
32#define ST40PCI_LSR0 0X14
33#define ST40PCI_LAR0 0x1c
34
35#define ST40PCI_INT 0x24
36#define INT_MNLTDIM (1<<15)
37#define INT_TTADI (1<<14)
38#define INT_TMTO (1<<9)
39#define INT_MDEI (1<<8)
40#define INT_APEDI (1<<7)
41#define INT_SDI (1<<6)
42#define INT_DPEITW (1<<5)
43#define INT_PEDITR (1<<4)
44#define INT_TADIM (1<<3)
45#define INT_MADIM (1<<2)
46#define INT_MWPDI (1<<1)
47#define INT_MRDPEI (1<<0)
48
49
50#define ST40PCI_INTM 0x28
51#define ST40PCI_AIR 0x2c
52
53#define ST40PCI_CIR 0x30
54#define CIR_PIOTEM (1<<31)
55#define CIR_RWTET (1<<26)
56
57#define ST40PCI_AINT 0x40
58#define AINT_MBI (1<<13)
59#define AINT_TBTOI (1<<12)
60#define AINT_MBTOI (1<<11)
61#define AINT_TAI (1<<3)
62#define AINT_MAI (1<<2)
63#define AINT_RDPEI (1<<1)
64#define AINT_WDPE (1<<0)
65
66#define ST40PCI_AINTM 0x44
67#define ST40PCI_BMIR 0x48
68#define ST40PCI_PAR 0x4c
69#define ST40PCI_MBR 0x50
70#define ST40PCI_IOBR 0x54
71#define ST40PCI_PINT 0x58
72#define ST40PCI_PINTM 0x5c
73#define ST40PCI_MBMR 0x70
74#define ST40PCI_IOBMR 0x74
75#define ST40PCI_PDR 0x78
76
77/* H8 specific registers start here */
78#define ST40PCI_WCBAR 0x7c
79#define ST40PCI_LOCCFG_UNLOCK 0x34
80
81#define ST40PCI_RBAR0 0x100
82#define ST40PCI_RSR0 0x104
83#define ST40PCI_RLAR0 0x108
84
85#define ST40PCI_RBAR1 0x110
86#define ST40PCI_RSR1 0x114
87#define ST40PCI_RLAR1 0x118
88
89
90#define ST40PCI_RBAR2 0x120
91#define ST40PCI_RSR2 0x124
92#define ST40PCI_RLAR2 0x128
93
94#define ST40PCI_RBAR3 0x130
95#define ST40PCI_RSR3 0x134
96#define ST40PCI_RLAR3 0x138
97
98#define ST40PCI_RBAR4 0x140
99#define ST40PCI_RSR4 0x144
100#define ST40PCI_RLAR4 0x148
101
102#define ST40PCI_RBAR5 0x150
103#define ST40PCI_RSR5 0x154
104#define ST40PCI_RLAR5 0x158
105
106#define ST40PCI_RBAR6 0x160
107#define ST40PCI_RSR6 0x164
108#define ST40PCI_RLAR6 0x168
109
110#define ST40PCI_RBAR7 0x170
111#define ST40PCI_RSR7 0x174
112#define ST40PCI_RLAR7 0x178
113
114
115#define ST40PCI_RBAR(n) (0x100+(0x10*(n)))
116#define ST40PCI_RSR(n) (0x104+(0x10*(n)))
117#define ST40PCI_RLAR(n) (0x108+(0x10*(n)))
118
119#define ST40PCI_PERF 0x80
120#define PERF_MASTER_WRITE_POSTING (1<<4)
121/* H8 specific registers end here */
122
123
124/* These are configs space registers */
125#define ST40PCI_CSR_VID 0x10000
126#define ST40PCI_CSR_DID 0x10002
127#define ST40PCI_CSR_CMD 0x10004
128#define ST40PCI_CSR_STATUS 0x10006
129#define ST40PCI_CSR_MBAR0 0x10010
130#define ST40PCI_CSR_TRDY 0x10040
131#define ST40PCI_CSR_RETRY 0x10041
132#define ST40PCI_CSR_MIT 0x1000d
133
134#define ST40_IO_ADDR 0xb6000000
135
136#endif /* __PCI_ST40_H__ */
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index 1f141a8ba17c..4b81d9c47b00 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -10,7 +10,6 @@ obj-y := debugtraps.o io.o io_generic.o irq.o machvec.o process.o ptrace.o \
10 10
11obj-y += cpu/ timers/ 11obj-y += cpu/ timers/
12obj-$(CONFIG_VSYSCALL) += vsyscall/ 12obj-$(CONFIG_VSYSCALL) += vsyscall/
13
14obj-$(CONFIG_SMP) += smp.o 13obj-$(CONFIG_SMP) += smp.o
15obj-$(CONFIG_CF_ENABLER) += cf-enabler.o 14obj-$(CONFIG_CF_ENABLER) += cf-enabler.o
16obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o 15obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o
@@ -22,3 +21,5 @@ obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
22obj-$(CONFIG_CRASH_DUMP) += crash_dump.o 21obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
23obj-$(CONFIG_PM) += pm.o 22obj-$(CONFIG_PM) += pm.o
24obj-$(CONFIG_STACKTRACE) += stacktrace.o 23obj-$(CONFIG_STACKTRACE) += stacktrace.o
24
25EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S
index 2b2a9e02fb75..b6abf38d3a8d 100644
--- a/arch/sh/kernel/cpu/sh3/ex.S
+++ b/arch/sh/kernel/cpu/sh3/ex.S
@@ -46,7 +46,7 @@ ENTRY(exception_handling_table)
46 .long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/ 46 .long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/
47ENTRY(nmi_slot) 47ENTRY(nmi_slot)
48#if defined (CONFIG_KGDB_NMI) 48#if defined (CONFIG_KGDB_NMI)
49 .long debug_enter /* 1C0 */ ! Allow trap to debugger 49 .long kgdb_handle_exception /* 1C0 */ ! Allow trap to debugger
50#else 50#else
51 .long exception_none /* 1C0 */ ! Not implemented yet 51 .long exception_none /* 1C0 */ ! Not implemented yet
52#endif 52#endif
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 21375d777e99..bc9c28a69bf1 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -139,14 +139,6 @@ int __init detect_cpu_and_cache_system(void)
139 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER | 139 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
140 CPU_HAS_LLSC; 140 CPU_HAS_LLSC;
141 break; 141 break;
142 case 0x8000:
143 boot_cpu_data.type = CPU_ST40RA;
144 boot_cpu_data.flags |= CPU_HAS_FPU;
145 break;
146 case 0x8100:
147 boot_cpu_data.type = CPU_ST40GX1;
148 boot_cpu_data.flags |= CPU_HAS_FPU;
149 break;
150 case 0x700: 142 case 0x700:
151 boot_cpu_data.type = CPU_SH4_501; 143 boot_cpu_data.type = CPU_SH4_501;
152 boot_cpu_data.icache.ways = 2; 144 boot_cpu_data.icache.ways = 2;
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index 348da194ec99..0586bc62ad96 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -11,7 +11,6 @@
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/kernel_stat.h> 12#include <linux/kernel_stat.h>
13#include <linux/seq_file.h> 13#include <linux/seq_file.h>
14#include <linux/irq.h>
15#include <asm/processor.h> 14#include <asm/processor.h>
16#include <asm/machvec.h> 15#include <asm/machvec.h>
17#include <asm/uaccess.h> 16#include <asm/uaccess.h>
diff --git a/arch/sh/kernel/kgdb_stub.c b/arch/sh/kernel/kgdb_stub.c
index 2fdc700dfd6e..d453c3a1c79f 100644
--- a/arch/sh/kernel/kgdb_stub.c
+++ b/arch/sh/kernel/kgdb_stub.c
@@ -102,6 +102,7 @@
102#include <linux/init.h> 102#include <linux/init.h>
103#include <linux/console.h> 103#include <linux/console.h>
104#include <linux/sysrq.h> 104#include <linux/sysrq.h>
105#include <linux/module.h>
105#include <asm/system.h> 106#include <asm/system.h>
106#include <asm/cacheflush.h> 107#include <asm/cacheflush.h>
107#include <asm/current.h> 108#include <asm/current.h>
@@ -116,7 +117,9 @@ kgdb_debug_hook_t *kgdb_debug_hook;
116kgdb_bus_error_hook_t *kgdb_bus_err_hook; 117kgdb_bus_error_hook_t *kgdb_bus_err_hook;
117 118
118int (*kgdb_getchar)(void); 119int (*kgdb_getchar)(void);
120EXPORT_SYMBOL_GPL(kgdb_getchar);
119void (*kgdb_putchar)(int); 121void (*kgdb_putchar)(int);
122EXPORT_SYMBOL_GPL(kgdb_putchar);
120 123
121static void put_debug_char(int c) 124static void put_debug_char(int c)
122{ 125{
@@ -136,7 +139,7 @@ static int get_debug_char(void)
136#define NUMREGBYTES (MAXREG*4) 139#define NUMREGBYTES (MAXREG*4)
137#define OUTBUFMAX (NUMREGBYTES*2+512) 140#define OUTBUFMAX (NUMREGBYTES*2+512)
138 141
139enum regs { 142enum {
140 R0 = 0, R1, R2, R3, R4, R5, R6, R7, 143 R0 = 0, R1, R2, R3, R4, R5, R6, R7,
141 R8, R9, R10, R11, R12, R13, R14, R15, 144 R8, R9, R10, R11, R12, R13, R14, R15,
142 PC, PR, GBR, VBR, MACH, MACL, SR, 145 PC, PR, GBR, VBR, MACH, MACL, SR,
@@ -176,9 +179,13 @@ int kgdb_nofault; /* Boolean to ignore bus errs (i.e. in GDB) */
176 179
177/* SCI/UART settings, used in kgdb_console_setup() */ 180/* SCI/UART settings, used in kgdb_console_setup() */
178int kgdb_portnum = CONFIG_KGDB_DEFPORT; 181int kgdb_portnum = CONFIG_KGDB_DEFPORT;
182EXPORT_SYMBOL_GPL(kgdb_portnum);
179int kgdb_baud = CONFIG_KGDB_DEFBAUD; 183int kgdb_baud = CONFIG_KGDB_DEFBAUD;
184EXPORT_SYMBOL_GPL(kgdb_baud);
180char kgdb_parity = CONFIG_KGDB_DEFPARITY; 185char kgdb_parity = CONFIG_KGDB_DEFPARITY;
186EXPORT_SYMBOL_GPL(kgdb_parity);
181char kgdb_bits = CONFIG_KGDB_DEFBITS; 187char kgdb_bits = CONFIG_KGDB_DEFBITS;
188EXPORT_SYMBOL_GPL(kgdb_bits);
182 189
183/* Jump buffer for setjmp/longjmp */ 190/* Jump buffer for setjmp/longjmp */
184static jmp_buf rem_com_env; 191static jmp_buf rem_com_env;
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 0b8c45d53a47..4156aac8c27d 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -303,7 +303,6 @@ static const char *cpu_name[] = {
303 [CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R", 303 [CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R",
304 [CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R", 304 [CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R",
305 [CPU_SH7760] = "SH7760", 305 [CPU_SH7760] = "SH7760",
306 [CPU_ST40RA] = "ST40RA", [CPU_ST40GX1] = "ST40GX1",
307 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501", 306 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
308 [CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780", 307 [CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
309 [CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343", 308 [CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",
diff --git a/arch/sh/kernel/sh_ksyms.c b/arch/sh/kernel/sh_ksyms.c
index 548e4285b375..e1a6de9088b5 100644
--- a/arch/sh/kernel/sh_ksyms.c
+++ b/arch/sh/kernel/sh_ksyms.c
@@ -106,7 +106,6 @@ DECLARE_EXPORT(__movmem);
106DECLARE_EXPORT(__movstr); 106DECLARE_EXPORT(__movstr);
107#endif 107#endif
108 108
109#ifdef CONFIG_CPU_SH4
110#if __GNUC__ == 4 109#if __GNUC__ == 4
111DECLARE_EXPORT(__movmem_i4_even); 110DECLARE_EXPORT(__movmem_i4_even);
112DECLARE_EXPORT(__movmem_i4_odd); 111DECLARE_EXPORT(__movmem_i4_odd);
@@ -126,7 +125,6 @@ DECLARE_EXPORT(__movstr_i4_even);
126DECLARE_EXPORT(__movstr_i4_odd); 125DECLARE_EXPORT(__movstr_i4_odd);
127DECLARE_EXPORT(__movstrSI12_i4); 126DECLARE_EXPORT(__movstrSI12_i4);
128#endif /* __GNUC__ == 4 */ 127#endif /* __GNUC__ == 4 */
129#endif
130 128
131#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \ 129#if !defined(CONFIG_CACHE_OFF) && (defined(CONFIG_CPU_SH4) || \
132 defined(CONFIG_SH7705_CACHE_32KB)) 130 defined(CONFIG_SH7705_CACHE_32KB))
diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile
index e23dd1a3fccd..9dc7b6985052 100644
--- a/arch/sh/lib/Makefile
+++ b/arch/sh/lib/Makefile
@@ -9,3 +9,5 @@ memcpy-y := memcpy.o
9memcpy-$(CONFIG_CPU_SH4) := memcpy-sh4.o 9memcpy-$(CONFIG_CPU_SH4) := memcpy-sh4.o
10 10
11lib-y += $(memcpy-y) 11lib-y += $(memcpy-y)
12
13EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index cf446bbab5b0..1265f204f7d1 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -17,7 +17,7 @@ config CPU_SH4
17 bool 17 bool
18 select CPU_HAS_INTEVT 18 select CPU_HAS_INTEVT
19 select CPU_HAS_SR_RB 19 select CPU_HAS_SR_RB
20 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2 20 select CPU_HAS_PTEA if !CPU_SH4A || CPU_SHX2
21 select CPU_HAS_FPU if !CPU_SH4AL_DSP 21 select CPU_HAS_FPU if !CPU_SH4AL_DSP
22 22
23config CPU_SH4A 23config CPU_SH4A
@@ -29,10 +29,6 @@ config CPU_SH4AL_DSP
29 select CPU_SH4A 29 select CPU_SH4A
30 select CPU_HAS_DSP 30 select CPU_HAS_DSP
31 31
32config CPU_SUBTYPE_ST40
33 bool
34 select CPU_SH4
35
36config CPU_SHX2 32config CPU_SHX2
37 bool 33 bool
38 34
@@ -152,21 +148,6 @@ config CPU_SUBTYPE_SH4_202
152 bool "Support SH4-202 processor" 148 bool "Support SH4-202 processor"
153 select CPU_SH4 149 select CPU_SH4
154 150
155# ST40 Processor Support
156
157config CPU_SUBTYPE_ST40STB1
158 bool "Support ST40STB1/ST40RA processors"
159 select CPU_SUBTYPE_ST40
160 help
161 Select ST40STB1 if you have a ST40RA CPU.
162 This was previously called the ST40STB1, hence the option name.
163
164config CPU_SUBTYPE_ST40GX1
165 bool "Support ST40GX1 processor"
166 select CPU_SUBTYPE_ST40
167 help
168 Select ST40GX1 if you have a ST40GX1 CPU.
169
170# SH-4A Processor Support 151# SH-4A Processor Support
171 152
172config CPU_SUBTYPE_SH7770 153config CPU_SUBTYPE_SH7770
diff --git a/arch/sh/mm/Makefile b/arch/sh/mm/Makefile
index ee30fb44dfe1..aa44607f072d 100644
--- a/arch/sh/mm/Makefile
+++ b/arch/sh/mm/Makefile
@@ -33,3 +33,5 @@ endif
33obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o 33obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
34obj-$(CONFIG_32BIT) += pmb.o 34obj-$(CONFIG_32BIT) += pmb.o
35obj-$(CONFIG_NUMA) += numa.o 35obj-$(CONFIG_NUMA) += numa.o
36
37EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/mm/clear_page.S b/arch/sh/mm/clear_page.S
index 8a706131e521..7a7c81ee3f01 100644
--- a/arch/sh/mm/clear_page.S
+++ b/arch/sh/mm/clear_page.S
@@ -150,48 +150,3 @@ ENTRY(__clear_user)
150 .long 8b, .Lbad_clear_user 150 .long 8b, .Lbad_clear_user
151 .long 9b, .Lbad_clear_user 151 .long 9b, .Lbad_clear_user
152.previous 152.previous
153
154#if defined(CONFIG_CPU_SH4)
155/*
156 * __clear_user_page
157 * @to: P3 address (with same color)
158 * @orig_to: P1 address
159 *
160 * void __clear_user_page(void *to, void *orig_to)
161 */
162
163/*
164 * r0 --- scratch
165 * r4 --- to
166 * r5 --- orig_to
167 * r6 --- to + PAGE_SIZE
168 */
169ENTRY(__clear_user_page)
170 mov.l .Lpsz,r0
171 mov r4,r6
172 add r0,r6
173 mov #0,r0
174 !
1751: ocbi @r5
176 add #32,r5
177 movca.l r0,@r4
178 mov r4,r1
179 add #32,r4
180 mov.l r0,@-r4
181 mov.l r0,@-r4
182 mov.l r0,@-r4
183 mov.l r0,@-r4
184 mov.l r0,@-r4
185 mov.l r0,@-r4
186 mov.l r0,@-r4
187 add #28,r4
188 cmp/eq r6,r4
189 bf/s 1b
190 ocbwb @r1
191 !
192 rts
193 nop
194.Lpsz: .long PAGE_SIZE
195
196#endif
197
diff --git a/arch/sh/mm/copy_page.S b/arch/sh/mm/copy_page.S
index 3d8409daa4be..40685018b952 100644
--- a/arch/sh/mm/copy_page.S
+++ b/arch/sh/mm/copy_page.S
@@ -68,67 +68,6 @@ ENTRY(copy_page_slow)
68 rts 68 rts
69 nop 69 nop
70 70
71#if defined(CONFIG_CPU_SH4)
72/*
73 * __copy_user_page
74 * @to: P1 address (with same color)
75 * @from: P1 address
76 * @orig_to: P1 address
77 *
78 * void __copy_user_page(void *to, void *from, void *orig_to)
79 */
80
81/*
82 * r0, r1, r2, r3, r4, r5, r6, r7 --- scratch
83 * r8 --- from + PAGE_SIZE
84 * r9 --- orig_to
85 * r10 --- to
86 * r11 --- from
87 */
88ENTRY(__copy_user_page)
89 mov.l r8,@-r15
90 mov.l r9,@-r15
91 mov.l r10,@-r15
92 mov.l r11,@-r15
93 mov r4,r10
94 mov r5,r11
95 mov r6,r9
96 mov r5,r8
97 mov.l .Lpsz,r0
98 add r0,r8
99 !
1001: ocbi @r9
101 add #32,r9
102 mov.l @r11+,r0
103 mov.l @r11+,r1
104 mov.l @r11+,r2
105 mov.l @r11+,r3
106 mov.l @r11+,r4
107 mov.l @r11+,r5
108 mov.l @r11+,r6
109 mov.l @r11+,r7
110 movca.l r0,@r10
111 mov r10,r0
112 add #32,r10
113 mov.l r7,@-r10
114 mov.l r6,@-r10
115 mov.l r5,@-r10
116 mov.l r4,@-r10
117 mov.l r3,@-r10
118 mov.l r2,@-r10
119 mov.l r1,@-r10
120 ocbwb @r0
121 cmp/eq r11,r8
122 bf/s 1b
123 add #28,r10
124 !
125 mov.l @r15+,r11
126 mov.l @r15+,r10
127 mov.l @r15+,r9
128 mov.l @r15+,r8
129 rts
130 nop
131#endif
132 .align 2 71 .align 2
133.Lpsz: .long PAGE_SIZE 72.Lpsz: .long PAGE_SIZE
134/* 73/*
diff --git a/arch/sh/mm/pg-sh4.c b/arch/sh/mm/pg-sh4.c
index 25f5c6f6821d..8c7a9ca79879 100644
--- a/arch/sh/mm/pg-sh4.c
+++ b/arch/sh/mm/pg-sh4.c
@@ -9,6 +9,8 @@
9#include <linux/mm.h> 9#include <linux/mm.h>
10#include <linux/mutex.h> 10#include <linux/mutex.h>
11#include <linux/fs.h> 11#include <linux/fs.h>
12#include <linux/highmem.h>
13#include <linux/module.h>
12#include <asm/mmu_context.h> 14#include <asm/mmu_context.h>
13#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
14 16
@@ -50,34 +52,61 @@ static inline void kunmap_coherent(struct page *page)
50void clear_user_page(void *to, unsigned long address, struct page *page) 52void clear_user_page(void *to, unsigned long address, struct page *page)
51{ 53{
52 __set_bit(PG_mapped, &page->flags); 54 __set_bit(PG_mapped, &page->flags);
53 if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) 55
54 clear_page(to); 56 clear_page(to);
55 else { 57 if ((((address & PAGE_MASK) ^ (unsigned long)to) & CACHE_ALIAS))
56 void *vto = kmap_coherent(page, address); 58 __flush_wback_region(to, PAGE_SIZE);
57 __clear_user_page(vto, to);
58 kunmap_coherent(vto);
59 }
60} 59}
61 60
62/* 61void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
63 * copy_user_page 62 unsigned long vaddr, void *dst, const void *src,
64 * @to: P1 address 63 unsigned long len)
65 * @from: P1 address
66 * @address: U0 address to be mapped
67 * @page: page (virt_to_page(to))
68 */
69void copy_user_page(void *to, void *from, unsigned long address,
70 struct page *page)
71{ 64{
65 void *vto;
66
72 __set_bit(PG_mapped, &page->flags); 67 __set_bit(PG_mapped, &page->flags);
73 if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) 68
74 copy_page(to, from); 69 vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
75 else { 70 memcpy(vto, src, len);
76 void *vfrom = kmap_coherent(page, address); 71 kunmap_coherent(vto);
77 __copy_user_page(vfrom, from, to); 72
78 kunmap_coherent(vfrom); 73 if (vma->vm_flags & VM_EXEC)
79 } 74 flush_cache_page(vma, vaddr, page_to_pfn(page));
75}
76
77void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
78 unsigned long vaddr, void *dst, const void *src,
79 unsigned long len)
80{
81 void *vfrom;
82
83 __set_bit(PG_mapped, &page->flags);
84
85 vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
86 memcpy(dst, vfrom, len);
87 kunmap_coherent(vfrom);
88}
89
90void copy_user_highpage(struct page *to, struct page *from,
91 unsigned long vaddr, struct vm_area_struct *vma)
92{
93 void *vfrom, *vto;
94
95 __set_bit(PG_mapped, &to->flags);
96
97 vto = kmap_atomic(to, KM_USER1);
98 vfrom = kmap_coherent(from, vaddr);
99 copy_page(vto, vfrom);
100 kunmap_coherent(vfrom);
101
102 if (((vaddr ^ (unsigned long)vto) & CACHE_ALIAS))
103 __flush_wback_region(vto, PAGE_SIZE);
104
105 kunmap_atomic(vto, KM_USER1);
106 /* Make sure this page is cleared on other CPU's too before using it */
107 smp_wmb();
80} 108}
109EXPORT_SYMBOL(copy_user_highpage);
81 110
82/* 111/*
83 * For SH-4, we have our own implementation for ptep_get_and_clear 112 * For SH-4, we have our own implementation for ptep_get_and_clear
diff --git a/arch/sh/oprofile/Makefile b/arch/sh/oprofile/Makefile
index 1f25d9bb7538..2efc2e79fd29 100644
--- a/arch/sh/oprofile/Makefile
+++ b/arch/sh/oprofile/Makefile
@@ -15,3 +15,4 @@ profdrvr-$(CONFIG_CPU_SUBTYPE_SH7091) := op_model_sh7750.o
15 15
16oprofile-y := $(DRIVER_OBJS) $(profdrvr-y) 16oprofile-y := $(DRIVER_OBJS) $(profdrvr-y)
17 17
18EXTRA_CFLAGS += -Werror
diff --git a/arch/sh64/kernel/process.c b/arch/sh64/kernel/process.c
index ceb9458abda4..0761af4d2a42 100644
--- a/arch/sh64/kernel/process.c
+++ b/arch/sh64/kernel/process.c
@@ -26,6 +26,7 @@
26#include <linux/reboot.h> 26#include <linux/reboot.h>
27#include <linux/init.h> 27#include <linux/init.h>
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/proc_fs.h>
29#include <asm/uaccess.h> 30#include <asm/uaccess.h>
30#include <asm/pgtable.h> 31#include <asm/pgtable.h>
31 32
@@ -656,9 +657,6 @@ unsigned long get_wchan(struct task_struct *p)
656 */ 657 */
657 658
658#if defined(CONFIG_SH64_PROC_ASIDS) 659#if defined(CONFIG_SH64_PROC_ASIDS)
659#include <linux/init.h>
660#include <linux/proc_fs.h>
661
662static int 660static int
663asids_proc_info(char *buf, char **start, off_t fpos, int length, int *eof, void *data) 661asids_proc_info(char *buf, char **start, off_t fpos, int length, int *eof, void *data)
664{ 662{
@@ -686,10 +684,8 @@ asids_proc_info(char *buf, char **start, off_t fpos, int length, int *eof, void
686 684
687static int __init register_proc_asids(void) 685static int __init register_proc_asids(void)
688{ 686{
689 create_proc_read_entry("asids", 0, NULL, asids_proc_info, NULL); 687 create_proc_read_entry("asids", 0, NULL, asids_proc_info, NULL);
690 return 0; 688 return 0;
691} 689}
692
693__initcall(register_proc_asids); 690__initcall(register_proc_asids);
694#endif 691#endif
695
diff --git a/arch/sh64/kernel/traps.c b/arch/sh64/kernel/traps.c
index c03101fab467..f32df3831f45 100644
--- a/arch/sh64/kernel/traps.c
+++ b/arch/sh64/kernel/traps.c
@@ -30,7 +30,6 @@
30#include <linux/interrupt.h> 30#include <linux/interrupt.h>
31#include <linux/sysctl.h> 31#include <linux/sysctl.h>
32#include <linux/module.h> 32#include <linux/module.h>
33
34#include <asm/system.h> 33#include <asm/system.h>
35#include <asm/uaccess.h> 34#include <asm/uaccess.h>
36#include <asm/io.h> 35#include <asm/io.h>
@@ -242,9 +241,6 @@ DO_ERROR(12, SIGILL, "reserved instruction", reserved_inst, current)
242 241
243#endif /* CONFIG_SH64_ID2815_WORKAROUND */ 242#endif /* CONFIG_SH64_ID2815_WORKAROUND */
244 243
245
246#include <asm/system.h>
247
248/* Called with interrupts disabled */ 244/* Called with interrupts disabled */
249asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs) 245asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
250{ 246{
@@ -984,4 +980,3 @@ asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
984 /* Clear all DEBUGINT causes */ 980 /* Clear all DEBUGINT causes */
985 poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0); 981 poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
986} 982}
987
diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c
index 78277a118b67..8e8c8b8e81ee 100644
--- a/drivers/rtc/rtc-sh.c
+++ b/drivers/rtc/rtc-sh.c
@@ -351,8 +351,10 @@ static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
351 tm->tm_sec, tm->tm_min, tm->tm_hour, 351 tm->tm_sec, tm->tm_min, tm->tm_hour,
352 tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday); 352 tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
353 353
354 if (rtc_valid_tm(tm) < 0) 354 if (rtc_valid_tm(tm) < 0) {
355 dev_err(dev, "invalid date\n"); 355 dev_err(dev, "invalid date\n");
356 rtc_time_to_tm(0, tm);
357 }
356 358
357 return 0; 359 return 0;
358} 360}
@@ -588,7 +590,7 @@ static int __devinit sh_rtc_probe(struct platform_device *pdev)
588 590
589 rtc->rtc_dev = rtc_device_register("sh", &pdev->dev, 591 rtc->rtc_dev = rtc_device_register("sh", &pdev->dev,
590 &sh_rtc_ops, THIS_MODULE); 592 &sh_rtc_ops, THIS_MODULE);
591 if (IS_ERR(rtc)) { 593 if (IS_ERR(rtc->rtc_dev)) {
592 ret = PTR_ERR(rtc->rtc_dev); 594 ret = PTR_ERR(rtc->rtc_dev);
593 goto err_badmap; 595 goto err_badmap;
594 } 596 }
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index e89ae29645d6..d24621ce799a 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -77,7 +77,6 @@
77# define SCIF_ONLY 77# define SCIF_ONLY
78#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 78#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
79# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 79# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
80# define SCI_NPORTS 2
81# define SCIF_ORER 0x0001 /* overrun error bit */ 80# define SCIF_ORER 0x0001 /* overrun error bit */
82# define PACR 0xa4050100 81# define PACR 0xa4050100
83# define PBCR 0xa4050102 82# define PBCR 0xa4050102
@@ -102,12 +101,6 @@
102# define SCIF_ORER 0x0001 /* overrun error bit */ 101# define SCIF_ORER 0x0001 /* overrun error bit */
103# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 102# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
104# define SCIF_ONLY 103# define SCIF_ONLY
105#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
106# define SCSPTR1 0xffe00020 /* 16 bit SCIF */
107# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
108# define SCIF_ORER 0x0001 /* overrun error bit */
109# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
110# define SCIF_ONLY
111#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 104#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
112# include <asm/hardware.h> 105# include <asm/hardware.h>
113# define SCIF_BASE_ADDR 0x01030000 106# define SCIF_BASE_ADDR 0x01030000
@@ -116,8 +109,7 @@
116# define SCIF_LSR2_OFFS 0x0000024 109# define SCIF_LSR2_OFFS 0x0000024
117# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 110# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
118# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 111# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
119# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, 112# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
120 TE=1,RE=1,REIE=1 */
121# define SCIF_ONLY 113# define SCIF_ONLY
122#elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 114#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
123# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 115# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
@@ -577,15 +569,6 @@ static inline int sci_rxd_in(struct uart_port *port)
577 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ 569 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
578 return 1; 570 return 1;
579} 571}
580#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
581static inline int sci_rxd_in(struct uart_port *port)
582{
583 if (port->mapbase == 0xffe00000)
584 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
585 else
586 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
587
588}
589#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 572#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
590static inline int sci_rxd_in(struct uart_port *port) 573static inline int sci_rxd_in(struct uart_port *port)
591{ 574{
diff --git a/drivers/sh/superhyway/superhyway.c b/drivers/sh/superhyway/superhyway.c
index 7d873b3b0513..4d0282b821b5 100644
--- a/drivers/sh/superhyway/superhyway.c
+++ b/drivers/sh/superhyway/superhyway.c
@@ -107,16 +107,17 @@ int superhyway_add_devices(struct superhyway_bus *bus,
107static int __init superhyway_init(void) 107static int __init superhyway_init(void)
108{ 108{
109 struct superhyway_bus *bus; 109 struct superhyway_bus *bus;
110 int ret = 0; 110 int ret;
111 111
112 device_register(&superhyway_bus_device); 112 ret = device_register(&superhyway_bus_device);
113 if (unlikely(ret))
114 return ret;
113 115
114 for (bus = superhyway_channels; bus->ops; bus++) 116 for (bus = superhyway_channels; bus->ops; bus++)
115 ret |= superhyway_scan_bus(bus); 117 ret |= superhyway_scan_bus(bus);
116 118
117 return ret; 119 return ret;
118} 120}
119
120postcore_initcall(superhyway_init); 121postcore_initcall(superhyway_init);
121 122
122static const struct superhyway_device_id * 123static const struct superhyway_device_id *
diff --git a/include/asm-sh/cacheflush.h b/include/asm-sh/cacheflush.h
index aa558da08471..b91246153b7e 100644
--- a/include/asm-sh/cacheflush.h
+++ b/include/asm-sh/cacheflush.h
@@ -43,21 +43,31 @@ extern void __flush_purge_region(void *start, int size);
43extern void __flush_invalidate_region(void *start, int size); 43extern void __flush_invalidate_region(void *start, int size);
44#endif 44#endif
45 45
46#define flush_cache_vmap(start, end) flush_cache_all() 46#ifdef CONFIG_CPU_SH4
47#define flush_cache_vunmap(start, end) flush_cache_all() 47extern void copy_to_user_page(struct vm_area_struct *vma,
48 struct page *page, unsigned long vaddr, void *dst, const void *src,
49 unsigned long len);
48 50
49#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 51extern void copy_from_user_page(struct vm_area_struct *vma,
52 struct page *page, unsigned long vaddr, void *dst, const void *src,
53 unsigned long len);
54#else
55#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
50 do { \ 56 do { \
51 flush_cache_page(vma, vaddr, page_to_pfn(page));\ 57 flush_cache_page(vma, vaddr, page_to_pfn(page));\
52 memcpy(dst, src, len); \ 58 memcpy(dst, src, len); \
53 flush_icache_user_range(vma, page, vaddr, len); \ 59 flush_icache_user_range(vma, page, vaddr, len); \
54 } while (0) 60 } while (0)
55 61
56#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 62#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
57 do { \ 63 do { \
58 flush_cache_page(vma, vaddr, page_to_pfn(page));\ 64 flush_cache_page(vma, vaddr, page_to_pfn(page));\
59 memcpy(dst, src, len); \ 65 memcpy(dst, src, len); \
60 } while (0) 66 } while (0)
67#endif
68
69#define flush_cache_vmap(start, end) flush_cache_all()
70#define flush_cache_vunmap(start, end) flush_cache_all()
61 71
62#define HAVE_ARCH_UNMAPPED_AREA 72#define HAVE_ARCH_UNMAPPED_AREA
63 73
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
index 3880ce047fe0..7b795ac5477c 100644
--- a/include/asm-sh/cpu-sh3/timer.h
+++ b/include/asm-sh/cpu-sh3/timer.h
@@ -23,8 +23,7 @@
23 * --------------------------------------------------------------------------- 23 * ---------------------------------------------------------------------------
24 */ 24 */
25 25
26#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ 26#if !defined(CONFIG_CPU_SUBTYPE_SH7720)
27 !defined(CONFIG_CPU_SUBTYPE_SH7727)
28#define TMU_TOCR 0xfffffe90 /* Byte access */ 27#define TMU_TOCR 0xfffffe90 /* Byte access */
29#endif 28#endif
30 29
@@ -58,8 +57,7 @@
58#define TMU2_TCOR 0xfffffeac /* Long access */ 57#define TMU2_TCOR 0xfffffeac /* Long access */
59#define TMU2_TCNT 0xfffffeb0 /* Long access */ 58#define TMU2_TCNT 0xfffffeb0 /* Long access */
60#define TMU2_TCR 0xfffffeb4 /* Word access */ 59#define TMU2_TCR 0xfffffeb4 /* Word access */
61#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ 60#if !defined(CONFIG_CPU_SUBTYPE_SH7720)
62 !defined(CONFIG_CPU_SUBTYPE_SH7727)
63#define TMU2_TCPR2 0xfffffeb8 /* Long access */ 61#define TMU2_TCPR2 0xfffffeb8 /* Long access */
64#endif 62#endif
65#endif 63#endif
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
index 3aa8b07da47d..d00a8fde7c7f 100644
--- a/include/asm-sh/page.h
+++ b/include/asm-sh/page.h
@@ -73,10 +73,13 @@ extern void copy_page_nommu(void *to, void *from);
73#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \ 73#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \
74 (defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)) 74 (defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB))
75struct page; 75struct page;
76extern void clear_user_page(void *to, unsigned long address, struct page *pg); 76struct vm_area_struct;
77extern void copy_user_page(void *to, void *from, unsigned long address, struct page *pg); 77extern void clear_user_page(void *to, unsigned long address, struct page *page);
78extern void __clear_user_page(void *to, void *orig_to); 78#ifdef CONFIG_CPU_SH4
79extern void __copy_user_page(void *to, void *from, void *orig_to); 79extern void copy_user_highpage(struct page *to, struct page *from,
80 unsigned long vaddr, struct vm_area_struct *vma);
81#define __HAVE_ARCH_COPY_USER_HIGHPAGE
82#endif
80#else 83#else
81#define clear_user_page(page, vaddr, pg) clear_page(page) 84#define clear_user_page(page, vaddr, pg) clear_page(page)
82#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) 85#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index 0b1d7c665659..8f1e8be8d15d 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -322,7 +322,9 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
322#define PAGE_KERNEL __pgprot(0) 322#define PAGE_KERNEL __pgprot(0)
323#define PAGE_KERNEL_NOCACHE __pgprot(0) 323#define PAGE_KERNEL_NOCACHE __pgprot(0)
324#define PAGE_KERNEL_RO __pgprot(0) 324#define PAGE_KERNEL_RO __pgprot(0)
325#define PAGE_KERNEL_PCC __pgprot(0) 325
326#define PAGE_KERNEL_PCC(slot, type) \
327 __pgprot(0)
326#endif 328#endif
327 329
328#endif /* __ASSEMBLY__ */ 330#endif /* __ASSEMBLY__ */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index ab0028db645a..fda68480f377 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -49,7 +49,7 @@ enum cpu_type {
49 49
50 /* SH-4 types */ 50 /* SH-4 types */
51 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, 51 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
52 CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501, 52 CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
53 53
54 /* SH-4A types */ 54 /* SH-4A types */
55 CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3, 55 CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h
index ed358a376e6e..b9789c8b4d15 100644
--- a/include/asm-sh/ptrace.h
+++ b/include/asm-sh/ptrace.h
@@ -42,9 +42,6 @@
42#define REG_FPSCR 55 42#define REG_FPSCR 55
43#define REG_FPUL 56 43#define REG_FPUL 56
44 44
45/* options set using PTRACE_SETOPTIONS */
46#define PTRACE_O_TRACESYSGOOD 0x00000001
47
48/* 45/*
49 * This struct defines the way the registers are stored on the 46 * This struct defines the way the registers are stored on the
50 * kernel stack during a system call or other kernel entry. 47 * kernel stack during a system call or other kernel entry.
diff --git a/include/asm-sh/vga.h b/include/asm-sh/vga.h
new file mode 100644
index 000000000000..06a5de8ace1a
--- /dev/null
+++ b/include/asm-sh/vga.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_SH_VGA_H
2#define __ASM_SH_VGA_H
3
4/* Stupid drivers. */
5
6#endif /* __ASM_SH_VGA_H */
diff --git a/include/asm-sh64/ptrace.h b/include/asm-sh64/ptrace.h
index a6d4da519db6..c424f80e3ae0 100644
--- a/include/asm-sh64/ptrace.h
+++ b/include/asm-sh64/ptrace.h
@@ -32,6 +32,4 @@ struct pt_regs {
32extern void show_regs(struct pt_regs *); 32extern void show_regs(struct pt_regs *);
33#endif 33#endif
34 34
35#define PTRACE_O_TRACESYSGOOD 0x00000001
36
37#endif /* __ASM_SH64_PTRACE_H */ 35#endif /* __ASM_SH64_PTRACE_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-10 05:15:50 -0500