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-rw-r--r--arch/microblaze/Kconfig15
-rw-r--r--arch/microblaze/Makefile1
-rw-r--r--arch/microblaze/include/asm/io.h16
-rw-r--r--arch/microblaze/include/asm/pgtable.h15
-rw-r--r--arch/microblaze/include/asm/prom.h15
-rw-r--r--arch/microblaze/pci/Makefile5
-rw-r--r--arch/microblaze/pci/indirect_pci.c163
-rw-r--r--arch/microblaze/pci/iomap.c39
-rw-r--r--drivers/pci/Makefile1
9 files changed, 269 insertions, 1 deletions
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 71ec04137417..e1fa0844ba4e 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -256,6 +256,21 @@ source "fs/Kconfig.binfmt"
256 256
257endmenu 257endmenu
258 258
259menu "Bus Options"
260
261config PCI
262 bool "PCI support"
263
264config PCI_DOMAINS
265 def_bool PCI
266
267config PCI_SYSCALL
268 def_bool PCI
269
270source "drivers/pci/Kconfig"
271
272endmenu
273
259source "net/Kconfig" 274source "net/Kconfig"
260 275
261source "drivers/Kconfig" 276source "drivers/Kconfig"
diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
index d2d6cfcb1a30..836832dd9b26 100644
--- a/arch/microblaze/Makefile
+++ b/arch/microblaze/Makefile
@@ -50,6 +50,7 @@ libs-y += $(LIBGCC)
50core-y += arch/microblaze/kernel/ 50core-y += arch/microblaze/kernel/
51core-y += arch/microblaze/mm/ 51core-y += arch/microblaze/mm/
52core-y += arch/microblaze/platform/ 52core-y += arch/microblaze/platform/
53core-$(CONFIG_PCI) += arch/microblaze/pci/
53 54
54drivers-$(CONFIG_OPROFILE) += arch/microblaze/oprofile/ 55drivers-$(CONFIG_OPROFILE) += arch/microblaze/oprofile/
55 56
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index f82df5d221a8..06d804b15a51 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -17,7 +17,21 @@
17#include <linux/mm.h> /* Get struct page {...} */ 17#include <linux/mm.h> /* Get struct page {...} */
18#include <asm-generic/iomap.h> 18#include <asm-generic/iomap.h>
19 19
20#define PCI_DRAM_OFFSET 0 20#ifndef CONFIG_PCI
21#define _IO_BASE 0
22#define _ISA_MEM_BASE 0
23#define PCI_DRAM_OFFSET 0
24#else
25#define _IO_BASE isa_io_base
26#define _ISA_MEM_BASE isa_mem_base
27#define PCI_DRAM_OFFSET pci_dram_offset
28#endif
29
30extern unsigned long isa_io_base;
31extern unsigned long pci_io_base;
32extern unsigned long pci_dram_offset;
33
34extern resource_size_t isa_mem_base;
21 35
22#define IO_SPACE_LIMIT (0xFFFFFFFF) 36#define IO_SPACE_LIMIT (0xFFFFFFFF)
23 37
diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
index cc3a4dfc3eaa..1c47f6f8bfb6 100644
--- a/arch/microblaze/include/asm/pgtable.h
+++ b/arch/microblaze/include/asm/pgtable.h
@@ -90,6 +90,21 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
90#endif /* __ASSEMBLY__ */ 90#endif /* __ASSEMBLY__ */
91 91
92/* 92/*
93 * Macro to mark a page protection value as "uncacheable".
94 */
95
96#define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \
97 _PAGE_WRITETHRU)
98
99#define pgprot_noncached(prot) \
100 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
101 _PAGE_NO_CACHE | _PAGE_GUARDED))
102
103#define pgprot_noncached_wc(prot) \
104 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
105 _PAGE_NO_CACHE))
106
107/*
93 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash 108 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash
94 * table containing PTEs, together with a set of 16 segment registers, to 109 * table containing PTEs, together with a set of 16 segment registers, to
95 * define the virtual to physical address mapping. 110 * define the virtual to physical address mapping.
diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h
index 03f45a963204..e7d67a329bd7 100644
--- a/arch/microblaze/include/asm/prom.h
+++ b/arch/microblaze/include/asm/prom.h
@@ -31,6 +31,21 @@
31/* Other Prototypes */ 31/* Other Prototypes */
32extern int early_uartlite_console(void); 32extern int early_uartlite_console(void);
33 33
34#ifdef CONFIG_PCI
35/*
36 * PCI <-> OF matching functions
37 * (XXX should these be here?)
38 */
39struct pci_bus;
40struct pci_dev;
41extern int pci_device_from_OF_node(struct device_node *node,
42 u8 *bus, u8 *devfn);
43extern struct device_node *pci_busdev_to_OF_node(struct pci_bus *bus,
44 int devfn);
45extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);
46extern void pci_create_OF_bus_map(void);
47#endif
48
34/* 49/*
35 * OF address retreival & translation 50 * OF address retreival & translation
36 */ 51 */
diff --git a/arch/microblaze/pci/Makefile b/arch/microblaze/pci/Makefile
new file mode 100644
index 000000000000..2b8901864b23
--- /dev/null
+++ b/arch/microblaze/pci/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile
3#
4
5obj-$(CONFIG_PCI) += pci_32.o pci-common.o indirect_pci.o iomap.o
diff --git a/arch/microblaze/pci/indirect_pci.c b/arch/microblaze/pci/indirect_pci.c
new file mode 100644
index 000000000000..25f18f017f21
--- /dev/null
+++ b/arch/microblaze/pci/indirect_pci.c
@@ -0,0 +1,163 @@
1/*
2 * Support for indirect PCI bridges.
3 *
4 * Copyright (C) 1998 Gabriel Paubert.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/delay.h>
15#include <linux/string.h>
16#include <linux/init.h>
17
18#include <asm/io.h>
19#include <asm/prom.h>
20#include <asm/pci-bridge.h>
21
22static int
23indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
24 int len, u32 *val)
25{
26 struct pci_controller *hose = pci_bus_to_host(bus);
27 volatile void __iomem *cfg_data;
28 u8 cfg_type = 0;
29 u32 bus_no, reg;
30
31 if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
32 if (bus->number != hose->first_busno)
33 return PCIBIOS_DEVICE_NOT_FOUND;
34 if (devfn != 0)
35 return PCIBIOS_DEVICE_NOT_FOUND;
36 }
37
38 if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
39 if (bus->number != hose->first_busno)
40 cfg_type = 1;
41
42 bus_no = (bus->number == hose->first_busno) ?
43 hose->self_busno : bus->number;
44
45 if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
46 reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
47 else
48 reg = offset & 0xfc; /* Only 3 bits for function */
49
50 if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
51 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
52 (devfn << 8) | reg | cfg_type));
53 else
54 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
55 (devfn << 8) | reg | cfg_type));
56
57 /*
58 * Note: the caller has already checked that offset is
59 * suitably aligned and that len is 1, 2 or 4.
60 */
61 cfg_data = hose->cfg_data + (offset & 3); /* Only 3 bits for function */
62 switch (len) {
63 case 1:
64 *val = in_8(cfg_data);
65 break;
66 case 2:
67 *val = in_le16(cfg_data);
68 break;
69 default:
70 *val = in_le32(cfg_data);
71 break;
72 }
73 return PCIBIOS_SUCCESSFUL;
74}
75
76static int
77indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
78 int len, u32 val)
79{
80 struct pci_controller *hose = pci_bus_to_host(bus);
81 volatile void __iomem *cfg_data;
82 u8 cfg_type = 0;
83 u32 bus_no, reg;
84
85 if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
86 if (bus->number != hose->first_busno)
87 return PCIBIOS_DEVICE_NOT_FOUND;
88 if (devfn != 0)
89 return PCIBIOS_DEVICE_NOT_FOUND;
90 }
91
92 if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)
93 if (bus->number != hose->first_busno)
94 cfg_type = 1;
95
96 bus_no = (bus->number == hose->first_busno) ?
97 hose->self_busno : bus->number;
98
99 if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)
100 reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
101 else
102 reg = offset & 0xfc;
103
104 if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)
105 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
106 (devfn << 8) | reg | cfg_type));
107 else
108 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
109 (devfn << 8) | reg | cfg_type));
110
111 /* surpress setting of PCI_PRIMARY_BUS */
112 if (hose->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
113 if ((offset == PCI_PRIMARY_BUS) &&
114 (bus->number == hose->first_busno))
115 val &= 0xffffff00;
116
117 /* Workaround for PCI_28 Errata in 440EPx/GRx */
118 if ((hose->indirect_type & INDIRECT_TYPE_BROKEN_MRM) &&
119 offset == PCI_CACHE_LINE_SIZE) {
120 val = 0;
121 }
122
123 /*
124 * Note: the caller has already checked that offset is
125 * suitably aligned and that len is 1, 2 or 4.
126 */
127 cfg_data = hose->cfg_data + (offset & 3);
128 switch (len) {
129 case 1:
130 out_8(cfg_data, val);
131 break;
132 case 2:
133 out_le16(cfg_data, val);
134 break;
135 default:
136 out_le32(cfg_data, val);
137 break;
138 }
139
140 return PCIBIOS_SUCCESSFUL;
141}
142
143static struct pci_ops indirect_pci_ops = {
144 .read = indirect_read_config,
145 .write = indirect_write_config,
146};
147
148void __init
149setup_indirect_pci(struct pci_controller *hose,
150 resource_size_t cfg_addr,
151 resource_size_t cfg_data, u32 flags)
152{
153 resource_size_t base = cfg_addr & PAGE_MASK;
154 void __iomem *mbase;
155
156 mbase = ioremap(base, PAGE_SIZE);
157 hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
158 if ((cfg_data & PAGE_MASK) != base)
159 mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
160 hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
161 hose->ops = &indirect_pci_ops;
162 hose->indirect_type = flags;
163}
diff --git a/arch/microblaze/pci/iomap.c b/arch/microblaze/pci/iomap.c
new file mode 100644
index 000000000000..3fbf16f4e16c
--- /dev/null
+++ b/arch/microblaze/pci/iomap.c
@@ -0,0 +1,39 @@
1/*
2 * ppc64 "iomap" interface implementation.
3 *
4 * (C) Copyright 2004 Linus Torvalds
5 */
6#include <linux/init.h>
7#include <linux/pci.h>
8#include <linux/mm.h>
9#include <asm/io.h>
10#include <asm/pci-bridge.h>
11
12void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max)
13{
14 resource_size_t start = pci_resource_start(dev, bar);
15 resource_size_t len = pci_resource_len(dev, bar);
16 unsigned long flags = pci_resource_flags(dev, bar);
17
18 if (!len)
19 return NULL;
20 if (max && len > max)
21 len = max;
22 if (flags & IORESOURCE_IO)
23 return ioport_map(start, len);
24 if (flags & IORESOURCE_MEM)
25 return ioremap(start, len);
26 /* What? */
27 return NULL;
28}
29EXPORT_SYMBOL(pci_iomap);
30
31void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
32{
33 if (isa_vaddr_is_ioport(addr))
34 return;
35 if (pcibios_vaddr_is_ioport(addr))
36 return;
37 iounmap(addr);
38}
39EXPORT_SYMBOL(pci_iounmap);
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 3d102dd87c9f..0b51857fbaf7 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_PPC) += setup-bus.o
48obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o 48obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
49obj-$(CONFIG_X86_VISWS) += setup-irq.o 49obj-$(CONFIG_X86_VISWS) += setup-irq.o
50obj-$(CONFIG_MN10300) += setup-bus.o 50obj-$(CONFIG_MN10300) += setup-bus.o
51obj-$(CONFIG_MICROBLAZE) += setup-bus.o
51 52
52# 53#
53# ACPI Related PCI FW Functions 54# ACPI Related PCI FW Functions
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-11 06:04:23 -0500