diff options
| -rw-r--r-- | drivers/net/s2io.c | 90 | ||||
| -rw-r--r-- | drivers/net/s2io.h | 7 |
2 files changed, 78 insertions, 19 deletions
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c index 7cc07c8e7076..cdf36745bb7b 100644 --- a/drivers/net/s2io.c +++ b/drivers/net/s2io.c | |||
| @@ -1372,6 +1372,16 @@ static int init_nic(struct s2io_nic *nic) | |||
| 1372 | } | 1372 | } |
| 1373 | } | 1373 | } |
| 1374 | 1374 | ||
| 1375 | /* Disable differentiated services steering logic */ | ||
| 1376 | for (i = 0; i < 64; i++) { | ||
| 1377 | if (rts_ds_steer(nic, i, 0) == FAILURE) { | ||
| 1378 | DBG_PRINT(ERR_DBG, "%s: failed rts ds steering", | ||
| 1379 | dev->name); | ||
| 1380 | DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i); | ||
| 1381 | return FAILURE; | ||
| 1382 | } | ||
| 1383 | } | ||
| 1384 | |||
| 1375 | /* Program statistics memory */ | 1385 | /* Program statistics memory */ |
| 1376 | writeq(mac_control->stats_mem_phy, &bar0->stat_addr); | 1386 | writeq(mac_control->stats_mem_phy, &bar0->stat_addr); |
| 1377 | 1387 | ||
| @@ -3195,26 +3205,37 @@ static void alarm_intr_handler(struct s2io_nic *nic) | |||
| 3195 | * SUCCESS on success and FAILURE on failure. | 3205 | * SUCCESS on success and FAILURE on failure. |
| 3196 | */ | 3206 | */ |
| 3197 | 3207 | ||
| 3198 | static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit) | 3208 | static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit, |
| 3209 | int bit_state) | ||
| 3199 | { | 3210 | { |
| 3200 | int ret = FAILURE, cnt = 0; | 3211 | int ret = FAILURE, cnt = 0, delay = 1; |
| 3201 | u64 val64; | 3212 | u64 val64; |
| 3202 | 3213 | ||
| 3203 | while (TRUE) { | 3214 | if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET)) |
| 3215 | return FAILURE; | ||
| 3216 | |||
| 3217 | do { | ||
| 3204 | val64 = readq(addr); | 3218 | val64 = readq(addr); |
| 3205 | if (!(val64 & busy_bit)) { | 3219 | if (bit_state == S2IO_BIT_RESET) { |
| 3206 | ret = SUCCESS; | 3220 | if (!(val64 & busy_bit)) { |
| 3207 | break; | 3221 | ret = SUCCESS; |
| 3222 | break; | ||
| 3223 | } | ||
| 3224 | } else { | ||
| 3225 | if (!(val64 & busy_bit)) { | ||
| 3226 | ret = SUCCESS; | ||
| 3227 | break; | ||
| 3228 | } | ||
| 3208 | } | 3229 | } |
| 3209 | 3230 | ||
| 3210 | if(in_interrupt()) | 3231 | if(in_interrupt()) |
| 3211 | mdelay(50); | 3232 | mdelay(delay); |
| 3212 | else | 3233 | else |
| 3213 | msleep(50); | 3234 | msleep(delay); |
| 3214 | 3235 | ||
| 3215 | if (cnt++ > 10) | 3236 | if (++cnt >= 10) |
| 3216 | break; | 3237 | delay = 50; |
| 3217 | } | 3238 | } while (cnt < 20); |
| 3218 | return ret; | 3239 | return ret; |
| 3219 | } | 3240 | } |
| 3220 | /* | 3241 | /* |
| @@ -4296,7 +4317,8 @@ static void s2io_set_multicast(struct net_device *dev) | |||
| 4296 | writeq(val64, &bar0->rmac_addr_cmd_mem); | 4317 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
| 4297 | /* Wait till command completes */ | 4318 | /* Wait till command completes */ |
| 4298 | wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, | 4319 | wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
| 4299 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING); | 4320 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
| 4321 | S2IO_BIT_RESET); | ||
| 4300 | 4322 | ||
| 4301 | sp->m_cast_flg = 1; | 4323 | sp->m_cast_flg = 1; |
| 4302 | sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET; | 4324 | sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET; |
| @@ -4312,7 +4334,8 @@ static void s2io_set_multicast(struct net_device *dev) | |||
| 4312 | writeq(val64, &bar0->rmac_addr_cmd_mem); | 4334 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
| 4313 | /* Wait till command completes */ | 4335 | /* Wait till command completes */ |
| 4314 | wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, | 4336 | wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
| 4315 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING); | 4337 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
| 4338 | S2IO_BIT_RESET); | ||
| 4316 | 4339 | ||
| 4317 | sp->m_cast_flg = 0; | 4340 | sp->m_cast_flg = 0; |
| 4318 | sp->all_multi_pos = 0; | 4341 | sp->all_multi_pos = 0; |
| @@ -4378,7 +4401,8 @@ static void s2io_set_multicast(struct net_device *dev) | |||
| 4378 | 4401 | ||
| 4379 | /* Wait for command completes */ | 4402 | /* Wait for command completes */ |
| 4380 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, | 4403 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
| 4381 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) { | 4404 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
| 4405 | S2IO_BIT_RESET)) { | ||
| 4382 | DBG_PRINT(ERR_DBG, "%s: Adding ", | 4406 | DBG_PRINT(ERR_DBG, "%s: Adding ", |
| 4383 | dev->name); | 4407 | dev->name); |
| 4384 | DBG_PRINT(ERR_DBG, "Multicasts failed\n"); | 4408 | DBG_PRINT(ERR_DBG, "Multicasts failed\n"); |
| @@ -4409,7 +4433,8 @@ static void s2io_set_multicast(struct net_device *dev) | |||
| 4409 | 4433 | ||
| 4410 | /* Wait for command completes */ | 4434 | /* Wait for command completes */ |
| 4411 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, | 4435 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
| 4412 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) { | 4436 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
| 4437 | S2IO_BIT_RESET)) { | ||
| 4413 | DBG_PRINT(ERR_DBG, "%s: Adding ", | 4438 | DBG_PRINT(ERR_DBG, "%s: Adding ", |
| 4414 | dev->name); | 4439 | dev->name); |
| 4415 | DBG_PRINT(ERR_DBG, "Multicasts failed\n"); | 4440 | DBG_PRINT(ERR_DBG, "Multicasts failed\n"); |
| @@ -4455,7 +4480,7 @@ static int s2io_set_mac_addr(struct net_device *dev, u8 * addr) | |||
| 4455 | writeq(val64, &bar0->rmac_addr_cmd_mem); | 4480 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
| 4456 | /* Wait till command completes */ | 4481 | /* Wait till command completes */ |
| 4457 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, | 4482 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
| 4458 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) { | 4483 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET)) { |
| 4459 | DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name); | 4484 | DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name); |
| 4460 | return FAILURE; | 4485 | return FAILURE; |
| 4461 | } | 4486 | } |
| @@ -6736,6 +6761,37 @@ static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type) | |||
| 6736 | } | 6761 | } |
| 6737 | 6762 | ||
| 6738 | /** | 6763 | /** |
| 6764 | * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS | ||
| 6765 | * or Traffic class respectively. | ||
| 6766 | * @nic: device peivate variable | ||
| 6767 | * Description: The function configures the receive steering to | ||
| 6768 | * desired receive ring. | ||
| 6769 | * Return Value: SUCCESS on success and | ||
| 6770 | * '-1' on failure (endian settings incorrect). | ||
| 6771 | */ | ||
| 6772 | static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring) | ||
| 6773 | { | ||
| 6774 | struct XENA_dev_config __iomem *bar0 = nic->bar0; | ||
| 6775 | register u64 val64 = 0; | ||
| 6776 | |||
| 6777 | if (ds_codepoint > 63) | ||
| 6778 | return FAILURE; | ||
| 6779 | |||
| 6780 | val64 = RTS_DS_MEM_DATA(ring); | ||
| 6781 | writeq(val64, &bar0->rts_ds_mem_data); | ||
| 6782 | |||
| 6783 | val64 = RTS_DS_MEM_CTRL_WE | | ||
| 6784 | RTS_DS_MEM_CTRL_STROBE_NEW_CMD | | ||
| 6785 | RTS_DS_MEM_CTRL_OFFSET(ds_codepoint); | ||
| 6786 | |||
| 6787 | writeq(val64, &bar0->rts_ds_mem_ctrl); | ||
| 6788 | |||
| 6789 | return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl, | ||
| 6790 | RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED, | ||
| 6791 | S2IO_BIT_RESET); | ||
| 6792 | } | ||
| 6793 | |||
| 6794 | /** | ||
| 6739 | * s2io_init_nic - Initialization of the adapter . | 6795 | * s2io_init_nic - Initialization of the adapter . |
| 6740 | * @pdev : structure containing the PCI related information of the device. | 6796 | * @pdev : structure containing the PCI related information of the device. |
| 6741 | * @pre: List of PCI devices supported by the driver listed in s2io_tbl. | 6797 | * @pre: List of PCI devices supported by the driver listed in s2io_tbl. |
| @@ -7029,7 +7085,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) | |||
| 7029 | RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET); | 7085 | RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET); |
| 7030 | writeq(val64, &bar0->rmac_addr_cmd_mem); | 7086 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
| 7031 | wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, | 7087 | wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
| 7032 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING); | 7088 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET); |
| 7033 | tmp64 = readq(&bar0->rmac_addr_data0_mem); | 7089 | tmp64 = readq(&bar0->rmac_addr_data0_mem); |
| 7034 | mac_down = (u32) tmp64; | 7090 | mac_down = (u32) tmp64; |
| 7035 | mac_up = (u32) (tmp64 >> 32); | 7091 | mac_up = (u32) (tmp64 >> 32); |
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h index 0de0c65f945a..d23a50f3b70d 100644 --- a/drivers/net/s2io.h +++ b/drivers/net/s2io.h | |||
| @@ -32,7 +32,8 @@ | |||
| 32 | #define FAILURE -1 | 32 | #define FAILURE -1 |
| 33 | #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL | 33 | #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL |
| 34 | #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100 | 34 | #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100 |
| 35 | 35 | #define S2IO_BIT_RESET 1 | |
| 36 | #define S2IO_BIT_SET 2 | ||
| 36 | #define CHECKBIT(value, nbit) (value & (1 << nbit)) | 37 | #define CHECKBIT(value, nbit) (value & (1 << nbit)) |
| 37 | 38 | ||
| 38 | /* Maximum time to flicker LED when asked to identify NIC using ethtool */ | 39 | /* Maximum time to flicker LED when asked to identify NIC using ethtool */ |
| @@ -1005,7 +1006,8 @@ static int s2io_set_swapper(struct s2io_nic * sp); | |||
| 1005 | static void s2io_card_down(struct s2io_nic *nic); | 1006 | static void s2io_card_down(struct s2io_nic *nic); |
| 1006 | static int s2io_card_up(struct s2io_nic *nic); | 1007 | static int s2io_card_up(struct s2io_nic *nic); |
| 1007 | static int get_xena_rev_id(struct pci_dev *pdev); | 1008 | static int get_xena_rev_id(struct pci_dev *pdev); |
| 1008 | static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit); | 1009 | static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit, |
| 1010 | int bit_state); | ||
| 1009 | static int s2io_add_isr(struct s2io_nic * sp); | 1011 | static int s2io_add_isr(struct s2io_nic * sp); |
| 1010 | static void s2io_rem_isr(struct s2io_nic * sp); | 1012 | static void s2io_rem_isr(struct s2io_nic * sp); |
| 1011 | 1013 | ||
| @@ -1019,6 +1021,7 @@ static void queue_rx_frame(struct sk_buff *skb); | |||
| 1019 | static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro); | 1021 | static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro); |
| 1020 | static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro, | 1022 | static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro, |
| 1021 | struct sk_buff *skb, u32 tcp_len); | 1023 | struct sk_buff *skb, u32 tcp_len); |
| 1024 | static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring); | ||
| 1022 | 1025 | ||
| 1023 | #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size | 1026 | #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size |
| 1024 | #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size | 1027 | #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size |
