diff options
| -rw-r--r-- | include/asm-mips/mach-au1x00/au1000.h | 614 | ||||
| -rw-r--r-- | include/asm-mips/mach-db1x00/db1200.h | 49 | ||||
| -rw-r--r-- | include/asm-mips/mach-pb1x00/pb1200.h | 52 |
3 files changed, 373 insertions, 342 deletions
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index a2a5168a443b..3bdce9126f16 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h | |||
| @@ -40,7 +40,9 @@ | |||
| 40 | 40 | ||
| 41 | #include <linux/delay.h> | 41 | #include <linux/delay.h> |
| 42 | #include <linux/types.h> | 42 | #include <linux/types.h> |
| 43 | |||
| 43 | #include <asm/io.h> | 44 | #include <asm/io.h> |
| 45 | #include <asm/irq.h> | ||
| 44 | 46 | ||
| 45 | /* cpu pipeline flush */ | 47 | /* cpu pipeline flush */ |
| 46 | void static inline au_sync(void) | 48 | void static inline au_sync(void) |
| @@ -523,63 +525,67 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; | |||
| 523 | /* Interrupt Numbers */ | 525 | /* Interrupt Numbers */ |
| 524 | /* Au1000 */ | 526 | /* Au1000 */ |
| 525 | #ifdef CONFIG_SOC_AU1000 | 527 | #ifdef CONFIG_SOC_AU1000 |
| 526 | #define AU1000_UART0_INT 0 | 528 | enum soc_au1000_ints { |
| 527 | #define AU1000_UART1_INT 1 /* au1000 */ | 529 | AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE, |
| 528 | #define AU1000_UART2_INT 2 /* au1000 */ | 530 | AU1000_UART0_INT = AU1000_FIRST_INT, |
| 529 | #define AU1000_UART3_INT 3 | 531 | AU1000_UART1_INT, /* au1000 */ |
| 530 | #define AU1000_SSI0_INT 4 /* au1000 */ | 532 | AU1000_UART2_INT, /* au1000 */ |
| 531 | #define AU1000_SSI1_INT 5 /* au1000 */ | 533 | AU1000_UART3_INT, |
| 532 | #define AU1000_DMA_INT_BASE 6 | 534 | AU1000_SSI0_INT, /* au1000 */ |
| 533 | #define AU1000_TOY_INT 14 | 535 | AU1000_SSI1_INT, /* au1000 */ |
| 534 | #define AU1000_TOY_MATCH0_INT 15 | 536 | AU1000_DMA_INT_BASE, |
| 535 | #define AU1000_TOY_MATCH1_INT 16 | 537 | |
| 536 | #define AU1000_TOY_MATCH2_INT 17 | 538 | AU1000_TOY_INT = AU1000_FIRST_INT + 14, |
| 537 | #define AU1000_RTC_INT 18 | 539 | AU1000_TOY_MATCH0_INT, |
| 538 | #define AU1000_RTC_MATCH0_INT 19 | 540 | AU1000_TOY_MATCH1_INT, |
| 539 | #define AU1000_RTC_MATCH1_INT 20 | 541 | AU1000_TOY_MATCH2_INT, |
| 540 | #define AU1000_RTC_MATCH2_INT 21 | 542 | AU1000_RTC_INT, |
| 541 | #define AU1000_IRDA_TX_INT 22 /* au1000 */ | 543 | AU1000_RTC_MATCH0_INT, |
| 542 | #define AU1000_IRDA_RX_INT 23 /* au1000 */ | 544 | AU1000_RTC_MATCH1_INT, |
| 543 | #define AU1000_USB_DEV_REQ_INT 24 | 545 | AU1000_RTC_MATCH2_INT, |
| 544 | #define AU1000_USB_DEV_SUS_INT 25 | 546 | AU1000_IRDA_TX_INT, /* au1000 */ |
| 545 | #define AU1000_USB_HOST_INT 26 | 547 | AU1000_IRDA_RX_INT, /* au1000 */ |
| 546 | #define AU1000_ACSYNC_INT 27 | 548 | AU1000_USB_DEV_REQ_INT, |
| 547 | #define AU1000_MAC0_DMA_INT 28 | 549 | AU1000_USB_DEV_SUS_INT, |
| 548 | #define AU1000_MAC1_DMA_INT 29 | 550 | AU1000_USB_HOST_INT, |
| 549 | #define AU1000_I2S_UO_INT 30 /* au1000 */ | 551 | AU1000_ACSYNC_INT, |
| 550 | #define AU1000_AC97C_INT 31 | 552 | AU1000_MAC0_DMA_INT, |
| 551 | #define AU1000_GPIO_0 32 | 553 | AU1000_MAC1_DMA_INT, |
| 552 | #define AU1000_GPIO_1 33 | 554 | AU1000_I2S_UO_INT, /* au1000 */ |
| 553 | #define AU1000_GPIO_2 34 | 555 | AU1000_AC97C_INT, |
| 554 | #define AU1000_GPIO_3 35 | 556 | AU1000_GPIO_0, |
| 555 | #define AU1000_GPIO_4 36 | 557 | AU1000_GPIO_1, |
| 556 | #define AU1000_GPIO_5 37 | 558 | AU1000_GPIO_2, |
| 557 | #define AU1000_GPIO_6 38 | 559 | AU1000_GPIO_3, |
| 558 | #define AU1000_GPIO_7 39 | 560 | AU1000_GPIO_4, |
| 559 | #define AU1000_GPIO_8 40 | 561 | AU1000_GPIO_5, |
| 560 | #define AU1000_GPIO_9 41 | 562 | AU1000_GPIO_6, |
| 561 | #define AU1000_GPIO_10 42 | 563 | AU1000_GPIO_7, |
| 562 | #define AU1000_GPIO_11 43 | 564 | AU1000_GPIO_8, |
| 563 | #define AU1000_GPIO_12 44 | 565 | AU1000_GPIO_9, |
| 564 | #define AU1000_GPIO_13 45 | 566 | AU1000_GPIO_10, |
| 565 | #define AU1000_GPIO_14 46 | 567 | AU1000_GPIO_11, |
| 566 | #define AU1000_GPIO_15 47 | 568 | AU1000_GPIO_12, |
| 567 | #define AU1000_GPIO_16 48 | 569 | AU1000_GPIO_13, |
| 568 | #define AU1000_GPIO_17 49 | 570 | AU1000_GPIO_14, |
| 569 | #define AU1000_GPIO_18 50 | 571 | AU1000_GPIO_15, |
| 570 | #define AU1000_GPIO_19 51 | 572 | AU1000_GPIO_16, |
| 571 | #define AU1000_GPIO_20 52 | 573 | AU1000_GPIO_17, |
| 572 | #define AU1000_GPIO_21 53 | 574 | AU1000_GPIO_18, |
| 573 | #define AU1000_GPIO_22 54 | 575 | AU1000_GPIO_19, |
| 574 | #define AU1000_GPIO_23 55 | 576 | AU1000_GPIO_20, |
| 575 | #define AU1000_GPIO_24 56 | 577 | AU1000_GPIO_21, |
| 576 | #define AU1000_GPIO_25 57 | 578 | AU1000_GPIO_22, |
| 577 | #define AU1000_GPIO_26 58 | 579 | AU1000_GPIO_23, |
| 578 | #define AU1000_GPIO_27 59 | 580 | AU1000_GPIO_24, |
| 579 | #define AU1000_GPIO_28 60 | 581 | AU1000_GPIO_25, |
| 580 | #define AU1000_GPIO_29 61 | 582 | AU1000_GPIO_26, |
| 581 | #define AU1000_GPIO_30 62 | 583 | AU1000_GPIO_27, |
| 582 | #define AU1000_GPIO_31 63 | 584 | AU1000_GPIO_28, |
| 585 | AU1000_GPIO_29, | ||
| 586 | AU1000_GPIO_30, | ||
| 587 | AU1000_GPIO_31, | ||
| 588 | }; | ||
| 583 | 589 | ||
| 584 | #define UART0_ADDR 0xB1100000 | 590 | #define UART0_ADDR 0xB1100000 |
| 585 | #define UART1_ADDR 0xB1200000 | 591 | #define UART1_ADDR 0xB1200000 |
| @@ -598,61 +604,65 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; | |||
| 598 | 604 | ||
| 599 | /* Au1500 */ | 605 | /* Au1500 */ |
| 600 | #ifdef CONFIG_SOC_AU1500 | 606 | #ifdef CONFIG_SOC_AU1500 |
| 601 | #define AU1500_UART0_INT 0 | 607 | enum soc_au1500_ints { |
| 602 | #define AU1000_PCI_INTA 1 /* au1500 */ | 608 | AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE, |
| 603 | #define AU1000_PCI_INTB 2 /* au1500 */ | 609 | AU1500_UART0_INT = AU1500_FIRST_INT, |
| 604 | #define AU1500_UART3_INT 3 | 610 | AU1000_PCI_INTA, /* au1500 */ |
| 605 | #define AU1000_PCI_INTC 4 /* au1500 */ | 611 | AU1000_PCI_INTB, /* au1500 */ |
| 606 | #define AU1000_PCI_INTD 5 /* au1500 */ | 612 | AU1500_UART3_INT, |
| 607 | #define AU1000_DMA_INT_BASE 6 | 613 | AU1000_PCI_INTC, /* au1500 */ |
| 608 | #define AU1000_TOY_INT 14 | 614 | AU1000_PCI_INTD, /* au1500 */ |
| 609 | #define AU1000_TOY_MATCH0_INT 15 | 615 | AU1000_DMA_INT_BASE, |
| 610 | #define AU1000_TOY_MATCH1_INT 16 | 616 | |
| 611 | #define AU1000_TOY_MATCH2_INT 17 | 617 | AU1000_TOY_INT = AU1500_FIRST_INT + 14, |
| 612 | #define AU1000_RTC_INT 18 | 618 | AU1000_TOY_MATCH0_INT, |
| 613 | #define AU1000_RTC_MATCH0_INT 19 | 619 | AU1000_TOY_MATCH1_INT, |
| 614 | #define AU1000_RTC_MATCH1_INT 20 | 620 | AU1000_TOY_MATCH2_INT, |
| 615 | #define AU1000_RTC_MATCH2_INT 21 | 621 | AU1000_RTC_INT, |
| 616 | #define AU1500_PCI_ERR_INT 22 | 622 | AU1000_RTC_MATCH0_INT, |
| 617 | #define AU1000_USB_DEV_REQ_INT 24 | 623 | AU1000_RTC_MATCH1_INT, |
| 618 | #define AU1000_USB_DEV_SUS_INT 25 | 624 | AU1000_RTC_MATCH2_INT, |
| 619 | #define AU1000_USB_HOST_INT 26 | 625 | AU1500_PCI_ERR_INT, |
| 620 | #define AU1000_ACSYNC_INT 27 | 626 | AU1000_USB_DEV_REQ_INT, |
| 621 | #define AU1500_MAC0_DMA_INT 28 | 627 | AU1000_USB_DEV_SUS_INT, |
| 622 | #define AU1500_MAC1_DMA_INT 29 | 628 | AU1000_USB_HOST_INT, |
| 623 | #define AU1000_AC97C_INT 31 | 629 | AU1000_ACSYNC_INT, |
| 624 | #define AU1000_GPIO_0 32 | 630 | AU1500_MAC0_DMA_INT, |
| 625 | #define AU1000_GPIO_1 33 | 631 | AU1500_MAC1_DMA_INT, |
| 626 | #define AU1000_GPIO_2 34 | 632 | AU1000_AC97C_INT = AU1500_FIRST_INT + 31, |
| 627 | #define AU1000_GPIO_3 35 | 633 | AU1000_GPIO_0, |
| 628 | #define AU1000_GPIO_4 36 | 634 | AU1000_GPIO_1, |
| 629 | #define AU1000_GPIO_5 37 | 635 | AU1000_GPIO_2, |
| 630 | #define AU1000_GPIO_6 38 | 636 | AU1000_GPIO_3, |
| 631 | #define AU1000_GPIO_7 39 | 637 | AU1000_GPIO_4, |
| 632 | #define AU1000_GPIO_8 40 | 638 | AU1000_GPIO_5, |
| 633 | #define AU1000_GPIO_9 41 | 639 | AU1000_GPIO_6, |
| 634 | #define AU1000_GPIO_10 42 | 640 | AU1000_GPIO_7, |
| 635 | #define AU1000_GPIO_11 43 | 641 | AU1000_GPIO_8, |
| 636 | #define AU1000_GPIO_12 44 | 642 | AU1000_GPIO_9, |
| 637 | #define AU1000_GPIO_13 45 | 643 | AU1000_GPIO_10, |
| 638 | #define AU1000_GPIO_14 46 | 644 | AU1000_GPIO_11, |
| 639 | #define AU1000_GPIO_15 47 | 645 | AU1000_GPIO_12, |
| 640 | #define AU1500_GPIO_200 48 | 646 | AU1000_GPIO_13, |
| 641 | #define AU1500_GPIO_201 49 | 647 | AU1000_GPIO_14, |
| 642 | #define AU1500_GPIO_202 50 | 648 | AU1000_GPIO_15, |
| 643 | #define AU1500_GPIO_203 51 | 649 | AU1500_GPIO_200, |
| 644 | #define AU1500_GPIO_20 52 | 650 | AU1500_GPIO_201, |
| 645 | #define AU1500_GPIO_204 53 | 651 | AU1500_GPIO_202, |
| 646 | #define AU1500_GPIO_205 54 | 652 | AU1500_GPIO_203, |
| 647 | #define AU1500_GPIO_23 55 | 653 | AU1500_GPIO_20, |
| 648 | #define AU1500_GPIO_24 56 | 654 | AU1500_GPIO_204, |
| 649 | #define AU1500_GPIO_25 57 | 655 | AU1500_GPIO_205, |
| 650 | #define AU1500_GPIO_26 58 | 656 | AU1500_GPIO_23, |
| 651 | #define AU1500_GPIO_27 59 | 657 | AU1500_GPIO_24, |
| 652 | #define AU1500_GPIO_28 60 | 658 | AU1500_GPIO_25, |
| 653 | #define AU1500_GPIO_206 61 | 659 | AU1500_GPIO_26, |
| 654 | #define AU1500_GPIO_207 62 | 660 | AU1500_GPIO_27, |
| 655 | #define AU1500_GPIO_208_215 63 | 661 | AU1500_GPIO_28, |
| 662 | AU1500_GPIO_206, | ||
| 663 | AU1500_GPIO_207, | ||
| 664 | AU1500_GPIO_208_215, | ||
| 665 | }; | ||
| 656 | 666 | ||
| 657 | /* shortcuts */ | 667 | /* shortcuts */ |
| 658 | #define INTA AU1000_PCI_INTA | 668 | #define INTA AU1000_PCI_INTA |
| @@ -675,63 +685,67 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; | |||
| 675 | 685 | ||
| 676 | /* Au1100 */ | 686 | /* Au1100 */ |
| 677 | #ifdef CONFIG_SOC_AU1100 | 687 | #ifdef CONFIG_SOC_AU1100 |
| 678 | #define AU1100_UART0_INT 0 | 688 | enum soc_au1100_ints { |
| 679 | #define AU1100_UART1_INT 1 | 689 | AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE, |
| 680 | #define AU1100_SD_INT 2 | 690 | AU1100_UART0_INT, |
| 681 | #define AU1100_UART3_INT 3 | 691 | AU1100_UART1_INT, |
| 682 | #define AU1000_SSI0_INT 4 | 692 | AU1100_SD_INT, |
| 683 | #define AU1000_SSI1_INT 5 | 693 | AU1100_UART3_INT, |
| 684 | #define AU1000_DMA_INT_BASE 6 | 694 | AU1000_SSI0_INT, |
| 685 | #define AU1000_TOY_INT 14 | 695 | AU1000_SSI1_INT, |
| 686 | #define AU1000_TOY_MATCH0_INT 15 | 696 | AU1000_DMA_INT_BASE, |
| 687 | #define AU1000_TOY_MATCH1_INT 16 | 697 | |
| 688 | #define AU1000_TOY_MATCH2_INT 17 | 698 | AU1000_TOY_INT = AU1100_FIRST_INT + 14, |
| 689 | #define AU1000_RTC_INT 18 | 699 | AU1000_TOY_MATCH0_INT, |
| 690 | #define AU1000_RTC_MATCH0_INT 19 | 700 | AU1000_TOY_MATCH1_INT, |
| 691 | #define AU1000_RTC_MATCH1_INT 20 | 701 | AU1000_TOY_MATCH2_INT, |
| 692 | #define AU1000_RTC_MATCH2_INT 21 | 702 | AU1000_RTC_INT, |
| 693 | #define AU1000_IRDA_TX_INT 22 | 703 | AU1000_RTC_MATCH0_INT, |
| 694 | #define AU1000_IRDA_RX_INT 23 | 704 | AU1000_RTC_MATCH1_INT, |
| 695 | #define AU1000_USB_DEV_REQ_INT 24 | 705 | AU1000_RTC_MATCH2_INT, |
| 696 | #define AU1000_USB_DEV_SUS_INT 25 | 706 | AU1000_IRDA_TX_INT, |
| 697 | #define AU1000_USB_HOST_INT 26 | 707 | AU1000_IRDA_RX_INT, |
| 698 | #define AU1000_ACSYNC_INT 27 | 708 | AU1000_USB_DEV_REQ_INT, |
| 699 | #define AU1100_MAC0_DMA_INT 28 | 709 | AU1000_USB_DEV_SUS_INT, |
| 700 | #define AU1100_GPIO_208_215 29 | 710 | AU1000_USB_HOST_INT, |
| 701 | #define AU1100_LCD_INT 30 | 711 | AU1000_ACSYNC_INT, |
| 702 | #define AU1000_AC97C_INT 31 | 712 | AU1100_MAC0_DMA_INT, |
| 703 | #define AU1000_GPIO_0 32 | 713 | AU1100_GPIO_208_215, |
| 704 | #define AU1000_GPIO_1 33 | 714 | AU1100_LCD_INT, |
| 705 | #define AU1000_GPIO_2 34 | 715 | AU1000_AC97C_INT, |
| 706 | #define AU1000_GPIO_3 35 | 716 | AU1000_GPIO_0, |
| 707 | #define AU1000_GPIO_4 36 | 717 | AU1000_GPIO_1, |
| 708 | #define AU1000_GPIO_5 37 | 718 | AU1000_GPIO_2, |
| 709 | #define AU1000_GPIO_6 38 | 719 | AU1000_GPIO_3, |
| 710 | #define AU1000_GPIO_7 39 | 720 | AU1000_GPIO_4, |
| 711 | #define AU1000_GPIO_8 40 | 721 | AU1000_GPIO_5, |
| 712 | #define AU1000_GPIO_9 41 | 722 | AU1000_GPIO_6, |
| 713 | #define AU1000_GPIO_10 42 | 723 | AU1000_GPIO_7, |
| 714 | #define AU1000_GPIO_11 43 | 724 | AU1000_GPIO_8, |
| 715 | #define AU1000_GPIO_12 44 | 725 | AU1000_GPIO_9, |
| 716 | #define AU1000_GPIO_13 45 | 726 | AU1000_GPIO_10, |
| 717 | #define AU1000_GPIO_14 46 | 727 | AU1000_GPIO_11, |
| 718 | #define AU1000_GPIO_15 47 | 728 | AU1000_GPIO_12, |
| 719 | #define AU1000_GPIO_16 48 | 729 | AU1000_GPIO_13, |
| 720 | #define AU1000_GPIO_17 49 | 730 | AU1000_GPIO_14, |
| 721 | #define AU1000_GPIO_18 50 | 731 | AU1000_GPIO_15, |
| 722 | #define AU1000_GPIO_19 51 | 732 | AU1000_GPIO_16, |
| 723 | #define AU1000_GPIO_20 52 | 733 | AU1000_GPIO_17, |
| 724 | #define AU1000_GPIO_21 53 | 734 | AU1000_GPIO_18, |
| 725 | #define AU1000_GPIO_22 54 | 735 | AU1000_GPIO_19, |
| 726 | #define AU1000_GPIO_23 55 | 736 | AU1000_GPIO_20, |
| 727 | #define AU1000_GPIO_24 56 | 737 | AU1000_GPIO_21, |
| 728 | #define AU1000_GPIO_25 57 | 738 | AU1000_GPIO_22, |
| 729 | #define AU1000_GPIO_26 58 | 739 | AU1000_GPIO_23, |
| 730 | #define AU1000_GPIO_27 59 | 740 | AU1000_GPIO_24, |
| 731 | #define AU1000_GPIO_28 60 | 741 | AU1000_GPIO_25, |
| 732 | #define AU1000_GPIO_29 61 | 742 | AU1000_GPIO_26, |
| 733 | #define AU1000_GPIO_30 62 | 743 | AU1000_GPIO_27, |
| 734 | #define AU1000_GPIO_31 63 | 744 | AU1000_GPIO_28, |
| 745 | AU1000_GPIO_29, | ||
| 746 | AU1000_GPIO_30, | ||
| 747 | AU1000_GPIO_31, | ||
| 748 | }; | ||
| 735 | 749 | ||
| 736 | #define UART0_ADDR 0xB1100000 | 750 | #define UART0_ADDR 0xB1100000 |
| 737 | #define UART1_ADDR 0xB1200000 | 751 | #define UART1_ADDR 0xB1200000 |
| @@ -746,69 +760,73 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; | |||
| 746 | #endif /* CONFIG_SOC_AU1100 */ | 760 | #endif /* CONFIG_SOC_AU1100 */ |
| 747 | 761 | ||
| 748 | #ifdef CONFIG_SOC_AU1550 | 762 | #ifdef CONFIG_SOC_AU1550 |
| 749 | #define AU1550_UART0_INT 0 | 763 | enum soc_au1550_ints { |
| 750 | #define AU1550_PCI_INTA 1 | 764 | AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE, |
| 751 | #define AU1550_PCI_INTB 2 | 765 | AU1550_UART0_INT = AU1550_FIRST_INT, |
| 752 | #define AU1550_DDMA_INT 3 | 766 | AU1550_PCI_INTA, |
| 753 | #define AU1550_CRYPTO_INT 4 | 767 | AU1550_PCI_INTB, |
| 754 | #define AU1550_PCI_INTC 5 | 768 | AU1550_DDMA_INT, |
| 755 | #define AU1550_PCI_INTD 6 | 769 | AU1550_CRYPTO_INT, |
| 756 | #define AU1550_PCI_RST_INT 7 | 770 | AU1550_PCI_INTC, |
| 757 | #define AU1550_UART1_INT 8 | 771 | AU1550_PCI_INTD, |
| 758 | #define AU1550_UART3_INT 9 | 772 | AU1550_PCI_RST_INT, |
| 759 | #define AU1550_PSC0_INT 10 | 773 | AU1550_UART1_INT, |
| 760 | #define AU1550_PSC1_INT 11 | 774 | AU1550_UART3_INT, |
| 761 | #define AU1550_PSC2_INT 12 | 775 | AU1550_PSC0_INT, |
| 762 | #define AU1550_PSC3_INT 13 | 776 | AU1550_PSC1_INT, |
| 763 | #define AU1000_TOY_INT 14 | 777 | AU1550_PSC2_INT, |
| 764 | #define AU1000_TOY_MATCH0_INT 15 | 778 | AU1550_PSC3_INT, |
| 765 | #define AU1000_TOY_MATCH1_INT 16 | 779 | AU1000_TOY_INT, |
| 766 | #define AU1000_TOY_MATCH2_INT 17 | 780 | AU1000_TOY_MATCH0_INT, |
| 767 | #define AU1000_RTC_INT 18 | 781 | AU1000_TOY_MATCH1_INT, |
| 768 | #define AU1000_RTC_MATCH0_INT 19 | 782 | AU1000_TOY_MATCH2_INT, |
| 769 | #define AU1000_RTC_MATCH1_INT 20 | 783 | AU1000_RTC_INT, |
| 770 | #define AU1000_RTC_MATCH2_INT 21 | 784 | AU1000_RTC_MATCH0_INT, |
| 771 | #define AU1550_NAND_INT 23 | 785 | AU1000_RTC_MATCH1_INT, |
| 772 | #define AU1550_USB_DEV_REQ_INT 24 | 786 | AU1000_RTC_MATCH2_INT, |
| 773 | #define AU1550_USB_DEV_SUS_INT 25 | 787 | |
| 774 | #define AU1550_USB_HOST_INT 26 | 788 | AU1550_NAND_INT = AU1550_FIRST_INT + 23, |
| 775 | #define AU1000_USB_DEV_REQ_INT AU1550_USB_DEV_REQ_INT | 789 | AU1550_USB_DEV_REQ_INT, |
| 776 | #define AU1000_USB_DEV_SUS_INT AU1550_USB_DEV_SUS_INT | 790 | AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT, |
| 777 | #define AU1000_USB_HOST_INT AU1550_USB_HOST_INT | 791 | AU1550_USB_DEV_SUS_INT, |
| 778 | #define AU1550_MAC0_DMA_INT 27 | 792 | AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT, |
| 779 | #define AU1550_MAC1_DMA_INT 28 | 793 | AU1550_USB_HOST_INT, |
| 780 | #define AU1000_GPIO_0 32 | 794 | AU1000_USB_HOST_INT = AU1550_USB_HOST_INT, |
| 781 | #define AU1000_GPIO_1 33 | 795 | AU1550_MAC0_DMA_INT, |
| 782 | #define AU1000_GPIO_2 34 | 796 | AU1550_MAC1_DMA_INT, |
| 783 | #define AU1000_GPIO_3 35 | 797 | AU1000_GPIO_0 = AU1550_FIRST_INT + 32, |
| 784 | #define AU1000_GPIO_4 36 | 798 | AU1000_GPIO_1, |
| 785 | #define AU1000_GPIO_5 37 | 799 | AU1000_GPIO_2, |
| 786 | #define AU1000_GPIO_6 38 | 800 | AU1000_GPIO_3, |
| 787 | #define AU1000_GPIO_7 39 | 801 | AU1000_GPIO_4, |
| 788 | #define AU1000_GPIO_8 40 | 802 | AU1000_GPIO_5, |
| 789 | #define AU1000_GPIO_9 41 | 803 | AU1000_GPIO_6, |
| 790 | #define AU1000_GPIO_10 42 | 804 | AU1000_GPIO_7, |
| 791 | #define AU1000_GPIO_11 43 | 805 | AU1000_GPIO_8, |
| 792 | #define AU1000_GPIO_12 44 | 806 | AU1000_GPIO_9, |
| 793 | #define AU1000_GPIO_13 45 | 807 | AU1000_GPIO_10, |
| 794 | #define AU1000_GPIO_14 46 | 808 | AU1000_GPIO_11, |
| 795 | #define AU1000_GPIO_15 47 | 809 | AU1000_GPIO_12, |
| 796 | #define AU1550_GPIO_200 48 | 810 | AU1000_GPIO_13, |
| 797 | #define AU1500_GPIO_201_205 49 // Logical or of GPIO201:205 | 811 | AU1000_GPIO_14, |
| 798 | #define AU1500_GPIO_16 50 | 812 | AU1000_GPIO_15, |
| 799 | #define AU1500_GPIO_17 51 | 813 | AU1550_GPIO_200, |
| 800 | #define AU1500_GPIO_20 52 | 814 | AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */ |
| 801 | #define AU1500_GPIO_21 53 | 815 | AU1500_GPIO_16, |
| 802 | #define AU1500_GPIO_22 54 | 816 | AU1500_GPIO_17, |
| 803 | #define AU1500_GPIO_23 55 | 817 | AU1500_GPIO_20, |
| 804 | #define AU1500_GPIO_24 56 | 818 | AU1500_GPIO_21, |
| 805 | #define AU1500_GPIO_25 57 | 819 | AU1500_GPIO_22, |
| 806 | #define AU1500_GPIO_26 58 | 820 | AU1500_GPIO_23, |
| 807 | #define AU1500_GPIO_27 59 | 821 | AU1500_GPIO_24, |
| 808 | #define AU1500_GPIO_28 60 | 822 | AU1500_GPIO_25, |
| 809 | #define AU1500_GPIO_206 61 | 823 | AU1500_GPIO_26, |
| 810 | #define AU1500_GPIO_207 62 | 824 | AU1500_GPIO_27, |
| 811 | #define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218 | 825 | AU1500_GPIO_28, |
| 826 | AU1500_GPIO_206, | ||
| 827 | AU1500_GPIO_207, | ||
| 828 | AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */ | ||
| 829 | }; | ||
| 812 | 830 | ||
| 813 | /* shortcuts */ | 831 | /* shortcuts */ |
| 814 | #define INTA AU1550_PCI_INTA | 832 | #define INTA AU1550_PCI_INTA |
| @@ -832,70 +850,74 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; | |||
| 832 | #endif /* CONFIG_SOC_AU1550 */ | 850 | #endif /* CONFIG_SOC_AU1550 */ |
| 833 | 851 | ||
| 834 | #ifdef CONFIG_SOC_AU1200 | 852 | #ifdef CONFIG_SOC_AU1200 |
| 835 | #define AU1200_UART0_INT 0 | 853 | enum soc_au1200_ints { |
| 836 | #define AU1200_SWT_INT 1 | 854 | AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE, |
| 837 | #define AU1200_SD_INT 2 | 855 | AU1200_UART0_INT = AU1200_FIRST_INT, |
| 838 | #define AU1200_DDMA_INT 3 | 856 | AU1200_SWT_INT, |
| 839 | #define AU1200_MAE_BE_INT 4 | 857 | AU1200_SD_INT, |
| 840 | #define AU1200_GPIO_200 5 | 858 | AU1200_DDMA_INT, |
| 841 | #define AU1200_GPIO_201 6 | 859 | AU1200_MAE_BE_INT, |
| 842 | #define AU1200_GPIO_202 7 | 860 | AU1200_GPIO_200, |
| 843 | #define AU1200_UART1_INT 8 | 861 | AU1200_GPIO_201, |
| 844 | #define AU1200_MAE_FE_INT 9 | 862 | AU1200_GPIO_202, |
| 845 | #define AU1200_PSC0_INT 10 | 863 | AU1200_UART1_INT, |
| 846 | #define AU1200_PSC1_INT 11 | 864 | AU1200_MAE_FE_INT, |
| 847 | #define AU1200_AES_INT 12 | 865 | AU1200_PSC0_INT, |
| 848 | #define AU1200_CAMERA_INT 13 | 866 | AU1200_PSC1_INT, |
| 849 | #define AU1000_TOY_INT 14 | 867 | AU1200_AES_INT, |
| 850 | #define AU1000_TOY_MATCH0_INT 15 | 868 | AU1200_CAMERA_INT, |
| 851 | #define AU1000_TOY_MATCH1_INT 16 | 869 | AU1000_TOY_INT, |
| 852 | #define AU1000_TOY_MATCH2_INT 17 | 870 | AU1000_TOY_MATCH0_INT, |
| 853 | #define AU1000_RTC_INT 18 | 871 | AU1000_TOY_MATCH1_INT, |
| 854 | #define AU1000_RTC_MATCH0_INT 19 | 872 | AU1000_TOY_MATCH2_INT, |
| 855 | #define AU1000_RTC_MATCH1_INT 20 | 873 | AU1000_RTC_INT, |
| 856 | #define AU1000_RTC_MATCH2_INT 21 | 874 | AU1000_RTC_MATCH0_INT, |
| 857 | #define AU1200_NAND_INT 23 | 875 | AU1000_RTC_MATCH1_INT, |
| 858 | #define AU1200_GPIO_204 24 | 876 | AU1000_RTC_MATCH2_INT, |
| 859 | #define AU1200_GPIO_205 25 | 877 | |
| 860 | #define AU1200_GPIO_206 26 | 878 | AU1200_NAND_INT = AU1200_FIRST_INT + 23, |
| 861 | #define AU1200_GPIO_207 27 | 879 | AU1200_GPIO_204, |
| 862 | #define AU1200_GPIO_208_215 28 // Logical OR of 208:215 | 880 | AU1200_GPIO_205, |
| 863 | #define AU1200_USB_INT 29 | 881 | AU1200_GPIO_206, |
| 864 | #define AU1000_USB_HOST_INT AU1200_USB_INT | 882 | AU1200_GPIO_207, |
| 865 | #define AU1200_LCD_INT 30 | 883 | AU1200_GPIO_208_215, /* Logical OR of 208:215 */ |
| 866 | #define AU1200_MAE_BOTH_INT 31 | 884 | AU1200_USB_INT, |
| 867 | #define AU1000_GPIO_0 32 | 885 | AU1000_USB_HOST_INT = AU1200_USB_INT, |
| 868 | #define AU1000_GPIO_1 33 | 886 | AU1200_LCD_INT, |
| 869 | #define AU1000_GPIO_2 34 | 887 | AU1200_MAE_BOTH_INT, |
| 870 | #define AU1000_GPIO_3 35 | 888 | AU1000_GPIO_0, |
| 871 | #define AU1000_GPIO_4 36 | 889 | AU1000_GPIO_1, |
| 872 | #define AU1000_GPIO_5 37 | 890 | AU1000_GPIO_2, |
| 873 | #define AU1000_GPIO_6 38 | 891 | AU1000_GPIO_3, |
| 874 | #define AU1000_GPIO_7 39 | 892 | AU1000_GPIO_4, |
| 875 | #define AU1000_GPIO_8 40 | 893 | AU1000_GPIO_5, |
| 876 | #define AU1000_GPIO_9 41 | 894 | AU1000_GPIO_6, |
| 877 | #define AU1000_GPIO_10 42 | 895 | AU1000_GPIO_7, |
| 878 | #define AU1000_GPIO_11 43 | 896 | AU1000_GPIO_8, |
| 879 | #define AU1000_GPIO_12 44 | 897 | AU1000_GPIO_9, |
| 880 | #define AU1000_GPIO_13 45 | 898 | AU1000_GPIO_10, |
| 881 | #define AU1000_GPIO_14 46 | 899 | AU1000_GPIO_11, |
| 882 | #define AU1000_GPIO_15 47 | 900 | AU1000_GPIO_12, |
| 883 | #define AU1000_GPIO_16 48 | 901 | AU1000_GPIO_13, |
| 884 | #define AU1000_GPIO_17 49 | 902 | AU1000_GPIO_14, |
| 885 | #define AU1000_GPIO_18 50 | 903 | AU1000_GPIO_15, |
| 886 | #define AU1000_GPIO_19 51 | 904 | AU1000_GPIO_16, |
| 887 | #define AU1000_GPIO_20 52 | 905 | AU1000_GPIO_17, |
| 888 | #define AU1000_GPIO_21 53 | 906 | AU1000_GPIO_18, |
| 889 | #define AU1000_GPIO_22 54 | 907 | AU1000_GPIO_19, |
| 890 | #define AU1000_GPIO_23 55 | 908 | AU1000_GPIO_20, |
| 891 | #define AU1000_GPIO_24 56 | 909 | AU1000_GPIO_21, |
| 892 | #define AU1000_GPIO_25 57 | 910 | AU1000_GPIO_22, |
| 893 | #define AU1000_GPIO_26 58 | 911 | AU1000_GPIO_23, |
| 894 | #define AU1000_GPIO_27 59 | 912 | AU1000_GPIO_24, |
| 895 | #define AU1000_GPIO_28 60 | 913 | AU1000_GPIO_25, |
| 896 | #define AU1000_GPIO_29 61 | 914 | AU1000_GPIO_26, |
| 897 | #define AU1000_GPIO_30 62 | 915 | AU1000_GPIO_27, |
| 898 | #define AU1000_GPIO_31 63 | 916 | AU1000_GPIO_28, |
| 917 | AU1000_GPIO_29, | ||
| 918 | AU1000_GPIO_30, | ||
| 919 | AU1000_GPIO_31, | ||
| 920 | }; | ||
| 899 | 921 | ||
| 900 | #define UART0_ADDR 0xB1100000 | 922 | #define UART0_ADDR 0xB1100000 |
| 901 | #define UART1_ADDR 0xB1200000 | 923 | #define UART1_ADDR 0xB1200000 |
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h index 647fdb54cc1d..050eae87ff01 100644 --- a/include/asm-mips/mach-db1x00/db1200.h +++ b/include/asm-mips/mach-db1x00/db1200.h | |||
| @@ -181,29 +181,34 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; | |||
| 181 | #define NAND_PHYS_ADDR 0x20000000 | 181 | #define NAND_PHYS_ADDR 0x20000000 |
| 182 | 182 | ||
| 183 | /* | 183 | /* |
| 184 | * External Interrupts for Pb1200 as of 8/6/2004. | 184 | * External Interrupts for Pb1200 as of 8/6/2004. |
| 185 | * Bit positions in the CPLD registers can be calculated by taking | 185 | * Bit positions in the CPLD registers can be calculated by taking |
| 186 | * the interrupt define and subtracting the DB1200_INT_BEGIN value. | 186 | * the interrupt define and subtracting the DB1200_INT_BEGIN value. |
| 187 | * *example: IDE bis pos is = 64 - 64 | 187 | * |
| 188 | ETH bit pos is = 65 - 64 | 188 | * Example: IDE bis pos is = 64 - 64 |
| 189 | * ETH bit pos is = 65 - 64 | ||
| 189 | */ | 190 | */ |
| 190 | #define DB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1) | 191 | enum external_pb1200_ints { |
| 191 | #define DB1200_IDE_INT (DB1200_INT_BEGIN + 0) | 192 | DB1200_INT_BEGIN = AU1000_MAX_INTR + 1, |
| 192 | #define DB1200_ETH_INT (DB1200_INT_BEGIN + 1) | 193 | |
| 193 | #define DB1200_PC0_INT (DB1200_INT_BEGIN + 2) | 194 | DB1200_IDE_INT = DB1200_INT_BEGIN, |
| 194 | #define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3) | 195 | DB1200_ETH_INT, |
| 195 | #define DB1200_PC1_INT (DB1200_INT_BEGIN + 4) | 196 | DB1200_PC0_INT, |
| 196 | #define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5) | 197 | DB1200_PC0_STSCHG_INT, |
| 197 | #define DB1200_DC_INT (DB1200_INT_BEGIN + 6) | 198 | DB1200_PC1_INT, |
| 198 | #define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7) | 199 | DB1200_PC1_STSCHG_INT, |
| 199 | #define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8) | 200 | DB1200_DC_INT, |
| 200 | #define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9) | 201 | DB1200_FLASHBUSY_INT, |
| 201 | #define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10) | 202 | DB1200_PC0_INSERT_INT, |
| 202 | #define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11) | 203 | DB1200_PC0_EJECT_INT, |
| 203 | #define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12) | 204 | DB1200_PC1_INSERT_INT, |
| 204 | #define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13) | 205 | DB1200_PC1_EJECT_INT, |
| 205 | 206 | DB1200_SD0_INSERT_INT, | |
| 206 | #define DB1200_INT_END (DB1200_INT_BEGIN + 15) | 207 | DB1200_SD0_EJECT_INT, |
| 208 | |||
| 209 | DB1200_INT_END = DB1200_INT_BEGIN + 15, | ||
| 210 | }; | ||
| 211 | |||
| 207 | 212 | ||
| 208 | /* For drivers/pcmcia/au1000_db1x00.c */ | 213 | /* For drivers/pcmcia/au1000_db1x00.c */ |
| 209 | 214 | ||
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h index 409d443322c1..d9f384acfea9 100644 --- a/include/asm-mips/mach-pb1x00/pb1200.h +++ b/include/asm-mips/mach-pb1x00/pb1200.h | |||
| @@ -217,31 +217,35 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; | |||
| 217 | 217 | ||
| 218 | 218 | ||
| 219 | /* | 219 | /* |
| 220 | * External Interrupts for Pb1200 as of 8/6/2004. | 220 | * External Interrupts for Pb1200 as of 8/6/2004. |
| 221 | * Bit positions in the CPLD registers can be calculated by taking | 221 | * Bit positions in the CPLD registers can be calculated by taking |
| 222 | * the interrupt define and subtracting the PB1200_INT_BEGIN value. | 222 | * the interrupt define and subtracting the PB1200_INT_BEGIN value. |
| 223 | * *example: IDE bis pos is = 64 - 64 | 223 | * |
| 224 | ETH bit pos is = 65 - 64 | 224 | * Example: IDE bis pos is = 64 - 64 |
| 225 | * ETH bit pos is = 65 - 64 | ||
| 225 | */ | 226 | */ |
| 226 | #define PB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1) | 227 | enum external_pb1200_ints { |
| 227 | #define PB1200_IDE_INT (PB1200_INT_BEGIN + 0) | 228 | PB1200_INT_BEGIN = AU1000_MAX_INTR + 1, |
| 228 | #define PB1200_ETH_INT (PB1200_INT_BEGIN + 1) | 229 | |
| 229 | #define PB1200_PC0_INT (PB1200_INT_BEGIN + 2) | 230 | PB1200_IDE_INT = PB1200_INT_BEGIN, |
| 230 | #define PB1200_PC0_STSCHG_INT (PB1200_INT_BEGIN + 3) | 231 | PB1200_ETH_INT, |
| 231 | #define PB1200_PC1_INT (PB1200_INT_BEGIN + 4) | 232 | PB1200_PC0_INT, |
| 232 | #define PB1200_PC1_STSCHG_INT (PB1200_INT_BEGIN + 5) | 233 | PB1200_PC0_STSCHG_INT, |
| 233 | #define PB1200_DC_INT (PB1200_INT_BEGIN + 6) | 234 | PB1200_PC1_INT, |
| 234 | #define PB1200_FLASHBUSY_INT (PB1200_INT_BEGIN + 7) | 235 | PB1200_PC1_STSCHG_INT, |
| 235 | #define PB1200_PC0_INSERT_INT (PB1200_INT_BEGIN + 8) | 236 | PB1200_DC_INT, |
| 236 | #define PB1200_PC0_EJECT_INT (PB1200_INT_BEGIN + 9) | 237 | PB1200_FLASHBUSY_INT, |
| 237 | #define PB1200_PC1_INSERT_INT (PB1200_INT_BEGIN + 10) | 238 | PB1200_PC0_INSERT_INT, |
| 238 | #define PB1200_PC1_EJECT_INT (PB1200_INT_BEGIN + 11) | 239 | PB1200_PC0_EJECT_INT, |
| 239 | #define PB1200_SD0_INSERT_INT (PB1200_INT_BEGIN + 12) | 240 | PB1200_PC1_INSERT_INT, |
| 240 | #define PB1200_SD0_EJECT_INT (PB1200_INT_BEGIN + 13) | 241 | PB1200_PC1_EJECT_INT, |
| 241 | #define PB1200_SD1_INSERT_INT (PB1200_INT_BEGIN + 14) | 242 | PB1200_SD0_INSERT_INT, |
| 242 | #define PB1200_SD1_EJECT_INT (PB1200_INT_BEGIN + 15) | 243 | PB1200_SD0_EJECT_INT, |
| 243 | 244 | PB1200_SD1_INSERT_INT, | |
| 244 | #define PB1200_INT_END (PB1200_INT_BEGIN + 15) | 245 | PB1200_SD1_EJECT_INT, |
| 246 | |||
| 247 | PB1200_INT_END (PB1200_INT_BEGIN + 15) | ||
| 248 | }; | ||
| 245 | 249 | ||
| 246 | /* For drivers/pcmcia/au1000_db1x00.c */ | 250 | /* For drivers/pcmcia/au1000_db1x00.c */ |
| 247 | #define BOARD_PC0_INT PB1200_PC0_INT | 251 | #define BOARD_PC0_INT PB1200_PC0_INT |
