diff options
| -rw-r--r-- | arch/arm/mach-at91/pm.c | 6 | ||||
| -rw-r--r-- | arch/arm/mach-at91/pm.h | 4 |
2 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 615668986480..87a31baf1cb3 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c | |||
| @@ -258,16 +258,18 @@ static int at91_pm_enter(suspend_state_t state) | |||
| 258 | * NOTE: the Wait-for-Interrupt instruction needs to be | 258 | * NOTE: the Wait-for-Interrupt instruction needs to be |
| 259 | * in icache so no SDRAM accesses are needed until the | 259 | * in icache so no SDRAM accesses are needed until the |
| 260 | * wakeup IRQ occurs and self-refresh is terminated. | 260 | * wakeup IRQ occurs and self-refresh is terminated. |
| 261 | * For ARM 926 based chips, this requirement is weaker | ||
| 262 | * as at91sam9 can access a RAM in self-refresh mode. | ||
| 261 | */ | 263 | */ |
| 262 | asm("b 1f; .align 5; 1:"); | 264 | asm("b 1f; .align 5; 1:"); |
| 263 | asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ | 265 | asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ |
| 264 | saved_lpr = sdram_selfrefresh_enable(); | 266 | saved_lpr = sdram_selfrefresh_enable(); |
| 265 | asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ | 267 | wait_for_interrupt_enable(); |
| 266 | sdram_selfrefresh_disable(saved_lpr); | 268 | sdram_selfrefresh_disable(saved_lpr); |
| 267 | break; | 269 | break; |
| 268 | 270 | ||
| 269 | case PM_SUSPEND_ON: | 271 | case PM_SUSPEND_ON: |
| 270 | asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ | 272 | cpu_do_idle(); |
| 271 | break; | 273 | break; |
| 272 | 274 | ||
| 273 | default: | 275 | default: |
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 8c87d0c1b8f8..2c4424bfa6c4 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h | |||
| @@ -21,6 +21,7 @@ static inline u32 sdram_selfrefresh_enable(void) | |||
| 21 | } | 21 | } |
| 22 | 22 | ||
| 23 | #define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) | 23 | #define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr) |
| 24 | #define wait_for_interrupt_enable() asm("mcr p15, 0, r0, c7, c0, 4") | ||
| 24 | 25 | ||
| 25 | #elif defined(CONFIG_ARCH_AT91CAP9) | 26 | #elif defined(CONFIG_ARCH_AT91CAP9) |
| 26 | #include <mach/at91cap9_ddrsdr.h> | 27 | #include <mach/at91cap9_ddrsdr.h> |
| @@ -38,6 +39,7 @@ static inline u32 sdram_selfrefresh_enable(void) | |||
| 38 | } | 39 | } |
| 39 | 40 | ||
| 40 | #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) | 41 | #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) |
| 42 | #define wait_for_interrupt_enable() cpu_do_idle() | ||
| 41 | 43 | ||
| 42 | #elif defined(CONFIG_ARCH_AT91SAM9G45) | 44 | #elif defined(CONFIG_ARCH_AT91SAM9G45) |
| 43 | #include <mach/at91sam9_ddrsdr.h> | 45 | #include <mach/at91sam9_ddrsdr.h> |
| @@ -74,6 +76,7 @@ static inline u32 sdram_selfrefresh_enable(void) | |||
| 74 | at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \ | 76 | at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \ |
| 75 | at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \ | 77 | at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \ |
| 76 | } while (0) | 78 | } while (0) |
| 79 | #define wait_for_interrupt_enable() cpu_do_idle() | ||
| 77 | 80 | ||
| 78 | #else | 81 | #else |
| 79 | #include <mach/at91sam9_sdramc.h> | 82 | #include <mach/at91sam9_sdramc.h> |
| @@ -98,5 +101,6 @@ static inline u32 sdram_selfrefresh_enable(void) | |||
| 98 | } | 101 | } |
| 99 | 102 | ||
| 100 | #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr) | 103 | #define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr) |
| 104 | #define wait_for_interrupt_enable() cpu_do_idle() | ||
| 101 | 105 | ||
| 102 | #endif | 106 | #endif |
