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-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8560ads.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts4
7 files changed, 14 insertions, 14 deletions
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 9dc292962a9a..8d1bf0fd9268 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -71,14 +71,14 @@
71 }; 71 };
72 72
73 memory-controller@2000 { 73 memory-controller@2000 {
74 compatible = "fsl,8540-memory-controller"; 74 compatible = "fsl,mpc8540-memory-controller";
75 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>; 77 interrupts = <18 2>;
78 }; 78 };
79 79
80 L2: l2-cache-controller@20000 { 80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8540-l2-cache-controller"; 81 compatible = "fsl,mpc8540-l2-cache-controller";
82 reg = <0x20000 0x1000>; 82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes 83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K 84 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 9a3ad311aedf..87ff96549fac 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -71,14 +71,14 @@
71 }; 71 };
72 72
73 memory-controller@2000 { 73 memory-controller@2000 {
74 compatible = "fsl,8541-memory-controller"; 74 compatible = "fsl,mpc8541-memory-controller";
75 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>; 77 interrupts = <18 2>;
78 }; 78 };
79 79
80 L2: l2-cache-controller@20000 { 80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8541-l2-cache-controller"; 81 compatible = "fsl,mpc8541-l2-cache-controller";
82 reg = <0x20000 0x1000>; 82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes 83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K 84 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 98e94b465662..d793968743c9 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -73,14 +73,14 @@
73 }; 73 };
74 74
75 memory-controller@2000 { 75 memory-controller@2000 {
76 compatible = "fsl,8544-memory-controller"; 76 compatible = "fsl,mpc8544-memory-controller";
77 reg = <0x2000 0x1000>; 77 reg = <0x2000 0x1000>;
78 interrupt-parent = <&mpic>; 78 interrupt-parent = <&mpic>;
79 interrupts = <18 2>; 79 interrupts = <18 2>;
80 }; 80 };
81 81
82 L2: l2-cache-controller@20000 { 82 L2: l2-cache-controller@20000 {
83 compatible = "fsl,8544-l2-cache-controller"; 83 compatible = "fsl,mpc8544-l2-cache-controller";
84 reg = <0x20000 0x1000>; 84 reg = <0x20000 0x1000>;
85 cache-line-size = <32>; // 32 bytes 85 cache-line-size = <32>; // 32 bytes
86 cache-size = <0x40000>; // L2, 256K 86 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 0f5262452682..a17a5572fb73 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -74,14 +74,14 @@
74 }; 74 };
75 75
76 memory-controller@2000 { 76 memory-controller@2000 {
77 compatible = "fsl,8548-memory-controller"; 77 compatible = "fsl,mpc8548-memory-controller";
78 reg = <0x2000 0x1000>; 78 reg = <0x2000 0x1000>;
79 interrupt-parent = <&mpic>; 79 interrupt-parent = <&mpic>;
80 interrupts = <18 2>; 80 interrupts = <18 2>;
81 }; 81 };
82 82
83 L2: l2-cache-controller@20000 { 83 L2: l2-cache-controller@20000 {
84 compatible = "fsl,8548-l2-cache-controller"; 84 compatible = "fsl,mpc8548-l2-cache-controller";
85 reg = <0x20000 0x1000>; 85 reg = <0x20000 0x1000>;
86 cache-line-size = <32>; // 32 bytes 86 cache-line-size = <32>; // 32 bytes
87 cache-size = <0x80000>; // L2, 512K 87 cache-size = <0x80000>; // L2, 512K
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 065b2f093de2..5c5614f9eb17 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -71,14 +71,14 @@
71 }; 71 };
72 72
73 memory-controller@2000 { 73 memory-controller@2000 {
74 compatible = "fsl,8555-memory-controller"; 74 compatible = "fsl,mpc8555-memory-controller";
75 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>; 77 interrupts = <18 2>;
78 }; 78 };
79 79
80 L2: l2-cache-controller@20000 { 80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8555-l2-cache-controller"; 81 compatible = "fsl,mpc8555-l2-cache-controller";
82 reg = <0x20000 0x1000>; 82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes 83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K 84 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
index a5bb1ec70a5a..6e85e1ba0851 100644
--- a/arch/powerpc/boot/dts/mpc8560ads.dts
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -71,14 +71,14 @@
71 }; 71 };
72 72
73 memory-controller@2000 { 73 memory-controller@2000 {
74 compatible = "fsl,8540-memory-controller"; 74 compatible = "fsl,mpc8540-memory-controller";
75 reg = <0x2000 0x1000>; 75 reg = <0x2000 0x1000>;
76 interrupt-parent = <&mpic>; 76 interrupt-parent = <&mpic>;
77 interrupts = <18 2>; 77 interrupts = <18 2>;
78 }; 78 };
79 79
80 L2: l2-cache-controller@20000 { 80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,8540-l2-cache-controller"; 81 compatible = "fsl,mpc8540-l2-cache-controller";
82 reg = <0x20000 0x1000>; 82 reg = <0x20000 0x1000>;
83 cache-line-size = <32>; // 32 bytes 83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x40000>; // L2, 256K 84 cache-size = <0x40000>; // L2, 256K
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 92fb17876e7d..30cf0e098bb9 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -124,14 +124,14 @@
124 }; 124 };
125 125
126 memory-controller@2000 { 126 memory-controller@2000 {
127 compatible = "fsl,8568-memory-controller"; 127 compatible = "fsl,mpc8568-memory-controller";
128 reg = <0x2000 0x1000>; 128 reg = <0x2000 0x1000>;
129 interrupt-parent = <&mpic>; 129 interrupt-parent = <&mpic>;
130 interrupts = <18 2>; 130 interrupts = <18 2>;
131 }; 131 };
132 132
133 L2: l2-cache-controller@20000 { 133 L2: l2-cache-controller@20000 {
134 compatible = "fsl,8568-l2-cache-controller"; 134 compatible = "fsl,mpc8568-l2-cache-controller";
135 reg = <0x20000 0x1000>; 135 reg = <0x20000 0x1000>;
136 cache-line-size = <32>; // 32 bytes 136 cache-line-size = <32>; // 32 bytes
137 cache-size = <0x80000>; // L2, 512K 137 cache-size = <0x80000>; // L2, 512K
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-09 21:10:25 -0500